From: Andrew Rybchenko <arybchenko@solarflare.com>
Date: Thu, 24 Sep 2020 12:12:09 +0000 (+0100)
Subject: common/sfc_efx/base: fix Tx descriptor DMA sync on Riverhead
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=82192e2233649c6edf4b70b888faedd76d097a0f;p=dpdk.git

common/sfc_efx/base: fix Tx descriptor DMA sync on Riverhead

Rx/Tx queue DMA sync should not assume descriptor size to be the same
for all NIC familties since it Tx descritor size is 16 on Riverhead.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
---

diff --git a/drivers/common/sfc_efx/base/ef10_rx.c b/drivers/common/sfc_efx/base/ef10_rx.c
index 61e0dab5b9..2f0d2d2f5b 100644
--- a/drivers/common/sfc_efx/base/ef10_rx.c
+++ b/drivers/common/sfc_efx/base/ef10_rx.c
@@ -693,7 +693,7 @@ ef10_rx_qpush(
 
 	/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
 	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
-	    wptr, pushed & erp->er_mask);
+	    EF10_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);
 	EFSYS_PIO_WRITE_BARRIER();
 	EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
 	    erp->er_index, &dword, B_FALSE);
diff --git a/drivers/common/sfc_efx/base/ef10_tx.c b/drivers/common/sfc_efx/base/ef10_tx.c
index 61c7e49fe8..7cc9324b4b 100644
--- a/drivers/common/sfc_efx/base/ef10_tx.c
+++ b/drivers/common/sfc_efx/base/ef10_tx.c
@@ -375,7 +375,7 @@ ef10_tx_qpush(
 
 		/* Ensure ordering of memory (descriptors) and PIO (doorbell) */
 		EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
-					    wptr, id);
+		    EF10_TXQ_DESC_SIZE, wptr, id);
 		EFSYS_PIO_WRITE_BARRIER();
 		EFX_BAR_VI_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
 		    etp->et_index, &oword);
@@ -391,7 +391,7 @@ ef10_tx_qpush(
 
 		/* Ensure ordering of memory (descriptors) and PIO (doorbell) */
 		EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
-					    wptr, id);
+		    EF10_TXQ_DESC_SIZE, wptr, id);
 		EFSYS_PIO_WRITE_BARRIER();
 		EFX_BAR_VI_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
 		    etp->et_index, &dword, B_FALSE);
diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h
index d7e11c6323..52f974073f 100644
--- a/drivers/common/sfc_efx/base/efx_impl.h
+++ b/drivers/common/sfc_efx/base/efx_impl.h
@@ -1292,15 +1292,16 @@ struct efx_txq_s {
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
-#define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)	\
+#define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size,	\
+				      _wptr, _owptr)			\
 	do {								\
 		unsigned int _new = (_wptr);				\
 		unsigned int _old = (_owptr);				\
 									\
 		if ((_new) >= (_old))					\
 			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
-			    (_old) * sizeof (efx_desc_t),		\
-			    ((_new) - (_old)) * sizeof (efx_desc_t));	\
+			    (_old) * (_desc_size),			\
+			    ((_new) - (_old)) * (_desc_size));		\
 		else							\
 			/*						\
 			 * It is cheaper to sync entire map than sync	\
@@ -1309,7 +1310,7 @@ struct efx_txq_s {
 			 */						\
 			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
 			    0,						\
-			    (_entries) * sizeof (efx_desc_t));		\
+			    (_entries) * (_desc_size));			\
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
diff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c
index 5f17bf3afe..14eda45f4a 100644
--- a/drivers/common/sfc_efx/base/efx_rx.c
+++ b/drivers/common/sfc_efx/base/efx_rx.c
@@ -1581,7 +1581,7 @@ siena_rx_qpush(
 
 	/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
 	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
-	    wptr, pushed & erp->er_mask);
+	    SIENA_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);
 	EFSYS_PIO_WRITE_BARRIER();
 	EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
 			    erp->er_index, &dword, B_FALSE);
diff --git a/drivers/common/sfc_efx/base/efx_tx.c b/drivers/common/sfc_efx/base/efx_tx.c
index d7f31fd46d..d9568bf4a6 100644
--- a/drivers/common/sfc_efx/base/efx_tx.c
+++ b/drivers/common/sfc_efx/base/efx_tx.c
@@ -866,7 +866,7 @@ siena_tx_qpush(
 
 	/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
 	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
-	    wptr, pushed & etp->et_mask);
+	    SIENA_TXQ_DESC_SIZE, wptr, pushed & etp->et_mask);
 	EFSYS_PIO_WRITE_BARRIER();
 	EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,
 			    etp->et_index, &dword, B_FALSE);