From: Hongbo Zheng Date: Tue, 23 Mar 2021 11:21:03 +0000 (+0800) Subject: net/hns3: delete redundant xstats RAS statistics X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=9072cbd7c36262d34fb71aa46add998586575195;p=dpdk.git net/hns3: delete redundant xstats RAS statistics The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics. Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3949153502..139e893ac6 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5768,14 +5768,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { hns3_warn(hw, "Detected IMP RD poison!"); - hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { hns3_warn(hw, "Detected IMP CMDQ error!"); - hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 0fc0a1c422..314916c952 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -561,38 +561,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_int_cnt; - uint64_t ppu_mpf_abn_int_st2_msix_cnt; - uint64_t ssu_port_based_pf_int_cnt; - uint64_t ppp_pf_abnormal_int_cnt; - uint64_t ppu_pf_abnormal_int_msix_cnt; - - uint64_t imp_tcm_ecc_int_cnt; - uint64_t cmdq_mem_ecc_int_cnt; - uint64_t imp_rd_poison_int_cnt; - uint64_t tqp_int_ecc_int_cnt; - uint64_t msix_ecc_int_cnt; - uint64_t ssu_ecc_multi_bit_int_0_cnt; - uint64_t ssu_ecc_multi_bit_int_1_cnt; - uint64_t ssu_common_ecc_int_cnt; - uint64_t igu_int_cnt; - uint64_t ppp_mpf_abnormal_int_st1_cnt; - uint64_t ppp_mpf_abnormal_int_st3_cnt; - uint64_t ppu_mpf_abnormal_int_st1_cnt; - uint64_t ppu_mpf_abn_int_st2_ras_cnt; - uint64_t ppu_mpf_abnormal_int_st3_cnt; - uint64_t tm_sch_int_cnt; - uint64_t qcn_fifo_int_cnt; - uint64_t qcn_ecc_int_cnt; - uint64_t ncsi_ecc_int_cnt; - uint64_t ssu_port_based_err_int_cnt; - uint64_t ssu_fifo_overflow_int_cnt; - uint64_t ssu_ets_tcg_int_cnt; - uint64_t igu_egu_tnl_int_cnt; - uint64_t ppu_pf_abnormal_int_ras_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -738,9 +706,6 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 265dae8b53..c259f2e4a5 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } - hns3_error_int_stats_add(hns, reg); } err++; } diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 941c75f063..7cda36c796 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -201,65 +201,6 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = { HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)} }; -static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = { - {"MAC_AFIFO_TNL_INT_R", - HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)}, - {"SSU_PORT_BASED_ERR_INT_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)}, - {"PPP_PF_ABNORMAL_INT_ST0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)}, - {"IMP_TCM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)}, - {"CMDQ_MEM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)}, - {"IMP_RD_POISON_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)}, - {"TQP_INT_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)}, - {"MSIX_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)}, - {"SSU_COMMON_ERR_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)}, - {"IGU_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)}, - {"TM_SCH_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)}, - {"QCN_FIFO_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)}, - {"QCN_ECC_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)}, - {"NCSI_ECC_INT_RPT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)}, - {"SSU_PORT_BASED_ERR_INT_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)}, - {"SSU_FIFO_OVERFLOW_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)}, - {"SSU_ETS_TCG_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)}, - {"IGU_EGU_TNL_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)}, -}; - /* The statistic of reset */ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = { {"REQ_RESET_CNT", @@ -333,9 +274,6 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) -#define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \ - sizeof(hns3_error_int_stats_strings[0])) - #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \ sizeof(hns3_reset_stats_strings[0])) @@ -363,7 +301,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -750,23 +688,6 @@ hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } -void -hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) -{ - struct hns3_pf *pf = &hns->pf; - uint16_t i; - char *addr; - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - *(uint64_t *)addr += 1; - break; - } - } -} - static void hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) @@ -932,7 +853,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; struct hns3_hw *hw = &hns->hw; struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; @@ -986,13 +906,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } } /* Get the reset stat */ @@ -1134,13 +1047,6 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_imissed_stats_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_error_int_stats_strings[i].name); - count++; - } } for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, @@ -1358,7 +1264,6 @@ int hns3_dev_xstats_reset(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; int ret; /* Clear tqp stats */ @@ -1379,9 +1284,6 @@ hns3_dev_xstats_reset(struct rte_eth_dev *dev) if (ret) return ret; - /* Clear error stats */ - memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats)); - return 0; } diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 70a9c5bcd5..8ea69b4a93 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint32_t size); int hns3_stats_reset(struct rte_eth_dev *dev); -void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err); int hns3_tqp_stats_init(struct hns3_hw *hw); void hns3_tqp_stats_uninit(struct hns3_hw *hw); int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear);