From: Phil Yang <phil.yang@arm.com>
Date: Thu, 5 Sep 2019 10:55:07 +0000 (+0800)
Subject: net/mlx5: fix Rx CQ doorbell synchronization on aarch64
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=94a24aaf6c5bd0a03c2828e7411d30a4fc0ac075;p=dpdk.git

net/mlx5: fix Rx CQ doorbell synchronization on aarch64

The Rx completion queue doorbell field needs to be updated after
the last CQE decompressed. For the weaker memory model processors,
the compiler barrier is not sufficient to guarantee the order of
these operations, so use the coherent I/O memory barrier to make
sure these fields are updated in order.

Fixes: 570acdb1da8a ("net/mlx5: add vectorized Rx/Tx burst for ARM")
Cc: stable@dpdk.org

Suggested-by: Gavin Hu <gavin.hu@arm.com>
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index 99302869a7..e914d017d6 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -727,7 +727,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
 			rxq->decompressed -= n;
 		}
 	}
-	rte_compiler_barrier();
+	rte_cio_wmb();
 	*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
 	return rcvd_pkt;
 }