From: Beilei Xing Date: Mon, 8 Jan 2018 03:09:13 +0000 (+0800) Subject: net/i40e: support input set configuration X-Git-Tag: spdx-start~329 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=97bd4ef9a0fecfc660231d9547f94a8df616e8df;p=dpdk.git net/i40e: support input set configuration This patch supports getting/setting input set info for RSS, FDIR, and FDIR flexible payload. It also adds some helper functions for input set configuration. Signed-off-by: Beilei Xing Acked-by: Qi Zhang --- diff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c index 947f13b868..55ae2fefbf 100644 --- a/drivers/net/i40e/rte_pmd_i40e.c +++ b/drivers/net/i40e/rte_pmd_i40e.c @@ -2956,3 +2956,144 @@ int rte_pmd_i40e_flow_add_del_packet_template( return i40e_flow_add_del_fdir_filter(dev, &filter_conf, add); } + +int +rte_pmd_i40e_inset_get(uint16_t port, uint8_t pctype, + struct rte_pmd_i40e_inset *inset, + enum rte_pmd_i40e_inset_type inset_type) +{ + struct rte_eth_dev *dev; + struct i40e_hw *hw; + uint64_t inset_reg; + uint32_t mask_reg[2]; + int i; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev = &rte_eth_devices[port]; + + if (!is_i40e_supported(dev)) + return -ENOTSUP; + + if (pctype > 63) + return -EINVAL; + + hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + memset(inset, 0, sizeof(struct rte_pmd_i40e_inset)); + + switch (inset_type) { + case INSET_HASH: + /* Get input set */ + inset_reg = + i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype)); + inset_reg <<= I40E_32_BIT_WIDTH; + inset_reg |= + i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype)); + /* Get field mask */ + mask_reg[0] = + i40e_read_rx_ctl(hw, I40E_GLQF_HASH_MSK(0, pctype)); + mask_reg[1] = + i40e_read_rx_ctl(hw, I40E_GLQF_HASH_MSK(1, pctype)); + break; + case INSET_FDIR: + inset_reg = + i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1)); + inset_reg <<= I40E_32_BIT_WIDTH; + inset_reg |= + i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0)); + mask_reg[0] = + i40e_read_rx_ctl(hw, I40E_GLQF_FD_MSK(0, pctype)); + mask_reg[1] = + i40e_read_rx_ctl(hw, I40E_GLQF_FD_MSK(1, pctype)); + break; + case INSET_FDIR_FLX: + inset_reg = + i40e_read_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype)); + mask_reg[0] = + i40e_read_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, 0)); + mask_reg[1] = + i40e_read_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, 1)); + break; + default: + PMD_DRV_LOG(ERR, "Unsupported input set type."); + return -EINVAL; + } + + inset->inset = inset_reg; + + for (i = 0; i < 2; i++) { + inset->mask[i].field_idx = ((mask_reg[i] >> 16) & 0x3F); + inset->mask[i].mask = mask_reg[i] & 0xFFFF; + } + + return 0; +} + +int +rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype, + struct rte_pmd_i40e_inset *inset, + enum rte_pmd_i40e_inset_type inset_type) +{ + struct rte_eth_dev *dev; + struct i40e_hw *hw; + uint64_t inset_reg; + uint32_t mask_reg[2]; + int i; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev = &rte_eth_devices[port]; + + if (!is_i40e_supported(dev)) + return -ENOTSUP; + + if (pctype > 63) + return -EINVAL; + + hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* Clear mask first */ + for (i = 0; i < 2; i++) + i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0); + + inset_reg = inset->inset; + for (i = 0; i < 2; i++) + mask_reg[i] = (inset->mask[i].field_idx << 16) | + inset->mask[i].mask; + + switch (inset_type) { + case INSET_HASH: + i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), + (uint32_t)(inset_reg & UINT32_MAX)); + i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), + (uint32_t)((inset_reg >> + I40E_32_BIT_WIDTH) & UINT32_MAX)); + for (i = 0; i < 2; i++) + i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), + mask_reg[i]); + break; + case INSET_FDIR: + i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), + (uint32_t)(inset_reg & UINT32_MAX)); + i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), + (uint32_t)((inset_reg >> + I40E_32_BIT_WIDTH) & UINT32_MAX)); + for (i = 0; i < 2; i++) + i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), + mask_reg[i]); + break; + case INSET_FDIR_FLX: + i40e_check_write_reg(hw, I40E_PRTQF_FD_FLXINSET(pctype), + (uint32_t)(inset_reg & UINT32_MAX)); + for (i = 0; i < 2; i++) + i40e_check_write_reg(hw, I40E_PRTQF_FD_MSK(pctype, i), + mask_reg[i]); + break; + default: + PMD_DRV_LOG(ERR, "Unsupported input set type."); + return -EINVAL; + } + + I40E_WRITE_FLUSH(hw); + return 0; +} diff --git a/drivers/net/i40e/rte_pmd_i40e.h b/drivers/net/i40e/rte_pmd_i40e.h index 7ca37b1976..1bdb68a28e 100644 --- a/drivers/net/i40e/rte_pmd_i40e.h +++ b/drivers/net/i40e/rte_pmd_i40e.h @@ -289,6 +289,23 @@ struct rte_pmd_i40e_pkt_template_conf { uint32_t soft_id; }; +enum rte_pmd_i40e_inset_type { + INSET_NONE = 0, + INSET_HASH, + INSET_FDIR, + INSET_FDIR_FLX, +}; + +struct rte_pmd_i40e_inset_mask { + uint8_t field_idx; + uint16_t mask; +}; + +struct rte_pmd_i40e_inset { + uint64_t inset; + struct rte_pmd_i40e_inset_mask mask[2]; +}; + /** * Add or remove raw packet template filter to Flow Director. * @@ -905,4 +922,125 @@ int rte_pmd_i40e_query_vfid_by_mac(uint16_t port, int rte_pmd_i40e_rss_queue_region_conf(uint16_t port_id, enum rte_pmd_i40e_queue_region_op op_type, void *arg); +int rte_pmd_i40e_cfg_hash_inset(uint16_t port, + uint64_t pctype, uint64_t inset); + +/** + * Get input set + * + * @param port + * The port identifier of the Ethernet device. + * @param pctype + * HW pctype. + * @param inset + * Buffer for input set info. + * @param inset_type + * Type of input set. + * @return + * - (0) if successful. + * - (-ENODEV) if *port* invalid. + * - (-EINVAL) if bad parameter. + * - (-ENOTSUP) if operation not supported. + */ +int rte_pmd_i40e_inset_get(uint16_t port, uint8_t pctype, + struct rte_pmd_i40e_inset *inset, + enum rte_pmd_i40e_inset_type inset_type); + +/** + * Set input set + * + * @param port + * The port identifier of the Ethernet device. + * @param pctype + * HW pctype. + * @param inset + * Input set info. + * @param inset_type + * Type of input set. + * @return + * - (0) if successful. + * - (-ENODEV) if *port* invalid. + * - (-EINVAL) if bad parameter. + * - (-ENOTSUP) if operation not supported. + */ +int rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype, + struct rte_pmd_i40e_inset *inset, + enum rte_pmd_i40e_inset_type inset_type); + +/** + * Get bit value for some field index + * + * @param inset + * Input set value. + * @param field_idx + * Field index for input set. + * @return + * - (1) if set. + * - (0) if cleared. + */ +static inline int +rte_pmd_i40e_inset_field_get(uint64_t inset, uint8_t field_idx) +{ + uint8_t bit_idx; + + if (field_idx > 63) + return 0; + + bit_idx = 63 - field_idx; + if (inset & (1ULL << bit_idx)) + return 1; + + return 0; +} + +/** + * Set bit value for some field index + * + * @param inset + * Input set value. + * @param field_idx + * Field index for input set. + * @return + * - (-1) if failed. + * - (0) if success. + */ +static inline int +rte_pmd_i40e_inset_field_set(uint64_t *inset, uint8_t field_idx) +{ + uint8_t bit_idx; + + if (field_idx > 63) + return -1; + + bit_idx = 63 - field_idx; + *inset = *inset | (1ULL << bit_idx); + + return 0; +} + +/** + * Clear bit value for some field index + * + * @param inset + * Input set value. + * @param field_idx + * Field index for input set. + * @return + * - (-1) if failed. + * - (0) if success. + */ +static inline int +rte_pmd_i40e_inset_field_clear(uint64_t *inset, uint8_t field_idx) +{ + uint8_t bit_idx; + + if (field_idx > 63) + return -1; + + bit_idx = 63 - field_idx; + *inset = *inset & ~(1ULL << bit_idx); + + return 0; +} + #endif /* _PMD_I40E_H_ */ diff --git a/drivers/net/i40e/rte_pmd_i40e_version.map b/drivers/net/i40e/rte_pmd_i40e_version.map index ebbd24e034..cccd5768c2 100644 --- a/drivers/net/i40e/rte_pmd_i40e_version.map +++ b/drivers/net/i40e/rte_pmd_i40e_version.map @@ -58,3 +58,10 @@ DPDK_17.11 { rte_pmd_i40e_rss_queue_region_conf; } DPDK_17.08; + +DPDK_18.02 { + global: + + rte_pmd_i40e_inset_get; + rte_pmd_i40e_inset_set; +} DPDK_17.11; \ No newline at end of file