From: Shahaf Shuler Date: Wed, 3 May 2017 06:55:35 +0000 (+0300) Subject: net/mlx5: fix Tx max inline with TSO X-Git-Tag: spdx-start~3269 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=993b2455fbbd9f4339211d6faa7b15f8ecf84ec8;p=dpdk.git net/mlx5: fix Tx max inline with TSO When TSO is enabled, Verbs layer aggregates the TSO inline size with the txq inline size for the Tx creation, while the PMD takes the maximum among them. Fixing it by adjusting the max inline parameter before passing to to Verbs. Fixes: 3f13f8c23a7c ("net/mlx5: support hardware TSO") Signed-off-by: Shahaf Shuler Acked-by: Yongseok Koh Acked-by: Nelio Laranjeiro --- diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index f80740a139..de7e28be60 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -230,6 +230,9 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, struct ibv_exp_cq_attr cq_attr; } attr; unsigned int cqe_n; + const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER + + (RTE_CACHE_LINE_SIZE - 1)) / + RTE_CACHE_LINE_SIZE); int ret = 0; if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) { @@ -307,16 +310,23 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, priv->inline_max_packet_sz) + (RTE_CACHE_LINE_SIZE - 1)) / RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE; + } else if (priv->tso) { + int inline_diff = tmpl.txq.max_inline - max_tso_inline; + + /* + * Adjust inline value as Verbs aggregates + * tso_inline and txq_inline fields. + */ + attr.init.cap.max_inline_data = inline_diff > 0 ? + inline_diff * + RTE_CACHE_LINE_SIZE : + 0; } else { attr.init.cap.max_inline_data = tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE; } } if (priv->tso) { - uint16_t max_tso_inline = ((MLX5_MAX_TSO_HEADER + - (RTE_CACHE_LINE_SIZE - 1)) / - RTE_CACHE_LINE_SIZE); - attr.init.max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE; attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER;