From: Konstantin Ananyev <konstantin.ananyev@intel.com>
Date: Tue, 30 Jul 2019 10:19:27 +0000 (+0100)
Subject: examples/bpf: fix build
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=9a710863decb1cdb98efbdd5e11df3ebcfcc37b6;p=dpdk.git

examples/bpf: fix build

Example BPF programs t2.c, t3.c in folder examples/bpf are
failing to compile with latest dpdk.org master.
The reason is changes in some core DPDK header files, that causes
now inclusion of x86 specific headers.
To overcome the issue, minimize inclusion of DPDK header files
into BPF source code.

Bugzilla ID: 321

Fixes: 9dfc06c26a8b ("test/bpf: add samples")
Cc: stable@dpdk.org

Reported-by: Michel Machado <michel@digirati.com.br>
Suggested-by: Michel Machado <michel@digirati.com.br>
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
---

diff --git a/examples/bpf/mbuf.h b/examples/bpf/mbuf.h
index b623d8694f..e41c3d26e9 100644
--- a/examples/bpf/mbuf.h
+++ b/examples/bpf/mbuf.h
@@ -13,7 +13,6 @@
 
 #include <stdint.h>
 #include <rte_common.h>
-#include <rte_memory.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -364,6 +363,23 @@ typedef struct {
 	volatile int16_t cnt; /**< An internal counter value. */
 } rte_atomic16_t;
 
+#define RTE_CACHE_LINE_MIN_SIZE 64      /**< Minimum Cache line size. */
+
+/**
+ * Force minimum cache line alignment.
+ */
+#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
+
+/**
+ * IO virtual address type.
+ * When the physical addressing mode (IOVA as PA) is in use,
+ * the translation from an IO virtual address (IOVA) to a physical address
+ * is a direct mapping, i.e. the same value.
+ * Otherwise, in virtual mode (IOVA as VA), an IOMMU may do the translation.
+ */
+typedef uint64_t rte_iova_t;
+#define RTE_BAD_IOVA ((rte_iova_t)-1)
+
 /**
  * The generic rte_mbuf, containing a packet mbuf.
  */
@@ -377,7 +393,11 @@ struct rte_mbuf {
 	 * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes
 	 * working on vector drivers easier.
 	 */
-	phys_addr_t buf_physaddr __rte_aligned(sizeof(phys_addr_t));
+	RTE_STD_C11
+	union {
+		rte_iova_t buf_iova;
+		rte_iova_t buf_physaddr; /**< deprecated */
+	} __rte_aligned(sizeof(rte_iova_t));
 
 	/* next 8 bytes are initialised on RX descriptor rearm */
 	MARKER64 rearm_data;