From: Olivier Matz Date: Tue, 3 Apr 2018 13:26:44 +0000 (+0200) Subject: ring: relax alignment constraint on ring structure X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=a3d6026711d00183e308f1dd79933f6161840e04;p=dpdk.git ring: relax alignment constraint on ring structure The initial objective of commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting") was to add an empty cache line between the producer and consumer data (on platform with cache line size = 64B), preventing from having them on adjacent cache lines. Following discussion on the mailing list, it appears that this also imposes an alignment constraint that is not required. This patch removes the extra alignment constraint and adds the empty cache lines using padding fields in the structure. The size of rte_ring structure and the offset of the fields remain the same on platforms with cache line size = 64B: rte_ring = 384 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 rte_ring.cons = 256 But it has an impact on platform where cache line size is 128B: rte_ring = 384 -> 768 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 -> 256 rte_ring.cons = 256 -> 512 Suggested-by: Konstantin Ananyev Signed-off-by: Olivier Matz --- diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index fd9def20c2..d9d7e92b23 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -105,9 +105,3 @@ Deprecation Notices required the previous behavior can be configured using existing flow director APIs. There is no ABI/API break. This change will just remove a global configuration setting and require explicit configuration. - -* ring: The alignment constraints on the ring structure will be relaxed - to one cache line instead of two, and an empty cache line padding will - be added between the producer and consumer structures. The size of the - structure and the offset of the fields will remain the same on - platforms with 64B cache line, but will change on other platforms. diff --git a/doc/guides/rel_notes/release_18_05.rst b/doc/guides/rel_notes/release_18_05.rst index bc9cdda6af..149e73bbda 100644 --- a/doc/guides/rel_notes/release_18_05.rst +++ b/doc/guides/rel_notes/release_18_05.rst @@ -194,6 +194,12 @@ ABI Changes Also, make sure to start the actual text at the margin. ========================================================= +* ring: the alignment constraints on the ring structure has been relaxed + to one cache line instead of two, and an empty cache line padding is + added between the producer and consumer structures. The size of the + structure and the offset of the fields remains the same on platforms + with 64B cache line, but change on other platforms. + * **Additional fields in rte_eth_dev_info.** The ``rte_eth_dev_info`` structure has had two extra entries appended to the @@ -202,6 +208,7 @@ ABI Changes type ``uint16_t``: ``burst_size``, ``ring_size``, and ``nb_queues``. These are parameter values recommended for use by the PMD. + Removed Items ------------- @@ -292,7 +299,7 @@ The libraries prepended with a plus sign were incremented in this version. librte_power.so.1 librte_rawdev.so.1 librte_reorder.so.1 - librte_ring.so.1 + + librte_ring.so.2 librte_sched.so.1 librte_security.so.1 librte_table.so.3 diff --git a/lib/librte_ring/Makefile b/lib/librte_ring/Makefile index bde8907d6d..21a36770d4 100644 --- a/lib/librte_ring/Makefile +++ b/lib/librte_ring/Makefile @@ -11,7 +11,7 @@ LDLIBS += -lrte_eal EXPORT_MAP := rte_ring_version.map -LIBABIVER := 1 +LIBABIVER := 2 # all source are stored in SRCS-y SRCS-$(CONFIG_RTE_LIBRTE_RING) := rte_ring.c diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h index 253cdc96ac..d3d3f7f977 100644 --- a/lib/librte_ring/rte_ring.h +++ b/lib/librte_ring/rte_ring.h @@ -62,14 +62,6 @@ enum rte_ring_queue_behavior { struct rte_memzone; /* forward declaration, so as not to require memzone.h */ -#if RTE_CACHE_LINE_SIZE < 128 -#define PROD_ALIGN (RTE_CACHE_LINE_SIZE * 2) -#define CONS_ALIGN (RTE_CACHE_LINE_SIZE * 2) -#else -#define PROD_ALIGN RTE_CACHE_LINE_SIZE -#define CONS_ALIGN RTE_CACHE_LINE_SIZE -#endif - /* structure to hold a pair of head/tail values and other metadata */ struct rte_ring_headtail { volatile uint32_t head; /**< Prod/consumer head. */ @@ -101,11 +93,15 @@ struct rte_ring { uint32_t mask; /**< Mask (size-1) of ring. */ uint32_t capacity; /**< Usable size of ring */ + char pad0 __rte_cache_aligned; /**< empty cache line */ + /** Ring producer status. */ - struct rte_ring_headtail prod __rte_aligned(PROD_ALIGN); + struct rte_ring_headtail prod __rte_cache_aligned; + char pad1 __rte_cache_aligned; /**< empty cache line */ /** Ring consumer status. */ - struct rte_ring_headtail cons __rte_aligned(CONS_ALIGN); + struct rte_ring_headtail cons __rte_cache_aligned; + char pad2 __rte_cache_aligned; /**< empty cache line */ }; #define RING_F_SP_ENQ 0x0001 /**< The default enqueue is "single-producer". */