From: Chas Williams <3chas3@gmail.com> Date: Tue, 11 Oct 2016 23:04:52 +0000 (-0400) Subject: net/bnx2x: get cache line size from build configuration X-Git-Tag: spdx-start~5545 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=a518584d1fcfe377c86f518c917a205b692c838c;p=dpdk.git net/bnx2x: get cache line size from build configuration Correctly hint the cache line size. Remove unused macros associated with the cache line size. Fixes: 540a211084a7 ("bnx2x: driver core") Signed-off-by: Chas Williams <3chas3@gmail.com> Acked-by: Harish Patil --- diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 78757a8d2d..ed7c55fdf1 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -304,10 +304,7 @@ struct bnx2x_device_type { /* TCP with Timestamp Option (32) + IPv6 (40) */ /* max supported alignment is 256 (8 shift) */ -#define BNX2X_RX_ALIGN_SHIFT 8 -/* FW uses 2 cache lines alignment for start packet and size */ -#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT) -#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT) +#define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2)) #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)