From: Fabrice Desclaux Date: Tue, 26 Jun 2012 17:49:13 +0000 (+0200) Subject: first version of mainboard X-Git-Tag: v2~14 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=a8c4d1a6bf76c08fd4263c8832584071a739ba76;p=protos%2Fxbee-elec.git first version of mainboard --- diff --git a/gschem-sym/ATmega168-TQFP-1.sym b/gschem-sym/ATmega168-TQFP-1.sym new file mode 100644 index 0000000..6578062 --- /dev/null +++ b/gschem-sym/ATmega168-TQFP-1.sym @@ -0,0 +1,379 @@ +v 20060113 1 +P 3700 8100 3400 8100 1 0 0 +{ +T 3500 8150 5 8 1 1 0 0 1 +pinnumber=12 +T 3500 8050 5 8 0 1 0 2 1 +pinseq=12 +T 3350 8100 9 8 1 1 0 6 1 +pinlabel=(PCINT0/CLKO/ICP1) PB0 +T 3350 8100 5 8 0 1 0 8 1 +pintype=io +} +P 3700 7700 3400 7700 1 0 0 +{ +T 3500 7750 5 8 1 1 0 0 1 +pinnumber=13 +T 3500 7650 5 8 0 1 0 2 1 +pinseq=13 +T 3350 7700 9 8 1 1 0 6 1 +pinlabel=(PCINT1/OC1A) PB1 +T 3350 7700 5 8 0 1 0 8 1 +pintype=io +} +P 3700 7300 3400 7300 1 0 0 +{ +T 3500 7350 5 8 1 1 0 0 1 +pinnumber=14 +T 3500 7250 5 8 0 1 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0 0 0 0 1 +dist-license=GNU GPL +T 300 6200 5 10 0 0 0 0 1 +use-license=Unlimited diff --git a/gschem-sym/ATmega168_TQFP.sym b/gschem-sym/ATmega168_TQFP.sym new file mode 100644 index 0000000..096302f --- /dev/null +++ b/gschem-sym/ATmega168_TQFP.sym @@ -0,0 +1,476 @@ +v 20110115 2 +T 3000 8900 8 10 1 1 0 6 1 +refdes=U? +T 400 9050 5 10 0 0 0 0 1 +device=ATmega168_TQFP +T 400 9250 5 10 0 0 0 0 1 +footprint=TQFP44 +P 2300 100 2300 300 1 0 0 +{ +T 2350 200 5 8 1 1 0 0 1 +pinnumber=4 +T 2350 200 5 8 0 1 0 2 1 +pinseq=4 +T 2300 450 9 8 1 1 0 3 1 +pinlabel=Reset +T 2300 600 5 8 0 1 0 3 1 +pintype=in +} +L 2108 574 2492 574 3 0 0 0 -1 -1 +V 2300 350 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1700 100 1700 400 1 0 0 +{ +T 1750 200 5 8 1 1 0 0 1 +pinnumber=7 +T 1750 200 5 8 0 1 0 2 1 +pinseq=7 +T 1700 450 9 8 1 1 0 3 1 +pinlabel=XTAL2 +T 1700 600 5 8 0 1 0 3 1 +pintype=out +} +P 1100 100 1100 400 1 0 0 +{ +T 1150 200 5 8 1 1 0 0 1 +pinnumber=8 +T 1150 200 5 8 0 1 0 2 1 +pinseq=8 +T 1100 450 9 8 1 1 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+} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=1 +T 300 6350 5 8 0 1 0 8 1 +pinseq=1 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=PB5 (MOSI) +T 450 6400 5 8 0 1 0 2 1 +pintype=io +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=44 +T 300 6750 5 8 0 1 0 8 1 +pinseq=44 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=PB4 (SS) +T 450 6800 5 8 0 1 0 2 1 +pintype=io +} +L 862 6924 1062 6924 3 0 0 0 -1 -1 +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=43 +T 300 7150 5 8 0 1 0 8 1 +pinseq=43 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=PB3 (AIN1/OC0) +T 450 7200 5 8 0 1 0 2 1 +pintype=io +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=42 +T 300 7550 5 8 0 1 0 8 1 +pinseq=42 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=PB2 (AIN0/INT2) +T 450 7600 5 8 0 1 0 2 1 +pintype=io +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=41 +T 300 7950 5 8 0 1 0 8 1 +pinseq=41 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=PB1 (T1) +T 450 8000 5 8 0 1 0 2 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1 +pintype=io +} +P 3300 6000 3000 6000 1 0 0 +{ +T 3100 6050 5 8 1 1 0 0 1 +pinnumber=31 +T 3100 5950 5 8 0 1 0 2 1 +pinseq=31 +T 2950 6000 9 8 1 1 0 6 1 +pinlabel=(ADC6) PA6 +T 2950 6000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6400 3000 6400 1 0 0 +{ +T 3100 6450 5 8 1 1 0 0 1 +pinnumber=32 +T 3100 6350 5 8 0 1 0 2 1 +pinseq=32 +T 2950 6400 9 8 1 1 0 6 1 +pinlabel=(ADC5) PA5 +T 2950 6400 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6800 3000 6800 1 0 0 +{ +T 3100 6850 5 8 1 1 0 0 1 +pinnumber=33 +T 3100 6750 5 8 0 1 0 2 1 +pinseq=33 +T 2950 6800 9 8 1 1 0 6 1 +pinlabel=(ADC4) PA4 +T 2950 6800 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7200 3000 7200 1 0 0 +{ +T 3100 7250 5 8 1 1 0 0 1 +pinnumber=34 +T 3100 7150 5 8 0 1 0 2 1 +pinseq=34 +T 2950 7200 9 8 1 1 0 6 1 +pinlabel=(ADC3) PA3 +T 2950 7200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7600 3000 7600 1 0 0 +{ +T 3100 7650 5 8 1 1 0 0 1 +pinnumber=35 +T 3100 7550 5 8 0 1 0 2 1 +pinseq=35 +T 2950 7600 9 8 1 1 0 6 1 +pinlabel=(ADC2) PA2 +T 2950 7600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8000 3000 8000 1 0 0 +{ +T 3100 8050 5 8 1 1 0 0 1 +pinnumber=36 +T 3100 7950 5 8 0 1 0 2 1 +pinseq=36 +T 2950 8000 9 8 1 1 0 6 1 +pinlabel=(ADC1) PA1 +T 2950 8000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8400 3000 8400 1 0 0 +{ +T 3100 8450 5 8 1 1 0 0 1 +pinnumber=37 +T 3100 8350 5 8 0 1 0 2 1 +pinseq=37 +T 2950 8400 9 8 1 1 0 6 1 +pinlabel=(ADC0) PA0 +T 2950 8400 5 8 0 1 0 8 1 +pintype=io +} +B 400 400 2600 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 9850 5 10 0 0 0 0 1 +description=8-bit RISC micro controller (Atmel) +T 400 10050 5 10 0 0 0 0 1 +numslots=0 +T 400 10250 5 10 0 0 0 0 1 +author=Matthijs ten Berge +T 400 8850 9 10 1 0 0 0 1 +ATmega16 +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=27 +T 300 1550 5 8 0 1 0 8 1 +pinseq=27 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=AVCC +T 450 1600 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=29 +T 300 1150 5 8 0 1 0 8 1 +pinseq=29 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=AREF +T 450 1200 5 8 0 1 0 2 1 +pintype=io +} +T 0 0 8 10 0 0 0 0 1 +dist-license=GPL +T 1600 0 8 10 0 0 0 0 1 +use-license=unlimited +T 0 200 8 10 0 0 0 0 1 +comment=Suggested library: micro +P 3300 1800 3000 1800 1 0 0 +{ +T 3100 1850 5 8 1 1 0 0 1 +pinnumber=6 +T 3100 1750 5 8 0 1 0 2 1 +pinseq=6 +T 2950 1800 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 1800 5 8 0 1 0 8 1 +pintype=pwr +} +P 3300 1500 3000 1500 1 0 0 +{ +T 3100 1550 5 8 1 1 0 0 1 +pinnumber=18 +T 3100 1450 5 8 0 1 0 2 1 +pinseq=18 +T 2950 1500 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 1500 5 8 0 1 0 8 1 +pintype=pwr +} +P 3300 1200 3000 1200 1 0 0 +{ +T 3100 1250 5 8 1 1 0 0 1 +pinnumber=28 +T 3100 1150 5 8 0 1 0 2 1 +pinseq=28 +T 2950 1200 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 1200 5 8 0 1 0 8 1 +pintype=pwr +} +P 3300 900 3000 900 1 0 0 +{ +T 3100 950 5 8 1 1 0 0 1 +pinnumber=39 +T 3100 850 5 8 0 1 0 2 1 +pinseq=39 +T 2950 900 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 900 5 8 0 1 0 8 1 +pintype=pwr +} diff --git a/gschem-sym/ATmega16_TQFP.sym b/gschem-sym/ATmega16_TQFP.sym new file mode 100644 index 0000000..8c57aa2 --- /dev/null +++ b/gschem-sym/ATmega16_TQFP.sym @@ -0,0 +1,436 @@ +v 20040111 1 +T 3000 8900 8 10 1 1 0 6 1 +refdes=U? +T 400 9050 5 10 0 0 0 0 1 +device=ATmega16_TQFP +T 400 9250 5 10 0 0 0 0 1 +footprint=TQFP44 +T 400 9450 5 10 0 0 0 0 1 +net=GND:6,18,28,39 +T 400 9650 5 10 0 0 0 0 1 +net=Vcc:5,17,38 +P 2300 100 2300 300 1 0 0 +{ +T 2350 200 5 8 1 1 0 0 1 +pinnumber=4 +T 2350 200 5 8 0 1 0 2 1 +pinseq=4 +T 2300 450 9 8 1 1 0 3 1 +pinlabel=Reset +T 2300 600 5 8 0 1 0 3 1 +pintype=in +} +L 2108 574 2492 574 3 0 0 0 -1 -1 +V 2300 350 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1700 100 1700 400 1 0 0 +{ +T 1750 200 5 8 1 1 0 0 1 +pinnumber=7 +T 1750 200 5 8 0 1 0 2 1 +pinseq=7 +T 1700 450 9 8 1 1 0 3 1 +pinlabel=XTAL2 +T 1700 600 5 8 0 1 0 3 1 +pintype=out +} +P 1100 100 1100 400 1 0 0 +{ +T 1150 200 5 8 1 1 0 0 1 +pinnumber=8 +T 1150 200 5 8 0 1 0 2 1 +pinseq=8 +T 1100 450 9 8 1 1 0 3 1 +pinlabel=XTAL1 +T 1100 600 5 8 0 1 0 3 1 +pintype=in +} +P 100 2200 400 2200 1 0 0 +{ +T 300 2250 5 8 1 1 0 6 1 +pinnumber=16 +T 300 2150 5 8 0 1 0 8 1 +pinseq=16 +T 450 2200 9 8 1 1 0 0 1 +pinlabel=PD7 (OC2) +T 450 2200 5 8 0 1 0 2 1 +pintype=io +} +P 100 2600 400 2600 1 0 0 +{ +T 300 2650 5 8 1 1 0 6 1 +pinnumber=15 +T 300 2550 5 8 0 1 0 8 1 +pinseq=15 +T 450 2600 9 8 1 1 0 0 1 +pinlabel=PD6 (ICP1) +T 450 2600 5 8 0 1 0 2 1 +pintype=io +} +P 100 3000 400 3000 1 0 0 +{ +T 300 3050 5 8 1 1 0 6 1 +pinnumber=14 +T 300 2950 5 8 0 1 0 8 1 +pinseq=14 +T 450 3000 9 8 1 1 0 0 1 +pinlabel=PD5 (OC1A) +T 450 3000 5 8 0 1 0 2 1 +pintype=io +} +P 100 3400 400 3400 1 0 0 +{ +T 300 3450 5 8 1 1 0 6 1 +pinnumber=13 +T 300 3350 5 8 0 1 0 8 1 +pinseq=13 +T 450 3400 9 8 1 1 0 0 1 +pinlabel=PD4 (OC1B) +T 450 3400 5 8 0 1 0 2 1 +pintype=io +} +P 100 3800 400 3800 1 0 0 +{ +T 300 3850 5 8 1 1 0 6 1 +pinnumber=12 +T 300 3750 5 8 0 1 0 8 1 +pinseq=12 +T 450 3800 9 8 1 1 0 0 1 +pinlabel=PD3 (INT1) +T 450 3800 5 8 0 1 0 2 1 +pintype=io +} +P 100 4200 400 4200 1 0 0 +{ +T 300 4250 5 8 1 1 0 6 1 +pinnumber=11 +T 300 4150 5 8 0 1 0 8 1 +pinseq=11 +T 450 4200 9 8 1 1 0 0 1 +pinlabel=PD2 (INT0) +T 450 4200 5 8 0 1 0 2 1 +pintype=io +} +P 100 4600 400 4600 1 0 0 +{ +T 300 4650 5 8 1 1 0 6 1 +pinnumber=10 +T 300 4550 5 8 0 1 0 8 1 +pinseq=10 +T 450 4600 9 8 1 1 0 0 1 +pinlabel=PD1 (TXD) +T 450 4600 5 8 0 1 0 2 1 +pintype=io +} +P 100 5000 400 5000 1 0 0 +{ +T 300 5050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 4950 5 8 0 1 0 8 1 +pinseq=9 +T 450 5000 9 8 1 1 0 0 1 +pinlabel=PD0 (RXD) +T 450 5000 5 8 0 1 0 2 1 +pintype=io +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=3 +T 300 5550 5 8 0 1 0 8 1 +pinseq=3 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=PB7 (SCK) +T 450 5600 5 8 0 1 0 2 1 +pintype=io +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=2 +T 300 5950 5 8 0 1 0 8 1 +pinseq=2 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=PB6 (MISO) +T 450 6000 5 8 0 1 0 2 1 +pintype=io +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=1 +T 300 6350 5 8 0 1 0 8 1 +pinseq=1 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=PB5 (MOSI) +T 450 6400 5 8 0 1 0 2 1 +pintype=io +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=44 +T 300 6750 5 8 0 1 0 8 1 +pinseq=44 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=PB4 (SS) +T 450 6800 5 8 0 1 0 2 1 +pintype=io +} +L 862 6924 1062 6924 3 0 0 0 -1 -1 +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=43 +T 300 7150 5 8 0 1 0 8 1 +pinseq=43 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=PB3 (AIN1/OC0) +T 450 7200 5 8 0 1 0 2 1 +pintype=io +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=42 +T 300 7550 5 8 0 1 0 8 1 +pinseq=42 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=PB2 (AIN0/INT2) +T 450 7600 5 8 0 1 0 2 1 +pintype=io +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=41 +T 300 7950 5 8 0 1 0 8 1 +pinseq=41 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=PB1 (T1) +T 450 8000 5 8 0 1 0 2 1 +pintype=io +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=40 +T 300 8350 5 8 0 1 0 8 1 +pinseq=40 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=PB0 (XCK/T0) +T 450 8400 5 8 0 1 0 2 1 +pintype=io +} +P 3300 2200 3000 2200 1 0 0 +{ +T 3100 2250 5 8 1 1 0 0 1 +pinnumber=26 +T 3100 2150 5 8 0 1 0 2 1 +pinseq=26 +T 2950 2200 9 8 1 1 0 6 1 +pinlabel=(TOSC2) PC7 +T 2950 2200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 2600 3000 2600 1 0 0 +{ +T 3100 2650 5 8 1 1 0 0 1 +pinnumber=25 +T 3100 2550 5 8 0 1 0 2 1 +pinseq=25 +T 2950 2600 9 8 1 1 0 6 1 +pinlabel=(TOSC1) PC6 +T 2950 2600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3000 3000 3000 1 0 0 +{ +T 3100 3050 5 8 1 1 0 0 1 +pinnumber=24 +T 3100 2950 5 8 0 1 0 2 1 +pinseq=24 +T 2950 3000 9 8 1 1 0 6 1 +pinlabel=(TDI) PC5 +T 2950 3000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3400 3000 3400 1 0 0 +{ +T 3100 3450 5 8 1 1 0 0 1 +pinnumber=23 +T 3100 3350 5 8 0 1 0 2 1 +pinseq=23 +T 2950 3400 9 8 1 1 0 6 1 +pinlabel=(TDO) PC4 +T 2950 3400 5 8 0 1 0 8 1 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+pintype=io +} +P 3300 6000 3000 6000 1 0 0 +{ +T 3100 6050 5 8 1 1 0 0 1 +pinnumber=31 +T 3100 5950 5 8 0 1 0 2 1 +pinseq=31 +T 2950 6000 9 8 1 1 0 6 1 +pinlabel=(ADC6) PA6 +T 2950 6000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6400 3000 6400 1 0 0 +{ +T 3100 6450 5 8 1 1 0 0 1 +pinnumber=32 +T 3100 6350 5 8 0 1 0 2 1 +pinseq=32 +T 2950 6400 9 8 1 1 0 6 1 +pinlabel=(ADC5) PA5 +T 2950 6400 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6800 3000 6800 1 0 0 +{ +T 3100 6850 5 8 1 1 0 0 1 +pinnumber=33 +T 3100 6750 5 8 0 1 0 2 1 +pinseq=33 +T 2950 6800 9 8 1 1 0 6 1 +pinlabel=(ADC4) PA4 +T 2950 6800 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7200 3000 7200 1 0 0 +{ +T 3100 7250 5 8 1 1 0 0 1 +pinnumber=34 +T 3100 7150 5 8 0 1 0 2 1 +pinseq=34 +T 2950 7200 9 8 1 1 0 6 1 +pinlabel=(ADC3) PA3 +T 2950 7200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7600 3000 7600 1 0 0 +{ +T 3100 7650 5 8 1 1 0 0 1 +pinnumber=35 +T 3100 7550 5 8 0 1 0 2 1 +pinseq=35 +T 2950 7600 9 8 1 1 0 6 1 +pinlabel=(ADC2) PA2 +T 2950 7600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8000 3000 8000 1 0 0 +{ +T 3100 8050 5 8 1 1 0 0 1 +pinnumber=36 +T 3100 7950 5 8 0 1 0 2 1 +pinseq=36 +T 2950 8000 9 8 1 1 0 6 1 +pinlabel=(ADC1) PA1 +T 2950 8000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8400 3000 8400 1 0 0 +{ +T 3100 8450 5 8 1 1 0 0 1 +pinnumber=37 +T 3100 8350 5 8 0 1 0 2 1 +pinseq=37 +T 2950 8400 9 8 1 1 0 6 1 +pinlabel=(ADC0) PA0 +T 2950 8400 5 8 0 1 0 8 1 +pintype=io +} +B 400 400 2600 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 9850 5 10 0 0 0 0 1 +description=8-bit RISC micro controller (Atmel) +T 400 10050 5 10 0 0 0 0 1 +numslots=0 +T 400 10250 5 10 0 0 0 0 1 +author=Matthijs ten Berge +T 400 8850 9 10 1 0 0 0 1 +ATmega16 +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=27 +T 300 1550 5 8 0 1 0 8 1 +pinseq=27 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=AVCC +T 450 1600 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=29 +T 300 1150 5 8 0 1 0 8 1 +pinseq=29 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=AREF +T 450 1200 5 8 0 1 0 2 1 +pintype=io +} +T 0 0 8 10 0 0 0 0 1 +dist-license=GPL +T 1600 0 8 10 0 0 0 0 1 +use-license=unlimited +T 0 200 8 10 0 0 0 0 1 +comment=Suggested library: micro diff --git a/gschem-sym/ATxmega128A3u-AU.sym b/gschem-sym/ATxmega128A3u-AU.sym new file mode 100644 index 0000000..c10443d --- /dev/null +++ b/gschem-sym/ATxmega128A3u-AU.sym @@ -0,0 +1,596 @@ +v 20110115 2 +B 300 4300 4200 10100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 500 15000 9 10 0 0 0 0 1 +distlicense=GPL3 +T 500 15200 9 10 0 0 0 0 1 +uselicense=no restrictions +T 500 15400 9 10 0 0 0 0 1 +author=Kai-Martin Knaak, kmk@lilalaser.de +T 500 15800 9 10 0 0 0 0 1 +description=ATXmegaA1, TQFP-100 +T 500 16000 9 10 0 0 0 0 1 +device=ATXmegaA1 +T 4600 14400 8 8 1 1 0 0 1 +footprint=TQFP64_14 +T 2000 13300 8 36 1 1 270 0 1 +value=ATXmega128A3U-AU +T 4600 14600 8 10 1 1 0 0 1 +refdes=U? +P 200 11700 300 11700 1 0 0 +{ +T 350 11700 9 10 1 1 0 1 1 +pinlabel=PA6 +T 200 11750 5 8 1 1 0 6 1 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--git a/gschem-sym/MOD__MaxStream_XBee_PRO.fp b/gschem-sym/MOD__MaxStream_XBee_PRO.fp new file mode 100644 index 0000000..c3cf346 --- /dev/null +++ b/gschem-sym/MOD__MaxStream_XBee_PRO.fp @@ -0,0 +1,97 @@ +Element[0x0 "IC" "" "" 0 0 -48992 -62939 0 100 0x0] +( + ElementLine[-48992 65842 -48992 -42133 1000] + ElementLine[-48992 -42133 -20110 -65842 1000] + ElementLine[-20110 -65842 20110 -65842 1000] + ElementLine[20110 -65842 48992 -42133 1000] + ElementLine[48992 -42133 48992 65842 1000] + ElementLine[48992 65842 -48992 65842 1000] + ElementLine[-35433 15748 35433 15748 2000] + ElementLine[-35433 -14763 35433 -14763 2000] + ElementLine[-31496 9842 -22637 984 1000] + ElementLine[-22637 984 -26574 -9842 1000] + ElementLine[-26574 -9842 -18208 -9842 1000] + ElementLine[-18208 -9842 -16732 -4921 1000] + ElementLine[-16732 -4921 -11811 -9842 1000] + ElementLine[-11811 -9842 -6889 -9842 1000] + ElementLine[-6889 -9842 -15748 -1476 1000] + ElementLine[-15748 -1476 -11811 9842 1000] + ElementLine[-11811 9842 -18700 9842 1000] + ElementLine[-18700 9842 -20669 3937 1000] + ElementLine[-20669 3937 -26574 9842 1000] + ElementLine[-26574 9842 -31496 9842 1000] + ElementLine[492 9842 -5019 9842 2000] + ElementLine[-5019 9842 -5019 -3937 2000] + ElementLine[-5019 -3937 492 -3937 2000] + ElementLine[-5019 2952 492 2952 2000] + ElementLine[16486 9842 9596 9842 2000] + ElementLine[9596 9842 9596 -3937 2000] + ElementLine[9596 -3937 16486 -3937 2000] + ElementLine[9596 2952 14763 2952 2000] + ElementLine[29281 9842 22391 9842 2000] + ElementLine[22391 9842 22391 -3937 2000] + ElementLine[22391 -3937 29281 -3937 2000] + ElementLine[22391 2952 27559 2952 2000] + ElementArc[688 -492 3444 3444 90 180 2000] + ElementArc[688 6397 3444 3444 90 180 2000] + Pad[-44682 -39133 -41932 -39133 5500 2000 7500 "" "1" 0x0800] + Pad[-44682 -39133 -41932 -39133 5500 2000 7500 "" "1" 0x0880] + Pin[-43307 -39133 5500 2000 7500 2899 "" "1" 0x01] + Pad[-44682 -31259 -41932 -31259 5500 2000 7500 "" "2" 0x0800] + Pad[-44682 -31259 -41932 -31259 5500 2000 7500 "" "2" 0x0880] + Pin[-43307 -31259 5500 2000 7500 2899 "" "2" 0x01] + Pad[-44682 -23385 -41932 -23385 5500 2000 7500 "" "3" 0x0800] + Pad[-44682 -23385 -41932 -23385 5500 2000 7500 "" "3" 0x0880] + Pin[-43307 -23385 5500 2000 7500 2899 "" "3" 0x01] + Pad[-44682 -15511 -41932 -15511 5500 2000 7500 "" "4" 0x0800] + Pad[-44682 -15511 -41932 -15511 5500 2000 7500 "" "4" 0x0880] + Pin[-43307 -15511 5500 2000 7500 2899 "" "4" 0x01] + Pad[-44682 -7637 -41932 -7637 5500 2000 7500 "" "5" 0x0800] + Pad[-44682 -7637 -41932 -7637 5500 2000 7500 "" "5" 0x0880] + Pin[-43307 -7637 5500 2000 7500 2899 "" "5" 0x01] + Pad[-44682 236 -41932 236 5500 2000 7500 "" "6" 0x0800] + Pad[-44682 236 -41932 236 5500 2000 7500 "" "6" 0x0880] + Pin[-43307 236 5500 2000 7500 2899 "" "6" 0x01] + Pad[-44682 8110 -41932 8110 5500 2000 7500 "" "7" 0x0800] + Pad[-44682 8110 -41932 8110 5500 2000 7500 "" "7" 0x0880] + Pin[-43307 8110 5500 2000 7500 2899 "" "7" 0x01] + Pad[-44682 15984 -41932 15984 5500 2000 7500 "" "8" 0x0800] + Pad[-44682 15984 -41932 15984 5500 2000 7500 "" "8" 0x0880] + Pin[-43307 15984 5500 2000 7500 2899 "" "8" 0x01] + Pad[-44682 23858 -41932 23858 5500 2000 7500 "" "9" 0x0800] + Pad[-44682 23858 -41932 23858 5500 2000 7500 "" "9" 0x0880] + Pin[-43307 23858 5500 2000 7500 2899 "" "9" 0x01] + Pad[-44682 31732 -41932 31732 5500 2000 7500 "" "10" 0x0800] + Pad[-44682 31732 -41932 31732 5500 2000 7500 "" "10" 0x0880] + Pin[-43307 31732 5500 2000 7500 2899 "" "10" 0x01] + Pad[41932 31732 44682 31732 5500 2000 7500 "" "11" 0x0800] + Pad[41932 31732 44682 31732 5500 2000 7500 "" "11" 0x0880] + Pin[43307 31732 5500 2000 7500 2899 "" "11" 0x01] + Pad[41932 23858 44682 23858 5500 2000 7500 "" "12" 0x0800] + Pad[41932 23858 44682 23858 5500 2000 7500 "" "12" 0x0880] + Pin[43307 23858 5500 2000 7500 2899 "" "12" 0x01] + Pad[41932 15984 44682 15984 5500 2000 7500 "" "13" 0x0800] + Pad[41932 15984 44682 15984 5500 2000 7500 "" "13" 0x0880] + Pin[43307 15984 5500 2000 7500 2899 "" "13" 0x01] + Pad[41932 8110 44682 8110 5500 2000 7500 "" "14" 0x0800] + Pad[41932 8110 44682 8110 5500 2000 7500 "" "14" 0x0880] + Pin[43307 8110 5500 2000 7500 2899 "" "14" 0x01] + Pad[41932 236 44682 236 5500 2000 7500 "" "15" 0x0800] + Pad[41932 236 44682 236 5500 2000 7500 "" "15" 0x0880] + Pin[43307 236 5500 2000 7500 2899 "" "15" 0x01] + Pad[41932 -7637 44682 -7637 5500 2000 7500 "" "16" 0x0800] + Pad[41932 -7637 44682 -7637 5500 2000 7500 "" "16" 0x0880] + Pin[43307 -7637 5500 2000 7500 2899 "" "16" 0x01] + Pad[41932 -15511 44682 -15511 5500 2000 7500 "" "17" 0x0800] + Pad[41932 -15511 44682 -15511 5500 2000 7500 "" "17" 0x0880] + Pin[43307 -15511 5500 2000 7500 2899 "" "17" 0x01] + Pad[41932 -23385 44682 -23385 5500 2000 7500 "" "18" 0x0800] + Pad[41932 -23385 44682 -23385 5500 2000 7500 "" "18" 0x0880] + Pin[43307 -23385 5500 2000 7500 2899 "" "18" 0x01] + Pad[41932 -31259 44682 -31259 5500 2000 7500 "" "19" 0x0800] + Pad[41932 -31259 44682 -31259 5500 2000 7500 "" "19" 0x0880] + Pin[43307 -31259 5500 2000 7500 2899 "" "19" 0x01] + Pad[41932 -39133 44682 -39133 5500 2000 7500 "" "20" 0x0800] + Pad[41932 -39133 44682 -39133 5500 2000 7500 "" "20" 0x0880] + Pin[43307 -39133 5500 2000 7500 2899 "" "20" 0x01] +) diff --git a/gschem-sym/atmega168.sym b/gschem-sym/atmega168.sym new file mode 100644 index 0000000..97bd044 --- /dev/null +++ b/gschem-sym/atmega168.sym @@ -0,0 +1,320 @@ +v 20040111 1 +B 1000 1000 3000 5000 3 10 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1000 6050 8 10 1 1 0 0 1 +refdes=U? +T 1000 1000 9 8 0 1 0 2 1 +value= +T 1000 1000 9 8 0 1 0 2 1 +footprint=DIP-28-300 +T 1000 1000 9 8 0 1 0 2 1 +manufacturer=Atmel +T 1000 1000 9 8 0 1 0 2 1 +manufacturer_part_number=ATmega168-20PU +P 1000 5800 900 5800 1 0 1 +{ +T 950 5850 5 8 1 1 0 6 1 +pinnumber=1 +T 1050 5850 5 8 0 1 0 0 1 +pinseq=1 +T 1050 5750 5 8 0 1 0 2 1 +pintype=in +T 1050 5800 9 8 1 1 0 1 1 +pinlabel=RESET' +} +P 4000 2600 4100 2600 1 0 1 +{ +T 4050 2650 5 8 1 1 0 0 1 +pinnumber=2 +T 3950 2650 5 8 0 1 0 6 1 +pinseq=2 +T 3950 2550 5 8 0 1 0 8 1 +pintype=in +T 3950 2600 9 8 1 1 0 7 1 +pinlabel=PD0/PCINT16/RXD +} +P 4000 2400 4100 2400 1 0 1 +{ +T 4050 2450 5 8 1 1 0 0 1 +pinnumber=3 +T 3950 2450 5 8 0 1 0 6 1 +pinseq=3 +T 3950 2350 5 8 0 1 0 8 1 +pintype=in +T 3950 2400 9 8 1 1 0 7 1 +pinlabel=PD1/PCINT17/TXD +} +P 4000 2200 4100 2200 1 0 1 +{ +T 4050 2250 5 8 1 1 0 0 1 +pinnumber=4 +T 3950 2250 5 8 0 1 0 6 1 +pinseq=4 +T 3950 2150 5 8 0 1 0 8 1 +pintype=in +T 3950 2200 9 8 1 1 0 7 1 +pinlabel=PD2/PCINT18/INT0 +} +P 4000 2000 4100 2000 1 0 1 +{ +T 4050 2050 5 8 1 1 0 0 1 +pinnumber=5 +T 3950 2050 5 8 0 1 0 6 1 +pinseq=5 +T 3950 1950 5 8 0 1 0 8 1 +pintype=in +T 3950 2000 9 8 1 1 0 7 1 +pinlabel=PD3/PCINT19/INT1/OC2B +} +P 4000 1800 4100 1800 1 0 1 +{ +T 4050 1850 5 8 1 1 0 0 1 +pinnumber=6 +T 3950 1850 5 8 0 1 0 6 1 +pinseq=6 +T 3950 1750 5 8 0 1 0 8 1 +pintype=in +T 3950 1800 9 8 1 1 0 7 1 +pinlabel=PD4/PCINT20/XCK/T0 +} +P 1000 3400 900 3400 1 0 1 +{ +T 950 3450 5 8 1 1 0 6 1 +pinnumber=7 +T 1050 3450 5 8 0 1 0 0 1 +pinseq=7 +T 1050 3350 5 8 0 1 0 2 1 +pintype=pwr +T 1050 3400 9 8 1 1 0 1 1 +pinlabel=VCC +} +P 1000 1400 900 1400 1 0 1 +{ +T 950 1450 5 8 1 1 0 6 1 +pinnumber=8 +T 1050 1450 5 8 0 1 0 0 1 +pinseq=8 +T 1050 1350 5 8 0 1 0 2 1 +pintype=pwr +T 1050 1400 9 8 1 1 0 1 1 +pinlabel=GND +} +P 1000 4500 900 4500 1 0 1 +{ +T 950 4550 5 8 1 1 0 6 1 +pinnumber=9 +T 1050 4550 5 8 0 1 0 0 1 +pinseq=9 +T 1050 4450 5 8 0 1 0 2 1 +pintype=in +T 1050 4500 9 8 1 1 0 1 1 +pinlabel=XTAL1 +} +P 1000 3900 900 3900 1 0 1 +{ +T 950 3950 5 8 1 1 0 6 1 +pinnumber=10 +T 1050 3950 5 8 0 1 0 0 1 +pinseq=10 +T 1050 3850 5 8 0 1 0 2 1 +pintype=in +T 1050 3900 9 8 1 1 0 1 1 +pinlabel=XTAL2 +} +P 4000 1600 4100 1600 1 0 1 +{ +T 4050 1650 5 8 1 1 0 0 1 +pinnumber=11 +T 3950 1650 5 8 0 1 0 6 1 +pinseq=11 +T 3950 1550 5 8 0 1 0 8 1 +pintype=in +T 3950 1600 9 8 1 1 0 7 1 +pinlabel=PD5/PCINT21/OC0B/T1 +} +P 4000 1400 4100 1400 1 0 1 +{ +T 4050 1450 5 8 1 1 0 0 1 +pinnumber=12 +T 3950 1450 5 8 0 1 0 6 1 +pinseq=12 +T 3950 1350 5 8 0 1 0 8 1 +pintype=in +T 3950 1400 9 8 1 1 0 7 1 +pinlabel=PD6/PCINT22/OC0A/AIN0 +} +P 4000 1200 4100 1200 1 0 1 +{ +T 4050 1250 5 8 1 1 0 0 1 +pinnumber=13 +T 3950 1250 5 8 0 1 0 6 1 +pinseq=13 +T 3950 1150 5 8 0 1 0 8 1 +pintype=in +T 3950 1200 9 8 1 1 0 7 1 +pinlabel=PD7/PCINT23/AIN1 +} +P 4000 5800 4100 5800 1 0 1 +{ +T 4050 5850 5 8 1 1 0 0 1 +pinnumber=14 +T 3950 5850 5 8 0 1 0 6 1 +pinseq=14 +T 3950 5750 5 8 0 1 0 8 1 +pintype=in +T 3950 5800 9 8 1 1 0 7 1 +pinlabel=PB0/PCINT0/CLKO/ICP1 +} +P 4000 5600 4100 5600 1 0 1 +{ +T 4050 5650 5 8 1 1 0 0 1 +pinnumber=15 +T 3950 5650 5 8 0 1 0 6 1 +pinseq=15 +T 3950 5550 5 8 0 1 0 8 1 +pintype=in +T 3950 5600 9 8 1 1 0 7 1 +pinlabel=PB1/PCINT1/OC1A +} +P 4000 5400 4100 5400 1 0 1 +{ +T 4050 5450 5 8 1 1 0 0 1 +pinnumber=16 +T 3950 5450 5 8 0 1 0 6 1 +pinseq=16 +T 3950 5350 5 8 0 1 0 8 1 +pintype=in +T 3950 5400 9 8 1 1 0 7 1 +pinlabel=PB2/PCINT2/OC1B/SS' +} +P 4000 5200 4100 5200 1 0 1 +{ +T 4050 5250 5 8 1 1 0 0 1 +pinnumber=17 +T 3950 5250 5 8 0 1 0 6 1 +pinseq=17 +T 3950 5150 5 8 0 1 0 8 1 +pintype=in +T 3950 5200 9 8 1 1 0 7 1 +pinlabel=PB3/PCINT3/OC2A/MOSI +} +P 4000 5000 4100 5000 1 0 1 +{ +T 4050 5050 5 8 1 1 0 0 1 +pinnumber=18 +T 3950 5050 5 8 0 1 0 6 1 +pinseq=18 +T 3950 4950 5 8 0 1 0 8 1 +pintype=in +T 3950 5000 9 8 1 1 0 7 1 +pinlabel=PB4/PCINT4/MISO +} +P 4000 4800 4100 4800 1 0 1 +{ +T 4050 4850 5 8 1 1 0 0 1 +pinnumber=19 +T 3950 4850 5 8 0 1 0 6 1 +pinseq=19 +T 3950 4750 5 8 0 1 0 8 1 +pintype=in +T 3950 4800 9 8 1 1 0 7 1 +pinlabel=PB5/PCINT5/SCK +} +P 1000 2400 900 2400 1 0 1 +{ +T 950 2450 5 8 1 1 0 6 1 +pinnumber=20 +T 1050 2450 5 8 0 1 0 0 1 +pinseq=20 +T 1050 2350 5 8 0 1 0 2 1 +pintype=pwr +T 1050 2400 9 8 1 1 0 1 1 +pinlabel=AVCC +} +P 1000 2000 900 2000 1 0 1 +{ +T 950 2050 5 8 1 1 0 6 1 +pinnumber=21 +T 1050 2050 5 8 0 1 0 0 1 +pinseq=21 +T 1050 1950 5 8 0 1 0 2 1 +pintype=in +T 1050 2000 9 8 1 1 0 1 1 +pinlabel=AREF +} +P 1000 1200 900 1200 1 0 1 +{ +T 950 1250 5 8 1 1 0 6 1 +pinnumber=22 +T 1050 1250 5 8 0 1 0 0 1 +pinseq=22 +T 1050 1150 5 8 0 1 0 2 1 +pintype=pwr +T 1050 1200 9 8 1 1 0 1 1 +pinlabel=GND +} +P 4000 4400 4100 4400 1 0 1 +{ +T 4050 4450 5 8 1 1 0 0 1 +pinnumber=23 +T 3950 4450 5 8 0 1 0 6 1 +pinseq=23 +T 3950 4350 5 8 0 1 0 8 1 +pintype=in +T 3950 4400 9 8 1 1 0 7 1 +pinlabel=PC0/PCINT8/ADC0 +} +P 4000 4200 4100 4200 1 0 1 +{ +T 4050 4250 5 8 1 1 0 0 1 +pinnumber=24 +T 3950 4250 5 8 0 1 0 6 1 +pinseq=24 +T 3950 4150 5 8 0 1 0 8 1 +pintype=in +T 3950 4200 9 8 1 1 0 7 1 +pinlabel=PC1/PCINT9/ADC1 +} +P 4000 4000 4100 4000 1 0 1 +{ +T 4050 4050 5 8 1 1 0 0 1 +pinnumber=25 +T 3950 4050 5 8 0 1 0 6 1 +pinseq=25 +T 3950 3950 5 8 0 1 0 8 1 +pintype=in +T 3950 4000 9 8 1 1 0 7 1 +pinlabel=PC2/PCINT10/ADC2 +} +P 4000 3800 4100 3800 1 0 1 +{ +T 4050 3850 5 8 1 1 0 0 1 +pinnumber=26 +T 3950 3850 5 8 0 1 0 6 1 +pinseq=26 +T 3950 3750 5 8 0 1 0 8 1 +pintype=in +T 3950 3800 9 8 1 1 0 7 1 +pinlabel=PC3/PCINT11/ADC3 +} +P 4000 3600 4100 3600 1 0 1 +{ +T 4050 3650 5 8 1 1 0 0 1 +pinnumber=27 +T 3950 3650 5 8 0 1 0 6 1 +pinseq=27 +T 3950 3550 5 8 0 1 0 8 1 +pintype=in +T 3950 3600 9 8 1 1 0 7 1 +pinlabel=PC4/PCINT12/ADC4/SDA +} +P 4000 3400 4100 3400 1 0 1 +{ +T 4050 3450 5 8 1 1 0 0 1 +pinnumber=28 +T 3950 3450 5 8 0 1 0 6 1 +pinseq=28 +T 3950 3350 5 8 0 1 0 8 1 +pintype=in +T 3950 3400 9 8 1 1 0 7 1 +pinlabel=PC5/PCINT13/ADC5/SCL +} diff --git a/gschem-sym/lm1117.sym b/gschem-sym/lm1117.sym new file mode 100644 index 0000000..7a9425b --- /dev/null +++ b/gschem-sym/lm1117.sym @@ -0,0 +1,35 @@ +v 20110115 2 +B 300 300 1400 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1700 800 2000 800 1 0 1 +{ +T 1800 1100 5 10 0 0 0 0 1 +pinnumber=2 +T 1800 900 5 10 1 1 0 0 1 +pinseq=2 +T 1600 800 9 10 1 1 0 6 1 +pinlabel=Vout +} +P 0 800 300 800 1 0 0 +{ +T 200 900 5 10 1 1 0 6 1 +pinnumber=3 +T 0 1000 5 10 0 0 0 0 1 +pinseq=3 +T 400 800 9 10 1 1 0 0 1 +pinlabel=Vin +} +P 1000 0 1000 300 1 0 0 +{ +T 1100 100 5 10 1 1 0 0 1 +pinnumber=1 +T 200 100 5 10 0 0 0 0 1 +pinseq=1 +T 1000 400 9 10 1 1 0 3 1 +pinlabel=Ajd +} +T 300 1400 9 10 1 0 0 0 1 +LM1117 +T 300 1700 8 10 0 0 0 0 1 +device=LM317 +T 1700 1400 8 10 1 1 0 6 1 +refdes=U? diff --git a/gschem-sym/xbee.sym b/gschem-sym/xbee.sym new file mode 100644 index 0000000..99bcce6 --- /dev/null +++ b/gschem-sym/xbee.sym @@ -0,0 +1,232 @@ +v 20110115 2 +P 3800 3800 3500 3800 1 0 0 +{ +T 3900 3800 5 10 0 0 0 0 1 +pintype=io +T 3445 3795 9 9 1 1 0 6 1 +pinlabel=AD0 / DIO0 / Commisioning Button +T 3595 3845 5 10 1 1 0 0 1 +pinnumber=20 +T 3900 3800 5 10 0 0 0 0 1 +pinseq=20 +} +P 100 200 400 200 1 0 0 +{ +T -100 200 5 10 0 0 0 0 1 +pintype=pwr +T 455 195 9 9 1 1 0 0 1 +pinlabel=GND +T 305 245 5 10 1 1 0 6 1 +pinnumber=10 +T -100 200 5 10 0 0 0 0 1 +pinseq=10 +} +P 100 600 400 600 1 0 0 +{ +T -100 600 5 10 0 0 0 0 1 +pintype=io +T 455 595 9 9 1 1 0 0 1 +pinlabel=\_DTR\_ / SLEEP_RQ / DIO8 +T 305 645 5 10 1 1 0 6 1 +pinnumber=9 +T -100 600 5 10 0 0 0 0 1 +pinseq=9 +} +P 100 1400 400 1400 1 0 0 +{ +T -100 1400 5 10 0 0 0 0 1 +pintype=io +T 455 1395 9 9 1 1 0 0 1 +pinlabel=DIO11 +T 305 1445 5 10 1 1 0 6 1 +pinnumber=7 +T -100 1400 5 10 0 0 0 0 1 +pinseq=7 +} +P 100 1800 400 1800 1 0 0 +{ +T -100 1800 5 10 0 0 0 0 1 +pintype=io +T 455 1795 9 9 1 1 0 0 1 +pinlabel=RSSI PWM / DIO10 +T 305 1845 5 10 1 1 0 6 1 +pinnumber=6 +T -100 1800 5 10 0 0 0 0 1 +pinseq=6 +} +P 100 2200 400 2200 1 0 0 +{ +T -100 2200 5 10 0 0 0 0 1 +pintype=in +T 455 2195 9 9 1 1 0 0 1 +pinlabel=\_RESET\_ +T 305 2245 5 10 1 1 0 6 1 +pinnumber=5 +T -100 2200 5 10 0 0 0 0 1 +pinseq=5 +} +P 100 2600 400 2600 1 0 0 +{ +T -100 2600 5 10 0 0 0 0 1 +pintype=io +T 455 2595 9 9 1 1 0 0 1 +pinlabel=DIO12 +T 305 2645 5 10 1 1 0 6 1 +pinnumber=4 +T -100 2600 5 10 0 0 0 0 1 +pinseq=4 +} +P 100 1000 400 1000 1 0 0 +{ +T -100 1000 5 10 0 0 0 0 1 +pintype=pas +T 455 995 9 9 1 1 0 0 1 +pinlabel=RESERVED +T 305 1045 5 10 1 1 0 6 1 +pinnumber=8 +T -100 1000 5 10 0 0 0 0 1 +pinseq=8 +} +B 400 100 3100 3900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 3000 400 3000 1 0 0 +{ +T -100 3000 5 10 0 0 0 0 1 +pintype=in +T 455 2995 9 9 1 1 0 0 1 +pinlabel=DIN / \_CONFIG\_ +T 305 3045 5 10 1 1 0 6 1 +pinnumber=3 +T -100 3000 5 10 0 0 0 0 1 +pinseq=3 +} +P 100 3400 400 3400 1 0 0 +{ +T -100 3400 5 10 0 0 0 0 1 +pintype=out +T 455 3395 9 9 1 1 0 0 1 +pinlabel=DOUT +T 305 3445 5 10 1 1 0 6 1 +pinnumber=2 +T -100 3400 5 10 0 0 0 0 1 +pinseq=2 +} +P 100 3800 400 3800 1 0 0 +{ +T -100 3800 5 10 0 0 0 0 1 +pintype=pwr +T 455 3795 9 9 1 1 0 0 1 +pinlabel=VCC +T 305 3845 5 10 1 1 0 6 1 +pinnumber=1 +T -100 3800 5 10 0 0 0 0 1 +pinseq=1 +} +P 3800 3400 3500 3400 1 0 0 +{ +T 3900 3400 5 10 0 0 0 0 1 +pintype=io +T 3445 3395 9 9 1 1 0 6 1 +pinlabel=AD1 / DIO1 +T 3595 3445 5 10 1 1 0 0 1 +pinnumber=19 +T 3900 3400 5 10 0 0 0 0 1 +pinseq=19 +} +P 3800 3000 3500 3000 1 0 0 +{ +T 3900 3000 5 10 0 0 0 0 1 +pintype=io +T 3445 2995 9 9 1 1 0 6 1 +pinlabel=AD2 / DIO2 +T 3595 3045 5 10 1 1 0 0 1 +pinnumber=18 +T 3900 3000 5 10 0 0 0 0 1 +pinseq=18 +} +P 3800 2600 3500 2600 1 0 0 +{ +T 3900 2600 5 10 0 0 0 0 1 +pintype=io +T 3445 2595 9 9 1 1 0 6 1 +pinlabel=AD3 / DIO3 +T 3595 2645 5 10 1 1 0 0 1 +pinnumber=17 +T 3900 2600 5 10 0 0 0 0 1 +pinseq=17 +} +P 3800 2200 3500 2200 1 0 0 +{ +T 3900 2200 5 10 0 0 0 0 1 +pintype=io +T 3445 2195 9 9 1 1 0 6 1 +pinlabel=\_RTS\_ / DIO6 +T 3595 2245 5 10 1 1 0 0 1 +pinnumber=16 +T 3900 2200 5 10 0 0 0 0 1 +pinseq=16 +} +P 3800 1800 3500 1800 1 0 0 +{ +T 3900 1800 5 10 0 0 0 0 1 +pintype=io +T 3445 1795 9 9 1 1 0 6 1 +pinlabel=Associate / DIO5 +T 3595 1845 5 10 1 1 0 0 1 +pinnumber=15 +T 3900 1800 5 10 0 0 0 0 1 +pinseq=15 +} +P 3800 1400 3500 1400 1 0 0 +{ +T 3900 1400 5 10 0 0 0 0 1 +pintype=io +T 3445 1395 9 9 1 1 0 6 1 +pinlabel=VREF +T 3595 1445 5 10 1 1 0 0 1 +pinnumber=14 +T 3900 1400 5 10 0 0 0 0 1 +pinseq=14 +} +P 3800 200 3500 200 1 0 0 +{ +T 3900 200 5 10 0 0 0 0 1 +pintype=io +T 3445 195 9 9 1 1 0 6 1 +pinlabel=DIO4 +T 3595 245 5 10 1 1 0 0 1 +pinnumber=11 +T 3900 200 5 10 0 0 0 0 1 +pinseq=11 +} +P 3800 600 3500 600 1 0 0 +{ +T 3900 600 5 10 0 0 0 0 1 +pintype=io +T 3445 595 9 9 1 1 0 6 1 +pinlabel=\_CTS\_ / DIO7 +T 3595 645 5 10 1 1 0 0 1 +pinnumber=12 +T 3900 600 5 10 0 0 0 0 1 +pinseq=12 +} +P 3800 1000 3500 1000 1 0 0 +{ +T 3900 1000 5 10 0 0 0 0 1 +pintype=out +T 3445 995 9 9 1 1 0 6 1 +pinlabel=ON / \_SLEEP\_ +T 3595 1045 5 10 1 1 0 0 1 +pinnumber=13 +T 3900 1000 5 10 0 0 0 0 1 +pinseq=13 +} +T 3295 4100 8 10 1 1 0 0 1 +refdes=U? +T 400 4100 9 10 1 0 0 0 1 +XBEE +T 95 100 8 10 0 1 0 0 1 +author=Nicholas De Cicco velociostrich@gmail.com +T 95 100 8 10 0 1 0 0 1 +dist-license=GPLv3 +T 95 100 8 10 0 1 0 0 1 +use-license=unlimited diff --git a/mainboard/gafrc b/mainboard/gafrc new file mode 100644 index 0000000..f3dd10c --- /dev/null +++ b/mainboard/gafrc @@ -0,0 +1 @@ +(component-library "../gschem-sym") diff --git a/mainboard/mainboard.sch b/mainboard/mainboard.sch new file mode 100644 index 0000000..c92859d --- /dev/null +++ b/mainboard/mainboard.sch @@ -0,0 +1,1304 @@ +v 20110115 2 +C 43400 37500 1 0 0 ATxmega128A3u-AU.sym +{ +T 43900 53500 5 10 0 0 0 0 1 +device=ATXmegaA1 +T 47300 52000 5 8 1 1 0 0 1 +footprint=TQFP64_14 +T 45400 50800 5 36 1 1 270 0 1 +value=ATXmega128A3U-AU +T 47300 52200 5 10 1 1 0 0 1 +refdes=U1 +} +C 44600 53000 1 0 0 3.3V-plus-1.sym +C 44700 40600 1 0 0 gnd-1.sym +N 44800 53000 44800 52000 4 +N 44800 52500 46800 52500 4 +N 45200 52500 45200 52000 4 +N 45600 52500 45600 52000 4 +N 46000 52500 46000 52000 4 +N 46400 52500 46400 52000 4 +N 46800 52500 46800 52000 4 +N 44800 40900 44800 41700 4 +N 40800 40900 46800 40900 4 +N 45200 40900 45200 41700 4 +N 45600 40900 45600 41700 4 +N 46000 40900 46000 41700 4 +N 46400 40900 46400 41700 4 +N 46800 40900 46800 41700 4 +C 40600 42200 1 270 0 capacitor-1.sym +{ +T 41300 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 40900 42100 5 10 1 1 270 0 1 +refdes=C? +T 41500 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 40600 42400 5 10 1 1 270 0 1 +value=100nF +} +C 41100 42200 1 270 0 capacitor-1.sym +{ +T 41800 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 41400 42100 5 10 1 1 270 0 1 +refdes=C? +T 42000 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 41100 42400 5 10 1 1 270 0 1 +value=100nF +} +C 41600 42200 1 270 0 capacitor-1.sym +{ +T 42300 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 41900 42100 5 10 1 1 270 0 1 +refdes=C? +T 42500 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 41600 42400 5 10 1 1 270 0 1 +value=100nF +} +C 42100 42200 1 270 0 capacitor-1.sym +{ +T 42800 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 42400 42100 5 10 1 1 270 0 1 +refdes=C? +T 43000 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 42100 42400 5 10 1 1 270 0 1 +value=100nF +} +C 42600 42200 1 270 0 capacitor-1.sym +{ +T 43300 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 42900 42100 5 10 1 1 270 0 1 +refdes=C? +T 43500 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 42600 42400 5 10 1 1 270 0 1 +value=100nF +} +C 43100 42200 1 270 0 capacitor-1.sym +{ +T 43800 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 43400 42100 5 10 1 1 270 0 1 +refdes=C? +T 44000 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 43100 42400 5 10 1 1 270 0 1 +value=100nF +} +N 40800 40900 40800 41300 4 +N 41300 41300 41300 40900 4 +N 41800 41300 41800 40900 4 +N 42300 41300 42300 40900 4 +N 42800 41300 42800 40900 4 +N 43300 41300 43300 40900 4 +N 40800 42200 40800 42800 4 +N 41300 42200 41300 42600 4 +N 40800 42600 43300 42600 4 +N 41800 42200 41800 42600 4 +N 42300 42200 42300 42600 4 +N 42800 42200 42800 42600 4 +N 43300 42200 43300 42600 4 +C 52000 57300 1 0 0 5V-plus-1.sym +C 40600 42800 1 0 0 3.3V-plus-1.sym +C 61800 41900 1 0 0 xbee.sym +{ +T 65095 46000 5 10 1 1 0 0 1 +refdes=U3 +} +C 61100 46100 1 0 0 3.3V-plus-1.sym +N 61900 45700 61300 45700 4 +N 61900 45300 60700 45300 4 +{ +T 60700 45400 5 10 1 1 0 0 1 +netname=TX_XBEE +} +N 61900 44900 60700 44900 4 +{ +T 60700 45000 5 10 1 1 0 0 1 +netname=RX_XBEE +} +N 61900 42500 60900 42500 4 +{ +T 60900 42600 5 10 1 1 0 0 1 +netname=DTR_XBEE +} +N 65600 42500 66800 42500 4 +{ +T 65900 42600 5 10 1 1 0 0 1 +netname=CTS_XBEE +} +N 65600 44100 66800 44100 4 +{ +T 65900 44200 5 10 1 1 0 0 1 +netname=RTS_XBEE +} +C 61600 41400 1 0 0 gnd-1.sym +N 61300 45700 61300 46100 4 +C 60600 41900 1 0 0 capacitor-1.sym +{ +T 60800 42600 5 10 0 0 0 0 1 +device=CAPACITOR +T 60700 42200 5 10 1 1 0 0 1 +refdes=C? +T 60800 42800 5 10 0 0 0 0 1 +symversion=0.1 +T 60400 41900 5 10 1 1 0 0 1 +value=100nF +} +N 60300 42100 60300 42400 4 +C 60100 42400 1 0 0 3.3V-plus-1.sym +N 61900 42100 61500 42100 4 +N 61700 42100 61700 41700 4 +N 60300 42100 60600 42100 4 +N 43600 45200 42300 45200 4 +{ +T 42300 45300 5 10 1 1 0 0 1 +netname=TX_XBEE +} +N 43600 44900 42300 44900 4 +{ +T 42300 45000 5 10 1 1 0 0 1 +netname=RX_XBEE +} +C 52900 53100 1 0 0 ATmega168-TQFP-1.sym +{ +T 56300 61700 5 10 1 1 0 6 1 +refdes=U2 +T 53300 61900 5 10 0 0 0 0 1 +device=ATMEGA168 +T 53300 62100 5 10 0 0 0 0 1 +footprint=TQFP32 +} +C 52600 58500 1 0 0 gnd-1.sym +N 53000 58800 52700 58800 4 +N 52700 58800 52700 59600 4 +N 53000 59200 52700 59200 4 +N 53000 59600 52700 59600 4 +N 53000 57200 52200 57200 4 +N 52200 56800 52200 57300 4 +N 53000 56800 52200 56800 4 +N 70900 55600 71900 55600 4 +N 71900 55200 70600 55200 4 +C 71900 49200 1 0 0 connector16-2.sym +{ +T 72600 56100 5 10 1 1 0 6 1 +refdes=CONN? +T 72200 56050 5 10 0 0 0 0 1 +device=CONNECTOR_16 +T 72200 56250 5 10 0 0 0 0 1 +footprint=SIP16N +} +C 70700 55600 1 0 0 3.3V-plus-1.sym +C 70500 54900 1 0 0 gnd-1.sym +N 71900 54800 71000 54800 4 +{ +T 71000 54900 5 10 1 1 0 0 1 +netname=PDI_DATA +} +N 71900 54400 71000 54400 4 +{ +T 70600 54500 5 10 1 1 0 0 1 +netname=PDI_CLK_RESET +} +N 71900 54000 71000 54000 4 +{ +T 71000 54100 5 10 1 1 0 0 1 +netname=TMS_XMEGA +} +N 71900 53600 71000 53600 4 +{ +T 71000 53700 5 10 1 1 0 0 1 +netname=TDI_XMEGA +} +N 71900 53200 71000 53200 4 +{ +T 71000 53300 5 10 1 1 0 0 1 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