From: Harman Kalra <hkalra@marvell.com>
Date: Tue, 21 Sep 2021 11:00:38 +0000 (+0530)
Subject: common/cnxk: enable completion queue overflow errata
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=b21f07c94c5c63fc5b89484cdcfbbd36341a28d4;p=dpdk.git

common/cnxk: enable completion queue overflow errata

An issue exists on some HW revisions whereby if a CQ overflows
NIX may have undefined behavior, e.g. free incorrect buffers.
Implementing a workaround for this known HW issue.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
---

diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index b67f648e5a..b573879d47 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -17,7 +17,8 @@
 
 /* Apply BP/DROP when CQ is 95% full */
 #define NIX_CQ_THRESH_LEVEL	(5 * 256 / 100)
-#define NIX_RQ_AURA_THRESH(x)	(((x) * 95) / 100)
+#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
+#define NIX_RQ_AURA_THRESH(x)	(((x)*95) / 100)
 
 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
 #define CQ_CQE_THRESH_DEFAULT	0x1ULL
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 76e439e7a9..d7c4844d69 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -2,6 +2,8 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include <math.h>
+
 #include "roc_api.h"
 #include "roc_priv.h"
 
@@ -435,7 +437,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
 	cq->status = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS);
 	cq->wdata = (uint64_t)cq->qid << 32;
 	cq->roc_nix = roc_nix;
-	cq->drop_thresh = NIX_CQ_THRESH_LEVEL;
 
 	/* CQE of W16 */
 	desc_sz = cq->nb_desc * NIX_CQ_ENTRY_SZ;
@@ -476,8 +477,19 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
 	/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
 	cq_ctx->cint_idx = cq->qid;
 
-	cq_ctx->drop = cq->drop_thresh;
-	cq_ctx->drop_ena = 1;
+	if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
+		const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
+		uint16_t min_rx_drop;
+
+		min_rx_drop = ceil(rx_cq_skid / (float)cq->nb_desc);
+		cq_ctx->drop = min_rx_drop;
+		cq_ctx->drop_ena = 1;
+		cq->drop_thresh = min_rx_drop;
+	} else {
+		cq->drop_thresh = NIX_CQ_THRESH_LEVEL;
+		cq_ctx->drop = cq->drop_thresh;
+		cq_ctx->drop_ena = 1;
+	}
 
 	/* TX pause frames enable flow ctrl on RX side */
 	if (nix->tx_pause) {