From: Kishore Padmanabha Date: Mon, 20 Sep 2021 07:42:07 +0000 (+0530) Subject: net/bnxt: support tunnel offload X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=bdf4a3c6316b3e7b7a850efe5facf158cd658ee8;p=dpdk.git net/bnxt: support tunnel offload Add support for tunnel offload APIs. Specifically the following are supported. tunnel_decap_set, tunnel_match, tunnel_action_decap_release, tunnel_item_release. This provides support for VXLAN decap action where two flows can indicate tunnel offload rule. The first flow indicates the tunnel properties and second flow indicates the inner packet structure. The templates are updated to support this feature. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle Acked-by: Ajit Khaparde --- diff --git a/devtools/parse-flow-support.sh b/devtools/parse-flow-support.sh index 8462abe536..63c0b20e23 100755 --- a/devtools/parse-flow-support.sh +++ b/devtools/parse-flow-support.sh @@ -25,7 +25,8 @@ exclude() # $dir/tf_ulp/ulp_rte_handler_tbl.c | grep -wo "$1[[:alnum:]_]*" | sort -u | tr '\n' '|' | sed 's,.$,\n,') - grep -vE "$filter";; + exceptions='RTE_FLOW_ACTION_TYPE_SHARED' + grep -vE "$filter" | grep -vE $exceptions;; *) cat esac } diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index e0ebed3fed..6c4bcd2d90 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -37,9 +37,7 @@ enum bnxt_tf_rc { BNXT_TF_RC_PARSE_ERR = -2, BNXT_TF_RC_ERROR = -1, - BNXT_TF_RC_SUCCESS = 0, - BNXT_TF_RC_NORMAL = 1, - BNXT_TF_RC_FID = 2, + BNXT_TF_RC_SUCCESS = 0 }; /* eth IPv4 Type */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 475c7a6cdf..dfafd9ff5b 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp, if (rc) goto error_deinit; - ulp_tun_tbl_init(ulp_data->tun_tbl); - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); return rc; @@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void) { rte_spinlock_unlock(&bnxt_ulp_ctxt_lock); } + +/* Function to get the app tunnel details from the ulp context. */ +struct bnxt_flow_app_tun_ent * +bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp) +{ + if (!ulp || !ulp->cfg_data) + return NULL; + + return ulp->cfg_data->app_tun; +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 082ca501b6..006df9cbc5 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_LAST = 3 }; +enum bnxt_rte_flow_item_type { + BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN, + BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP, + BNXT_RTE_FLOW_ITEM_TYPE_LAST +}; + +enum bnxt_rte_flow_action_type { + BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN, + BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP, + BNXT_RTE_FLOW_ACTION_TYPE_LAST +}; + struct bnxt_ulp_df_rule_info { uint32_t def_port_flow_id; uint8_t valid; @@ -79,6 +91,7 @@ struct bnxt_ulp_data { bool accum_stats; uint8_t app_id; uint8_t num_shared_clients; + struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; }; struct bnxt_ulp_context { @@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx); void bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx); -int32_t -ulp_post_process_tun_flow(struct ulp_rte_parser_params *params); - struct bnxt_ulp_glb_resource_info * bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries); @@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void); uint8_t bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx); + +struct bnxt_flow_app_tun_ent * +bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp); + #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 238b1d9657..3daf5942e8 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -12,6 +12,7 @@ #include "ulp_fc_mgr.h" #include "ulp_port_db.h" #include "ulp_ha_mgr.h" +#include "ulp_tun.h" #include #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG #include "ulp_template_debug_proto.h" @@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, mapper_cparms->act_prop = ¶ms->act_prop; mapper_cparms->flow_id = params->fid; mapper_cparms->parent_flow = params->parent_flow; - mapper_cparms->parent_fid = params->parent_fid; + mapper_cparms->child_flow = params->child_flow; mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; mapper_cparms->flow_pattern_id = params->flow_pattern_id; mapper_cparms->act_pattern_id = params->act_pattern_id; mapper_cparms->app_id = params->app_id; mapper_cparms->port_id = params->port_id; + mapper_cparms->tun_idx = params->tun_idx; /* update the signature fields into the computed field list */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, @@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, params.func_id = func_id; params.priority = attr->priority; params.port_id = dev->data->port_id; + /* Perform the rte flow post process */ - ret = bnxt_ulp_rte_parser_post_process(¶ms); + bnxt_ulp_rte_parser_post_process(¶ms); + + /* do the tunnel offload process if any */ + ret = ulp_tunnel_offload_process(¶ms); if (ret == BNXT_TF_RC_ERROR) goto free_fid; - else if (ret == BNXT_TF_RC_FID) - goto return_fid; #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER @@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, if (ret) goto free_fid; -return_fid: bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); flow_id = (struct rte_flow *)((uintptr_t)fid); @@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev, goto parse_error; /* Perform the rte flow post process */ - ret = bnxt_ulp_rte_parser_post_process(¶ms); + bnxt_ulp_rte_parser_post_process(¶ms); + + /* do the tunnel offload process if any */ + ret = ulp_tunnel_offload_process(¶ms); if (ret == BNXT_TF_RC_ERROR) goto parse_error; - else if (ret == BNXT_TF_RC_FID) - return 0; ret = ulp_matcher_pattern_match(¶ms, &class_id); @@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev, return rc; } +/* Tunnel offload Apis */ +#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1 + +static int +bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev, + struct rte_flow_tunnel *tunnel, + struct rte_flow_action **pmd_actions, + uint32_t *num_of_actions, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + int32_t rc = 0; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + + if (tunnel == NULL) { + BNXT_TF_DBG(ERR, "No tunnel specified\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "no tunnel specified"); + return -EINVAL; + } + + if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) { + BNXT_TF_DBG(ERR, "Tunnel type unsupported\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel type unsupported"); + return -EINVAL; + } + + rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel decap set failed"); + return -EINVAL; + } + + rc = ulp_app_tun_entry_set_decap_action(tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel decap set failed"); + return -EINVAL; + } + + *pmd_actions = &tun_entry->action; + *num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS; + return 0; +} + +static int +bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev, + struct rte_flow_tunnel *tunnel, + struct rte_flow_item **pmd_items, + uint32_t *num_of_items, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + int32_t rc = 0; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + + if (tunnel == NULL) { + BNXT_TF_DBG(ERR, "No tunnel specified\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "no tunnel specified"); + return -EINVAL; + } + + if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) { + BNXT_TF_DBG(ERR, "Tunnel type unsupported\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "tunnel type unsupported"); + return -EINVAL; + } + + rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel match set failed"); + return -EINVAL; + } + + rc = ulp_app_tun_entry_set_decap_item(tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel match set failed"); + return -EINVAL; + } + + *pmd_items = &tun_entry->item; + *num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS; + return 0; +} + +static int +bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev, + struct rte_flow_action *pmd_actions, + uint32_t num_actions, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + const struct rte_flow_action *action_item = pmd_actions; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) { + BNXT_TF_DBG(ERR, "num actions is invalid\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "num actions is invalid"); + return -EINVAL; + } + while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { + if (action_item->type == (typeof(tun_entry->action.type)) + BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) { + tun_entry = ulp_app_tun_match_entry(ulp_ctx, + action_item->conf); + ulp_app_tun_entry_delete(tun_entry); + } + action_item++; + } + return 0; +} + +static int +bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev, + struct rte_flow_item *pmd_items, + uint32_t num_items, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) { + BNXT_TF_DBG(ERR, "num items is invalid\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "num items is invalid"); + return -EINVAL; + } + + tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec); + ulp_app_tun_entry_delete(tun_entry); + return 0; +} + const struct rte_flow_ops bnxt_ulp_rte_flow_ops = { .validate = bnxt_ulp_flow_validate, .create = bnxt_ulp_flow_create, .destroy = bnxt_ulp_flow_destroy, .flush = bnxt_ulp_flow_flush, .query = bnxt_ulp_flow_query, - .isolate = NULL + .isolate = NULL, + /* Tunnel offload callbacks */ + .tunnel_decap_set = bnxt_ulp_tunnel_decap_set, + .tunnel_match = bnxt_ulp_tunnel_match, + .tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release, + .tunnel_item_release = bnxt_ulp_tunnel_item_release, + .get_restore_info = NULL }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index e18f314856..0da6070d7d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Mon May 17 15:30:41 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index 9c419f6a15..f74687acfa 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { [BNXT_ULP_CLASS_HID_15db] = 342, [BNXT_ULP_CLASS_HID_1151] = 343, [BNXT_ULP_CLASS_HID_315d] = 344, - [BNXT_ULP_CLASS_HID_34c6] = 345, - [BNXT_ULP_CLASS_HID_0c22] = 346, - [BNXT_ULP_CLASS_HID_1cbe] = 347, - [BNXT_ULP_CLASS_HID_179a] = 348, - [BNXT_ULP_CLASS_HID_59be] = 349, - [BNXT_ULP_CLASS_HID_515a] = 350, - [BNXT_ULP_CLASS_HID_1c72] = 351, - [BNXT_ULP_CLASS_HID_171e] = 352, - [BNXT_ULP_CLASS_HID_19c8] = 353, - [BNXT_ULP_CLASS_HID_112c] = 354, - [BNXT_ULP_CLASS_HID_4d68] = 355, - [BNXT_ULP_CLASS_HID_444c] = 356, - [BNXT_ULP_CLASS_HID_0e8c] = 357, - [BNXT_ULP_CLASS_HID_09e0] = 358, - [BNXT_ULP_CLASS_HID_1af0] = 359, - [BNXT_ULP_CLASS_HID_15d4] = 360, - [BNXT_ULP_CLASS_HID_1dd0] = 361, - [BNXT_ULP_CLASS_HID_14f4] = 362, - [BNXT_ULP_CLASS_HID_70b0] = 363, - [BNXT_ULP_CLASS_HID_4854] = 364, - [BNXT_ULP_CLASS_HID_3dd4] = 365, - [BNXT_ULP_CLASS_HID_34f8] = 366, - [BNXT_ULP_CLASS_HID_09e8] = 367, - [BNXT_ULP_CLASS_HID_008c] = 368, - [BNXT_ULP_CLASS_HID_34e6] = 369, - [BNXT_ULP_CLASS_HID_0c02] = 370, - [BNXT_ULP_CLASS_HID_1c9e] = 371, - [BNXT_ULP_CLASS_HID_17ba] = 372, - [BNXT_ULP_CLASS_HID_429e] = 373, - [BNXT_ULP_CLASS_HID_5dba] = 374, - [BNXT_ULP_CLASS_HID_2a16] = 375, - [BNXT_ULP_CLASS_HID_2532] = 376, - [BNXT_ULP_CLASS_HID_2da2] = 377, - [BNXT_ULP_CLASS_HID_24fe] = 378, - [BNXT_ULP_CLASS_HID_355a] = 379, - [BNXT_ULP_CLASS_HID_0c76] = 380, - [BNXT_ULP_CLASS_HID_13e6] = 381, - [BNXT_ULP_CLASS_HID_7276] = 382, - [BNXT_ULP_CLASS_HID_42d2] = 383, - [BNXT_ULP_CLASS_HID_5dee] = 384, - [BNXT_ULP_CLASS_HID_59de] = 385, - [BNXT_ULP_CLASS_HID_513a] = 386, - [BNXT_ULP_CLASS_HID_1c12] = 387, - [BNXT_ULP_CLASS_HID_177e] = 388, - [BNXT_ULP_CLASS_HID_0e92] = 389, - [BNXT_ULP_CLASS_HID_09fe] = 390, - [BNXT_ULP_CLASS_HID_5c1a] = 391, - [BNXT_ULP_CLASS_HID_5746] = 392, - [BNXT_ULP_CLASS_HID_79da] = 393, - [BNXT_ULP_CLASS_HID_7106] = 394, - [BNXT_ULP_CLASS_HID_3c1e] = 395, - [BNXT_ULP_CLASS_HID_377a] = 396, - [BNXT_ULP_CLASS_HID_2e9e] = 397, - [BNXT_ULP_CLASS_HID_29fa] = 398, - [BNXT_ULP_CLASS_HID_14d2] = 399, - [BNXT_ULP_CLASS_HID_7742] = 400, - [BNXT_ULP_CLASS_HID_3706] = 401, - [BNXT_ULP_CLASS_HID_0fe2] = 402, - [BNXT_ULP_CLASS_HID_1f7e] = 403, - [BNXT_ULP_CLASS_HID_145a] = 404, - [BNXT_ULP_CLASS_HID_417e] = 405, - [BNXT_ULP_CLASS_HID_5e5a] = 406, - [BNXT_ULP_CLASS_HID_29f6] = 407, - [BNXT_ULP_CLASS_HID_26d2] = 408, - [BNXT_ULP_CLASS_HID_2e42] = 409, - [BNXT_ULP_CLASS_HID_271e] = 410, - [BNXT_ULP_CLASS_HID_36ba] = 411, - [BNXT_ULP_CLASS_HID_0f96] = 412, - [BNXT_ULP_CLASS_HID_1006] = 413, - [BNXT_ULP_CLASS_HID_7196] = 414, - [BNXT_ULP_CLASS_HID_4132] = 415, - [BNXT_ULP_CLASS_HID_5e0e] = 416, - [BNXT_ULP_CLASS_HID_59fe] = 417, - [BNXT_ULP_CLASS_HID_511a] = 418, - [BNXT_ULP_CLASS_HID_1c32] = 419, - [BNXT_ULP_CLASS_HID_175e] = 420, - [BNXT_ULP_CLASS_HID_0eb2] = 421, - [BNXT_ULP_CLASS_HID_09de] = 422, - [BNXT_ULP_CLASS_HID_5c3a] = 423, - [BNXT_ULP_CLASS_HID_5766] = 424, - [BNXT_ULP_CLASS_HID_79fa] = 425, - [BNXT_ULP_CLASS_HID_7126] = 426, - [BNXT_ULP_CLASS_HID_3c3e] = 427, - [BNXT_ULP_CLASS_HID_375a] = 428, - [BNXT_ULP_CLASS_HID_2ebe] = 429, - [BNXT_ULP_CLASS_HID_29da] = 430, - [BNXT_ULP_CLASS_HID_14f2] = 431, - [BNXT_ULP_CLASS_HID_7762] = 432, - [BNXT_ULP_CLASS_HID_19e8] = 433, - [BNXT_ULP_CLASS_HID_110c] = 434, - [BNXT_ULP_CLASS_HID_4d48] = 435, - [BNXT_ULP_CLASS_HID_446c] = 436, - [BNXT_ULP_CLASS_HID_0eac] = 437, - [BNXT_ULP_CLASS_HID_09c0] = 438, - [BNXT_ULP_CLASS_HID_1ad0] = 439, - [BNXT_ULP_CLASS_HID_15f4] = 440, - [BNXT_ULP_CLASS_HID_39ec] = 441, - [BNXT_ULP_CLASS_HID_3100] = 442, - [BNXT_ULP_CLASS_HID_0210] = 443, - [BNXT_ULP_CLASS_HID_1d34] = 444, - [BNXT_ULP_CLASS_HID_2ea0] = 445, - [BNXT_ULP_CLASS_HID_29c4] = 446, - [BNXT_ULP_CLASS_HID_3ad4] = 447, - [BNXT_ULP_CLASS_HID_35e8] = 448, - [BNXT_ULP_CLASS_HID_5d80] = 449, - [BNXT_ULP_CLASS_HID_54a4] = 450, - [BNXT_ULP_CLASS_HID_29b4] = 451, - [BNXT_ULP_CLASS_HID_20c8] = 452, - [BNXT_ULP_CLASS_HID_7244] = 453, - [BNXT_ULP_CLASS_HID_4d98] = 454, - [BNXT_ULP_CLASS_HID_5e68] = 455, - [BNXT_ULP_CLASS_HID_598c] = 456, - [BNXT_ULP_CLASS_HID_1248] = 457, - [BNXT_ULP_CLASS_HID_74d8] = 458, - [BNXT_ULP_CLASS_HID_49a8] = 459, - [BNXT_ULP_CLASS_HID_40cc] = 460, - [BNXT_ULP_CLASS_HID_0b0c] = 461, - [BNXT_ULP_CLASS_HID_0220] = 462, - [BNXT_ULP_CLASS_HID_1730] = 463, - [BNXT_ULP_CLASS_HID_7980] = 464, - [BNXT_ULP_CLASS_HID_1db0] = 465, - [BNXT_ULP_CLASS_HID_1494] = 466, - [BNXT_ULP_CLASS_HID_70d0] = 467, - [BNXT_ULP_CLASS_HID_4834] = 468, - [BNXT_ULP_CLASS_HID_3db4] = 469, - [BNXT_ULP_CLASS_HID_3498] = 470, - [BNXT_ULP_CLASS_HID_0988] = 471, - [BNXT_ULP_CLASS_HID_00ec] = 472, - [BNXT_ULP_CLASS_HID_3f44] = 473, - [BNXT_ULP_CLASS_HID_36a8] = 474, - [BNXT_ULP_CLASS_HID_0b58] = 475, - [BNXT_ULP_CLASS_HID_02bc] = 476, - [BNXT_ULP_CLASS_HID_5f48] = 477, - [BNXT_ULP_CLASS_HID_56ac] = 478, - [BNXT_ULP_CLASS_HID_2b5c] = 479, - [BNXT_ULP_CLASS_HID_2280] = 480, - [BNXT_ULP_CLASS_HID_4000] = 481, - [BNXT_ULP_CLASS_HID_5b64] = 482, - [BNXT_ULP_CLASS_HID_2c14] = 483, - [BNXT_ULP_CLASS_HID_2778] = 484, - [BNXT_ULP_CLASS_HID_18f8] = 485, - [BNXT_ULP_CLASS_HID_13dc] = 486, - [BNXT_ULP_CLASS_HID_4c18] = 487, - [BNXT_ULP_CLASS_HID_477c] = 488, - [BNXT_ULP_CLASS_HID_1a88] = 489, - [BNXT_ULP_CLASS_HID_15ec] = 490, - [BNXT_ULP_CLASS_HID_4e28] = 491, - [BNXT_ULP_CLASS_HID_490c] = 492, - [BNXT_ULP_CLASS_HID_3a8c] = 493, - [BNXT_ULP_CLASS_HID_35f0] = 494, - [BNXT_ULP_CLASS_HID_06e0] = 495, - [BNXT_ULP_CLASS_HID_01c4] = 496, - [BNXT_ULP_CLASS_HID_1a08] = 497, - [BNXT_ULP_CLASS_HID_12ec] = 498, - [BNXT_ULP_CLASS_HID_4ea8] = 499, - [BNXT_ULP_CLASS_HID_478c] = 500, - [BNXT_ULP_CLASS_HID_0d4c] = 501, - [BNXT_ULP_CLASS_HID_0a20] = 502, - [BNXT_ULP_CLASS_HID_1930] = 503, - [BNXT_ULP_CLASS_HID_1614] = 504, - [BNXT_ULP_CLASS_HID_3a0c] = 505, - [BNXT_ULP_CLASS_HID_32e0] = 506, - [BNXT_ULP_CLASS_HID_01f0] = 507, - [BNXT_ULP_CLASS_HID_1ed4] = 508, - [BNXT_ULP_CLASS_HID_2d40] = 509, - [BNXT_ULP_CLASS_HID_2a24] = 510, - [BNXT_ULP_CLASS_HID_3934] = 511, - [BNXT_ULP_CLASS_HID_3608] = 512, - [BNXT_ULP_CLASS_HID_5e60] = 513, - [BNXT_ULP_CLASS_HID_5744] = 514, - [BNXT_ULP_CLASS_HID_2a54] = 515, - [BNXT_ULP_CLASS_HID_2328] = 516, - [BNXT_ULP_CLASS_HID_71a4] = 517, - [BNXT_ULP_CLASS_HID_4e78] = 518, - [BNXT_ULP_CLASS_HID_5d88] = 519, - [BNXT_ULP_CLASS_HID_5a6c] = 520, - [BNXT_ULP_CLASS_HID_11a8] = 521, - [BNXT_ULP_CLASS_HID_7738] = 522, - [BNXT_ULP_CLASS_HID_4a48] = 523, - [BNXT_ULP_CLASS_HID_432c] = 524, - [BNXT_ULP_CLASS_HID_08ec] = 525, - [BNXT_ULP_CLASS_HID_01c0] = 526, - [BNXT_ULP_CLASS_HID_14d0] = 527, - [BNXT_ULP_CLASS_HID_7a60] = 528, - [BNXT_ULP_CLASS_HID_1d90] = 529, - [BNXT_ULP_CLASS_HID_14b4] = 530, - [BNXT_ULP_CLASS_HID_70f0] = 531, - [BNXT_ULP_CLASS_HID_4814] = 532, - [BNXT_ULP_CLASS_HID_3d94] = 533, - [BNXT_ULP_CLASS_HID_34b8] = 534, - [BNXT_ULP_CLASS_HID_09a8] = 535, - [BNXT_ULP_CLASS_HID_00cc] = 536, - [BNXT_ULP_CLASS_HID_3f64] = 537, - [BNXT_ULP_CLASS_HID_3688] = 538, - [BNXT_ULP_CLASS_HID_0b78] = 539, - [BNXT_ULP_CLASS_HID_029c] = 540, - [BNXT_ULP_CLASS_HID_5f68] = 541, - [BNXT_ULP_CLASS_HID_568c] = 542, - [BNXT_ULP_CLASS_HID_2b7c] = 543, - [BNXT_ULP_CLASS_HID_22a0] = 544, - [BNXT_ULP_CLASS_HID_4020] = 545, - [BNXT_ULP_CLASS_HID_5b44] = 546, - [BNXT_ULP_CLASS_HID_2c34] = 547, - [BNXT_ULP_CLASS_HID_2758] = 548, - [BNXT_ULP_CLASS_HID_18d8] = 549, - [BNXT_ULP_CLASS_HID_13fc] = 550, - [BNXT_ULP_CLASS_HID_4c38] = 551, - [BNXT_ULP_CLASS_HID_475c] = 552, - [BNXT_ULP_CLASS_HID_1aa8] = 553, - [BNXT_ULP_CLASS_HID_15cc] = 554, - [BNXT_ULP_CLASS_HID_4e08] = 555, - [BNXT_ULP_CLASS_HID_492c] = 556, - [BNXT_ULP_CLASS_HID_3aac] = 557, - [BNXT_ULP_CLASS_HID_35d0] = 558, - [BNXT_ULP_CLASS_HID_06c0] = 559, - [BNXT_ULP_CLASS_HID_01e4] = 560, - [BNXT_ULP_CLASS_HID_4d32] = 561, - [BNXT_ULP_CLASS_HID_54aa] = 562, - [BNXT_ULP_CLASS_HID_0686] = 563, - [BNXT_ULP_CLASS_HID_540e] = 564, - [BNXT_ULP_CLASS_HID_2e3c] = 565, - [BNXT_ULP_CLASS_HID_3a20] = 566, - [BNXT_ULP_CLASS_HID_46f0] = 567, - [BNXT_ULP_CLASS_HID_52e4] = 568, - [BNXT_ULP_CLASS_HID_55e4] = 569, - [BNXT_ULP_CLASS_HID_21f8] = 570, - [BNXT_ULP_CLASS_HID_75e8] = 571, - [BNXT_ULP_CLASS_HID_41fc] = 572, - [BNXT_ULP_CLASS_HID_4d12] = 573, - [BNXT_ULP_CLASS_HID_548a] = 574, - [BNXT_ULP_CLASS_HID_3356] = 575, - [BNXT_ULP_CLASS_HID_1ace] = 576, - [BNXT_ULP_CLASS_HID_1a9a] = 577, - [BNXT_ULP_CLASS_HID_4d46] = 578, - [BNXT_ULP_CLASS_HID_2812] = 579, - [BNXT_ULP_CLASS_HID_338a] = 580, - [BNXT_ULP_CLASS_HID_06e6] = 581, - [BNXT_ULP_CLASS_HID_546e] = 582, - [BNXT_ULP_CLASS_HID_46ee] = 583, - [BNXT_ULP_CLASS_HID_0d22] = 584, - [BNXT_ULP_CLASS_HID_26e2] = 585, - [BNXT_ULP_CLASS_HID_746a] = 586, - [BNXT_ULP_CLASS_HID_1fa6] = 587, - [BNXT_ULP_CLASS_HID_2d2e] = 588, - [BNXT_ULP_CLASS_HID_4ef2] = 589, - [BNXT_ULP_CLASS_HID_576a] = 590, - [BNXT_ULP_CLASS_HID_30b6] = 591, - [BNXT_ULP_CLASS_HID_192e] = 592, - [BNXT_ULP_CLASS_HID_197a] = 593, - [BNXT_ULP_CLASS_HID_4ea6] = 594, - [BNXT_ULP_CLASS_HID_2bf2] = 595, - [BNXT_ULP_CLASS_HID_306a] = 596, - [BNXT_ULP_CLASS_HID_06c6] = 597, - [BNXT_ULP_CLASS_HID_544e] = 598, - [BNXT_ULP_CLASS_HID_46ce] = 599, - [BNXT_ULP_CLASS_HID_0d02] = 600, - [BNXT_ULP_CLASS_HID_26c2] = 601, - [BNXT_ULP_CLASS_HID_744a] = 602, - [BNXT_ULP_CLASS_HID_1f86] = 603, - [BNXT_ULP_CLASS_HID_2d0e] = 604, - [BNXT_ULP_CLASS_HID_2e1c] = 605, - [BNXT_ULP_CLASS_HID_3a00] = 606, - [BNXT_ULP_CLASS_HID_46d0] = 607, - [BNXT_ULP_CLASS_HID_52c4] = 608, - [BNXT_ULP_CLASS_HID_4e10] = 609, - [BNXT_ULP_CLASS_HID_5a04] = 610, - [BNXT_ULP_CLASS_HID_1f98] = 611, - [BNXT_ULP_CLASS_HID_72f8] = 612, - [BNXT_ULP_CLASS_HID_0a78] = 613, - [BNXT_ULP_CLASS_HID_166c] = 614, - [BNXT_ULP_CLASS_HID_233c] = 615, - [BNXT_ULP_CLASS_HID_0f20] = 616, - [BNXT_ULP_CLASS_HID_2a7c] = 617, - [BNXT_ULP_CLASS_HID_3660] = 618, - [BNXT_ULP_CLASS_HID_4330] = 619, - [BNXT_ULP_CLASS_HID_2f24] = 620, - [BNXT_ULP_CLASS_HID_5584] = 621, - [BNXT_ULP_CLASS_HID_2198] = 622, - [BNXT_ULP_CLASS_HID_7588] = 623, - [BNXT_ULP_CLASS_HID_419c] = 624, - [BNXT_ULP_CLASS_HID_7758] = 625, - [BNXT_ULP_CLASS_HID_43ac] = 626, - [BNXT_ULP_CLASS_HID_0c10] = 627, - [BNXT_ULP_CLASS_HID_1864] = 628, - [BNXT_ULP_CLASS_HID_30c8] = 629, - [BNXT_ULP_CLASS_HID_1cdc] = 630, - [BNXT_ULP_CLASS_HID_50cc] = 631, - [BNXT_ULP_CLASS_HID_3d20] = 632, - [BNXT_ULP_CLASS_HID_529c] = 633, - [BNXT_ULP_CLASS_HID_3ef0] = 634, - [BNXT_ULP_CLASS_HID_72e0] = 635, - [BNXT_ULP_CLASS_HID_5ef4] = 636, - [BNXT_ULP_CLASS_HID_2dfc] = 637, - [BNXT_ULP_CLASS_HID_39e0] = 638, - [BNXT_ULP_CLASS_HID_4530] = 639, - [BNXT_ULP_CLASS_HID_5124] = 640, - [BNXT_ULP_CLASS_HID_4df0] = 641, - [BNXT_ULP_CLASS_HID_59e4] = 642, - [BNXT_ULP_CLASS_HID_1c78] = 643, - [BNXT_ULP_CLASS_HID_7118] = 644, - [BNXT_ULP_CLASS_HID_0998] = 645, - [BNXT_ULP_CLASS_HID_158c] = 646, - [BNXT_ULP_CLASS_HID_20dc] = 647, - [BNXT_ULP_CLASS_HID_0cc0] = 648, - [BNXT_ULP_CLASS_HID_299c] = 649, - [BNXT_ULP_CLASS_HID_3580] = 650, - [BNXT_ULP_CLASS_HID_40d0] = 651, - [BNXT_ULP_CLASS_HID_2cc4] = 652, - [BNXT_ULP_CLASS_HID_55a4] = 653, - [BNXT_ULP_CLASS_HID_21b8] = 654, - [BNXT_ULP_CLASS_HID_75a8] = 655, - [BNXT_ULP_CLASS_HID_41bc] = 656, - [BNXT_ULP_CLASS_HID_7778] = 657, - [BNXT_ULP_CLASS_HID_438c] = 658, - [BNXT_ULP_CLASS_HID_0c30] = 659, - [BNXT_ULP_CLASS_HID_1844] = 660, - [BNXT_ULP_CLASS_HID_30e8] = 661, - [BNXT_ULP_CLASS_HID_1cfc] = 662, - [BNXT_ULP_CLASS_HID_50ec] = 663, - [BNXT_ULP_CLASS_HID_3d00] = 664, - [BNXT_ULP_CLASS_HID_52bc] = 665, - [BNXT_ULP_CLASS_HID_3ed0] = 666, - [BNXT_ULP_CLASS_HID_72c0] = 667, - [BNXT_ULP_CLASS_HID_5ed4] = 668, - [BNXT_ULP_CLASS_HID_3866] = 669, - [BNXT_ULP_CLASS_HID_381e] = 670, - [BNXT_ULP_CLASS_HID_3860] = 671, - [BNXT_ULP_CLASS_HID_0454] = 672, - [BNXT_ULP_CLASS_HID_3818] = 673, - [BNXT_ULP_CLASS_HID_042c] = 674, - [BNXT_ULP_CLASS_HID_3846] = 675, - [BNXT_ULP_CLASS_HID_387e] = 676, - [BNXT_ULP_CLASS_HID_3ba6] = 677, - [BNXT_ULP_CLASS_HID_385e] = 678, - [BNXT_ULP_CLASS_HID_3840] = 679, - [BNXT_ULP_CLASS_HID_0474] = 680, - [BNXT_ULP_CLASS_HID_3878] = 681, - [BNXT_ULP_CLASS_HID_044c] = 682, - [BNXT_ULP_CLASS_HID_3ba0] = 683, - [BNXT_ULP_CLASS_HID_0794] = 684, - [BNXT_ULP_CLASS_HID_3858] = 685, - [BNXT_ULP_CLASS_HID_046c] = 686 + [BNXT_ULP_CLASS_HID_3612] = 345, + [BNXT_ULP_CLASS_HID_66da] = 346, + [BNXT_ULP_CLASS_HID_6165] = 347, + [BNXT_ULP_CLASS_HID_2aa1] = 348, + [BNXT_ULP_CLASS_HID_09cd] = 349, + [BNXT_ULP_CLASS_HID_3845] = 350, + [BNXT_ULP_CLASS_HID_11e9] = 351, + [BNXT_ULP_CLASS_HID_4361] = 352, + [BNXT_ULP_CLASS_HID_218d] = 353, + [BNXT_ULP_CLASS_HID_5105] = 354, + [BNXT_ULP_CLASS_HID_0c89] = 355, + [BNXT_ULP_CLASS_HID_3e81] = 356, + [BNXT_ULP_CLASS_HID_1dad] = 357, + [BNXT_ULP_CLASS_HID_4ca5] = 358, + [BNXT_ULP_CLASS_HID_25c9] = 359, + [BNXT_ULP_CLASS_HID_57c1] = 360, + [BNXT_ULP_CLASS_HID_33ed] = 361, + [BNXT_ULP_CLASS_HID_65e5] = 362, + [BNXT_ULP_CLASS_HID_6dd9] = 363, + [BNXT_ULP_CLASS_HID_261d] = 364, + [BNXT_ULP_CLASS_HID_0571] = 365, + [BNXT_ULP_CLASS_HID_34f9] = 366, + [BNXT_ULP_CLASS_HID_1d55] = 367, + [BNXT_ULP_CLASS_HID_4fdd] = 368, + [BNXT_ULP_CLASS_HID_2d31] = 369, + [BNXT_ULP_CLASS_HID_5db9] = 370, + [BNXT_ULP_CLASS_HID_0035] = 371, + [BNXT_ULP_CLASS_HID_323d] = 372, + [BNXT_ULP_CLASS_HID_1111] = 373, + [BNXT_ULP_CLASS_HID_4019] = 374, + [BNXT_ULP_CLASS_HID_2975] = 375, + [BNXT_ULP_CLASS_HID_5b7d] = 376, + [BNXT_ULP_CLASS_HID_3f51] = 377, + [BNXT_ULP_CLASS_HID_6959] = 378, + [BNXT_ULP_CLASS_HID_0e85] = 379, + [BNXT_ULP_CLASS_HID_380d] = 380, + [BNXT_ULP_CLASS_HID_1f21] = 381, + [BNXT_ULP_CLASS_HID_4ea9] = 382, + [BNXT_ULP_CLASS_HID_1705] = 383, + [BNXT_ULP_CLASS_HID_418d] = 384, + [BNXT_ULP_CLASS_HID_2721] = 385, + [BNXT_ULP_CLASS_HID_57a9] = 386, + [BNXT_ULP_CLASS_HID_1a25] = 387, + [BNXT_ULP_CLASS_HID_342d] = 388, + [BNXT_ULP_CLASS_HID_2b01] = 389, + [BNXT_ULP_CLASS_HID_5a09] = 390, + [BNXT_ULP_CLASS_HID_2325] = 391, + [BNXT_ULP_CLASS_HID_5d2d] = 392, + [BNXT_ULP_CLASS_HID_3101] = 393, + [BNXT_ULP_CLASS_HID_6309] = 394, + [BNXT_ULP_CLASS_HID_0bad] = 395, + [BNXT_ULP_CLASS_HID_2535] = 396, + [BNXT_ULP_CLASS_HID_1869] = 397, + [BNXT_ULP_CLASS_HID_4bf1] = 398, + [BNXT_ULP_CLASS_HID_136d] = 399, + [BNXT_ULP_CLASS_HID_43f5] = 400, + [BNXT_ULP_CLASS_HID_2129] = 401, + [BNXT_ULP_CLASS_HID_53b1] = 402, + [BNXT_ULP_CLASS_HID_072d] = 403, + [BNXT_ULP_CLASS_HID_3135] = 404, + [BNXT_ULP_CLASS_HID_1429] = 405, + [BNXT_ULP_CLASS_HID_4731] = 406, + [BNXT_ULP_CLASS_HID_2f6d] = 407, + [BNXT_ULP_CLASS_HID_5f75] = 408, + [BNXT_ULP_CLASS_HID_3d69] = 409, + [BNXT_ULP_CLASS_HID_6f71] = 410, + [BNXT_ULP_CLASS_HID_0dbd] = 411, + [BNXT_ULP_CLASS_HID_3f25] = 412, + [BNXT_ULP_CLASS_HID_1239] = 413, + [BNXT_ULP_CLASS_HID_4da1] = 414, + [BNXT_ULP_CLASS_HID_153d] = 415, + [BNXT_ULP_CLASS_HID_45a5] = 416, + [BNXT_ULP_CLASS_HID_3bb9] = 417, + [BNXT_ULP_CLASS_HID_55a1] = 418, + [BNXT_ULP_CLASS_HID_193d] = 419, + [BNXT_ULP_CLASS_HID_4b25] = 420, + [BNXT_ULP_CLASS_HID_2e39] = 421, + [BNXT_ULP_CLASS_HID_5921] = 422, + [BNXT_ULP_CLASS_HID_213d] = 423, + [BNXT_ULP_CLASS_HID_5125] = 424, + [BNXT_ULP_CLASS_HID_3739] = 425, + [BNXT_ULP_CLASS_HID_093d] = 426, + [BNXT_ULP_CLASS_HID_684d] = 427, + [BNXT_ULP_CLASS_HID_2389] = 428, + [BNXT_ULP_CLASS_HID_00e5] = 429, + [BNXT_ULP_CLASS_HID_316d] = 430, + [BNXT_ULP_CLASS_HID_18c1] = 431, + [BNXT_ULP_CLASS_HID_4a49] = 432, + [BNXT_ULP_CLASS_HID_28a5] = 433, + [BNXT_ULP_CLASS_HID_582d] = 434, + [BNXT_ULP_CLASS_HID_05a1] = 435, + [BNXT_ULP_CLASS_HID_37a9] = 436, + [BNXT_ULP_CLASS_HID_1485] = 437, + [BNXT_ULP_CLASS_HID_458d] = 438, + [BNXT_ULP_CLASS_HID_2ce1] = 439, + [BNXT_ULP_CLASS_HID_5ee9] = 440, + [BNXT_ULP_CLASS_HID_3ac5] = 441, + [BNXT_ULP_CLASS_HID_6ccd] = 442, + [BNXT_ULP_CLASS_HID_0b11] = 443, + [BNXT_ULP_CLASS_HID_3d99] = 444, + [BNXT_ULP_CLASS_HID_1ab5] = 445, + [BNXT_ULP_CLASS_HID_4b3d] = 446, + [BNXT_ULP_CLASS_HID_1291] = 447, + [BNXT_ULP_CLASS_HID_4419] = 448, + [BNXT_ULP_CLASS_HID_22b5] = 449, + [BNXT_ULP_CLASS_HID_523d] = 450, + [BNXT_ULP_CLASS_HID_1fb1] = 451, + [BNXT_ULP_CLASS_HID_31b9] = 452, + [BNXT_ULP_CLASS_HID_2e95] = 453, + [BNXT_ULP_CLASS_HID_5f9d] = 454, + [BNXT_ULP_CLASS_HID_26b1] = 455, + [BNXT_ULP_CLASS_HID_58b9] = 456, + [BNXT_ULP_CLASS_HID_3495] = 457, + [BNXT_ULP_CLASS_HID_669d] = 458, + [BNXT_ULP_CLASS_HID_0e39] = 459, + [BNXT_ULP_CLASS_HID_20a1] = 460, + [BNXT_ULP_CLASS_HID_1dfd] = 461, + [BNXT_ULP_CLASS_HID_4e65] = 462, + [BNXT_ULP_CLASS_HID_16f9] = 463, + [BNXT_ULP_CLASS_HID_4661] = 464, + [BNXT_ULP_CLASS_HID_24bd] = 465, + [BNXT_ULP_CLASS_HID_5625] = 466, + [BNXT_ULP_CLASS_HID_02b9] = 467, + [BNXT_ULP_CLASS_HID_34a1] = 468, + [BNXT_ULP_CLASS_HID_11bd] = 469, + [BNXT_ULP_CLASS_HID_42a5] = 470, + [BNXT_ULP_CLASS_HID_2af9] = 471, + [BNXT_ULP_CLASS_HID_5ae1] = 472, + [BNXT_ULP_CLASS_HID_38fd] = 473, + [BNXT_ULP_CLASS_HID_6ae5] = 474, + [BNXT_ULP_CLASS_HID_0829] = 475, + [BNXT_ULP_CLASS_HID_3ab1] = 476, + [BNXT_ULP_CLASS_HID_17ad] = 477, + [BNXT_ULP_CLASS_HID_4835] = 478, + [BNXT_ULP_CLASS_HID_10a9] = 479, + [BNXT_ULP_CLASS_HID_4031] = 480, + [BNXT_ULP_CLASS_HID_3e2d] = 481, + [BNXT_ULP_CLASS_HID_5035] = 482, + [BNXT_ULP_CLASS_HID_1ca9] = 483, + [BNXT_ULP_CLASS_HID_4eb1] = 484, + [BNXT_ULP_CLASS_HID_2bad] = 485, + [BNXT_ULP_CLASS_HID_5cb5] = 486, + [BNXT_ULP_CLASS_HID_24a9] = 487, + [BNXT_ULP_CLASS_HID_54b1] = 488, + [BNXT_ULP_CLASS_HID_32ad] = 489, + [BNXT_ULP_CLASS_HID_0ca9] = 490, + [BNXT_ULP_CLASS_HID_7f35] = 491, + [BNXT_ULP_CLASS_HID_34f1] = 492, + [BNXT_ULP_CLASS_HID_179d] = 493, + [BNXT_ULP_CLASS_HID_2615] = 494, + [BNXT_ULP_CLASS_HID_0fb9] = 495, + [BNXT_ULP_CLASS_HID_5d31] = 496, + [BNXT_ULP_CLASS_HID_3fdd] = 497, + [BNXT_ULP_CLASS_HID_4f55] = 498, + [BNXT_ULP_CLASS_HID_12d9] = 499, + [BNXT_ULP_CLASS_HID_20d1] = 500, + [BNXT_ULP_CLASS_HID_03fd] = 501, + [BNXT_ULP_CLASS_HID_52f5] = 502, + [BNXT_ULP_CLASS_HID_3b99] = 503, + [BNXT_ULP_CLASS_HID_4991] = 504, + [BNXT_ULP_CLASS_HID_2dbd] = 505, + [BNXT_ULP_CLASS_HID_7bb5] = 506, + [BNXT_ULP_CLASS_HID_34c6] = 507, + [BNXT_ULP_CLASS_HID_0c22] = 508, + [BNXT_ULP_CLASS_HID_1cbe] = 509, + [BNXT_ULP_CLASS_HID_179a] = 510, + [BNXT_ULP_CLASS_HID_59be] = 511, + [BNXT_ULP_CLASS_HID_515a] = 512, + [BNXT_ULP_CLASS_HID_1c72] = 513, + [BNXT_ULP_CLASS_HID_171e] = 514, + [BNXT_ULP_CLASS_HID_19c8] = 515, + [BNXT_ULP_CLASS_HID_112c] = 516, + [BNXT_ULP_CLASS_HID_4d68] = 517, + [BNXT_ULP_CLASS_HID_444c] = 518, + [BNXT_ULP_CLASS_HID_0e8c] = 519, + [BNXT_ULP_CLASS_HID_09e0] = 520, + [BNXT_ULP_CLASS_HID_1af0] = 521, + [BNXT_ULP_CLASS_HID_15d4] = 522, + [BNXT_ULP_CLASS_HID_1dd0] = 523, + [BNXT_ULP_CLASS_HID_14f4] = 524, + [BNXT_ULP_CLASS_HID_70b0] = 525, + [BNXT_ULP_CLASS_HID_4854] = 526, + [BNXT_ULP_CLASS_HID_3dd4] = 527, + [BNXT_ULP_CLASS_HID_34f8] = 528, + [BNXT_ULP_CLASS_HID_09e8] = 529, + [BNXT_ULP_CLASS_HID_008c] = 530, + [BNXT_ULP_CLASS_HID_34e6] = 531, + [BNXT_ULP_CLASS_HID_0c02] = 532, + [BNXT_ULP_CLASS_HID_1c9e] = 533, + [BNXT_ULP_CLASS_HID_17ba] = 534, + [BNXT_ULP_CLASS_HID_429e] = 535, + [BNXT_ULP_CLASS_HID_5dba] = 536, + [BNXT_ULP_CLASS_HID_2a16] = 537, + [BNXT_ULP_CLASS_HID_2532] = 538, + [BNXT_ULP_CLASS_HID_2da2] = 539, + [BNXT_ULP_CLASS_HID_24fe] = 540, + [BNXT_ULP_CLASS_HID_355a] = 541, + [BNXT_ULP_CLASS_HID_0c76] = 542, + [BNXT_ULP_CLASS_HID_13e6] = 543, + [BNXT_ULP_CLASS_HID_7276] = 544, + [BNXT_ULP_CLASS_HID_42d2] = 545, + [BNXT_ULP_CLASS_HID_5dee] = 546, + [BNXT_ULP_CLASS_HID_59de] = 547, + [BNXT_ULP_CLASS_HID_513a] = 548, + [BNXT_ULP_CLASS_HID_1c12] = 549, + [BNXT_ULP_CLASS_HID_177e] = 550, + [BNXT_ULP_CLASS_HID_0e92] = 551, + [BNXT_ULP_CLASS_HID_09fe] = 552, + [BNXT_ULP_CLASS_HID_5c1a] = 553, + [BNXT_ULP_CLASS_HID_5746] = 554, + [BNXT_ULP_CLASS_HID_79da] = 555, + [BNXT_ULP_CLASS_HID_7106] = 556, + [BNXT_ULP_CLASS_HID_3c1e] = 557, + [BNXT_ULP_CLASS_HID_377a] = 558, + [BNXT_ULP_CLASS_HID_2e9e] = 559, + [BNXT_ULP_CLASS_HID_29fa] = 560, + [BNXT_ULP_CLASS_HID_14d2] = 561, + [BNXT_ULP_CLASS_HID_7742] = 562, + [BNXT_ULP_CLASS_HID_3706] = 563, + [BNXT_ULP_CLASS_HID_0fe2] = 564, + [BNXT_ULP_CLASS_HID_1f7e] = 565, + [BNXT_ULP_CLASS_HID_145a] = 566, + [BNXT_ULP_CLASS_HID_417e] = 567, + [BNXT_ULP_CLASS_HID_5e5a] = 568, + [BNXT_ULP_CLASS_HID_29f6] = 569, + [BNXT_ULP_CLASS_HID_26d2] = 570, + [BNXT_ULP_CLASS_HID_2e42] = 571, + [BNXT_ULP_CLASS_HID_271e] = 572, + [BNXT_ULP_CLASS_HID_36ba] = 573, + [BNXT_ULP_CLASS_HID_0f96] = 574, + [BNXT_ULP_CLASS_HID_1006] = 575, + [BNXT_ULP_CLASS_HID_7196] = 576, + [BNXT_ULP_CLASS_HID_4132] = 577, + [BNXT_ULP_CLASS_HID_5e0e] = 578, + [BNXT_ULP_CLASS_HID_59fe] = 579, + [BNXT_ULP_CLASS_HID_511a] = 580, + [BNXT_ULP_CLASS_HID_1c32] = 581, + [BNXT_ULP_CLASS_HID_175e] = 582, + [BNXT_ULP_CLASS_HID_0eb2] = 583, + [BNXT_ULP_CLASS_HID_09de] = 584, + [BNXT_ULP_CLASS_HID_5c3a] = 585, + [BNXT_ULP_CLASS_HID_5766] = 586, + [BNXT_ULP_CLASS_HID_79fa] = 587, + [BNXT_ULP_CLASS_HID_7126] = 588, + [BNXT_ULP_CLASS_HID_3c3e] = 589, + [BNXT_ULP_CLASS_HID_375a] = 590, + [BNXT_ULP_CLASS_HID_2ebe] = 591, + [BNXT_ULP_CLASS_HID_29da] = 592, + [BNXT_ULP_CLASS_HID_14f2] = 593, + [BNXT_ULP_CLASS_HID_7762] = 594, + [BNXT_ULP_CLASS_HID_19e8] = 595, + [BNXT_ULP_CLASS_HID_110c] = 596, + [BNXT_ULP_CLASS_HID_4d48] = 597, + [BNXT_ULP_CLASS_HID_446c] = 598, + [BNXT_ULP_CLASS_HID_0eac] = 599, + [BNXT_ULP_CLASS_HID_09c0] = 600, + [BNXT_ULP_CLASS_HID_1ad0] = 601, + [BNXT_ULP_CLASS_HID_15f4] = 602, + [BNXT_ULP_CLASS_HID_39ec] = 603, + [BNXT_ULP_CLASS_HID_3100] = 604, + [BNXT_ULP_CLASS_HID_0210] = 605, + [BNXT_ULP_CLASS_HID_1d34] = 606, + [BNXT_ULP_CLASS_HID_2ea0] = 607, + [BNXT_ULP_CLASS_HID_29c4] = 608, + [BNXT_ULP_CLASS_HID_3ad4] = 609, + [BNXT_ULP_CLASS_HID_35e8] = 610, + [BNXT_ULP_CLASS_HID_5d80] = 611, + [BNXT_ULP_CLASS_HID_54a4] = 612, + [BNXT_ULP_CLASS_HID_29b4] = 613, + [BNXT_ULP_CLASS_HID_20c8] = 614, + [BNXT_ULP_CLASS_HID_7244] = 615, + [BNXT_ULP_CLASS_HID_4d98] = 616, + [BNXT_ULP_CLASS_HID_5e68] = 617, + [BNXT_ULP_CLASS_HID_598c] = 618, + [BNXT_ULP_CLASS_HID_1248] = 619, + [BNXT_ULP_CLASS_HID_74d8] = 620, + [BNXT_ULP_CLASS_HID_49a8] = 621, + [BNXT_ULP_CLASS_HID_40cc] = 622, + [BNXT_ULP_CLASS_HID_0b0c] = 623, + [BNXT_ULP_CLASS_HID_0220] = 624, + [BNXT_ULP_CLASS_HID_1730] = 625, + [BNXT_ULP_CLASS_HID_7980] = 626, + [BNXT_ULP_CLASS_HID_1db0] = 627, + [BNXT_ULP_CLASS_HID_1494] = 628, + [BNXT_ULP_CLASS_HID_70d0] = 629, + [BNXT_ULP_CLASS_HID_4834] = 630, + [BNXT_ULP_CLASS_HID_3db4] = 631, + [BNXT_ULP_CLASS_HID_3498] = 632, + [BNXT_ULP_CLASS_HID_0988] = 633, + [BNXT_ULP_CLASS_HID_00ec] = 634, + [BNXT_ULP_CLASS_HID_3f44] = 635, + [BNXT_ULP_CLASS_HID_36a8] = 636, + [BNXT_ULP_CLASS_HID_0b58] = 637, + [BNXT_ULP_CLASS_HID_02bc] = 638, + [BNXT_ULP_CLASS_HID_5f48] = 639, + [BNXT_ULP_CLASS_HID_56ac] = 640, + [BNXT_ULP_CLASS_HID_2b5c] = 641, + [BNXT_ULP_CLASS_HID_2280] = 642, + [BNXT_ULP_CLASS_HID_4000] = 643, + [BNXT_ULP_CLASS_HID_5b64] = 644, + [BNXT_ULP_CLASS_HID_2c14] = 645, + [BNXT_ULP_CLASS_HID_2778] = 646, + [BNXT_ULP_CLASS_HID_18f8] = 647, + [BNXT_ULP_CLASS_HID_13dc] = 648, + [BNXT_ULP_CLASS_HID_4c18] = 649, + [BNXT_ULP_CLASS_HID_477c] = 650, + [BNXT_ULP_CLASS_HID_1a88] = 651, + [BNXT_ULP_CLASS_HID_15ec] = 652, + [BNXT_ULP_CLASS_HID_4e28] = 653, + [BNXT_ULP_CLASS_HID_490c] = 654, + [BNXT_ULP_CLASS_HID_3a8c] = 655, + [BNXT_ULP_CLASS_HID_35f0] = 656, + [BNXT_ULP_CLASS_HID_06e0] = 657, + [BNXT_ULP_CLASS_HID_01c4] = 658, + [BNXT_ULP_CLASS_HID_1a08] = 659, + [BNXT_ULP_CLASS_HID_12ec] = 660, + [BNXT_ULP_CLASS_HID_4ea8] = 661, + [BNXT_ULP_CLASS_HID_478c] = 662, + [BNXT_ULP_CLASS_HID_0d4c] = 663, + [BNXT_ULP_CLASS_HID_0a20] = 664, + [BNXT_ULP_CLASS_HID_1930] = 665, + [BNXT_ULP_CLASS_HID_1614] = 666, + [BNXT_ULP_CLASS_HID_3a0c] = 667, + [BNXT_ULP_CLASS_HID_32e0] = 668, + [BNXT_ULP_CLASS_HID_01f0] = 669, + [BNXT_ULP_CLASS_HID_1ed4] = 670, + [BNXT_ULP_CLASS_HID_2d40] = 671, + [BNXT_ULP_CLASS_HID_2a24] = 672, + [BNXT_ULP_CLASS_HID_3934] = 673, + [BNXT_ULP_CLASS_HID_3608] = 674, + [BNXT_ULP_CLASS_HID_5e60] = 675, + [BNXT_ULP_CLASS_HID_5744] = 676, + [BNXT_ULP_CLASS_HID_2a54] = 677, + [BNXT_ULP_CLASS_HID_2328] = 678, + [BNXT_ULP_CLASS_HID_71a4] = 679, + [BNXT_ULP_CLASS_HID_4e78] = 680, + [BNXT_ULP_CLASS_HID_5d88] = 681, + [BNXT_ULP_CLASS_HID_5a6c] = 682, + [BNXT_ULP_CLASS_HID_11a8] = 683, + [BNXT_ULP_CLASS_HID_7738] = 684, + [BNXT_ULP_CLASS_HID_4a48] = 685, + [BNXT_ULP_CLASS_HID_432c] = 686, + [BNXT_ULP_CLASS_HID_08ec] = 687, + [BNXT_ULP_CLASS_HID_01c0] = 688, + [BNXT_ULP_CLASS_HID_14d0] = 689, + [BNXT_ULP_CLASS_HID_7a60] = 690, + [BNXT_ULP_CLASS_HID_1d90] = 691, + [BNXT_ULP_CLASS_HID_14b4] = 692, + [BNXT_ULP_CLASS_HID_70f0] = 693, + [BNXT_ULP_CLASS_HID_4814] = 694, + [BNXT_ULP_CLASS_HID_3d94] = 695, + [BNXT_ULP_CLASS_HID_34b8] = 696, + [BNXT_ULP_CLASS_HID_09a8] = 697, + [BNXT_ULP_CLASS_HID_00cc] = 698, + [BNXT_ULP_CLASS_HID_3f64] = 699, + [BNXT_ULP_CLASS_HID_3688] = 700, + [BNXT_ULP_CLASS_HID_0b78] = 701, + [BNXT_ULP_CLASS_HID_029c] = 702, + [BNXT_ULP_CLASS_HID_5f68] = 703, + [BNXT_ULP_CLASS_HID_568c] = 704, + [BNXT_ULP_CLASS_HID_2b7c] = 705, + [BNXT_ULP_CLASS_HID_22a0] = 706, + [BNXT_ULP_CLASS_HID_4020] = 707, + [BNXT_ULP_CLASS_HID_5b44] = 708, + [BNXT_ULP_CLASS_HID_2c34] = 709, + [BNXT_ULP_CLASS_HID_2758] = 710, + [BNXT_ULP_CLASS_HID_18d8] = 711, + [BNXT_ULP_CLASS_HID_13fc] = 712, + [BNXT_ULP_CLASS_HID_4c38] = 713, + [BNXT_ULP_CLASS_HID_475c] = 714, + [BNXT_ULP_CLASS_HID_1aa8] = 715, + [BNXT_ULP_CLASS_HID_15cc] = 716, + [BNXT_ULP_CLASS_HID_4e08] = 717, + [BNXT_ULP_CLASS_HID_492c] = 718, + [BNXT_ULP_CLASS_HID_3aac] = 719, + [BNXT_ULP_CLASS_HID_35d0] = 720, + [BNXT_ULP_CLASS_HID_06c0] = 721, + [BNXT_ULP_CLASS_HID_01e4] = 722, + [BNXT_ULP_CLASS_HID_4d32] = 723, + [BNXT_ULP_CLASS_HID_54aa] = 724, + [BNXT_ULP_CLASS_HID_0686] = 725, + [BNXT_ULP_CLASS_HID_540e] = 726, + [BNXT_ULP_CLASS_HID_2e3c] = 727, + [BNXT_ULP_CLASS_HID_3a20] = 728, + [BNXT_ULP_CLASS_HID_46f0] = 729, + [BNXT_ULP_CLASS_HID_52e4] = 730, + [BNXT_ULP_CLASS_HID_55e4] = 731, + [BNXT_ULP_CLASS_HID_21f8] = 732, + [BNXT_ULP_CLASS_HID_75e8] = 733, + [BNXT_ULP_CLASS_HID_41fc] = 734, + [BNXT_ULP_CLASS_HID_4d12] = 735, + [BNXT_ULP_CLASS_HID_548a] = 736, + [BNXT_ULP_CLASS_HID_3356] = 737, + [BNXT_ULP_CLASS_HID_1ace] = 738, + [BNXT_ULP_CLASS_HID_1a9a] = 739, + [BNXT_ULP_CLASS_HID_4d46] = 740, + [BNXT_ULP_CLASS_HID_2812] = 741, + [BNXT_ULP_CLASS_HID_338a] = 742, + [BNXT_ULP_CLASS_HID_06e6] = 743, + [BNXT_ULP_CLASS_HID_546e] = 744, + [BNXT_ULP_CLASS_HID_46ee] = 745, + [BNXT_ULP_CLASS_HID_0d22] = 746, + [BNXT_ULP_CLASS_HID_26e2] = 747, + [BNXT_ULP_CLASS_HID_746a] = 748, + [BNXT_ULP_CLASS_HID_1fa6] = 749, + [BNXT_ULP_CLASS_HID_2d2e] = 750, + [BNXT_ULP_CLASS_HID_4ef2] = 751, + [BNXT_ULP_CLASS_HID_576a] = 752, + [BNXT_ULP_CLASS_HID_30b6] = 753, + [BNXT_ULP_CLASS_HID_192e] = 754, + [BNXT_ULP_CLASS_HID_197a] = 755, + [BNXT_ULP_CLASS_HID_4ea6] = 756, + [BNXT_ULP_CLASS_HID_2bf2] = 757, + [BNXT_ULP_CLASS_HID_306a] = 758, + [BNXT_ULP_CLASS_HID_06c6] = 759, + [BNXT_ULP_CLASS_HID_544e] = 760, + [BNXT_ULP_CLASS_HID_46ce] = 761, + [BNXT_ULP_CLASS_HID_0d02] = 762, + [BNXT_ULP_CLASS_HID_26c2] = 763, + [BNXT_ULP_CLASS_HID_744a] = 764, + [BNXT_ULP_CLASS_HID_1f86] = 765, + [BNXT_ULP_CLASS_HID_2d0e] = 766, + [BNXT_ULP_CLASS_HID_2e1c] = 767, + [BNXT_ULP_CLASS_HID_3a00] = 768, + [BNXT_ULP_CLASS_HID_46d0] = 769, + [BNXT_ULP_CLASS_HID_52c4] = 770, + [BNXT_ULP_CLASS_HID_4e10] = 771, + [BNXT_ULP_CLASS_HID_5a04] = 772, + [BNXT_ULP_CLASS_HID_1f98] = 773, + [BNXT_ULP_CLASS_HID_72f8] = 774, + [BNXT_ULP_CLASS_HID_0a78] = 775, + [BNXT_ULP_CLASS_HID_166c] = 776, + [BNXT_ULP_CLASS_HID_233c] = 777, + [BNXT_ULP_CLASS_HID_0f20] = 778, + [BNXT_ULP_CLASS_HID_2a7c] = 779, + [BNXT_ULP_CLASS_HID_3660] = 780, + [BNXT_ULP_CLASS_HID_4330] = 781, + [BNXT_ULP_CLASS_HID_2f24] = 782, + [BNXT_ULP_CLASS_HID_5584] = 783, + [BNXT_ULP_CLASS_HID_2198] = 784, + [BNXT_ULP_CLASS_HID_7588] = 785, + [BNXT_ULP_CLASS_HID_419c] = 786, + [BNXT_ULP_CLASS_HID_7758] = 787, + [BNXT_ULP_CLASS_HID_43ac] = 788, + [BNXT_ULP_CLASS_HID_0c10] = 789, + [BNXT_ULP_CLASS_HID_1864] = 790, + [BNXT_ULP_CLASS_HID_30c8] = 791, + [BNXT_ULP_CLASS_HID_1cdc] = 792, + [BNXT_ULP_CLASS_HID_50cc] = 793, + [BNXT_ULP_CLASS_HID_3d20] = 794, + [BNXT_ULP_CLASS_HID_529c] = 795, + [BNXT_ULP_CLASS_HID_3ef0] = 796, + [BNXT_ULP_CLASS_HID_72e0] = 797, + [BNXT_ULP_CLASS_HID_5ef4] = 798, + [BNXT_ULP_CLASS_HID_2dfc] = 799, + [BNXT_ULP_CLASS_HID_39e0] = 800, + [BNXT_ULP_CLASS_HID_4530] = 801, + [BNXT_ULP_CLASS_HID_5124] = 802, + [BNXT_ULP_CLASS_HID_4df0] = 803, + [BNXT_ULP_CLASS_HID_59e4] = 804, + [BNXT_ULP_CLASS_HID_1c78] = 805, + [BNXT_ULP_CLASS_HID_7118] = 806, + [BNXT_ULP_CLASS_HID_0998] = 807, + [BNXT_ULP_CLASS_HID_158c] = 808, + [BNXT_ULP_CLASS_HID_20dc] = 809, + [BNXT_ULP_CLASS_HID_0cc0] = 810, + [BNXT_ULP_CLASS_HID_299c] = 811, + [BNXT_ULP_CLASS_HID_3580] = 812, + [BNXT_ULP_CLASS_HID_40d0] = 813, + [BNXT_ULP_CLASS_HID_2cc4] = 814, + [BNXT_ULP_CLASS_HID_55a4] = 815, + [BNXT_ULP_CLASS_HID_21b8] = 816, + [BNXT_ULP_CLASS_HID_75a8] = 817, + [BNXT_ULP_CLASS_HID_41bc] = 818, + [BNXT_ULP_CLASS_HID_7778] = 819, + [BNXT_ULP_CLASS_HID_438c] = 820, + [BNXT_ULP_CLASS_HID_0c30] = 821, + [BNXT_ULP_CLASS_HID_1844] = 822, + [BNXT_ULP_CLASS_HID_30e8] = 823, + [BNXT_ULP_CLASS_HID_1cfc] = 824, + [BNXT_ULP_CLASS_HID_50ec] = 825, + [BNXT_ULP_CLASS_HID_3d00] = 826, + [BNXT_ULP_CLASS_HID_52bc] = 827, + [BNXT_ULP_CLASS_HID_3ed0] = 828, + [BNXT_ULP_CLASS_HID_72c0] = 829, + [BNXT_ULP_CLASS_HID_5ed4] = 830, + [BNXT_ULP_CLASS_HID_3866] = 831, + [BNXT_ULP_CLASS_HID_381e] = 832, + [BNXT_ULP_CLASS_HID_3860] = 833, + [BNXT_ULP_CLASS_HID_0454] = 834, + [BNXT_ULP_CLASS_HID_3818] = 835, + [BNXT_ULP_CLASS_HID_042c] = 836, + [BNXT_ULP_CLASS_HID_3846] = 837, + [BNXT_ULP_CLASS_HID_387e] = 838, + [BNXT_ULP_CLASS_HID_3ba6] = 839, + [BNXT_ULP_CLASS_HID_385e] = 840, + [BNXT_ULP_CLASS_HID_3840] = 841, + [BNXT_ULP_CLASS_HID_0474] = 842, + [BNXT_ULP_CLASS_HID_3878] = 843, + [BNXT_ULP_CLASS_HID_044c] = 844, + [BNXT_ULP_CLASS_HID_3ba0] = 845, + [BNXT_ULP_CLASS_HID_0794] = 846, + [BNXT_ULP_CLASS_HID_3858] = 847, + [BNXT_ULP_CLASS_HID_046c] = 848 }; /* Array for the proto matcher list */ @@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT } }, [345] = { - .class_hid = BNXT_ULP_CLASS_HID_34c6, + .class_hid = BNXT_ULP_CLASS_HID_3612, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 81920, + .flow_pattern_id = 0, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_F1 | + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT } + }, + [346] = { + .class_hid = BNXT_ULP_CLASS_HID_66da, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 81928, + .flow_pattern_id = 0, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_F1 | + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT } + }, + [347] = { + .class_hid = BNXT_ULP_CLASS_HID_6165, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 1313792, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC } + }, + [348] = { + .class_hid = BNXT_ULP_CLASS_HID_2aa1, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 1321984, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC } + }, + [349] = { + .class_hid = BNXT_ULP_CLASS_HID_09cd, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3410944, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC } + }, + [350] = { + .class_hid = BNXT_ULP_CLASS_HID_3845, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3419136, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC } + }, + [351] = { + .class_hid = BNXT_ULP_CLASS_HID_11e9, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2148797440, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [352] = { + .class_hid = BNXT_ULP_CLASS_HID_4361, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2148805632, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [353] = { + .class_hid = BNXT_ULP_CLASS_HID_218d, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2150894592, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [354] = { + .class_hid = BNXT_ULP_CLASS_HID_5105, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2150902784, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [355] = { + .class_hid = BNXT_ULP_CLASS_HID_0c89, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4296281088, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [356] = { + .class_hid = BNXT_ULP_CLASS_HID_3e81, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4296289280, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [357] = { + .class_hid = BNXT_ULP_CLASS_HID_1dad, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4298378240, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [358] = { + .class_hid = BNXT_ULP_CLASS_HID_4ca5, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4298386432, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [359] = { + .class_hid = BNXT_ULP_CLASS_HID_25c9, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6443764736, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [360] = { + .class_hid = BNXT_ULP_CLASS_HID_57c1, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6443772928, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [361] = { + .class_hid = BNXT_ULP_CLASS_HID_33ed, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6445861888, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [362] = { + .class_hid = BNXT_ULP_CLASS_HID_65e5, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6445870080, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [363] = { + .class_hid = BNXT_ULP_CLASS_HID_6dd9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 1313792, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC } + }, + [364] = { + .class_hid = BNXT_ULP_CLASS_HID_261d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 1321984, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC } + }, + [365] = { + .class_hid = BNXT_ULP_CLASS_HID_0571, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3410944, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC } + }, + [366] = { + .class_hid = BNXT_ULP_CLASS_HID_34f9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3419136, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC } + }, + [367] = { + .class_hid = BNXT_ULP_CLASS_HID_1d55, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2148797440, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [368] = { + .class_hid = BNXT_ULP_CLASS_HID_4fdd, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2148805632, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [369] = { + .class_hid = BNXT_ULP_CLASS_HID_2d31, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2150894592, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [370] = { + .class_hid = BNXT_ULP_CLASS_HID_5db9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2150902784, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [371] = { + .class_hid = BNXT_ULP_CLASS_HID_0035, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4296281088, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [372] = { + .class_hid = BNXT_ULP_CLASS_HID_323d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4296289280, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [373] = { + .class_hid = BNXT_ULP_CLASS_HID_1111, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4298378240, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [374] = { + .class_hid = BNXT_ULP_CLASS_HID_4019, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4298386432, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [375] = { + .class_hid = BNXT_ULP_CLASS_HID_2975, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6443764736, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [376] = { + .class_hid = BNXT_ULP_CLASS_HID_5b7d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6443772928, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [377] = { + .class_hid = BNXT_ULP_CLASS_HID_3f51, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6445861888, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [378] = { + .class_hid = BNXT_ULP_CLASS_HID_6959, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6445870080, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [379] = { + .class_hid = BNXT_ULP_CLASS_HID_0e85, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8591248384, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [380] = { + .class_hid = BNXT_ULP_CLASS_HID_380d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8591256576, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [381] = { + .class_hid = BNXT_ULP_CLASS_HID_1f21, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8593345536, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [382] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8593353728, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [383] = { + .class_hid = BNXT_ULP_CLASS_HID_1705, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10738732032, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [384] = { + .class_hid = BNXT_ULP_CLASS_HID_418d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10738740224, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [385] = { + .class_hid = BNXT_ULP_CLASS_HID_2721, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10740829184, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [386] = { + .class_hid = BNXT_ULP_CLASS_HID_57a9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10740837376, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [387] = { + .class_hid = BNXT_ULP_CLASS_HID_1a25, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12886215680, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [388] = { + .class_hid = BNXT_ULP_CLASS_HID_342d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12886223872, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [389] = { + .class_hid = BNXT_ULP_CLASS_HID_2b01, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12888312832, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [390] = { + .class_hid = BNXT_ULP_CLASS_HID_5a09, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12888321024, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [391] = { + .class_hid = BNXT_ULP_CLASS_HID_2325, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15033699328, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [392] = { + .class_hid = BNXT_ULP_CLASS_HID_5d2d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15033707520, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [393] = { + .class_hid = BNXT_ULP_CLASS_HID_3101, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15035796480, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [394] = { + .class_hid = BNXT_ULP_CLASS_HID_6309, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15035804672, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [395] = { + .class_hid = BNXT_ULP_CLASS_HID_0bad, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17181182976, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [396] = { + .class_hid = BNXT_ULP_CLASS_HID_2535, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17181191168, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [397] = { + .class_hid = BNXT_ULP_CLASS_HID_1869, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17183280128, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [398] = { + .class_hid = BNXT_ULP_CLASS_HID_4bf1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17183288320, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [399] = { + .class_hid = BNXT_ULP_CLASS_HID_136d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19328666624, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [400] = { + .class_hid = BNXT_ULP_CLASS_HID_43f5, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19328674816, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [401] = { + .class_hid = BNXT_ULP_CLASS_HID_2129, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19330763776, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [402] = { + .class_hid = BNXT_ULP_CLASS_HID_53b1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19330771968, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [403] = { + .class_hid = BNXT_ULP_CLASS_HID_072d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21476150272, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [404] = { + .class_hid = BNXT_ULP_CLASS_HID_3135, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21476158464, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [405] = { + .class_hid = BNXT_ULP_CLASS_HID_1429, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21478247424, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [406] = { + .class_hid = BNXT_ULP_CLASS_HID_4731, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21478255616, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [407] = { + .class_hid = BNXT_ULP_CLASS_HID_2f6d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23623633920, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [408] = { + .class_hid = BNXT_ULP_CLASS_HID_5f75, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23623642112, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [409] = { + .class_hid = BNXT_ULP_CLASS_HID_3d69, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23625731072, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [410] = { + .class_hid = BNXT_ULP_CLASS_HID_6f71, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23625739264, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [411] = { + .class_hid = BNXT_ULP_CLASS_HID_0dbd, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25771117568, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [412] = { + .class_hid = BNXT_ULP_CLASS_HID_3f25, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25771125760, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [413] = { + .class_hid = BNXT_ULP_CLASS_HID_1239, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25773214720, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [414] = { + .class_hid = BNXT_ULP_CLASS_HID_4da1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25773222912, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [415] = { + .class_hid = BNXT_ULP_CLASS_HID_153d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27918601216, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [416] = { + .class_hid = BNXT_ULP_CLASS_HID_45a5, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27918609408, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [417] = { + .class_hid = BNXT_ULP_CLASS_HID_3bb9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27920698368, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [418] = { + .class_hid = BNXT_ULP_CLASS_HID_55a1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27920706560, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [419] = { + .class_hid = BNXT_ULP_CLASS_HID_193d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30066084864, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [420] = { + .class_hid = BNXT_ULP_CLASS_HID_4b25, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30066093056, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [421] = { + .class_hid = BNXT_ULP_CLASS_HID_2e39, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30068182016, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [422] = { + .class_hid = BNXT_ULP_CLASS_HID_5921, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30068190208, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [423] = { + .class_hid = BNXT_ULP_CLASS_HID_213d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32213568512, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [424] = { + .class_hid = BNXT_ULP_CLASS_HID_5125, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32213576704, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [425] = { + .class_hid = BNXT_ULP_CLASS_HID_3739, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32215665664, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [426] = { + .class_hid = BNXT_ULP_CLASS_HID_093d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32215673856, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [427] = { + .class_hid = BNXT_ULP_CLASS_HID_684d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 1313792, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC } + }, + [428] = { + .class_hid = BNXT_ULP_CLASS_HID_2389, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 1321984, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC } + }, + [429] = { + .class_hid = BNXT_ULP_CLASS_HID_00e5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 3410944, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC } + }, + [430] = { + .class_hid = BNXT_ULP_CLASS_HID_316d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 3419136, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC } + }, + [431] = { + .class_hid = BNXT_ULP_CLASS_HID_18c1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2148797440, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [432] = { + .class_hid = BNXT_ULP_CLASS_HID_4a49, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2148805632, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [433] = { + .class_hid = BNXT_ULP_CLASS_HID_28a5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2150894592, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [434] = { + .class_hid = BNXT_ULP_CLASS_HID_582d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2150902784, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [435] = { + .class_hid = BNXT_ULP_CLASS_HID_05a1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4296281088, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [436] = { + .class_hid = BNXT_ULP_CLASS_HID_37a9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4296289280, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [437] = { + .class_hid = BNXT_ULP_CLASS_HID_1485, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4298378240, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [438] = { + .class_hid = BNXT_ULP_CLASS_HID_458d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4298386432, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [439] = { + .class_hid = BNXT_ULP_CLASS_HID_2ce1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6443764736, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [440] = { + .class_hid = BNXT_ULP_CLASS_HID_5ee9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6443772928, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [441] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6445861888, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [442] = { + .class_hid = BNXT_ULP_CLASS_HID_6ccd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6445870080, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [443] = { + .class_hid = BNXT_ULP_CLASS_HID_0b11, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8591248384, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [444] = { + .class_hid = BNXT_ULP_CLASS_HID_3d99, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8591256576, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [445] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8593345536, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [446] = { + .class_hid = BNXT_ULP_CLASS_HID_4b3d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8593353728, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [447] = { + .class_hid = BNXT_ULP_CLASS_HID_1291, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10738732032, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [448] = { + .class_hid = BNXT_ULP_CLASS_HID_4419, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10738740224, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [449] = { + .class_hid = BNXT_ULP_CLASS_HID_22b5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10740829184, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [450] = { + .class_hid = BNXT_ULP_CLASS_HID_523d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10740837376, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [451] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12886215680, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [452] = { + .class_hid = BNXT_ULP_CLASS_HID_31b9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12886223872, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [453] = { + .class_hid = BNXT_ULP_CLASS_HID_2e95, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12888312832, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [454] = { + .class_hid = BNXT_ULP_CLASS_HID_5f9d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12888321024, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [455] = { + .class_hid = BNXT_ULP_CLASS_HID_26b1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15033699328, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [456] = { + .class_hid = BNXT_ULP_CLASS_HID_58b9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15033707520, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [457] = { + .class_hid = BNXT_ULP_CLASS_HID_3495, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15035796480, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [458] = { + .class_hid = BNXT_ULP_CLASS_HID_669d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15035804672, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [459] = { + .class_hid = BNXT_ULP_CLASS_HID_0e39, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17181182976, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [460] = { + .class_hid = BNXT_ULP_CLASS_HID_20a1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17181191168, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [461] = { + .class_hid = BNXT_ULP_CLASS_HID_1dfd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17183280128, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [462] = { + .class_hid = BNXT_ULP_CLASS_HID_4e65, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17183288320, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [463] = { + .class_hid = BNXT_ULP_CLASS_HID_16f9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19328666624, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [464] = { + .class_hid = BNXT_ULP_CLASS_HID_4661, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19328674816, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [465] = { + .class_hid = BNXT_ULP_CLASS_HID_24bd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19330763776, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [466] = { + .class_hid = BNXT_ULP_CLASS_HID_5625, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19330771968, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [467] = { + .class_hid = BNXT_ULP_CLASS_HID_02b9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21476150272, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [468] = { + .class_hid = BNXT_ULP_CLASS_HID_34a1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21476158464, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [469] = { + .class_hid = BNXT_ULP_CLASS_HID_11bd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21478247424, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [470] = { + .class_hid = BNXT_ULP_CLASS_HID_42a5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21478255616, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [471] = { + .class_hid = BNXT_ULP_CLASS_HID_2af9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23623633920, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [472] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23623642112, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [473] = { + .class_hid = BNXT_ULP_CLASS_HID_38fd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23625731072, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [474] = { + .class_hid = BNXT_ULP_CLASS_HID_6ae5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23625739264, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [475] = { + .class_hid = BNXT_ULP_CLASS_HID_0829, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25771117568, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [476] = { + .class_hid = BNXT_ULP_CLASS_HID_3ab1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25771125760, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [477] = { + .class_hid = BNXT_ULP_CLASS_HID_17ad, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25773214720, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [478] = { + .class_hid = BNXT_ULP_CLASS_HID_4835, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25773222912, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [479] = { + .class_hid = BNXT_ULP_CLASS_HID_10a9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27918601216, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [480] = { + .class_hid = BNXT_ULP_CLASS_HID_4031, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27918609408, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [481] = { + .class_hid = BNXT_ULP_CLASS_HID_3e2d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27920698368, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [482] = { + .class_hid = BNXT_ULP_CLASS_HID_5035, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27920706560, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [483] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30066084864, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [484] = { + .class_hid = BNXT_ULP_CLASS_HID_4eb1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30066093056, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [485] = { + .class_hid = BNXT_ULP_CLASS_HID_2bad, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30068182016, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [486] = { + .class_hid = BNXT_ULP_CLASS_HID_5cb5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30068190208, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [487] = { + .class_hid = BNXT_ULP_CLASS_HID_24a9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32213568512, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [488] = { + .class_hid = BNXT_ULP_CLASS_HID_54b1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32213576704, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [489] = { + .class_hid = BNXT_ULP_CLASS_HID_32ad, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32215665664, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [490] = { + .class_hid = BNXT_ULP_CLASS_HID_0ca9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32215673856, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [491] = { + .class_hid = BNXT_ULP_CLASS_HID_7f35, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 1313792, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC } + }, + [492] = { + .class_hid = BNXT_ULP_CLASS_HID_34f1, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 1321984, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC } + }, + [493] = { + .class_hid = BNXT_ULP_CLASS_HID_179d, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 3410944, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC } + }, + [494] = { + .class_hid = BNXT_ULP_CLASS_HID_2615, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 3419136, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC } + }, + [495] = { + .class_hid = BNXT_ULP_CLASS_HID_0fb9, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2148797440, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [496] = { + .class_hid = BNXT_ULP_CLASS_HID_5d31, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2148805632, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [497] = { + .class_hid = BNXT_ULP_CLASS_HID_3fdd, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2150894592, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [498] = { + .class_hid = BNXT_ULP_CLASS_HID_4f55, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2150902784, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [499] = { + .class_hid = BNXT_ULP_CLASS_HID_12d9, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4296281088, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [500] = { + .class_hid = BNXT_ULP_CLASS_HID_20d1, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4296289280, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [501] = { + .class_hid = BNXT_ULP_CLASS_HID_03fd, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4298378240, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [502] = { + .class_hid = BNXT_ULP_CLASS_HID_52f5, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4298386432, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [503] = { + .class_hid = BNXT_ULP_CLASS_HID_3b99, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6443764736, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [504] = { + .class_hid = BNXT_ULP_CLASS_HID_4991, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6443772928, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [505] = { + .class_hid = BNXT_ULP_CLASS_HID_2dbd, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6445861888, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [506] = { + .class_hid = BNXT_ULP_CLASS_HID_7bb5, .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6445870080, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [507] = { + .class_hid = BNXT_ULP_CLASS_HID_34c6, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 0, @@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [346] = { + [508] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4100, .flow_pattern_id = 0, @@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [347] = { + [509] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 0, @@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [348] = { + [510] = { .class_hid = BNXT_ULP_CLASS_HID_179a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 6148, .flow_pattern_id = 0, @@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [349] = { + [511] = { .class_hid = BNXT_ULP_CLASS_HID_59be, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 0, @@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [350] = { + [512] = { .class_hid = BNXT_ULP_CLASS_HID_515a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 16388, .flow_pattern_id = 0, @@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [351] = { + [513] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 0, @@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [352] = { + [514] = { .class_hid = BNXT_ULP_CLASS_HID_171e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 24580, .flow_pattern_id = 0, @@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [353] = { + [515] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 0, @@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [354] = { + [516] = { .class_hid = BNXT_ULP_CLASS_HID_112c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32772, .flow_pattern_id = 0, @@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [355] = { + [517] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 0, @@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [356] = { + [518] = { .class_hid = BNXT_ULP_CLASS_HID_444c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32836, .flow_pattern_id = 0, @@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [357] = { + [519] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [358] = { + [520] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [359] = { + [521] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 0, @@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [360] = { + [522] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49220, .flow_pattern_id = 0, @@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [361] = { + [523] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 0, @@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [362] = { + [524] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131076, .flow_pattern_id = 0, @@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [363] = { + [525] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 0, @@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [364] = { + [526] = { .class_hid = BNXT_ULP_CLASS_HID_4854, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131140, .flow_pattern_id = 0, @@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [365] = { + [527] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 0, @@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [366] = { + [528] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196612, .flow_pattern_id = 0, @@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [367] = { + [529] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 0, @@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [368] = { + [530] = { .class_hid = BNXT_ULP_CLASS_HID_008c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196676, .flow_pattern_id = 0, @@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [369] = { + [531] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 0, @@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [370] = { + [532] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4100, .flow_pattern_id = 0, @@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [371] = { + [533] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 0, @@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [372] = { + [534] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 6148, .flow_pattern_id = 0, @@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [373] = { + [535] = { .class_hid = BNXT_ULP_CLASS_HID_429e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 0, @@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [374] = { + [536] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 12292, .flow_pattern_id = 0, @@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [375] = { + [537] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 0, @@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [376] = { + [538] = { .class_hid = BNXT_ULP_CLASS_HID_2532, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 14340, .flow_pattern_id = 0, @@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [377] = { + [539] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 0, @@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [378] = { + [540] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 20484, .flow_pattern_id = 0, @@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [379] = { + [541] = { .class_hid = BNXT_ULP_CLASS_HID_355a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 0, @@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [380] = { + [542] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 22532, .flow_pattern_id = 0, @@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [381] = { + [543] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 0, @@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [382] = { + [544] = { .class_hid = BNXT_ULP_CLASS_HID_7276, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 28676, .flow_pattern_id = 0, @@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [383] = { + [545] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 0, @@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [384] = { + [546] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 30724, .flow_pattern_id = 0, @@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [385] = { + [547] = { .class_hid = BNXT_ULP_CLASS_HID_59de, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 0, @@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [386] = { + [548] = { .class_hid = BNXT_ULP_CLASS_HID_513a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 16388, .flow_pattern_id = 0, @@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [387] = { + [549] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 0, @@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [388] = { + [550] = { .class_hid = BNXT_ULP_CLASS_HID_177e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 24580, .flow_pattern_id = 0, @@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [389] = { + [551] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [390] = { + [552] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [391] = { + [553] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 0, @@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [392] = { + [554] = { .class_hid = BNXT_ULP_CLASS_HID_5746, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 57348, .flow_pattern_id = 0, @@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [393] = { + [555] = { .class_hid = BNXT_ULP_CLASS_HID_79da, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 0, @@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [394] = { + [556] = { .class_hid = BNXT_ULP_CLASS_HID_7106, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 81924, .flow_pattern_id = 0, @@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [395] = { + [557] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 0, @@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [396] = { + [558] = { .class_hid = BNXT_ULP_CLASS_HID_377a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 90116, .flow_pattern_id = 0, @@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [397] = { + [559] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [398] = { + [560] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [399] = { + [561] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 0, @@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [400] = { + [562] = { .class_hid = BNXT_ULP_CLASS_HID_7742, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 122884, .flow_pattern_id = 0, @@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [401] = { + [563] = { .class_hid = BNXT_ULP_CLASS_HID_3706, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 0, @@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [402] = { + [564] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4100, .flow_pattern_id = 0, @@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [403] = { + [565] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 0, @@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [404] = { + [566] = { .class_hid = BNXT_ULP_CLASS_HID_145a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 6148, .flow_pattern_id = 0, @@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [405] = { + [567] = { .class_hid = BNXT_ULP_CLASS_HID_417e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 0, @@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [406] = { + [568] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 12292, .flow_pattern_id = 0, @@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [407] = { + [569] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 0, @@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [408] = { + [570] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 14340, .flow_pattern_id = 0, @@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [409] = { + [571] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 0, @@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [410] = { + [572] = { .class_hid = BNXT_ULP_CLASS_HID_271e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 20484, .flow_pattern_id = 0, @@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [411] = { + [573] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 0, @@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [412] = { + [574] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 22532, .flow_pattern_id = 0, @@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [413] = { + [575] = { .class_hid = BNXT_ULP_CLASS_HID_1006, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 0, @@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [414] = { + [576] = { .class_hid = BNXT_ULP_CLASS_HID_7196, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 28676, .flow_pattern_id = 0, @@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [415] = { + [577] = { .class_hid = BNXT_ULP_CLASS_HID_4132, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 0, @@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [416] = { + [578] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 30724, .flow_pattern_id = 0, @@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [417] = { + [579] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 0, @@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [418] = { + [580] = { .class_hid = BNXT_ULP_CLASS_HID_511a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 16388, .flow_pattern_id = 0, @@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [419] = { + [581] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 0, @@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [420] = { + [582] = { .class_hid = BNXT_ULP_CLASS_HID_175e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 24580, .flow_pattern_id = 0, @@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [421] = { + [583] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [422] = { + [584] = { .class_hid = BNXT_ULP_CLASS_HID_09de, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [423] = { + [585] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 0, @@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [424] = { + [586] = { .class_hid = BNXT_ULP_CLASS_HID_5766, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 57348, .flow_pattern_id = 0, @@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [425] = { + [587] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 0, @@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [426] = { + [588] = { .class_hid = BNXT_ULP_CLASS_HID_7126, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 81924, .flow_pattern_id = 0, @@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [427] = { + [589] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 0, @@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [428] = { + [590] = { .class_hid = BNXT_ULP_CLASS_HID_375a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 90116, .flow_pattern_id = 0, @@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [429] = { + [591] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [430] = { + [592] = { .class_hid = BNXT_ULP_CLASS_HID_29da, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [431] = { + [593] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 0, @@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [432] = { + [594] = { .class_hid = BNXT_ULP_CLASS_HID_7762, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 122884, .flow_pattern_id = 0, @@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [433] = { + [595] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 0, @@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [434] = { + [596] = { .class_hid = BNXT_ULP_CLASS_HID_110c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32772, .flow_pattern_id = 0, @@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [435] = { + [597] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 0, @@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [436] = { + [598] = { .class_hid = BNXT_ULP_CLASS_HID_446c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32836, .flow_pattern_id = 0, @@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [437] = { + [599] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [438] = { + [600] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [439] = { + [601] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 0, @@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [440] = { + [602] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49220, .flow_pattern_id = 0, @@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [441] = { + [603] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 0, @@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [442] = { + [604] = { .class_hid = BNXT_ULP_CLASS_HID_3100, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98308, .flow_pattern_id = 0, @@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [443] = { + [605] = { .class_hid = BNXT_ULP_CLASS_HID_0210, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 0, @@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [444] = { + [606] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98372, .flow_pattern_id = 0, @@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [445] = { + [607] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [446] = { + [608] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [447] = { + [609] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 0, @@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [448] = { + [610] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114756, .flow_pattern_id = 0, @@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [449] = { + [611] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 0, @@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [450] = { + [612] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163844, .flow_pattern_id = 0, @@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [451] = { + [613] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 0, @@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [452] = { + [614] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163908, .flow_pattern_id = 0, @@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [453] = { + [615] = { .class_hid = BNXT_ULP_CLASS_HID_7244, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 0, @@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [454] = { + [616] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180228, .flow_pattern_id = 0, @@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [455] = { + [617] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 0, @@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [456] = { + [618] = { .class_hid = BNXT_ULP_CLASS_HID_598c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180292, .flow_pattern_id = 0, @@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [457] = { + [619] = { .class_hid = BNXT_ULP_CLASS_HID_1248, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 0, @@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [458] = { + [620] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229380, .flow_pattern_id = 0, @@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [459] = { + [621] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 0, @@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [460] = { + [622] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229444, .flow_pattern_id = 0, @@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [461] = { + [623] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 0, @@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [462] = { + [624] = { .class_hid = BNXT_ULP_CLASS_HID_0220, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245764, .flow_pattern_id = 0, @@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [463] = { + [625] = { .class_hid = BNXT_ULP_CLASS_HID_1730, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 0, @@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [464] = { + [626] = { .class_hid = BNXT_ULP_CLASS_HID_7980, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245828, .flow_pattern_id = 0, @@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [465] = { + [627] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 0, @@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [466] = { + [628] = { .class_hid = BNXT_ULP_CLASS_HID_1494, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131076, .flow_pattern_id = 0, @@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [467] = { + [629] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 0, @@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [468] = { + [630] = { .class_hid = BNXT_ULP_CLASS_HID_4834, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131140, .flow_pattern_id = 0, @@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [469] = { + [631] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 0, @@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [470] = { + [632] = { .class_hid = BNXT_ULP_CLASS_HID_3498, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196612, .flow_pattern_id = 0, @@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [471] = { + [633] = { .class_hid = BNXT_ULP_CLASS_HID_0988, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 0, @@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [472] = { + [634] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196676, .flow_pattern_id = 0, @@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [473] = { + [635] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 0, @@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [474] = { + [636] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393220, .flow_pattern_id = 0, @@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [475] = { + [637] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 0, @@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [476] = { + [638] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393284, .flow_pattern_id = 0, @@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [477] = { + [639] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 0, @@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [478] = { + [640] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458756, .flow_pattern_id = 0, @@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [479] = { + [641] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 0, @@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [480] = { + [642] = { .class_hid = BNXT_ULP_CLASS_HID_2280, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458820, .flow_pattern_id = 0, @@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [481] = { + [643] = { .class_hid = BNXT_ULP_CLASS_HID_4000, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 0, @@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [482] = { + [644] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655364, .flow_pattern_id = 0, @@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [483] = { + [645] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 0, @@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [484] = { + [646] = { .class_hid = BNXT_ULP_CLASS_HID_2778, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655428, .flow_pattern_id = 0, @@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [485] = { + [647] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 0, @@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [486] = { + [648] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720900, .flow_pattern_id = 0, @@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [487] = { + [649] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 0, @@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [488] = { + [650] = { .class_hid = BNXT_ULP_CLASS_HID_477c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720964, .flow_pattern_id = 0, @@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [489] = { + [651] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 0, @@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [490] = { + [652] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917508, .flow_pattern_id = 0, @@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [491] = { + [653] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 0, @@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [492] = { + [654] = { .class_hid = BNXT_ULP_CLASS_HID_490c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917572, .flow_pattern_id = 0, @@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [493] = { + [655] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 0, @@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [494] = { + [656] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983044, .flow_pattern_id = 0, @@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [495] = { + [657] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 0, @@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [496] = { + [658] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983108, .flow_pattern_id = 0, @@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [497] = { + [659] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 0, @@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [498] = { + [660] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32772, .flow_pattern_id = 0, @@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [499] = { + [661] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 0, @@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [500] = { + [662] = { .class_hid = BNXT_ULP_CLASS_HID_478c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32836, .flow_pattern_id = 0, @@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [501] = { + [663] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [502] = { + [664] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [503] = { + [665] = { .class_hid = BNXT_ULP_CLASS_HID_1930, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 0, @@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [504] = { + [666] = { .class_hid = BNXT_ULP_CLASS_HID_1614, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49220, .flow_pattern_id = 0, @@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [505] = { + [667] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 0, @@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [506] = { + [668] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98308, .flow_pattern_id = 0, @@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [507] = { + [669] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 0, @@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [508] = { + [670] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98372, .flow_pattern_id = 0, @@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [509] = { + [671] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [510] = { + [672] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [511] = { + [673] = { .class_hid = BNXT_ULP_CLASS_HID_3934, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 0, @@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [512] = { + [674] = { .class_hid = BNXT_ULP_CLASS_HID_3608, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114756, .flow_pattern_id = 0, @@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [513] = { + [675] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 0, @@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [514] = { + [676] = { .class_hid = BNXT_ULP_CLASS_HID_5744, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163844, .flow_pattern_id = 0, @@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [515] = { + [677] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 0, @@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [516] = { + [678] = { .class_hid = BNXT_ULP_CLASS_HID_2328, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163908, .flow_pattern_id = 0, @@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [517] = { + [679] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 0, @@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [518] = { + [680] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180228, .flow_pattern_id = 0, @@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [519] = { + [681] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 0, @@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [520] = { + [682] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180292, .flow_pattern_id = 0, @@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [521] = { + [683] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 0, @@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [522] = { + [684] = { .class_hid = BNXT_ULP_CLASS_HID_7738, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229380, .flow_pattern_id = 0, @@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [523] = { + [685] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 0, @@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [524] = { + [686] = { .class_hid = BNXT_ULP_CLASS_HID_432c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229444, .flow_pattern_id = 0, @@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [525] = { + [687] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 0, @@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [526] = { + [688] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245764, .flow_pattern_id = 0, @@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [527] = { + [689] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 0, @@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [528] = { + [690] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245828, .flow_pattern_id = 0, @@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [529] = { + [691] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 0, @@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [530] = { + [692] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131076, .flow_pattern_id = 0, @@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [531] = { + [693] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 0, @@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [532] = { + [694] = { .class_hid = BNXT_ULP_CLASS_HID_4814, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131140, .flow_pattern_id = 0, @@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [533] = { + [695] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 0, @@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [534] = { + [696] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196612, .flow_pattern_id = 0, @@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [535] = { + [697] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 0, @@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [536] = { + [698] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196676, .flow_pattern_id = 0, @@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [537] = { + [699] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 0, @@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [538] = { + [700] = { .class_hid = BNXT_ULP_CLASS_HID_3688, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393220, .flow_pattern_id = 0, @@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [539] = { + [701] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 0, @@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [540] = { + [702] = { .class_hid = BNXT_ULP_CLASS_HID_029c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393284, .flow_pattern_id = 0, @@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [541] = { + [703] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 0, @@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [542] = { + [704] = { .class_hid = BNXT_ULP_CLASS_HID_568c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458756, .flow_pattern_id = 0, @@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [543] = { + [705] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 0, @@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [544] = { + [706] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458820, .flow_pattern_id = 0, @@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [545] = { + [707] = { .class_hid = BNXT_ULP_CLASS_HID_4020, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 0, @@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [546] = { + [708] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655364, .flow_pattern_id = 0, @@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [547] = { + [709] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 0, @@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [548] = { + [710] = { .class_hid = BNXT_ULP_CLASS_HID_2758, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655428, .flow_pattern_id = 0, @@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [549] = { + [711] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 0, @@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [550] = { + [712] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720900, .flow_pattern_id = 0, @@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [551] = { + [713] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 0, @@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [552] = { + [714] = { .class_hid = BNXT_ULP_CLASS_HID_475c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720964, .flow_pattern_id = 0, @@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [553] = { + [715] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 0, @@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [554] = { + [716] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917508, .flow_pattern_id = 0, @@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [555] = { + [717] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 0, @@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [556] = { + [718] = { .class_hid = BNXT_ULP_CLASS_HID_492c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917572, .flow_pattern_id = 0, @@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [557] = { + [719] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 0, @@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [558] = { + [720] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983044, .flow_pattern_id = 0, @@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [559] = { + [721] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 0, @@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [560] = { + [722] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983108, .flow_pattern_id = 0, @@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [561] = { + [723] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 1, @@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [562] = { + [724] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 1, @@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [563] = { + [725] = { .class_hid = BNXT_ULP_CLASS_HID_0686, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 1, @@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [564] = { + [726] = { .class_hid = BNXT_ULP_CLASS_HID_540e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 1, @@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [565] = { + [727] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 1, @@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [566] = { + [728] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 1, @@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [567] = { + [729] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [568] = { + [730] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 1, @@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [569] = { + [731] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 1, @@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [570] = { + [732] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 1, @@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [571] = { + [733] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 1, @@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [572] = { + [734] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 1, @@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [573] = { + [735] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 1, @@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [574] = { + [736] = { .class_hid = BNXT_ULP_CLASS_HID_548a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 1, @@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [575] = { + [737] = { .class_hid = BNXT_ULP_CLASS_HID_3356, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 1, @@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [576] = { + [738] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 1, @@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [577] = { + [739] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 1, @@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [578] = { + [740] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 1, @@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [579] = { + [741] = { .class_hid = BNXT_ULP_CLASS_HID_2812, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 1, @@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [580] = { + [742] = { .class_hid = BNXT_ULP_CLASS_HID_338a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 1, @@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [581] = { + [743] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 1, @@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [582] = { + [744] = { .class_hid = BNXT_ULP_CLASS_HID_546e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 1, @@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [583] = { + [745] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [584] = { + [746] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 1, @@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [585] = { + [747] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 1, @@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [586] = { + [748] = { .class_hid = BNXT_ULP_CLASS_HID_746a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 1, @@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [587] = { + [749] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [588] = { + [750] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 1, @@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [589] = { + [751] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 1, @@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [590] = { + [752] = { .class_hid = BNXT_ULP_CLASS_HID_576a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 1, @@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [591] = { + [753] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 1, @@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [592] = { + [754] = { .class_hid = BNXT_ULP_CLASS_HID_192e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 1, @@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [593] = { + [755] = { .class_hid = BNXT_ULP_CLASS_HID_197a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 1, @@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [594] = { + [756] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 1, @@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [595] = { + [757] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 1, @@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [596] = { + [758] = { .class_hid = BNXT_ULP_CLASS_HID_306a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 1, @@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [597] = { + [759] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 1, @@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [598] = { + [760] = { .class_hid = BNXT_ULP_CLASS_HID_544e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 1, @@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [599] = { + [761] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [600] = { + [762] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 1, @@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [601] = { + [763] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 1, @@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [602] = { + [764] = { .class_hid = BNXT_ULP_CLASS_HID_744a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 1, @@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [603] = { + [765] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [604] = { + [766] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 1, @@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [605] = { + [767] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 1, @@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [606] = { + [768] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 1, @@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [607] = { + [769] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [608] = { + [770] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 1, @@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [609] = { + [771] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 1, @@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [610] = { + [772] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 1, @@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [611] = { + [773] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [612] = { + [774] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 1, @@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [613] = { + [775] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 1, @@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [614] = { + [776] = { .class_hid = BNXT_ULP_CLASS_HID_166c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 1, @@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [615] = { + [777] = { .class_hid = BNXT_ULP_CLASS_HID_233c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 1, @@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [616] = { + [778] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 1, @@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [617] = { + [779] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 1, @@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [618] = { + [780] = { .class_hid = BNXT_ULP_CLASS_HID_3660, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 1, @@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [619] = { + [781] = { .class_hid = BNXT_ULP_CLASS_HID_4330, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 1, @@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [620] = { + [782] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 1, @@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [621] = { + [783] = { .class_hid = BNXT_ULP_CLASS_HID_5584, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 1, @@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [622] = { + [784] = { .class_hid = BNXT_ULP_CLASS_HID_2198, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 1, @@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [623] = { + [785] = { .class_hid = BNXT_ULP_CLASS_HID_7588, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 1, @@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [624] = { + [786] = { .class_hid = BNXT_ULP_CLASS_HID_419c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 1, @@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [625] = { + [787] = { .class_hid = BNXT_ULP_CLASS_HID_7758, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 1, @@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [626] = { + [788] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 1, @@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [627] = { + [789] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 1, @@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [628] = { + [790] = { .class_hid = BNXT_ULP_CLASS_HID_1864, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 1, @@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [629] = { + [791] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 1, @@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [630] = { + [792] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 1, @@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [631] = { + [793] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 1, @@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [632] = { + [794] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 1, @@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [633] = { + [795] = { .class_hid = BNXT_ULP_CLASS_HID_529c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 1, @@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [634] = { + [796] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 1, @@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [635] = { + [797] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 1, @@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [636] = { + [798] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 1, @@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [637] = { + [799] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 1, @@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [638] = { + [800] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 1, @@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [639] = { + [801] = { .class_hid = BNXT_ULP_CLASS_HID_4530, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [640] = { + [802] = { .class_hid = BNXT_ULP_CLASS_HID_5124, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 1, @@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [641] = { + [803] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 1, @@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [642] = { + [804] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 1, @@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [643] = { + [805] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [644] = { + [806] = { .class_hid = BNXT_ULP_CLASS_HID_7118, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 1, @@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [645] = { + [807] = { .class_hid = BNXT_ULP_CLASS_HID_0998, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 1, @@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [646] = { + [808] = { .class_hid = BNXT_ULP_CLASS_HID_158c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 1, @@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [647] = { + [809] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 1, @@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [648] = { + [810] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 1, @@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [649] = { + [811] = { .class_hid = BNXT_ULP_CLASS_HID_299c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 1, @@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [650] = { + [812] = { .class_hid = BNXT_ULP_CLASS_HID_3580, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 1, @@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [651] = { + [813] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 1, @@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [652] = { + [814] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 1, @@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [653] = { + [815] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 1, @@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [654] = { + [816] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 1, @@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [655] = { + [817] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 1, @@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [656] = { + [818] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 1, @@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [657] = { + [819] = { .class_hid = BNXT_ULP_CLASS_HID_7778, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 1, @@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [658] = { + [820] = { .class_hid = BNXT_ULP_CLASS_HID_438c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 1, @@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [659] = { + [821] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 1, @@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [660] = { + [822] = { .class_hid = BNXT_ULP_CLASS_HID_1844, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 1, @@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [661] = { + [823] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 1, @@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [662] = { + [824] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 1, @@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [663] = { + [825] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 1, @@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [664] = { + [826] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 1, @@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [665] = { + [827] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 1, @@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [666] = { + [828] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 1, @@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [667] = { + [829] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 1, @@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [668] = { + [830] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 1, @@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [669] = { + [831] = { .class_hid = BNXT_ULP_CLASS_HID_3866, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC } }, - [670] = { + [832] = { .class_hid = BNXT_ULP_CLASS_HID_381e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC } }, - [671] = { + [833] = { .class_hid = BNXT_ULP_CLASS_HID_3860, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC } }, - [672] = { + [834] = { .class_hid = BNXT_ULP_CLASS_HID_0454, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID } }, - [673] = { + [835] = { .class_hid = BNXT_ULP_CLASS_HID_3818, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC } }, - [674] = { + [836] = { .class_hid = BNXT_ULP_CLASS_HID_042c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID } }, - [675] = { + [837] = { .class_hid = BNXT_ULP_CLASS_HID_3846, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC } }, - [676] = { + [838] = { .class_hid = BNXT_ULP_CLASS_HID_387e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC } }, - [677] = { + [839] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC } }, - [678] = { + [840] = { .class_hid = BNXT_ULP_CLASS_HID_385e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC } }, - [679] = { + [841] = { .class_hid = BNXT_ULP_CLASS_HID_3840, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC } }, - [680] = { + [842] = { .class_hid = BNXT_ULP_CLASS_HID_0474, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID } }, - [681] = { + [843] = { .class_hid = BNXT_ULP_CLASS_HID_3878, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC } }, - [682] = { + [844] = { .class_hid = BNXT_ULP_CLASS_HID_044c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID } }, - [683] = { + [845] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC } }, - [684] = { + [846] = { .class_hid = BNXT_ULP_CLASS_HID_0794, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID } }, - [685] = { + [847] = { .class_hid = BNXT_ULP_CLASS_HID_3858, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC } }, - [686] = { + [848] = { .class_hid = BNXT_ULP_CLASS_HID_046c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID } } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index b6db49cc5d..e55d0923a5 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -11,13 +11,13 @@ #define BNXT_ULP_REGFILE_MAX_SZ 40 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 10 +#define BNXT_ULP_GEN_TBL_MAX_SZ 12 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849 #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 -#define BNXT_ULP_CLASS_HID_SHFTR 23 -#define BNXT_ULP_CLASS_HID_SHFTL 23 +#define BNXT_ULP_CLASS_HID_SHFTR 24 +#define BNXT_ULP_CLASS_HID_SHFTL 24 #define BNXT_ULP_CLASS_HID_MASK 32767 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 @@ -36,14 +36,14 @@ #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 #define BNXT_ULP_APP_ID_SHIFT 4 -#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 -#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495 -#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43 -#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49 +#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6 #define ULP_THOR_CLASS_TBL_LIST_SIZE 33 #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 8 @@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000, BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000 + BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 }; enum bnxt_ulp_accept_opc { @@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60, BNXT_ULP_CF_IDX_WC_MATCH = 61, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62, - BNXT_ULP_CF_IDX_F1_DMAC = 63, - BNXT_ULP_CF_IDX_LAST = 64 + BNXT_ULP_CF_IDX_TUNNEL_ID = 63, + BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64, + BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65, + BNXT_ULP_CF_IDX_LAST = 66 }; enum bnxt_ulp_cond_list_opc { @@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc { BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7, BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8, BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9, - BNXT_ULP_FUNC_OPC_LAST = 10 + BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10, + BNXT_ULP_FUNC_OPC_LAST = 11 }; enum bnxt_ulp_func_src { @@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc { BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2, BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3, BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4, - BNXT_ULP_TCAM_TBL_OPC_LAST = 5 + BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5, + BNXT_ULP_TCAM_TBL_OPC_LAST = 6 }; enum bnxt_ulp_template_type { @@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5 }; enum bnxt_ulp_act_prop_sz { @@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_15db = 0x15db, BNXT_ULP_CLASS_HID_1151 = 0x1151, BNXT_ULP_CLASS_HID_315d = 0x315d, + BNXT_ULP_CLASS_HID_3612 = 0x3612, + BNXT_ULP_CLASS_HID_66da = 0x66da, + BNXT_ULP_CLASS_HID_6165 = 0x6165, + BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1, + BNXT_ULP_CLASS_HID_09cd = 0x09cd, + BNXT_ULP_CLASS_HID_3845 = 0x3845, + BNXT_ULP_CLASS_HID_11e9 = 0x11e9, + BNXT_ULP_CLASS_HID_4361 = 0x4361, + BNXT_ULP_CLASS_HID_218d = 0x218d, + BNXT_ULP_CLASS_HID_5105 = 0x5105, + BNXT_ULP_CLASS_HID_0c89 = 0x0c89, + BNXT_ULP_CLASS_HID_3e81 = 0x3e81, + BNXT_ULP_CLASS_HID_1dad = 0x1dad, + BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5, + BNXT_ULP_CLASS_HID_25c9 = 0x25c9, + BNXT_ULP_CLASS_HID_57c1 = 0x57c1, + BNXT_ULP_CLASS_HID_33ed = 0x33ed, + BNXT_ULP_CLASS_HID_65e5 = 0x65e5, + BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9, + BNXT_ULP_CLASS_HID_261d = 0x261d, + BNXT_ULP_CLASS_HID_0571 = 0x0571, + BNXT_ULP_CLASS_HID_34f9 = 0x34f9, + BNXT_ULP_CLASS_HID_1d55 = 0x1d55, + BNXT_ULP_CLASS_HID_4fdd = 0x4fdd, + BNXT_ULP_CLASS_HID_2d31 = 0x2d31, + BNXT_ULP_CLASS_HID_5db9 = 0x5db9, + BNXT_ULP_CLASS_HID_0035 = 0x0035, + BNXT_ULP_CLASS_HID_323d = 0x323d, + BNXT_ULP_CLASS_HID_1111 = 0x1111, + BNXT_ULP_CLASS_HID_4019 = 0x4019, + BNXT_ULP_CLASS_HID_2975 = 0x2975, + BNXT_ULP_CLASS_HID_5b7d = 0x5b7d, + BNXT_ULP_CLASS_HID_3f51 = 0x3f51, + BNXT_ULP_CLASS_HID_6959 = 0x6959, + BNXT_ULP_CLASS_HID_0e85 = 0x0e85, + BNXT_ULP_CLASS_HID_380d = 0x380d, + BNXT_ULP_CLASS_HID_1f21 = 0x1f21, + BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9, + BNXT_ULP_CLASS_HID_1705 = 0x1705, + BNXT_ULP_CLASS_HID_418d = 0x418d, + BNXT_ULP_CLASS_HID_2721 = 0x2721, + BNXT_ULP_CLASS_HID_57a9 = 0x57a9, + BNXT_ULP_CLASS_HID_1a25 = 0x1a25, + BNXT_ULP_CLASS_HID_342d = 0x342d, + BNXT_ULP_CLASS_HID_2b01 = 0x2b01, + BNXT_ULP_CLASS_HID_5a09 = 0x5a09, + BNXT_ULP_CLASS_HID_2325 = 0x2325, + BNXT_ULP_CLASS_HID_5d2d = 0x5d2d, + BNXT_ULP_CLASS_HID_3101 = 0x3101, + BNXT_ULP_CLASS_HID_6309 = 0x6309, + BNXT_ULP_CLASS_HID_0bad = 0x0bad, + BNXT_ULP_CLASS_HID_2535 = 0x2535, + BNXT_ULP_CLASS_HID_1869 = 0x1869, + BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1, + BNXT_ULP_CLASS_HID_136d = 0x136d, + BNXT_ULP_CLASS_HID_43f5 = 0x43f5, + BNXT_ULP_CLASS_HID_2129 = 0x2129, + BNXT_ULP_CLASS_HID_53b1 = 0x53b1, + BNXT_ULP_CLASS_HID_072d = 0x072d, + BNXT_ULP_CLASS_HID_3135 = 0x3135, + BNXT_ULP_CLASS_HID_1429 = 0x1429, + BNXT_ULP_CLASS_HID_4731 = 0x4731, + BNXT_ULP_CLASS_HID_2f6d = 0x2f6d, + BNXT_ULP_CLASS_HID_5f75 = 0x5f75, + BNXT_ULP_CLASS_HID_3d69 = 0x3d69, + BNXT_ULP_CLASS_HID_6f71 = 0x6f71, + BNXT_ULP_CLASS_HID_0dbd = 0x0dbd, + BNXT_ULP_CLASS_HID_3f25 = 0x3f25, + BNXT_ULP_CLASS_HID_1239 = 0x1239, + BNXT_ULP_CLASS_HID_4da1 = 0x4da1, + BNXT_ULP_CLASS_HID_153d = 0x153d, + BNXT_ULP_CLASS_HID_45a5 = 0x45a5, + BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9, + BNXT_ULP_CLASS_HID_55a1 = 0x55a1, + BNXT_ULP_CLASS_HID_193d = 0x193d, + BNXT_ULP_CLASS_HID_4b25 = 0x4b25, + BNXT_ULP_CLASS_HID_2e39 = 0x2e39, + BNXT_ULP_CLASS_HID_5921 = 0x5921, + BNXT_ULP_CLASS_HID_213d = 0x213d, + BNXT_ULP_CLASS_HID_5125 = 0x5125, + BNXT_ULP_CLASS_HID_3739 = 0x3739, + BNXT_ULP_CLASS_HID_093d = 0x093d, + BNXT_ULP_CLASS_HID_684d = 0x684d, + BNXT_ULP_CLASS_HID_2389 = 0x2389, + BNXT_ULP_CLASS_HID_00e5 = 0x00e5, + BNXT_ULP_CLASS_HID_316d = 0x316d, + BNXT_ULP_CLASS_HID_18c1 = 0x18c1, + BNXT_ULP_CLASS_HID_4a49 = 0x4a49, + BNXT_ULP_CLASS_HID_28a5 = 0x28a5, + BNXT_ULP_CLASS_HID_582d = 0x582d, + BNXT_ULP_CLASS_HID_05a1 = 0x05a1, + BNXT_ULP_CLASS_HID_37a9 = 0x37a9, + BNXT_ULP_CLASS_HID_1485 = 0x1485, + BNXT_ULP_CLASS_HID_458d = 0x458d, + BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1, + BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9, + BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5, + BNXT_ULP_CLASS_HID_6ccd = 0x6ccd, + BNXT_ULP_CLASS_HID_0b11 = 0x0b11, + BNXT_ULP_CLASS_HID_3d99 = 0x3d99, + BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5, + BNXT_ULP_CLASS_HID_4b3d = 0x4b3d, + BNXT_ULP_CLASS_HID_1291 = 0x1291, + BNXT_ULP_CLASS_HID_4419 = 0x4419, + BNXT_ULP_CLASS_HID_22b5 = 0x22b5, + BNXT_ULP_CLASS_HID_523d = 0x523d, + BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1, + BNXT_ULP_CLASS_HID_31b9 = 0x31b9, + BNXT_ULP_CLASS_HID_2e95 = 0x2e95, + BNXT_ULP_CLASS_HID_5f9d = 0x5f9d, + BNXT_ULP_CLASS_HID_26b1 = 0x26b1, + BNXT_ULP_CLASS_HID_58b9 = 0x58b9, + BNXT_ULP_CLASS_HID_3495 = 0x3495, + BNXT_ULP_CLASS_HID_669d = 0x669d, + BNXT_ULP_CLASS_HID_0e39 = 0x0e39, + BNXT_ULP_CLASS_HID_20a1 = 0x20a1, + BNXT_ULP_CLASS_HID_1dfd = 0x1dfd, + BNXT_ULP_CLASS_HID_4e65 = 0x4e65, + BNXT_ULP_CLASS_HID_16f9 = 0x16f9, + BNXT_ULP_CLASS_HID_4661 = 0x4661, + BNXT_ULP_CLASS_HID_24bd = 0x24bd, + BNXT_ULP_CLASS_HID_5625 = 0x5625, + BNXT_ULP_CLASS_HID_02b9 = 0x02b9, + BNXT_ULP_CLASS_HID_34a1 = 0x34a1, + BNXT_ULP_CLASS_HID_11bd = 0x11bd, + BNXT_ULP_CLASS_HID_42a5 = 0x42a5, + BNXT_ULP_CLASS_HID_2af9 = 0x2af9, + BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1, + BNXT_ULP_CLASS_HID_38fd = 0x38fd, + BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5, + BNXT_ULP_CLASS_HID_0829 = 0x0829, + BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1, + BNXT_ULP_CLASS_HID_17ad = 0x17ad, + BNXT_ULP_CLASS_HID_4835 = 0x4835, + BNXT_ULP_CLASS_HID_10a9 = 0x10a9, + BNXT_ULP_CLASS_HID_4031 = 0x4031, + BNXT_ULP_CLASS_HID_3e2d = 0x3e2d, + BNXT_ULP_CLASS_HID_5035 = 0x5035, + BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9, + BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1, + BNXT_ULP_CLASS_HID_2bad = 0x2bad, + BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5, + BNXT_ULP_CLASS_HID_24a9 = 0x24a9, + BNXT_ULP_CLASS_HID_54b1 = 0x54b1, + BNXT_ULP_CLASS_HID_32ad = 0x32ad, + BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9, + BNXT_ULP_CLASS_HID_7f35 = 0x7f35, + BNXT_ULP_CLASS_HID_34f1 = 0x34f1, + BNXT_ULP_CLASS_HID_179d = 0x179d, + BNXT_ULP_CLASS_HID_2615 = 0x2615, + BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9, + BNXT_ULP_CLASS_HID_5d31 = 0x5d31, + BNXT_ULP_CLASS_HID_3fdd = 0x3fdd, + BNXT_ULP_CLASS_HID_4f55 = 0x4f55, + BNXT_ULP_CLASS_HID_12d9 = 0x12d9, + BNXT_ULP_CLASS_HID_20d1 = 0x20d1, + BNXT_ULP_CLASS_HID_03fd = 0x03fd, + BNXT_ULP_CLASS_HID_52f5 = 0x52f5, + BNXT_ULP_CLASS_HID_3b99 = 0x3b99, + BNXT_ULP_CLASS_HID_4991 = 0x4991, + BNXT_ULP_CLASS_HID_2dbd = 0x2dbd, + BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5, BNXT_ULP_CLASS_HID_34c6 = 0x34c6, BNXT_ULP_CLASS_HID_0c22 = 0x0c22, BNXT_ULP_CLASS_HID_1cbe = 0x1cbe, @@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid { }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3, - BNXT_ULP_DF_TPL_DEFAULT_VFR = 4 + BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4, + BNXT_ULP_DF_TPL_DEFAULT_VFR = 5 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h index 115bdc644c..1d7bbfe2cc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ @@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask { BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 }; enum bnxt_ulp_hf_0_2_1_bitmask { BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000 }; enum bnxt_ulp_hf_0_2_2_bitmask { BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000 }; enum bnxt_ulp_hf_0_2_3_bitmask { BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000 }; enum bnxt_ulp_hf_0_2_4_bitmask { BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000 + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000 }; -enum bnxt_ulp_hf_0_2_5_bitmask { - BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000 +enum bnxt_ulp_hf_0_3_0_bitmask { + BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; -enum bnxt_ulp_hf_0_2_6_bitmask { - BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 +enum bnxt_ulp_hf_0_3_1_bitmask { + BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; -enum bnxt_ulp_hf_0_2_7_bitmask { - BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 +enum bnxt_ulp_hf_0_3_2_bitmask { + BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 }; -enum bnxt_ulp_hf_0_2_8_bitmask { - BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000 +enum bnxt_ulp_hf_0_3_3_bitmask { + BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; -enum bnxt_ulp_hf_0_2_9_bitmask { - BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000 +enum bnxt_ulp_hf_0_3_4_bitmask { + BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000 }; -enum bnxt_ulp_hf_0_2_10_bitmask { - BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 +enum bnxt_ulp_hf_0_3_5_bitmask { + BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000 }; -enum bnxt_ulp_hf_0_2_11_bitmask { - BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 +enum bnxt_ulp_hf_0_3_6_bitmask { + BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 +}; + +enum bnxt_ulp_hf_0_3_7_bitmask { + BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 +}; + +enum bnxt_ulp_hf_0_3_8_bitmask { + BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000 +}; + +enum bnxt_ulp_hf_0_3_9_bitmask { + BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf_0_3_10_bitmask { + BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 +}; + +enum bnxt_ulp_hf_0_3_11_bitmask { + BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 2debaea0ca..58b4dba63c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 0, .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE", + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 2, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE", + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 2, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = { [4098] = 2, [4100] = 3, [4102] = 4, - [4136] = 5, - [4138] = 6, - [4140] = 7, - [4142] = 8, - [4144] = 9, - [4146] = 10, - [4148] = 11, - [4150] = 12, + [4116] = 5, + [4118] = 6, + [4120] = 7, + [4122] = 8, + [4124] = 9, + [4126] = 10, + [4128] = 11, + [4130] = 12, + [4132] = 13, + [4134] = 14, + [4170] = 15, + [4172] = 16, + [4174] = 17, + [4176] = 18, + [4190] = 19, + [4191] = 20, + [4192] = 21, + [4193] = 22, [4224] = 0, [4225] = 1, - [4226] = 2, - [4228] = 3, - [4230] = 4, - [4244] = 5, - [4246] = 6, - [4248] = 7, - [4250] = 8, - [4252] = 9, - [4254] = 10, - [4256] = 11, - [4258] = 12, - [4260] = 13, - [4262] = 14, + [4227] = 20, + [4229] = 21, + [4231] = 22, + [4244] = 2, + [4245] = 23, + [4246] = 3, + [4247] = 24, + [4248] = 4, + [4249] = 25, + [4250] = 5, + [4251] = 26, + [4252] = 6, + [4253] = 27, + [4254] = 7, + [4255] = 28, + [4256] = 8, + [4257] = 29, + [4258] = 9, + [4259] = 30, + [4260] = 10, + [4261] = 31, + [4262] = 11, + [4263] = 32, + [4298] = 12, + [4300] = 13, + [4302] = 14, + [4304] = 15, + [4318] = 16, + [4319] = 17, + [4320] = 18, + [4321] = 19, [4352] = 0, [4353] = 1, - [4354] = 2, - [4356] = 3, - [4358] = 4, - [4392] = 8, - [4394] = 9, - [4396] = 10, - [4398] = 11, - [4400] = 12, - [4402] = 13, - [4404] = 14, - [4406] = 15, - [4434] = 5, - [4438] = 6, - [4442] = 7, + [4355] = 20, + [4357] = 21, + [4359] = 22, + [4372] = 2, + [4373] = 23, + [4374] = 3, + [4375] = 24, + [4376] = 4, + [4377] = 25, + [4378] = 5, + [4379] = 26, + [4380] = 6, + [4381] = 27, + [4382] = 7, + [4383] = 28, + [4384] = 8, + [4385] = 29, + [4386] = 9, + [4387] = 30, + [4388] = 10, + [4389] = 31, + [4390] = 11, + [4391] = 32, + [4409] = 33, + [4411] = 34, + [4413] = 35, + [4415] = 36, + [4417] = 37, + [4419] = 38, + [4421] = 39, + [4423] = 40, + [4425] = 41, + [4426] = 12, + [4428] = 13, + [4430] = 14, + [4432] = 15, + [4446] = 16, + [4447] = 17, + [4448] = 18, + [4449] = 19, [4480] = 0, [4481] = 1, - [4482] = 2, - [4484] = 3, - [4486] = 4, - [4500] = 8, - [4502] = 9, - [4504] = 10, - [4506] = 11, - [4508] = 12, - [4510] = 13, - [4512] = 14, - [4514] = 15, - [4516] = 16, - [4518] = 17, - [4562] = 5, - [4566] = 6, - [4570] = 7, + [4483] = 20, + [4485] = 21, + [4487] = 22, + [4500] = 2, + [4501] = 23, + [4502] = 3, + [4503] = 24, + [4504] = 4, + [4505] = 25, + [4506] = 5, + [4507] = 26, + [4508] = 6, + [4509] = 27, + [4510] = 7, + [4511] = 28, + [4512] = 8, + [4513] = 29, + [4514] = 9, + [4515] = 30, + [4516] = 10, + [4517] = 31, + [4518] = 11, + [4519] = 32, + [4554] = 12, + [4555] = 33, + [4556] = 13, + [4557] = 34, + [4558] = 14, + [4559] = 35, + [4560] = 15, + [4561] = 36, + [4574] = 16, + [4575] = 17, + [4576] = 18, + [4577] = 19, [4608] = 0, [4609] = 1, - [4610] = 2, - [4612] = 3, - [4614] = 4, - [4648] = 5, - [4650] = 6, - [4652] = 7, - [4654] = 8, - [4656] = 9, - [4658] = 10, - [4660] = 11, - [4662] = 12, - [4664] = 13, - [4666] = 14, - [4668] = 15, - [4670] = 16, - [4672] = 17, - [4674] = 18, - [4676] = 19, - [4678] = 20, - [4680] = 21, - [4736] = 0, - [4737] = 1, - [4738] = 2, - [4740] = 3, - [4742] = 4, - [4756] = 5, - [4758] = 6, - [4760] = 7, - [4762] = 8, - [4764] = 9, - [4766] = 10, - [4768] = 11, - [4770] = 12, - [4772] = 13, - [4774] = 14, - [4792] = 15, - [4794] = 16, - [4796] = 17, - [4798] = 18, - [4800] = 19, - [4802] = 20, - [4804] = 21, - [4806] = 22, - [4808] = 23, - [4864] = 0, - [4865] = 1, - [4866] = 2, - [4868] = 3, - [4870] = 4, - [4904] = 5, - [4906] = 6, - [4908] = 7, - [4910] = 8, - [4912] = 9, - [4914] = 10, - [4916] = 11, - [4918] = 12, - [4938] = 13, - [4940] = 14, - [4942] = 15, - [4944] = 16, - [4992] = 0, - [4993] = 1, - [4994] = 2, - [4996] = 3, - [4998] = 4, - [5012] = 5, - [5014] = 6, - [5016] = 7, - [5018] = 8, - [5020] = 9, - [5022] = 10, - [5024] = 11, - [5026] = 12, - [5028] = 13, - [5030] = 14, - [5066] = 15, - [5068] = 16, - [5070] = 17, - [5072] = 18, - [5120] = 0, - [5121] = 1, - [5122] = 2, - [5124] = 3, - [5126] = 4, - [5160] = 8, - [5162] = 9, - [5164] = 10, - [5166] = 11, - [5168] = 12, - [5170] = 13, - [5172] = 14, - [5174] = 15, - [5176] = 16, - [5178] = 17, - [5180] = 18, - [5182] = 19, - [5184] = 20, - [5186] = 21, - [5188] = 22, - [5190] = 23, - [5192] = 24, - [5202] = 5, - [5206] = 6, - [5210] = 7, - [5248] = 0, - [5249] = 1, - [5250] = 2, - [5252] = 3, - [5254] = 4, - [5268] = 8, - [5270] = 9, - [5272] = 10, - [5274] = 11, - [5276] = 12, - [5278] = 13, - [5280] = 14, - [5282] = 15, - [5284] = 16, - [5286] = 17, - [5304] = 18, - [5306] = 19, - [5308] = 20, - [5310] = 21, - [5312] = 22, - [5314] = 23, - [5316] = 24, - [5318] = 25, - [5320] = 26, - [5330] = 5, - [5334] = 6, - [5338] = 7, - [5376] = 0, - [5377] = 1, - [5378] = 2, - [5380] = 3, - [5382] = 4, - [5416] = 8, - [5418] = 9, - [5420] = 10, - [5422] = 11, - [5424] = 12, - [5426] = 13, - [5428] = 14, - [5430] = 15, - [5450] = 16, - [5452] = 17, - [5454] = 18, - [5456] = 19, - [5458] = 5, - [5462] = 6, - [5466] = 7, - [5504] = 0, - [5505] = 1, - [5506] = 2, - [5508] = 3, - [5510] = 4, - [5524] = 8, - [5526] = 9, - [5528] = 10, - [5530] = 11, - [5532] = 12, - [5534] = 13, - [5536] = 14, - [5538] = 15, - [5540] = 16, - [5542] = 17, - [5578] = 18, - [5580] = 19, - [5582] = 20, - [5584] = 21, - [5586] = 5, - [5590] = 6, - [5594] = 7 + [4611] = 20, + [4613] = 21, + [4615] = 22, + [4619] = 33, + [4621] = 34, + [4623] = 35, + [4625] = 36, + [4627] = 37, + [4628] = 2, + [4629] = 23, + [4630] = 3, + [4631] = 24, + [4632] = 4, + [4633] = 25, + [4634] = 5, + [4635] = 26, + [4636] = 6, + [4637] = 27, + [4638] = 7, + [4639] = 28, + [4640] = 8, + [4641] = 29, + [4642] = 9, + [4643] = 30, + [4644] = 10, + [4645] = 31, + [4646] = 11, + [4647] = 32, + [4682] = 12, + [4684] = 13, + [4686] = 14, + [4688] = 15, + [4702] = 16, + [4703] = 17, + [4704] = 18, + [4705] = 19, + [6144] = 0, + [6145] = 1, + [6146] = 2, + [6148] = 3, + [6150] = 4, + [6184] = 5, + [6186] = 6, + [6188] = 7, + [6190] = 8, + [6192] = 9, + [6194] = 10, + [6196] = 11, + [6198] = 12, + [6272] = 0, + [6273] = 1, + [6274] = 2, + [6276] = 3, + [6278] = 4, + [6292] = 5, + [6294] = 6, + [6296] = 7, + [6298] = 8, + [6300] = 9, + [6302] = 10, + [6304] = 11, + [6306] = 12, + [6308] = 13, + [6310] = 14, + [6400] = 0, + [6401] = 1, + [6402] = 2, + [6404] = 3, + [6406] = 4, + [6440] = 8, + [6442] = 9, + [6444] = 10, + [6446] = 11, + [6448] = 12, + [6450] = 13, + [6452] = 14, + [6454] = 15, + [6482] = 5, + [6486] = 6, + [6490] = 7, + [6528] = 0, + [6529] = 1, + [6530] = 2, + [6532] = 3, + [6534] = 4, + [6548] = 8, + [6550] = 9, + [6552] = 10, + [6554] = 11, + [6556] = 12, + [6558] = 13, + [6560] = 14, + [6562] = 15, + [6564] = 16, + [6566] = 17, + [6610] = 5, + [6614] = 6, + [6618] = 7, + [6656] = 0, + [6657] = 1, + [6658] = 2, + [6660] = 3, + [6662] = 4, + [6696] = 5, + [6698] = 6, + [6700] = 7, + [6702] = 8, + [6704] = 9, + [6706] = 10, + [6708] = 11, + [6710] = 12, + [6712] = 13, + [6714] = 14, + [6716] = 15, + [6718] = 16, + [6720] = 17, + [6722] = 18, + [6724] = 19, + [6726] = 20, + [6728] = 21, + [6784] = 0, + [6785] = 1, + [6786] = 2, + [6788] = 3, + [6790] = 4, + [6804] = 5, + [6806] = 6, + [6808] = 7, + [6810] = 8, + [6812] = 9, + [6814] = 10, + [6816] = 11, + [6818] = 12, + [6820] = 13, + [6822] = 14, + [6840] = 15, + [6842] = 16, + [6844] = 17, + [6846] = 18, + [6848] = 19, + [6850] = 20, + [6852] = 21, + [6854] = 22, + [6856] = 23, + [6912] = 0, + [6913] = 1, + [6914] = 2, + [6916] = 3, + [6918] = 4, + [6952] = 5, + [6954] = 6, + [6956] = 7, + [6958] = 8, + [6960] = 9, + [6962] = 10, + [6964] = 11, + [6966] = 12, + [6986] = 13, + [6988] = 14, + [6990] = 15, + [6992] = 16, + [7040] = 0, + [7041] = 1, + [7042] = 2, + [7044] = 3, + [7046] = 4, + [7060] = 5, + [7062] = 6, + [7064] = 7, + [7066] = 8, + [7068] = 9, + [7070] = 10, + [7072] = 11, + [7074] = 12, + [7076] = 13, + [7078] = 14, + [7114] = 15, + [7116] = 16, + [7118] = 17, + [7120] = 18, + [7168] = 0, + [7169] = 1, + [7170] = 2, + [7172] = 3, + [7174] = 4, + [7208] = 8, + [7210] = 9, + [7212] = 10, + [7214] = 11, + [7216] = 12, + [7218] = 13, + [7220] = 14, + [7222] = 15, + [7224] = 16, + [7226] = 17, + [7228] = 18, + [7230] = 19, + [7232] = 20, + [7234] = 21, + [7236] = 22, + [7238] = 23, + [7240] = 24, + [7250] = 5, + [7254] = 6, + [7258] = 7, + [7296] = 0, + [7297] = 1, + [7298] = 2, + [7300] = 3, + [7302] = 4, + [7316] = 8, + [7318] = 9, + [7320] = 10, + [7322] = 11, + [7324] = 12, + [7326] = 13, + [7328] = 14, + [7330] = 15, + [7332] = 16, + [7334] = 17, + [7352] = 18, + [7354] = 19, + [7356] = 20, + [7358] = 21, + [7360] = 22, + [7362] = 23, + [7364] = 24, + [7366] = 25, + [7368] = 26, + [7378] = 5, + [7382] = 6, + [7386] = 7, + [7424] = 0, + [7425] = 1, + [7426] = 2, + [7428] = 3, + [7430] = 4, + [7464] = 8, + [7466] = 9, + [7468] = 10, + [7470] = 11, + [7472] = 12, + [7474] = 13, + [7476] = 14, + [7478] = 15, + [7498] = 16, + [7500] = 17, + [7502] = 18, + [7504] = 19, + [7506] = 5, + [7510] = 6, + [7514] = 7, + [7552] = 0, + [7553] = 1, + [7554] = 2, + [7556] = 3, + [7558] = 4, + [7572] = 8, + [7574] = 9, + [7576] = 10, + [7578] = 11, + [7580] = 12, + [7582] = 13, + [7584] = 14, + [7586] = 15, + [7588] = 16, + [7590] = 17, + [7626] = 18, + [7628] = 19, + [7630] = 20, + [7632] = 21, + [7634] = 5, + [7638] = 6, + [7642] = 7 }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index e342f340d9..d20c4197fa 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 4 } }, - /* class_tid: 3, ingress */ - [3] = { + /* class_tid: 4, ingress */ + [4] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 15, .start_tbl_idx = 12, @@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .cond_start_idx = 8, .cond_nums = 1 } }, - /* class_tid: 4, egress */ - [4] = { + /* class_tid: 5, egress */ + [5] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 6, .start_tbl_idx = 27, @@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 38, .result_num_fields = 5 }, - { /* class_tid: 3, , table: int_full_act_record.0 */ + { /* class_tid: 4, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 17 }, - { /* class_tid: 3, , table: port_table.wr_0 */ + { /* class_tid: 4, , table: port_table.wr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, @@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 152, .result_num_fields = 5 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 0 }, - { /* class_tid: 3, , table: control.ing_0 */ + { /* class_tid: 4, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, , table: control.egr_0 */ + { /* class_tid: 4, , table: control.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: int_full_act_record.egr_0 */ + { /* class_tid: 4, , table: int_full_act_record.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 0 }, - { /* class_tid: 3, , table: control.egr_1 */ + { /* class_tid: 4, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 1 }, - { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.loopback */ + { /* class_tid: 5, , table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.vf_ing */ + { /* class_tid: 5, , table: int_full_act_record.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */ + { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = @@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 11 }, - { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_O_L4 }, - /* cond_reject: thor, class_tid: 3 */ + /* cond_reject: thor, class_tid: 4 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 3, control.ing_0 */ + /* cond_execute: class_tid: 4, control.ing_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, control.egr_0 */ + /* cond_execute: class_tid: 4, control.egr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 3, control.egr_1 */ + /* cond_execute: class_tid: 4, control.egr_1 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_reject: thor, class_tid: 4 */ + /* cond_reject: thor, class_tid: 5 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE @@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SKIP } }, - /* class_tid: 3, , table: port_table.wr_0 */ + /* class_tid: 4, , table: port_table.wr_0 */ { .field_info_mask = { .description = "dev.port_id", @@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { .description = "svif", @@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .field_info_mask = { .description = "etype", @@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { 1} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { .field_info_mask = { .description = "svif", @@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */ { .field_info_mask = { .description = "svif", @@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .field_info_mask = { .description = "etype", @@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: int_full_act_record.0 */ + /* class_tid: 4, , table: int_full_act_record.0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: port_table.wr_0 */ + /* class_tid: 4, , table: port_table.wr_0 */ { .description = "rid", .field_bit_size = 32, @@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "prof_func_id", .field_bit_size = 7, @@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, @@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, , table: int_full_act_record.egr_0 */ + /* class_tid: 4, , table: int_full_act_record.egr_0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "prof_func_id", .field_bit_size = 7, @@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, - /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.loopback */ + /* class_tid: 5, , table: int_full_act_record.loopback */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.vf_ing */ + /* class_tid: 5, , table: int_full_act_record.vf_ing */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */ + /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 29 }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 29 }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index b6d2afd55b..de924fe81a 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Mon May 17 15:54:03 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index 85b8950e49..7b6ee03a4b 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri May 14 10:26:31 2021 */ +/* date: Mon May 17 15:54:03 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 1 } }, - /* class_tid: 2, egress */ + /* class_tid: 2, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 15, @@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 24, .cond_nums = 1 } }, - /* class_tid: 3, ingress */ + /* class_tid: 3, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 22, + .num_tbls = 15, .start_tbl_idx = 33, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 30, + .cond_nums = 1 } + }, + /* class_tid: 4, ingress */ + [4] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 22, + .start_tbl_idx = 48, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 35, + .cond_start_idx = 41, .cond_nums = 0 } }, - /* class_tid: 4, egress */ - [4] = { + /* class_tid: 5, egress */ + [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 19, - .start_tbl_idx = 55, + .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 41, + .cond_start_idx = 47, .cond_nums = 0 } } }; @@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 2, , table: tunnel_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 5, + .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 25, - .cond_nums = 1 }, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 223, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 2, .ident_start_idx = 9, .ident_nums = 1 }, + { /* class_tid: 2, , table: control.tunnel_cache_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 25, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 2, , table: l2_cntxt_tcam.1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 225, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 127, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 10, + .ident_nums = 1 + }, + { /* class_tid: 2, , table: tunnel_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 238, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 2, + .result_start_idx = 140, + .result_bit_size = 52, + .result_num_fields = 3 + }, + { /* class_tid: 2, , table: control.flow_type_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 5, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 26, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, { /* class_tid: 2, , table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 224, + .key_start_idx = 240, .blob_key_bit_size = 73, .key_bit_size = 73, .key_num_fields = 5, - .ident_start_idx = 10, + .ident_start_idx = 11, .ident_nums = 1 }, - { /* class_tid: 2, , table: control.0 */ + { /* class_tid: 2, , table: control.mac_addr_cache_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { { /* class_tid: 2, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 229, + .key_start_idx = 245, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 127, + .result_start_idx = 143, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 11, - .ident_nums = 1 + .ident_start_idx = 12, + .ident_nums = 0 }, { /* class_tid: 2, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 242, + .key_start_idx = 258, .blob_key_bit_size = 73, .key_bit_size = 73, .key_num_fields = 5, - .result_start_idx = 140, + .result_start_idx = 156, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 2, , table: profile_tcam_cache.rd */ + { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 247, + .key_start_idx = 263, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, .ident_start_idx = 12, .ident_nums = 3 }, - { /* class_tid: 2, , table: control.gen_tbl_miss */ + { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 2, , table: control.conflict_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 4, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_EQ, - .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, - .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, - .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, - .func_dst_opr = BNXT_ULP_RF_IDX_CC }, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 2, , table: profile_tcam.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 250, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 144, - .result_bit_size = 38, - .result_num_fields = 17, - .ident_start_idx = 15, - .ident_nums = 1 - }, - { /* class_tid: 2, , table: profile_tcam.ipv6 */ + { /* class_tid: 2, , table: profile_tcam.f2 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 1, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 293, + .key_start_idx = 266, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 161, + .result_start_idx = 160, .result_bit_size = 38, - .result_num_fields = 17, - .ident_start_idx = 16, - .ident_nums = 1 + .result_num_fields = 17 }, - { /* class_tid: 2, , table: profile_tcam_cache.wr */ + { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 336, + .key_start_idx = 309, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 178, + .result_start_idx = 177, .result_bit_size = 122, .result_num_fields = 5 }, - { /* class_tid: 2, , table: em.ipv4 */ + { /* class_tid: 2, , table: em.tun */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, - .cond_nums = 2 }, + .cond_start_idx = 29, + .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 339, - .blob_key_bit_size = 176, - .key_bit_size = 176, - .key_num_fields = 10, - .result_start_idx = 183, + .key_start_idx = 312, + .blob_key_bit_size = 112, + .key_bit_size = 112, + .key_num_fields = 8, + .result_start_idx = 182, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, , table: eem.ipv4 */ + { /* class_tid: 2, , table: eem.tun */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, - .cond_nums = 2 }, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 30, + .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 349, + .key_start_idx = 320, .blob_key_bit_size = 448, .key_bit_size = 448, - .key_num_fields = 10, - .result_start_idx = 192, + .key_num_fields = 8, + .result_start_idx = 191, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, , table: em.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 31, .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 359, - .blob_key_bit_size = 416, - .key_bit_size = 416, - .key_num_fields = 11, - .result_start_idx = 201, - .result_bit_size = 64, - .result_num_fields = 9 + .key_start_idx = 328, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 15, + .ident_nums = 1 }, - { /* class_tid: 2, , table: eem.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, + { /* class_tid: 3, , table: mac_addr_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, + .cond_start_idx = 32, .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 370, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 210, - .result_bit_size = 64, - .result_num_fields = 9 + .key_start_idx = 329, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .ident_start_idx = 16, + .ident_nums = 1 }, - { /* class_tid: 3, , table: int_full_act_record.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 219, - .result_bit_size = 128, - .result_num_fields = 26 - }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 381, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 17, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: control.ing_0 */ + { /* class_tid: 3, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 32, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 382, + .key_start_idx = 334, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 245, + .result_start_idx = 200, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 17, .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + { /* class_tid: 3, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 395, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 258, + .key_start_idx = 347, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .result_start_idx = 213, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 262, - .result_bit_size = 32, - .result_num_fields = 1 - }, - { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: profile_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 33, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 263, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 352, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 18, + .ident_nums = 3 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: control.gen_tbl_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 2, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 264, - .result_bit_size = 32, - .result_num_fields = 1 + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 33, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: control.egr_0 */ + { /* class_tid: 3, , table: control.conflict_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 6, + .cond_true_goto = 4, + .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: int_full_act_record.egr_vfr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 265, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 3, , table: profile_tcam.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 2, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 396, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 18, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: control.egr_1 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 35, .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 355, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 217, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 21, + .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ + { /* class_tid: 3, , table: profile_tcam.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 397, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 291, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 18, - .ident_nums = 0 + .key_start_idx = 398, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 234, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 22, + .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + { /* class_tid: 3, , table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 410, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 304, - .result_bit_size = 62, - .result_num_fields = 4 + .key_start_idx = 441, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 251, + .result_bit_size = 122, + .result_num_fields = 5 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 3, , table: em.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 36, + .cond_nums = 2 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 411, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 18, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: control.egr_2 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 412, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 308, + .key_start_idx = 444, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 256, .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 18, - .ident_nums = 1 + .result_num_fields = 9 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 3, , table: eem.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 425, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 321, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 3, , table: int_full_act_record.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 325, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 351, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 454, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 10, + .result_start_idx = 265, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + { /* class_tid: 3, , table: em.ipv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 40, + .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 352, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 464, + .blob_key_bit_size = 416, + .key_bit_size = 416, + .key_num_fields = 11, + .result_start_idx = 274, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + { /* class_tid: 3, , table: eem.ipv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 0, @@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 41, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 353, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 475, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 11, + .result_start_idx = 283, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 4, , table: int_full_act_record.loopback */ + { /* class_tid: 4, , table: int_full_act_record.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 41, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 354, + .result_start_idx = 292, .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .result_num_fields = 26 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 426, + .key_start_idx = 486, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 19, + .ident_start_idx = 23, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.vf_0 */ + { /* class_tid: 4, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, @@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 427, + .key_start_idx = 487, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 380, + .result_start_idx = 318, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 19, + .ident_start_idx = 23, .ident_nums = 1 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 440, + .key_start_idx = 500, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 393, + .result_start_idx = 331, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 42, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 397, + .result_start_idx = 335, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 42, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 398, + .result_start_idx = 336, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 42, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 399, + .result_start_idx = 337, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.vf_ing */ + { /* class_tid: 4, , table: control.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 6, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 42, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, , table: int_full_act_record.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 400, + .result_start_idx = 338, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 441, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 426, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 20, - .ident_nums = 0 - }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 454, + .key_start_idx = 501, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 20, + .ident_start_idx = 24, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.vfr_0 */ + { /* class_tid: 4, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 43, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 455, + .key_start_idx = 502, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 439, + .result_start_idx = 364, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 20, + .ident_start_idx = 24, .ident_nums = 0 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 468, + .key_start_idx = 515, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 452, + .result_start_idx = 377, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 44, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 456, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12 + .key_start_idx = 516, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 24, + .ident_nums = 0 }, - { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { + { /* class_tid: 4, , table: control.egr_2 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 44, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 45, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 517, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 381, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 24, + .ident_nums = 1 + }, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 45, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 530, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 394, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 4, , table: int_full_act_record.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 468, + .result_start_idx = 398, .result_bit_size = 128, - .result_num_fields = 26 + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 424, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 425, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 426, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */ + { /* class_tid: 5, , table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 47, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 494, + .result_start_idx = 427, .result_bit_size = 128, - .result_num_fields = 26 + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 531, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 25, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: control.vf_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 47, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 469, + .key_start_idx = 532, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 520, + .result_start_idx = 453, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 20, - .ident_nums = 0 + .ident_start_idx = 25, + .ident_nums = 1 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 545, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 466, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 470, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 471, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 472, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 5, , table: int_full_act_record.vf_ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 473, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 482, + .key_start_idx = 546, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 533, + .result_start_idx = 499, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 20, + .ident_start_idx = 26, .ident_nums = 0 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 559, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 26, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: control.vfr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 48, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 560, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 512, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 26, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 573, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 525, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 529, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 + }, + { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 541, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 567, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 574, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 593, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 26, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 587, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 606, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 26, + .ident_nums = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { /* cond_reject: wh_plus, class_tid: 1 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, @@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH }, - /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */ + /* cond_execute: class_tid: 2, control.tunnel_cache_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.flow_type_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F1 + }, + /* cond_execute: class_tid: 2, control.mac_addr_cache_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, em.tun */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_reject: wh_plus, class_tid: 3 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, + /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, - /* cond_execute: class_tid: 2, control.0 */ + /* cond_execute: class_tid: 3, control.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.gen_tbl_miss */ + /* cond_execute: class_tid: 3, control.gen_tbl_miss */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.conflict_check */ + /* cond_execute: class_tid: 3, control.conflict_check */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_CC }, - /* cond_execute: class_tid: 2, profile_tcam.ipv4 */ + /* cond_execute: class_tid: 3, profile_tcam.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 2, em.ipv4 */ + /* cond_execute: class_tid: 3, em.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, }, @@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 2, eem.ipv4 */ + /* cond_execute: class_tid: 3, eem.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, }, @@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 2, em.ipv6 */ + /* cond_execute: class_tid: 3, em.ipv6 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, }, - /* cond_execute: class_tid: 3, control.ing_0 */ + /* cond_execute: class_tid: 4, control.ing_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, control.egr_0 */ + /* cond_execute: class_tid: 4, control.egr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 3, control.egr_1 */ + /* cond_execute: class_tid: 4, control.egr_1 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, control.egr_2 */ + /* cond_execute: class_tid: 4, control.egr_2 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */ + /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE @@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, control.vf_0 */ + /* cond_execute: class_tid: 5, control.vf_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, control.vfr_0 */ + /* cond_execute: class_tid: 5, control.vfr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS @@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, , table: tunnel_cache.rd */ { .field_info_mask = { .description = "svif", @@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, - /* class_tid: 2, , table: mac_addr_cache.rd */ { .field_info_mask = { - .description = "svif", + .description = "tunnel_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + 0xff} }, .field_info_spec = { - .description = "svif", + .description = "tunnel_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} } }, + /* class_tid: 2, , table: l2_cntxt_tcam.1 */ { .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} - } - }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "mac0_addr", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "svif", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "svif", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 2, , table: mac_addr_cache.wr */ + /* class_tid: 2, , table: tunnel_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} + } + }, + /* class_tid: 2, , table: mac_addr_cache.rd */ { .field_info_mask = { .description = "svif", @@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + 0xff} }, .field_info_spec = { .description = "tun_hdr", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac_addr", @@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 2, , table: profile_tcam_cache.rd */ + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 2, , table: profile_tcam.ipv4 */ { .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "l4_hdr_type", + .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_type", + .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_type", + .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l3_hdr_type", + .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "l3_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + 1} } }, + /* class_tid: 2, , table: mac_addr_cache.wr */ { .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_vtag_present", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_vtag_present", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, + .description = "vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, + .description = "vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, + /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ { .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 2, , table: profile_tcam.f2 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "l4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "l4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_err", + .description = "l4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_err", + .description = "l4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_valid", + .description = "l4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_valid", + .description = "l4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl4_hdr_error", + .description = "l3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_error", + .description = "l3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "l3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", + .description = "l3_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", + .description = "l3_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_src", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_ipv6_cmp_src", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "tl3_hdr_isIP", + .description = "l2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_isIP", + .description = "l2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_two_vtags", + .description = "l2_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_two_vtags", + .description = "l2_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_vtag_present", + .description = "l2_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_vtag_present", + .description = "l2_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_hdr_valid", + .description = "tun_hdr_err", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tl2_hdr_valid", + .description = "tun_hdr_err", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "hrec_next", + .description = "tun_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "hrec_next", + .description = "tun_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + ULP_WP_SYM_TL4_HDR_TYPE_UDP} } }, { .field_info_mask = { - .description = "agg_error", + .description = "tl4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "agg_error", + .description = "tl4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL4_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", + .description = "tl3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "valid", + .description = "tl3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 2, , table: profile_tcam.ipv6 */ { .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + 0xff} }, .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_error", + .description = "tl3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + 0xff} }, .field_info_spec = { - .description = "l4_hdr_error", + .description = "tl3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "l4_hdr_valid", + .description = "tl2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_valid", + .description = "tl2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_dst", + .description = "tl2_vtag_present", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_dst", + .description = "tl2_vtag_present", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV6} + ULP_WP_SYM_TL2_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "l3_hdr_error", + .description = "hrec_next", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_error", + .description = "hrec_next", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "l2_vtag_present", + .description = "agg_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_vtag_present", + .description = "agg_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_uc_mc_bc", + .description = "recycle_cnt", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_uc_mc_bc", + .description = "recycle_cnt", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_type", + .description = "pkt_type_0", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_hdr_type", + .description = "pkt_type_0", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "l2_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + 1} } }, + /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ { .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, + /* class_tid: 2, , table: em.tun */ { .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} }, .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 2, , table: eem.tun */ { .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 339, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 339, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} }, .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} } }, { .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, + /* class_tid: 3, , table: mac_addr_cache.rd */ { .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "agg_error", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "agg_error", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, + /* class_tid: 3, , table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, - /* class_tid: 2, , table: profile_tcam_cache.wr */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 2, , table: em.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} } }, { .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 32, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 1} }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 32, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 1} } }, + /* class_tid: 3, , table: mac_addr_cache.wr */ { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, - 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "one_tag", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "one_tag", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, - /* class_tid: 2, , table: eem.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, + /* class_tid: 3, , table: profile_tcam_cache.rd */ { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, + /* class_tid: 3, , table: profile_tcam.ipv4 */ { .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 2, , table: em.ipv6 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "l3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "l3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 128, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 128, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 128, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 128, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + 0xff} }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + ULP_WP_SYM_L2_HDR_VALID_YES} } }, - /* class_tid: 2, , table: eem.ipv6 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 35, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 35, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - }, - .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 128, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 128, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 128, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "tl4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "tl4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + 1} } }, + /* class_tid: 3, , table: profile_tcam.ipv6 */ { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "l3_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "l3_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff} }, .field_info_spec = { - .description = "valid", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } - }, - { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "tl4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "tl4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", + .description = "tl4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff} }, .field_info_spec = { - .description = "valid", + .description = "tl4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + 1} } }, + /* class_tid: 3, , table: profile_tcam_cache.wr */ { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, + /* class_tid: 3, , table: em.ipv4 */ { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 1} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ { .field_info_mask = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "mac0_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "mac0_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, , table: eem.ipv4 */ { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3.prot", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .field_info_mask = { - .description = "svif", + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "svif", + .description = "em_profile_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + /* class_tid: 3, , table: em.ipv6 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l2.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l2.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "mac1_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 2} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, , table: eem.ipv6 */ { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 35, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 35, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff, + 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.dst", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "l3.dst", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.src", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "l3.src", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, { @@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opr1 = { 1} } - } -}; - -struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { - /* class_tid: 1, , table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + }, + { + .description = "l2_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_pri", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_tpid", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "bd_act_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.ipv4 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.ipv6 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { - .description = "parif", + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 7} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ + { + .description = "wc_key_id", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 20} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, + /* class_tid: 1, , table: em.ipv4 */ { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "ext_flow_cntr", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "act_rec_int", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", - .field_bit_size = 1, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 3} }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l1_cacheable", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 1, , table: mac_addr_cache.wr */ + /* class_tid: 1, , table: eem.ipv4 */ { - .description = "rid", - .field_bit_size = 32, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "ext_flow_cntr", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (173 >> 8) & 0xff, + 173 & 0xff} }, - /* class_tid: 1, , table: profile_tcam.ipv4 */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .description = "wc_search_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.0", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, + /* class_tid: 1, , table: em.ipv6 */ { - .description = "em_key_mask.1", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "em_key_mask.2", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.3", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.4", - .field_bit_size = 1, + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} + 3} }, { - .description = "em_key_mask.5", + .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.6", + .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + 1} }, + /* class_tid: 1, , table: eem.ipv6 */ { - .description = "em_key_mask.7", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "em_key_mask.8", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.9", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", + .description = "act_rec_size", .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 3} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (413 >> 8) & 0xff, + 413 & 0xff} }, { - .description = "em_search_en", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 3} }, { - .description = "pl_byp_lkup_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, , table: profile_tcam.ipv6 */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 1, , table: em.vxlan */ { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "wc_search_en", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.0", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.1", - .field_bit_size = 1, + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.2", - .field_bit_size = 1, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.3", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.4", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + 3} }, { - .description = "em_key_mask.5", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.6", + .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + 1} }, + /* class_tid: 1, , table: eem.vxlan */ { - .description = "em_key_mask.7", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "em_key_mask.8", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.9", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", + .description = "act_rec_size", .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 7} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .description = "em_search_en", - .field_bit_size = 1, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (197 >> 8) & 0xff, + 197 & 0xff} }, - /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .description = "wc_search_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.0", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, + /* class_tid: 2, , table: l2_cntxt_tcam.1 */ { - .description = "em_key_mask.1", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.2", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.3", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.4", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.5", - .field_bit_size = 1, + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.6", - .field_bit_size = 1, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.7", - .field_bit_size = 1, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.8", - .field_bit_size = 1, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.9", + .description = "bd_act_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 20} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_search_en", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { 1} }, { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, , table: profile_tcam_cache.wr */ + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: tunnel_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "profile_tcam_index", + .description = "l2_cntxt_tcam_index", .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { - .description = "flow_sig_id", - .field_bit_size = 64, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, - /* class_tid: 1, , table: em.ipv4 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} }, { - .description = "ext_flow_cntr", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "key_size", - .field_bit_size = 9, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "bd_act_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, - /* class_tid: 1, , table: eem.ipv4 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ext_flow_cntr", - .field_bit_size = 1, + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, , table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, { - .description = "act_rec_int", - .field_bit_size = 1, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "key_size", - .field_bit_size = 9, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (173 >> 8) & 0xff, - 173 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, , table: profile_tcam.f2 */ { - .description = "reserved", - .field_bit_size = 11, + .description = "wc_key_id", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", + .description = "wc_search_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "em_key_mask.0", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, - /* class_tid: 1, , table: em.ipv6 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "em_key_mask.1", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + 1} }, { - .description = "ext_flow_cntr", + .description = "em_key_mask.2", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", + .description = "em_key_mask.3", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "em_key_mask.4", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "key_size", - .field_bit_size = 9, + .description = "em_key_mask.5", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "em_key_mask.6", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "em_key_mask.7", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", + .description = "em_key_mask.8", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "em_key_mask.9", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 8} }, - /* class_tid: 1, , table: eem.ipv6 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "ext_flow_cntr", + .description = "em_search_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "act_rec_int", + .description = "pl_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "key_size", - .field_bit_size = 9, + .description = "profile_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { - .description = "strength", - .field_bit_size = 2, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 3} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "l1_cacheable", - .field_bit_size = 1, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", - .field_bit_size = 1, + .description = "flow_sig_id", + .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 1} + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 1, , table: em.vxlan */ + /* class_tid: 2, , table: em.tun */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, , table: eem.vxlan */ + /* class_tid: 2, , table: eem.tun */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (197 >> 8) & 0xff, - 197 & 0xff} + (109 >> 8) & 0xff, + 109 & 0xff} }, { .description = "reserved", @@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: mac_addr_cache.wr */ + /* class_tid: 3, , table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: profile_tcam.ipv4 */ + /* class_tid: 3, , table: profile_tcam.ipv4 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: profile_tcam.ipv6 */ + /* class_tid: 3, , table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: profile_tcam_cache.wr */ + /* class_tid: 3, , table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 2, , table: em.ipv4 */ + /* class_tid: 3, , table: em.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: eem.ipv4 */ + /* class_tid: 3, , table: eem.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: em.ipv6 */ + /* class_tid: 3, , table: em.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: eem.ipv6 */ + /* class_tid: 3, , table: eem.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: int_full_act_record.ing_0 */ + /* class_tid: 4, , table: int_full_act_record.ing_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, @@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: int_full_act_record.egr_vfr */ + /* class_tid: 4, , table: int_full_act_record.egr_vfr */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .description = "rid", .field_bit_size = 32, @@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: int_full_act_record.egr_0 */ + /* class_tid: 4, , table: int_full_act_record.egr_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.loopback */ + /* class_tid: 5, , table: int_full_act_record.loopback */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.vf_ing */ + /* class_tid: 5, , table: int_full_act_record.vf_ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .description = "rid", .field_bit_size = 32, @@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */ + /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */ + /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, , table: tunnel_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, + /* class_tid: 2, , table: l2_cntxt_tcam.1 */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, /* class_tid: 2, , table: mac_addr_cache.rd */ { .description = "l2_cntxt_id", @@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ + /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ + { + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 + }, + { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 64, + .ident_bit_pos = 58 + }, + { + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 3, , table: mac_addr_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 3, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 2, , table: profile_tcam_cache.rd */ + /* class_tid: 3, , table: profile_tcam_cache.rd */ { .description = "em_profile_id", .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, @@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 32 }, - /* class_tid: 2, , table: profile_tcam.ipv4 */ + /* class_tid: 3, , table: profile_tcam.ipv4 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 2, , table: profile_tcam.ipv6 */ + /* class_tid: 3, , table: profile_tcam.ipv6 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 22c51976ac..d6b4f93d31 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, } /* Update the parent counters if it is child flow */ - if (sw_acc_tbl_entry->parent_flow_id) { + if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) { + uint32_t pc_idx; + /* Update the parent counters */ t_sw = sw_acc_tbl_entry; - if (ulp_flow_db_parent_flow_count_update(ctxt, - t_sw->parent_flow_id, + pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID; + if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx, t_sw->pkt_count, t_sw->byte_count)) { PMD_DRV_LOG(ERR, "Error updating parent counters\n"); @@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir, ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0; ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0; ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0; + ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0; ulp_fc_info->num_entries--; pthread_mutex_unlock(&ulp_fc_info->fc_lock); @@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, uint32_t hw_cntr_id = 0, sw_cntr_idx = 0; struct sw_acc_counter *sw_acc_tbl_entry; bool found_cntr_resource = false; + bool found_parent_flow = false; + uint32_t pc_idx = 0; ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); if (!ulp_fc_info) @@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, (params.resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT || params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT || - params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) { found_cntr_resource = true; break; } + if (params.resource_func == + BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) { + found_parent_flow = true; + pc_idx = params.resource_hndl; + } + } while (!rc && nxt_resource_index); bnxt_ulp_cntxt_release_fdb_lock(ctxt); @@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, dir = params.direction; hw_cntr_id = params.resource_hndl; - if (params.resource_sub_type == + if (!found_parent_flow && + params.resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { if (!ulp_fc_info->num_counters) return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count); @@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, sw_acc_tbl_entry->byte_count = 0; } pthread_mutex_unlock(&ulp_fc_info->fc_lock); - } else if (params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) { + } else if (found_parent_flow && + params.resource_sub_type == + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { /* Get stats from the parent child table */ - ulp_flow_db_parent_flow_count_get(ctxt, flow_id, + ulp_flow_db_parent_flow_count_get(ctxt, pc_idx, &count->hits, &count->bytes, count->reset); - count->hits_set = 1; - count->bytes_set = 1; + if (count->hits) + count->hits_set = 1; + if (count->bytes) + count->bytes_set = 1; } else { /* TBD: Handle External counters */ rc = -EINVAL; @@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, * * hw_cntr_id [in] The HW flow counter ID * - * fid [in] parent flow id + * pc_idx [in] parent child db index * */ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir, uint32_t hw_cntr_id, - uint32_t fid) + uint32_t pc_idx) { struct bnxt_ulp_fc_info *ulp_fc_info; uint32_t sw_cntr_idx; @@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, pthread_mutex_lock(&ulp_fc_info->fc_lock); sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx; if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) { - ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid; + pc_idx |= FLOW_CNTR_PC_FLOW_VALID; + ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx; } else { BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n", - hw_cntr_id, fid); + hw_cntr_id, pc_idx); rc = -ENOENT; } pthread_mutex_unlock(&ulp_fc_info->fc_lock); diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h index 448d05c118..9825ed2a27 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h @@ -21,12 +21,14 @@ #define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \ (d)->byte_count_shift) +#define FLOW_CNTR_PC_FLOW_VALID 0x1000000 + struct sw_acc_counter { uint64_t pkt_count; uint64_t byte_count; bool valid; uint32_t hw_cntr_id; - uint32_t parent_flow_id; + uint32_t pc_flow_idx; }; struct hw_fc_mem_info { @@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx, * * hw_cntr_id [in] The HW flow counter ID * - * fid [in] parent flow id + * pc_idx [in] parent child db index * */ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir, uint32_t hw_cntr_id, - uint32_t fid); + uint32_t pc_idx); #endif /* _ULP_FC_MGR_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 016c86fb6e..9e6bd90aea 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -386,101 +386,6 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db) } } -/* internal validation function for parent flow tbl */ -static struct bnxt_ulp_flow_db * -ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt, - uint32_t fid) -{ - struct bnxt_ulp_flow_db *flow_db; - - flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); - if (!flow_db) { - BNXT_TF_DBG(ERR, "Invalid Arguments\n"); - return NULL; - } - - /* check for max flows */ - if (fid >= flow_db->flow_tbl.num_flows || !fid) { - BNXT_TF_DBG(ERR, "Invalid flow index\n"); - return NULL; - } - - /* No support for parent child db then just exit */ - if (!flow_db->parent_child_db.entries_count) { - BNXT_TF_DBG(ERR, "parent child db not supported\n"); - return NULL; - } - - return flow_db; -} - -/* - * Set the tunnel index in the parent flow - * - * ulp_ctxt [in] Ptr to ulp_context - * parent_idx [in] The parent index of the parent flow entry - * - * returns index on success and negative on failure. - */ -static int32_t -ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_idx, uint8_t tun_idx) -{ - struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - - flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); - if (!flow_db) { - BNXT_TF_DBG(ERR, "Invalid Arguments\n"); - return -EINVAL; - } - - /* check for parent idx validity */ - p_pdb = &flow_db->parent_child_db; - if (parent_idx >= p_pdb->entries_count || - !p_pdb->parent_flow_tbl[parent_idx].parent_fid) { - BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx); - return -EINVAL; - } - - p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx; - return 0; -} - -/* - * Get the tunnel index from the parent flow - * - * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry - * - * returns 0 if counter accum is set else -1. - */ -static int32_t -ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, uint8_t *tun_idx) -{ - struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx; - - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid); - if (!flow_db) { - BNXT_TF_DBG(ERR, "parent child db validation failed\n"); - return -EINVAL; - } - - p_pdb = &flow_db->parent_child_db; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) { - *tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx; - return 0; - } - } - - return -EINVAL; -} - /* * Initialize the flow database. Memory is allocated in this * call and assigned to the flow database. @@ -783,9 +688,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, struct bnxt_ulp_flow_tbl *flow_tbl; struct ulp_fdb_resource_info *nxt_resource, *fid_resource; uint32_t nxt_idx = 0; - struct bnxt_tun_cache_entry *tun_tbl; - uint8_t tun_idx = 0; - int rc; flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); if (!flow_db) { @@ -862,18 +764,6 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt, params->resource_hndl); } - if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) { - tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt); - if (!tun_tbl) - return -EINVAL; - - rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx); - if (rc) - return rc; - - ulp_clear_tun_entry(tun_tbl, tun_idx); - } - /* all good, return success */ return 0; } @@ -892,7 +782,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, enum bnxt_ulp_fdb_type flow_type, uint32_t fid) { - struct bnxt_tun_cache_entry *tun_tbl; struct bnxt_ulp_flow_tbl *flow_tbl; struct bnxt_ulp_flow_db *flow_db; @@ -934,12 +823,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) ulp_flow_db_func_id_set(flow_db, fid, 0); - tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt); - if (!tun_tbl) - return -EINVAL; - - ulp_clear_tun_inner_entry(tun_tbl, fid); - #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid); #endif @@ -1307,24 +1190,84 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx, return 0; } +/* internal validation function for parent flow tbl */ +static struct ulp_fdb_parent_info * +ulp_flow_db_pc_db_entry_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t pc_idx) +{ + struct bnxt_ulp_flow_db *flow_db; + + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); + if (!flow_db) { + BNXT_TF_DBG(ERR, "Invalid Arguments\n"); + return NULL; + } + + /* check for max flows */ + if (pc_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) { + BNXT_TF_DBG(ERR, "Invalid tunnel index\n"); + return NULL; + } + + /* No support for parent child db then just exit */ + if (!flow_db->parent_child_db.entries_count) { + BNXT_TF_DBG(ERR, "parent child db not supported\n"); + return NULL; + } + if (!flow_db->parent_child_db.parent_flow_tbl[pc_idx].valid) { + BNXT_TF_DBG(ERR, "Not a valid tunnel index\n"); + return NULL; + } + + return &flow_db->parent_child_db.parent_flow_tbl[pc_idx]; +} + +/* internal validation function for parent flow tbl */ +static struct bnxt_ulp_flow_db * +ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt, + uint32_t tun_idx) +{ + struct bnxt_ulp_flow_db *flow_db; + + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); + if (!flow_db) { + BNXT_TF_DBG(ERR, "Invalid Arguments\n"); + return NULL; + } + + /* check for max flows */ + if (tun_idx >= BNXT_ULP_MAX_TUN_CACHE_ENTRIES) { + BNXT_TF_DBG(ERR, "Invalid tunnel index\n"); + return NULL; + } + + /* No support for parent child db then just exit */ + if (!flow_db->parent_child_db.entries_count) { + BNXT_TF_DBG(ERR, "parent child db not supported\n"); + return NULL; + } + + return flow_db; +} + /* * Allocate the entry in the parent-child database * * ulp_ctxt [in] Ptr to ulp_context - * fid [in] The flow id to the flow entry + * tun_idx [in] The tunnel index of the flow entry * * returns index on success and negative on failure. */ -int32_t -ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt, - uint32_t fid) +static int32_t +ulp_flow_db_pc_db_idx_alloc(struct bnxt_ulp_context *ulp_ctxt, + uint32_t tun_idx) { struct bnxt_ulp_flow_db *flow_db; struct ulp_fdb_parent_child_db *p_pdb; uint32_t idx, free_idx = 0; /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid); + flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, tun_idx); if (!flow_db) { BNXT_TF_DBG(ERR, "parent child db validation failed\n"); return -EINVAL; @@ -1332,11 +1275,11 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt, p_pdb = &flow_db->parent_child_db; for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) { - BNXT_TF_DBG(ERR, "fid is already allocated\n"); - return -EINVAL; + if (p_pdb->parent_flow_tbl[idx].valid && + p_pdb->parent_flow_tbl[idx].tun_idx == tun_idx) { + return idx; } - if (!p_pdb->parent_flow_tbl[idx].parent_fid && !free_idx) + if (!p_pdb->parent_flow_tbl[idx].valid && !free_idx) free_idx = idx + 1; } /* no free slots */ @@ -1347,132 +1290,148 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt, free_idx -= 1; /* set the Fid in the parent child */ - p_pdb->parent_flow_tbl[free_idx].parent_fid = fid; + p_pdb->parent_flow_tbl[free_idx].tun_idx = tun_idx; + p_pdb->parent_flow_tbl[free_idx].valid = 1; return free_idx; } /* * Free the entry in the parent-child database * - * ulp_ctxt [in] Ptr to ulp_context - * fid [in] The flow id to the flow entry + * pc_entry [in] Ptr to parent child db entry * - * returns 0 on success and negative on failure. + * returns none. */ -int32_t -ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt, - uint32_t fid) +static void +ulp_flow_db_pc_db_entry_free(struct bnxt_ulp_context *ulp_ctxt, + struct ulp_fdb_parent_info *pc_entry) { + struct bnxt_tun_cache_entry *tun_tbl; struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx; + uint64_t *tmp_bitset; - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid); - if (!flow_db) { - BNXT_TF_DBG(ERR, "parent child db validation failed\n"); - return -EINVAL; - } + /* free the tunnel entry */ + tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt); + if (tun_tbl) + ulp_tunnel_offload_entry_clear(tun_tbl, pc_entry->tun_idx); - p_pdb = &flow_db->parent_child_db; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) { - /* free the contents */ - p_pdb->parent_flow_tbl[idx].parent_fid = 0; - memset(p_pdb->parent_flow_tbl[idx].child_fid_bitset, - 0, p_pdb->child_bitset_size); - return 0; - } - } - BNXT_TF_DBG(ERR, "parent entry not found = %x\n", fid); - return -EINVAL; + /* free the child bitset*/ + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); + if (flow_db) + memset(pc_entry->child_fid_bitset, 0, + flow_db->parent_child_db.child_bitset_size); + + /* free the contents */ + tmp_bitset = pc_entry->child_fid_bitset; + memset(pc_entry, 0, sizeof(struct ulp_fdb_parent_info)); + pc_entry->child_fid_bitset = tmp_bitset; } /* - * Set or reset the child flow in the parent-child database + * Set or reset the parent flow in the parent-child database * * ulp_ctxt [in] Ptr to ulp_context + * pc_idx [in] The index to parent child db * parent_fid [in] The flow id of the parent flow entry - * child_fid [in] The flow id of the child flow entry * set_flag [in] Use 1 for setting child, 0 to reset * * returns zero on success and negative on failure. */ int32_t -ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt, +ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt, + uint32_t pc_idx, uint32_t parent_fid, - uint32_t child_fid, uint32_t set_flag) { + struct ulp_fdb_parent_info *pc_entry; struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx, a_idx; - uint64_t *t; - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid); + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); if (!flow_db) { BNXT_TF_DBG(ERR, "parent child db validation failed\n"); return -EINVAL; } /* check for fid validity */ - if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) { - BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid); + if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) { + BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid); return -EINVAL; } - p_pdb = &flow_db->parent_child_db; - a_idx = child_fid / ULP_INDEX_BITMAP_SIZE; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) { - t = p_pdb->parent_flow_tbl[idx].child_fid_bitset; - if (set_flag) - ULP_INDEX_BITMAP_SET(t[a_idx], child_fid); - else - ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid); - return 0; - } + /* validate the arguments and parent child entry */ + pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx); + if (!pc_entry) { + BNXT_TF_DBG(ERR, "failed to get the parent child entry\n"); + return -EINVAL; } - BNXT_TF_DBG(ERR, "Unable to set the parent-child flow %x:%x\n", - parent_fid, child_fid); - return -1; + + if (set_flag) { + pc_entry->parent_fid = parent_fid; + } else { + if (pc_entry->parent_fid != parent_fid) + BNXT_TF_DBG(ERR, "Panic: invalid parent id\n"); + pc_entry->parent_fid = 0; + + /* Free the parent child db entry if no user present */ + if (!pc_entry->f2_cnt) + ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry); + } + return 0; } /* - * Get the parent index from the parent-child database + * Set or reset the child flow in the parent-child database * * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry - * parent_idx [out] The parent index of parent flow entry + * pc_idx [in] The index to parent child db + * child_fid [in] The flow id of the child flow entry + * set_flag [in] Use 1 for setting child, 0 to reset * * returns zero on success and negative on failure. */ int32_t -ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, - uint32_t *parent_idx) +ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt, + uint32_t pc_idx, + uint32_t child_fid, + uint32_t set_flag) { + struct ulp_fdb_parent_info *pc_entry; struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx; + uint32_t a_idx; + uint64_t *t; - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid); + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); if (!flow_db) { BNXT_TF_DBG(ERR, "parent child db validation failed\n"); return -EINVAL; } - p_pdb = &flow_db->parent_child_db; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) { - *parent_idx = idx; - return 0; - } + /* check for fid validity */ + if (child_fid >= flow_db->flow_tbl.num_flows || !child_fid) { + BNXT_TF_DBG(ERR, "Invalid child flow index %x\n", child_fid); + return -EINVAL; } - BNXT_TF_DBG(ERR, "Unable to get the parent flow %x\n", parent_fid); - return -1; + + /* validate the arguments and parent child entry */ + pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx); + if (!pc_entry) { + BNXT_TF_DBG(ERR, "failed to get the parent child entry\n"); + return -EINVAL; + } + + a_idx = child_fid / ULP_INDEX_BITMAP_SIZE; + t = pc_entry->child_fid_bitset; + if (set_flag) { + ULP_INDEX_BITMAP_SET(t[a_idx], child_fid); + pc_entry->f2_cnt++; + } else { + ULP_INDEX_BITMAP_RESET(t[a_idx], child_fid); + if (pc_entry->f2_cnt) + pc_entry->f2_cnt--; + if (!pc_entry->f2_cnt && !pc_entry->parent_fid) + ulp_flow_db_pc_db_entry_free(ulp_ctxt, pc_entry); + } + return 0; } /* @@ -1541,13 +1500,13 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db, * Set the counter accumulation in the parent flow * * ulp_ctxt [in] Ptr to ulp_context - * parent_idx [in] The parent index of the parent flow entry + * pc_idx [in] The parent child index of the parent flow entry * * returns index on success and negative on failure. */ static int32_t ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_idx) + uint32_t pc_idx) { struct bnxt_ulp_flow_db *flow_db; struct ulp_fdb_parent_child_db *p_pdb; @@ -1560,50 +1519,16 @@ ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt, /* check for parent idx validity */ p_pdb = &flow_db->parent_child_db; - if (parent_idx >= p_pdb->entries_count || - !p_pdb->parent_flow_tbl[parent_idx].parent_fid) { - BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx); + if (pc_idx >= p_pdb->entries_count || + !p_pdb->parent_flow_tbl[pc_idx].parent_fid) { + BNXT_TF_DBG(ERR, "Invalid parent child index %x\n", pc_idx); return -EINVAL; } - p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1; + p_pdb->parent_flow_tbl[pc_idx].counter_acc = 1; return 0; } -/* - * Get the counter accumulation in the parent flow - * - * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry - * - * returns 0 if counter accum is set else -1. - */ -static int32_t -ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid) -{ - struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx; - - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid); - if (!flow_db) { - BNXT_TF_DBG(ERR, "parent child db validation failed\n"); - return -EINVAL; - } - - p_pdb = &flow_db->parent_child_db; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) { - if (p_pdb->parent_flow_tbl[idx].counter_acc) - return 0; - break; - } - } - return -1; -} - /* * Orphan the child flow entry * This is called only for child flows that have @@ -1677,22 +1602,30 @@ int32_t ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms) { struct ulp_flow_db_res_params fid_parms; - uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC; + uint32_t sub_typ = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT; struct ulp_flow_db_res_params res_params; - int32_t fid_idx, rc; + int32_t pc_idx; - /* create the child flow entry in parent flow table */ - fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid); - if (fid_idx < 0) { - BNXT_TF_DBG(ERR, "Error in creating parent flow fid %x\n", - parms->fid); - return -1; + /* create or get the parent child database */ + pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx); + if (pc_idx < 0) { + BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n", + parms->tun_idx); + return -EINVAL; + } + + /* Update the parent fid */ + if (ulp_flow_db_pc_db_parent_flow_set(parms->ulp_ctx, pc_idx, + parms->fid, 1)) { + BNXT_TF_DBG(ERR, "Error in setting parent fid %x\n", + parms->tun_idx); + return -EINVAL; } /* Add the parent details in the resource list of the flow */ memset(&fid_parms, 0, sizeof(fid_parms)); fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW; - fid_parms.resource_hndl = fid_idx; + fid_parms.resource_hndl = pc_idx; fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, parms->fid, &fid_parms)) { @@ -1710,20 +1643,13 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms) &res_params)) { /* Enable the counter accumulation in parent entry */ if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx, - fid_idx)) { + pc_idx)) { BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n", parms->fid); return -1; } } - rc = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx, - parms->tun_idx); - if (rc) { - BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n"); - return rc; - } - return 0; } @@ -1741,13 +1667,19 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms) uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT; enum bnxt_ulp_resource_func res_fun; struct ulp_flow_db_res_params res_p; - uint32_t parent_fid = parms->parent_fid; - int32_t rc; + int32_t rc, pc_idx; + + /* create or get the parent child database */ + pc_idx = ulp_flow_db_pc_db_idx_alloc(parms->ulp_ctx, parms->tun_idx); + if (pc_idx < 0) { + BNXT_TF_DBG(ERR, "Error in getting parent child db %x\n", + parms->tun_idx); + return -1; + } /* create the parent flow entry in parent flow table */ - rc = ulp_flow_db_parent_child_flow_set(parms->ulp_ctx, - parms->parent_fid, - parms->fid, 1); + rc = ulp_flow_db_pc_db_child_flow_set(parms->ulp_ctx, pc_idx, + parms->fid, 1); if (rc) { BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid); return rc; @@ -1756,7 +1688,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms) /* Add the parent details in the resource list of the flow */ memset(&fid_parms, 0, sizeof(fid_parms)); fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW; - fid_parms.resource_hndl = parms->parent_fid; + fid_parms.resource_hndl = pc_idx; fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO; rc = ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, @@ -1767,30 +1699,26 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms) return rc; } - /* check if accumulation count is set for parent flow */ - rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx, - parms->parent_fid); + /* check if internal count action included for this flow.*/ + res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE; + rc = ulp_flow_db_resource_params_get(parms->ulp_ctx, + BNXT_ULP_FDB_TYPE_REGULAR, + parms->fid, + res_fun, + sub_type, + &res_p); if (!rc) { - /* check if internal count action included for this flow.*/ - res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE; - rc = ulp_flow_db_resource_params_get(parms->ulp_ctx, - BNXT_ULP_FDB_TYPE_REGULAR, - parms->fid, - res_fun, - sub_type, - &res_p); - if (!rc) { - /* update the counter manager to include parent fid */ - if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx, - res_p.direction, - res_p.resource_hndl, - parent_fid)) { - BNXT_TF_DBG(ERR, "Error in setting child %x\n", - parms->fid); - return -1; - } + /* update the counter manager to include parent fid */ + if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx, + res_p.direction, + res_p.resource_hndl, + pc_idx)) { + BNXT_TF_DBG(ERR, "Error in setting child %x\n", + parms->fid); + return -1; } } + /* return success */ return 0; } @@ -1799,7 +1727,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms) * Update the parent counters * * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry + * pc_idx [in] The parent flow entry idx * packet_count [in] - packet count * byte_count [in] - byte count * @@ -1807,41 +1735,31 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms) */ int32_t ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, + uint32_t pc_idx, uint64_t packet_count, uint64_t byte_count) { - struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx; + struct ulp_fdb_parent_info *pc_entry; - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid); - if (!flow_db) { - BNXT_TF_DBG(ERR, "parent child db validation failed\n"); + /* validate the arguments and get parent child entry */ + pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx); + if (!pc_entry) { + BNXT_TF_DBG(ERR, "failed to get the parent child entry\n"); return -EINVAL; } - p_pdb = &flow_db->parent_child_db; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) { - if (p_pdb->parent_flow_tbl[idx].counter_acc) { - p_pdb->parent_flow_tbl[idx].pkt_count += - packet_count; - p_pdb->parent_flow_tbl[idx].byte_count += - byte_count; - } - return 0; - } + if (pc_entry->counter_acc) { + pc_entry->pkt_count += packet_count; + pc_entry->byte_count += byte_count; } - return -ENOENT; + return 0; } /* * Get the parent accumulation counters * * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry + * pc_idx [in] The parent flow entry idx * packet_count [out] - packet count * byte_count [out] - byte count * @@ -1849,37 +1767,27 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt, */ int32_t ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, uint64_t *packet_count, + uint32_t pc_idx, uint64_t *packet_count, uint64_t *byte_count, uint8_t count_reset) { - struct bnxt_ulp_flow_db *flow_db; - struct ulp_fdb_parent_child_db *p_pdb; - uint32_t idx; + struct ulp_fdb_parent_info *pc_entry; - /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid); - if (!flow_db) { - BNXT_TF_DBG(ERR, "parent child db validation failed\n"); + /* validate the arguments and get parent child entry */ + pc_entry = ulp_flow_db_pc_db_entry_get(ulp_ctxt, pc_idx); + if (!pc_entry) { + BNXT_TF_DBG(ERR, "failed to get the parent child entry\n"); return -EINVAL; } - p_pdb = &flow_db->parent_child_db; - for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) { - if (p_pdb->parent_flow_tbl[idx].counter_acc) { - *packet_count = - p_pdb->parent_flow_tbl[idx].pkt_count; - *byte_count = - p_pdb->parent_flow_tbl[idx].byte_count; - if (count_reset) { - p_pdb->parent_flow_tbl[idx].pkt_count = 0; - p_pdb->parent_flow_tbl[idx].byte_count = 0; - } - } - return 0; + if (pc_entry->counter_acc) { + *packet_count = pc_entry->pkt_count; + *byte_count = pc_entry->byte_count; + if (count_reset) { + pc_entry->pkt_count = 0; + pc_entry->byte_count = 0; } } - return -ENOENT; + return 0; } /* @@ -1897,7 +1805,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt) uint32_t idx; /* validate the arguments */ - flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1); + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); if (!flow_db) { BNXT_TF_DBG(ERR, "parent child db validation failed\n"); return; @@ -1905,7 +1813,7 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt) p_pdb = &flow_db->parent_child_db; for (idx = 0; idx < p_pdb->entries_count; idx++) { - if (p_pdb->parent_flow_tbl[idx].parent_fid && + if (p_pdb->parent_flow_tbl[idx].valid && p_pdb->parent_flow_tbl[idx].counter_acc) { p_pdb->parent_flow_tbl[idx].pkt_count = 0; p_pdb->parent_flow_tbl[idx].byte_count = 0; diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index 0ddfa6f66d..8680ee8f65 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -58,6 +58,7 @@ struct bnxt_ulp_flow_tbl { /* Structure to maintain parent-child flow relationships */ struct ulp_fdb_parent_info { + uint32_t valid; uint32_t parent_fid; uint32_t counter_acc; uint64_t pkt_count; @@ -259,45 +260,38 @@ int32_t ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx, uint32_t flow_id, uint16_t *cfa_action); -/* - * Allocate the entry in the parent-child database - * - * ulp_ctxt [in] Ptr to ulp_context - * fid [in] The flow id to the flow entry - * - * returns index on success and negative on failure. - */ -int32_t -ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt, - uint32_t fid); /* - * Free the entry in the parent-child database + * Set or reset the parent flow in the parent-child database * * ulp_ctxt [in] Ptr to ulp_context - * fid [in] The flow id to the flow entry + * pc_idx [in] The index to parent child db + * parent_fid [in] The flow id of the parent flow entry + * set_flag [in] Use 1 for setting child, 0 to reset * - * returns 0 on success and negative on failure. + * returns zero on success and negative on failure. */ int32_t -ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt, - uint32_t fid); +ulp_flow_db_pc_db_parent_flow_set(struct bnxt_ulp_context *ulp_ctxt, + uint32_t pc_idx, + uint32_t parent_fid, + uint32_t set_flag); /* * Set or reset the child flow in the parent-child database * * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry + * pc_idx [in] The index to parent child db * child_fid [in] The flow id of the child flow entry * set_flag [in] Use 1 for setting child, 0 to reset * * returns zero on success and negative on failure. */ int32_t -ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, - uint32_t child_fid, - uint32_t set_flag); +ulp_flow_db_pc_db_child_flow_set(struct bnxt_ulp_context *ulp_ctxt, + uint32_t pc_idx, + uint32_t child_fid, + uint32_t set_flag); /* * Get the parent index from the parent-child database @@ -368,7 +362,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms); * Update the parent counters * * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry + * pc_idx [in] The parent flow entry idx * packet_count [in] - packet count * byte_count [in] - byte count * @@ -376,14 +370,14 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms); */ int32_t ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, + uint32_t pc_idx, uint64_t packet_count, uint64_t byte_count); /* * Get the parent accumulation counters * * ulp_ctxt [in] Ptr to ulp_context - * parent_fid [in] The flow id of the parent flow entry + * pc_idx [in] The parent flow entry idx * packet_count [out] - packet count * byte_count [out] - byte count * @@ -391,7 +385,7 @@ ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt, */ int32_t ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt, - uint32_t parent_fid, + uint32_t pc_idx, uint64_t *packet_count, uint64_t *byte_count, uint8_t count_reset); diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 7fc3767b33..6d804c7ef9 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -544,34 +544,14 @@ ulp_mapper_parent_flow_free(struct bnxt_ulp_context *ulp, uint32_t parent_fid, struct ulp_flow_db_res_params *res) { - uint32_t idx, child_fid = 0, parent_idx; - struct bnxt_ulp_flow_db *flow_db; + uint32_t pc_idx; - parent_idx = (uint32_t)res->resource_hndl; + pc_idx = (uint32_t)res->resource_hndl; - /* check the validity of the parent fid */ - if (ulp_flow_db_parent_flow_idx_get(ulp, parent_fid, &idx) || - idx != parent_idx) { - BNXT_TF_DBG(ERR, "invalid parent flow id %x\n", parent_fid); - return -EINVAL; - } - - /* Clear all the child flows parent index */ - flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp); - while (!ulp_flow_db_parent_child_flow_next_entry_get(flow_db, idx, - &child_fid)) { - /* update the child flows resource handle */ - if (ulp_flow_db_child_flow_reset(ulp, BNXT_ULP_FDB_TYPE_REGULAR, - child_fid)) { - BNXT_TF_DBG(ERR, "failed to reset child flow %x\n", - child_fid); - return -EINVAL; - } - } - - /* free the parent entry in the parent table flow */ - if (ulp_flow_db_parent_flow_free(ulp, parent_fid)) { - BNXT_TF_DBG(ERR, "failed to free parent flow %x\n", parent_fid); + /* reset the child flow bitset*/ + if (ulp_flow_db_pc_db_parent_flow_set(ulp, pc_idx, parent_fid, 0)) { + BNXT_TF_DBG(ERR, "error in reset parent flow bitset %x:%x\n", + pc_idx, parent_fid); return -EINVAL; } return 0; @@ -582,16 +562,14 @@ ulp_mapper_child_flow_free(struct bnxt_ulp_context *ulp, uint32_t child_fid, struct ulp_flow_db_res_params *res) { - uint32_t parent_fid; + uint32_t pc_idx; - parent_fid = (uint32_t)res->resource_hndl; - if (!parent_fid) - return 0; /* Already freed - orphan child*/ + pc_idx = (uint32_t)res->resource_hndl; /* reset the child flow bitset*/ - if (ulp_flow_db_parent_child_flow_set(ulp, parent_fid, child_fid, 0)) { + if (ulp_flow_db_pc_db_child_flow_set(ulp, pc_idx, child_fid, 0)) { BNXT_TF_DBG(ERR, "error in resetting child flow bitset %x:%x\n", - parent_fid, child_fid); + pc_idx, child_fid); return -EINVAL; } return 0; @@ -1944,6 +1922,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } + /* If only allocation of identifier then perform and exit */ + if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT) { + rc = ulp_mapper_tcam_tbl_scan_ident_alloc(parms, tbl); + return rc; + } + kflds = ulp_mapper_key_fields_get(parms, tbl, &num_kflds); if (!kflds || !num_kflds) { BNXT_TF_DBG(ERR, "Failed to get key fields\n"); @@ -3889,7 +3873,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, parms.class_tid = cparms->class_tid; parms.flow_type = cparms->flow_type; parms.parent_flow = cparms->parent_flow; - parms.parent_fid = cparms->parent_fid; + parms.child_flow = cparms->child_flow; parms.fid = cparms->flow_id; parms.tun_idx = cparms->tun_idx; parms.app_priority = cparms->app_priority; @@ -3954,7 +3938,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx, rc = ulp_flow_db_parent_flow_create(&parms); if (rc) goto flow_error; - } else if (parms.parent_fid) { + } else if (parms.child_flow) { /* create a child flow details */ rc = ulp_flow_db_child_flow_create(&parms); if (rc) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h index 004e89ac2b..d4d6969bb5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h @@ -53,7 +53,7 @@ struct bnxt_ulp_mapper_parms { enum bnxt_ulp_fdb_type flow_type; struct bnxt_ulp_mapper_data *mapper_data; struct bnxt_ulp_device_params *device_params; - uint32_t parent_fid; + uint32_t child_flow; uint32_t parent_flow; uint8_t tun_idx; uint32_t app_priority; @@ -79,8 +79,8 @@ struct bnxt_ulp_mapper_create_parms { enum bnxt_ulp_fdb_type flow_type; uint32_t flow_id; - /* if set then create it as a child flow with parent as parent_fid */ - uint32_t parent_fid; + /* if set then create it as a child flow */ + uint32_t child_flow; /* if set then create a parent flow */ uint32_t parent_flow; uint8_t tun_idx; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c index 35e9858727..9b165c12b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c @@ -215,6 +215,21 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = { } }; +struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = { + [BNXT_RTE_FLOW_ACTION_TYPE_END - BNXT_RTE_FLOW_ACTION_TYPE_END] = { + .act_type = BNXT_ULP_ACT_TYPE_END, + .proto_act_func = NULL + }, + [BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ACTION_TYPE_END] = { + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_vendor_vxlan_decap_act_handler + }, + [BNXT_RTE_FLOW_ACTION_TYPE_LAST - BNXT_RTE_FLOW_ACTION_TYPE_END] = { + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL + } +}; + /* * This table has to be indexed based on the rte_flow_item_type that is part of * DPDK. The below array is list of parsing functions for each of the flow items @@ -414,3 +429,19 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { .proto_hdr_func = NULL } }; + +struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[] = { + [BNXT_RTE_FLOW_ITEM_TYPE_END - BNXT_RTE_FLOW_ITEM_TYPE_END] = { + .hdr_type = BNXT_ULP_HDR_TYPE_END, + .proto_hdr_func = NULL + }, + [BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP - BNXT_RTE_FLOW_ITEM_TYPE_END] = { + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vendor_vxlan_decap_hdr_handler + }, + [BNXT_RTE_FLOW_ITEM_TYPE_LAST - BNXT_RTE_FLOW_ITEM_TYPE_END] = { + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL + }, + +}; diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 79b9957781..fadcd3873c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -125,13 +125,21 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[], /* Parse all the items in the pattern */ while (item && item->type != RTE_FLOW_ITEM_TYPE_END) { - /* get the header information from the flow_hdr_info table */ - hdr_info = &ulp_hdr_info[item->type]; + if (item->type >= (uint32_t) + BNXT_RTE_FLOW_ITEM_TYPE_END) { + if (item->type >= + (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST) + goto hdr_parser_error; + /* get the header information */ + hdr_info = &ulp_vendor_hdr_info[item->type - + BNXT_RTE_FLOW_ITEM_TYPE_END]; + } else { + if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2) + goto hdr_parser_error; + hdr_info = &ulp_hdr_info[item->type]; + } if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_NOT_SUPPORTED) { - BNXT_TF_DBG(ERR, - "Truflow parser does not support type %d\n", - item->type); - return BNXT_TF_RC_PARSE_ERR; + goto hdr_parser_error; } else if (hdr_info->hdr_type == BNXT_ULP_HDR_TYPE_SUPPORTED) { /* call the registered callback handler */ if (hdr_info->proto_hdr_func) { @@ -145,6 +153,11 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[], } /* update the implied SVIF */ return ulp_rte_parser_implicit_match_port_process(params); + +hdr_parser_error: + BNXT_TF_DBG(ERR, "Truflow parser does not support type %d\n", + item->type); + return BNXT_TF_RC_PARSE_ERR; } /* @@ -160,16 +173,23 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* Parse all the items in the pattern */ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { - /* get the header information from the flow_hdr_info table */ - hdr_info = &ulp_act_info[action_item->type]; - if (hdr_info->act_type == - BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) { - BNXT_TF_DBG(ERR, - "Truflow parser does not support act %u\n", - action_item->type); - return BNXT_TF_RC_ERROR; - } else if (hdr_info->act_type == - BNXT_ULP_ACT_TYPE_SUPPORTED) { + if (action_item->type >= + (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) { + if (action_item->type >= + (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST) + goto act_parser_error; + /* get the header information from bnxt actinfo table */ + hdr_info = &ulp_vendor_act_info[action_item->type - + BNXT_RTE_FLOW_ACTION_TYPE_END]; + } else { + if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED) + goto act_parser_error; + /* get the header information from the act info table */ + hdr_info = &ulp_act_info[action_item->type]; + } + if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_NOT_SUPPORTED) { + goto act_parser_error; + } else if (hdr_info->act_type == BNXT_ULP_ACT_TYPE_SUPPORTED) { /* call the registered callback handler */ if (hdr_info->proto_act_func) { if (hdr_info->proto_act_func(action_item, @@ -184,6 +204,11 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* update the implied port details */ ulp_rte_parser_implicit_act_port_process(params); return BNXT_TF_RC_SUCCESS; + +act_parser_error: + BNXT_TF_DBG(ERR, "Truflow parser does not support act %u\n", + action_item->type); + return BNXT_TF_RC_ERROR; } /* @@ -325,11 +350,10 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params) /* * Function to handle the post processing of the parsing details */ -int32_t +void bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params) { ulp_post_process_normal_flow(params); - return ulp_post_process_tun_flow(params); } /* @@ -660,7 +684,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, { const struct rte_flow_item_eth *eth_spec = item->spec; const struct rte_flow_item_eth *eth_mask = item->mask; - uint32_t idx = 0; + uint32_t idx = 0, dmac_idx = 0; uint32_t size; uint16_t eth_type = 0; uint32_t inner_flag = 0; @@ -686,6 +710,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, * Copy the rte_flow_item for eth into hdr_field using ethernet * header fields */ + dmac_idx = idx; size = sizeof(((struct rte_flow_item_eth *)NULL)->dst.addr_bytes); ulp_rte_prsr_fld_mask(params, &idx, size, ulp_deference_struct(eth_spec, dst.addr_bytes), @@ -719,6 +744,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, inner_flag = 1; } else { ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID, + dmac_idx); } /* Update the field protocol hdr bitmap */ ulp_rte_l2_proto_type_update(params, eth_type, inner_flag); @@ -926,7 +953,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, const struct rte_flow_item_ipv4 *ipv4_spec = item->spec; const struct rte_flow_item_ipv4 *ipv4_mask = item->mask; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = 0; + uint32_t idx = 0, dip_idx = 0; uint32_t size; uint8_t proto = 0; uint32_t inner_flag = 0; @@ -939,22 +966,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_ERROR; } - if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits, - BNXT_ULP_HDR_BIT_O_ETH) && - !ULP_BITMAP_ISSET(params->hdr_bitmap.bits, - BNXT_ULP_HDR_BIT_I_ETH)) { - /* Since F2 flow does not include eth item, when parser detects - * IPv4/IPv6 item list and it belongs to the outer header; i.e., - * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set, - * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index. - * This will allow the parser post processor to update the - * t_dmac in hdr_field[o_eth.dmac] - */ - idx += (BNXT_ULP_PROTO_HDR_ETH_NUM + - BNXT_ULP_PROTO_HDR_VLAN_NUM); - params->field_idx = idx; - } - if (ulp_rte_prsr_fld_size_validate(params, &idx, BNXT_ULP_PROTO_HDR_IPV4_NUM)) { BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); @@ -1033,6 +1044,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, ulp_deference_struct(ipv4_mask, hdr.src_addr), ULP_PRSR_ACT_DEFAULT); + dip_idx = idx; size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.dst_addr); ulp_rte_prsr_fld_mask(params, &idx, size, ulp_deference_struct(ipv4_spec, hdr.dst_addr), @@ -1048,6 +1060,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); + /* Update the tunnel offload dest ip offset */ + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID, + dip_idx); } /* Some of the PMD applications may set the protocol field @@ -1071,7 +1086,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, const struct rte_flow_item_ipv6 *ipv6_spec = item->spec; const struct rte_flow_item_ipv6 *ipv6_mask = item->mask; struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; - uint32_t idx = 0; + uint32_t idx = 0, dip_idx = 0; uint32_t size; uint32_t ver_spec = 0, ver_mask = 0; uint32_t tc_spec = 0, tc_mask = 0; @@ -1087,22 +1102,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_ERROR; } - if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits, - BNXT_ULP_HDR_BIT_O_ETH) && - !ULP_BITMAP_ISSET(params->hdr_bitmap.bits, - BNXT_ULP_HDR_BIT_I_ETH)) { - /* Since F2 flow does not include eth item, when parser detects - * IPv4/IPv6 item list and it belongs to the outer header; i.e., - * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set, - * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index. - * This will allow the parser post processor to update the - * t_dmac in hdr_field[o_eth.dmac] - */ - idx += (BNXT_ULP_PROTO_HDR_ETH_NUM + - BNXT_ULP_PROTO_HDR_VLAN_NUM); - params->field_idx = idx; - } - if (ulp_rte_prsr_fld_size_validate(params, &idx, BNXT_ULP_PROTO_HDR_IPV6_NUM)) { BNXT_TF_DBG(ERR, "Error parsing protocol header\n"); @@ -1171,6 +1170,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, ulp_deference_struct(ipv6_mask, hdr.src_addr), ULP_PRSR_ACT_DEFAULT); + dip_idx = idx; size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.dst_addr); ulp_rte_prsr_fld_mask(params, &idx, size, ulp_deference_struct(ipv6_spec, hdr.dst_addr), @@ -1186,6 +1186,9 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); + /* Update the tunnel offload dest ip offset */ + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID, + dip_idx); } /* Update the field protocol hdr bitmap */ @@ -1200,9 +1203,11 @@ static void ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param, uint16_t dst_port) { - if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) + if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) { ULP_BITMAP_SET(param->hdr_fp_bit.bits, BNXT_ULP_HDR_BIT_T_VXLAN); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1); + } if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_VXLAN) || @@ -2484,3 +2489,24 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item, return ret; } + +/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */ +int32_t +ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item, + struct ulp_rte_parser_params *params) +{ + /* Set the F1 flow header bit */ + ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1); + return ulp_rte_vxlan_decap_act_handler(action_item, params); +} + +/* Function to handle the parsing of bnxt vendor Flow item vxlan Header. */ +int32_t +ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params) +{ + RTE_SET_USED(item); + /* Set the F2 flow header bit */ + ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2); + return ulp_rte_vxlan_decap_act_handler(NULL, params); +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h index 4431f1bbd0..673172c811 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h @@ -75,7 +75,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* * Function to handle the post processing of the parsing details */ -int32_t +void bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params); /* Function to handle the parsing of RTE Flow item PF Header. */ @@ -270,4 +270,12 @@ int32_t ulp_rte_shared_act_handler(const struct rte_flow_action *action_item, struct ulp_rte_parser_params *params); +int32_t +ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item, + struct ulp_rte_parser_params *params); + +int32_t +ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item, + struct ulp_rte_parser_params *params); + #endif /* _ULP_RTE_PARSER_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 0cbac66237..2685e63432 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -78,17 +78,19 @@ struct ulp_rte_parser_params { uint32_t priority; uint32_t fid; uint32_t parent_flow; - uint32_t parent_fid; + uint32_t child_flow; uint16_t func_id; uint16_t port_id; uint32_t class_id; uint32_t act_tmpl; struct bnxt_ulp_context *ulp_ctx; uint32_t hdr_sig_id; - uint32_t flow_sig_id; + uint64_t flow_sig_id; uint32_t flow_pattern_id; uint32_t act_pattern_id; uint8_t app_id; + uint8_t tun_idx; + }; /* Flow Parser Header Information Structure */ @@ -101,6 +103,7 @@ struct bnxt_ulp_rte_hdr_info { /* Flow Parser Header Information Structure Array defined in template source*/ extern struct bnxt_ulp_rte_hdr_info ulp_hdr_info[]; +extern struct bnxt_ulp_rte_hdr_info ulp_vendor_hdr_info[]; /* Flow Parser Action Information Structure */ struct bnxt_ulp_rte_act_info { @@ -113,6 +116,7 @@ struct bnxt_ulp_rte_act_info { /* Flow Parser Action Information Structure Array defined in template source*/ extern struct bnxt_ulp_rte_act_info ulp_act_info[]; +extern struct bnxt_ulp_rte_act_info ulp_vendor_act_info[]; /* Flow Matcher structures */ struct bnxt_ulp_header_match_info { @@ -136,7 +140,7 @@ struct bnxt_ulp_class_match_info { uint8_t wc_pri; uint8_t app_sig; uint32_t hdr_sig_id; - uint32_t flow_sig_id; + uint64_t flow_sig_id; uint32_t flow_pattern_id; }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index a1dd5b902c..7ce6740633 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -3,225 +3,111 @@ * All rights reserved. */ -#include - -#include - +#include "bnxt.h" +#include "bnxt_ulp.h" #include "ulp_tun.h" -#include "ulp_rte_parser.h" -#include "ulp_template_db_enum.h" -#include "ulp_template_struct.h" -#include "ulp_matcher.h" -#include "ulp_mapper.h" -#include "ulp_flow_db.h" +#include "ulp_utils.h" -/* This function programs the outer tunnel flow in the hardware. */ -static int32_t -ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, - struct bnxt_tun_cache_entry *tun_entry, - uint16_t tun_idx) +/* returns negative on error, 1 if new entry is allocated or zero if old */ +int32_t +ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx, + struct rte_flow_tunnel *app_tunnel, + struct bnxt_flow_app_tun_ent **tun_entry) { - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; - int ret; - - /* Reset the JUMP action bit in the action bitmap as we don't - * offload this action. - */ - ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP); - - ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1); - -#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG -#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER - /* Dump the rte flow pattern */ - ulp_parser_hdr_info_dump(params); - /* Dump the rte flow action */ - ulp_parser_act_info_dump(params); -#endif -#endif - - ret = ulp_matcher_pattern_match(params, ¶ms->class_id); - if (ret != BNXT_TF_RC_SUCCESS) - goto err; + struct bnxt_flow_app_tun_ent *tun_ent_list; + int32_t i, rc = 0, free_entry = -1; - ret = ulp_matcher_action_match(params, ¶ms->act_tmpl); - if (ret != BNXT_TF_RC_SUCCESS) - goto err; - - params->parent_flow = true; - bnxt_ulp_init_mapper_params(&mparms, params, - BNXT_ULP_FDB_TYPE_REGULAR); - mparms.tun_idx = tun_idx; - - /* Call the ulp mapper to create the flow in the hardware. */ - ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms); - if (ret) - goto err; - - /* Store the tunnel dmac in the tunnel cache table and use it while - * programming tunnel inner flow. - */ - memcpy(tun_entry->t_dmac, - ¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec, - RTE_ETHER_ADDR_LEN); - - tun_entry->tun_flow_info[params->port_id].state = - BNXT_ULP_FLOW_STATE_TUN_O_OFFLD; - tun_entry->outer_tun_flow_id = params->fid; - - /* Tunnel outer flow and it's related inner flows are correlated - * based on Tunnel Destination IP Address. - */ - if (tun_entry->t_dst_ip_valid) - goto done; - if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4)) - memcpy(&tun_entry->t_dst_ip, - ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec, - sizeof(rte_be32_t)); - else - memcpy(tun_entry->t_dst_ip6, - ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec, - sizeof(tun_entry->t_dst_ip6)); - tun_entry->t_dst_ip_valid = true; + tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx); + if (!tun_ent_list) { + BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n"); + return -EINVAL; + } -done: - return BNXT_TF_RC_FID; + for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { + if (!tun_ent_list[i].ref_cnt) { + if (free_entry < 0) + free_entry = i; + } else { + if (!memcmp(&tun_ent_list[i].app_tunnel, + app_tunnel, + sizeof(struct rte_flow_tunnel))) { + *tun_entry = &tun_ent_list[i]; + tun_ent_list[free_entry].ref_cnt++; + return rc; + } + } + } + if (free_entry >= 0) { + *tun_entry = &tun_ent_list[free_entry]; + memcpy(&tun_ent_list[free_entry].app_tunnel, app_tunnel, + sizeof(struct rte_flow_tunnel)); + tun_ent_list[free_entry].ref_cnt = 1; + rc = 1; + } else { + BNXT_TF_DBG(ERR, "ulp app tunnel list is full\n"); + return -ENOMEM; + } -err: - memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry)); - return BNXT_TF_RC_ERROR; + return rc; } -/* This function programs the inner tunnel flow in the hardware. */ -static void -ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry, - struct ulp_rte_parser_params *tun_o_params) +void +ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry) { - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; - struct ulp_per_port_flow_info *flow_info; - struct ulp_rte_parser_params *inner_params; - int ret; - - /* Tunnel inner flow doesn't have tunnel dmac, use the tunnel - * dmac that was stored during F1 programming. - */ - flow_info = &tun_entry->tun_flow_info[tun_o_params->port_id]; - STAILQ_FOREACH(inner_params, &flow_info->tun_i_prms_list, next) { - memcpy(&inner_params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], - tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); - inner_params->parent_fid = tun_entry->outer_tun_flow_id; - - bnxt_ulp_init_mapper_params(&mparms, inner_params, - BNXT_ULP_FDB_TYPE_REGULAR); - - ret = ulp_mapper_flow_create(inner_params->ulp_ctx, &mparms); - if (ret) - PMD_DRV_LOG(ERR, - "Failed to create inner tun flow, FID:%u.", - inner_params->fid); + if (tun_entry) { + if (tun_entry->ref_cnt) { + tun_entry->ref_cnt--; + if (!tun_entry->ref_cnt) + memset(tun_entry, 0, + sizeof(struct bnxt_flow_app_tun_ent)); + } } } -/* This function either install outer tunnel flow & inner tunnel flow - * or just the outer tunnel flow based on the flow state. - */ -static int32_t -ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params, - struct bnxt_tun_cache_entry *tun_entry, - uint16_t tun_idx) +int32_t +ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry) { - int ret; - - ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx); - if (ret == BNXT_TF_RC_ERROR) { - PMD_DRV_LOG(ERR, "Failed to create outer tunnel flow."); - return ret; - } + if (!tun_entry) + return -EINVAL; - /* Install any cached tunnel inner flows that came before tunnel - * outer flow. - */ - ulp_install_inner_tun_flow(tun_entry, params); - - return BNXT_TF_RC_FID; + tun_entry->action.type = (typeof(tun_entry->action.type)) + BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP; + tun_entry->action.conf = tun_entry; + return 0; } -/* This function will be called if inner tunnel flow request comes before - * outer tunnel flow request. - */ -static int32_t -ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params, - struct bnxt_tun_cache_entry *tun_entry) +int32_t +ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry) { - struct ulp_rte_parser_params *inner_tun_params; - struct ulp_per_port_flow_info *flow_info; - int ret; - -#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG -#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER - /* Dump the rte flow pattern */ - ulp_parser_hdr_info_dump(params); - /* Dump the rte flow action */ - ulp_parser_act_info_dump(params); -#endif -#endif - - ret = ulp_matcher_pattern_match(params, ¶ms->class_id); - if (ret != BNXT_TF_RC_SUCCESS) - return BNXT_TF_RC_ERROR; - - ret = ulp_matcher_action_match(params, ¶ms->act_tmpl); - if (ret != BNXT_TF_RC_SUCCESS) - return BNXT_TF_RC_ERROR; - - /* If Tunnel inner flow comes first then we can't install it in the - * hardware, because, Tunnel inner flow will not have L2 context - * information. So, just cache the Tunnel inner flow information - * and program it in the context of F1 flow installation. - */ - flow_info = &tun_entry->tun_flow_info[params->port_id]; - inner_tun_params = rte_zmalloc("ulp_inner_tun_params", - sizeof(struct ulp_rte_parser_params), 0); - if (!inner_tun_params) - return BNXT_TF_RC_ERROR; - memcpy(inner_tun_params, params, sizeof(struct ulp_rte_parser_params)); - STAILQ_INSERT_TAIL(&flow_info->tun_i_prms_list, inner_tun_params, - next); - flow_info->tun_i_cnt++; - - /* F1 and it's related Tunnel inner flows are correlated based on - * Tunnel Destination IP Address. It could be already set, if - * the inner flow got offloaded first. - */ - if (tun_entry->t_dst_ip_valid) - goto done; - if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4)) - memcpy(&tun_entry->t_dst_ip, - ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec, - sizeof(rte_be32_t)); - else - memcpy(tun_entry->t_dst_ip6, - ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec, - sizeof(tun_entry->t_dst_ip6)); - tun_entry->t_dst_ip_valid = true; - -done: - return BNXT_TF_RC_FID; + if (!tun_entry) + return -EINVAL; + + tun_entry->item.type = (typeof(tun_entry->item.type)) + BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP; + tun_entry->item.spec = tun_entry; + tun_entry->item.last = NULL; + tun_entry->item.mask = NULL; + return 0; } -/* This function will be called if inner tunnel flow request comes after - * the outer tunnel flow request. - */ -static int32_t -ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params, - struct bnxt_tun_cache_entry *tun_entry) +struct bnxt_flow_app_tun_ent * +ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, + const void *ctx) { - memcpy(¶ms->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX], - tun_entry->t_dmac, RTE_ETHER_ADDR_LEN); + struct bnxt_flow_app_tun_ent *tun_ent_list; + int32_t i; - params->parent_fid = tun_entry->outer_tun_flow_id; + tun_ent_list = bnxt_ulp_cntxt_ptr2_app_tun_list_get(ulp_ctx); + if (!tun_ent_list) { + BNXT_TF_DBG(ERR, "unable to get the app tunnel list\n"); + return NULL; + } - return BNXT_TF_RC_NORMAL; + for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { + if (&tun_ent_list[i] == ctx) + return &tun_ent_list[i]; + } + return NULL; } static int32_t @@ -229,203 +115,116 @@ ulp_get_tun_entry(struct ulp_rte_parser_params *params, struct bnxt_tun_cache_entry **tun_entry, uint16_t *tun_idx) { - int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID; + int32_t i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID; struct bnxt_tun_cache_entry *tun_tbl; - bool tun_entry_found = false, free_entry_found = false; + uint32_t dip_idx, dmac_idx, use_ipv4 = 0; tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx); - if (!tun_tbl) + if (!tun_tbl) { + BNXT_TF_DBG(ERR, "Error: could not get Tunnel table\n"); return BNXT_TF_RC_ERROR; + } + + /* get the outer destination ip field index */ + dip_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID); + dmac_idx = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID); + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4)) + use_ipv4 = 1; for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { - if (!memcmp(&tun_tbl[i].t_dst_ip, - ¶ms->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec, - sizeof(rte_be32_t)) || - !memcmp(&tun_tbl[i].t_dst_ip6, - ¶ms->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec, - 16)) { - tun_entry_found = true; - break; + if (!tun_tbl[i].t_dst_ip_valid) { + if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) + first_free_entry = i; + continue; } - - if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) { - first_free_entry = i; - free_entry_found = true; + /* match on the destination ip of the tunnel */ + if ((use_ipv4 && !memcmp(&tun_tbl[i].t_dst_ip, + params->hdr_field[dip_idx].spec, + sizeof(rte_be32_t))) || + (!use_ipv4 && + !memcmp(tun_tbl[i].t_dst_ip6, + params->hdr_field[dip_idx].spec, + sizeof(((struct bnxt_tun_cache_entry *) + NULL)->t_dst_ip6)))) { + *tun_entry = &tun_tbl[i]; + *tun_idx = i; + return 0; } } - - if (tun_entry_found) { - *tun_entry = &tun_tbl[i]; - *tun_idx = i; - } else { - if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) - return BNXT_TF_RC_ERROR; - *tun_entry = &tun_tbl[first_free_entry]; - *tun_idx = first_free_entry; - } - - return 0; -} - -int32_t -ulp_post_process_tun_flow(struct ulp_rte_parser_params *params) -{ - bool inner_tun_sig, cache_inner_tun_flow; - bool outer_tun_reject, outer_tun_flow, inner_tun_flow; - enum bnxt_ulp_tun_flow_state flow_state; - struct bnxt_tun_cache_entry *tun_entry; - uint32_t l3_tun, l3_tun_decap; - uint16_t tun_idx; - int rc; - - /* Computational fields that indicate it's a TUNNEL DECAP flow */ - l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN); - l3_tun_decap = ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_L3_TUN_DECAP); - if (!l3_tun) - return BNXT_TF_RC_NORMAL; - - rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx); - if (rc == BNXT_TF_RC_ERROR) - return rc; - - if (params->port_id >= RTE_MAX_ETHPORTS) + if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID) { + BNXT_TF_DBG(ERR, "Error: No entry available in tunnel table\n"); return BNXT_TF_RC_ERROR; - flow_state = tun_entry->tun_flow_info[params->port_id].state; - /* Outer tunnel flow validation */ - outer_tun_flow = BNXT_OUTER_TUN_FLOW(l3_tun, params); - outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state, - outer_tun_flow); - - /* Inner tunnel flow validation */ - inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params); - cache_inner_tun_flow = BNXT_CACHE_INNER_TUN_FLOW(flow_state, - inner_tun_sig); - inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig); - - if (outer_tun_reject) { - tun_entry->outer_tun_rej_cnt++; - BNXT_TF_DBG(ERR, - "Tunnel F1 flow rejected, COUNT: %d\n", - tun_entry->outer_tun_rej_cnt); } - if (outer_tun_reject) - return BNXT_TF_RC_ERROR; - else if (cache_inner_tun_flow) - return ulp_post_process_cache_inner_tun_flow(params, tun_entry); - else if (outer_tun_flow) - return ulp_post_process_outer_tun_flow(params, tun_entry, - tun_idx); - else if (inner_tun_flow) - return ulp_post_process_inner_tun_flow(params, tun_entry); - else - return BNXT_TF_RC_NORMAL; -} + *tun_idx = first_free_entry; + *tun_entry = &tun_tbl[first_free_entry]; + tun_tbl[first_free_entry].t_dst_ip_valid = true; -void -ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl) -{ - struct ulp_per_port_flow_info *flow_info; - int i, j; + /* Update the destination ip and mac */ + if (use_ipv4) + memcpy(&tun_tbl[first_free_entry].t_dst_ip, + params->hdr_field[dip_idx].spec, sizeof(rte_be32_t)); + else + memcpy(tun_tbl[first_free_entry].t_dst_ip6, + params->hdr_field[dip_idx].spec, + sizeof(((struct bnxt_tun_cache_entry *) + NULL)->t_dst_ip6)); + memcpy(tun_tbl[first_free_entry].t_dmac, + params->hdr_field[dmac_idx].spec, RTE_ETHER_ADDR_LEN); - for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[i].tun_flow_info[j]; - STAILQ_INIT(&flow_info->tun_i_prms_list); - } - } + return 0; } +/* Tunnel API to delete the tunnel entry */ void -ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx) +ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl, + uint8_t tun_idx) { - struct ulp_rte_parser_params *inner_params; - struct ulp_per_port_flow_info *flow_info; - int j; - - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; - STAILQ_FOREACH(inner_params, - &flow_info->tun_i_prms_list, - next) { - STAILQ_REMOVE(&flow_info->tun_i_prms_list, - inner_params, - ulp_rte_parser_params, next); - rte_free(inner_params); - } - } - - memset(&tun_tbl[tun_idx], 0, - sizeof(struct bnxt_tun_cache_entry)); - - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[tun_idx].tun_flow_info[j]; - STAILQ_INIT(&flow_info->tun_i_prms_list); - } + memset(&tun_tbl[tun_idx], 0, sizeof(struct bnxt_tun_cache_entry)); } -static bool -ulp_chk_and_rem_tun_i_flow(struct bnxt_tun_cache_entry *tun_entry, - struct ulp_per_port_flow_info *flow_info, - uint32_t fid) +/* Tunnel API to perform tunnel offload process when there is F1/F2 flows */ +int32_t +ulp_tunnel_offload_process(struct ulp_rte_parser_params *params) { - struct ulp_rte_parser_params *inner_params; - int j; - - STAILQ_FOREACH(inner_params, - &flow_info->tun_i_prms_list, - next) { - if (inner_params->fid == fid) { - STAILQ_REMOVE(&flow_info->tun_i_prms_list, - inner_params, - ulp_rte_parser_params, - next); - rte_free(inner_params); - flow_info->tun_i_cnt--; - /* When a dpdk application offloads a duplicate - * tunnel inner flow on a port that it is not - * destined to, there won't be a tunnel outer flow - * associated with these duplicate tunnel inner flows. - * So, when the last tunnel inner flow ages out, the - * driver has to clear the tunnel entry, otherwise - * the tunnel entry cannot be reused. - */ - if (!flow_info->tun_i_cnt && - flow_info->state != BNXT_ULP_FLOW_STATE_TUN_O_OFFLD) { - memset(tun_entry, 0, - sizeof(struct bnxt_tun_cache_entry)); - for (j = 0; j < RTE_MAX_ETHPORTS; j++) - STAILQ_INIT(&flow_info->tun_i_prms_list); - } - return true; - } - } + struct bnxt_tun_cache_entry *tun_entry; + uint16_t tun_idx; + int32_t rc = BNXT_TF_RC_SUCCESS; - return false; -} + /* Perform the tunnel offload only for F1 and F2 flows */ + if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_F1) && + !ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_F2)) + return rc; -/* When a dpdk application offloads the same tunnel inner flow - * on all the uplink ports, a tunnel inner flow entry is cached - * even if it is not for the right uplink port. Such tunnel - * inner flows will eventually get aged out as there won't be - * any traffic on these ports. When such a flow destroy is - * called, cleanup the tunnel inner flow entry. - */ -void -ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid) -{ - struct ulp_per_port_flow_info *flow_info; - int i, j; + /* search for the tunnel entry if not found create one */ + rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx); + if (rc == BNXT_TF_RC_ERROR) + return rc; - for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) { - if (!tun_tbl[i].t_dst_ip_valid) - continue; - for (j = 0; j < RTE_MAX_ETHPORTS; j++) { - flow_info = &tun_tbl[i].tun_flow_info[j]; - if (ulp_chk_and_rem_tun_i_flow(&tun_tbl[i], - flow_info, fid) == true) - return; - } + /* Tunnel offload for the outer Tunnel flow */ + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_F1)) { + /* Reset the JUMP action bit in the action bitmap as we don't + * offload this action. + */ + ULP_BITMAP_RESET(params->act_bitmap.bits, + BNXT_ULP_ACT_BIT_JUMP); + params->parent_flow = true; + params->tun_idx = tun_idx; + tun_entry->outer_tun_flow_id = params->fid; + } else if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_F2)) { + ULP_BITMAP_RESET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_F2); + /* add the vxlan decap action for F2 flows */ + ULP_BITMAP_SET(params->act_bitmap.bits, + BNXT_ULP_ACT_BIT_VXLAN_DECAP); + params->child_flow = true; + params->tun_idx = tun_idx; + params->parent_flow = false; } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_TUNNEL_ID, tun_idx); + return rc; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h index 898071bfe7..0fc2ac39d1 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.h +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h @@ -8,7 +8,6 @@ #include #include -#include #include "rte_version.h" #include "rte_ethdev.h" @@ -16,60 +15,6 @@ #include "ulp_template_db_enum.h" #include "ulp_template_struct.h" -#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \ - ((l3_tun) && \ - ULP_BITMAP_ISSET((params)->act_bitmap.bits, \ - BNXT_ULP_ACT_BIT_JUMP)) -#define BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params) \ - ((l3_tun) && (l3_tun_decap) && \ - !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits, \ - BNXT_ULP_HDR_BIT_O_ETH)) - -#define BNXT_CACHE_INNER_TUN_FLOW(state, inner_tun_sig) \ - ((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig)) -#define BNXT_INNER_TUN_FLOW(state, inner_tun_sig) \ - ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig)) - -/* It is invalid to get another outer flow offload request - * for the same tunnel, while the outer flow is already offloaded. - */ -#define BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig) \ - ((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig)) - -#define ULP_TUN_O_DMAC_HDR_FIELD_INDEX 1 -#define ULP_TUN_O_IPV4_DIP_INDEX 19 -#define ULP_TUN_O_IPV6_DIP_INDEX 17 - -/* When a flow offload request comes the following state transitions - * happen based on the order in which the outer & inner flow offload - * requests arrive. - * - * If inner tunnel flow offload request arrives first then the flow - * state will remain in BNXT_ULP_FLOW_STATE_NORMAL state. - * The following outer tunnel flow offload request will change the - * state of the flow to BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from - * BNXT_ULP_FLOW_STATE_NORMAL. - * - * If outer tunnel flow offload request arrives first then the flow state - * will change from BNXT_ULP_FLOW_STATE_NORMAL to - * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD. - * - * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner - * tunnel flow offload requests after that point will be treated as a - * normal flow and the tunnel flow state remains in - * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD - */ -enum bnxt_ulp_tun_flow_state { - BNXT_ULP_FLOW_STATE_NORMAL = 0, - BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, -}; - -struct ulp_per_port_flow_info { - enum bnxt_ulp_tun_flow_state state; - uint32_t tun_i_cnt; - STAILQ_HEAD(, ulp_rte_parser_params) tun_i_prms_list; -}; - struct bnxt_tun_cache_entry { bool t_dst_ip_valid; uint8_t t_dmac[RTE_ETHER_ADDR_LEN]; @@ -78,17 +23,39 @@ struct bnxt_tun_cache_entry { uint8_t t_dst_ip6[16]; }; uint32_t outer_tun_flow_id; - uint16_t outer_tun_rej_cnt; - struct ulp_per_port_flow_info tun_flow_info[RTE_MAX_ETHPORTS]; }; -void -ulp_tun_tbl_init(struct bnxt_tun_cache_entry *tun_tbl); +struct bnxt_flow_app_tun_ent { + struct rte_flow_tunnel app_tunnel; + uint32_t tun_id; + uint32_t ref_cnt; + struct rte_flow_action action; + struct rte_flow_item item; +}; + +int32_t +ulp_app_tun_search_entry(struct bnxt_ulp_context *ulp_ctx, + struct rte_flow_tunnel *app_tunnel, + struct bnxt_flow_app_tun_ent **tun_entry); void -ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx); +ulp_app_tun_entry_delete(struct bnxt_flow_app_tun_ent *tun_entry); +int32_t +ulp_app_tun_entry_set_decap_action(struct bnxt_flow_app_tun_ent *tun_entry); + +int32_t +ulp_app_tun_entry_set_decap_item(struct bnxt_flow_app_tun_ent *tun_entry); + +struct bnxt_flow_app_tun_ent * +ulp_app_tun_match_entry(struct bnxt_ulp_context *ulp_ctx, const void *ctx); + +/* Tunnel API to delete the tunnel entry */ void -ulp_clear_tun_inner_entry(struct bnxt_tun_cache_entry *tun_tbl, uint32_t fid); +ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl, + uint8_t tun_idx); + +int32_t +ulp_tunnel_offload_process(struct ulp_rte_parser_params *params); #endif