From: Anoob Joseph Date: Tue, 9 Oct 2018 09:07:34 +0000 (+0530) Subject: crypto/octeontx: add PMD skeleton X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=bfe2ae495ee2;p=dpdk.git crypto/octeontx: add PMD skeleton Adding OCTEON TX crypto PMD skeleton. Updating the maintainers files to claim responsibility. Also enabling driver by default by adding the component in common_base. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian S Signed-off-by: Tejasree Kondoj --- diff --git a/MAINTAINERS b/MAINTAINERS index d65f1d7c8a..851e440bbd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,11 @@ F: drivers/crypto/armv8/ F: doc/guides/cryptodevs/armv8.rst F: doc/guides/cryptodevs/features/armv8.ini +Cavium OCTEON TX crypto +M: Anoob Joseph +F: drivers/common/cpt/ +F: drivers/crypto/octeontx/ + Crypto Scheduler M: Fan Zhang F: drivers/crypto/scheduler/ diff --git a/config/common_base b/config/common_base index 022fbd7885..6347404bf2 100644 --- a/config/common_base +++ b/config/common_base @@ -506,6 +506,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=n CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4 +# +# Compile PMD for Cavium OCTEON TX crypto device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y + # # Compile PMD for QuickAssist based devices - see docs for details # diff --git a/drivers/common/cpt/cpt_pmd_logs.h b/drivers/common/cpt/cpt_pmd_logs.h new file mode 100644 index 0000000000..4cbec4e36c --- /dev/null +++ b/drivers/common/cpt/cpt_pmd_logs.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ + +#ifndef _CPT_PMD_LOGS_H_ +#define _CPT_PMD_LOGS_H_ + +#include + +/* + * This file defines log macros + */ + +#define CPT_PMD_DRV_LOG_RAW(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, cpt_logtype, \ + "cpt: %s(): " fmt "\n", __func__, ##args) + +#define CPT_PMD_INIT_FUNC_TRACE() CPT_PMD_DRV_LOG_RAW(DEBUG, " >>") + +#define CPT_LOG_INFO(fmt, args...) \ + CPT_PMD_DRV_LOG_RAW(INFO, fmt, ## args) +#define CPT_LOG_WARN(fmt, args...) \ + CPT_PMD_DRV_LOG_RAW(WARNING, fmt, ## args) +#define CPT_LOG_ERR(fmt, args...) \ + CPT_PMD_DRV_LOG_RAW(ERR, fmt, ## args) + +/* + * DP logs, toggled out at compile time if level lower than current level. + * DP logs would be logged under 'PMD' type. So for dynamic logging, the + * level of 'pmd' has to be used. + */ +#define CPT_LOG_DP(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, fmt "\n", ## args) + +#define CPT_LOG_DP_DEBUG(fmt, args...) \ + CPT_LOG_DP(DEBUG, fmt, ## args) +#define CPT_LOG_DP_INFO(fmt, args...) \ + CPT_LOG_DP(INFO, fmt, ## args) +#define CPT_LOG_DP_WARN(fmt, args...) \ + CPT_LOG_DP(WARNING, fmt, ## args) +#define CPT_LOG_DP_ERR(fmt, args...) \ + CPT_LOG_DP(ERR, fmt, ## args) + +/* + * cpt_logtype will be used for common logging. This field would be initialized + * by otx_* driver routines during PCI probe. + */ +int cpt_logtype; + +#endif /* _CPT_PMD_LOGS_H_ */ diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index c480cbd37e..c083e64ffb 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 6ed853b7ab..b09fe1b396 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -2,7 +2,7 @@ # Copyright(c) 2017 Intel Corporation drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam', - 'null', 'openssl', 'qat', 'scheduler', 'virtio'] + 'null', 'octeontx', 'openssl', 'qat', 'scheduler', 'virtio'] std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile new file mode 100644 index 0000000000..12fec75b03 --- /dev/null +++ b/drivers/crypto/octeontx/Makefile @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Cavium, Inc +# + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_octeontx_crypto.a + +# library version +LIBABIVER := 1 + +# build flags +CFLAGS += $(WERROR_FLAGS) + +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_cryptodev +LDLIBS += -lrte_pci -lrte_bus_pci + +VPATH += $(RTE_SDK)/drivers/crypto/octeontx + +CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX +CFLAGS += -I$(RTE_SDK)/drivers/common/cpt + +# PMD code +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c + +# export include files +SYMLINK-y-include += + +# versioning export map +EXPORT_MAP := rte_pmd_octeontx_crypto_version.map + +# library dependencies +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_cryptodev +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf +DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build new file mode 100644 index 0000000000..656409089a --- /dev/null +++ b/drivers/crypto/octeontx/meson.build @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Cavium, Inc +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_pci'] +name = 'octeontx_crypto' + +sources = files('otx_cryptodev.c', + 'otx_cryptodev_ops.c') + +cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX' +includes += include_directories('../../common/cpt') diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c new file mode 100644 index 0000000000..43933ddf0d --- /dev/null +++ b/drivers/crypto/octeontx/otx_cryptodev.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ + +#include +#include +#include +#include +#include +#include + +/* CPT common headers */ +#include "cpt_pmd_logs.h" + +#include "otx_cryptodev.h" +#include "otx_cryptodev_ops.h" + +static int otx_cryptodev_logtype; + +static struct rte_pci_id pci_id_cpt_table[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID), + }, + /* sentinel */ + { + .device_id = 0 + }, +}; + +static void +otx_cpt_logtype_init(void) +{ + cpt_logtype = otx_cryptodev_logtype; +} + +static int +otx_cpt_pci_probe(struct rte_pci_driver *pci_drv, + struct rte_pci_device *pci_dev) +{ + struct rte_cryptodev *cryptodev; + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + int retval; + + if (pci_drv == NULL) + return -ENODEV; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + cryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id()); + if (cryptodev == NULL) + return -ENOMEM; + + cryptodev->device = &pci_dev->device; + cryptodev->device->driver = &pci_drv->driver; + cryptodev->driver_id = otx_cryptodev_driver_id; + + /* init user callbacks */ + TAILQ_INIT(&(cryptodev->link_intr_cbs)); + + /* init logtype used in common */ + otx_cpt_logtype_init(); + + /* Invoke PMD device initialization function */ + retval = otx_cpt_dev_create(cryptodev); + if (retval == 0) + return 0; + + CPT_LOG_ERR("[DRV %s]: Failed to create device " + "(vendor_id: 0x%x device_id: 0x%x", + pci_drv->driver.name, + (unsigned int) pci_dev->id.vendor_id, + (unsigned int) pci_dev->id.device_id); + + cryptodev->attached = RTE_CRYPTODEV_DETACHED; + + return -ENXIO; +} + +static int +otx_cpt_pci_remove(struct rte_pci_device *pci_dev) +{ + struct rte_cryptodev *cryptodev; + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + + if (pci_dev == NULL) + return -EINVAL; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + cryptodev = rte_cryptodev_pmd_get_named_dev(name); + if (cryptodev == NULL) + return -ENODEV; + + if (pci_dev->driver == NULL) + return -ENODEV; + + /* free crypto device */ + rte_cryptodev_pmd_release_device(cryptodev); + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + rte_free(cryptodev->data->dev_private); + + cryptodev->device = NULL; + cryptodev->device->driver = NULL; + cryptodev->data = NULL; + + return 0; +} + +static struct rte_pci_driver otx_cryptodev_pmd = { + .id_table = pci_id_cpt_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = otx_cpt_pci_probe, + .remove = otx_cpt_pci_remove, +}; + +static struct cryptodev_driver otx_cryptodev_drv; + +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver, + otx_cryptodev_driver_id); + +RTE_INIT(otx_cpt_init_log) +{ + /* Bus level logs */ + otx_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx"); + if (otx_cryptodev_logtype >= 0) + rte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE); +} diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h new file mode 100644 index 0000000000..6c2871d712 --- /dev/null +++ b/drivers/crypto/octeontx/otx_cryptodev.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ + +#ifndef _OTX_CRYPTODEV_H_ +#define _OTX_CRYPTODEV_H_ + +/* Cavium OCTEON TX crypto PMD device name */ +#define CRYPTODEV_NAME_OCTEONTX_PMD crypto_octeontx + +/* Device ID */ +#define PCI_VENDOR_ID_CAVIUM 0x177d +#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041 + +/* + * Crypto device driver ID + */ +uint8_t otx_cryptodev_driver_id; + +#endif /* _OTX_CRYPTODEV_H_ */ diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c new file mode 100644 index 0000000000..1b5f108840 --- /dev/null +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ + +#include + +#include "otx_cryptodev.h" +#include "otx_cryptodev_ops.h" + +int +otx_cpt_dev_create(struct rte_cryptodev *c_dev) +{ + RTE_SET_USED(c_dev); + return 0; +} diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h new file mode 100644 index 0000000000..3f2d8291a7 --- /dev/null +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ + +#ifndef _OTX_CRYPTODEV_OPS_H_ +#define _OTX_CRYPTODEV_OPS_H_ + +int +otx_cpt_dev_create(struct rte_cryptodev *c_dev); + +#endif /* _OTX_CRYPTODEV_OPS_H_ */ diff --git a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map new file mode 100644 index 0000000000..521e51f411 --- /dev/null +++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map @@ -0,0 +1,4 @@ +DPDK_18.11 { + + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 502292c747..6391f721d5 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -227,6 +227,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += -L$(LIBSSO_ZUC_PATH)/build -lsso _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -lrte_pmd_armv8 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy) _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC) += -lrte_pmd_dpaa2_sec