From: Ruifeng Wang Date: Wed, 15 Sep 2021 08:33:39 +0000 (+0800) Subject: net/i40e: fix risk in descriptor read in scalar Rx X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=c4d3e8fbe485f244391797f7610512de377675e0;p=dpdk.git net/i40e: fix risk in descriptor read in scalar Rx Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates that the rest of the descriptor words have valid values. Hence, the word containing DD bit must be read first before reading the rest of the descriptor words. Since the entire descriptor is not read atomically, on relaxed memory ordered systems like Aarch64, read of the word containing DD field could be reordered after read of other words. Read barrier is inserted between read of the word with DD field and read of other words. The barrier ensures that the fetched data is correct. Testpmd single core test showed no performance drop on x86 or N1SDP. On ThunderX2, 22% performance regression was observed. Fixes: 7b0cf70135d1 ("net/i40e: support ARM platform") Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli --- diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 41fe3bf481..e4cb33dc3c 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -744,6 +744,12 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) break; } + /** + * Use acquire fence to ensure that qword1 which includes DD + * bit is loaded before loading of other descriptor words. + */ + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); + rxd = *rxdp; nb_hold++; rxe = &sw_ring[rx_id]; @@ -860,6 +866,12 @@ i40e_recv_scattered_pkts(void *rx_queue, break; } + /** + * Use acquire fence to ensure that qword1 which includes DD + * bit is loaded before loading of other descriptor words. + */ + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); + rxd = *rxdp; nb_hold++; rxe = &sw_ring[rx_id];