From: zer0 Date: Sat, 19 Dec 2009 18:16:43 +0000 (+0100) Subject: ini X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=ccc6954bb046671b9e28c5806db5121c1eef49c0;p=aversive.git ini --- ccc6954bb046671b9e28c5806db5121c1eef49c0 diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 0000000..ec82f9f --- /dev/null +++ b/AUTHORS @@ -0,0 +1,17 @@ + +Aversive Project is Copyrighted Droids Corporation (2009) + +Historical authors are Christophe RIEHL (tof) and Olivier MATZ (zer0). + +We are members of Droids Corporation -> http://www.droids-corp.org + +Thanks to other contributors / users : + jlg + JDaM + Serpilliere + Eirbot (robotik club of ENSEIRB, http://www.enseirb.fr/robot) + Microb Technology (an independant robotik club) + ESIAL robotik club + The whole avr-gcc team for their great work !!! + Some people will be added here, you can find their names in sources. + diff --git a/COPYING b/COPYING new file mode 100644 index 0000000..b386943 --- /dev/null +++ b/COPYING @@ -0,0 +1,15 @@ + + Copyright Droids Corporation, Microb Technology, Eirbot (2007) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA diff --git a/CVS/Entries b/CVS/Entries new file mode 100644 index 0000000..a1c2304 --- /dev/null +++ b/CVS/Entries @@ -0,0 +1,10 @@ +/AUTHORS/1.1.10.3/Fri Jan 30 20:35:47 2009//Tb_zer0 +/COPYING/1.1.10.2/Mon Mar 5 12:33:03 2007//Tb_zer0 +/Makefile/1.35.4.6/Thu Dec 6 08:57:59 2007//Tb_zer0 +/README/1.3.10.4/Tue Mar 20 00:06:36 2007//Tb_zer0 +/RELEASE/1.45.6.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +D/config//// +D/include//// +D/mk//// +D/modules//// +D/projects//// diff --git a/CVS/Repository b/CVS/Repository new file mode 100644 index 0000000..b26ff0c --- /dev/null +++ b/CVS/Repository @@ -0,0 +1 @@ +aversive diff --git a/CVS/Root b/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/CVS/Tag b/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/CVS/Template b/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..aa4d034 --- /dev/null +++ b/Makefile @@ -0,0 +1,107 @@ +# Microb Technology, Eirbot, Droids-corp 2005 - Zer0 +# Makefile for generating all tests ! +# + +PROJECT_DIRS=\ +modules/base/math/fixed_point/test\ +modules/base/math/vect2/test\ +modules/base/scheduler/test\ +modules/crypto/test\ +modules/encoding/hamming/test\ +modules/encoding/base64/test\ +modules/comm/uart/test\ +modules/debug/diagnostic/test\ +modules/ihm/menu/test\ +modules/hardware/adc/test\ +modules/hardware/timer/test\ +modules/hardware/pwm/test\ +modules/devices/ihm/lcd/test\ +modules/devices/servo/multiservo/test\ +modules/devices/robot/robot_system/test\ +modules/devices/control_system/control_system_manager/test\ +modules/devices/control_system/filters/pid/test\ +modules/devices/control_system/filters/quadramp/test\ +modules/debug/error/test\ +projects/example1\ +projects/example2 + +HOSTPROJECT_DIRS=\ +modules/base/math/fixed_point/test\ +modules/base/math/vect2/test\ +modules/crypto/test\ +modules/encoding/hamming/test\ +modules/encoding/base64/test\ +modules/ihm/menu/test\ +modules/devices/control_system/control_system_manager/test\ +modules/devices/control_system/filters/pid/test\ +modules/devices/control_system/filters/quadramp/test + +CFLAGS=-Werror +export CFLAGS + + +all: avrall hostall + + +clean: avrclean hostclean + + +%_config: + @if [ \( ! -f $(@:_config=)/.aversive_conf \) -o \ + \( ! -f $(@:_config=)/autoconf.h \) ]; then \ + echo -n Configuring $(@:_config=)... ; \ + make -C $(@:_config=) noconfig > /dev/null; \ + echo done ; \ + fi + +### AVR + +avrall: $(PROJECT_DIRS:=_config) $(PROJECT_DIRS:=_avrmake) + + +avrclean: $(PROJECT_DIRS:=_avrclean) + + +%_avrmake: + @echo + @echo "Module $(@:_avrmake=) (avr)" | sed 's,.,=,g' + @echo "Module $(@:_avrmake=) (avr)" + @echo "Module $(@:_avrmake=) (avr)" | sed 's,.,=,g' + @echo + make -C $(@:_avrmake=) + + +%_avrclean: + make -C $(@:_avrclean=) clean + + +### HOST + +hostall: $(HOSTPROJECT_DIRS:=_config) $(HOSTPROJECT_DIRS:=_hostmake) + + +hostclean: $(HOSTPROJECT_DIRS:=_hostclean) + + +%_hostmake: + @echo + @echo "Module $(@:_hostmake=) (host)" | sed 's,.,=,g' + @echo "Module $(@:_hostmake=) (host)" + @echo "Module $(@:_hostmake=) (host)" | sed 's,.,=,g' + @echo + make -C $(@:_hostmake=) H=1 + + +%_hostclean: + make -C $(@:_hostclean=) clean H=1 + + +### + +mrproper: + find . -name "autoconf.h" -o -name ".aversive_conf" -o -name "*.hex" -o -name "*~" -o -name "*.eep" -o -name "*.obj" -o -name "*.elf" -o -name "*.map" -o -name "*.obj" -o -name "*.a90" -o -name "*.sym" -o -name "*.lnk" -o -name "*.lss" -o -name "*.a" -o -name "*.{avr,host}.d" -o -name "*.o" -o -name "*.avr.d.*" -o -name "*.host.d.*" -o -name "*.lst" | xargs rm -f + + +.PHONY : all clean avrall avrclean hostall hostclean \ + $(PROJECT_DIRS:=.avrall) $(PROJECT_DIRS:=.avrclean) \ +$(HOSTPROJECT_DIRS:=.hostall) $(HOSTPROJECT_DIRS:=.hostclean) diff --git a/README b/README new file mode 100644 index 0000000..731e3d4 --- /dev/null +++ b/README @@ -0,0 +1,81 @@ +== AVERSIVE == + +Authors (see AUTHORS file for details) : +- Christophe RIEHL +- Olivier MATZ + +(Droids-Corporation, Microb Technology, Eirbot) + +=== Introduction + +This is a development framework for AVR. You need avr-gcc to run +it. The goal of this project is to provide modules to make development +on avr easier. + +Untar the archive (or checkout it from the CVS), run ./configure, it +will generate several Makefiles (if you skip this step, the main +Makefile will automatiquely do it for you). You can edit these files +to customize some settings. You can now type make to compile all tests +programs of the framework. If you want to create a new project, there +are some examples. + +This is a development version, there are certainly a lot of +bugs. Don't hesitate to tell us if you find one. +-> avr-list@droids-corp.org + +You can also have a look to our bugzilla : +-> http://bugzilla.droids-corp.org + +There's a page about this project : +-> http://wiki.droids-corp.org/mediawiki/index.php/Aversive + +=== The aversive source tree + +config -> files related to aversive configuration + config/fuses_defs -> fuse names and help + config/gen_headers -> dirty scripts for generating some .h + config/scripts -> project configuration scripts (imported + from linux-2.4 kernel) + +include -> generic Aversive include files, that are + not related to a module + +mk -> Aversive Makefiles (project, module, and + templates) + +modules -> modules directory. A "module" is a small + library that provide a specific + functionnality + modules/base -> common modules, frequently used + modules/comm -> communication modules (uart, spi, i2c, ...) + modules/crypto -> modules for cryptographic operations + modules/debug -> helper modules for debugging + modules/devices -> modules related to a device that is not + part of an Atmel AVR (lcd, motors, ...) + modules/encoding -> buffer conversion (base64, hamming) + modules/hardware -> generic interfaces module for specific AVR + hardware (timers, ADC, ...) + modules/ihm -> Human-machine interface modules (menu, and + probably a future CLI) + +projects -> Project examples (to be enhanced) + projects/example1 + projects/example2 + + +=== Using Aversive + +You need avr-gcc/avr-libc to use Aversive. + +Once you have untared the archive (or checkouted it from the CVS), you +can run 'make' to compile all tests programs. + +--- + +If you want to compile a test program: + +cd projects/example1 +make menuconfig +make + + diff --git a/RELEASE b/RELEASE new file mode 100644 index 0000000..4636dbc --- /dev/null +++ b/RELEASE @@ -0,0 +1,4 @@ +See more informations in bugzilla : + +http://bugzilla.droids-corp.org + diff --git a/config/.config b/config/.config new file mode 100644 index 0000000..9603725 --- /dev/null +++ b/config/.config @@ -0,0 +1,117 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_UTILS=y +CONFIG_MODULE_UTILS_CREATE_CONFIG=y +CONFIG_MODULE_WAIT=y +CONFIG_MODULE_WAIT_CREATE_CONFIG=y +CONFIG_MODULE_LIST=y +CONFIG_MODULE_LIST_CREATE_CONFIG=y +CONFIG_MODULE_NOSCHED=y +# CONFIG_MODULE_SCHEDULER1 is not set +# CONFIG_MODULE_SCHEDULER2 is not set +# CONFIG_MODULE_SCHEDULER1_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER2_CREATE_CONFIG is not set + +# +# Communication modules +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +# CONFIG_AVRDUDE_FUSE is not set diff --git a/config/CVS/Entries b/config/CVS/Entries new file mode 100644 index 0000000..d6c952e --- /dev/null +++ b/config/CVS/Entries @@ -0,0 +1,8 @@ +/.config/1.9.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/Configure.help/1.13.4.19/Sat Apr 25 09:06:43 2009//Tb_zer0 +/config.in/1.42.4.32/Sun Nov 8 17:33:14 2009//Tb_zer0 +/generate_aversive_config/1.23.4.17/Sat May 2 10:01:38 2009//Tb_zer0 +/prog_fuses.sh/1.3.4.5/Sun Apr 6 17:33:57 2008//Tb_zer0 +D/fuses_defs//// +D/gen_headers//// +D/scripts//// diff --git a/config/CVS/Repository b/config/CVS/Repository new file mode 100644 index 0000000..06ddf55 --- /dev/null +++ b/config/CVS/Repository @@ -0,0 +1 @@ +aversive/config diff --git a/config/CVS/Root b/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/config/CVS/Tag b/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/config/CVS/Template b/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/config/Configure.help b/config/Configure.help new file mode 100644 index 0000000..f300a4f --- /dev/null +++ b/config/Configure.help @@ -0,0 +1,365 @@ +# +# Format of this file: descriptionvariable helptext.... +# If the question being documented is of type "choice", we list +# only the first occurring config variable. The help texts +# must not contain empty lines. No variable should occur twice; if it +# does, only the first occurrence will be used by Configure. The lines +# in a help text should be indented two positions. Lines starting with +# `#' are ignored. To be nice to menuconfig, limit your lines to 70 +# characters. Use emacs' kfill.el to edit this file or you lose. +# + +CONFIG_MCU_ATMEGA128 + Choose your target device. + +CONFIG_QUARTZ + Choose the speed of your target device. This frequency is specified in + Hertz. + +CONFIG_OPTM_0 + Choose this option to customize code optimization (see + the gcc manual for details). The -Os option is recommanded + for most purposes. + +CONFIG_MATH_LIB + Include math lib in the linker flags. + +CONFIG_MINIMAL_PRINTF + Choose printf style. The minimal printf cannot handle floats. The advanced + printf can, but it requires the math lib. Disable it if you don't use + printf, you'll win some prog space. + +CONFIG_FORMAT_IHEX + Set the default format of generated executable. The Intel HEX + format is the default choice, as it is a simple format, supported + by avrdude. You can also choose raw binary or S-records (see + avr-objcopy manual for details). + + + +CONFIG_MODULE_CIRBUF + This module provides a circular buffer implementation (fifo or lifo). + +CONFIG_MODULE_FIXED_POINT + This module provides functions for using fixed point variables. Using + this type can be faster and/or more accurate than using float in some + cases (for example if you mainly do sums). It requires the math lib. + + +CONFIG_MODULE_VECT2 + This module provides functions for converting 2D vectors from + polar to cartesian and vice versa. + + +CONFIG_MODULE_SCHEDULER + The 'scheduler' module is NOT a scheduler in the same way than in + a multitask kernel. This module allow to schedule functions in the + future (only a call, or periodical call). If CONFIG_MODULE_SCHEDULER_USE_TIMERS + option is not enabled, the functions are called from TIMER0 interrupt, + else you can choose which timer to use. This module is able to handle + priority between events. + +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG + Create a scheduler_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_SCHEDULER_TIMER0 + Use either the hardware/timer module, the timer0 or a manual call + for the to call the scheduler. The generic timer module support + many archs and timers. If you don't enable it, you must use TIMER0 + overflow interrupt, and only some AVR are supported, or you should + can call the scheduler manually. In this case, the SCHEDULER_UNIT + macro has to be defined in configuration file. + + +CONFIG_TIME + This module can be used to get a human readable time. It uses the + scheduler module. Its goal is not to be very precise, but just + simple to use. provides two timers: one in s and us, and one in + us which doesn't overflow on seconds (better to substract two + times) + +CONFIG_MODULE_TIME_CREATE_CONFIG + Create a time_config.h file if it does not exist, with a default + configuration. + + +CONFIG_TIME_EXT + This module can be used to have a very precise, yet human-readable, + time. It uses TIMER2 in asynchronous mode, you MUST have a 32.768kHz + quartz connected to TOSC1 and TOSC2 pins. + Provides a global time value (instant 0 is the initialization of the + module). Warning: this module uses some hardcoded values for + timer 2 configuration, it may not work on all AVR. + +CONFIG_MODULE_TIME_EXT_CREATE_CONFIG + Create a time_ext_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_UART + This module provide functions to use the embedded UART or USART in + the AVR. With this module, it is more easy to configure it, and + data can be emited on interruption. The uart module also contains + a fifo for emission and reception (configurable in uart_config.h). + +CONFIG_MODULE_UART_CREATE_CONFIG + Create a uart_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_SPI + This module provide functions to use the embedded SPI in + the AVR. + +CONFIG_MODULE_SPI_CREATE_CONFIG + Create a spi_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_I2C + This module provide functions to use the embedded I2C (TWI + interface) in the AVR. + +CONFIG_MODULE_I2C_CREATE_CONFIG + Create a i2c_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_MF2_CLIENT + This module provide functions to interface with a device that uses + the mf2 protocol. With the client, you can interface with a PS/2 keyboard. + +CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER + Enabling this option avoid active loops and enable mf2 watchdog. + The watchdog avoid desynchronisation if there is transmission + problems or if keyboard is unplugged during operation. + +CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG + Create a mf2_client_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_MF2_SERVER + This module provide functions to interface with a device that uses + the mf2 protocol. With the server, you can emulate a PS/2 keyboard. + +CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG + Create a mf2_server_config.h file if it does not exist, with a default + configuration. + + +CONFIG_MODULE_TIMER + This module provide some simple functions to use some timers + functionnalities of AVR. + +CONFIG_MODULE_TIMER_CREATE_CONFIG + Create a timer_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_PWM + This module provide a driver to use the PWM (Pulse Width Modulation) + hardware of the AVR : the configuration can be statically or dynamically + defined. This module can be replaced by PWM_NG. + +CONFIG_MODULE_PWM_CREATE_CONFIG + Create a pwm_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_PWM_NG + This module provide a driver to use the PWM (Pulse Width Modulation) + hardware of the AVR : the configuration is set dynamically. + + + +CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL + This module drives a 3-phase synchronous motor (called brushless) + This is done with 3 hall sensors who give the position of the rotor. + The controller polls these sensors, and updates 3 PWM outputs to drive + the 3 phases. + +CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE + This is a double implementation of the MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL + This module drives two 3-phase synchronous motor (called brushless) + This is done with 3 hall sensors who give the position of the rotor. + The controller polls these sensors, and updates 3 PWM outputs to drive + the 3 phases of each motor + +CONFIG_MODULE_CC2420 + This modules implements the protocol to use a CC2420 radio chip. + This radio chip is IEEE 802.15.4 compliant and is widely used + in wireless sensors. + This modules requires SPI to be activated. + +CONFIG_MODULE_MENU + The menu module provides some helpers to create a human-machine + interface that uses a tree-organized static menu. + +CONFIG_MODULE_VT100 + This module provides functions to parse vt100 commands. + +CONFIG_MODULE_RDLINE + The rdline module provides an interface for editing a buffer on a + vt100 terminal, for instance through a UART. + +CONFIG_MODULE_RDLINE_CREATE_CONFIG + Create a rdline_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_RDLINE_KILL_BUF + Enable cut/paste (with CTRL-k and CTRL-y) + +CONFIG_MODULE_RDLINE_HISTORY + Enable history buffer, to save last commands (up and down arrows) + +CONFIG_MODULE_PARSE + The parse module is able to parse a buffer containing strings, + numbers, (...) into a C structure. + + +CONFIG_MODULE_LCD + This module provide an interface to control an external standard + LCD screen (text mode). + +CONFIG_MODULE_LCD_CREATE_CONFIG + Create a lcd_config.h file if it does not exist, with a default + configuration. + + +CONFIG_MODULE_MULTISERVO + This module provide an interface to command many servo (like in model + toys). It uses one timer (a 8 bits or a 16 bits, depending on accuracy + you want). As it does not uses the PWM mode of timer, it can consum + some CPU time in interrupt, but you can command up to 10 servos + and the output ports can be on a non-specialized port. + +CONFIG_MODULE_MULTISERVO_CREATE_CONFIG + Create a servo_config.h file if it does not exist, with a default + configuration. + + +CONFIG_MODULE_ENCODERS_MICROB + Provide an interface for reading values from encoders. The electric + scheme is provided in the file encoders_microb.h + +CONFIG_MODULE_ENCODERS_SPI + Provide an interface for reading values from encoders. This module + uses the SPI interface to update values. + +CONFIG_MODULE_ENCODERS_EIRBOT + Provide an interface for reading values from encoders. The electric + scheme should be provided in the file encoders_eirbot.h + +CONFIG_MODULE_ROBOT_SYSTEM + The Robot System module role is to provide a virtual system that + represents a robot by its angle/distance instead of left/right + wheels. It provides a virtual angle/distance PWM and a virtual + angle/distance encoder. + +CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + If the robot has external and motor encoder, you can use both + by defining this option. + +CONFIG_MODULE_POSITION_MANAGER + This module processes the position of the robot, depending of the + value returned by the associated robot system, and some physical + parameters of the robot. + +CONFIG_MODULE_TRAJECTORY_MANAGER + Manage the control systems of the robot, depending on the position, + the physical parameters of the robot, and the user consign. Command + can be something like trajectory_goto_xya(...) + +CONFIG_MODULE_BLOCKING_DETECTION_MANAGER + Detect when the robot is blocked on an obstacle. + +CONFIG_MODULE_OBSTACLE_AVOIDANCE + Determine a optimized path from a point to antoher, avioding + obstacles. + + +CONTROL_SYSTEM_MANAGER + A module that manages a servo control system. It uses filters, like + the PID filter to work. This module also needs a the in/out functions + of the controled system, for instance encoders and PWM, but it can + any other func that has the same interface. + +CONFIG_MODULE_PID + This filter provides a PID (proportionnal, integral, derivate). + +CONFIG_MODULE_PID_CREATE_CONFIG + Create a pid_config.h file if it does not exist, with a default + configuration. + +CONFIG_MODULE_RAMP + This module limits the variation of the input of the filter. It can + be used in a speed control system as a consign filter to set a + maximum acceleration. + +CONFIG_MODULE_QUADRAMP + This module limits the variation of the input, and the variation + of the derivate of the input. It can be used in a position control + system as a consign filter to specify a maximum acceleration and a + maximum speed. + +CONFIG_MODULE_QUADRAMP_DERIVATE + This module generates the same kind of ramp than the quadramp. + however here we generate the derivate of this ramp, which is a speed + consign which can be fed to a speed PID. + The advantages are less computation (no square root), and a better + robustness against blocking. + +CONFIG_MODULE_BIQUAD + This module is a general digital filter. It is very useful for all + filtering purposes, not only for control loops. You can implement + every digital filter with this module ! Sometimes you will have to + put a few in series. + +CONFIG_MODULE_AES + Enable AES crypto functions in Aversive + +CONFIG_MODULE_AES_CTR + Enable AES counter mode + +CONFIG_MODULE_MD5 + Enable MD5 alg functions in Aversive + +CONFIG_MODULE_MD5_HMAC + Enable md5 HMAC functions in Aversive + +CONFIG_MODULE_RC4 + Enable RC4 alg functions in Aversive + + +CONFIG_MODULE_BASE64 + Enable base64 encoding module, compatible with PEM. + +CONFIG_MODULE_HAMMING + Enable Hamming encoding module, which is an error detection + coding system. + + +CONFIG_MODULE_DIAGNOSTIC + this module contains tools to view the stack space or the processor + charge (interrupts) + +CONFIG_MODULE_ERROR + this module helps storing and handling errors, warnings and so on... + +CONFIG_AVRDUDE_PROG_FUTURELEC + Choose the hardware programmer type. Please see the avrdude manual + for details. + +CONFIG_AVRDUDE_PORT + Choose the avrdude device. Under linux, it can be '/dev/parport0' or + '/dev/ttyS0', depending on the programmer type. Under win32, it can + look like 'com1' for instance. + +CONFIG_AVRDUDE_BAUDRATE + Choose the baudrate. This can be very useful if you are using a stk500 + bootloader, and you want to speed it up. + +CONFIG_AVRDUDE_CHECK_SIGNATURE + Avrdude normally checks the device signature, but some bootloaders doesn't + implement this, or your device may not communicate with Avrdude. This option + allows you to bypass this check. + +CONFIG_AVRDUDE_FUSE + If you enable this option, a script will be launched just after this + saving the configuration. This script uses avrdude to program the + fuse value of your target device. NOT IMPLEMENTED YET. diff --git a/config/config.in b/config/config.in new file mode 100644 index 0000000..583b736 --- /dev/null +++ b/config/config.in @@ -0,0 +1,553 @@ +mainmenu_name "Aversive project configuration" + +############################################################################# + +mainmenu_option next_comment +comment 'Hardware' +# name must be CONFIG_MCU_##mcu name## + +choice 'Avr type' "\ + AT90s2313 CONFIG_MCU_AT90S2313 \ + AT90s2323 CONFIG_MCU_AT90S2323 \ + AT90s2333 CONFIG_MCU_AT90S3333 \ + AT90s2343 CONFIG_MCU_AT90S2343 \ + ATtiny22 CONFIG_MCU_ATTINY22 \ + ATtiny26 CONFIG_MCU_ATTINY26 \ + AT90s4414 CONFIG_MCU_AT90S4414 \ + AT90s4433 CONFIG_MCU_AT90S4433 \ + AT90s4434 CONFIG_MCU_AT90S4434 \ + AT90s8515 CONFIG_MCU_AT90S8515 \ + AT90c8534 CONFIG_MCU_AT90S8534 \ + AT90s8535 CONFIG_MCU_AT90S8535 \ + AT86rf401 CONFIG_MCU_AT86RF401 \ + ATmega103 CONFIG_MCU_ATMEGA103 \ + ATmega603 CONFIG_MCU_ATMEGA603 \ + AT43usb320 CONFIG_MCU_AT43USB320 \ + AT43usb355 CONFIG_MCU_AT43USB355 \ + AT76c711 CONFIG_MCU_AT76C711 \ + ATmega8 CONFIG_MCU_ATMEGA8 \ + ATmega48 CONFIG_MCU_ATMEGA48 \ + ATmega88 CONFIG_MCU_ATMEGA88 \ + ATmega8515 CONFIG_MCU_ATMEGA8515 \ + ATmega8535 CONFIG_MCU_ATMEGA8535 \ + ATtiny13 CONFIG_MCU_ATTINY13 \ + ATtiny2313 CONFIG_MCU_ATTINY2313 \ + ATmega16 CONFIG_MCU_ATMEGA16 \ + ATmega161 CONFIG_MCU_ATMEGA161 \ + ATmega162 CONFIG_MCU_ATMEGA162 \ + ATmega163 CONFIG_MCU_ATMEGA163 \ + ATmega165 CONFIG_MCU_ATMEGA165 \ + ATmega168 CONFIG_MCU_ATMEGA168 \ + ATmega169 CONFIG_MCU_ATMEGA169 \ + ATmega32 CONFIG_MCU_ATMEGA32 \ + ATmega323 CONFIG_MCU_ATMEGA323 \ + ATmega325 CONFIG_MCU_ATMEGA325 \ + ATmega3250 CONFIG_MCU_ATMEGA3250 \ + ATmega64 CONFIG_MCU_ATMEGA64 \ + ATmega645 CONFIG_MCU_ATMEGA645 \ + ATmega6450 CONFIG_MCU_ATMEGA6450 \ + ATmega128 CONFIG_MCU_ATMEGA128 \ + ATmega1281 CONFIG_MCU_ATMEGA1281 \ + AT90can128 CONFIG_MCU_AT90CAN128 \ + AT94k CONFIG_MCU_AT94K \ + AT90s1200 CONFIG_MCU_AT90S1200 \ + ATmega2560 CONFIG_MCU_ATMEGA2560 \ + ATmega256 CONFIG_MCU_ATMEGA256 \ +" ATmega128 + +int 'Quartz Frequency (Hz)' CONFIG_QUARTZ '12000000' + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Generation options' + + +choice 'Optimization level' "\ + -O0 CONFIG_OPTM_0 \ + -O1 CONFIG_OPTM_1 \ + -O2 CONFIG_OPTM_2 \ + -O3 CONFIG_OPTM_3 \ + -Os CONFIG_OPTM_S \ +" -Os + +bool 'Include Math lib' CONFIG_MATH_LIB + +bool 'fdevopen compatibility' CONFIG_FDEVOPEN_COMPAT + +# printf version, advanced depends on math lib +if [ "$CONFIG_MATH_LIB" = "y" ]; then + +choice 'Printf capabilities' "\ + none CONFIG_NO_PRINTF \ + minimal CONFIG_MINIMAL_PRINTF \ + standard CONFIG_STANDARD_PRINTF \ + advanced CONFIG_ADVANCED_PRINTF \ +" standard + +else + +choice 'Printf capabilities' "\ + none CONFIG_NO_PRINTF \ + minimal CONFIG_MINIMAL_PRINTF \ + standard CONFIG_STANDARD_PRINTF \ +" standard + +fi + +choice 'Default output format' "\ + ihex CONFIG_FORMAT_IHEX \ + srec CONFIG_FORMAT_SREC \ + binary CONFIG_FORMAT_BINARY \ +" ihex + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Base modules' + +comment 'Enable math library in generation options to see all modules' + +#### CIRCULAR BUFFER +bool 'Circular buffer' CONFIG_MODULE_CIRBUF +dep_bool ' |-- Allow buffer larger than 127' CONFIG_MODULE_CIRBUF_LARGE \ + $CONFIG_MODULE_CIRBUF + + +#### FIXED_POINT +dep_bool 'Fixed_Point lib' CONFIG_MODULE_FIXED_POINT \ + $CONFIG_MATH_LIB + + +#### VECT2 +dep_bool 'Vect2 lib' CONFIG_MODULE_VECT2 \ + $CONFIG_MATH_LIB + +#### GEOMETRY +dep_bool 'Geometry lib' CONFIG_MODULE_GEOMETRY \ + $CONFIG_MATH_LIB + +#### SCHEDULER +bool 'Scheduler' CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- enable debug statistics' CONFIG_MODULE_SCHEDULER_STATS \ + $CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- Create Default scheduler config' CONFIG_MODULE_SCHEDULER_CREATE_CONFIG \ + $CONFIG_MODULE_SCHEDULER + +if [ "$CONFIG_MODULE_TIMER" = "y" ]; then + +choice 'Scheduler config' "use_timer_module CONFIG_MODULE_SCHEDULER_USE_TIMERS\ + use_timer0 CONFIG_MODULE_SCHEDULER_TIMER0\ + manual CONFIG_MODULE_SCHEDULER_MANUAL" use_timer_module + +else + +choice 'Scheduler config' "use_timer_module CONFIG_MODULE_SCHEDULER_USE_TIMERS\ + use_timer0 CONFIG_MODULE_SCHEDULER_TIMER0\ + manual CONFIG_MODULE_SCHEDULER_MANUAL" use_timer0 + +fi + +#### TIME +dep_bool 'Time' CONFIG_MODULE_TIME \ + $CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- Create Default time config' CONFIG_MODULE_TIME_CREATE_CONFIG \ + $CONFIG_MODULE_TIME + +#### TIME_EXT +bool 'Time - reloaded' CONFIG_MODULE_TIME_EXT + +dep_bool ' |-- Create Default time_ext config' CONFIG_MODULE_TIME_EXT_CREATE_CONFIG \ + $CONFIG_MODULE_TIME_EXT + + + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Communication modules' + +comment 'uart needs circular buffer, mf2 client may need scheduler' + +#### UART +dep_bool 'Uart' CONFIG_MODULE_UART \ + $CONFIG_MODULE_CIRBUF + +dep_bool ' |-- Allow 9 bits operations' CONFIG_MODULE_UART_9BITS \ + $CONFIG_MODULE_UART + +dep_bool ' |-- Create Default uart config' CONFIG_MODULE_UART_CREATE_CONFIG \ + $CONFIG_MODULE_UART + +#### SPI +bool 'spi (very EXPERIMENTAL)' CONFIG_MODULE_SPI + +dep_bool ' |-- Create Default spi config' CONFIG_MODULE_SPI_CREATE_CONFIG \ + $CONFIG_MODULE_SPI + +#### I2C +bool 'i2c' CONFIG_MODULE_I2C + +dep_bool ' |-- Allow master mode' CONFIG_MODULE_I2C_MASTER \ + $CONFIG_MODULE_I2C + +dep_bool ' |-- Allow multimaster mode' CONFIG_MODULE_I2C_MULTIMASTER \ + $CONFIG_MODULE_I2C_MASTER + +dep_bool ' |-- Create Default i2c config' CONFIG_MODULE_I2C_CREATE_CONFIG \ + $CONFIG_MODULE_I2C + + +#### MF2_CLIENT +bool 'mf2_client (very EXPERIMENTAL)' CONFIG_MODULE_MF2_CLIENT + +dep_bool ' |-- Use scheduler (watchdog + no active loops)' CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER \ + $CONFIG_MODULE_MF2_CLIENT \ + $CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- Create Default mf2_client config' CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG \ + $CONFIG_MODULE_MF2_CLIENT + +#### MF2_SERVER +bool 'mf2_server (very EXPERIMENTAL)' CONFIG_MODULE_MF2_SERVER + +dep_bool ' |-- Create Default mf2_server config' CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG \ + $CONFIG_MODULE_MF2_SERVER + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Hardware modules' + +#### TIMER +bool 'Timer' CONFIG_MODULE_TIMER + +dep_bool ' |-- Create Default timer config' CONFIG_MODULE_TIMER_CREATE_CONFIG \ + $CONFIG_MODULE_TIMER + +dep_bool ' |-- Allow dynamic modification of prescaler' CONFIG_MODULE_TIMER_DYNAMIC \ + $CONFIG_MODULE_TIMER + + +#### PWM +bool 'PWM' CONFIG_MODULE_PWM + +dep_bool ' |-- Create Default pwm config' CONFIG_MODULE_PWM_CREATE_CONFIG \ + $CONFIG_MODULE_PWM + + +#### PWM_NG +bool 'PWM_ng' CONFIG_MODULE_PWM_NG + +#### ADC +bool 'ADC' CONFIG_MODULE_ADC + +dep_bool ' |-- Create Default adc config' CONFIG_MODULE_ADC_CREATE_CONFIG \ + $CONFIG_MODULE_ADC + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'IHM modules' + +#### menu +bool 'Menu' CONFIG_MODULE_MENU + +#### vt100 +bool 'Vt100' CONFIG_MODULE_VT100 + +#### rdline +dep_bool 'Rdline' CONFIG_MODULE_RDLINE \ + $CONFIG_MODULE_VT100 \ + $CONFIG_MODULE_CIRBUF + +dep_bool ' |-- Create Default rdline config' CONFIG_MODULE_RDLINE_CREATE_CONFIG \ + $CONFIG_MODULE_RDLINE + +dep_bool ' |-- Enable cut/paste' CONFIG_MODULE_RDLINE_KILL_BUF \ + $CONFIG_MODULE_RDLINE + +dep_bool ' |-- Enable history' CONFIG_MODULE_RDLINE_HISTORY \ + $CONFIG_MODULE_RDLINE + +#### parse + +bool 'Parse' CONFIG_MODULE_PARSE +dep_bool ' |-- Do not parse float' CONFIG_MODULE_PARSE_NO_FLOAT \ + $CONFIG_MODULE_PARSE + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'External devices modules' + +#### LCD +bool 'LCD' CONFIG_MODULE_LCD + +dep_bool ' |-- Create Default lcd config' CONFIG_MODULE_LCD_CREATE_CONFIG \ + $CONFIG_MODULE_LCD + +#### SERVO +bool 'Multiservo' CONFIG_MODULE_MULTISERVO + +dep_bool ' |-- Create Default servo config' CONFIG_MODULE_MULTISERVO_CREATE_CONFIG \ + $CONFIG_MODULE_MULTISERVO + +bool 'AX-12' CONFIG_MODULE_AX12 + +dep_bool ' |-- Create Default AX-12 config' CONFIG_MODULE_AX12_CREATE_CONFIG\ + $CONFIG_MODULE_AX12 + +mainmenu_option next_comment +comment 'Brushless motor drivers (you should enable pwm modules to see all)' + +#### CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL +dep_bool '3 phase motor with digital hall sensors' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL \ + $CONFIG_MODULE_PWM + +dep_bool ' |-- Create Default brushless_3phase_digital_hall config' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG \ + $CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL + +#### CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE +dep_bool 'two 3 phase motor with digital hall sensors' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE \ + $CONFIG_MODULE_PWM + +dep_bool ' Create Default brushless_3phase_digital_hall_double config' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG \ + $CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE + +endmenu # (brushless) + +mainmenu_option next_comment +comment 'Encoders (you need comm/spi for encoders_spi)' + +#### ENCODERS +bool 'Encoders (microb)' CONFIG_MODULE_ENCODERS_MICROB + +dep_bool ' |-- Create Default encoders_microb config' CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG \ + $CONFIG_MODULE_ENCODERS_MICROB + +#### ENCODERS +bool 'Encoders (eirbot)' CONFIG_MODULE_ENCODERS_EIRBOT + +dep_bool ' |-- Create Default encoders_eirbot config' CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG \ + $CONFIG_MODULE_ENCODERS_EIRBOT + +#### ENCODERS +dep_bool 'Encoders_spi (microb)' CONFIG_MODULE_ENCODERS_SPI \ + $CONFIG_MODULE_SPI + +dep_bool ' |-- Create Default encoders_spi config' CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG \ + $CONFIG_MODULE_ENCODERS_SPI + +endmenu # (encoders) + +mainmenu_option next_comment +comment 'Robot specific modules' + +#### ROBOT_SYSTEM +dep_bool 'Robot System' CONFIG_MODULE_ROBOT_SYSTEM \ + $CONFIG_MODULE_FIXED_POINT + +dep_bool ' |-- Allow motor and external encoders' CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT \ + $CONFIG_MODULE_ROBOT_SYSTEM + +#### POSITION_MANAGER +dep_bool 'Position manager' CONFIG_MODULE_POSITION_MANAGER \ + $CONFIG_MODULE_ROBOT_SYSTEM + +dep_bool ' |-- Compensate centrifugal force' CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE \ + $CONFIG_MODULE_POSITION_MANAGER + +#### TRAJECTORY MANAGER +dep_bool 'Trajectory manager' CONFIG_MODULE_TRAJECTORY_MANAGER \ + $CONFIG_MODULE_POSITION_MANAGER \ + $CONFIG_MODULE_SCHEDULER \ + $CONFIG_MODULE_VECT2 \ + $CONFIG_MODULE_FIXED_POINT + +#### BLOCKING DETECTION MANAGER +bool 'Blocking detection manager' CONFIG_MODULE_BLOCKING_DETECTION_MANAGER + +#### OBSTACLE AVOIDANCE +dep_bool 'Obstacle Avoidance' CONFIG_MODULE_OBSTACLE_AVOIDANCE\ + $CONFIG_MODULE_GEOMETRY + +dep_bool ' |-- Create Default Obstacle Avoidance config' CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG \ + $CONFIG_MODULE_OBSTACLE_AVOIDANCE + +endmenu # (robot) + +mainmenu_option next_comment +comment 'Control system modules' + +#### CONTROL SYSTEM MANAGER +bool 'Control System Manager' CONFIG_MODULE_CONTROL_SYSTEM_MANAGER + +comment 'Filters' + +bool 'PID' CONFIG_MODULE_PID + +dep_bool ' |-- Create Default PID config' CONFIG_MODULE_PID_CREATE_CONFIG \ + $CONFIG_MODULE_PID + +bool 'ramp' CONFIG_MODULE_RAMP + +bool 'Quadramp' CONFIG_MODULE_QUADRAMP + +bool 'Quadramp derivate' CONFIG_MODULE_QUADRAMP_DERIVATE + +bool 'Biquad' CONFIG_MODULE_BIQUAD + +endmenu # (control system) + + +mainmenu_option next_comment +comment 'Radio devices' +comment 'Some radio devices require SPI to be activated' +#### RADIO DEVICES +dep_bool 'CC2420 Radio Device (IEEE 802.15.4) (VERY EXPERIMENTAL)' CONFIG_MODULE_CC2420 \ + $CONFIG_MODULE_SPI + +dep_bool ' |-- Create Default CC2420 config' CONFIG_MODULE_CC2420_CREATE_CONFIG \ + $CONFIG_MODULE_CC2420 + +endmenu # radio + + +endmenu # (devices) + +############################################################################# + + +mainmenu_option next_comment +comment 'Crypto modules' + +comment 'Crypto modules depend on utils module' + +#### AES +bool 'aes' CONFIG_MODULE_AES + +dep_bool 'aes counter mode' CONFIG_MODULE_AES_CTR \ + $CONFIG_MODULE_AES + +#### MD5 +bool 'md5' CONFIG_MODULE_MD5 + +dep_bool 'md5 hmac' CONFIG_MODULE_MD5_HMAC \ + $CONFIG_MODULE_MD5 + +#### RC4 +bool 'rc4' CONFIG_MODULE_RC4 + +endmenu # (crypto) + +############################################################################# + + +mainmenu_option next_comment +comment 'Encodings modules' + +comment 'Encoding modules depend on utils module' + +#### BASE 64 +bool 'Base64 encoding (PEM)' CONFIG_MODULE_BASE64 + +#### HAMMING +bool 'Hamming' CONFIG_MODULE_HAMMING + +endmenu # (encodings) + + +############################################################################# + + +mainmenu_option next_comment +comment 'Debug modules' + +comment 'Debug modules depend on utils module' + +#### DIAGNOSTIC +bool 'diagnostic' CONFIG_MODULE_DIAGNOSTIC + +dep_bool ' |-- Create Default diagnostic config' CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG \ + $CONFIG_MODULE_DIAGNOSTIC + +#### ERROR +bool 'error' CONFIG_MODULE_ERROR + +dep_bool ' |-- Create Default error config' CONFIG_MODULE_ERROR_CREATE_CONFIG \ + $CONFIG_MODULE_ERROR + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Programmer options' + +choice 'Programmer' "avrdude CONFIG_AVRDUDE\ + avarice CONFIG_AVARICE +" avrdude + +mainmenu_option next_comment +comment 'Avrdude' + +choice 'Programmer type' "futurlec CONFIG_AVRDUDE_PROG_FUTURELEC\ + abcmini CONFIG_AVRDUDE_PROG_ABCMINI\ + picoweb CONFIG_AVRDUDE_PROG_PICOWEB\ + sp12 CONFIG_AVRDUDE_PROG_SP12\ + alf CONFIG_AVRDUDE_PROG_ALF\ + bascom CONFIG_AVRDUDE_PROG_BASCOM\ + dt006 CONFIG_AVRDUDE_PROG_DT006\ + pony-stk200 CONFIG_AVRDUDE_PROG_PONY_STK200\ + stk200 CONFIG_AVRDUDE_PROG_STK200\ + pavr CONFIG_AVRDUDE_PROG_PAVR\ + butterfly CONFIG_AVRDUDE_PROG_BUTTERFLY\ + avr910 CONFIG_AVRDUDE_PROG_AVR910\ + stk500 CONFIG_AVRDUDE_PROG_STK500\ + avrisp CONFIG_AVRDUDE_PROG_AVRISP\ + bsd CONFIG_AVRDUDE_PROG_BSD\ + dapa CONFIG_AVRDUDE_PROG_DAPA\ + jtag1 CONFIG_AVRDUDE_PROG_JTAG1\ + avr109 CONFIG_AVRDUDE_PROG_AVR109\ +" stk200 + +string 'Port device' CONFIG_AVRDUDE_PORT '/dev/parport0' + +int 'Programmer baudrate' CONFIG_AVRDUDE_BAUDRATE '19200' + +endmenu + +mainmenu_option next_comment +comment 'Avarice' + +string 'Port device' CONFIG_AVARICE_PORT '/dev/ttyS0' + +int 'Debug TCP Port' CONFIG_AVARICE_DEBUG_PORT '1234' + +choice 'Programmer type' "mkI CONFIG_AVARICE_PROG_MKI\ + mkII CONFIG_AVARICE_PROG_MKII +" mkI + +endmenu + +bool 'Check device signature' CONFIG_AVRDUDE_CHECK_SIGNATURE + +endmenu + +############################################################################# diff --git a/config/config.in.~1.42.4.32.~ b/config/config.in.~1.42.4.32.~ new file mode 100644 index 0000000..583b736 --- /dev/null +++ b/config/config.in.~1.42.4.32.~ @@ -0,0 +1,553 @@ +mainmenu_name "Aversive project configuration" + +############################################################################# + +mainmenu_option next_comment +comment 'Hardware' +# name must be CONFIG_MCU_##mcu name## + +choice 'Avr type' "\ + AT90s2313 CONFIG_MCU_AT90S2313 \ + AT90s2323 CONFIG_MCU_AT90S2323 \ + AT90s2333 CONFIG_MCU_AT90S3333 \ + AT90s2343 CONFIG_MCU_AT90S2343 \ + ATtiny22 CONFIG_MCU_ATTINY22 \ + ATtiny26 CONFIG_MCU_ATTINY26 \ + AT90s4414 CONFIG_MCU_AT90S4414 \ + AT90s4433 CONFIG_MCU_AT90S4433 \ + AT90s4434 CONFIG_MCU_AT90S4434 \ + AT90s8515 CONFIG_MCU_AT90S8515 \ + AT90c8534 CONFIG_MCU_AT90S8534 \ + AT90s8535 CONFIG_MCU_AT90S8535 \ + AT86rf401 CONFIG_MCU_AT86RF401 \ + ATmega103 CONFIG_MCU_ATMEGA103 \ + ATmega603 CONFIG_MCU_ATMEGA603 \ + AT43usb320 CONFIG_MCU_AT43USB320 \ + AT43usb355 CONFIG_MCU_AT43USB355 \ + AT76c711 CONFIG_MCU_AT76C711 \ + ATmega8 CONFIG_MCU_ATMEGA8 \ + ATmega48 CONFIG_MCU_ATMEGA48 \ + ATmega88 CONFIG_MCU_ATMEGA88 \ + ATmega8515 CONFIG_MCU_ATMEGA8515 \ + ATmega8535 CONFIG_MCU_ATMEGA8535 \ + ATtiny13 CONFIG_MCU_ATTINY13 \ + ATtiny2313 CONFIG_MCU_ATTINY2313 \ + ATmega16 CONFIG_MCU_ATMEGA16 \ + ATmega161 CONFIG_MCU_ATMEGA161 \ + ATmega162 CONFIG_MCU_ATMEGA162 \ + ATmega163 CONFIG_MCU_ATMEGA163 \ + ATmega165 CONFIG_MCU_ATMEGA165 \ + ATmega168 CONFIG_MCU_ATMEGA168 \ + ATmega169 CONFIG_MCU_ATMEGA169 \ + ATmega32 CONFIG_MCU_ATMEGA32 \ + ATmega323 CONFIG_MCU_ATMEGA323 \ + ATmega325 CONFIG_MCU_ATMEGA325 \ + ATmega3250 CONFIG_MCU_ATMEGA3250 \ + ATmega64 CONFIG_MCU_ATMEGA64 \ + ATmega645 CONFIG_MCU_ATMEGA645 \ + ATmega6450 CONFIG_MCU_ATMEGA6450 \ + ATmega128 CONFIG_MCU_ATMEGA128 \ + ATmega1281 CONFIG_MCU_ATMEGA1281 \ + AT90can128 CONFIG_MCU_AT90CAN128 \ + AT94k CONFIG_MCU_AT94K \ + AT90s1200 CONFIG_MCU_AT90S1200 \ + ATmega2560 CONFIG_MCU_ATMEGA2560 \ + ATmega256 CONFIG_MCU_ATMEGA256 \ +" ATmega128 + +int 'Quartz Frequency (Hz)' CONFIG_QUARTZ '12000000' + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Generation options' + + +choice 'Optimization level' "\ + -O0 CONFIG_OPTM_0 \ + -O1 CONFIG_OPTM_1 \ + -O2 CONFIG_OPTM_2 \ + -O3 CONFIG_OPTM_3 \ + -Os CONFIG_OPTM_S \ +" -Os + +bool 'Include Math lib' CONFIG_MATH_LIB + +bool 'fdevopen compatibility' CONFIG_FDEVOPEN_COMPAT + +# printf version, advanced depends on math lib +if [ "$CONFIG_MATH_LIB" = "y" ]; then + +choice 'Printf capabilities' "\ + none CONFIG_NO_PRINTF \ + minimal CONFIG_MINIMAL_PRINTF \ + standard CONFIG_STANDARD_PRINTF \ + advanced CONFIG_ADVANCED_PRINTF \ +" standard + +else + +choice 'Printf capabilities' "\ + none CONFIG_NO_PRINTF \ + minimal CONFIG_MINIMAL_PRINTF \ + standard CONFIG_STANDARD_PRINTF \ +" standard + +fi + +choice 'Default output format' "\ + ihex CONFIG_FORMAT_IHEX \ + srec CONFIG_FORMAT_SREC \ + binary CONFIG_FORMAT_BINARY \ +" ihex + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Base modules' + +comment 'Enable math library in generation options to see all modules' + +#### CIRCULAR BUFFER +bool 'Circular buffer' CONFIG_MODULE_CIRBUF +dep_bool ' |-- Allow buffer larger than 127' CONFIG_MODULE_CIRBUF_LARGE \ + $CONFIG_MODULE_CIRBUF + + +#### FIXED_POINT +dep_bool 'Fixed_Point lib' CONFIG_MODULE_FIXED_POINT \ + $CONFIG_MATH_LIB + + +#### VECT2 +dep_bool 'Vect2 lib' CONFIG_MODULE_VECT2 \ + $CONFIG_MATH_LIB + +#### GEOMETRY +dep_bool 'Geometry lib' CONFIG_MODULE_GEOMETRY \ + $CONFIG_MATH_LIB + +#### SCHEDULER +bool 'Scheduler' CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- enable debug statistics' CONFIG_MODULE_SCHEDULER_STATS \ + $CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- Create Default scheduler config' CONFIG_MODULE_SCHEDULER_CREATE_CONFIG \ + $CONFIG_MODULE_SCHEDULER + +if [ "$CONFIG_MODULE_TIMER" = "y" ]; then + +choice 'Scheduler config' "use_timer_module CONFIG_MODULE_SCHEDULER_USE_TIMERS\ + use_timer0 CONFIG_MODULE_SCHEDULER_TIMER0\ + manual CONFIG_MODULE_SCHEDULER_MANUAL" use_timer_module + +else + +choice 'Scheduler config' "use_timer_module CONFIG_MODULE_SCHEDULER_USE_TIMERS\ + use_timer0 CONFIG_MODULE_SCHEDULER_TIMER0\ + manual CONFIG_MODULE_SCHEDULER_MANUAL" use_timer0 + +fi + +#### TIME +dep_bool 'Time' CONFIG_MODULE_TIME \ + $CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- Create Default time config' CONFIG_MODULE_TIME_CREATE_CONFIG \ + $CONFIG_MODULE_TIME + +#### TIME_EXT +bool 'Time - reloaded' CONFIG_MODULE_TIME_EXT + +dep_bool ' |-- Create Default time_ext config' CONFIG_MODULE_TIME_EXT_CREATE_CONFIG \ + $CONFIG_MODULE_TIME_EXT + + + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Communication modules' + +comment 'uart needs circular buffer, mf2 client may need scheduler' + +#### UART +dep_bool 'Uart' CONFIG_MODULE_UART \ + $CONFIG_MODULE_CIRBUF + +dep_bool ' |-- Allow 9 bits operations' CONFIG_MODULE_UART_9BITS \ + $CONFIG_MODULE_UART + +dep_bool ' |-- Create Default uart config' CONFIG_MODULE_UART_CREATE_CONFIG \ + $CONFIG_MODULE_UART + +#### SPI +bool 'spi (very EXPERIMENTAL)' CONFIG_MODULE_SPI + +dep_bool ' |-- Create Default spi config' CONFIG_MODULE_SPI_CREATE_CONFIG \ + $CONFIG_MODULE_SPI + +#### I2C +bool 'i2c' CONFIG_MODULE_I2C + +dep_bool ' |-- Allow master mode' CONFIG_MODULE_I2C_MASTER \ + $CONFIG_MODULE_I2C + +dep_bool ' |-- Allow multimaster mode' CONFIG_MODULE_I2C_MULTIMASTER \ + $CONFIG_MODULE_I2C_MASTER + +dep_bool ' |-- Create Default i2c config' CONFIG_MODULE_I2C_CREATE_CONFIG \ + $CONFIG_MODULE_I2C + + +#### MF2_CLIENT +bool 'mf2_client (very EXPERIMENTAL)' CONFIG_MODULE_MF2_CLIENT + +dep_bool ' |-- Use scheduler (watchdog + no active loops)' CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER \ + $CONFIG_MODULE_MF2_CLIENT \ + $CONFIG_MODULE_SCHEDULER + +dep_bool ' |-- Create Default mf2_client config' CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG \ + $CONFIG_MODULE_MF2_CLIENT + +#### MF2_SERVER +bool 'mf2_server (very EXPERIMENTAL)' CONFIG_MODULE_MF2_SERVER + +dep_bool ' |-- Create Default mf2_server config' CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG \ + $CONFIG_MODULE_MF2_SERVER + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Hardware modules' + +#### TIMER +bool 'Timer' CONFIG_MODULE_TIMER + +dep_bool ' |-- Create Default timer config' CONFIG_MODULE_TIMER_CREATE_CONFIG \ + $CONFIG_MODULE_TIMER + +dep_bool ' |-- Allow dynamic modification of prescaler' CONFIG_MODULE_TIMER_DYNAMIC \ + $CONFIG_MODULE_TIMER + + +#### PWM +bool 'PWM' CONFIG_MODULE_PWM + +dep_bool ' |-- Create Default pwm config' CONFIG_MODULE_PWM_CREATE_CONFIG \ + $CONFIG_MODULE_PWM + + +#### PWM_NG +bool 'PWM_ng' CONFIG_MODULE_PWM_NG + +#### ADC +bool 'ADC' CONFIG_MODULE_ADC + +dep_bool ' |-- Create Default adc config' CONFIG_MODULE_ADC_CREATE_CONFIG \ + $CONFIG_MODULE_ADC + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'IHM modules' + +#### menu +bool 'Menu' CONFIG_MODULE_MENU + +#### vt100 +bool 'Vt100' CONFIG_MODULE_VT100 + +#### rdline +dep_bool 'Rdline' CONFIG_MODULE_RDLINE \ + $CONFIG_MODULE_VT100 \ + $CONFIG_MODULE_CIRBUF + +dep_bool ' |-- Create Default rdline config' CONFIG_MODULE_RDLINE_CREATE_CONFIG \ + $CONFIG_MODULE_RDLINE + +dep_bool ' |-- Enable cut/paste' CONFIG_MODULE_RDLINE_KILL_BUF \ + $CONFIG_MODULE_RDLINE + +dep_bool ' |-- Enable history' CONFIG_MODULE_RDLINE_HISTORY \ + $CONFIG_MODULE_RDLINE + +#### parse + +bool 'Parse' CONFIG_MODULE_PARSE +dep_bool ' |-- Do not parse float' CONFIG_MODULE_PARSE_NO_FLOAT \ + $CONFIG_MODULE_PARSE + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'External devices modules' + +#### LCD +bool 'LCD' CONFIG_MODULE_LCD + +dep_bool ' |-- Create Default lcd config' CONFIG_MODULE_LCD_CREATE_CONFIG \ + $CONFIG_MODULE_LCD + +#### SERVO +bool 'Multiservo' CONFIG_MODULE_MULTISERVO + +dep_bool ' |-- Create Default servo config' CONFIG_MODULE_MULTISERVO_CREATE_CONFIG \ + $CONFIG_MODULE_MULTISERVO + +bool 'AX-12' CONFIG_MODULE_AX12 + +dep_bool ' |-- Create Default AX-12 config' CONFIG_MODULE_AX12_CREATE_CONFIG\ + $CONFIG_MODULE_AX12 + +mainmenu_option next_comment +comment 'Brushless motor drivers (you should enable pwm modules to see all)' + +#### CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL +dep_bool '3 phase motor with digital hall sensors' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL \ + $CONFIG_MODULE_PWM + +dep_bool ' |-- Create Default brushless_3phase_digital_hall config' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG \ + $CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL + +#### CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE +dep_bool 'two 3 phase motor with digital hall sensors' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE \ + $CONFIG_MODULE_PWM + +dep_bool ' Create Default brushless_3phase_digital_hall_double config' CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG \ + $CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE + +endmenu # (brushless) + +mainmenu_option next_comment +comment 'Encoders (you need comm/spi for encoders_spi)' + +#### ENCODERS +bool 'Encoders (microb)' CONFIG_MODULE_ENCODERS_MICROB + +dep_bool ' |-- Create Default encoders_microb config' CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG \ + $CONFIG_MODULE_ENCODERS_MICROB + +#### ENCODERS +bool 'Encoders (eirbot)' CONFIG_MODULE_ENCODERS_EIRBOT + +dep_bool ' |-- Create Default encoders_eirbot config' CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG \ + $CONFIG_MODULE_ENCODERS_EIRBOT + +#### ENCODERS +dep_bool 'Encoders_spi (microb)' CONFIG_MODULE_ENCODERS_SPI \ + $CONFIG_MODULE_SPI + +dep_bool ' |-- Create Default encoders_spi config' CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG \ + $CONFIG_MODULE_ENCODERS_SPI + +endmenu # (encoders) + +mainmenu_option next_comment +comment 'Robot specific modules' + +#### ROBOT_SYSTEM +dep_bool 'Robot System' CONFIG_MODULE_ROBOT_SYSTEM \ + $CONFIG_MODULE_FIXED_POINT + +dep_bool ' |-- Allow motor and external encoders' CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT \ + $CONFIG_MODULE_ROBOT_SYSTEM + +#### POSITION_MANAGER +dep_bool 'Position manager' CONFIG_MODULE_POSITION_MANAGER \ + $CONFIG_MODULE_ROBOT_SYSTEM + +dep_bool ' |-- Compensate centrifugal force' CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE \ + $CONFIG_MODULE_POSITION_MANAGER + +#### TRAJECTORY MANAGER +dep_bool 'Trajectory manager' CONFIG_MODULE_TRAJECTORY_MANAGER \ + $CONFIG_MODULE_POSITION_MANAGER \ + $CONFIG_MODULE_SCHEDULER \ + $CONFIG_MODULE_VECT2 \ + $CONFIG_MODULE_FIXED_POINT + +#### BLOCKING DETECTION MANAGER +bool 'Blocking detection manager' CONFIG_MODULE_BLOCKING_DETECTION_MANAGER + +#### OBSTACLE AVOIDANCE +dep_bool 'Obstacle Avoidance' CONFIG_MODULE_OBSTACLE_AVOIDANCE\ + $CONFIG_MODULE_GEOMETRY + +dep_bool ' |-- Create Default Obstacle Avoidance config' CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG \ + $CONFIG_MODULE_OBSTACLE_AVOIDANCE + +endmenu # (robot) + +mainmenu_option next_comment +comment 'Control system modules' + +#### CONTROL SYSTEM MANAGER +bool 'Control System Manager' CONFIG_MODULE_CONTROL_SYSTEM_MANAGER + +comment 'Filters' + +bool 'PID' CONFIG_MODULE_PID + +dep_bool ' |-- Create Default PID config' CONFIG_MODULE_PID_CREATE_CONFIG \ + $CONFIG_MODULE_PID + +bool 'ramp' CONFIG_MODULE_RAMP + +bool 'Quadramp' CONFIG_MODULE_QUADRAMP + +bool 'Quadramp derivate' CONFIG_MODULE_QUADRAMP_DERIVATE + +bool 'Biquad' CONFIG_MODULE_BIQUAD + +endmenu # (control system) + + +mainmenu_option next_comment +comment 'Radio devices' +comment 'Some radio devices require SPI to be activated' +#### RADIO DEVICES +dep_bool 'CC2420 Radio Device (IEEE 802.15.4) (VERY EXPERIMENTAL)' CONFIG_MODULE_CC2420 \ + $CONFIG_MODULE_SPI + +dep_bool ' |-- Create Default CC2420 config' CONFIG_MODULE_CC2420_CREATE_CONFIG \ + $CONFIG_MODULE_CC2420 + +endmenu # radio + + +endmenu # (devices) + +############################################################################# + + +mainmenu_option next_comment +comment 'Crypto modules' + +comment 'Crypto modules depend on utils module' + +#### AES +bool 'aes' CONFIG_MODULE_AES + +dep_bool 'aes counter mode' CONFIG_MODULE_AES_CTR \ + $CONFIG_MODULE_AES + +#### MD5 +bool 'md5' CONFIG_MODULE_MD5 + +dep_bool 'md5 hmac' CONFIG_MODULE_MD5_HMAC \ + $CONFIG_MODULE_MD5 + +#### RC4 +bool 'rc4' CONFIG_MODULE_RC4 + +endmenu # (crypto) + +############################################################################# + + +mainmenu_option next_comment +comment 'Encodings modules' + +comment 'Encoding modules depend on utils module' + +#### BASE 64 +bool 'Base64 encoding (PEM)' CONFIG_MODULE_BASE64 + +#### HAMMING +bool 'Hamming' CONFIG_MODULE_HAMMING + +endmenu # (encodings) + + +############################################################################# + + +mainmenu_option next_comment +comment 'Debug modules' + +comment 'Debug modules depend on utils module' + +#### DIAGNOSTIC +bool 'diagnostic' CONFIG_MODULE_DIAGNOSTIC + +dep_bool ' |-- Create Default diagnostic config' CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG \ + $CONFIG_MODULE_DIAGNOSTIC + +#### ERROR +bool 'error' CONFIG_MODULE_ERROR + +dep_bool ' |-- Create Default error config' CONFIG_MODULE_ERROR_CREATE_CONFIG \ + $CONFIG_MODULE_ERROR + +endmenu + +############################################################################# + +mainmenu_option next_comment +comment 'Programmer options' + +choice 'Programmer' "avrdude CONFIG_AVRDUDE\ + avarice CONFIG_AVARICE +" avrdude + +mainmenu_option next_comment +comment 'Avrdude' + +choice 'Programmer type' "futurlec CONFIG_AVRDUDE_PROG_FUTURELEC\ + abcmini CONFIG_AVRDUDE_PROG_ABCMINI\ + picoweb CONFIG_AVRDUDE_PROG_PICOWEB\ + sp12 CONFIG_AVRDUDE_PROG_SP12\ + alf CONFIG_AVRDUDE_PROG_ALF\ + bascom CONFIG_AVRDUDE_PROG_BASCOM\ + dt006 CONFIG_AVRDUDE_PROG_DT006\ + pony-stk200 CONFIG_AVRDUDE_PROG_PONY_STK200\ + stk200 CONFIG_AVRDUDE_PROG_STK200\ + pavr CONFIG_AVRDUDE_PROG_PAVR\ + butterfly CONFIG_AVRDUDE_PROG_BUTTERFLY\ + avr910 CONFIG_AVRDUDE_PROG_AVR910\ + stk500 CONFIG_AVRDUDE_PROG_STK500\ + avrisp CONFIG_AVRDUDE_PROG_AVRISP\ + bsd CONFIG_AVRDUDE_PROG_BSD\ + dapa CONFIG_AVRDUDE_PROG_DAPA\ + jtag1 CONFIG_AVRDUDE_PROG_JTAG1\ + avr109 CONFIG_AVRDUDE_PROG_AVR109\ +" stk200 + +string 'Port device' CONFIG_AVRDUDE_PORT '/dev/parport0' + +int 'Programmer baudrate' CONFIG_AVRDUDE_BAUDRATE '19200' + +endmenu + +mainmenu_option next_comment +comment 'Avarice' + +string 'Port device' CONFIG_AVARICE_PORT '/dev/ttyS0' + +int 'Debug TCP Port' CONFIG_AVARICE_DEBUG_PORT '1234' + +choice 'Programmer type' "mkI CONFIG_AVARICE_PROG_MKI\ + mkII CONFIG_AVARICE_PROG_MKII +" mkI + +endmenu + +bool 'Check device signature' CONFIG_AVRDUDE_CHECK_SIGNATURE + +endmenu + +############################################################################# diff --git a/config/fuses_defs/CVS/Entries b/config/fuses_defs/CVS/Entries new file mode 100644 index 0000000..4937361 --- /dev/null +++ b/config/fuses_defs/CVS/Entries @@ -0,0 +1,54 @@ +/at90can128/1.2.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90pwm2/1.2.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90pwm3/1.2.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s1200/1.2.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s2313/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s2323/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s2343/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s4414/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s4433/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s4434/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s8515/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/at90s8535/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega103/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega128/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega16/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega161/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega162/1.3.4.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega163/1.2.8.1/Sun Nov 26 21:05:59 2006//Tb_zer0 +/atmega165/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega168/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega169/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega2560/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega2561/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega32/1.3.4.2/Thu Sep 6 08:11:05 2007//Tb_zer0 +/atmega323/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega325/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega3250/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega329/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega3290/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega406/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega48/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega64/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega644/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega645/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega6450/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega649/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega6490/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega8/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega8515/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega8535/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/atmega88/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny11/1.2.8.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny12/1.2.8.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny13/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny15/1.2.8.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny22/1.2.8.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny2313/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny24/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny25/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny26/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny28/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny45/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/attiny85/1.2.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +D diff --git a/config/fuses_defs/CVS/Repository b/config/fuses_defs/CVS/Repository new file mode 100644 index 0000000..1e65499 --- /dev/null +++ b/config/fuses_defs/CVS/Repository @@ -0,0 +1 @@ +aversive/config/fuses_defs diff --git a/config/fuses_defs/CVS/Root b/config/fuses_defs/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/config/fuses_defs/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/config/fuses_defs/CVS/Tag b/config/fuses_defs/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/config/fuses_defs/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/config/fuses_defs/CVS/Template b/config/fuses_defs/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/at90can128 b/config/fuses_defs/at90can128 new file mode 100644 index 0000000..7b80297 --- /dev/null +++ b/config/fuses_defs/at90can128 @@ -0,0 +1,20 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator output option +2 5 lfuse SUT1 1 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 3 efuse BODLEVEL2 1 Brown out detector trigger level +17 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +19 0 efuse TA0SEL 1 (Reserved to factory tests) diff --git a/config/fuses_defs/at90pwm2 b/config/fuses_defs/at90pwm2 new file mode 100644 index 0000000..bd28762 --- /dev/null +++ b/config/fuses_defs/at90pwm2 @@ -0,0 +1,20 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator output option +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 3 efuse BODLEVEL2 1 Brown out detector trigger level +17 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +19 0 efuse TA0SEL 1 (Reserved to factory tests) diff --git a/config/fuses_defs/at90pwm3 b/config/fuses_defs/at90pwm3 new file mode 100644 index 0000000..bd28762 --- /dev/null +++ b/config/fuses_defs/at90pwm3 @@ -0,0 +1,20 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator output option +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 3 efuse BODLEVEL2 1 Brown out detector trigger level +17 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +19 0 efuse TA0SEL 1 (Reserved to factory tests) diff --git a/config/fuses_defs/at90s1200 b/config/fuses_defs/at90s1200 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/at90s2313 b/config/fuses_defs/at90s2313 new file mode 100644 index 0000000..4be8454 --- /dev/null +++ b/config/fuses_defs/at90s2313 @@ -0,0 +1,2 @@ +0 5 fuse SPIEN 0 Serial Program Downloading Enabled +1 0 fuse FSTRT 1 Short Start-up time selected diff --git a/config/fuses_defs/at90s2323 b/config/fuses_defs/at90s2323 new file mode 100644 index 0000000..c4aefa7 --- /dev/null +++ b/config/fuses_defs/at90s2323 @@ -0,0 +1 @@ +0 5 fuse SPIEN 0 Serial Program Downloading Enabled diff --git a/config/fuses_defs/at90s2343 b/config/fuses_defs/at90s2343 new file mode 100644 index 0000000..5c6c558 --- /dev/null +++ b/config/fuses_defs/at90s2343 @@ -0,0 +1,2 @@ +0 5 fuse SPIEN 0 Serial Program Downloading Enabled +1 0 fuse FSTRT 1 Short Start-up time selected (default value is for AT90S2343-10) diff --git a/config/fuses_defs/at90s4414 b/config/fuses_defs/at90s4414 new file mode 100644 index 0000000..9661077 --- /dev/null +++ b/config/fuses_defs/at90s4414 @@ -0,0 +1,2 @@ +0 1 lfuse SPIEN Serial Program Downloading Enabled +1 2 lfuse FSTRT Short Start-up time selected diff --git a/config/fuses_defs/at90s4433 b/config/fuses_defs/at90s4433 new file mode 100644 index 0000000..bde27f2 --- /dev/null +++ b/config/fuses_defs/at90s4433 @@ -0,0 +1,6 @@ +0 5 fuse SPIEN 0 Enable Serial programming and Data Downloading (ignored) +1 7 fuse BODLEVEL 1 Brown out detector trigger level +2 6 fuse BODEN 1 Brown out detector enable +3 2 fuse CKSEL2 0 Select Clock Source +4 1 fuse CKSEL1 1 Select Clock Source +5 0 fuse CKSEL0 0 Select Clock Source diff --git a/config/fuses_defs/at90s4434 b/config/fuses_defs/at90s4434 new file mode 100644 index 0000000..9661077 --- /dev/null +++ b/config/fuses_defs/at90s4434 @@ -0,0 +1,2 @@ +0 1 lfuse SPIEN Serial Program Downloading Enabled +1 2 lfuse FSTRT Short Start-up time selected diff --git a/config/fuses_defs/at90s8515 b/config/fuses_defs/at90s8515 new file mode 100644 index 0000000..4be8454 --- /dev/null +++ b/config/fuses_defs/at90s8515 @@ -0,0 +1,2 @@ +0 5 fuse SPIEN 0 Serial Program Downloading Enabled +1 0 fuse FSTRT 1 Short Start-up time selected diff --git a/config/fuses_defs/at90s8535 b/config/fuses_defs/at90s8535 new file mode 100644 index 0000000..4be8454 --- /dev/null +++ b/config/fuses_defs/at90s8535 @@ -0,0 +1,2 @@ +0 5 fuse SPIEN 0 Serial Program Downloading Enabled +1 0 fuse FSTRT 1 Short Start-up time selected diff --git a/config/fuses_defs/atmega103 b/config/fuses_defs/atmega103 new file mode 100644 index 0000000..020ab1b --- /dev/null +++ b/config/fuses_defs/atmega103 @@ -0,0 +1,8 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source diff --git a/config/fuses_defs/atmega128 b/config/fuses_defs/atmega128 new file mode 100644 index 0000000..e4c396a --- /dev/null +++ b/config/fuses_defs/atmega128 @@ -0,0 +1,18 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator Options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 1 efuse M103C 0 ATmega103 compatibility mode +17 0 efuse WDTON 1 Watchdog timer always on diff --git a/config/fuses_defs/atmega16 b/config/fuses_defs/atmega16 new file mode 100644 index 0000000..937ac09 --- /dev/null +++ b/config/fuses_defs/atmega16 @@ -0,0 +1,16 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator Options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector diff --git a/config/fuses_defs/atmega161 b/config/fuses_defs/atmega161 new file mode 100644 index 0000000..c7d13b6 --- /dev/null +++ b/config/fuses_defs/atmega161 @@ -0,0 +1,6 @@ +0 5 lfuse BOOTRST 1 Boot Reset Vector Enabled +1 4 lfuse SPIEN 0 Serial program downloading (SPI) enabled +2 3 lfuse SUT 1 Start-up time +3 2 lfuse CKSEL2 0 Select Clock Source +4 1 lfuse CKSEL1 1 Select Clock Source +5 0 lfuse CKSEL0 0 Select Clock Source diff --git a/config/fuses_defs/atmega162 b/config/fuses_defs/atmega162 new file mode 100644 index 0000000..36f29bc --- /dev/null +++ b/config/fuses_defs/atmega162 @@ -0,0 +1,20 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 4 efuse M161C 1 ATMega 161 compatibility mode +17 3 efuse BODLEVEL2 1 Brown out detector trigger level +18 2 efuse BODLEVEL1 1 Brown out detector trigger level +19 1 efuse BODLEVEL0 1 Brown out detector trigger level diff --git a/config/fuses_defs/atmega163 b/config/fuses_defs/atmega163 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/atmega165 b/config/fuses_defs/atmega165 new file mode 100644 index 0000000..ef2a252 --- /dev/null +++ b/config/fuses_defs/atmega165 @@ -0,0 +1,20 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 3 efuse BODLEVEL2 1 Brown out detector trigger level +17 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +19 0 efuse RESERVED 1 Reserved for future use diff --git a/config/fuses_defs/atmega168 b/config/fuses_defs/atmega168 new file mode 100644 index 0000000..bd00801 --- /dev/null +++ b/config/fuses_defs/atmega168 @@ -0,0 +1,19 @@ +0 7 lfuse CKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 1 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse RSTDISBL 1 External reset disable +9 6 hfuse DWEN 1 debugWIRE Enable +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog Timer Always On +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +14 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +15 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +16 2 efuse BOOTSZ1 0 Select boot size +17 1 efuse BOOTSZ0 0 Select boot size +18 0 efuse BOOTRST 1 Select reset vector diff --git a/config/fuses_defs/atmega169 b/config/fuses_defs/atmega169 new file mode 100644 index 0000000..ef2a252 --- /dev/null +++ b/config/fuses_defs/atmega169 @@ -0,0 +1,20 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 3 efuse BODLEVEL2 1 Brown out detector trigger level +17 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +19 0 efuse RESERVED 1 Reserved for future use diff --git a/config/fuses_defs/atmega2560 b/config/fuses_defs/atmega2560 new file mode 100644 index 0000000..c389033 --- /dev/null +++ b/config/fuses_defs/atmega2560 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL2 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 0 efuse BODLEVEL0 1 Brown-out Detector trigger level diff --git a/config/fuses_defs/atmega2561 b/config/fuses_defs/atmega2561 new file mode 100644 index 0000000..c389033 --- /dev/null +++ b/config/fuses_defs/atmega2561 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL2 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 0 efuse BODLEVEL0 1 Brown-out Detector trigger level diff --git a/config/fuses_defs/atmega32 b/config/fuses_defs/atmega32 new file mode 100644 index 0000000..c83ac23 --- /dev/null +++ b/config/fuses_defs/atmega32 @@ -0,0 +1,16 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector diff --git a/config/fuses_defs/atmega323 b/config/fuses_defs/atmega323 new file mode 100644 index 0000000..1c4bd7a --- /dev/null +++ b/config/fuses_defs/atmega323 @@ -0,0 +1,13 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 3 lfuse CKSEL3 0 Select Clock Source +3 2 lfuse CKSEL2 0 Select Clock Source +4 1 lfuse CKSEL1 0 Select Clock Source +5 0 lfuse CKSEL0 1 Select Clock Source +6 7 hfuse OCDEN 1 Enable OCD +7 6 hfuse JTAGEN 0 Enable JTAG +8 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +9 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +10 2 hfuse BOOTSZ1 0 Select Boot Size +11 1 hfuse BOOTSZ0 0 Select Boot Size +12 0 hfuse BOOTRST 1 Select Reset Vector diff --git a/config/fuses_defs/atmega325 b/config/fuses_defs/atmega325 new file mode 100644 index 0000000..1ace0e7 --- /dev/null +++ b/config/fuses_defs/atmega325 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RSTDISBL 1 External Reset Disable diff --git a/config/fuses_defs/atmega3250 b/config/fuses_defs/atmega3250 new file mode 100644 index 0000000..1ace0e7 --- /dev/null +++ b/config/fuses_defs/atmega3250 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RSTDISBL 1 External Reset Disable diff --git a/config/fuses_defs/atmega329 b/config/fuses_defs/atmega329 new file mode 100644 index 0000000..1ace0e7 --- /dev/null +++ b/config/fuses_defs/atmega329 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RSTDISBL 1 External Reset Disable diff --git a/config/fuses_defs/atmega3290 b/config/fuses_defs/atmega3290 new file mode 100644 index 0000000..1ace0e7 --- /dev/null +++ b/config/fuses_defs/atmega3290 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RSTDISBL 1 External Reset Disable diff --git a/config/fuses_defs/atmega406 b/config/fuses_defs/atmega406 new file mode 100644 index 0000000..fc116f9 --- /dev/null +++ b/config/fuses_defs/atmega406 @@ -0,0 +1,9 @@ +0 7 lfuse WDTON 1 Watchdog Timer Always On +1 6 lfuse EESAVE 1 EEPROM memory is preserved through chip erase +2 5 lfuse BOOTSZ1 0 Select boot size +3 4 lfuse BOOTSZ0 0 Select boot size +4 3 lfuse BOOTRST 1 Select reset vector +5 2 lfuse SUT1 1 Select start-up time +6 1 lfuse SUT0 0 Select start-up time +7 1 hfuse OCDEN 1 Enable OCD +8 0 hfuse JTAGEN 0 Enable JTAG diff --git a/config/fuses_defs/atmega48 b/config/fuses_defs/atmega48 new file mode 100644 index 0000000..db4a34c --- /dev/null +++ b/config/fuses_defs/atmega48 @@ -0,0 +1,17 @@ +0 7 lfuse CKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 1 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse RSTDISBL 1 External reset disable +9 6 hfuse DWEN 1 debugWIRE Enable +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog Timer Always On +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +14 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +15 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +16 0 efuse SELFPRGEN 1 Self Programming Enable diff --git a/config/fuses_defs/atmega64 b/config/fuses_defs/atmega64 new file mode 100644 index 0000000..2a4cc38 --- /dev/null +++ b/config/fuses_defs/atmega64 @@ -0,0 +1,18 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator Options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 1 efuse CompMode 1 Compabillity mode +17 0 efuse WDTON 1 Watchdog timer always on diff --git a/config/fuses_defs/atmega644 b/config/fuses_defs/atmega644 new file mode 100644 index 0000000..c389033 --- /dev/null +++ b/config/fuses_defs/atmega644 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL2 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL1 1 Brown-out Detector trigger level +18 0 efuse BODLEVEL0 1 Brown-out Detector trigger level diff --git a/config/fuses_defs/atmega645 b/config/fuses_defs/atmega645 new file mode 100644 index 0000000..1ace0e7 --- /dev/null +++ b/config/fuses_defs/atmega645 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RSTDISBL 1 External Reset Disable diff --git a/config/fuses_defs/atmega6450 b/config/fuses_defs/atmega6450 new file mode 100644 index 0000000..1ace0e7 --- /dev/null +++ b/config/fuses_defs/atmega6450 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RSTDISBL 1 External Reset Disable diff --git a/config/fuses_defs/atmega649 b/config/fuses_defs/atmega649 new file mode 100644 index 0000000..8d3de21 --- /dev/null +++ b/config/fuses_defs/atmega649 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RESERVED 1 Reserved fuse bit, do not program diff --git a/config/fuses_defs/atmega6490 b/config/fuses_defs/atmega6490 new file mode 100644 index 0000000..8d3de21 --- /dev/null +++ b/config/fuses_defs/atmega6490 @@ -0,0 +1,19 @@ +0 7 lfuse CLKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Oscillator options +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse OCDEN 1 Enable OCD +9 6 hfuse JTAGEN 0 Enable JTAG +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog timer always on +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector +16 2 efuse BODLEVEL1 1 Brown-out Detector trigger level +17 1 efuse BODLEVEL0 1 Brown-out Detector trigger level +18 0 efuse RESERVED 1 Reserved fuse bit, do not program diff --git a/config/fuses_defs/atmega8 b/config/fuses_defs/atmega8 new file mode 100644 index 0000000..7abc694 --- /dev/null +++ b/config/fuses_defs/atmega8 @@ -0,0 +1,16 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse RSTDISBL 1 Disable reset +9 6 hfuse WTDON 0 Enable watchdog +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator Options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector diff --git a/config/fuses_defs/atmega8515 b/config/fuses_defs/atmega8515 new file mode 100644 index 0000000..896aaf8 --- /dev/null +++ b/config/fuses_defs/atmega8515 @@ -0,0 +1,16 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse S8515C 1 AT90S4414/8515 compabillity mode +9 6 hfuse WDTON 1 Watchdog timer always on +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator Options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector diff --git a/config/fuses_defs/atmega8535 b/config/fuses_defs/atmega8535 new file mode 100644 index 0000000..6858b1e --- /dev/null +++ b/config/fuses_defs/atmega8535 @@ -0,0 +1,16 @@ +0 7 lfuse BODLEVEL 1 Brown out detector trigger level +1 6 lfuse BODEN 1 Brown out detector enable +2 5 lfuse SUT1 0 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 7 hfuse S8535C 1 AT90S4434/8535 compabillity mode +9 6 hfuse WDTON 1 Watchdog timer always on +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse CKOPT 1 Oscillator Options +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BOOTSZ1 0 Select Boot Size +14 1 hfuse BOOTSZ0 0 Select Boot Size +15 0 hfuse BOOTRST 1 Select Reset Vector diff --git a/config/fuses_defs/atmega88 b/config/fuses_defs/atmega88 new file mode 100644 index 0000000..bd00801 --- /dev/null +++ b/config/fuses_defs/atmega88 @@ -0,0 +1,19 @@ +0 7 lfuse CKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 1 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse RSTDISBL 1 External reset disable +9 6 hfuse DWEN 1 debugWIRE Enable +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog Timer Always On +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +14 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +15 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +16 2 efuse BOOTSZ1 0 Select boot size +17 1 efuse BOOTSZ0 0 Select boot size +18 0 efuse BOOTRST 1 Select reset vector diff --git a/config/fuses_defs/attiny11 b/config/fuses_defs/attiny11 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/attiny12 b/config/fuses_defs/attiny12 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/attiny13 b/config/fuses_defs/attiny13 new file mode 100644 index 0000000..be81d46 --- /dev/null +++ b/config/fuses_defs/attiny13 @@ -0,0 +1,13 @@ +0 7 lfuse SPIEN 0 SPI programming enable +1 6 lfuse EESAVE 1 Keep EEprom contents during chip erase +2 5 lfuse WDTON 1 Watch dog timer always on +3 4 lfuse CKDIV8 0 Start up with system clock divided by 8 +4 3 lfuse SUT1 1 Select start-up time +5 2 lfuse SUT0 0 Select start-up time +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 4 hfuse SELFPRGEN 1 Self Programming Enable +9 3 hfuse DWEN 1 DebugWire Enable +10 2 hfuse BODLEVEL1 1 Enable BOD and select level +11 1 hfuse BODLEVEL0 1 Enable BOD and select level +12 0 hfuse RSTDISBL 1 Disable external reset diff --git a/config/fuses_defs/attiny15 b/config/fuses_defs/attiny15 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/attiny22 b/config/fuses_defs/attiny22 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/attiny2313 b/config/fuses_defs/attiny2313 new file mode 100644 index 0000000..db4a34c --- /dev/null +++ b/config/fuses_defs/attiny2313 @@ -0,0 +1,17 @@ +0 7 lfuse CKDIV8 0 Divide clock by 8 +1 6 lfuse CKOUT 1 Clock output +2 5 lfuse SUT1 1 Select start-up time +3 4 lfuse SUT0 0 Select start-up time +4 3 lfuse CKSEL3 0 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 1 Select Clock Source +7 0 lfuse CKSEL0 0 Select Clock Source +8 7 hfuse RSTDISBL 1 External reset disable +9 6 hfuse DWEN 1 debugWIRE Enable +10 5 hfuse SPIEN 0 Enable Serial programming and Data Downloading +11 4 hfuse WDTON 1 Watchdog Timer Always On +12 3 hfuse EESAVE 1 EEPROM memory is preserved through chip erase +13 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +14 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +15 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +16 0 efuse SELFPRGEN 1 Self Programming Enable diff --git a/config/fuses_defs/attiny24 b/config/fuses_defs/attiny24 new file mode 100644 index 0000000..8747aa3 --- /dev/null +++ b/config/fuses_defs/attiny24 @@ -0,0 +1,17 @@ +0 0 lfuse CKSEL0 0 Select Clock source +1 1 lfuse CKSEL1 1 Select Clock source +2 2 lfuse CKSEL2 0 Select Clock source +3 3 lfuse CKSEL3 1 Select Clock source +4 4 lfuse SUT0 0 Select start-up time +5 5 lfuse SUT1 1 Select start-up time +6 6 lfuse CKOUT 1 Clock Output Enable +7 7 lfuse CKDIV8 0 Divide clock by 8 +8 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +9 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +10 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +11 3 hfuse EESAVE 1 EEPROM memory is preserved through the Chip Erase +12 4 hfuse WDTON 1 Watchdog Timer always on +13 5 hfuse SPIEN 0 Enable Serial Program and Data Downloading +14 6 hfuse DWEN 1 DebugWIRE Enable +15 7 hfuse RSTDISBL 1 External Reset disable +16 0 efuse SELFPRGEN 1 Self-Programming Enable diff --git a/config/fuses_defs/attiny25 b/config/fuses_defs/attiny25 new file mode 100644 index 0000000..8747aa3 --- /dev/null +++ b/config/fuses_defs/attiny25 @@ -0,0 +1,17 @@ +0 0 lfuse CKSEL0 0 Select Clock source +1 1 lfuse CKSEL1 1 Select Clock source +2 2 lfuse CKSEL2 0 Select Clock source +3 3 lfuse CKSEL3 1 Select Clock source +4 4 lfuse SUT0 0 Select start-up time +5 5 lfuse SUT1 1 Select start-up time +6 6 lfuse CKOUT 1 Clock Output Enable +7 7 lfuse CKDIV8 0 Divide clock by 8 +8 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +9 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +10 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +11 3 hfuse EESAVE 1 EEPROM memory is preserved through the Chip Erase +12 4 hfuse WDTON 1 Watchdog Timer always on +13 5 hfuse SPIEN 0 Enable Serial Program and Data Downloading +14 6 hfuse DWEN 1 DebugWIRE Enable +15 7 hfuse RSTDISBL 1 External Reset disable +16 0 efuse SELFPRGEN 1 Self-Programming Enable diff --git a/config/fuses_defs/attiny26 b/config/fuses_defs/attiny26 new file mode 100644 index 0000000..0adce1c --- /dev/null +++ b/config/fuses_defs/attiny26 @@ -0,0 +1,13 @@ +0 7 lfuse PLLCK 1 Use PLL for internal clock +1 6 lfuse CKOPT 1 Oscillator options +2 5 lfuse SUT1 1 Select start-up time +3 4 lfuse SUT0 1 Select start-up time +4 3 lfuse CKSEL3 1 Select Clock Source +5 2 lfuse CKSEL2 0 Select Clock Source +6 1 lfuse CKSEL1 0 Select Clock Source +7 0 lfuse CKSEL0 1 Select Clock Source +8 4 hfuse RSTDISBL 1 Select if PB/ is I/O pin or RESET pin +9 3 hfuse SPIEN 0 Enable Serial Program and Data Downloading +10 2 hfuse EESAVE 1 EEPROM memory is preserved through the Chip Erase +11 1 hfuse BODLEVEL 1 Brown out detector trigger level +12 0 hfuse BODEN 1 Brown out detector enable diff --git a/config/fuses_defs/attiny28 b/config/fuses_defs/attiny28 new file mode 100644 index 0000000..e69de29 diff --git a/config/fuses_defs/attiny45 b/config/fuses_defs/attiny45 new file mode 100644 index 0000000..8747aa3 --- /dev/null +++ b/config/fuses_defs/attiny45 @@ -0,0 +1,17 @@ +0 0 lfuse CKSEL0 0 Select Clock source +1 1 lfuse CKSEL1 1 Select Clock source +2 2 lfuse CKSEL2 0 Select Clock source +3 3 lfuse CKSEL3 1 Select Clock source +4 4 lfuse SUT0 0 Select start-up time +5 5 lfuse SUT1 1 Select start-up time +6 6 lfuse CKOUT 1 Clock Output Enable +7 7 lfuse CKDIV8 0 Divide clock by 8 +8 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +9 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +10 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +11 3 hfuse EESAVE 1 EEPROM memory is preserved through the Chip Erase +12 4 hfuse WDTON 1 Watchdog Timer always on +13 5 hfuse SPIEN 0 Enable Serial Program and Data Downloading +14 6 hfuse DWEN 1 DebugWIRE Enable +15 7 hfuse RSTDISBL 1 External Reset disable +16 0 efuse SELFPRGEN 1 Self-Programming Enable diff --git a/config/fuses_defs/attiny85 b/config/fuses_defs/attiny85 new file mode 100644 index 0000000..8747aa3 --- /dev/null +++ b/config/fuses_defs/attiny85 @@ -0,0 +1,17 @@ +0 0 lfuse CKSEL0 0 Select Clock source +1 1 lfuse CKSEL1 1 Select Clock source +2 2 lfuse CKSEL2 0 Select Clock source +3 3 lfuse CKSEL3 1 Select Clock source +4 4 lfuse SUT0 0 Select start-up time +5 5 lfuse SUT1 1 Select start-up time +6 6 lfuse CKOUT 1 Clock Output Enable +7 7 lfuse CKDIV8 0 Divide clock by 8 +8 0 hfuse BODLEVEL0 1 Brown-out Detector trigger level +9 1 hfuse BODLEVEL1 1 Brown-out Detector trigger level +10 2 hfuse BODLEVEL2 1 Brown-out Detector trigger level +11 3 hfuse EESAVE 1 EEPROM memory is preserved through the Chip Erase +12 4 hfuse WDTON 1 Watchdog Timer always on +13 5 hfuse SPIEN 0 Enable Serial Program and Data Downloading +14 6 hfuse DWEN 1 DebugWIRE Enable +15 7 hfuse RSTDISBL 1 External Reset disable +16 0 efuse SELFPRGEN 1 Self-Programming Enable diff --git a/config/gen_headers/CVS/Entries b/config/gen_headers/CVS/Entries new file mode 100644 index 0000000..ea4d003 --- /dev/null +++ b/config/gen_headers/CVS/Entries @@ -0,0 +1,8 @@ +/README/1.1.2.2/Mon Jan 15 20:14:56 2007//Tb_zer0 +/all.sh/1.1.2.5/Fri Jan 23 22:53:08 2009//Tb_zer0 +/convert_to_txt.sh/1.1.2.1/Thu Nov 30 21:52:42 2006//Tb_zer0 +/gen_regs.py/1.1.2.6/Fri Jan 23 22:53:08 2009//Tb_zer0 +/get_docs.sh/1.1.2.1/Thu Nov 30 21:52:42 2006//Tb_zer0 +/make_links.sh/1.1.2.1/Thu Nov 30 21:52:42 2006//Tb_zer0 +/parse_doc.py/1.1.2.1/Thu Nov 30 21:52:42 2006//Tb_zer0 +D diff --git a/config/gen_headers/CVS/Repository b/config/gen_headers/CVS/Repository new file mode 100644 index 0000000..a2ade1a --- /dev/null +++ b/config/gen_headers/CVS/Repository @@ -0,0 +1 @@ +aversive/config/gen_headers diff --git a/config/gen_headers/CVS/Root b/config/gen_headers/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/config/gen_headers/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/config/gen_headers/CVS/Tag b/config/gen_headers/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/config/gen_headers/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/config/gen_headers/CVS/Template b/config/gen_headers/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/config/gen_headers/README b/config/gen_headers/README new file mode 100644 index 0000000..6feab97 --- /dev/null +++ b/config/gen_headers/README @@ -0,0 +1,7 @@ +These scripts are used to generate aversive_ATxxxxx in aversive/include +directory. If you feel strong enough to try them... ok ;) But keep +in mind that's they are quick'n'dirty scripts, and not written to work +on every machine. They make some assemptions about the atmel website +for documentation downloading... so they could fail tomorrow. + +The script expects an 'xml' dir. diff --git a/config/gen_headers/all.sh b/config/gen_headers/all.sh new file mode 100755 index 0000000..2a17f14 --- /dev/null +++ b/config/gen_headers/all.sh @@ -0,0 +1,71 @@ +#!/bin/sh + +HDR_DIR=headers +XML_DIR=xml + +mkdir -p ${HDR_DIR} +mkdir -p ${XML_DIR} + +echo "-- generating header files --" + +rm -rf ${HDR_DIR} +mkdir -p ${HDR_DIR}/aversive/parts + +cd ${XML_DIR} +for i in *.xml ; do + echo $i + ../gen_regs.py $i > ../${HDR_DIR}/aversive/parts/${i%.xml}.h +done +cd - + +cd ${HDR_DIR}/aversive/parts + +EL= +cat < ../parts.h +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + +#ifndef _AVERSIVE_PARTS_H_ +#define _AVERSIVE_PARTS_H_ + +EOF + +for i in *.h ; do + part=${i%.h} + part=${part#aversive_} + if [ "$part" = "parts" ]; then + continue + fi + echo "#${EL}if defined (__AVR_${part}__)" >> ../parts.h + echo "#include " >> ../parts.h + EL=el +done +echo "#else" >> ../parts.h +echo "#error \"This arch is not implemented yet\"" >> ../parts.h +echo "#endif" >> ../parts.h +echo >> ../parts.h +echo "#endif /* _AVERSIVE_PARTS_H_ */" >> ../parts.h +cd - + diff --git a/config/gen_headers/convert_to_txt.sh b/config/gen_headers/convert_to_txt.sh new file mode 100755 index 0000000..ce9e251 --- /dev/null +++ b/config/gen_headers/convert_to_txt.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +if [ $# -ne 1 ]; then + echo "usage: $0 DST_DIR" + exit 1 +fi + +OUT_DIR=$1 + +cd ${OUT_DIR} + +for i in *.pdf; do + echo Converting $i + pdftotext $i +done + diff --git a/config/gen_headers/gen_regs.py b/config/gen_headers/gen_regs.py new file mode 100755 index 0000000..3e59596 --- /dev/null +++ b/config/gen_headers/gen_regs.py @@ -0,0 +1,341 @@ +#!/usr/bin/python + +import xml.parsers.expat +import sys, re + +not_a_register=["IO_START_ADDR", + "IO_STOP_ADDR", + "EXT_IO_START_ADDR", + "EXT_IO_STOP_ADDR", + "MEM_START_ADDR", + "MEM_STOP_ADDR", + ] +curtree=[] +curattrtree=[] + + +##### timer prescalers + +prescaler_timer_num = -1 +prescaler_timers = {} + +def prescaler_module(): + global prescaler_timer_num + global prescaler_timers + + if curtree[-1] != "module": + return + if not curattrtree[-1].has_key("class"): + return + if not curattrtree[-1]["class"].startswith("TIMER_COUNTER"): + return + prescaler_timer_num = int(curattrtree[-1]["class"].replace("TIMER_COUNTER_", "")) + prescaler_timers[prescaler_timer_num] = [] + +def prescaler_clk(): + global prescaler_timer_num + global prescaler_timers + + if curtree[-3:] != ["module", "enumerator", "enum"]: + return + if not curattrtree[-2].has_key("name"): + return + if not curattrtree[-2]["name"].startswith("CLK_SEL_"): + return + if not curattrtree[-3].has_key("class"): + return + if not curattrtree[-3]["class"].startswith("TIMER_COUNTER"): + return + val = int(curattrtree[-1]["val"], 16) + text = curattrtree[-1]["text"] + if text == "No Clock Source (Stopped)": + prescaler = 0 + elif text == "Running, No Prescaling": + prescaler = 1 + elif text.startswith("Running, CLK/"): + prescaler = int(text.split("/")[1]) + elif text == "Running, ExtClk Tx Falling Edge": + prescaler = -1 + elif text == "Running, ExtClk Tx Rising Edge": + prescaler = -2 + else: + prescaler = -3 + prescaler_timers[prescaler_timer_num].append((val,prescaler)) + +def prescaler_module_end(): + global prescaler_timer_num + global prescaler_timers + + if curtree[-1] != "module": + return + if prescaler_timer_num == -1: + return + prescaler_timer_num = -1 + +def prescaler_print(): + global prescaler_timers + keys = prescaler_timers.keys() + keys.sort() + for k in keys: + print "/* prescalers timer %d */"%(k) + for p in prescaler_timers[k]: + if p[1] == -1: + txt = "FALL" + elif p[1] == -2: + txt = "RISE" + else: + txt = str(p[1]) + txt = "#define TIMER%d_PRESCALER_DIV_%s"%(k, txt) + txt = txt.ljust(40) + print "%s%d"%(txt, p[0]) + print + for p in prescaler_timers[k]: + txt = "#define TIMER%d_PRESCALER_REG_%d"%(k, p[0]) + txt = txt.ljust(40) + print "%s%d"%(txt, p[1]) + print + print + +##### + +# timer intrp + +timer_dict={} +sigtimer_OV_dict={} +sigtimer_OC_dict={} +sigtimer_IC_dict={} + +def timer_intrp(data): + if len(curtree) <= 3: + return + if curtree[-1] != "SOURCE": + return + if not curtree[-2].startswith("VECTOR"): + return + if not data.startswith("TIMER"): + return + timernum = re.sub("TIMER([0-9]).*", r"\1", data) + subtimernum=re.sub("TIMER[0-9].*COMP([A-C])", r"\1", data) + if len(subtimernum) != 1: + subtimernum="" + timerid = timernum+subtimernum + if data.find("OVF") != -1: + timer_dict[timerid] = 1 + sigtimer_OV_dict[timerid] = 1 + elif data.find("COMP") != -1: + timer_dict[timerid] = 1 + sigtimer_OC_dict[timerid] = 1 + elif data.find("CAPT") != -1: + timer_dict[timerid] = 1 + sigtimer_IC_dict[timerid] = 1 + +def timer_intrp_print(): + l=timer_dict.keys() + l.sort() + print "/* available timers */" + for k in l: + print "#define TIMER%s_AVAILABLE"%k + print + + l=sigtimer_OV_dict.keys() + l.sort() + i=0 + print "/* overflow interrupt number */" + for k in l: + print "#define SIG_OVERFLOW%s_NUM %d"%(k,i) + i+=1 + print "#define SIG_OVERFLOW_TOTAL_NUM %d"%i + print + + l=sigtimer_OC_dict.keys() + l.sort() + i=0 + print "/* output compare interrupt number */" + for k in l: + print "#define SIG_OUTPUT_COMPARE%s_NUM %d"%(k,i) + i+=1 + print "#define SIG_OUTPUT_COMPARE_TOTAL_NUM %d"%i + print + + i=0 + print "/* Pwm nums */" + for k in l: + print "#define PWM%s_NUM %d"%(k,i) + i+=1 + print "#define PWM_TOTAL_NUM %d"%i + print + + l=sigtimer_IC_dict.keys() + l.sort() + i=0 + print "/* input capture interrupt number */" + for k in l: + print "#define SIG_INPUT_CAPTURE%s_NUM %d"%(k,i) + i+=1 + print "#define SIG_INPUT_CAPTURE_TOTAL_NUM %d"%i + print + + +##### + +# regs +bits={} +regs={} + +def regs_parse(): + if len(curtree) <= 3: + return + if curtree[-1].find("_MASK") == -1: + return + if curtree[-3] != "IO_MEMORY": + return + bitname = curtree[-1].replace("_MASK", "_REG") + bitname = bitname.replace("-", "_") + + if bits.has_key(bitname) == False: + bits[bitname]=[] + bits[bitname].append(curtree[-2]) + + if regs.has_key(curtree[-2])==False: + regs[curtree[-2]]=[] + regs[curtree[-2]].append(bitname) + +def regs_print(): + for r in regs.keys(): + print + print "/* %s */"%r + for b in regs[r]: + if len(bits[b]) != 1: + reglist = bits[b][:] + reglist.remove(r) + regliststr = reduce(lambda x, y: x+", "+y, reglist) + print "/* #define %s %s%s */ /* dup in %s */"%(b, " "*(20-len(b)), r, regliststr) + else: + print "#define %s %s%s"%(b, " "*(20-len(b)), r) + print + +##### + +# pins + +alt_name = None +pin_name = None +pins_dict = {} + +def pins_parse(data): + global alt_name, pin_name + + if len(curtree) < 4: + return + if curtree[-1] not in [ "NAME", "ALT_NAME", "PIN_NAME" ]: + return + if not curtree[-2].startswith("PIN"): + return + if curtree[-4] != "PACKAGE": + return + pins = data[1:-1].split(":") + if curtree[-1] == "NAME": + alt_name = pins[0] + pin_name = pins[1:] + elif curtree[-1] == "ALT_NAME": + alt_name = pins[0] + elif curtree[-1] == "PIN_NAME": + pin_name = pins + +def pins_end(): + global alt_name, pin_name + + if len(curtree) < 3: + return + if not curtree[-1].startswith("PIN"): + return + if curtree[-3] != "PACKAGE": + return + if alt_name != None and re.match("P[A-Z][0-7]", alt_name): + pins_dict[alt_name[1:]] = pin_name + alt_name = None + pin_name = None + +def pins_print(): + keys = pins_dict.keys() + keys.sort() + print "/* pins mapping */" + for k in keys: + for p in pins_dict[k]: + p = p.replace("'", "") + print "#define %s_PORT PORT%s"%(p, k[0]) + print "#define %s_BIT %s"%(p, k[1]) + print + print + +##### + +def start_element(name, attrs): + global state, curtree, sigtimer_list, not_a_register, bits, regs + + curtree.append(name) + curattrtree.append(attrs) + + prescaler_module() + prescaler_clk() + + regs_parse() + + +def end_element(name): + global state, curtree, sigtimer_list, not_a_register + + prescaler_module_end() + pins_end() + + curtree.pop() + curattrtree.pop() + + +def char_data(data): + timer_intrp(data) + pins_parse(data) + + +print """/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + +""" + +p = xml.parsers.expat.ParserCreate() + +p.StartElementHandler = start_element +p.EndElementHandler = end_element +p.CharacterDataHandler = char_data + +f=open(sys.argv[1]) +p.Parse(f.read(), 1) + +prescaler_print() +timer_intrp_print() +regs_print() +pins_print() + +f.close() diff --git a/config/gen_headers/get_docs.sh b/config/gen_headers/get_docs.sh new file mode 100755 index 0000000..1bfd8ca --- /dev/null +++ b/config/gen_headers/get_docs.sh @@ -0,0 +1,45 @@ +#!/bin/sh + +if [ $# -ne 1 ]; then + echo "usage: $0 DST_DIR" + exit 1 +fi + +OUT_DIR=$1 + +URL_BASE=http://www.atmel.com +FAMILY_PATH=/dyn/products/datasheets.asp?family_id=607 +DOC_PATH=/dyn/resources/prod_documents/ + +DOCS=`wget -O - ${URL_BASE}${FAMILY_PATH} | grep ${DOC_PATH} | sed 's,.*'${DOC_PATH}'\([a-zA-Z0-9\.]*pdf\).*$,\1,' | sort -u | grep ^doc` + +cd ${OUT_DIR} +for i in ${DOCS}; do + echo "Downloading $i" + wget ${URL_BASE}${DOC_PATH}$i +done +cd - + +##################### + +# same with mature products + +URL_BASE=http://www.atmel.com +DOC_PATH=/dyn/resources/prod_documents/ + +DOCS2="DOC0838.PDF DOC0839.PDF DOC1004.PDF DOC1042.PDF DOC0841.PDF DOC1041.PDF Doc0945.pdf DOC1228.PDF doc1142.pdf doc1457.pdf" + +cd ${OUT_DIR} +for i in ${DOCS2}; do + echo "Downloading $i" + wget ${URL_BASE}${DOC_PATH}$i +done +cd - + +################### + +cd ${OUT_DIR} +for i in ${DOCS} ${DOCS2}; do + mv $i `echo $i | tr [A-Z] [a-z]` 2>/dev/null +done +cd - diff --git a/config/gen_headers/make_links.sh b/config/gen_headers/make_links.sh new file mode 100755 index 0000000..521a0fa --- /dev/null +++ b/config/gen_headers/make_links.sh @@ -0,0 +1,23 @@ +#!/bin/sh + +if [ $# -ne 3 ]; then + echo "usage: $0 SRC_DIR DST_DIR PDF_DST_DIR" + exit 1 +fi + +SRC_DIR=$1 +OUT_DIR=$2 +OUT2_DIR=$3 + +RE='^ATtiny[0-9]*\((L)\)\?$\|^ATtiny[0-9]*\(L\)\?$\|^ATtiny[0-9]*L/V$\|^ATmega[0-9]*/V$\|^ATmega[0-9]*\((L)\)\?$\|^AT90S[0-9]*\((L)\)\?$\|^AT90S/LS[0-9]*\((L)\)\?$' + +#\|^AT90PWM[0-9A-Z]*\(/[0-9A-Z]*\)*$' + +for i in ${SRC_DIR}/*.txt ; do + echo ==== $i ==== + for j in `grep -o $RE $i | sed 's,(L),,g' | sed 's,S/LS,S,g' | sed 's,L/V,,g' | sed 's,L,,g'| sed 's,/V,,g' | sed 's,V,,g' | sort -u`; do + echo ln -s ../$i ${OUT_DIR}/$j + ln -s ../$i ${OUT_DIR}/$j + ln -s ../${i%txt}pdf ${OUT2_DIR}/$j.pdf + done +done diff --git a/config/gen_headers/parse_doc.py b/config/gen_headers/parse_doc.py new file mode 100755 index 0000000..49c36c0 --- /dev/null +++ b/config/gen_headers/parse_doc.py @@ -0,0 +1,106 @@ +#!/usr/bin/python + +import os, sys, re + +def replace(s): +# print s+" --- "+ re.sub(".*/([0-9]*) .*",r"\1",s) + return re.sub(".*/([0-9]*).*",r"\1",s.split("\n")[0]) + + +def get_clocks(s): + timer=re.sub("CS([0-3n])0.*",r"\1",s.split("\n")[0]) + + cut=re.search("CS[^%s]"%timer, s) + if cut!= None: + s=s[:cut.start()] +# print s + + separators=[" CK", "PCK", "clkI/O", "clkT0S", "clkT2S"] + separators=map(lambda x:(s.count(x),x), separators) + separators.sort(cmp=lambda x,y:cmp(x[0],y[0])) + sep=separators[-1][1] +# print "---> " + sep + + l=s.split(sep) + newlist=[timer, 0, 1] + prev_x=0 + + for i in l: + try: + x=int(replace(i)) + except: + continue + + if x=0: + line="#define TIMER%s_PRESCALER_DIV_%d"%(n,d) + out+="%s%s%d\n"%(line, (35-len(line))*" ", i) + elif d==-1: + line="#define TIMER%s_PRESCALER_EXT_FALL"%(n) + out+="%s%s%d\n"%(line, (35-len(line))*" ", i) + elif d==-2: + line="#define TIMER%s_PRESCALER_EXT_RISE"%(n) + out+="%s%s%d\n"%(line, (35-len(line))*" ", i) + i+=1 + out+="\n" + + i=0 + for d in l: + out+="#define TIMER%s_PRESCALER_REG_%d %d\n"%(n,i,d) + i+=1 + out+="\n" + out+="\n" + return out + + + +if len(sys.argv) != 3: + print "bad args. usage: parse_doc.py DOC_DIR DST_DIR" + sys.exit(1) + +for name in os.listdir(sys.argv[1]): + f=open(os.path.join(sys.argv[1],name)) + list=[] + s=f.read() + list+=(re.findall('CS00.*topped.' + '.*\n'*15, s)) + list+=(re.findall('CS10.*topped.' + '.*\n'*15, s)) + list+=(re.findall('CS20.*topped.' + '.*\n'*15, s)) + list+=(re.findall('CS30.*topped.' + '.*\n'*15, s)) + list+=(re.findall('CSn0.*topped.' + '.*\n'*15, s)) + print "---- %s ----"%name +# print list + g=open(os.path.join(sys.argv[2],name),"w") + clks=[] + for i in list: + elt=get_clocks(i) + if elt[0]=='n': + elt[0]='1' + clks.append(elt[:]) + elt[0]='3' + clks.append(elt) + else: + clks.append(elt) + + clks.sort(cmp=lambda x,y:cmp(int(x[0]),int(y[0]))) + defines=get_defs(clks) + g.write("%s\n"%defines) + g.close() diff --git a/config/generate_aversive_config b/config/generate_aversive_config new file mode 100755 index 0000000..534a131 --- /dev/null +++ b/config/generate_aversive_config @@ -0,0 +1,218 @@ +#!/bin/sh + +# +# usage generate_aversive_config config_file dst_module_file +# + +# +# order is important !! High level modules first (defines link order) +# +MODULES_LIST="CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL,/devices/brushless_motors/brushless_3phase_digital_hall + CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE,/devices/brushless_motors/brushless_3phase_digital_hall_double + CONFIG_MODULE_MENU,ihm/menu + CONFIG_MODULE_PARSE,ihm/parse + CONFIG_MODULE_RDLINE,ihm/rdline + CONFIG_MODULE_VT100,ihm/vt100 + CONFIG_MODULE_LCD,devices/ihm/lcd + CONFIG_MODULE_MULTISERVO,devices/servo/multiservo + CONFIG_MODULE_AX12,devices/servo/ax12 + CONFIG_MODULE_ENCODERS_SPI,devices/encoders/encoders_spi + CONFIG_MODULE_ENCODERS_MICROB,devices/encoders/encoders_microb + CONFIG_MODULE_ENCODERS_EIRBOT,devices/encoders/encoders_eirbot + CONFIG_MODULE_TRAJECTORY_MANAGER,devices/robot/trajectory_manager + CONFIG_MODULE_BLOCKING_DETECTION_MANAGER,devices/robot/blocking_detection_manager + CONFIG_MODULE_OBSTACLE_AVOIDANCE,devices/robot/obstacle_avoidance + CONFIG_MODULE_POSITION_MANAGER,devices/robot/position_manager + CONFIG_MODULE_ROBOT_SYSTEM,devices/robot/robot_system + CONFIG_MODULE_PID,devices/control_system/filters/pid + CONFIG_MODULE_RAMP,devices/control_system/filters/ramp + CONFIG_MODULE_QUADRAMP,devices/control_system/filters/quadramp + CONFIG_MODULE_QUADRAMP_DERIVATE,devices/control_system/filters/quadramp_derivate + CONFIG_MODULE_BIQUAD,devices/control_system/filters/biquad + CONFIG_MODULE_CONTROL_SYSTEM_MANAGER,devices/control_system/control_system_manager + CONFIG_MODULE_TIME,base/time + CONFIG_MODULE_SCHEDULER,base/scheduler + CONFIG_MODULE_SPI,comm/spi + CONFIG_MODULE_CC2420,devices/radio/cc2420 + CONFIG_MODULE_UART,comm/uart + CONFIG_MODULE_I2C,comm/i2c + CONFIG_MODULE_MF2_CLIENT,comm/mf2_client + CONFIG_MODULE_MF2_SERVER,comm/mf2_server + CONFIG_MODULE_PWM,hardware/pwm + CONFIG_MODULE_PWM_NG,hardware/pwm_ng + CONFIG_MODULE_ADC,hardware/adc + CONFIG_MODULE_AES,crypto/aes + CONFIG_MODULE_MD5,crypto/md5 + CONFIG_MODULE_RC4,crypto/rc4 + CONFIG_MODULE_HAMMING,encoding/hamming + CONFIG_MODULE_TIMER,hardware/timer + CONFIG_MODULE_BASE64,encoding/base64 + CONFIG_MODULE_CIRBUF,base/cirbuf + CONFIG_MODULE_DIAGNOSTIC,debug/diagnostic + CONFIG_MODULE_ERROR,debug/error + CONFIG_MODULE_FIXED_POINT,base/math/fixed_point + CONFIG_MODULE_TIME_EXT,base/time_ext + CONFIG_MODULE_GEOMETRY,base/math/geometry + CONFIG_MODULE_VECT2,base/math/vect2" + +echo +echo Generating aversive configuration files + +# does the .config file exists ? +if [ ! -f $1 ]; then + echo "No such file <$1>" + exit 1 +fi + +echo "# Aversive configuration" > $2 + +#### +##### MCU, compilation options, output format +#### + +echo -n "MCU = " >> $2 +echo `grep "CONFIG_MCU_.*=y" $1 | sed s,CONFIG_MCU_,, | sed s,=y,, | tr "[A-Z]" "[a-z]"` >> $2 + +echo -n "OPT = " >> $2 +echo `grep "CONFIG_OPTM_.*=y" $1 | sed s,CONFIG_OPTM_,, | sed s,=y,, | tr "[A-Z]" "[a-z]"` >> $2 + +if grep "CONFIG_FORMAT_IHEX=y" $1 > /dev/null 2> /dev/null + then + echo "FORMAT = ihex" >> $2 + echo "FORMAT_EXTENSION = hex" >> $2 +fi + +if grep "CONFIG_FORMAT_SREC=y" $1 > /dev/null 2> /dev/null + then + echo "FORMAT = srec" >> $2 + echo "FORMAT_EXTENSION = srec" >> $2 +fi + +if grep "CONFIG_FORMAT_BINARY=y" $1 > /dev/null 2> /dev/null + then + echo "FORMAT = binary" >> $2 + echo "FORMAT_EXTENSION = bin" >> $2 +fi + +#### +##### Math lib and printf +#### + +if grep "CONFIG_MATH_LIB=y" $1 > /dev/null 2> /dev/null + then + echo "MATH_LIB = -lm" >> $2 +else + echo "MATH_LIB = " >> $2 +fi + +if grep "CONFIG_MINIMAL_PRINTF=y" $1 > /dev/null 2> /dev/null + then + echo "PRINTF_LDFLAGS = -Wl,-u,vfprintf -lprintf_min" >> $2 +fi + +if grep "CONFIG_STANDARD_PRINTF=y" $1 > /dev/null 2> /dev/null + then + echo "PRINTF_LDFLAGS = " >> $2 +fi + +if grep "CONFIG_ADVANCED_PRINTF=y" $1 > /dev/null 2> /dev/null + then + echo "PRINTF_LDFLAGS = -Wl,-u,vfprintf -lprintf_flt" >> $2 +fi + +if grep "CONFIG_FDEVOPEN_COMPAT=y" $1 > /dev/null 2> /dev/null + then + echo "CFLAGS += -D__STDIO_FDEVOPEN_COMPAT_12" >> $2 +fi + + + +#### +##### Programmer +#### + +if grep "CONFIG_AVRDUDE=y" $1 > /dev/null 2> /dev/null + then + echo "PROGRAMMER = avrdude" >> $2 +fi + +echo -n "AVRDUDE_PROGRAMMER = " >> $2 +echo `grep "CONFIG_AVRDUDE_PROG_.*=y" $1 | sed s,CONFIG_AVRDUDE_PROG_,, | sed s,=y,, | tr [A-Z_] [a-z\-]` >> $2 + +echo -n "AVRDUDE_PORT = " >> $2 +echo `grep "CONFIG_AVRDUDE_PORT" $1 | sed s,CONFIG_AVRDUDE_PORT=,,` >> $2 + +echo -n "AVRDUDE_BAUDRATE = " >> $2 +echo `grep "CONFIG_AVRDUDE_BAUDRATE" $1 | sed s,CONFIG_AVRDUDE_BAUDRATE=,,` >> $2 + +if grep "CONFIG_AVRDUDE_CHECK_SIGNATURE=y" $1 > /dev/null 2> /dev/null + then + echo "AVRDUDE_FLAGS_SIGNATURE_CHECK =" >> $2 +else + echo "AVRDUDE_FLAGS_SIGNATURE_CHECK = -F" >> $2 +fi + + +if grep "CONFIG_AVARICE=y" $1 > /dev/null 2> /dev/null + then + echo "PROGRAMMER = avarice" >> $2 + if ! grep "CONFIG_FORMAT_BINARY=y" $1 > /dev/null 2> /dev/null + then + echo "WARNING: With avarice, output format should be binary" + fi +fi + +if grep "CONFIG_AVARICE_PROG_MKI=y" $1 > /dev/null 2> /dev/null + then + echo "AVARICE_PROGRAMMER = mkI" >> $2 +fi + +if grep "CONFIG_AVARICE_PROG_MKII=y" $1 > /dev/null 2> /dev/null + then + echo "AVARICE_PROGRAMMER = mkII" >> $2 +fi + +echo -n "AVARICE_PORT = " >> $2 +echo `grep "CONFIG_AVARICE_PORT" $1 | sed s,CONFIG_AVARICE_PORT=,,` >> $2 + +echo -n "AVARICE_DEBUG_PORT = " >> $2 +echo `grep "CONFIG_AVARICE_DEBUG_PORT" $1 | sed s,CONFIG_AVARICE_DEBUG_PORT=,,` >> $2 + + +#### +##### Generation of the module list +#### +echo -n "MODULES =" >> $2 + +for i in $MODULES_LIST +do + config=`echo $i | cut -d ',' -f1-1` + path=`echo $i | cut -d ',' -f2-2` + + + if grep $config=y $1 2>/dev/null >/dev/null + then + echo -n " "$path >> $2 + fi + + if grep -q "${config}_CREATE_CONFIG=y" $1; then + CONF_FILE=`basename $path`_config.h + if [ -f $CONF_FILE ] + then + echo Cannot create default conf file $CONF_FILE, file exists + else + if [ ! -f $AVERSIVE_DIR/modules/$path/config/$CONF_FILE ]; then + echo Cannot create default conf file $CONF_FILE, no config sample in $AVERSIVE_DIR/modules/$path/config/$CONF_FILE + else + echo Creating default conf file $CONF_FILE . + cp $AVERSIVE_DIR/modules/$path/config/$CONF_FILE . + fi + fi + fi +done +echo >> $2 + + + + +echo >> $2 diff --git a/config/prog_fuses.sh b/config/prog_fuses.sh new file mode 100755 index 0000000..176bfd0 --- /dev/null +++ b/config/prog_fuses.sh @@ -0,0 +1,258 @@ +#!/bin/sh + +# bit $1 is set in $2 (8 bits) +bit_is_set() { + return $[ $[ $2 / $[ ( 1 << $1 ) ] ] % 2 ] + # <<$ fix syntax coloration +} + +# $1 = name +# $2 = value +disp_fuse() { + echo -n "$1:" + echo -n -e "\t" + let bit=7 + while [ $bit -ge 0 ]; + do + NAME=`cut -d ' ' -f 2- ${MCU_DESC_FILE} | grep "^$bit $1" | cut -d ' ' -f 3` + if [ -z "$NAME" ]; then + echo -n "XXXX" + else + bit_is_set $bit $2 + bitval=$? + echo -n "$NAME=$bitval" + fi + echo -n " " + let bit=$bit-1 + done + echo +} + +# $1 filename +intel2hex() { + echo "0x`cat $1 | head -1 | cut -b10-11`" > $1.tmp + mv $1.tmp $1 +} + +# $1 filename +hex2intel() { + printf ":01000000%.2X" `cat $1` > $1.tmp + printf "%.2X\n" $[ 0xFF - `cat $1` ] >> $1.tmp + echo ":00000001FF" >> $1.tmp + mv $1.tmp $1 +} + + +# 1/ read fuse state if possible +# 2/ prompt every bit +# 3/ program + +MCU_DESC_FILE=$1 + +echo "----------------------------------------------------------" +echo " Programming fuses" +echo "----------------------------------------------------------" +echo +echo "Warning : It can bue dangerous to program your fuses: some" +echo "configurations will prevent you to program your uC. Be sure" +echo "that you have carrefully read the documentation, and that" +echo "you know what you're doing" +echo +echo "Warning : 0 means programmed and 1 means unprogrammed (see" +echo "AVR documentation for details" +echo +echo "BIT FAT WARNING ! PLEASE CHECK THE DOCUMENTATION BEFORE" +echo "PROGRAMMING BECAUSE SOME PARTS HAVE NOT BEEN TESTED" +echo + +while true + do + echo -n "Are you sure ? [y/n] " + read ans + + case $ans in + y|Y) + break + ;; + n|N) + echo " abort..." + exit 0 + ;; + *) + echo " Please type 'y' or 'n'" + esac +done + +if [ ! -f ${MCU_DESC_FILE} ]; then + echo "ERROR" + echo "Can't find the file ${MCU_DESC_FILE}" + echo "If `basename ${MCU_DESC_FILE}` is a valid uC, you should add it in" + echo "AVERSIVE/config/fuses_defs directory" + exit 1 +fi + +if [ -z "${PROGRAMMER}" ]; then + echo "ERROR !" + echo " PROGRAMMER variable is not defined, check that the script" + echo " is launched from a 'make fuse' in project directory" + exit 1 +fi + +if [ "${PROGRAMMER}" = "avrdude" -a -z "${AVRDUDE}" ]; then + echo "ERROR !" + echo " AVRDUDE variable is not defined, check that the script" + echo " is launched from a 'make fuse' in project directory" + exit 1 +fi + +if [ "${AVARICE}" = "avarice" -a -z "${AVARICE}" ]; then + echo "ERROR !" + echo " AVARICE variable is not defined, check that the script" + echo " is launched from a 'make fuse' in project directory" + exit 1 +fi + +if [ "${PROGRAMMER}" = "avarice" ]; then + echo "ERROR !" + echo " Sorry, AVARICE fuse programming is not implemented now" + exit 1 +fi + +if [ `wc -c ${MCU_DESC_FILE} | cut -d ' ' -f 1` -eq 0 ]; then + echo "Aborting : this uC does not have any fuse to program." + exit 0 +fi + + +FUSE_LIST=`cut -d ' ' -f 3 ${MCU_DESC_FILE} | sort -u` + +echo "Reading current fuse state" + +if [ ! -z "${AVRDUDE_DELAY}" ]; then + DELAY="-i ${AVRDUDE_DELAY}" +else + DELAY="" +fi + +CANNOT_READ=0 + +for f in ${FUSE_LIST} + do + rm -f $f 2> /dev/null + echo 0x00 > ${f}_new + ${AVRDUDE} ${DELAY} -p ${MCU} -P `echo ${AVRDUDE_PORT} | sed 's,",,g'` -c ${AVRDUDE_PROGRAMMER} -U ${f}:r:${f}:i + if [ ! -f $f ]; then + CANNOT_READ=1 + fi +done + +echo +echo + +if [ $CANNOT_READ -eq 1 ]; then + echo -n "Problem during reading fuse. Continue anyway with writing ? [y/N] " + read ans + case $ans in + y|Y) + echo " ok" + echo + echo + + ;; + *|n|N) + echo " abort..." + exit 1 + esac +else + for f in ${FUSE_LIST}; do + intel2hex $f + disp_fuse $f `cat $f` + done + echo + echo +fi + +echo "Now please enter the new value for each fuse. The default one" +echo "is the value that has been read, or factory default if read failed" +echo +echo + +NB_LINE=`wc -l ${MCU_DESC_FILE} | cut -d ' ' -f 1` +SEQ_END=$[ ${NB_LINE} - 1 ] + +for i in `seq 0 ${SEQ_END}` + do + LINE=`grep "^${i} " ${MCU_DESC_FILE}` + BIT=`echo ${LINE} | cut -d ' ' -f 2` + FUSE=`echo ${LINE} | cut -d ' ' -f 3` + NAME=`echo ${LINE} | cut -d ' ' -f 4` + FACTORY=`echo ${LINE} | cut -d ' ' -f 5` + DEFAULT=${FACTORY} + CURRENT=x + HELP=`echo ${LINE} | cut -d ' ' -f 6-` + if [ -f ${FUSE} ]; then + BIN_FUSE=`cat $FUSE` + bit_is_set $BIT `printf "%d" $BIN_FUSE` + CURRENT=$? + DEFAULT=${CURRENT} + fi + + echo -n "[$FUSE:${BIT}] ${NAME} <${HELP}> (factory=${DEFAULT}) (current=${CURRENT}) [${DEFAULT}] ? " + read ans + + if [ -z "$ans" ] ; then + ans=${DEFAULT} + fi + + case $ans in + 1) + printf "0x%x\n" $[ $[ ( 1 << $BIT ) ] + `cat ${FUSE}_new` ] > ${FUSE}_new + # <<$ fix syntax coloration + echo " get 1 (unprogrammed)" + ;; + 0) + echo " get 0 (programmed)" + ;; + *) + echo "Bad answer, aborting..." + exit 1 + esac + +done + +echo +echo "Summary of new values :" +echo + +for f in ${FUSE_LIST}; do + if [ ! -f ${f}_new ]; then + echo "ERROR: cannot find ${f}_new, aborting" + exit 1 + fi + disp_fuse $f `cat ${f}_new` +done + +echo + + +while true + do + echo -n "Are you sure ? [y/n] " + read ans + + case $ans in + y|Y) + for f in ${FUSE_LIST}; do + hex2intel ${f}_new + ${AVRDUDE} -p ${MCU} -P `echo ${AVRDUDE_PORT} | sed 's,",,g'` -c ${AVRDUDE_PROGRAMMER} -U ${f}:w:${f}_new:i ${DELAY} + done + exit 0 + ;; + n|N) + echo " abort..." + exit 0 + ;; + *) + echo " Please type 'y' or 'n'" + esac +done diff --git a/config/scripts/CVS/Entries b/config/scripts/CVS/Entries new file mode 100644 index 0000000..4dd0b6a --- /dev/null +++ b/config/scripts/CVS/Entries @@ -0,0 +1,5 @@ +/Configure/1.8.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/Makefile/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/Menuconfig/1.7.6.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/README.Menuconfig/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +D/lxdialog//// diff --git a/config/scripts/CVS/Repository b/config/scripts/CVS/Repository new file mode 100644 index 0000000..53375a5 --- /dev/null +++ b/config/scripts/CVS/Repository @@ -0,0 +1 @@ +aversive/config/scripts diff --git a/config/scripts/CVS/Root b/config/scripts/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/config/scripts/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/config/scripts/CVS/Tag b/config/scripts/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/config/scripts/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/config/scripts/CVS/Template b/config/scripts/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/config/scripts/Configure b/config/scripts/Configure new file mode 100644 index 0000000..dc0f9f5 --- /dev/null +++ b/config/scripts/Configure @@ -0,0 +1,421 @@ +#! /bin/sh +# +# This script is used to configure an Aversive project. It is mainly +# coming from the Linux Kernel Configure script. Thanks to the authors. +# + + + +# Make sure we're really running bash. +# +# I would really have preferred to write this script in a language with +# better string handling, but alas, bash is the only scripting language +# that I can be reasonable sure everybody has on their linux machine. +# +[ -z "$BASH" ] && { echo "Configure requires bash" 1>&2; exit 1; } + +# Disable filename globbing once and for all. +# Enable function cacheing. +set -f -h + +# +# Dummy functions for use with a config.in modified for menuconf +# +function mainmenu_option () { + : +} +function mainmenu_name () { + : +} +function endmenu () { + : +} + +# +# help prints the corresponding help text from ${HELP_FILE} to stdout +# +# help variable +# +function help () { + if [ -f ${HELP_FILE} ] + then + #first escape regexp special characters in the argument: + var=$(echo "$1"|sed 's/[][\/.^$*]/\\&/g') + #now pick out the right help text: + text=$(sed -n "/^$var[ ]*\$/,\${ + /^$var[ ]*\$/c\\ +${var}:\\ + + /^#/b + /^[^ ]/q + p + }" ${HELP_FILE}) + if [ -z "$text" ] + then + echo; echo " Sorry, no help available for this option yet.";echo + else + (echo; echo "$text") | ${PAGER:-more} + fi + else + echo; + echo " Can't access the file ${HELP_FILE} which" + echo " should contain the help texts." + echo + fi +} + + +# +# readln reads a line into $ans. +# +# readln prompt default oldval +# +function readln () { + if [ "$DEFAULT" = "-d" ]; then + echo "$1" + ans=$2 + else + echo -n "$1" + [ -z "$3" ] && echo -n "(NEW) " + IFS='@' read ans || exit 1 + [ -z "$ans" ] && ans=$2 + fi +} + +# +# comment does some pretty-printing +# +# comment 'xxx' +# +function comment () { + echo "*"; echo "* $1" ; echo "*" + (echo "" ; echo "#"; echo "# $1" ; echo "#") >>$CONFIG + (echo "" ; echo "/*"; echo " * $1" ; echo " */") >>$CONFIG_H +} + +# +# define_bool sets the value of a boolean argument +# +# define_bool define value +# + +function define_bool () { + case "$2" in + "y") + echo "$1=y" >>$CONFIG + echo "#define $1 1" >>$CONFIG_H + ;; + + "n") + echo "# $1 is not set" >>$CONFIG + echo "#undef $1" >>$CONFIG_H + ;; + esac + eval "$1=$2" +} + +# +# bool processes a boolean argument +# +# bool question define +# +function bool () { + old=$(eval echo "\${$2}") + def=${old:-'n'} + case "$def" in + "y" | "m") defprompt="Y/n/?" + def="y" + ;; + "n") defprompt="N/y/?" + ;; + esac + while :; do + readln "$1 ($2) [$defprompt] " "$def" "$old" + case "$ans" in + [yY] | [yY]es ) define_bool "$2" "y" + break;; + [nN] | [nN]o ) define_bool "$2" "n" + break;; + * ) help "$2" + ;; + esac + done +} + +function dep_bool () { + ques=$1 + var=$2 + shift 2 + while [ $# -gt 0 ]; do + case "$1" in + n) + define_bool "$var" "n" + return + ;; + esac + shift + done + + bool "$ques" "$var" +} + + +# +# define_int sets the value of a integer argument +# +# define_int define value +# +function define_int () { + echo "$1=$2" >>$CONFIG + echo "#define $1 ($2)" >>$CONFIG_H + eval "$1=$2" +} + +# +# int processes an integer argument with optional limits +# +# int question define default [min max] +# +function int () { + old=$(eval echo "\${$2}") + def=${old:-$3} + if [ $# -gt 3 ]; then + min=$4 + else + min=-1000000000 # !! + fi + if [ $# -gt 4 ]; then + max=$5 + else + max=1000000000 # !! + fi + while :; do + readln "$1 ($2) [$def] " "$def" "$old" + echo [$ans] + if expr \( \( $ans + 0 \) \>= $min \) \& \( $ans \<= $max \) >/dev/null 2>&1 ; then + define_int "$2" "$ans" + break + else + help "$2" + fi + done +} + +# +# define_hex sets the value of a hexadecimal argument +# +# define_hex define value +# +function define_hex () { + echo "$1=$2" >>$CONFIG + echo "#define $1 0x${2#*[x,X]}" >>$CONFIG_H + eval "$1=$2" +} + +# +# hex processes an hexadecimal argument +# +# hex question define default +# +function hex () { + old=$(eval echo "\${$2}") + def=${old:-$3} + def=${def#*[x,X]} + while :; do + readln "$1 ($2) [$def] " "$def" "$old" + ans=${ans#*[x,X]} + if expr "$ans" : '[0-9a-fA-F][0-9a-fA-F]*$' > /dev/null; then + define_hex "$2" "$ans" + break + else + help "$2" + fi + done +} + +# +# define_string sets the value of a string argument +# +# define_string define value +# +function define_string () { + echo "$1=\"$2\"" >>$CONFIG + echo "#define $1 \"$2\"" >>$CONFIG_H + eval "$1=\"$2\"" +} + +# +# string processes a string argument +# +# string question define default +# +function string () { + old=$(eval echo "\${$2}") + def=${old:-$3} + while :; do + if [ "$old" = "?" ]; then + readln "$1 ($2) [$def] " "$def" "" + else + readln "$1 ($2) [$def] " "$def" "$old" + fi + if [ "$ans" = "?" ]; then + help "$2" + else + break + fi + done + define_string "$2" "$ans" +} +# +# choice processes a choice list (1-out-of-n) +# +# choice question choice-list default +# +# The choice list has a syntax of: +# NAME WHITESPACE VALUE { WHITESPACE NAME WHITESPACE VALUE } +# The user may enter any unique prefix of one of the NAMEs and +# choice will define VALUE as if it were a boolean option. +# VALUE must be in all uppercase. Normally, VALUE is of the +# form CONFIG_. Thus, if the user selects , +# the CPP symbol CONFIG_ will be defined and the +# shell variable CONFIG_ will be set to "y". +# +function choice () { + question="$1" + choices="$2" + old= + def=$3 + + # determine default answer: + names="" + set -- $choices + firstvar=$2 + while [ -n "$2" ]; do + if [ -n "$names" ]; then + names="$names, $1" + else + names="$1" + fi + if [ "$(eval echo \"\${$2}\")" = "y" ]; then + old=$1 + def=$1 + fi + shift; shift + done + + val="" + while [ -z "$val" ]; do + ambg=n + readln "$question ($names) [$def] " "$def" "$old" + ans=$(echo $ans | tr a-z A-Z) + set -- $choices + while [ -n "$1" ]; do + name=$(echo $1 | tr a-z A-Z) + case "$name" in + "$ans"* | */"$ans"* ) + case "$name" in + "$ans" | */"$ans"/* | \ + "$ans"/* | */"$ans" ) + val="$2" + break # exact match + ;; + esac + if [ -n "$val" ]; then + echo;echo \ + " Sorry, \"$ans\" is ambiguous; please enter a longer string." + echo + val="" + ambg=y + break + else + val="$2" + fi;; + esac + shift; shift + done + if [ "$val" = "" -a "$ambg" = "n" ]; then + help "$firstvar" + fi + done + set -- $choices + while [ -n "$2" ]; do + if [ "$2" = "$val" ]; then + echo " defined $val" + define_bool "$2" "y" + else + define_bool "$2" "n" + fi + shift; shift + done +} + +CONFIG=.tmpconfig +CONFIG_H=.tmpconfig.h +trap "rm -f $CONFIG $CONFIG_H ; exit 1" 1 2 +if [ -z "$HELP_FILE" ] +then + HELP_FILE="Documentation/Configure.help" +fi + +# +# Make sure we start out with a clean slate. +# +echo "#" > $CONFIG +echo "# Automatically generated make config: don't edit" >> $CONFIG +echo "#" >> $CONFIG + +echo "/*" > $CONFIG_H +echo " * Automatically generated C config: don't edit" >> $CONFIG_H +echo " */" >> $CONFIG_H +echo "#define AUTOCONF_INCLUDED" >> $CONFIG_H + +DEFAULT="" +if [ "$1" = "-d" ] ; then + DEFAULT="-d" + shift +fi + +CONFIG_IN=./config.in +if [ "$1" != "" ] ; then + CONFIG_IN=$1 +fi + +DEFAULTS=$AVERSIVE_DIR/config/.config +if [ -f .config ]; then + DEFAULTS=.config +fi + +if [ -f $DEFAULTS ]; then + echo "#" + echo "# Using defaults found in" $DEFAULTS + echo "#" + . $DEFAULTS + sed -e 's/# \(CONFIG_[^ ]*\) is not.*/\1=n/' <$DEFAULTS >.config-is-not.$$ + . .config-is-not.$$ + rm .config-is-not.$$ +else + echo "#" + echo "# No defaults found" + echo "#" +fi + +. $CONFIG_IN + +rm -f .config.old +if [ -f .config ]; then + mv .config .config.old +fi +mv .tmpconfig .config +if [ -w "`dirname ${AUTOCONF_FILE:=include/linux/autoconf.h}`" ]; then + mv .tmpconfig.h ${AUTOCONF_FILE:-include/linux/autoconf.h} +fi + +$AVERSIVE_DIR/config/generate_aversive_config .config .aversive_conf + +echo +echo "*** End of Aversive project configuration." +echo "*** Next, you should run 'make clean, then make'." +echo + + +exit 0 diff --git a/config/scripts/Makefile b/config/scripts/Makefile new file mode 100644 index 0000000..9ee50b7 --- /dev/null +++ b/config/scripts/Makefile @@ -0,0 +1,39 @@ +HEADER=header.tk +TAIL=tail.tk + +# Previous versions always remade kconfig.tk because they always depended +# on soundscript. This runs fairly fast, and I can't find all the +# Config.in files to depend on anyways. So I'll force it to remake. + +kconfig.tk: dummy + +kconfig.tk: ${TOPDIR}/Makefile ${TOPDIR}/arch/${ARCH}/config.in \ + tkparse ${HEADER} ${TAIL} + @if [ -f /usr/local/bin/wish ]; then \ + echo '#!'"/usr/local/bin/wish -f" > kconfig.tk; \ + else \ + echo '#!'"/usr/bin/wish -f" > kconfig.tk; \ + fi + cat ${HEADER} >> ./kconfig.tk + ./tkparse < ../arch/${ARCH}/config.in >> kconfig.tk + echo "set defaults \"arch/${ARCH}/defconfig\"" >> kconfig.tk + echo "set ARCH \"${ARCH}\"" >> kconfig.tk + cat ${TAIL} >> kconfig.tk + chmod 755 kconfig.tk + +tkparse: tkparse.o tkcond.o tkgen.o + ${HOSTCC} -o tkparse tkparse.o tkcond.o tkgen.o + +tkparse.o: tkparse.c tkparse.h + +tkcond.o: tkcond.c tkparse.h + +tkgen.o: tkgen.c tkparse.h + +tkparse.o tkcond.o tkgen.o: + $(HOSTCC) $(HOSTCFLAGS) -c -o $@ $(@:.o=.c) + +clean: + rm -f *~ kconfig.tk *.o tkparse + +# include $(TOPDIR)/Rules.make diff --git a/config/scripts/Menuconfig b/config/scripts/Menuconfig new file mode 100644 index 0000000..3b826c9 --- /dev/null +++ b/config/scripts/Menuconfig @@ -0,0 +1,1197 @@ +#! /bin/sh +# +# This script is used to configure an Aversive project. It is mainly +# coming from the Linux Kernel Menuconfig script. Thanks to the authors. +# + +# +# Change this to TRUE if you prefer all kernel options listed +# in a single menu rather than the standard menu hierarchy. +# +single_menu_mode= + +# +# Make sure we're really running bash. +# +[ -z "$BASH" ] && { echo "Menuconfig requires bash" 1>&2; exit 1; } + +# +# Cache function definitions, turn off posix compliance +# +set -h +o posix + + + +# Given a configuration variable, set the global variable $x to its value, +# and the global variable $info to the string " (NEW)" if this is a new +# variable. +# +# This function looks for: (1) the current value, or (2) the default value +# from the arch-dependent defconfig file, or (3) a default passed by the caller. + +function set_x_info () { + eval x=\$$1 + if [ -z "$x" ]; then + eval `sed -n -e 's/# \(.*\) is not set.*/\1=n/' -e "/^$1=/p" arch/$ARCH/defconfig` + eval x=\${$1:-"$2"} + eval $1=$x + eval INFO_$1="' (NEW)'" + fi + eval info="\$INFO_$1" +} + +# +# Load the functions used by the config.in files. +# +# I do this because these functions must be redefined depending +# on whether they are being called for interactive use or for +# saving a configuration to a file. +# +# Thank the heavens bash supports nesting function definitions. +# +load_functions () { + +# +# Additional comments +# +function comment () { + comment_ctr=$[ comment_ctr + 1 ] + echo -ne "': $comment_ctr' '--- $1' " >>MCmenu +} + +# +# Define a boolean to a specific value. +# +function define_bool () { + eval $1=$2 +} + +function define_hex () { + eval $1=$2 +} + +function define_int () { + eval $1=$2 +} + +function define_string () { + eval $1="$2" +} + +# +# Create a boolean (Yes/No) function for our current menu +# which calls our local bool function. +# +function bool () { + set_x_info "$2" "n" + + case $x in + y|m) flag="*" ;; + n) flag=" " ;; + esac + + echo -ne "'$2' '[$flag] $1$info' " >>MCmenu + + echo -e "function $2 () { l_bool '$2' \"\$1\" ;}\n" >>MCradiolists +} + +# +# Same as above, but now only Y and N are allowed as dependency +# (i.e. third and next arguments). +# +function dep_bool () { + ques="$1" + var="$2" + dep=y + shift 2 + while [ $# -gt 0 ]; do + if [ "$1" = y ]; then + shift + else + dep=n + shift $# + fi + done + if [ "$dep" = y ]; then + bool "$ques" "$var" + else + define_bool "$var" n + fi +} + +# +# Add a menu item which will call our local int function. +# +function int () { + set_x_info "$2" "$3" + + echo -ne "'$2' '($x) $1$info' " >>MCmenu + + echo -e "function $2 () { l_int '$1' '$2' '$3' '$x' ;}" >>MCradiolists +} + +# +# Add a menu item which will call our local hex function. +# +function hex () { + set_x_info "$2" "$3" + x=${x##*[x,X]} + + echo -ne "'$2' '($x) $1$info' " >>MCmenu + + echo -e "function $2 () { l_hex '$1' '$2' '$3' '$x' ;}" >>MCradiolists +} + +# +# Add a menu item which will call our local string function. +# +function string () { + set_x_info "$2" "$3" + + echo -ne "'$2' ' $1: \"$x\"$info' " >>MCmenu + + echo -e "function $2 () { l_string '$1' '$2' '$3' '$x' ;}" >>MCradiolists +} + +# +# Add a menu item which will call our local One-of-Many choice list. +# +function choice () { + # + # Need to remember params cause they're gonna get reset. + # + title=$1 + choices=$2 + default=$3 + current= + + # + # Find out if one of the choices is already set. + # If it's not then make it the default. + # + set -- $choices + firstchoice=$2 + + while [ -n "$2" ] + do + if eval [ "_\$$2" = "_y" ] + then + current=$1 + break + fi + shift ; shift + done + + : ${current:=$default} + + echo -ne "'$firstchoice' '($current) $title' " >>MCmenu + + echo -e " + function $firstchoice () \ + { l_choice '$title' \"$choices\" $current ;}" >>MCradiolists +} + +} # END load_functions() + + + +################################################################# + +# +# Extract available help for an option from Configure.help +# and send it to standard output. +# +# Most of this function was borrowed from the original kernel +# Configure script. +# +function extract_help () { + if [ -f ${HELP_FILE} ] + then + #first escape regexp special characters in the argument: + var=$(echo "$1"|sed 's/[][\/.^$*]/\\&/g') + #now pick out the right help text: + text=$(sed -n "/^$var[ ]*\$/,\${ + /^$var[ ]*\$/c\\ +${var}:\\ + + /^#/b + /^[^ ]/q + s/^ // + p + }" ${HELP_FILE}) + + if [ -z "$text" ] + then + echo "There is no help available for this Aversive option." + return 1 + else + echo "$text" + fi + else + echo "There is no help available for this Aversive option." + return 1 + fi +} + +# +# Activate a help dialog. +# +function help () { + if extract_help $1 >help.out + then + $DIALOG --backtitle "$backtitle" --title "$2"\ + --textbox help.out $ROWS $COLS + else + $DIALOG --backtitle "$backtitle" \ + --textbox help.out $ROWS $COLS + fi + rm -f help.out +} + +# +# Show the README file. +# +function show_readme () { + $DIALOG --backtitle "$backtitle" \ + --textbox scripts/README.Menuconfig $ROWS $COLS +} + +# +# Begin building the dialog menu command and Initialize the +# Radiolist function file. +# +function menu_name () { + echo -ne "$DIALOG --title '$1'\ + --backtitle '$backtitle' \ + --menu '$menu_instructions' \ + $ROWS $COLS $((ROWS-10)) \ + '$default' " >MCmenu + >MCradiolists +} + +# +# Add a submenu option to the menu currently under construction. +# +function submenu () { + echo -ne "'activate_menu $2' '$1 --->' " >>MCmenu +} + +# +# Handle a boolean (Yes/No) option. +# +function l_bool () { + if [ -n "$2" ] + then + case "$2" in + y|m) eval $1=y ;; + c) eval x=\$$1 + case $x in + y) eval $1=n ;; + n) eval $1=y ;; + *) eval $1=y ;; + esac ;; + *) eval $1=n ;; + esac + else + echo -ne "\007" + fi +} + +# +# Create a dialog for entering an integer into a kernel option. +# +function l_int () { + while true + do + if $DIALOG --title "$1" \ + --backtitle "$backtitle" \ + --inputbox "$inputbox_instructions_int" \ + 10 75 "$4" 2>MCdialog.out + then + answer="`cat MCdialog.out`" + answer="${answer:-$3}" + + # Semantics of + and ? in GNU expr changed, so + # we avoid them: + if expr "$answer" : '0$' '|' "$answer" : '[1-9][0-9]*$' '|' "$answer" : '-[1-9][0-9]*$' >/dev/null + then + eval $2="$answer" + else + eval $2="$3" + echo -en "\007" + ${DIALOG} --backtitle "$backtitle" \ + --infobox "You have made an invalid entry." 3 43 + sleep 2 + fi + + break + fi + + help "$2" "$1" + done +} + +# +# Create a dialog for entering a hexadecimal into a kernel option. +# +function l_hex () { + while true + do + if $DIALOG --title "$1" \ + --backtitle "$backtitle" \ + --inputbox "$inputbox_instructions_hex" \ + 10 75 "$4" 2>MCdialog.out + then + answer="`cat MCdialog.out`" + answer="${answer:-$3}" + answer="${answer##*[x,X]}" + + if expr "$answer" : '[0-9a-fA-F][0-9a-fA-F]*$' >/dev/null + then + eval $2="$answer" + else + eval $2="$3" + echo -en "\007" + ${DIALOG} --backtitle "$backtitle" \ + --infobox "You have made an invalid entry." 3 43 + sleep 2 + fi + + break + fi + + help "$2" "$1" + done +} + +# +# Create a dialog for entering a string into a kernel option. +# +function l_string () { + while true + do + if $DIALOG --title "$1" \ + --backtitle "$backtitle" \ + --inputbox "$inputbox_instructions_string" \ + 10 75 "$4" 2>MCdialog.out + then + answer="`cat MCdialog.out`" + answer="${answer:-$3}" + + # + # Someone may add a nice check for the entered + # string here... + # + eval $2=\"$answer\" + + break + fi + + help "$2" "$1" + done +} + + +# +# Handle a one-of-many choice list. +# +function l_choice () { + # + # Need to remember params cause they're gonna get reset. + # + title="$1" + choices="$2" + current="$3" + chosen= + + # + # Scan current value of choices and set radiolist switches. + # + list= + set -- $choices + firstchoice=$2 + while [ -n "$2" ] + do + case "$1" in + "$current"*) if [ -z "$chosen" ]; then + list="$list $2 $1 ON " + chosen=1 + else + list="$list $2 $1 OFF " + fi ;; + *) list="$list $2 $1 OFF " ;; + esac + + shift ; shift + done + + while true + do + if $DIALOG --title "$title" \ + --backtitle "$backtitle" \ + --radiolist "$radiolist_instructions" \ + 15 70 6 $list 2>MCdialog.out + then + choice=`cat MCdialog.out` + break + fi + + help "$firstchoice" "$title" + done + + # + # Now set the boolean value of each option based on + # the selection made from the radiolist. + # + set -- $choices + while [ -n "$2" ] + do + if [ "$2" = "$choice" ] + then + eval $2="y" + else + eval $2="n" + fi + + shift ; shift + done +} + +# +# Call awk, and watch for error codes, etc. +# +function callawk () { +awk "$1" || echo "Awk died with error code $?. Giving up." || exit 1 +} + +# +# A faster awk based recursive parser. (I hope) +# +function parser1 () { +callawk ' +BEGIN { + menu_no = 0 + comment_is_option = 0 + parser("'$CONFIG_IN'","MCmenu0") +} + +function parser(ifile,menu) { + + while (getline >menu + + newmenu = sprintf("MCmenu%d", menu_no); + printf( "function MCmenu%s () {\n"\ + "default=$1\n"\ + "menu_name %s\n",\ + menu_no, $0) >newmenu + + parser(ifile, newmenu) + } + else if ($0 ~ /^#|\$MAKE|mainmenu_name/) { + printf("") >>menu + } + else if ($1 ~ "endmenu") { + printf("}\n") >>menu + return + } + else if ($1 == "source") { + parser($2,menu) + } + else { + print >>menu + } + } +}' +} + +# +# Secondary parser for single menu mode. +# +function parser2 () { +callawk ' +BEGIN { + parser("'$CONFIG_IN'","MCmenu0") +} + +function parser(ifile,menu) { + + while (getline >menu + } + else if ($1 ~ /mainmenu_option|endmenu/) { + printf("") >>menu + } + else if ($1 == "source") { + parser($2,menu) + } + else { + print >>menu + } + } +}' +} + +# +# Parse all the config.in files into mini scripts. +# +function parse_config_files () { + rm -f MCmenu* + + echo "function MCmenu0 () {" >MCmenu0 + echo 'default=$1' >>MCmenu0 + echo "menu_name 'Main Menu'" >>MCmenu0 + + if [ "_$single_menu_mode" = "_TRUE" ] + then + parser2 + else + parser1 + fi + + echo "comment ''" >>MCmenu0 + echo "g_alt_config" >>MCmenu0 + echo "s_alt_config" >>MCmenu0 + + echo "}" >>MCmenu0 + + # + # These mini scripts must be sourced into the current + # environment in order for all of this to work. Leaving + # them on the disk as executables screws up the recursion + # in activate_menu(), among other things. Once they are + # sourced we can discard them. + # + for i in MCmenu* + do + echo -n "." + source ./$i + done + rm -f MCmenu* +} + +# +# This is the menu tree's bootstrap. +# +# Executes the parsed menus on demand and creates a set of functions, +# one per configuration option. These functions will in turn execute +# dialog commands or recursively call other menus. +# +function activate_menu () { + rm -f lxdialog.scrltmp + while true + do + comment_ctr=0 #So comment lines get unique tags + + $1 "$default" 2> MCerror #Create the lxdialog menu & functions + + if [ "$?" != "0" ] + then + clear + cat < /' MCerror + cat <. + +EOM + cleanup + exit 1 + fi + rm -f MCerror + + . ./MCradiolists #Source the menu's functions + + . ./MCmenu 2>MCdialog.out #Activate the lxdialog menu + ret=$? + + read selection "*|*"alt_config"*) + show_readme ;; + *) + eval help $selection ;; + esac + ;; + 255|1) + break + ;; + 139) + stty sane + clear + cat < + +EOM + cleanup + exit 139 + ;; + esac + done +} + +# +# Create a menu item to load an alternate configuration file. +# +g_alt_config () { + echo -n "get_alt_config 'Load an Alternate Configuration File' "\ + >>MCmenu +} + +# +# Get alternate config file name and load the +# configuration from it. +# +get_alt_config () { + set -f ## Switch file expansion OFF + + while true + do + ALT_CONFIG="${ALT_CONFIG:-$DEFAULTS}" + + $DIALOG --backtitle "$backtitle" \ + --inputbox "\ +Enter the name of the configuration file you wish to load. \ +Accept the name shown to restore the configuration you \ +last retrieved. Leave blank to abort."\ + 11 55 "$ALT_CONFIG" 2>MCdialog.out + + if [ "$?" = "0" ] + then + ALT_CONFIG=`cat MCdialog.out` + + [ "_" = "_$ALT_CONFIG" ] && break + + if eval [ -r "$ALT_CONFIG" ] + then + eval load_config_file "$ALT_CONFIG" + break + else + echo -ne "\007" + $DIALOG --backtitle "$backtitle" \ + --infobox "File does not exist!" 3 38 + sleep 2 + fi + else + cat <help.out + +For various reasons, one may wish to keep several different Aversive +configurations available on a single machine. + +If you have saved a previous configuration in a file other than the +Aversive's default, entering the name of the file here will allow you +to modify that configuration. + +If you are uncertain, then you have probably never used alternate +configuration files. You should therefor leave this blank to abort. + +EOM + $DIALOG --backtitle "$backtitle"\ + --title "Load Alternate Configuration"\ + --textbox help.out $ROWS $COLS + fi + done + + set +f ## Switch file expansion ON + rm -f help.out MCdialog.out +} + +# +# Create a menu item to store an alternate config file. +# +s_alt_config () { + echo -n "save_alt_config 'Save Configuration to an Alternate File' "\ + >>MCmenu +} + +# +# Get an alternate config file name and save the current +# configuration to it. +# +save_alt_config () { + set -f ## Switch file expansion OFF + + while true + do + $DIALOG --backtitle "$backtitle" \ + --inputbox "\ +Enter a filename to which this configuration should be saved \ +as an alternate. Leave blank to abort."\ + 10 55 "$ALT_CONFIG" 2>MCdialog.out + + if [ "$?" = "0" ] + then + ALT_CONFIG=`cat MCdialog.out` + + [ "_" = "_$ALT_CONFIG" ] && break + + if eval touch $ALT_CONFIG 2>/dev/null + then + eval save_configuration $ALT_CONFIG + load_functions ## RELOAD + break + else + echo -ne "\007" + $DIALOG --backtitle "$backtitle" \ + --infobox "Can't create file! Probably a nonexistent directory." 3 60 + sleep 2 + fi + else + cat <help.out + +For various reasons, one may wish to keep different kernel +configurations available on a single machine. + +Entering a file name here will allow you to later retrieve, modify +and use the current configuration as an alternate to whatever +configuration options you have selected at that time. + +If you are uncertain what all this means then you should probably +leave this blank. +EOM + $DIALOG --backtitle "$backtitle"\ + --title "Save Alternate Configuration"\ + --textbox help.out $ROWS $COLS + fi + done + + set +f ## Switch file expansion ON + rm -f help.out MCdialog.out +} + +# +# Load config options from a file. +# Converts all "# OPTION is not set" lines to "OPTION=n" lines +# +function load_config_file () { + awk ' + /# .* is not set.*/ { printf("%s=n\n", $2) } + ! /# .* is not set.*/ { print } + ' $1 >.tmpconfig + + source ./.tmpconfig + rm -f .tmpconfig +} + +# +# Just what it says. +# +save_configuration () { + echo + echo -n "Saving your Aversive configuration." + + # + # Now, let's redefine the configuration functions for final + # output to the config files. + # + # Nested function definitions, YIPEE! + # + function bool () { + set_x_info "$2" "n" + eval define_bool "$2" "$x" + } + + function dep_bool () { + set_x_info "$2" "n" + var="$2" + shift 2 + while [ $# -gt 0 ]; do + if [ "$1" = y ]; then + shift + else + x=n; shift $# + fi + done + define_bool "$var" "$x" + } + + function dep_mbool () { + set_x_info "$2" "n" + var="$2" + shift 2 + while [ $# -gt 0 ]; do + if [ "$1" = y -o "$1" = m ]; then + shift + else + x=n; shift $# + fi + done + define_bool "$var" "$x" + } + + function int () { + set_x_info "$2" "$3" + echo "$2=$x" >>$CONFIG + echo "#define $2 ($x)" >>$CONFIG_H + } + + function hex () { + set_x_info "$2" "$3" + echo "$2=$x" >>$CONFIG + echo "#define $2 0x${x##*[x,X]}" >>$CONFIG_H + } + + function string () { + set_x_info "$2" "$3" + echo "$2=\"$x\"" >>$CONFIG + echo "#define $2 \"$x\"" >>$CONFIG_H + } + + function define_hex () { + eval $1="$2" + echo "$1=$2" >>$CONFIG + echo "#define $1 0x${2##*[x,X]}" >>$CONFIG_H + } + + function define_int () { + eval $1="$2" + echo "$1=$2" >>$CONFIG + echo "#define $1 ($2)" >>$CONFIG_H + } + + function define_string () { + eval $1="$2" + echo "$1=\"$2\"" >>$CONFIG + echo "#define $1 \"$2\"" >>$CONFIG_H + } + + function define_bool () { + eval $1="$2" + + case "$2" in + y) + echo "$1=y" >>$CONFIG + echo "#define $1 1" >>$CONFIG_H + ;; + + n) + echo "# $1 is not set" >>$CONFIG + echo "#undef $1" >>$CONFIG_H + ;; + esac + } + + function choice () { + # + # Find the first choice that's already set to 'y' + # + choices="$2" + default="$3" + current= + chosen= + + set -- $choices + while [ -n "$2" ] + do + if eval [ "_\$$2" = "_y" ] + then + current=$1 + break + fi + shift ; shift + done + + # + # Use the default if none were set. + # + : ${current:=$default} + + # + # Output all choices (to be compatible with other configs). + # + set -- $choices + while [ -n "$2" ] + do + case "$1" in + "$current"*) if [ -z "$chosen" ]; then + define_bool "$2" "y" + chosen=1 + else + define_bool "$2" "n" + fi ;; + *) define_bool "$2" "n" ;; + esac + shift ; shift + done + } + + function mainmenu_name () { + : + } + + function mainmenu_option () { + comment_is_option=TRUE + } + + function endmenu () { + : + } + + function comment () { + if [ "$comment_is_option" ] + then + comment_is_option= + echo >>$CONFIG + echo "#" >>$CONFIG + echo "# $1" >>$CONFIG + echo "#" >>$CONFIG + + echo >>$CONFIG_H + echo "/*" >>$CONFIG_H + echo " * $1" >>$CONFIG_H + echo " */" >>$CONFIG_H + fi + } + + echo -n "." + + DEF_CONFIG="${1:-.config}" + #DEF_CONFIG_H="include/linux/autoconf.h" + DEF_CONFIG_H="autoconf.h" + + CONFIG=.tmpconfig + CONFIG_H=.tmpconfig.h + + echo "#" >$CONFIG + echo "# Automatically generated by make menuconfig: don't edit" >>$CONFIG + echo "#" >>$CONFIG + + echo "/*" >$CONFIG_H + echo " * Automatically generated by make menuconfig: don't edit" >>$CONFIG_H + echo " */" >>$CONFIG_H + echo "#define AUTOCONF_INCLUDED" >> $CONFIG_H + + echo -n "." + if . $CONFIG_IN >>.menuconfig.log 2>&1 + then + if [ "$DEF_CONFIG" = ".config" -a -d `dirname $DEF_CONFIG_H` ] + then + mv $CONFIG_H $DEF_CONFIG_H + fi + + if [ -f "$DEF_CONFIG" ] + then + rm -f ${DEF_CONFIG}.old + mv $DEF_CONFIG ${DEF_CONFIG}.old + fi + + mv $CONFIG $DEF_CONFIG + + return 0 + else + return 1 + fi +} + +# +# Remove temporary files +# +cleanup () { + cleanup1 + cleanup2 +} + +cleanup1 () { + rm -f MCmenu* MCradiolists MCdialog.out help.out +} + +cleanup2 () { + rm -f .tmpconfig .tmpconfig.h +} + +set_geometry () { + # Some distributions export these with incorrect values + # which can really screw up some ncurses programs. + LINES= COLUMNS= + + ROWS=${1:-24} COLS=${2:-80} + + # Just in case the nasty rlogin bug returns. + # + [ $ROWS = 0 ] && ROWS=24 + [ $COLS = 0 ] && COLS=80 + + if [ $ROWS -lt 19 -o $COLS -lt 80 ] + then + echo -e "\n\007Your display is too small to run Menuconfig!" + echo "It must be at least 19 lines by 80 columns." + exit 0 + fi + + ROWS=$((ROWS-4)) COLS=$((COLS-5)) +} + + +set_geometry `stty size 2>/dev/null` + +menu_instructions="\ +Arrow keys navigate the menu. \ + selects submenus --->. \ +Highlighted letters are hotkeys. \ +Pressing includes, excludes. \ +Press to exit, for Help. \ +Legend: [*] built-in [ ] excluded " + +radiolist_instructions="\ +Use the arrow keys to navigate this window or \ +press the hotkey of the item you wish to select \ +followed by the . +Press for additional information about this option." + +inputbox_instructions_int="\ +Please enter a decimal value. \ +Fractions will not be accepted. \ +Use the key to move from the input field to the buttons below it." + +inputbox_instructions_hex="\ +Please enter a hexadecimal value. \ +Use the key to move from the input field to the buttons below it." + +inputbox_instructions_string="\ +Please enter a string value. \ +Use the key to move from the input field to the buttons below it." + +DIALOG="$AVERSIVE_DIR/config/scripts/lxdialog/lxdialog" + +kernel_version="${VERSIONPKG}" + +backtitle="Aversive Configuration" + +trap "cleanup ; exit 1" 1 2 15 + + +# +# Locate default files. +# +CONFIG_IN=./config.in +if [ "$1" != "" ] ; then + CONFIG_IN=$1 +fi + +DEFAULTS=$AVERSIVE_DIR/config/.config +if [ -f .config ]; then + DEFAULTS=.config +fi + +if [ -f $DEFAULTS ] +then + echo "Using defaults found in" $DEFAULTS + load_config_file $DEFAULTS +else + echo "No defaults found" +fi + +if [ -z "$HELP_FILE" ] +then + HELP_FILE="Documentation/Configure.help" +fi + +# Fresh new log. +>.menuconfig.log + +# Load the functions used by the config.in files. +echo -n "Preparing scripts: functions" +load_functions + +if [ ! -e $CONFIG_IN ] +then + echo "Your main config.in file ($CONFIG_IN) does not exist" + exit 1 +fi + +if [ ! -x $DIALOG ] +then + echo "Your lxdialog utility does not exist" + exit 1 +fi + +# +# Read config.in files and parse them into one shell function per menu. +# +echo -n ", parsing" +parse_config_files $CONFIG_IN + +echo "done." +# +# Start the ball rolling from the top. +# +activate_menu MCmenu0 + +# +# All done! +# +cleanup1 + +# +# Confirm and Save +# +if $DIALOG --backtitle "$backtitle" \ + --yesno "Do you wish to save your new configuration?" 5 60 +then + save_configuration + $AVERSIVE_DIR/config/generate_aversive_config .config .aversive_conf + echo + echo + echo "*** End of Aversive configuration." + echo "*** Next, you should run 'make clean', then 'make'" + echo +else + echo + echo + echo Your configuration changes were NOT saved. + echo +fi + + +# Remove log if empty. +if [ ! -s .menuconfig.log ] ; then + rm -f .menuconfig.log +fi + +exit 0 diff --git a/config/scripts/README.Menuconfig b/config/scripts/README.Menuconfig new file mode 100644 index 0000000..5c28589 --- /dev/null +++ b/config/scripts/README.Menuconfig @@ -0,0 +1,194 @@ +Menuconfig gives the Linux kernel configuration a long needed face +lift. Featuring text based color menus and dialogs, it does not +require X Windows. With this utility you can easily select a kernel +option to modify without sifting through 100 other options. + +Overview +-------- +Some kernel features may be built directly into the kernel. +Some may be made into loadable runtime modules. Some features +may be completely removed altogether. There are also certain +kernel parameters which are not really features, but must be +entered in as decimal or hexadecimal numbers or possibly text. + +Menu items beginning with [*], or [ ] represent features +configured to be built in, modularized or removed respectively. +Pointed brackets <> represent module capable features. + more... + +To change any of these features, highlight it with the cursor +keys and press to build it in, to make it a module or + to removed it. You may also press the to cycle +through the available options (ie. Y->N->M->Y). + +Items beginning with numbers or other text within parenthesis can +be changed by highlighting the item and pressing . Then +enter the new parameter into the dialog box that pops up. + + +Some additional keyboard hints: + +Menus +---------- +o Use the Up/Down arrow keys (cursor keys) to highlight the item + you wish to change or submenu wish to select and press . + Submenus are designated by "--->". + + Shortcut: Press the option's highlighted letter (hotkey). + Pressing a hotkey more than once will sequence + through all visible items which use that hotkey. + + You may also use the and keys to scroll + unseen options into view. + +o To exit a menu use the cursor keys to highlight the button + and press . + + Shortcut: Press or or if there is no hotkey + using those letters. You may press a single , but + there is a delayed response which you may find annoying. + + Also, the and cursor keys will cycle between and + + + +Data Entry +----------- +o Enter the requested information and press + If you are entering hexadecimal values, it is not necessary to + add the '0x' prefix to the entry. + +o For help, use the or cursor keys to highlight the help option + and press . You can try as well. + + +Text Box (Help Window) +-------- +o Use the cursor keys to scroll up/down/left/right. The VI editor + keys h,j,k,l function here as do and for those + who are familiar with less and lynx. + +o Press , , or to exit. + + +Final Acceptance +---------------- +With the exception of the old style sound configuration, +YOUR CHANGES ARE NOT FINAL. You will be given a last chance to +confirm them prior to exiting Menuconfig. + +If Menuconfig quits with an error while saving your configuration, +you may look in the file /usr/src/linux/.menuconfig.log for +information which may help you determine the cause. + +Alternate Configuration Files +----------------------------- +Menuconfig supports the use of alternate configuration files for +those who, for various reasons, find it necessary to switch +between different kernel configurations. + +At the end of the main menu you will find two options. One is +for saving the current configuration to a file of your choosing. +The other option is for loading a previously saved alternate +configuration. + +Even if you don't use alternate configuration files, but you +find during a Menuconfig session that you have completely messed +up your settings, you may use the "Load Alternate..." option to +restore your previously saved settings from ".config" without +restarting Menuconfig. + +Other information +----------------- +The windowing utility, lxdialog, will only be rebuilt if your kernel +source tree is fresh, or changes are patched into it via a kernel +patch or you do 'make mrproper'. If changes to lxdialog are patched +in, most likely the rebuild time will be short. You may force a +complete rebuild of lxdialog by changing to it's directory and doing +'make clean all' + +If you use Menuconfig in an XTERM window make sure you have your +$TERM variable set to point to a xterm definition which supports color. +Otherwise, Menuconfig will look rather bad. Menuconfig will not +display correctly in a RXVT window because rxvt displays only one +intensity of color, bright. + +Menuconfig will display larger menus on screens or xterms which are +set to display more than the standard 25 row by 80 column geometry. +In order for this to work, the "stty size" command must be able to +display the screen's current row and column geometry. I STRONGLY +RECOMMEND that you make sure you do NOT have the shell variables +LINES and COLUMNS exported into your environment. Some distributions +export those variables via /etc/profile. Some ncurses programs can +become confused when those variables (LINES & COLUMNS) don't reflect +the true screen size. + + +NOTICE: lxdialog requires the ncurses libraries to compile. If you + don't already have ncurses you really should get it. + + The makefile for lxdialog attempts to find your ncurses + header file. Although it should find the header for older + versions of ncurses, it is probably a good idea to get the + latest ncurses anyway. + + If you have upgraded your ncurses libraries, MAKE SURE you + remove the old ncurses header files. If you don't you + will most certainly get a segmentation fault. + +WARNING: It is not recommended that you change any defines in + lxdialog's header files. If you have a grayscale display and + are brave, you may tinker with color.h to tune the colors to + your preference. + +COMPATIBILITY ISSUE: + There have been some compatibility problems reported with + older versions of bash and sed. I am trying to work these + out but it is preferable that you upgrade those utilities. + + +******** IMPORTANT, OPTIONAL ALTERNATE PERSONALITY AVAILABLE ******** +******** ******** +If you prefer to have all of the kernel options listed in a single +menu, rather than the default multimenu hierarchy, you may edit the +Menuconfig script and change the line "single_menu_mode=" to +"single_menu_mode=TRUE". + +This mode is not recommended unless you have a fairly fast machine. +********************************************************************* + + +Propaganda +---------- +The windowing support utility (lxdialog) is a VERY modified version of +the dialog utility by Savio Lam . Although lxdialog +is significantly different from dialog, I have left Savio's copyrights +intact. Please DO NOT contact Savio with questions about lxdialog. +He will not be able to assist. + +William Roadcap was the original author of Menuconfig. +Michael Elizabeth Chastain is the current maintainer. + + diff --git a/config/scripts/lxdialog/BIG.FAT.WARNING b/config/scripts/lxdialog/BIG.FAT.WARNING new file mode 100644 index 0000000..a8999d8 --- /dev/null +++ b/config/scripts/lxdialog/BIG.FAT.WARNING @@ -0,0 +1,4 @@ +This is NOT the official version of dialog. This version has been +significantly modified from the original. It is for use by the Linux +kernel configuration script. Please do not bother Savio Lam with +questions about this program. diff --git a/config/scripts/lxdialog/CVS/Entries b/config/scripts/lxdialog/CVS/Entries new file mode 100644 index 0000000..152c669 --- /dev/null +++ b/config/scripts/lxdialog/CVS/Entries @@ -0,0 +1,13 @@ +/BIG.FAT.WARNING/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/Makefile/1.2.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/checklist.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/colors.h/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/dialog.h/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/inputbox.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/lxdialog.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/menubox.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/msgbox.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/textbox.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/util.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/yesno.c/1.1.10.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +D diff --git a/config/scripts/lxdialog/CVS/Repository b/config/scripts/lxdialog/CVS/Repository new file mode 100644 index 0000000..3de016f --- /dev/null +++ b/config/scripts/lxdialog/CVS/Repository @@ -0,0 +1 @@ +aversive/config/scripts/lxdialog diff --git a/config/scripts/lxdialog/CVS/Root b/config/scripts/lxdialog/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/config/scripts/lxdialog/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/config/scripts/lxdialog/CVS/Tag b/config/scripts/lxdialog/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/config/scripts/lxdialog/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/config/scripts/lxdialog/CVS/Template b/config/scripts/lxdialog/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/config/scripts/lxdialog/Makefile b/config/scripts/lxdialog/Makefile new file mode 100644 index 0000000..ed8d17c --- /dev/null +++ b/config/scripts/lxdialog/Makefile @@ -0,0 +1,46 @@ +HOSTCFLAGS += -DLOCALE +LIBS = -lncurses + +ifeq (/usr/include/ncurses/ncurses.h, $(wildcard /usr/include/ncurses/ncurses.h)) + HOSTCFLAGS += -I/usr/include/ncurses -DCURSES_LOC="" +else +ifeq (/usr/include/ncurses/curses.h, $(wildcard /usr/include/ncurses/curses.h)) + HOSTCFLAGS += -I/usr/include/ncurses -DCURSES_LOC="" +else +ifeq (/usr/include/ncurses.h, $(wildcard /usr/include/ncurses.h)) + HOSTCFLAGS += -DCURSES_LOC="" +else + HOSTCFLAGS += -DCURSES_LOC="" +endif +endif +endif + + +OBJS = checklist.o menubox.o textbox.o yesno.o inputbox.o \ + util.o lxdialog.o msgbox.o + +%.o: %.c + $(HOSTCC) $(HOSTCFLAGS) -c -o $@ $< + +all: ncurses lxdialog + +lxdialog: $(OBJS) + $(HOSTCC) -o lxdialog $(OBJS) $(LIBS) + +ncurses: + @echo "main() {}" > lxtemp.c + @if $(HOSTCC) -lncurses lxtemp.c ; then \ + rm -f lxtemp.c a.out; \ + else \ + rm -f lxtemp.c; \ + echo -e "\007" ;\ + echo ">> Unable to find the Ncurses libraries." ;\ + echo ">>" ;\ + echo ">> You must have Ncurses installed in order" ;\ + echo ">> to use 'make menuconfig'" ;\ + echo ;\ + exit 1 ;\ + fi + +clean: + rm -f core *.o *~ lxdialog diff --git a/config/scripts/lxdialog/checklist.c b/config/scripts/lxdialog/checklist.c new file mode 100644 index 0000000..a1bf1f7 --- /dev/null +++ b/config/scripts/lxdialog/checklist.c @@ -0,0 +1,359 @@ +/* + * checklist.c -- implements the checklist box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * Stuart Herbert - S.Herbert@sheffield.ac.uk: radiolist extension + * Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +static int list_width, check_x, item_x, checkflag; + +/* + * Print list item + */ +static void +print_item (WINDOW * win, const char *item, int status, + int choice, int selected) +{ + int i; + + /* Clear 'residue' of last item */ + wattrset (win, menubox_attr); + wmove (win, choice, 0); + for (i = 0; i < list_width; i++) + waddch (win, ' '); + + wmove (win, choice, check_x); + wattrset (win, selected ? check_selected_attr : check_attr); + if (checkflag == FLAG_CHECK) + wprintw (win, "[%c]", status ? 'X' : ' '); + else + wprintw (win, "(%c)", status ? 'X' : ' '); + + wattrset (win, selected ? tag_selected_attr : tag_attr); + mvwaddch(win, choice, item_x, item[0]); + wattrset (win, selected ? item_selected_attr : item_attr); + waddstr (win, (char *)item+1); +} + +/* + * Print the scroll indicators. + */ +static void +print_arrows (WINDOW * win, int choice, int item_no, int scroll, + int y, int x, int height) +{ + wmove(win, y, x); + + if (scroll > 0) { + wattrset (win, uarrow_attr); + waddch (win, ACS_UARROW); + waddstr (win, "(-)"); + } + else { + wattrset (win, menubox_attr); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + } + + y = y + height + 1; + wmove(win, y, x); + + if ((height < item_no) && (scroll + choice < item_no - 1)) { + wattrset (win, darrow_attr); + waddch (win, ACS_DARROW); + waddstr (win, "(+)"); + } + else { + wattrset (win, menubox_border_attr); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + } +} + +/* + * Display the termination buttons + */ +static void +print_buttons( WINDOW *dialog, int height, int width, int selected) +{ + int x = width / 2 - 11; + int y = height - 2; + + print_button (dialog, "Select", y, x, selected == 0); + print_button (dialog, " Help ", y, x + 14, selected == 1); + + wmove(dialog, y, x+1 + 14*selected); + wrefresh (dialog); +} + +/* + * Display a dialog box with a list of options that can be turned on or off + * The `flag' parameter is used to select between radiolist and checklist. + */ +int +dialog_checklist (const char *title, const char *prompt, int height, int width, + int list_height, int item_no, const char * const * items, int flag) + +{ + int i, x, y, box_x, box_y; + int key = 0, button = 0, choice = 0, scroll = 0, max_choice, *status; + WINDOW *dialog, *list; + + checkflag = flag; + + /* Allocate space for storing item on/off status */ + if ((status = malloc (sizeof (int) * item_no)) == NULL) { + endwin (); + fprintf (stderr, + "\nCan't allocate memory in dialog_checklist().\n"); + exit (-1); + } + + /* Initializes status */ + for (i = 0; i < item_no; i++) { + status[i] = !strcasecmp (items[i * 3 + 2], "on"); + if (!choice && status[i]) + choice = i; + } + + max_choice = MIN (list_height, item_no); + + /* center dialog box on screen */ + x = (COLS - width) / 2; + y = (LINES - height) / 2; + + draw_shadow (stdscr, y, x, height, width); + + dialog = newwin (height, width, y, x); + keypad (dialog, TRUE); + + draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); + wattrset (dialog, border_attr); + mvwaddch (dialog, height-3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch (dialog, ACS_HLINE); + wattrset (dialog, dialog_attr); + waddch (dialog, ACS_RTEE); + + if (title != NULL && strlen(title) >= width-2 ) { + /* truncate long title -- mec */ + char * title2 = malloc(width-2+1); + memcpy( title2, title, width-2 ); + title2[width-2] = '\0'; + title = title2; + } + + if (title != NULL) { + wattrset (dialog, title_attr); + mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); + waddstr (dialog, (char *)title); + waddch (dialog, ' '); + } + + wattrset (dialog, dialog_attr); + print_autowrap (dialog, prompt, width - 2, 1, 3); + + list_width = width - 6; + box_y = height - list_height - 5; + box_x = (width - list_width) / 2 - 1; + + /* create new window for the list */ + list = subwin (dialog, list_height, list_width, y+box_y+1, x+box_x+1); + + keypad (list, TRUE); + + /* draw a box around the list items */ + draw_box (dialog, box_y, box_x, list_height + 2, list_width + 2, + menubox_border_attr, menubox_attr); + + /* Find length of longest item in order to center checklist */ + check_x = 0; + for (i = 0; i < item_no; i++) + check_x = MAX (check_x, + strlen (items[i * 3 + 1]) + 4); + + check_x = (list_width - check_x) / 2; + item_x = check_x + 4; + + if (choice >= list_height) { + scroll = choice - list_height + 1; + choice -= scroll; + } + + /* Print the list */ + for (i = 0; i < max_choice; i++) { + print_item (list, items[(scroll+i) * 3 + 1], + status[i+scroll], i, i == choice); + } + + wnoutrefresh (list); + + print_arrows(dialog, choice, item_no, scroll, + box_y, box_x + check_x + 5, list_height); + + print_buttons(dialog, height, width, 0); + + while (key != ESC) { + key = wgetch (dialog); + + for (i = 0; i < max_choice; i++) + if (toupper(key) == toupper(items[(scroll+i)*3+1][0])) + break; + + + if ( i < max_choice || key == KEY_UP || key == KEY_DOWN || + key == '+' || key == '-' ) { + if (key == KEY_UP || key == '-') { + if (!choice) { + if (!scroll) + continue; + /* Scroll list down */ + if (list_height > 1) { + /* De-highlight current first item */ + print_item (list, items[scroll * 3 + 1], + status[scroll], 0, FALSE); + scrollok (list, TRUE); + wscrl (list, -1); + scrollok (list, FALSE); + } + scroll--; + print_item (list, items[scroll * 3 + 1], + status[scroll], 0, TRUE); + wnoutrefresh (list); + + print_arrows(dialog, choice, item_no, scroll, + box_y, box_x + check_x + 5, list_height); + + wrefresh (dialog); + + continue; /* wait for another key press */ + } else + i = choice - 1; + } else if (key == KEY_DOWN || key == '+') { + if (choice == max_choice - 1) { + if (scroll + choice >= item_no - 1) + continue; + /* Scroll list up */ + if (list_height > 1) { + /* De-highlight current last item before scrolling up */ + print_item (list, items[(scroll + max_choice - 1) * 3 + 1], + status[scroll + max_choice - 1], + max_choice - 1, FALSE); + scrollok (list, TRUE); + scroll (list); + scrollok (list, FALSE); + } + scroll++; + print_item (list, items[(scroll + max_choice - 1) * 3 + 1], + status[scroll + max_choice - 1], + max_choice - 1, TRUE); + wnoutrefresh (list); + + print_arrows(dialog, choice, item_no, scroll, + box_y, box_x + check_x + 5, list_height); + + wrefresh (dialog); + + continue; /* wait for another key press */ + } else + i = choice + 1; + } + if (i != choice) { + /* De-highlight current item */ + print_item (list, items[(scroll + choice) * 3 + 1], + status[scroll + choice], choice, FALSE); + /* Highlight new item */ + choice = i; + print_item (list, items[(scroll + choice) * 3 + 1], + status[scroll + choice], choice, TRUE); + wnoutrefresh (list); + wrefresh (dialog); + } + continue; /* wait for another key press */ + } + switch (key) { + case 'H': + case 'h': + case '?': + delwin (dialog); + free (status); + return 1; + case TAB: + case KEY_LEFT: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 1 : (button > 1 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh (dialog); + break; + case 'S': + case 's': + case ' ': + case '\n': + if (!button) { + if (flag == FLAG_CHECK) { + status[scroll + choice] = !status[scroll + choice]; + wmove (list, choice, check_x); + wattrset (list, check_selected_attr); + wprintw (list, "[%c]", status[scroll + choice] ? 'X' : ' '); + } else { + if (!status[scroll + choice]) { + for (i = 0; i < item_no; i++) + status[i] = 0; + status[scroll + choice] = 1; + for (i = 0; i < max_choice; i++) + print_item (list, items[(scroll + i) * 3 + 1], + status[scroll + i], i, i == choice); + } + } + wnoutrefresh (list); + wrefresh (dialog); + + for (i = 0; i < item_no; i++) { + if (status[i]) { + if (flag == FLAG_CHECK) { + fprintf (stderr, "\"%s\" ", items[i * 3]); + } else { + fprintf (stderr, "%s", items[i * 3]); + } + + } + } + } + delwin (dialog); + free (status); + return button; + case 'X': + case 'x': + key = ESC; + case ESC: + break; + } + } + + delwin (dialog); + free (status); + return -1; /* ESC pressed */ +} diff --git a/config/scripts/lxdialog/colors.h b/config/scripts/lxdialog/colors.h new file mode 100644 index 0000000..d34dd37 --- /dev/null +++ b/config/scripts/lxdialog/colors.h @@ -0,0 +1,161 @@ +/* + * colors.h -- color attribute definitions + * + * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +/* + * Default color definitions + * + * *_FG = foreground + * *_BG = background + * *_HL = highlight? + */ +#define SCREEN_FG COLOR_CYAN +#define SCREEN_BG COLOR_BLUE +#define SCREEN_HL TRUE + +#define SHADOW_FG COLOR_BLACK +#define SHADOW_BG COLOR_BLACK +#define SHADOW_HL TRUE + +#define DIALOG_FG COLOR_BLACK +#define DIALOG_BG COLOR_WHITE +#define DIALOG_HL FALSE + +#define TITLE_FG COLOR_YELLOW +#define TITLE_BG COLOR_WHITE +#define TITLE_HL TRUE + +#define BORDER_FG COLOR_WHITE +#define BORDER_BG COLOR_WHITE +#define BORDER_HL TRUE + +#define BUTTON_ACTIVE_FG COLOR_WHITE +#define BUTTON_ACTIVE_BG COLOR_BLUE +#define BUTTON_ACTIVE_HL TRUE + +#define BUTTON_INACTIVE_FG COLOR_BLACK +#define BUTTON_INACTIVE_BG COLOR_WHITE +#define BUTTON_INACTIVE_HL FALSE + +#define BUTTON_KEY_ACTIVE_FG COLOR_WHITE +#define BUTTON_KEY_ACTIVE_BG COLOR_BLUE +#define BUTTON_KEY_ACTIVE_HL TRUE + +#define BUTTON_KEY_INACTIVE_FG COLOR_RED +#define BUTTON_KEY_INACTIVE_BG COLOR_WHITE +#define BUTTON_KEY_INACTIVE_HL FALSE + +#define BUTTON_LABEL_ACTIVE_FG COLOR_YELLOW +#define BUTTON_LABEL_ACTIVE_BG COLOR_BLUE +#define BUTTON_LABEL_ACTIVE_HL TRUE + +#define BUTTON_LABEL_INACTIVE_FG COLOR_BLACK +#define BUTTON_LABEL_INACTIVE_BG COLOR_WHITE +#define BUTTON_LABEL_INACTIVE_HL TRUE + +#define INPUTBOX_FG COLOR_BLACK +#define INPUTBOX_BG COLOR_WHITE +#define INPUTBOX_HL FALSE + +#define INPUTBOX_BORDER_FG COLOR_BLACK +#define INPUTBOX_BORDER_BG COLOR_WHITE +#define INPUTBOX_BORDER_HL FALSE + +#define SEARCHBOX_FG COLOR_BLACK +#define SEARCHBOX_BG COLOR_WHITE +#define SEARCHBOX_HL FALSE + +#define SEARCHBOX_TITLE_FG COLOR_YELLOW +#define SEARCHBOX_TITLE_BG COLOR_WHITE +#define SEARCHBOX_TITLE_HL TRUE + +#define SEARCHBOX_BORDER_FG COLOR_WHITE +#define SEARCHBOX_BORDER_BG COLOR_WHITE +#define SEARCHBOX_BORDER_HL TRUE + +#define POSITION_INDICATOR_FG COLOR_YELLOW +#define POSITION_INDICATOR_BG COLOR_WHITE +#define POSITION_INDICATOR_HL TRUE + +#define MENUBOX_FG COLOR_BLACK +#define MENUBOX_BG COLOR_WHITE +#define MENUBOX_HL FALSE + +#define MENUBOX_BORDER_FG COLOR_WHITE +#define MENUBOX_BORDER_BG COLOR_WHITE +#define MENUBOX_BORDER_HL TRUE + +#define ITEM_FG COLOR_BLACK +#define ITEM_BG COLOR_WHITE +#define ITEM_HL FALSE + +#define ITEM_SELECTED_FG COLOR_WHITE +#define ITEM_SELECTED_BG COLOR_BLUE +#define ITEM_SELECTED_HL TRUE + +#define TAG_FG COLOR_YELLOW +#define TAG_BG COLOR_WHITE +#define TAG_HL TRUE + +#define TAG_SELECTED_FG COLOR_YELLOW +#define TAG_SELECTED_BG COLOR_BLUE +#define TAG_SELECTED_HL TRUE + +#define TAG_KEY_FG COLOR_YELLOW +#define TAG_KEY_BG COLOR_WHITE +#define TAG_KEY_HL TRUE + +#define TAG_KEY_SELECTED_FG COLOR_YELLOW +#define TAG_KEY_SELECTED_BG COLOR_BLUE +#define TAG_KEY_SELECTED_HL TRUE + +#define CHECK_FG COLOR_BLACK +#define CHECK_BG COLOR_WHITE +#define CHECK_HL FALSE + +#define CHECK_SELECTED_FG COLOR_WHITE +#define CHECK_SELECTED_BG COLOR_BLUE +#define CHECK_SELECTED_HL TRUE + +#define UARROW_FG COLOR_GREEN +#define UARROW_BG COLOR_WHITE +#define UARROW_HL TRUE + +#define DARROW_FG COLOR_GREEN +#define DARROW_BG COLOR_WHITE +#define DARROW_HL TRUE + +/* End of default color definitions */ + +#define C_ATTR(x,y) ((x ? A_BOLD : 0) | COLOR_PAIR((y))) +#define COLOR_NAME_LEN 10 +#define COLOR_COUNT 8 + +/* + * Global variables + */ + +typedef struct { + char name[COLOR_NAME_LEN]; + int value; +} color_names_st; + +extern color_names_st color_names[]; +extern int color_table[][3]; diff --git a/config/scripts/lxdialog/dialog.h b/config/scripts/lxdialog/dialog.h new file mode 100644 index 0000000..0e30d00 --- /dev/null +++ b/config/scripts/lxdialog/dialog.h @@ -0,0 +1,184 @@ + +/* + * dialog.h -- common declarations for all dialog modules + * + * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include CURSES_LOC + +/* + * Colors in ncurses 1.9.9e do not work properly since foreground and + * background colors are OR'd rather than separately masked. This version + * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible + * with standard curses. The simplest fix (to make this work with standard + * curses) uses the wbkgdset() function, not used in the original hack. + * Turn it off if we're building with 1.9.9e, since it just confuses things. + */ +#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE) +#define OLD_NCURSES 1 +#undef wbkgdset +#define wbkgdset(w,p) /*nothing*/ +#else +#define OLD_NCURSES 0 +#endif + +#define TR(params) _tracef params + +#define ESC 27 +#define TAB 9 +#define MAX_LEN 2048 +#define BUF_SIZE (10*1024) +#define MIN(x,y) (x < y ? x : y) +#define MAX(x,y) (x > y ? x : y) + + +#ifndef ACS_ULCORNER +#define ACS_ULCORNER '+' +#endif +#ifndef ACS_LLCORNER +#define ACS_LLCORNER '+' +#endif +#ifndef ACS_URCORNER +#define ACS_URCORNER '+' +#endif +#ifndef ACS_LRCORNER +#define ACS_LRCORNER '+' +#endif +#ifndef ACS_HLINE +#define ACS_HLINE '-' +#endif +#ifndef ACS_VLINE +#define ACS_VLINE '|' +#endif +#ifndef ACS_LTEE +#define ACS_LTEE '+' +#endif +#ifndef ACS_RTEE +#define ACS_RTEE '+' +#endif +#ifndef ACS_UARROW +#define ACS_UARROW '^' +#endif +#ifndef ACS_DARROW +#define ACS_DARROW 'v' +#endif + +/* + * Attribute names + */ +#define screen_attr attributes[0] +#define shadow_attr attributes[1] +#define dialog_attr attributes[2] +#define title_attr attributes[3] +#define border_attr attributes[4] +#define button_active_attr attributes[5] +#define button_inactive_attr attributes[6] +#define button_key_active_attr attributes[7] +#define button_key_inactive_attr attributes[8] +#define button_label_active_attr attributes[9] +#define button_label_inactive_attr attributes[10] +#define inputbox_attr attributes[11] +#define inputbox_border_attr attributes[12] +#define searchbox_attr attributes[13] +#define searchbox_title_attr attributes[14] +#define searchbox_border_attr attributes[15] +#define position_indicator_attr attributes[16] +#define menubox_attr attributes[17] +#define menubox_border_attr attributes[18] +#define item_attr attributes[19] +#define item_selected_attr attributes[20] +#define tag_attr attributes[21] +#define tag_selected_attr attributes[22] +#define tag_key_attr attributes[23] +#define tag_key_selected_attr attributes[24] +#define check_attr attributes[25] +#define check_selected_attr attributes[26] +#define uarrow_attr attributes[27] +#define darrow_attr attributes[28] + +/* number of attributes */ +#define ATTRIBUTE_COUNT 29 + +/* + * Global variables + */ +extern bool use_colors; +extern bool use_shadow; + +extern chtype attributes[]; + +extern const char *backtitle; + +/* + * Function prototypes + */ +extern void create_rc (const char *filename); +extern int parse_rc (void); + + +void init_dialog (void); +void end_dialog (void); +void attr_clear (WINDOW * win, int height, int width, chtype attr); +void dialog_clear (void); +void color_setup (void); +void print_autowrap (WINDOW * win, const char *prompt, int width, int y, int x); +void print_button (WINDOW * win, const char *label, int y, int x, int selected); +void draw_box (WINDOW * win, int y, int x, int height, int width, chtype box, + chtype border); +void draw_shadow (WINDOW * win, int y, int x, int height, int width); + +int first_alpha (const char *string, const char *exempt); +int dialog_yesno (const char *title, const char *prompt, int height, int width); +int dialog_msgbox (const char *title, const char *prompt, int height, + int width, int pause); +int dialog_textbox (const char *title, const char *file, int height, int width); +int dialog_menu (const char *title, const char *prompt, int height, int width, + int menu_height, const char *choice, int item_no, + const char * const * items); +int dialog_checklist (const char *title, const char *prompt, int height, + int width, int list_height, int item_no, + const char * const * items, int flag); +extern unsigned char dialog_input_result[]; +int dialog_inputbox (const char *title, const char *prompt, int height, + int width, const char *init); + +/* + * This is the base for fictitious keys, which activate + * the buttons. + * + * Mouse-generated keys are the following: + * -- the first 32 are used as numbers, in addition to '0'-'9' + * -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o') + * -- uppercase chars are used to invoke the button (M_EVENT + 'O') + */ +#define M_EVENT (KEY_MAX+1) + + +/* + * The `flag' parameter in checklist is used to select between + * radiolist and checklist + */ +#define FLAG_CHECK 1 +#define FLAG_RADIO 0 diff --git a/config/scripts/lxdialog/inputbox.c b/config/scripts/lxdialog/inputbox.c new file mode 100644 index 0000000..fa7bebc --- /dev/null +++ b/config/scripts/lxdialog/inputbox.c @@ -0,0 +1,240 @@ +/* + * inputbox.c -- implements the input box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +unsigned char dialog_input_result[MAX_LEN + 1]; + +/* + * Print the termination buttons + */ +static void +print_buttons(WINDOW *dialog, int height, int width, int selected) +{ + int x = width / 2 - 11; + int y = height - 2; + + print_button (dialog, " Ok ", y, x, selected==0); + print_button (dialog, " Help ", y, x + 14, selected==1); + + wmove(dialog, y, x+1+14*selected); + wrefresh(dialog); +} + +/* + * Display a dialog box for inputing a string + */ +int +dialog_inputbox (const char *title, const char *prompt, int height, int width, + const char *init) +{ + int i, x, y, box_y, box_x, box_width; + int input_x = 0, scroll = 0, key = 0, button = -1; + unsigned char *instr = dialog_input_result; + WINDOW *dialog; + + /* center dialog box on screen */ + x = (COLS - width) / 2; + y = (LINES - height) / 2; + + + draw_shadow (stdscr, y, x, height, width); + + dialog = newwin (height, width, y, x); + keypad (dialog, TRUE); + + draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); + wattrset (dialog, border_attr); + mvwaddch (dialog, height-3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch (dialog, ACS_HLINE); + wattrset (dialog, dialog_attr); + waddch (dialog, ACS_RTEE); + + if (title != NULL && strlen(title) >= width-2 ) { + /* truncate long title -- mec */ + char * title2 = malloc(width-2+1); + memcpy( title2, title, width-2 ); + title2[width-2] = '\0'; + title = title2; + } + + if (title != NULL) { + wattrset (dialog, title_attr); + mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); + waddstr (dialog, (char *)title); + waddch (dialog, ' '); + } + + wattrset (dialog, dialog_attr); + print_autowrap (dialog, prompt, width - 2, 1, 3); + + /* Draw the input field box */ + box_width = width - 6; + getyx (dialog, y, x); + box_y = y + 2; + box_x = (width - box_width) / 2; + draw_box (dialog, y + 1, box_x - 1, 3, box_width + 2, + border_attr, dialog_attr); + + print_buttons(dialog, height, width, 0); + + /* Set up the initial value */ + wmove (dialog, box_y, box_x); + wattrset (dialog, inputbox_attr); + + if (!init) + instr[0] = '\0'; + else + strcpy (instr, init); + + input_x = strlen (instr); + + if (input_x >= box_width) { + scroll = input_x - box_width + 1; + input_x = box_width - 1; + for (i = 0; i < box_width - 1; i++) + waddch (dialog, instr[scroll + i]); + } else + waddstr (dialog, instr); + + wmove (dialog, box_y, box_x + input_x); + + wrefresh (dialog); + + while (key != ESC) { + key = wgetch (dialog); + + if (button == -1) { /* Input box selected */ + switch (key) { + case TAB: + case KEY_UP: + case KEY_DOWN: + break; + case KEY_LEFT: + continue; + case KEY_RIGHT: + continue; + case KEY_BACKSPACE: + case 127: + if (input_x || scroll) { + wattrset (dialog, inputbox_attr); + if (!input_x) { + scroll = scroll < box_width - 1 ? + 0 : scroll - (box_width - 1); + wmove (dialog, box_y, box_x); + for (i = 0; i < box_width; i++) + waddch (dialog, instr[scroll + input_x + i] ? + instr[scroll + input_x + i] : ' '); + input_x = strlen (instr) - scroll; + } else + input_x--; + instr[scroll + input_x] = '\0'; + mvwaddch (dialog, box_y, input_x + box_x, ' '); + wmove (dialog, box_y, input_x + box_x); + wrefresh (dialog); + } + continue; + default: + if (key < 0x100 && isprint (key)) { + if (scroll + input_x < MAX_LEN) { + wattrset (dialog, inputbox_attr); + instr[scroll + input_x] = key; + instr[scroll + input_x + 1] = '\0'; + if (input_x == box_width - 1) { + scroll++; + wmove (dialog, box_y, box_x); + for (i = 0; i < box_width - 1; i++) + waddch (dialog, instr[scroll + i]); + } else { + wmove (dialog, box_y, input_x++ + box_x); + waddch (dialog, key); + } + wrefresh (dialog); + } else + flash (); /* Alarm user about overflow */ + continue; + } + } + } + switch (key) { + case 'O': + case 'o': + delwin (dialog); + return 0; + case 'H': + case 'h': + delwin (dialog); + return 1; + case KEY_UP: + case KEY_LEFT: + switch (button) { + case -1: + button = 1; /* Indicates "Cancel" button is selected */ + print_buttons(dialog, height, width, 1); + break; + case 0: + button = -1; /* Indicates input box is selected */ + print_buttons(dialog, height, width, 0); + wmove (dialog, box_y, box_x + input_x); + wrefresh (dialog); + break; + case 1: + button = 0; /* Indicates "OK" button is selected */ + print_buttons(dialog, height, width, 0); + break; + } + break; + case TAB: + case KEY_DOWN: + case KEY_RIGHT: + switch (button) { + case -1: + button = 0; /* Indicates "OK" button is selected */ + print_buttons(dialog, height, width, 0); + break; + case 0: + button = 1; /* Indicates "Cancel" button is selected */ + print_buttons(dialog, height, width, 1); + break; + case 1: + button = -1; /* Indicates input box is selected */ + print_buttons(dialog, height, width, 0); + wmove (dialog, box_y, box_x + input_x); + wrefresh (dialog); + break; + } + break; + case ' ': + case '\n': + delwin (dialog); + return (button == -1 ? 0 : button); + case 'X': + case 'x': + key = ESC; + case ESC: + break; + } + } + + delwin (dialog); + return -1; /* ESC pressed */ +} diff --git a/config/scripts/lxdialog/lxdialog.c b/config/scripts/lxdialog/lxdialog.c new file mode 100644 index 0000000..6f4c1fd --- /dev/null +++ b/config/scripts/lxdialog/lxdialog.c @@ -0,0 +1,226 @@ +/* + * dialog - Display simple dialog boxes from shell scripts + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +static void Usage (const char *name); + +typedef int (jumperFn) (const char *title, int argc, const char * const * argv); + +struct Mode { + char *name; + int argmin, argmax, argmod; + jumperFn *jumper; +}; + +jumperFn j_menu, j_checklist, j_radiolist, j_yesno, j_textbox, j_inputbox; +jumperFn j_msgbox, j_infobox; + +static struct Mode modes[] = +{ + {"--menu", 9, 0, 3, j_menu}, + {"--checklist", 9, 0, 3, j_checklist}, + {"--radiolist", 9, 0, 3, j_radiolist}, + {"--yesno", 5,5,1, j_yesno}, + {"--textbox", 5,5,1, j_textbox}, + {"--inputbox", 5, 6, 1, j_inputbox}, + {"--msgbox", 5, 5, 1, j_msgbox}, + {"--infobox", 5, 5, 1, j_infobox}, + {NULL, 0, 0, 0, NULL} +}; + +static struct Mode *modePtr; + +#ifdef LOCALE +#include +#endif + +int +main (int argc, const char * const * argv) +{ + int offset = 0, clear_screen = 0, end_common_opts = 0, retval; + const char *title = NULL; + +#ifdef LOCALE + (void) setlocale (LC_ALL, ""); +#endif + +#ifdef TRACE + trace(TRACE_CALLS|TRACE_UPDATE); +#endif + if (argc < 2) { + Usage (argv[0]); + exit (-1); + } + + while (offset < argc - 1 && !end_common_opts) { /* Common options */ + if (!strcmp (argv[offset + 1], "--title")) { + if (argc - offset < 3 || title != NULL) { + Usage (argv[0]); + exit (-1); + } else { + title = argv[offset + 2]; + offset += 2; + } + } else if (!strcmp (argv[offset + 1], "--backtitle")) { + if (backtitle != NULL) { + Usage (argv[0]); + exit (-1); + } else { + backtitle = argv[offset + 2]; + offset += 2; + } + } else if (!strcmp (argv[offset + 1], "--clear")) { + if (clear_screen) { /* Hey, "--clear" can't appear twice! */ + Usage (argv[0]); + exit (-1); + } else if (argc == 2) { /* we only want to clear the screen */ + init_dialog (); + refresh (); /* init_dialog() will clear the screen for us */ + end_dialog (); + return 0; + } else { + clear_screen = 1; + offset++; + } + } else /* no more common options */ + end_common_opts = 1; + } + + if (argc - 1 == offset) { /* no more options */ + Usage (argv[0]); + exit (-1); + } + /* use a table to look for the requested mode, to avoid code duplication */ + + for (modePtr = modes; modePtr->name; modePtr++) /* look for the mode */ + if (!strcmp (argv[offset + 1], modePtr->name)) + break; + + if (!modePtr->name) + Usage (argv[0]); + if (argc - offset < modePtr->argmin) + Usage (argv[0]); + if (modePtr->argmax && argc - offset > modePtr->argmax) + Usage (argv[0]); + + + + init_dialog (); + retval = (*(modePtr->jumper)) (title, argc - offset, argv + offset); + + if (clear_screen) { /* clear screen before exit */ + attr_clear (stdscr, LINES, COLS, screen_attr); + refresh (); + } + end_dialog(); + + exit (retval); +} + +/* + * Print program usage + */ +static void +Usage (const char *name) +{ + fprintf (stderr, "\ +\ndialog, by Savio Lam (lam836@cs.cuhk.hk).\ +\n patched by Stuart Herbert (S.Herbert@shef.ac.uk)\ +\n modified/gutted for use as a Linux kernel config tool by \ +\n William Roadcap (roadcapw@cfw.com)\ +\n\ +\n* Display dialog boxes from shell scripts *\ +\n\ +\nUsage: %s --clear\ +\n %s [--title ] [--backtitle <backtitle>] --clear <Box options>\ +\n\ +\nBox options:\ +\n\ +\n --menu <text> <height> <width> <menu height> <tag1> <item1>...\ +\n --checklist <text> <height> <width> <list height> <tag1> <item1> <status1>...\ +\n --radiolist <text> <height> <width> <list height> <tag1> <item1> <status1>...\ +\n --textbox <file> <height> <width>\ +\n --inputbox <text> <height> <width> [<init>]\ +\n --yesno <text> <height> <width>\ +\n", name, name); + exit (-1); +} + +/* + * These are the program jumpers + */ + +int +j_menu (const char *t, int ac, const char * const * av) +{ + return dialog_menu (t, av[2], atoi (av[3]), atoi (av[4]), + atoi (av[5]), av[6], (ac - 6) / 2, av + 7); +} + +int +j_checklist (const char *t, int ac, const char * const * av) +{ + return dialog_checklist (t, av[2], atoi (av[3]), atoi (av[4]), + atoi (av[5]), (ac - 6) / 3, av + 6, FLAG_CHECK); +} + +int +j_radiolist (const char *t, int ac, const char * const * av) +{ + return dialog_checklist (t, av[2], atoi (av[3]), atoi (av[4]), + atoi (av[5]), (ac - 6) / 3, av + 6, FLAG_RADIO); +} + +int +j_textbox (const char *t, int ac, const char * const * av) +{ + return dialog_textbox (t, av[2], atoi (av[3]), atoi (av[4])); +} + +int +j_yesno (const char *t, int ac, const char * const * av) +{ + return dialog_yesno (t, av[2], atoi (av[3]), atoi (av[4])); +} + +int +j_inputbox (const char *t, int ac, const char * const * av) +{ + int ret = dialog_inputbox (t, av[2], atoi (av[3]), atoi (av[4]), + ac == 6 ? av[5] : (char *) NULL); + if (ret == 0) + fprintf(stderr, dialog_input_result); + return ret; +} + +int +j_msgbox (const char *t, int ac, const char * const * av) +{ + return dialog_msgbox (t, av[2], atoi (av[3]), atoi (av[4]), 1); +} + +int +j_infobox (const char *t, int ac, const char * const * av) +{ + return dialog_msgbox (t, av[2], atoi (av[3]), atoi (av[4]), 0); +} + diff --git a/config/scripts/lxdialog/menubox.c b/config/scripts/lxdialog/menubox.c new file mode 100644 index 0000000..d6dc07d --- /dev/null +++ b/config/scripts/lxdialog/menubox.c @@ -0,0 +1,437 @@ +/* + * menubox.c -- implements the menu box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Changes by Clifford Wolf (god@clifford.at) + * + * [ 1998-06-13 ] + * + * *) A bugfix for the Page-Down problem + * + * *) Formerly when I used Page Down and Page Up, the cursor would be set + * to the first position in the menu box. Now lxdialog is a bit + * smarter and works more like other menu systems (just have a look at + * it). + * + * *) Formerly if I selected something my scrolling would be broken because + * lxdialog is re-invoked by the Menuconfig shell script, can't + * remember the last scrolling position, and just sets it so that the + * cursor is at the bottom of the box. Now it writes the temporary file + * lxdialog.scrltmp which contains this information. The file is + * deleted by lxdialog if the user leaves a submenu or enters a new + * one, but it would be nice if Menuconfig could make another "rm -f" + * just to be sure. Just try it out - you will recognise a difference! + * + * [ 1998-06-14 ] + * + * *) Now lxdialog is crash-safe against broken "lxdialog.scrltmp" files + * and menus change their size on the fly. + * + * *) If for some reason the last scrolling position is not saved by + * lxdialog, it sets the scrolling so that the selected item is in the + * middle of the menu box, not at the bottom. + * + * 02 January 1999, Michael Elizabeth Chastain (mec@shout.net) + * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus. + * This fixes a bug in Menuconfig where using ' ' to descend into menus + * would leave mis-synchronized lxdialog.scrltmp files lying around, + * fscanf would read in 'scroll', and eventually that value would get used. + */ + +#include "dialog.h" + +static int menu_width, item_x; + +/* + * Print menu item + */ +static void +print_item (WINDOW * win, const char *item, int choice, int selected, int hotkey) +{ + int j; + char menu_item[menu_width+1]; + + strncpy(menu_item, item, menu_width); + menu_item[menu_width] = 0; + j = first_alpha(menu_item, "YyNnMm"); + + /* Clear 'residue' of last item */ + wattrset (win, menubox_attr); + wmove (win, choice, 0); +#if OLD_NCURSES + { + int i; + for (i = 0; i < menu_width; i++) + waddch (win, ' '); + } +#else + wclrtoeol(win); +#endif + wattrset (win, selected ? item_selected_attr : item_attr); + mvwaddstr (win, choice, item_x, menu_item); + if (hotkey) { + wattrset (win, selected ? tag_key_selected_attr : tag_key_attr); + mvwaddch(win, choice, item_x+j, menu_item[j]); + } +} + +/* + * Print the scroll indicators. + */ +static void +print_arrows (WINDOW * win, int item_no, int scroll, + int y, int x, int height) +{ + int cur_y, cur_x; + + getyx(win, cur_y, cur_x); + + wmove(win, y, x); + + if (scroll > 0) { + wattrset (win, uarrow_attr); + waddch (win, ACS_UARROW); + waddstr (win, "(-)"); + } + else { + wattrset (win, menubox_attr); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + } + + y = y + height + 1; + wmove(win, y, x); + + if ((height < item_no) && (scroll + height < item_no)) { + wattrset (win, darrow_attr); + waddch (win, ACS_DARROW); + waddstr (win, "(+)"); + } + else { + wattrset (win, menubox_border_attr); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + waddch (win, ACS_HLINE); + } + + wmove(win, cur_y, cur_x); +} + +/* + * Display the termination buttons. + */ +static void +print_buttons (WINDOW *win, int height, int width, int selected) +{ + int x = width / 2 - 16; + int y = height - 2; + + print_button (win, "Select", y, x, selected == 0); + print_button (win, " Exit ", y, x + 12, selected == 1); + print_button (win, " Help ", y, x + 24, selected == 2); + + wmove(win, y, x+1+12*selected); + wrefresh (win); +} + +/* + * Display a menu for choosing among a number of options + */ +int +dialog_menu (const char *title, const char *prompt, int height, int width, + int menu_height, const char *current, int item_no, + const char * const * items) + +{ + int i, j, x, y, box_x, box_y; + int key = 0, button = 0, scroll = 0, choice = 0, first_item = 0, max_choice; + WINDOW *dialog, *menu; + FILE *f; + + max_choice = MIN (menu_height, item_no); + + /* center dialog box on screen */ + x = (COLS - width) / 2; + y = (LINES - height) / 2; + + draw_shadow (stdscr, y, x, height, width); + + dialog = newwin (height, width, y, x); + keypad (dialog, TRUE); + + draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); + wattrset (dialog, border_attr); + mvwaddch (dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch (dialog, ACS_HLINE); + wattrset (dialog, dialog_attr); + wbkgdset (dialog, dialog_attr & A_COLOR); + waddch (dialog, ACS_RTEE); + + if (title != NULL && strlen(title) >= width-2 ) { + /* truncate long title -- mec */ + char * title2 = malloc(width-2+1); + memcpy( title2, title, width-2 ); + title2[width-2] = '\0'; + title = title2; + } + + if (title != NULL) { + wattrset (dialog, title_attr); + mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); + waddstr (dialog, (char *)title); + waddch (dialog, ' '); + } + + wattrset (dialog, dialog_attr); + print_autowrap (dialog, prompt, width - 2, 1, 3); + + menu_width = width - 6; + box_y = height - menu_height - 5; + box_x = (width - menu_width) / 2 - 1; + + /* create new window for the menu */ + menu = subwin (dialog, menu_height, menu_width, + y + box_y + 1, x + box_x + 1); + keypad (menu, TRUE); + + /* draw a box around the menu items */ + draw_box (dialog, box_y, box_x, menu_height + 2, menu_width + 2, + menubox_border_attr, menubox_attr); + + /* + * Find length of longest item in order to center menu. + * Set 'choice' to default item. + */ + item_x = 0; + for (i = 0; i < item_no; i++) { + item_x = MAX (item_x, MIN(menu_width, strlen (items[i * 2 + 1]) + 2)); + if (strcmp(current, items[i*2]) == 0) choice = i; + } + + item_x = (menu_width - item_x) / 2; + + /* get the scroll info from the temp file */ + if ( (f=fopen("lxdialog.scrltmp","r")) != NULL ) { + if ( (fscanf(f,"%d\n",&scroll) == 1) && (scroll <= choice) && + (scroll+max_choice > choice) && (scroll >= 0) && + (scroll+max_choice <= item_no) ) { + first_item = scroll; + choice = choice - scroll; + fclose(f); + } else { + scroll=0; + remove("lxdialog.scrltmp"); + fclose(f); + f=NULL; + } + } + if ( (choice >= max_choice) || (f==NULL && choice >= max_choice/2) ) { + if (choice >= item_no-max_choice/2) + scroll = first_item = item_no-max_choice; + else + scroll = first_item = choice - max_choice/2; + choice = choice - scroll; + } + + /* Print the menu */ + for (i=0; i < max_choice; i++) { + print_item (menu, items[(first_item + i) * 2 + 1], i, i == choice, + (items[(first_item + i)*2][0] != ':')); + } + + wnoutrefresh (menu); + + print_arrows(dialog, item_no, scroll, + box_y, box_x+item_x+1, menu_height); + + print_buttons (dialog, height, width, 0); + + while (key != ESC) { + key = wgetch(dialog); + + if (key < 256 && isalpha(key)) key = tolower(key); + + if (strchr("ynm", key)) + i = max_choice; + else { + for (i = choice+1; i < max_choice; i++) { + j = first_alpha(items[(scroll+i)*2+1], "YyNnMm"); + if (key == tolower(items[(scroll+i)*2+1][j])) + break; + } + if (i == max_choice) + for (i = 0; i < max_choice; i++) { + j = first_alpha(items[(scroll+i)*2+1], "YyNnMm"); + if (key == tolower(items[(scroll+i)*2+1][j])) + break; + } + } + + if (i < max_choice || + key == KEY_UP || key == KEY_DOWN || + key == '-' || key == '+' || + key == KEY_PPAGE || key == KEY_NPAGE) { + + print_item (menu, items[(scroll+choice)*2+1], choice, FALSE, + (items[(scroll+choice)*2][0] != ':')); + + if (key == KEY_UP || key == '-') { + if (choice < 2 && scroll) { + /* Scroll menu down */ + scrollok (menu, TRUE); + wscrl (menu, -1); + scrollok (menu, FALSE); + + scroll--; + + print_item (menu, items[scroll * 2 + 1], 0, FALSE, + (items[scroll*2][0] != ':')); + } else + choice = MAX(choice - 1, 0); + + } else if (key == KEY_DOWN || key == '+') { + + print_item (menu, items[(scroll+choice)*2+1], choice, FALSE, + (items[(scroll+choice)*2][0] != ':')); + + if ((choice > max_choice-3) && + (scroll + max_choice < item_no) + ) { + /* Scroll menu up */ + scrollok (menu, TRUE); + scroll (menu); + scrollok (menu, FALSE); + + scroll++; + + print_item (menu, items[(scroll+max_choice-1)*2+1], + max_choice-1, FALSE, + (items[(scroll+max_choice-1)*2][0] != ':')); + } else + choice = MIN(choice+1, max_choice-1); + + } else if (key == KEY_PPAGE) { + scrollok (menu, TRUE); + for (i=0; (i < max_choice); i++) { + if (scroll > 0) { + wscrl (menu, -1); + scroll--; + print_item (menu, items[scroll * 2 + 1], 0, FALSE, + (items[scroll*2][0] != ':')); + } else { + if (choice > 0) + choice--; + } + } + scrollok (menu, FALSE); + + } else if (key == KEY_NPAGE) { + for (i=0; (i < max_choice); i++) { + if (scroll+max_choice < item_no) { + scrollok (menu, TRUE); + scroll(menu); + scrollok (menu, FALSE); + scroll++; + print_item (menu, items[(scroll+max_choice-1)*2+1], + max_choice-1, FALSE, + (items[(scroll+max_choice-1)*2][0] != ':')); + } else { + if (choice+1 < max_choice) + choice++; + } + } + + } else + choice = i; + + print_item (menu, items[(scroll+choice)*2+1], choice, TRUE, + (items[(scroll+choice)*2][0] != ':')); + + print_arrows(dialog, item_no, scroll, + box_y, box_x+item_x+1, menu_height); + + wnoutrefresh (menu); + wrefresh (dialog); + + continue; /* wait for another key press */ + } + + switch (key) { + case KEY_LEFT: + case TAB: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 2 : (button > 2 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh (dialog); + break; + case ' ': + case 's': + case 'y': + case 'n': + case 'm': + /* save scroll info */ + if ( (f=fopen("lxdialog.scrltmp","w")) != NULL ) { + fprintf(f,"%d\n",scroll); + fclose(f); + } + delwin (dialog); + fprintf(stderr, "%s\n", items[(scroll + choice) * 2]); + switch (key) { + case 's': return 3; + case 'y': return 3; + case 'n': return 4; + case 'm': return 5; + case ' ': return 6; + } + return 0; + case 'h': + case '?': + button = 2; + case '\n': + delwin (dialog); + if (button == 2) + fprintf(stderr, "%s \"%s\"\n", + items[(scroll + choice) * 2], + items[(scroll + choice) * 2 + 1] + + first_alpha(items[(scroll + choice) * 2 + 1],"")); + else + fprintf(stderr, "%s\n", items[(scroll + choice) * 2]); + + remove("lxdialog.scrltmp"); + return button; + case 'e': + case 'x': + key = ESC; + case ESC: + break; + } + } + + delwin (dialog); + remove("lxdialog.scrltmp"); + return -1; /* ESC pressed */ +} diff --git a/config/scripts/lxdialog/msgbox.c b/config/scripts/lxdialog/msgbox.c new file mode 100644 index 0000000..93692e1 --- /dev/null +++ b/config/scripts/lxdialog/msgbox.c @@ -0,0 +1,85 @@ +/* + * msgbox.c -- implements the message box and info box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +/* + * Display a message box. Program will pause and display an "OK" button + * if the parameter 'pause' is non-zero. + */ +int +dialog_msgbox (const char *title, const char *prompt, int height, int width, + int pause) +{ + int i, x, y, key = 0; + WINDOW *dialog; + + /* center dialog box on screen */ + x = (COLS - width) / 2; + y = (LINES - height) / 2; + + draw_shadow (stdscr, y, x, height, width); + + dialog = newwin (height, width, y, x); + keypad (dialog, TRUE); + + draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); + + if (title != NULL && strlen(title) >= width-2 ) { + /* truncate long title -- mec */ + char * title2 = malloc(width-2+1); + memcpy( title2, title, width-2 ); + title2[width-2] = '\0'; + title = title2; + } + + if (title != NULL) { + wattrset (dialog, title_attr); + mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); + waddstr (dialog, (char *)title); + waddch (dialog, ' '); + } + wattrset (dialog, dialog_attr); + print_autowrap (dialog, prompt, width - 2, 1, 2); + + if (pause) { + wattrset (dialog, border_attr); + mvwaddch (dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch (dialog, ACS_HLINE); + wattrset (dialog, dialog_attr); + waddch (dialog, ACS_RTEE); + + print_button (dialog, " Ok ", + height - 2, width / 2 - 4, TRUE); + + wrefresh (dialog); + while (key != ESC && key != '\n' && key != ' ' && + key != 'O' && key != 'o' && key != 'X' && key != 'x') + key = wgetch (dialog); + } else { + key = '\n'; + wrefresh (dialog); + } + + delwin (dialog); + return key == ESC ? -1 : 0; +} diff --git a/config/scripts/lxdialog/textbox.c b/config/scripts/lxdialog/textbox.c new file mode 100644 index 0000000..ecf5541 --- /dev/null +++ b/config/scripts/lxdialog/textbox.c @@ -0,0 +1,556 @@ +/* + * textbox.c -- implements the text box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +static void back_lines (int n); +static void print_page (WINDOW * win, int height, int width); +static void print_line (WINDOW * win, int row, int width); +static char *get_line (void); +static void print_position (WINDOW * win, int height, int width); + +static int hscroll = 0, fd, file_size, bytes_read; +static int begin_reached = 1, end_reached = 0, page_length; +static char *buf, *page; + +/* + * Display text from a file in a dialog box. + */ +int +dialog_textbox (const char *title, const char *file, int height, int width) +{ + int i, x, y, cur_x, cur_y, fpos, key = 0; + int passed_end; + char search_term[MAX_LEN + 1]; + WINDOW *dialog, *text; + + search_term[0] = '\0'; /* no search term entered yet */ + + /* Open input file for reading */ + if ((fd = open (file, O_RDONLY)) == -1) { + endwin (); + fprintf (stderr, + "\nCan't open input file in dialog_textbox().\n"); + exit (-1); + } + /* Get file size. Actually, 'file_size' is the real file size - 1, + since it's only the last byte offset from the beginning */ + if ((file_size = lseek (fd, 0, SEEK_END)) == -1) { + endwin (); + fprintf (stderr, "\nError getting file size in dialog_textbox().\n"); + exit (-1); + } + /* Restore file pointer to beginning of file after getting file size */ + if (lseek (fd, 0, SEEK_SET) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer in dialog_textbox().\n"); + exit (-1); + } + /* Allocate space for read buffer */ + if ((buf = malloc (BUF_SIZE + 1)) == NULL) { + endwin (); + fprintf (stderr, "\nCan't allocate memory in dialog_textbox().\n"); + exit (-1); + } + if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { + endwin (); + fprintf (stderr, "\nError reading file in dialog_textbox().\n"); + exit (-1); + } + buf[bytes_read] = '\0'; /* mark end of valid data */ + page = buf; /* page is pointer to start of page to be displayed */ + + /* center dialog box on screen */ + x = (COLS - width) / 2; + y = (LINES - height) / 2; + + + draw_shadow (stdscr, y, x, height, width); + + dialog = newwin (height, width, y, x); + keypad (dialog, TRUE); + + /* Create window for text region, used for scrolling text */ + text = subwin (dialog, height - 4, width - 2, y + 1, x + 1); + wattrset (text, dialog_attr); + wbkgdset (text, dialog_attr & A_COLOR); + + keypad (text, TRUE); + + /* register the new window, along with its borders */ + draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); + + wattrset (dialog, border_attr); + mvwaddch (dialog, height-3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch (dialog, ACS_HLINE); + wattrset (dialog, dialog_attr); + wbkgdset (dialog, dialog_attr & A_COLOR); + waddch (dialog, ACS_RTEE); + + if (title != NULL && strlen(title) >= width-2 ) { + /* truncate long title -- mec */ + char * title2 = malloc(width-2+1); + memcpy( title2, title, width-2 ); + title2[width-2] = '\0'; + title = title2; + } + + if (title != NULL) { + wattrset (dialog, title_attr); + mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); + waddstr (dialog, (char *)title); + waddch (dialog, ' '); + } + print_button (dialog, " Exit ", height - 2, width / 2 - 4, TRUE); + wnoutrefresh (dialog); + getyx (dialog, cur_y, cur_x); /* Save cursor position */ + + /* Print first page of text */ + attr_clear (text, height - 4, width - 2, dialog_attr); + print_page (text, height - 4, width - 2); + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh (dialog); + + while ((key != ESC) && (key != '\n')) { + key = wgetch (dialog); + switch (key) { + case 'E': /* Exit */ + case 'e': + case 'X': + case 'x': + delwin (dialog); + free (buf); + close (fd); + return 0; + case 'g': /* First page */ + case KEY_HOME: + if (!begin_reached) { + begin_reached = 1; + /* First page not in buffer? */ + if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { + endwin (); + fprintf (stderr, + "\nError moving file pointer in dialog_textbox().\n"); + exit (-1); + } + if (fpos > bytes_read) { /* Yes, we have to read it in */ + if (lseek (fd, 0, SEEK_SET) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer in " + "dialog_textbox().\n"); + exit (-1); + } + if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { + endwin (); + fprintf (stderr, + "\nError reading file in dialog_textbox().\n"); + exit (-1); + } + buf[bytes_read] = '\0'; + } + page = buf; + print_page (text, height - 4, width - 2); + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh (dialog); + } + break; + case 'G': /* Last page */ + case KEY_END: + + end_reached = 1; + /* Last page not in buffer? */ + if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { + endwin (); + fprintf (stderr, + "\nError moving file pointer in dialog_textbox().\n"); + exit (-1); + } + if (fpos < file_size) { /* Yes, we have to read it in */ + if (lseek (fd, -BUF_SIZE, SEEK_END) == -1) { + endwin (); + fprintf (stderr, + "\nError moving file pointer in dialog_textbox().\n"); + exit (-1); + } + if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { + endwin (); + fprintf (stderr, + "\nError reading file in dialog_textbox().\n"); + exit (-1); + } + buf[bytes_read] = '\0'; + } + page = buf + bytes_read; + back_lines (height - 4); + print_page (text, height - 4, width - 2); + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh (dialog); + break; + case 'K': /* Previous line */ + case 'k': + case KEY_UP: + if (!begin_reached) { + back_lines (page_length + 1); + + /* We don't call print_page() here but use scrolling to ensure + faster screen update. However, 'end_reached' and + 'page_length' should still be updated, and 'page' should + point to start of next page. This is done by calling + get_line() in the following 'for' loop. */ + scrollok (text, TRUE); + wscrl (text, -1); /* Scroll text region down one line */ + scrollok (text, FALSE); + page_length = 0; + passed_end = 0; + for (i = 0; i < height - 4; i++) { + if (!i) { + /* print first line of page */ + print_line (text, 0, width - 2); + wnoutrefresh (text); + } else + /* Called to update 'end_reached' and 'page' */ + get_line (); + if (!passed_end) + page_length++; + if (end_reached && !passed_end) + passed_end = 1; + } + + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh (dialog); + } + break; + case 'B': /* Previous page */ + case 'b': + case KEY_PPAGE: + if (begin_reached) + break; + back_lines (page_length + height - 4); + print_page (text, height - 4, width - 2); + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); + wrefresh (dialog); + break; + case 'J': /* Next line */ + case 'j': + case KEY_DOWN: + if (!end_reached) { + begin_reached = 0; + scrollok (text, TRUE); + scroll (text); /* Scroll text region up one line */ + scrollok (text, FALSE); + print_line (text, height - 5, width - 2); + wnoutrefresh (text); + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh (dialog); + } + break; + case KEY_NPAGE: /* Next page */ + case ' ': + if (end_reached) + break; + + begin_reached = 0; + print_page (text, height - 4, width - 2); + print_position (dialog, height, width); + wmove (dialog, cur_y, cur_x); + wrefresh (dialog); + break; + case '0': /* Beginning of line */ + case 'H': /* Scroll left */ + case 'h': + case KEY_LEFT: + if (hscroll <= 0) + break; + + if (key == '0') + hscroll = 0; + else + hscroll--; + /* Reprint current page to scroll horizontally */ + back_lines (page_length); + print_page (text, height - 4, width - 2); + wmove (dialog, cur_y, cur_x); + wrefresh (dialog); + break; + case 'L': /* Scroll right */ + case 'l': + case KEY_RIGHT: + if (hscroll >= MAX_LEN) + break; + hscroll++; + /* Reprint current page to scroll horizontally */ + back_lines (page_length); + print_page (text, height - 4, width - 2); + wmove (dialog, cur_y, cur_x); + wrefresh (dialog); + break; + case ESC: + break; + } + } + + delwin (dialog); + free (buf); + close (fd); + return -1; /* ESC pressed */ +} + +/* + * Go back 'n' lines in text file. Called by dialog_textbox(). + * 'page' will be updated to point to the desired line in 'buf'. + */ +static void +back_lines (int n) +{ + int i, fpos; + + begin_reached = 0; + /* We have to distinguish between end_reached and !end_reached + since at end of file, the line is not ended by a '\n'. + The code inside 'if' basically does a '--page' to move one + character backward so as to skip '\n' of the previous line */ + if (!end_reached) { + /* Either beginning of buffer or beginning of file reached? */ + if (page == buf) { + if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer in " + "back_lines().\n"); + exit (-1); + } + if (fpos > bytes_read) { /* Not beginning of file yet */ + /* We've reached beginning of buffer, but not beginning of + file yet, so read previous part of file into buffer. + Note that we only move backward for BUF_SIZE/2 bytes, + but not BUF_SIZE bytes to avoid re-reading again in + print_page() later */ + /* Really possible to move backward BUF_SIZE/2 bytes? */ + if (fpos < BUF_SIZE / 2 + bytes_read) { + /* No, move less then */ + if (lseek (fd, 0, SEEK_SET) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer in " + "back_lines().\n"); + exit (-1); + } + page = buf + fpos - bytes_read; + } else { /* Move backward BUF_SIZE/2 bytes */ + if (lseek (fd, -(BUF_SIZE / 2 + bytes_read), SEEK_CUR) + == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer " + "in back_lines().\n"); + exit (-1); + } + page = buf + BUF_SIZE / 2; + } + if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { + endwin (); + fprintf (stderr, "\nError reading file in back_lines().\n"); + exit (-1); + } + buf[bytes_read] = '\0'; + } else { /* Beginning of file reached */ + begin_reached = 1; + return; + } + } + if (*(--page) != '\n') { /* '--page' here */ + /* Something's wrong... */ + endwin (); + fprintf (stderr, "\nInternal error in back_lines().\n"); + exit (-1); + } + } + /* Go back 'n' lines */ + for (i = 0; i < n; i++) + do { + if (page == buf) { + if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { + endwin (); + fprintf (stderr, + "\nError moving file pointer in back_lines().\n"); + exit (-1); + } + if (fpos > bytes_read) { + /* Really possible to move backward BUF_SIZE/2 bytes? */ + if (fpos < BUF_SIZE / 2 + bytes_read) { + /* No, move less then */ + if (lseek (fd, 0, SEEK_SET) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer " + "in back_lines().\n"); + exit (-1); + } + page = buf + fpos - bytes_read; + } else { /* Move backward BUF_SIZE/2 bytes */ + if (lseek (fd, -(BUF_SIZE / 2 + bytes_read), + SEEK_CUR) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer" + " in back_lines().\n"); + exit (-1); + } + page = buf + BUF_SIZE / 2; + } + if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { + endwin (); + fprintf (stderr, "\nError reading file in " + "back_lines().\n"); + exit (-1); + } + buf[bytes_read] = '\0'; + } else { /* Beginning of file reached */ + begin_reached = 1; + return; + } + } + } while (*(--page) != '\n'); + page++; +} + +/* + * Print a new page of text. Called by dialog_textbox(). + */ +static void +print_page (WINDOW * win, int height, int width) +{ + int i, passed_end = 0; + + page_length = 0; + for (i = 0; i < height; i++) { + print_line (win, i, width); + if (!passed_end) + page_length++; + if (end_reached && !passed_end) + passed_end = 1; + } + wnoutrefresh (win); +} + +/* + * Print a new line of text. Called by dialog_textbox() and print_page(). + */ +static void +print_line (WINDOW * win, int row, int width) +{ + int y, x; + char *line; + + line = get_line (); + line += MIN (strlen (line), hscroll); /* Scroll horizontally */ + wmove (win, row, 0); /* move cursor to correct line */ + waddch (win, ' '); + waddnstr (win, line, MIN (strlen (line), width - 2)); + + getyx (win, y, x); + /* Clear 'residue' of previous line */ +#if OLD_NCURSES + { + int i; + for (i = 0; i < width - x; i++) + waddch (win, ' '); + } +#else + wclrtoeol(win); +#endif +} + +/* + * Return current line of text. Called by dialog_textbox() and print_line(). + * 'page' should point to start of current line before calling, and will be + * updated to point to start of next line. + */ +static char * +get_line (void) +{ + int i = 0, fpos; + static char line[MAX_LEN + 1]; + + end_reached = 0; + while (*page != '\n') { + if (*page == '\0') { + /* Either end of file or end of buffer reached */ + if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer in " + "get_line().\n"); + exit (-1); + } + if (fpos < file_size) { /* Not end of file yet */ + /* We've reached end of buffer, but not end of file yet, + so read next part of file into buffer */ + if ((bytes_read = read (fd, buf, BUF_SIZE)) == -1) { + endwin (); + fprintf (stderr, "\nError reading file in get_line().\n"); + exit (-1); + } + buf[bytes_read] = '\0'; + page = buf; + } else { + if (!end_reached) + end_reached = 1; + break; + } + } else if (i < MAX_LEN) + line[i++] = *(page++); + else { + /* Truncate lines longer than MAX_LEN characters */ + if (i == MAX_LEN) + line[i++] = '\0'; + page++; + } + } + if (i <= MAX_LEN) + line[i] = '\0'; + if (!end_reached) + page++; /* move pass '\n' */ + + return line; +} + +/* + * Print current position + */ +static void +print_position (WINDOW * win, int height, int width) +{ + int fpos, percent; + + if ((fpos = lseek (fd, 0, SEEK_CUR)) == -1) { + endwin (); + fprintf (stderr, "\nError moving file pointer in print_position().\n"); + exit (-1); + } + wattrset (win, position_indicator_attr); + wbkgdset (win, position_indicator_attr & A_COLOR); + percent = !file_size ? + 100 : ((fpos - bytes_read + page - buf) * 100) / file_size; + wmove (win, height - 3, width - 9); + wprintw (win, "(%3d%%)", percent); +} diff --git a/config/scripts/lxdialog/util.c b/config/scripts/lxdialog/util.c new file mode 100644 index 0000000..b3a7af9 --- /dev/null +++ b/config/scripts/lxdialog/util.c @@ -0,0 +1,359 @@ +/* + * util.c + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + + +/* use colors by default? */ +bool use_colors = 1; + +const char *backtitle = NULL; + +const char *dialog_result; + +/* + * Attribute values, default is for mono display + */ +chtype attributes[] = +{ + A_NORMAL, /* screen_attr */ + A_NORMAL, /* shadow_attr */ + A_NORMAL, /* dialog_attr */ + A_BOLD, /* title_attr */ + A_NORMAL, /* border_attr */ + A_REVERSE, /* button_active_attr */ + A_DIM, /* button_inactive_attr */ + A_REVERSE, /* button_key_active_attr */ + A_BOLD, /* button_key_inactive_attr */ + A_REVERSE, /* button_label_active_attr */ + A_NORMAL, /* button_label_inactive_attr */ + A_NORMAL, /* inputbox_attr */ + A_NORMAL, /* inputbox_border_attr */ + A_NORMAL, /* searchbox_attr */ + A_BOLD, /* searchbox_title_attr */ + A_NORMAL, /* searchbox_border_attr */ + A_BOLD, /* position_indicator_attr */ + A_NORMAL, /* menubox_attr */ + A_NORMAL, /* menubox_border_attr */ + A_NORMAL, /* item_attr */ + A_REVERSE, /* item_selected_attr */ + A_BOLD, /* tag_attr */ + A_REVERSE, /* tag_selected_attr */ + A_BOLD, /* tag_key_attr */ + A_REVERSE, /* tag_key_selected_attr */ + A_BOLD, /* check_attr */ + A_REVERSE, /* check_selected_attr */ + A_BOLD, /* uarrow_attr */ + A_BOLD /* darrow_attr */ +}; + + +#include "colors.h" + +/* + * Table of color values + */ +int color_table[][3] = +{ + {SCREEN_FG, SCREEN_BG, SCREEN_HL}, + {SHADOW_FG, SHADOW_BG, SHADOW_HL}, + {DIALOG_FG, DIALOG_BG, DIALOG_HL}, + {TITLE_FG, TITLE_BG, TITLE_HL}, + {BORDER_FG, BORDER_BG, BORDER_HL}, + {BUTTON_ACTIVE_FG, BUTTON_ACTIVE_BG, BUTTON_ACTIVE_HL}, + {BUTTON_INACTIVE_FG, BUTTON_INACTIVE_BG, BUTTON_INACTIVE_HL}, + {BUTTON_KEY_ACTIVE_FG, BUTTON_KEY_ACTIVE_BG, BUTTON_KEY_ACTIVE_HL}, + {BUTTON_KEY_INACTIVE_FG, BUTTON_KEY_INACTIVE_BG, BUTTON_KEY_INACTIVE_HL}, + {BUTTON_LABEL_ACTIVE_FG, BUTTON_LABEL_ACTIVE_BG, BUTTON_LABEL_ACTIVE_HL}, + {BUTTON_LABEL_INACTIVE_FG, BUTTON_LABEL_INACTIVE_BG, + BUTTON_LABEL_INACTIVE_HL}, + {INPUTBOX_FG, INPUTBOX_BG, INPUTBOX_HL}, + {INPUTBOX_BORDER_FG, INPUTBOX_BORDER_BG, INPUTBOX_BORDER_HL}, + {SEARCHBOX_FG, SEARCHBOX_BG, SEARCHBOX_HL}, + {SEARCHBOX_TITLE_FG, SEARCHBOX_TITLE_BG, SEARCHBOX_TITLE_HL}, + {SEARCHBOX_BORDER_FG, SEARCHBOX_BORDER_BG, SEARCHBOX_BORDER_HL}, + {POSITION_INDICATOR_FG, POSITION_INDICATOR_BG, POSITION_INDICATOR_HL}, + {MENUBOX_FG, MENUBOX_BG, MENUBOX_HL}, + {MENUBOX_BORDER_FG, MENUBOX_BORDER_BG, MENUBOX_BORDER_HL}, + {ITEM_FG, ITEM_BG, ITEM_HL}, + {ITEM_SELECTED_FG, ITEM_SELECTED_BG, ITEM_SELECTED_HL}, + {TAG_FG, TAG_BG, TAG_HL}, + {TAG_SELECTED_FG, TAG_SELECTED_BG, TAG_SELECTED_HL}, + {TAG_KEY_FG, TAG_KEY_BG, TAG_KEY_HL}, + {TAG_KEY_SELECTED_FG, TAG_KEY_SELECTED_BG, TAG_KEY_SELECTED_HL}, + {CHECK_FG, CHECK_BG, CHECK_HL}, + {CHECK_SELECTED_FG, CHECK_SELECTED_BG, CHECK_SELECTED_HL}, + {UARROW_FG, UARROW_BG, UARROW_HL}, + {DARROW_FG, DARROW_BG, DARROW_HL}, +}; /* color_table */ + +/* + * Set window to attribute 'attr' + */ +void +attr_clear (WINDOW * win, int height, int width, chtype attr) +{ + int i, j; + + wattrset (win, attr); + for (i = 0; i < height; i++) { + wmove (win, i, 0); + for (j = 0; j < width; j++) + waddch (win, ' '); + } + touchwin (win); +} + +void dialog_clear (void) +{ + attr_clear (stdscr, LINES, COLS, screen_attr); + /* Display background title if it exists ... - SLH */ + if (backtitle != NULL) { + int i; + + wattrset (stdscr, screen_attr); + mvwaddstr (stdscr, 0, 1, (char *)backtitle); + wmove (stdscr, 1, 1); + for (i = 1; i < COLS - 1; i++) + waddch (stdscr, ACS_HLINE); + } + wnoutrefresh (stdscr); +} + +/* + * Do some initialization for dialog + */ +void +init_dialog (void) +{ + initscr (); /* Init curses */ + keypad (stdscr, TRUE); + cbreak (); + noecho (); + + + if (use_colors) /* Set up colors */ + color_setup (); + + + dialog_clear (); +} + +/* + * Setup for color display + */ +void +color_setup (void) +{ + int i; + + if (has_colors ()) { /* Terminal supports color? */ + start_color (); + + /* Initialize color pairs */ + for (i = 0; i < ATTRIBUTE_COUNT; i++) + init_pair (i + 1, color_table[i][0], color_table[i][1]); + + /* Setup color attributes */ + for (i = 0; i < ATTRIBUTE_COUNT; i++) + attributes[i] = C_ATTR (color_table[i][2], i + 1); + } +} + +/* + * End using dialog functions. + */ +void +end_dialog (void) +{ + endwin (); +} + + +/* + * Print a string of text in a window, automatically wrap around to the + * next line if the string is too long to fit on one line. Newline + * characters '\n' are replaced by spaces. We start on a new line + * if there is no room for at least 4 nonblanks following a double-space. + */ +void +print_autowrap (WINDOW * win, const char *prompt, int width, int y, int x) +{ + int newl, cur_x, cur_y; + int i, prompt_len, room, wlen; + char tempstr[MAX_LEN + 1], *word, *sp, *sp2; + + strcpy (tempstr, prompt); + + prompt_len = strlen(tempstr); + + /* + * Remove newlines + */ + for(i=0; i<prompt_len; i++) { + if(tempstr[i] == '\n') tempstr[i] = ' '; + } + + if (prompt_len <= width - x * 2) { /* If prompt is short */ + wmove (win, y, (width - prompt_len) / 2); + waddstr (win, tempstr); + } else { + cur_x = x; + cur_y = y; + newl = 1; + word = tempstr; + while (word && *word) { + sp = index(word, ' '); + if (sp) + *sp++ = 0; + + /* Wrap to next line if either the word does not fit, + or it is the first word of a new sentence, and it is + short, and the next word does not fit. */ + room = width - cur_x; + wlen = strlen(word); + if (wlen > room || + (newl && wlen < 4 && sp && wlen+1+strlen(sp) > room + && (!(sp2 = index(sp, ' ')) || wlen+1+(sp2-sp) > room))) { + cur_y++; + cur_x = x; + } + wmove (win, cur_y, cur_x); + waddstr (win, word); + getyx (win, cur_y, cur_x); + cur_x++; + if (sp && *sp == ' ') { + cur_x++; /* double space */ + while (*++sp == ' '); + newl = 1; + } else + newl = 0; + word = sp; + } + } +} + +/* + * Print a button + */ +void +print_button (WINDOW * win, const char *label, int y, int x, int selected) +{ + int i, temp; + + wmove (win, y, x); + wattrset (win, selected ? button_active_attr : button_inactive_attr); + waddstr (win, "<"); + temp = strspn (label, " "); + label += temp; + wattrset (win, selected ? button_label_active_attr + : button_label_inactive_attr); + for (i = 0; i < temp; i++) + waddch (win, ' '); + wattrset (win, selected ? button_key_active_attr + : button_key_inactive_attr); + waddch (win, label[0]); + wattrset (win, selected ? button_label_active_attr + : button_label_inactive_attr); + waddstr (win, (char *)label + 1); + wattrset (win, selected ? button_active_attr : button_inactive_attr); + waddstr (win, ">"); + wmove (win, y, x + temp + 1); +} + +/* + * Draw a rectangular box with line drawing characters + */ +void +draw_box (WINDOW * win, int y, int x, int height, int width, + chtype box, chtype border) +{ + int i, j; + + wattrset (win, 0); + for (i = 0; i < height; i++) { + wmove (win, y + i, x); + for (j = 0; j < width; j++) + if (!i && !j) + waddch (win, border | ACS_ULCORNER); + else if (i == height - 1 && !j) + waddch (win, border | ACS_LLCORNER); + else if (!i && j == width - 1) + waddch (win, box | ACS_URCORNER); + else if (i == height - 1 && j == width - 1) + waddch (win, box | ACS_LRCORNER); + else if (!i) + waddch (win, border | ACS_HLINE); + else if (i == height - 1) + waddch (win, box | ACS_HLINE); + else if (!j) + waddch (win, border | ACS_VLINE); + else if (j == width - 1) + waddch (win, box | ACS_VLINE); + else + waddch (win, box | ' '); + } +} + +/* + * Draw shadows along the right and bottom edge to give a more 3D look + * to the boxes + */ +void +draw_shadow (WINDOW * win, int y, int x, int height, int width) +{ + int i; + + if (has_colors ()) { /* Whether terminal supports color? */ + wattrset (win, shadow_attr); + wmove (win, y + height, x + 2); + for (i = 0; i < width; i++) + waddch (win, winch (win) & A_CHARTEXT); + for (i = y + 1; i < y + height + 1; i++) { + wmove (win, i, x + width); + waddch (win, winch (win) & A_CHARTEXT); + waddch (win, winch (win) & A_CHARTEXT); + } + wnoutrefresh (win); + } +} + +/* + * Return the position of the first alphabetic character in a string. + */ +int +first_alpha(const char *string, const char *exempt) +{ + int i, in_paren=0, c; + + for (i = 0; i < strlen(string); i++) { + c = tolower(string[i]); + + if (strchr("<[(", c)) ++in_paren; + if (strchr(">])", c)) --in_paren; + + if ((! in_paren) && isalpha(c) && + strchr(exempt, c) == 0) + return i; + } + + return 0; +} diff --git a/config/scripts/lxdialog/yesno.c b/config/scripts/lxdialog/yesno.c new file mode 100644 index 0000000..11fcc25 --- /dev/null +++ b/config/scripts/lxdialog/yesno.c @@ -0,0 +1,118 @@ +/* + * yesno.c -- implements the yes/no box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "dialog.h" + +/* + * Display termination buttons + */ +static void +print_buttons(WINDOW *dialog, int height, int width, int selected) +{ + int x = width / 2 - 10; + int y = height - 2; + + print_button (dialog, " Yes ", y, x, selected == 0); + print_button (dialog, " No ", y, x + 13, selected == 1); + + wmove(dialog, y, x+1 + 13*selected ); + wrefresh (dialog); +} + +/* + * Display a dialog box with two buttons - Yes and No + */ +int +dialog_yesno (const char *title, const char *prompt, int height, int width) +{ + int i, x, y, key = 0, button = 0; + WINDOW *dialog; + + /* center dialog box on screen */ + x = (COLS - width) / 2; + y = (LINES - height) / 2; + + draw_shadow (stdscr, y, x, height, width); + + dialog = newwin (height, width, y, x); + keypad (dialog, TRUE); + + draw_box (dialog, 0, 0, height, width, dialog_attr, border_attr); + wattrset (dialog, border_attr); + mvwaddch (dialog, height-3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch (dialog, ACS_HLINE); + wattrset (dialog, dialog_attr); + waddch (dialog, ACS_RTEE); + + if (title != NULL && strlen(title) >= width-2 ) { + /* truncate long title -- mec */ + char * title2 = malloc(width-2+1); + memcpy( title2, title, width-2 ); + title2[width-2] = '\0'; + title = title2; + } + + if (title != NULL) { + wattrset (dialog, title_attr); + mvwaddch (dialog, 0, (width - strlen(title))/2 - 1, ' '); + waddstr (dialog, (char *)title); + waddch (dialog, ' '); + } + + wattrset (dialog, dialog_attr); + print_autowrap (dialog, prompt, width - 2, 1, 3); + + print_buttons(dialog, height, width, 0); + + while (key != ESC) { + key = wgetch (dialog); + switch (key) { + case 'Y': + case 'y': + delwin (dialog); + return 0; + case 'N': + case 'n': + delwin (dialog); + return 1; + + case TAB: + case KEY_LEFT: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 1 : (button > 1 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh (dialog); + break; + case ' ': + case '\n': + delwin (dialog); + return button; + case ESC: + break; + } + } + + delwin (dialog); + return -1; /* ESC pressed */ +} diff --git a/include/CVS/Entries b/include/CVS/Entries new file mode 100644 index 0000000..6cbbb70 --- /dev/null +++ b/include/CVS/Entries @@ -0,0 +1,2 @@ +/aversive.h/1.1.2.6/Mon May 18 12:19:51 2009//Tb_zer0 +D/aversive//// diff --git a/include/CVS/Repository b/include/CVS/Repository new file mode 100644 index 0000000..24f2bb0 --- /dev/null +++ b/include/CVS/Repository @@ -0,0 +1 @@ +aversive/include diff --git a/include/CVS/Root b/include/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/include/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/include/CVS/Tag b/include/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/include/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/include/CVS/Template b/include/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/include/aversive.h b/include/aversive.h new file mode 100644 index 0000000..c61c409 --- /dev/null +++ b/include/aversive.h @@ -0,0 +1,269 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: aversive.h,v 1.1.2.6 2009-05-18 12:19:51 zer0 Exp $ + * + */ + +/** + * here are some cute little macros, and other stuff, microcontroller + * related ! + */ + + +#ifndef _AVERSIVE_H_ +#define _AVERSIVE_H_ + +#include <autoconf.h> + +#ifndef HOST_VERSION +#include <avr/interrupt.h> +#include <avr/io.h> +#endif + +#include <aversive/types.h> +#include <aversive/errno.h> +#include <aversive/irq_lock.h> + + +#ifndef __AVR_LIBC_VERSION__ /* version.h should be included by avr/io.h */ +#define __AVR_LIBC_VERSION__ 0UL +#endif + +#ifndef HOST_VERSION +#if __AVR_LIBC_VERSION__ < 10403UL +#include <avr/signal.h> +#endif +#endif + +#define F_CPU ((unsigned long)CONFIG_QUARTZ) + +#define Hz 1l +#define KHz 1000l +#define MHz 1000000l + + + +/* + * a few "mathematical" macros : maximums and minimums + */ + +/** + * signed maxmimum : both signs are tested + */ +#define S_MAX(to_saturate, value_max) \ +do { \ + if (to_saturate > value_max) \ + to_saturate = value_max; \ + else if (to_saturate < -value_max) \ + to_saturate = -value_max; \ + } while(0) + +/** + * unsigned maximum : result >0 is forced + */ +#define U_MAX(to_saturate, value_max) \ +do { \ + if (to_saturate > value_max) \ + to_saturate = value_max; \ + else if (to_saturate < 0) \ + to_saturate = 0; \ + } while(0) + +/** + * simple maximum + */ +#define MAX(to_saturate, value_max) \ +do { \ + if (to_saturate > value_max) \ + to_saturate = value_max; \ +} while(0) + +/** + * simple minimum + */ +#define MIN(to_saturate, value_min) \ +do { \ + if (to_saturate < value_min) \ + to_saturate = value_min; \ +} while(0) + + +/** absolute + * while the abs() function in the libc works only with int type + * this macro works with every numerical type including floats + */ +#define ABS(val) ({ \ + __typeof(val) __val = (val); \ + if (__val < 0) \ + __val = - __val; \ + __val; \ + }) + +/* + * Extract bytes and u16 from larger integer + */ + +#if __BYTE_ORDER != __LITTLE_ENDIAN && __BYTE_ORDER != __BIG_ENDIAN +# error "Endianness not defined" +#endif + +struct extract32 { + union { + struct { +#if __BYTE_ORDER == __LITTLE_ENDIAN + uint8_t u8_0; + uint8_t u8_1; + uint8_t u8_2; + uint8_t u8_3; +#elif __BYTE_ORDER == __BIG_ENDIAN + uint8_t u8_3; + uint8_t u8_2; + uint8_t u8_1; + uint8_t u8_0; +#endif + } __attribute__ ((packed)) u8; + struct { +#if __BYTE_ORDER == __LITTLE_ENDIAN + uint16_t u16_0; + uint16_t u16_1; +#elif __BYTE_ORDER == __BIG_ENDIAN + uint16_t u16_1; + uint16_t u16_0; +#endif + } __attribute__ ((packed)) u16; + struct { +#if __BYTE_ORDER == __LITTLE_ENDIAN + uint8_t u8_0; + uint16_t u16_mid; + uint8_t u8_3; +#elif __BYTE_ORDER == __BIG_ENDIAN + uint8_t u8_3; + uint16_t u16_mid; + uint8_t u8_0; +#endif + } __attribute__ ((packed)) u16_b; + uint32_t u32; + } __attribute__ ((packed)) u; +} __attribute__ ((packed)); + +#define extr32_08_0(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_0; }) +#define extr32_08_1(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_1; }) +#define extr32_08_2(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_2; }) +#define extr32_08_3(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_3; }) + +#define extr32_16_0(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u16.u16_0; }) +#define extr32_16_1(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u16.u16_1; }) +#define extr32_16_mid(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u16_b.u16_mid; }) + + +struct extract16 { + union { + struct { +#if __BYTE_ORDER == __LITTLE_ENDIAN + uint8_t u8_0; + uint8_t u8_1; +#elif __BYTE_ORDER == __BIG_ENDIAN + uint8_t u8_1; + uint8_t u8_0; +#endif + } __attribute__ ((packed)) u8; + uint16_t u16; + } __attribute__ ((packed)) u; +} __attribute__ ((packed)); + +#define extr16_08_0(i) ({ struct extract16 __x; __x.u.u16 = i; __x.u.u8.u8_0; }) +#define extr16_08_1(i) ({ struct extract16 __x; __x.u.u16 = i; __x.u.u8.u8_1; }) + + + +/* a few asm utilities */ + +#ifndef HOST_VERSION +#ifndef nop +#define nop() __asm__ __volatile__ ("NOP\n") /** nop instruction, 1 CPU cycle consumed */ +#endif +#ifndef nothing +#define nothing() __asm__ __volatile__ (" \n") /** nothing */ +#endif +#ifndef cli +#define cli() __asm__ __volatile__ ("CLI\n") /** disable interrupts */ +#endif +#ifndef sei +#define sei() __asm__ __volatile__ ("SEI\n") /** enable interrupts */ +#endif +/** simple software reset, but doesn't initialize the registers */ +#ifndef reset +#define reset() \ +do { \ + __asm__ __volatile__ ("ldi r30,0\n"); \ + __asm__ __volatile__ ("ldi r31,0\n"); \ + __asm__ __volatile__ ("ijmp\n"); \ +} while(0) +#endif + +#else /* HOST_VERSION */ +#define nop() do {} while(0) +#define nothing() do {} while(0) +#define cli() do {} while(0) +#define sei() do {} while(0) +#endif /* HOST_VERSION */ + +/** + * little bit toggeling macro + * + * change pin state + * usage : + * BIT_TOGGLE(PORTB,2) to make the pin 2 of PORTB toggle + */ +#define BIT_TOGGLE(port,bit) do {\ + if(bit_is_set(PIN(port),bit)) \ + cbi(port,bit); \ + else \ + sbi(port,bit); \ + } while(0) + + +/** booleans */ +#define FALSE 0 +#define TRUE 1 +#define False FALSE +#define false FALSE +#define True TRUE +#define true TRUE + + +/** DDR and PINS from port adress */ +#define DDR(port) (*(&(port) -1)) +#define PIN(port) (*(&(port) -2)) + +/** open collector simulation macros */ +#define OPEN_CO_INIT(port, bit) sbi(port,bit) +#define OPEN_CO_HIGH(port, bit) cbi(DDR(port),bit) +#define OPEN_CO_LOW(port, bit) cbi(DDR(port),bit) + +/** deprecated macros in libc, but they're almost used, so we implement them again ;) */ +#ifndef cbi +#define cbi(sfr, bit) ( sfr &= ~ _BV(bit)) +#endif +#ifndef sbi +#define sbi(sfr, bit) ( sfr |= _BV(bit)) +#endif + + +#endif /* ifndef _AVERSIVE_H_ */ + diff --git a/include/aversive/CVS/Entries b/include/aversive/CVS/Entries new file mode 100644 index 0000000..a9f0370 --- /dev/null +++ b/include/aversive/CVS/Entries @@ -0,0 +1,11 @@ +/errno.h/1.1.2.2/Fri Jan 23 23:05:39 2009//Tb_zer0 +/error.h/1.1.2.2/Fri Jun 1 09:37:22 2007//Tb_zer0 +/irq_lock.h/1.1.2.1/Wed May 23 17:18:09 2007//Tb_zer0 +/list.h/1.1.2.4/Sun Aug 19 10:35:45 2007//Tb_zer0 +/parts.h/1.1.2.2/Fri Jan 23 22:53:08 2009//Tb_zer0 +/pgmspace.h/1.1.2.4/Wed Nov 21 21:54:38 2007//Tb_zer0 +/queue.h/1.1.2.1/Wed May 23 17:18:09 2007//Tb_zer0 +/timers.h/1.1.2.4/Fri Jan 23 23:54:16 2009//Tb_zer0 +/types.h/1.1.2.1/Wed May 23 17:18:09 2007//Tb_zer0 +/wait.h/1.1.2.1/Wed May 23 17:18:09 2007//Tb_zer0 +D/parts//// diff --git a/include/aversive/CVS/Repository b/include/aversive/CVS/Repository new file mode 100644 index 0000000..49c7b0f --- /dev/null +++ b/include/aversive/CVS/Repository @@ -0,0 +1 @@ +aversive/include/aversive diff --git a/include/aversive/CVS/Root b/include/aversive/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/include/aversive/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/include/aversive/CVS/Tag b/include/aversive/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/include/aversive/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/include/aversive/CVS/Template b/include/aversive/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/include/aversive/errno.h b/include/aversive/errno.h new file mode 100644 index 0000000..766c48c --- /dev/null +++ b/include/aversive/errno.h @@ -0,0 +1,73 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: errno.h,v 1.1.2.2 2009-01-23 23:05:39 zer0 Exp $ + * + */ + +/* This file contains general errors that can be returned from functions + * We have to be carreful and try to return these error as often as possible + * isntead of a function-specific value + */ + +#ifndef _AVERSIVE_ERRNO_H_ +#define _AVERSIVE_ERRNO_H_ + +#ifndef HOST_VERSION + +/* from avr-libc, does not define a lots of errors */ +#include <errno.h> + +/** No error */ +#define ESUCCESS 0 +/** Operation not permitted */ +#define EPERM 1 +/** No such file or directory */ +#define ENOENT 2 +/** I/O error */ +#define EIO 5 +/** No such device or address */ +#define ENXIO 6 +/** Argument list too long */ +#define E2BIG 7 +/** Try again */ +#define EAGAIN 11 +/** Out of memory */ +#define ENOMEM 12 +/** Bad address */ +#define EFAULT 14 +/** Device or resource busy */ +#define EBUSY 16 +/** Invalid argument */ +#define EINVAL 22 +/** Domain error */ +/* #define EDOM 33 */ /* in libc */ +/** Range error */ +/* #define ERANGE 34 */ /* in libc */ +/** Not supported */ +#define ENOTSUP 126 /* the correct number is 128 */ +/** Unkwow error */ +#define EUNKNOW 127 + +/* must not be > 127 because it can be stored on an int8_t */ + +#else /* HOST_VERSION */ +#include <sys/errno.h> + +#endif /* HOST_VERSION */ + +#endif /* AVERSIVE_ERRNO_H_ */ diff --git a/include/aversive/error.h b/include/aversive/error.h new file mode 100644 index 0000000..c34028a --- /dev/null +++ b/include/aversive/error.h @@ -0,0 +1,42 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error.h,v 1.1.2.2 2007-06-01 09:37:22 zer0 Exp $ + * + */ + +#ifndef _AVERSIVE_ERROR_H_ +#define _AVERSIVE_ERROR_H_ + +#include <autoconf.h> + +#ifdef CONFIG_MODULE_ERROR +#include <error.h> +#else + +#define EMERG(num, text...) do {} while(0) + +#define ERROR(num, text...) do {} while(0) + +#define WARNING(num, text...) do {} while(0) + +#define NOTICE(num, text...) do {} while(0) + +#define DEBUG(num, text...) do {} while(0) + +#endif +#endif diff --git a/include/aversive/irq_lock.h b/include/aversive/irq_lock.h new file mode 100644 index 0000000..c8afdc4 --- /dev/null +++ b/include/aversive/irq_lock.h @@ -0,0 +1,65 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: irq_lock.h,v 1.1.2.1 2007-05-23 17:18:09 zer0 Exp $ + * + */ + +/** \file modules/base/utils/irq_lock_macros.h + * \brief Interface of the utils module + * + * here are defined the three macros : + * + * IRQ_LOCK(flags); this saves interrupt state + * IRQ_UNLOCK(flags); this restores interrupt state + * + * code example follows: + * + * uint8_t flags; + * IRQ_LOCK(flags); + * // code to be protected against interrupts ... + * IRQ_UNLOCK(flags); // needs to be associated with an unlock + * + */ + + +#ifndef _AVERSIVE_IRQ_LOCK_H_ +#define _AVERSIVE_IRQ_LOCK_H_ + +#ifdef HOST_VERSION + +/* we must use 'flags' to avoid a warning */ +#define IRQ_UNLOCK(flags) flags=0 +#define IRQ_LOCK(flags) flags=0 +#define GLOBAL_IRQ_ARE_MASKED() (1) + +#else + +#define GLOBAL_IRQ_ARE_MASKED() (!(bit_is_set(SREG,7))) + +#define IRQ_LOCK(flags) do { \ + flags = SREG; \ + cli(); \ + } while(0) + +#define IRQ_UNLOCK(flags) do { \ + SREG = flags; \ + } while ( 0 ) + +#endif /* ! HOST_VERSION */ + +#endif /* _AVERSIVE_IRQ_LOCK_H_ */ diff --git a/include/aversive/list.h b/include/aversive/list.h new file mode 100644 index 0000000..98c2e2f --- /dev/null +++ b/include/aversive/list.h @@ -0,0 +1,532 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: list.h,v 1.1.2.4 2007-08-19 10:35:45 zer0 Exp $ + * + */ + +/** + * This header file provides LISTs implemented in tables. Don't use + * list size > 127. + * + * WARNING --------------------- + * This header file will probably be deprecated in a soon. + * future. Consider using the 'cirbuf' module (circular buffer) instead. + * Indeed, the full-macro implementation of this header file is not + * the most efficient in terms of code size.... :) + * WARNING --------------------- + * + * + * Header + * ------ + * + * struct list_hdr { + * u08 size; < The size of the fifo + * u08 cur_size; < number of data in the fifo + * u08 beg_indice; < indice of the first elt + * u08 read_cursor; < read cursor + * } __attribute__ ((packed)); + * + * + * --------------------------------------------- + * I I I I I + * I size IcursizeI beg I rcurs I elements ... + * I I I I I + * --------------------------------------------- + * + * <-------------------------------> + * list_hdr + * + * + * Data + * ---- + * + * Data are stored in a circular buffer, beginning is specified by + * beg_indice in header. + * + * + * Type + * ---- + * + * For example, the type of a list of u08 with 10 elements is : + * + * struct list_u08_10 { + * struct list_hdr hdr; + * u08 elt[10]; + * } + * + * - With this example, an empty list is : + * size = 10 + * cursize = 0 + * beg = X + * curs = X + * + * - A full list : + * size = 10 + * cursize = 10 + * beg = X + * curs = X + * + * + * Functions & Macros + * ------------------ + * + * ********** Define and init + * + * LIST_TYPE(typename, elttype, size) -> define type : + * + * #define LIST_TYPE(typename, elttype, size) + * typedef struct typename { + * struct list_hdr hdr; + * elttype elt[size]; + * } typename; + * + * LIST_INIT(list, beginning) -> flushes the list, and set size and beginning + * + * + * ********** Control + * + * u08 LIST_FULL(list) + * u08 LIST_EMPTY(list) + * + * u08 LIST_READ_GOTO(*elt, list, i) -> place the read cursor at position i (0 means + * the beginning of the list) and set the elt if + * pointer not NULL + * + * u08 LIST_READ_LEFT(*elt, list, i) -> move the read cursor left by i + * u08 LIST_READ_RIGHT(*elt, list, i) -> move the read cursor right by i + * u08 LIST_READ_START(*elt, list) + * u08 LIST_READ_END(*elt, list) + * + * Examples : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 3 2 3 X X A B C X + * + * + * we do LIST_READ_LEFT(NULL, x,x, 1) : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 3 2 2 X X A B C X + * + * + * we do LIST_READ_LEFT(NULL, x,x, 1), but return 1 instead of 0 because we + * overwrapped : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 3 4 4 X X A B C X + * + * + * we do LIST_READ_GOTO(NULL, x,x, 0) : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 3 4 2 X X A B C X + * + * + * + * ********** accesses modifying the list + * + * u08 LIST_PUSH_START(elt, list) -> add at the beginning (prepend) + * u08 LIST_PUSH_END(elt, list) -> add at the end (append) + * u08 LIST_PULL_START(elt *, list) -> del at the beginning + * u08 LIST_PULL_END(elt *, list) -> del at the end + * + * u08 LIST_ARRAY_PUSH_START(*elt, list, n) -> prepend n elts + * from elt pointer + * u08 LIST_ARRAY_PUSH_END(*elt, list, n) -> append n elts + * u08 LIST_ARRAY_PULL_START(elt *, list, n) -> del n elts from buffer + * u08 LIST_ARRAY_PULL_END(elt *, list, n) -> del at the end + * + * Examples : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 4 2 3 X X B C D E + * + * + * we do LIST_PUSH_START(A, l, u08) : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 5 1 3 X A B C D E + * + * + * we do LIST_PUSH_END(F, l, u08) : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 6 1 3 F A B C D E + * + * we do LIST_PUSH_END(X, l, u08) -> return -1 + * + * + * + * ********** Accesses NOT modifying the list + * + * u08 LIST_FIRST(elt *, list) -> Return the first elt + * u08 LIST_LAST(elt *, list) -> Return the last elt + * + * u08 LIST_READ(elt *, list) -> Return the elt pointed by + * the read cursor + * + * u08 LIST_ARRAY_READ(elt *, list, n) -> reads n elts from read cursor + * + * u08 LIST_READ_GET_PTR(list) -> return a pointer to the read + * cursor. Warning, perhaps you need to do LIST_ALIGN_XXXX() before + * + * ********** loop functions + * + * #define LIST_FOREACH(list, elt) + * for( u08 ret = LIST_READ_START(elt, list) ; + * ret == 0 ; + * ret = LIST_READ_RIGHT(*elt, list, 1) ) + * + * + * ********** Alignement functions + * + * these functions can by quite long to execute. If possible, try to + * avoid using them by choosing a good place for the beg_indice when + * calling init of list. If you need it, prefer using + * LIST_ALIGN_CONTINUOUS if possible. + * + * u08 LIST_ALIGN_LEFT(list) + * u08 LIST_ALIGN_RIGHT(list) + * u08 LIST_ALIGN_CONTINUOUS(list) -> just try to put data in a + * countinuous memory region in + * minimum operations. + * + * Example : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 4 3 4 D X X A B C + * + * + * we do LIST_ALIGN_LEFT(list) : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 4 0 1 A B C D X X + * + * we do LIST_ALIGN_RIGHT(list) : + * + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 4 2 3 X X A B C D + * + * + * With these functions, you can easily imagine a network stack, + * prepending headers to data, without copying the buffer multiple times. + * + * Example : + * + * LIST_INIT(mylist, 5) + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 0 5 5 X X X X X X + * + * LIST_ARRAY_PUSH_START("DATA", mylist, u08, strlen("DATA")) + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 4 2 5 X X D A T A + * + * LIST_PUSH_START('H', mylist, u08) (push header) + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 5 1 5 X H D A T A + * + * LIST_PUSH_START('H', mylist, u08) (push another header) + * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 | + * 6 6 0 5 H H D A T A + * + */ + + +#ifndef _AVERSIVE_LIST_H_ +#define _AVERSIVE_LIST_H_ + +#ifndef LIST_DEBUG +#define LIST_DEBUG 0 +#endif + +#include <stdio.h> + +#define WOVERWRAPPED -1 + +#ifdef HOST_VERSION +#define CR "\n" +#else +#define CR "\r\n" +#endif + +#include <aversive.h> + +/** + * This structure is the header of a list type. + */ +struct list_hdr { + uint8_t size; /**< The size of the list (number of elements) */ + uint8_t cur_size; /**< number of data in the list */ + uint8_t beg_indice; /**< indice of the first elt */ + int8_t read_cursor; /**< read cursor */ +} __attribute__ ((packed)); + +/** + * This is a generic kind of list, in which we suppose that elements + * are char +*/ +struct generic_list { + struct list_hdr hdr; + char elt[0]; +} __attribute__ ((packed)); + + +/** + * Define a new list type + */ +#define LIST_TYPEDEF(typename, elttype, size) \ +typedef struct typename { \ + struct list_hdr hdr; \ + elttype elt[size]; \ +} typename; + +#define LIST_INIT(list, beginning) \ +do { \ + list.hdr.size = sizeof(list.elt)/sizeof(list.elt[0]); \ + list.hdr.cur_size = 0; \ + list.hdr.beg_indice = beginning; \ + list.hdr.read_cursor = beginning; \ +} while(0) + + +/** + * Return 1 if the list is full + */ +#define LIST_FULL(list) (list.hdr.size == list.hdr.cur_size) + +/** + * Return 1 if the list is empty + */ +#define LIST_EMPTY(list) (list.hdr.cur_size == 0) + +/** + * return current size of the list (number of used elements) + */ +#define LIST_CURSIZE(list) (list.hdr.cur_size) + +/** + * return size of the list (used + free elements) + */ +#define LIST_SIZE(list) (list.hdr.size) + +/** + * return the number of free elts + */ +#define LIST_FREESIZE(list) (list.hdr.size-list.hdr.cur_size) + + + +#define LIST_READ_START(list, elt_p) ({ \ + uint8_t __ret=0; \ + list.hdr.read_cursor = 0 ; \ + *elt_p = list.elt[list.hdr.beg_indice] ; \ + if(LIST_DEBUG) \ + printf("LIST_READ_START(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \ + __ret; \ +}) + +#define LIST_READ_END(list, elt_p) ({ \ + uint8_t __ret=0; \ + list.hdr.read_cursor = list.hdr.cur_size-1; \ + *elt_p = list.elt[(list.hdr.beg_indice-1+list.hdr.cur_size) % list.hdr.size] ; \ + if(LIST_DEBUG) \ + printf("LIST_READ_END(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \ + __ret; \ +}) + + +#define LIST_READ_GOTO(list, elt_p, i) ({ \ + uint8_t __ret=0; \ + if( (i<0) || (i>=list.hdr.cur_size) ) \ + __ret = EINVAL; \ + else { \ + list.hdr.read_cursor = i; \ + *elt_p = list.elt[(list.hdr.beg_indice+i) % list.hdr.size] ; \ + } \ + if(LIST_DEBUG) \ + printf("LIST_READ_GOTO(%s, %s, %d) -> ret %d"CR,#list, #elt_p, i, __ret); \ + __ret; \ +}) + +#define LIST_READ_MOVE(list, elt_p, i) ({\ +uint8_t __ret=0; \ + if (i<0) { \ + if( (-i) > list.hdr.read_cursor ) \ + __ret = WOVERWRAPPED ; \ + list.hdr.read_cursor -= ((-i) % list.hdr.cur_size) ; \ + if (list.hdr.read_cursor < 0) \ + list.hdr.read_cursor += list.hdr.cur_size ; \ + } \ + else { \ + if( i >= list.hdr.cur_size - list.hdr.read_cursor ) \ + __ret = WOVERWRAPPED ; \ + list.hdr.read_cursor += (i % list.hdr.cur_size) ; \ + if (list.hdr.read_cursor >= list.hdr.cur_size) \ + list.hdr.read_cursor -= list.hdr.cur_size ; \ + } \ + if(LIST_DEBUG) \ + printf("LIST_READ_MOVE(%s, %s, %d) -> ret %d"CR,#list, #elt_p, i, __ret); \ + *elt_p = list.elt[(list.hdr.beg_indice+list.hdr.read_cursor) % list.hdr.size] ; \ + __ret; \ +}) + +#define LIST_READ(list, elt_p) ({\ + *elt_p = list.elt[(list.hdr.beg_indice+list.hdr.read_cursor) % list.hdr.size] ; \ + 0; \ +}) + +#define LIST_PUSH_START(list, e) ({ \ + uint8_t __ret=0; \ + if( LIST_FULL(list) ) \ + __ret=EINVAL; \ + else { \ + list.hdr.beg_indice = (list.hdr.beg_indice-1+list.hdr.size) % list.hdr.size; \ + list.elt [ list.hdr.beg_indice ] = e ; \ + list.hdr.cur_size ++ ; \ + } \ +if(LIST_DEBUG) \ + printf("LIST_PUSH_START(%s, %s) -> ret %d"CR,#list, #e, __ret); \ + __ret; \ +}) + +#define LIST_PUSH_END(list, e) ({ \ + uint8_t __ret=0; \ + if( LIST_FULL(list) ) \ + __ret=EINVAL; \ + else { \ + list.elt [ (list.hdr.beg_indice+list.hdr.cur_size) % list.hdr.size ] = e ; \ + list.hdr.cur_size ++ ; \ + } \ +if(LIST_DEBUG) \ + printf("LIST_PUSH_END(%s, %s) -> ret %d"CR,#list, #e, __ret); \ + __ret; \ +}) + +#define LIST_PULL_START(list, elt_p) ({ \ + uint8_t __ret=0; \ + if( LIST_EMPTY(list) ) \ + __ret=EINVAL; \ + else { \ + *elt_p = list.elt [ list.hdr.beg_indice ] ; \ + list.hdr.beg_indice = (list.hdr.beg_indice+1) % list.hdr.size; \ + list.hdr.cur_size -- ; \ + } \ +if(LIST_DEBUG) \ + printf("LIST_PULL_START(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \ + __ret; \ +}) + +#define LIST_PULL_END(list, elt_p) ({ \ + uint8_t __ret=0; \ + if( LIST_EMPTY(list) ) \ + __ret=EINVAL; \ + else { \ + *elt_p = list.elt [ (list.hdr.beg_indice-1+list.hdr.cur_size) % list.hdr.size ] ; \ + list.hdr.cur_size -- ; \ + } \ +if(LIST_DEBUG) \ + printf("LIST_PULL_END(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \ + __ret; \ +}) + +/* start by the last elt */ +#define LIST_ARRAY_PUSH_START(list, array, nb) ({\ + uint8_t __ret=0; \ + int8_t __i; \ + for(__i=nb-1 ; (__i>=0) && (!__ret) ; __i--) { \ + __ret=LIST_PUSH_START(list, array[__i]); \ + } \ + if(LIST_DEBUG) \ + printf("LIST_ARRAY_PUSH_START(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \ + __ret; \ +}) + +#define LIST_ARRAY_PUSH_END(list, array, nb) ({\ + uint8_t __ret=0, __i; \ + for(__i=0 ; (__i<nb) && (!__ret) ; __i++) { \ + __ret=LIST_PUSH_END(list, array[__i]); \ + } \ + if(LIST_DEBUG) \ + printf("LIST_ARRAY_PUSH_END(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \ + __ret; \ +}) + +#define LIST_ARRAY_PULL_START(list, array, nb) ({\ + uint8_t __ret=0, __i; \ + for(__i=0 ; (__i<nb) && (!__ret) ; __i++) { \ + __ret=LIST_PULL_START(list, (array+__i)); \ + } \ + if(LIST_DEBUG) \ + printf("LIST_ARRAY_PULL_START(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \ + __ret; \ +}) + +#define LIST_ARRAY_PULL_END(list, array, nb) ({\ + uint8_t __ret=0; \ + int8_t __i; \ + for(__i=nb-1 ; (__i>=0) && (!__ret) ; __i--) { \ + __ret=LIST_PULL_END(list, (array+__i)); \ + } \ + if(LIST_DEBUG) \ + printf("LIST_ARRAY_PULL_END(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \ + __ret; \ +}) + + +/* convert a list to an array, copy nb elts or less + * if list is too small, return number of copied elts */ +#define LIST_TO_ARRAY(list, array, nb) ({\ + int8_t __i; \ + for(__i=0 ; __i<nb && __i<list.hdr.cur_size ; __i++) { \ + array[__i] = list.elt[(__i+list.hdr.beg_indice) % list.hdr.size]; \ + } \ + if(LIST_DEBUG) \ + printf("LIST_TO_ARRAY(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __i); \ + __i; \ +}) + + +#define LIST_ALIGN_LEFT(list) ({ \ +uint8_t __ret=0, __i; \ +if(list.hdr.beg_indice != 0) { \ + if(list.hdr.beg_indice+list.hdr.cur_size <= list.hdr.size) { \ + for(__i=0 ; __i<list.hdr.cur_size ; __i++) { \ + list.elt[__i] = list.elt[__i+list.hdr.beg_indice]; \ + } \ + } \ + else { \ + uint8_t buffer_size=(list.hdr.size - list.hdr.beg_indice < (list.hdr.cur_size + list.hdr.beg_indice)%list.hdr.size) ? \ + (list.hdr.size - list.hdr.beg_indice) * sizeof(list.elt[0]) : \ + ((list.hdr.cur_size + list.hdr.beg_indice)%list.hdr.size) * sizeof(list.elt[0]); \ + { \ + uint8_t buffer[buffer_size]; \ + memcpy(buffer, list.elt, buffer_size); \ + for(__i=0 ; __i<(list.hdr.cur_size - buffer_size/sizeof(list.elt[0])) ; __i++) { \ + list.elt[__i] = list.elt[__i+list.hdr.beg_indice]; \ + } \ + memcpy(&list.elt[list.hdr.cur_size - buffer_size/sizeof(list.elt[0])], buffer, buffer_size); \ + } \ + } \ + list.hdr.beg_indice=0; \ +} \ + if(LIST_DEBUG) \ + printf("LIST_ALIGN_LEFT()"CR); \ + __ret; \ +}) + +#endif /* _AVERSIVE_LIST_H_ */ diff --git a/include/aversive/parts.h b/include/aversive/parts.h new file mode 100644 index 0000000..329342f --- /dev/null +++ b/include/aversive/parts.h @@ -0,0 +1,275 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + +#ifndef _AVERSIVE_PARTS_H_ +#define _AVERSIVE_PARTS_H_ + +#if defined (__AVR_AT86RF401__) +#include <aversive/parts/AT86RF401.h> +#elif defined (__AVR_AT89S51__) +#include <aversive/parts/AT89S51.h> +#elif defined (__AVR_AT89S52__) +#include <aversive/parts/AT89S52.h> +#elif defined (__AVR_AT90CAN128__) +#include <aversive/parts/AT90CAN128.h> +#elif defined (__AVR_AT90CAN32__) +#include <aversive/parts/AT90CAN32.h> +#elif defined (__AVR_AT90CAN64__) +#include <aversive/parts/AT90CAN64.h> +#elif defined (__AVR_AT90PWM2__) +#include <aversive/parts/AT90PWM2.h> +#elif defined (__AVR_AT90PWM216__) +#include <aversive/parts/AT90PWM216.h> +#elif defined (__AVR_AT90PWM2B__) +#include <aversive/parts/AT90PWM2B.h> +#elif defined (__AVR_AT90PWM3__) +#include <aversive/parts/AT90PWM3.h> +#elif defined (__AVR_AT90PWM316__) +#include <aversive/parts/AT90PWM316.h> +#elif defined (__AVR_AT90PWM3B__) +#include <aversive/parts/AT90PWM3B.h> +#elif defined (__AVR_AT90S1200__) +#include <aversive/parts/AT90S1200.h> +#elif defined (__AVR_AT90S2313__) +#include <aversive/parts/AT90S2313.h> +#elif defined (__AVR_AT90S2323__) +#include <aversive/parts/AT90S2323.h> +#elif defined (__AVR_AT90S2343__) +#include <aversive/parts/AT90S2343.h> +#elif defined (__AVR_AT90S4414__) +#include <aversive/parts/AT90S4414.h> +#elif defined (__AVR_AT90S4433__) +#include <aversive/parts/AT90S4433.h> +#elif defined (__AVR_AT90S4434__) +#include <aversive/parts/AT90S4434.h> +#elif defined (__AVR_AT90S8515__) +#include <aversive/parts/AT90S8515.h> +#elif defined (__AVR_AT90S8515comp__) +#include <aversive/parts/AT90S8515comp.h> +#elif defined (__AVR_AT90S8535__) +#include <aversive/parts/AT90S8535.h> +#elif defined (__AVR_AT90S8535comp__) +#include <aversive/parts/AT90S8535comp.h> +#elif defined (__AVR_AT90USB1286__) +#include <aversive/parts/AT90USB1286.h> +#elif defined (__AVR_AT90USB1287__) +#include <aversive/parts/AT90USB1287.h> +#elif defined (__AVR_AT90USB162__) +#include <aversive/parts/AT90USB162.h> +#elif defined (__AVR_AT90USB646__) +#include <aversive/parts/AT90USB646.h> +#elif defined (__AVR_AT90USB647__) +#include <aversive/parts/AT90USB647.h> +#elif defined (__AVR_AT90USB82__) +#include <aversive/parts/AT90USB82.h> +#elif defined (__AVR_ATmega103__) +#include <aversive/parts/ATmega103.h> +#elif defined (__AVR_ATmega103comp__) +#include <aversive/parts/ATmega103comp.h> +#elif defined (__AVR_ATmega128__) +#include <aversive/parts/ATmega128.h> +#elif defined (__AVR_ATmega1280__) +#include <aversive/parts/ATmega1280.h> +#elif defined (__AVR_ATmega1281__) +#include <aversive/parts/ATmega1281.h> +#elif defined (__AVR_ATmega1284P__) +#include <aversive/parts/ATmega1284P.h> +#elif defined (__AVR_ATmega128A__) +#include <aversive/parts/ATmega128A.h> +#elif defined (__AVR_ATmega16__) +#include <aversive/parts/ATmega16.h> +#elif defined (__AVR_ATmega161__) +#include <aversive/parts/ATmega161.h> +#elif defined (__AVR_ATmega161comp__) +#include <aversive/parts/ATmega161comp.h> +#elif defined (__AVR_ATmega162__) +#include <aversive/parts/ATmega162.h> +#elif defined (__AVR_ATmega163__) +#include <aversive/parts/ATmega163.h> +#elif defined (__AVR_ATmega164P__) +#include <aversive/parts/ATmega164P.h> +#elif defined (__AVR_ATmega165__) +#include <aversive/parts/ATmega165.h> +#elif defined (__AVR_ATmega165P__) +#include <aversive/parts/ATmega165P.h> +#elif defined (__AVR_ATmega168__) +#include <aversive/parts/ATmega168.h> +#elif defined (__AVR_ATmega168P__) +#include <aversive/parts/ATmega168P.h> +#elif defined (__AVR_ATmega168PA__) +#include <aversive/parts/ATmega168PA.h> +#elif defined (__AVR_ATmega169__) +#include <aversive/parts/ATmega169.h> +#elif defined (__AVR_ATmega169P__) +#include <aversive/parts/ATmega169P.h> +#elif defined (__AVR_ATmega16A__) +#include <aversive/parts/ATmega16A.h> +#elif defined (__AVR_ATmega16HVA__) +#include <aversive/parts/ATmega16HVA.h> +#elif defined (__AVR_ATmega16U4__) +#include <aversive/parts/ATmega16U4.h> +#elif defined (__AVR_ATmega2560__) +#include <aversive/parts/ATmega2560.h> +#elif defined (__AVR_ATmega2561__) +#include <aversive/parts/ATmega2561.h> +#elif defined (__AVR_ATmega32__) +#include <aversive/parts/ATmega32.h> +#elif defined (__AVR_ATmega323__) +#include <aversive/parts/ATmega323.h> +#elif defined (__AVR_ATmega324P__) +#include <aversive/parts/ATmega324P.h> +#elif defined (__AVR_ATmega324PA__) +#include <aversive/parts/ATmega324PA.h> +#elif defined (__AVR_ATmega325__) +#include <aversive/parts/ATmega325.h> +#elif defined (__AVR_ATmega3250__) +#include <aversive/parts/ATmega3250.h> +#elif defined (__AVR_ATmega3250P__) +#include <aversive/parts/ATmega3250P.h> +#elif defined (__AVR_ATmega325P__) +#include <aversive/parts/ATmega325P.h> +#elif defined (__AVR_ATmega328P__) +#include <aversive/parts/ATmega328P.h> +#elif defined (__AVR_ATmega329__) +#include <aversive/parts/ATmega329.h> +#elif defined (__AVR_ATmega3290__) +#include <aversive/parts/ATmega3290.h> +#elif defined (__AVR_ATmega3290P__) +#include <aversive/parts/ATmega3290P.h> +#elif defined (__AVR_ATmega329P__) +#include <aversive/parts/ATmega329P.h> +#elif defined (__AVR_ATmega32A__) +#include <aversive/parts/ATmega32A.h> +#elif defined (__AVR_ATmega32C1__) +#include <aversive/parts/ATmega32C1.h> +#elif defined (__AVR_ATmega32HVB__) +#include <aversive/parts/ATmega32HVB.h> +#elif defined (__AVR_ATmega32M1__) +#include <aversive/parts/ATmega32M1.h> +#elif defined (__AVR_ATmega32U4__) +#include <aversive/parts/ATmega32U4.h> +#elif defined (__AVR_ATmega32U6__) +#include <aversive/parts/ATmega32U6.h> +#elif defined (__AVR_ATmega406__) +#include <aversive/parts/ATmega406.h> +#elif defined (__AVR_ATmega48__) +#include <aversive/parts/ATmega48.h> +#elif defined (__AVR_ATmega48P__) +#include <aversive/parts/ATmega48P.h> +#elif defined (__AVR_ATmega64__) +#include <aversive/parts/ATmega64.h> +#elif defined (__AVR_ATmega640__) +#include <aversive/parts/ATmega640.h> +#elif defined (__AVR_ATmega644__) +#include <aversive/parts/ATmega644.h> +#elif defined (__AVR_ATmega644P__) +#include <aversive/parts/ATmega644P.h> +#elif defined (__AVR_ATmega645__) +#include <aversive/parts/ATmega645.h> +#elif defined (__AVR_ATmega6450__) +#include <aversive/parts/ATmega6450.h> +#elif defined (__AVR_ATmega649__) +#include <aversive/parts/ATmega649.h> +#elif defined (__AVR_ATmega6490__) +#include <aversive/parts/ATmega6490.h> +#elif defined (__AVR_ATmega64A__) +#include <aversive/parts/ATmega64A.h> +#elif defined (__AVR_ATmega8__) +#include <aversive/parts/ATmega8.h> +#elif defined (__AVR_ATmega8515__) +#include <aversive/parts/ATmega8515.h> +#elif defined (__AVR_ATmega8535__) +#include <aversive/parts/ATmega8535.h> +#elif defined (__AVR_ATmega88__) +#include <aversive/parts/ATmega88.h> +#elif defined (__AVR_ATmega88P__) +#include <aversive/parts/ATmega88P.h> +#elif defined (__AVR_ATmega88PA__) +#include <aversive/parts/ATmega88PA.h> +#elif defined (__AVR_ATmega8A__) +#include <aversive/parts/ATmega8A.h> +#elif defined (__AVR_ATtiny10__) +#include <aversive/parts/ATtiny10.h> +#elif defined (__AVR_ATtiny11__) +#include <aversive/parts/ATtiny11.h> +#elif defined (__AVR_ATtiny12__) +#include <aversive/parts/ATtiny12.h> +#elif defined (__AVR_ATtiny13__) +#include <aversive/parts/ATtiny13.h> +#elif defined (__AVR_ATtiny13A__) +#include <aversive/parts/ATtiny13A.h> +#elif defined (__AVR_ATtiny15__) +#include <aversive/parts/ATtiny15.h> +#elif defined (__AVR_ATtiny167__) +#include <aversive/parts/ATtiny167.h> +#elif defined (__AVR_ATtiny22__) +#include <aversive/parts/ATtiny22.h> +#elif defined (__AVR_ATtiny2313__) +#include <aversive/parts/ATtiny2313.h> +#elif defined (__AVR_ATtiny24__) +#include <aversive/parts/ATtiny24.h> +#elif defined (__AVR_ATtiny25__) +#include <aversive/parts/ATtiny25.h> +#elif defined (__AVR_ATtiny26__) +#include <aversive/parts/ATtiny26.h> +#elif defined (__AVR_ATtiny261__) +#include <aversive/parts/ATtiny261.h> +#elif defined (__AVR_ATtiny28__) +#include <aversive/parts/ATtiny28.h> +#elif defined (__AVR_ATtiny43U__) +#include <aversive/parts/ATtiny43U.h> +#elif defined (__AVR_ATtiny44__) +#include <aversive/parts/ATtiny44.h> +#elif defined (__AVR_ATtiny45__) +#include <aversive/parts/ATtiny45.h> +#elif defined (__AVR_ATtiny461__) +#include <aversive/parts/ATtiny461.h> +#elif defined (__AVR_ATtiny48__) +#include <aversive/parts/ATtiny48.h> +#elif defined (__AVR_ATtiny84__) +#include <aversive/parts/ATtiny84.h> +#elif defined (__AVR_ATtiny85__) +#include <aversive/parts/ATtiny85.h> +#elif defined (__AVR_ATtiny861__) +#include <aversive/parts/ATtiny861.h> +#elif defined (__AVR_ATtiny88__) +#include <aversive/parts/ATtiny88.h> +#elif defined (__AVR_ATxmega128A1__) +#include <aversive/parts/ATxmega128A1.h> +#elif defined (__AVR_ATxmega128A3__) +#include <aversive/parts/ATxmega128A3.h> +#elif defined (__AVR_ATxmega256A3__) +#include <aversive/parts/ATxmega256A3.h> +#elif defined (__AVR_ATxmega256A3B__) +#include <aversive/parts/ATxmega256A3B.h> +#elif defined (__AVR_ATxmega64A1__) +#include <aversive/parts/ATxmega64A1.h> +#elif defined (__AVR_ATxmega64A3__) +#include <aversive/parts/ATxmega64A3.h> +#else +#error "This arch is not implemented yet" +#endif + +#endif /* _AVERSIVE_PARTS_H_ */ diff --git a/include/aversive/parts/AT86RF401.h b/include/aversive/parts/AT86RF401.h new file mode 100644 index 0000000..8aa9f86 --- /dev/null +++ b/include/aversive/parts/AT86RF401.h @@ -0,0 +1,215 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* VCOTUNE */ +#define VCOTUNE0_REG VCOTUNE +#define VCOTUNE1_REG VCOTUNE +#define VCOTUNE2_REG VCOTUNE +#define VCOTUNE3_REG VCOTUNE +#define VCOTUNE4_REG VCOTUNE +#define VCOVDET0_REG VCOTUNE +#define VCOVDET1_REG VCOTUNE + +/* BL_CONFIG */ +#define BL0_REG BL_CONFIG +#define BL1_REG BL_CONFIG +#define BL2_REG BL_CONFIG +#define BL3_REG BL_CONFIG +#define BL4_REG BL_CONFIG +#define BL5_REG BL_CONFIG +#define BLV_REG BL_CONFIG +#define BL_REG BL_CONFIG + +/* DEEDR */ +#define ED0_REG DEEDR +#define ED1_REG DEEDR +#define ED2_REG DEEDR +#define ED3_REG DEEDR +#define ED4_REG DEEDR +#define ED5_REG DEEDR +#define ED6_REG DEEDR +#define ED7_REG DEEDR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* DEEAR */ +#define BA0_REG DEEAR +#define BA1_REG DEEAR +#define BA2_REG DEEAR +#define PA3_REG DEEAR +#define PA4_REG DEEAR +#define PA5_REG DEEAR +#define PA6_REG DEEAR + +/* AVR_CONFIG */ +#define BBM_REG AVR_CONFIG +#define SLEEP_REG AVR_CONFIG +#define BLI_REG AVR_CONFIG +#define BD_REG AVR_CONFIG +#define TM_REG AVR_CONFIG +#define ACS0_REG AVR_CONFIG +#define ACS1_REG AVR_CONFIG + +/* B_DET */ +#define BD0_REG B_DET +#define BD1_REG B_DET +#define BD2_REG B_DET +#define BD3_REG B_DET +#define BD4_REG B_DET +#define BD5_REG B_DET + +/* LOCKDET2 */ +#define LC0_REG LOCKDET2 +#define LC1_REG LOCKDET2 +#define LC2_REG LOCKDET2 +#define ULC0_REG LOCKDET2 +#define ULC1_REG LOCKDET2 +#define ULC2_REG LOCKDET2 +#define LAT_REG LOCKDET2 +#define EUD_REG LOCKDET2 + +/* TX_CNTL */ +#define LOC_REG TX_CNTL +#define TXK_REG TX_CNTL +#define TXE_REG TX_CNTL +#define FSK_REG TX_CNTL + +/* BTCNT */ +#define C0_REG BTCNT +#define C1_REG BTCNT +#define C2_REG BTCNT +#define C3_REG BTCNT +#define C4_REG BTCNT +#define C5_REG BTCNT +#define C6_REG BTCNT +#define C7_REG BTCNT + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* BTCR */ +#define F0_REG BTCR +#define DATA_REG BTCR +#define F2_REG BTCR +#define IE_REG BTCR +#define M0_REG BTCR +#define M1_REG BTCR +#define C8_REG BTCR +#define C9_REG BTCR + +/* IO_DATIN */ +#define IOI0_REG IO_DATIN +#define IOI1_REG IO_DATIN +#define IOI2_REG IO_DATIN +#define IOI3_REG IO_DATIN +#define IOI4_REG IO_DATIN +#define IOI5_REG IO_DATIN + +/* IO_ENAB */ +#define IOE0_REG IO_ENAB +#define IOE1_REG IO_ENAB +#define IOE2_REG IO_ENAB +#define IOE3_REG IO_ENAB +#define IOE4_REG IO_ENAB +#define IOE5_REG IO_ENAB + +/* LOCKDET1 */ +#define CS0_REG LOCKDET1 +#define CS1_REG LOCKDET1 +#define BOD_REG LOCKDET1 +#define ENKO_REG LOCKDET1 +#define UPOK_REG LOCKDET1 + +/* IO_DATOUT */ +#define IOO0_REG IO_DATOUT +#define IOO1_REG IO_DATOUT +#define IOO2_REG IO_DATOUT +#define IOO3_REG IO_DATOUT +#define IOO4_REG IO_DATOUT +#define IOO5_REG IO_DATOUT + +/* DEECR */ +#define EER_REG DEECR +#define EEL_REG DEECR +#define EEU_REG DEECR +#define BSY_REG DEECR + +/* PWR_ATTEN */ +#define PCF0_REG PWR_ATTEN +#define PCF1_REG PWR_ATTEN +#define PCF2_REG PWR_ATTEN +#define PCC0_REG PWR_ATTEN +#define PCC1_REG PWR_ATTEN +#define PCC2_REG PWR_ATTEN + +/* pins mapping */ + diff --git a/include/aversive/parts/AT89S51.h b/include/aversive/parts/AT89S51.h new file mode 100644 index 0000000..f808b9c --- /dev/null +++ b/include/aversive/parts/AT89S51.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* pins mapping */ + diff --git a/include/aversive/parts/AT89S52.h b/include/aversive/parts/AT89S52.h new file mode 100644 index 0000000..f808b9c --- /dev/null +++ b/include/aversive/parts/AT89S52.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* pins mapping */ + diff --git a/include/aversive/parts/AT90CAN128.h b/include/aversive/parts/AT90CAN128.h new file mode 100644 index 0000000..84fee1a --- /dev/null +++ b/include/aversive/parts/AT90CAN128.h @@ -0,0 +1,1622 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* CANGSTA */ +#define ERRP_REG CANGSTA +#define BOFF_REG CANGSTA +#define ENFG_REG CANGSTA +#define RXBSY_REG CANGSTA +#define TXBSY_REG CANGSTA +#define OVRG_REG CANGSTA + +/* CANGCON */ +#define SWRES_REG CANGCON +#define ENASTB_REG CANGCON +#define TEST_REG CANGCON +#define LISTEN_REG CANGCON +#define SYNTTC_REG CANGCON +#define TTC_REG CANGCON +#define OVRQ_REG CANGCON +#define ABRQ_REG CANGCON + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* CANIDM1 */ +#define IDMSK21_REG CANIDM1 +#define IDMSK22_REG CANIDM1 +#define IDMSK23_REG CANIDM1 +#define IDMSK24_REG CANIDM1 +#define IDMSK25_REG CANIDM1 +#define IDMSK26_REG CANIDM1 +#define IDMSK27_REG CANIDM1 +#define IDMSK28_REG CANIDM1 + +/* CANIDM3 */ +#define IDMSK5_REG CANIDM3 +#define IDMSK6_REG CANIDM3 +#define IDMSK7_REG CANIDM3 +#define IDMSK8_REG CANIDM3 +#define IDMSK9_REG CANIDM3 +#define IDMSK10_REG CANIDM3 +#define IDMSK11_REG CANIDM3 +#define IDMSK12_REG CANIDM3 + +/* CANIDM2 */ +#define IDMSK13_REG CANIDM2 +#define IDMSK14_REG CANIDM2 +#define IDMSK15_REG CANIDM2 +#define IDMSK16_REG CANIDM2 +#define IDMSK17_REG CANIDM2 +#define IDMSK18_REG CANIDM2 +#define IDMSK19_REG CANIDM2 +#define IDMSK20_REG CANIDM2 + +/* CANIDM4 */ +#define IDEMSK_REG CANIDM4 +#define RTRMSK_REG CANIDM4 +#define IDMSK0_REG CANIDM4 +#define IDMSK1_REG CANIDM4 +#define IDMSK2_REG CANIDM4 +#define IDMSK3_REG CANIDM4 +#define IDMSK4_REG CANIDM4 + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* CANGIT */ +#define AERG_REG CANGIT +#define FERG_REG CANGIT +#define CERG_REG CANGIT +#define SERG_REG CANGIT +#define BXOK_REG CANGIT +#define OVRTIM_REG CANGIT +#define BOFFIT_REG CANGIT +#define CANIT_REG CANGIT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* CANGIE */ +#define ENOVRT_REG CANGIE +#define ENERG_REG CANGIE +#define ENBX_REG CANGIE +#define ENERR_REG CANGIE +#define ENTX_REG CANGIE +#define ENRX_REG CANGIE +#define ENBOFF_REG CANGIE +#define ENIT_REG CANGIE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* CANIE2 */ +#define IEMOB0_REG CANIE2 +#define IEMOB1_REG CANIE2 +#define IEMOB2_REG CANIE2 +#define IEMOB3_REG CANIE2 +#define IEMOB4_REG CANIE2 +#define IEMOB5_REG CANIE2 +#define IEMOB6_REG CANIE2 +#define IEMOB7_REG CANIE2 + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* CANIE1 */ +#define IEMOB8_REG CANIE1 +#define IEMOB9_REG CANIE1 +#define IEMOB10_REG CANIE1 +#define IEMOB11_REG CANIE1 +#define IEMOB12_REG CANIE1 +#define IEMOB13_REG CANIE1 +#define IEMOB14_REG CANIE1 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* CANIDT4 */ +#define RB0TAG_REG CANIDT4 +#define RB1TAG_REG CANIDT4 +#define RTRTAG_REG CANIDT4 +#define IDT0_REG CANIDT4 +#define IDT1_REG CANIDT4 +#define IDT2_REG CANIDT4 +#define IDT3_REG CANIDT4 +#define IDT4_REG CANIDT4 + +/* CANIDT2 */ +#define IDT13_REG CANIDT2 +#define IDT14_REG CANIDT2 +#define IDT15_REG CANIDT2 +#define IDT16_REG CANIDT2 +#define IDT17_REG CANIDT2 +#define IDT18_REG CANIDT2 +#define IDT19_REG CANIDT2 +#define IDT20_REG CANIDT2 + +/* CANIDT3 */ +#define IDT5_REG CANIDT3 +#define IDT6_REG CANIDT3 +#define IDT7_REG CANIDT3 +#define IDT8_REG CANIDT3 +#define IDT9_REG CANIDT3 +#define IDT10_REG CANIDT3 +#define IDT11_REG CANIDT3 +#define IDT12_REG CANIDT3 + +/* CANIDT1 */ +#define IDT21_REG CANIDT1 +#define IDT22_REG CANIDT1 +#define IDT23_REG CANIDT1 +#define IDT24_REG CANIDT1 +#define IDT25_REG CANIDT1 +#define IDT26_REG CANIDT1 +#define IDT27_REG CANIDT1 +#define IDT28_REG CANIDT1 + +/* CANSIT1 */ +#define SIT8_REG CANSIT1 +#define SIT9_REG CANSIT1 +#define SIT10_REG CANSIT1 +#define SIT11_REG CANSIT1 +#define SIT12_REG CANSIT1 +#define SIT13_REG CANSIT1 +#define SIT14_REG CANSIT1 + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* CANCDMOB */ +#define DLC0_REG CANCDMOB +#define DLC1_REG CANCDMOB +#define DLC2_REG CANCDMOB +#define DLC3_REG CANCDMOB +#define IDE_REG CANCDMOB +#define RPLV_REG CANCDMOB +#define CONMOB0_REG CANCDMOB +#define CONMOB1_REG CANCDMOB + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* CANSIT2 */ +#define SIT0_REG CANSIT2 +#define SIT1_REG CANSIT2 +#define SIT2_REG CANSIT2 +#define SIT3_REG CANSIT2 +#define SIT4_REG CANSIT2 +#define SIT5_REG CANSIT2 +#define SIT6_REG CANSIT2 +#define SIT7_REG CANSIT2 + +/* CANHPMOB */ +#define CGP0_REG CANHPMOB +#define CGP1_REG CANHPMOB +#define CGP2_REG CANHPMOB +#define CGP3_REG CANHPMOB +#define HPMOB0_REG CANHPMOB +#define HPMOB1_REG CANHPMOB +#define HPMOB2_REG CANHPMOB +#define HPMOB3_REG CANHPMOB + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* CANPAGE */ +#define INDX0_REG CANPAGE +#define INDX1_REG CANPAGE +#define INDX2_REG CANPAGE +#define AINC_REG CANPAGE +#define MOBNB0_REG CANPAGE +#define MOBNB1_REG CANPAGE +#define MOBNB2_REG CANPAGE +#define MOBNB3_REG CANPAGE + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* CANSTMOB */ +#define AERR_REG CANSTMOB +#define FERR_REG CANSTMOB +#define CERR_REG CANSTMOB +#define SERR_REG CANSTMOB +#define BERR_REG CANSTMOB +#define RXOK_REG CANSTMOB +#define TXOK_REG CANSTMOB +#define DLCW_REG CANSTMOB + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* CANEN2 */ +#define ENMOB0_REG CANEN2 +#define ENMOB1_REG CANEN2 +#define ENMOB2_REG CANEN2 +#define ENMOB3_REG CANEN2 +#define ENMOB4_REG CANEN2 +#define ENMOB5_REG CANEN2 +#define ENMOB6_REG CANEN2 +#define ENMOB7_REG CANEN2 + +/* CANEN1 */ +#define ENMOB8_REG CANEN1 +#define ENMOB9_REG CANEN1 +#define ENMOB10_REG CANEN1 +#define ENMOB11_REG CANEN1 +#define ENMOB12_REG CANEN1 +#define ENMOB13_REG CANEN1 +#define ENMOB14_REG CANEN1 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* CANBT2 */ +#define PRS0_REG CANBT2 +#define PRS1_REG CANBT2 +#define PRS2_REG CANBT2 +#define SJW0_REG CANBT2 +#define SJW1_REG CANBT2 + +/* CANBT3 */ +#define SMP_REG CANBT3 +#define PHS10_REG CANBT3 +#define PHS11_REG CANBT3 +#define PHS12_REG CANBT3 +#define PHS20_REG CANBT3 +#define PHS21_REG CANBT3 +#define PHS22_REG CANBT3 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* CANBT1 */ +#define BRP0_REG CANBT1 +#define BRP1_REG CANBT1 +#define BRP2_REG CANBT1 +#define BRP3_REG CANBT1 +#define BRP4_REG CANBT1 +#define BRP5_REG CANBT1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/AT90CAN32.h b/include/aversive/parts/AT90CAN32.h new file mode 100644 index 0000000..84fee1a --- /dev/null +++ b/include/aversive/parts/AT90CAN32.h @@ -0,0 +1,1622 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* CANGSTA */ +#define ERRP_REG CANGSTA +#define BOFF_REG CANGSTA +#define ENFG_REG CANGSTA +#define RXBSY_REG CANGSTA +#define TXBSY_REG CANGSTA +#define OVRG_REG CANGSTA + +/* CANGCON */ +#define SWRES_REG CANGCON +#define ENASTB_REG CANGCON +#define TEST_REG CANGCON +#define LISTEN_REG CANGCON +#define SYNTTC_REG CANGCON +#define TTC_REG CANGCON +#define OVRQ_REG CANGCON +#define ABRQ_REG CANGCON + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* CANIDM1 */ +#define IDMSK21_REG CANIDM1 +#define IDMSK22_REG CANIDM1 +#define IDMSK23_REG CANIDM1 +#define IDMSK24_REG CANIDM1 +#define IDMSK25_REG CANIDM1 +#define IDMSK26_REG CANIDM1 +#define IDMSK27_REG CANIDM1 +#define IDMSK28_REG CANIDM1 + +/* CANIDM3 */ +#define IDMSK5_REG CANIDM3 +#define IDMSK6_REG CANIDM3 +#define IDMSK7_REG CANIDM3 +#define IDMSK8_REG CANIDM3 +#define IDMSK9_REG CANIDM3 +#define IDMSK10_REG CANIDM3 +#define IDMSK11_REG CANIDM3 +#define IDMSK12_REG CANIDM3 + +/* CANIDM2 */ +#define IDMSK13_REG CANIDM2 +#define IDMSK14_REG CANIDM2 +#define IDMSK15_REG CANIDM2 +#define IDMSK16_REG CANIDM2 +#define IDMSK17_REG CANIDM2 +#define IDMSK18_REG CANIDM2 +#define IDMSK19_REG CANIDM2 +#define IDMSK20_REG CANIDM2 + +/* CANIDM4 */ +#define IDEMSK_REG CANIDM4 +#define RTRMSK_REG CANIDM4 +#define IDMSK0_REG CANIDM4 +#define IDMSK1_REG CANIDM4 +#define IDMSK2_REG CANIDM4 +#define IDMSK3_REG CANIDM4 +#define IDMSK4_REG CANIDM4 + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* CANGIT */ +#define AERG_REG CANGIT +#define FERG_REG CANGIT +#define CERG_REG CANGIT +#define SERG_REG CANGIT +#define BXOK_REG CANGIT +#define OVRTIM_REG CANGIT +#define BOFFIT_REG CANGIT +#define CANIT_REG CANGIT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* CANGIE */ +#define ENOVRT_REG CANGIE +#define ENERG_REG CANGIE +#define ENBX_REG CANGIE +#define ENERR_REG CANGIE +#define ENTX_REG CANGIE +#define ENRX_REG CANGIE +#define ENBOFF_REG CANGIE +#define ENIT_REG CANGIE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* CANIE2 */ +#define IEMOB0_REG CANIE2 +#define IEMOB1_REG CANIE2 +#define IEMOB2_REG CANIE2 +#define IEMOB3_REG CANIE2 +#define IEMOB4_REG CANIE2 +#define IEMOB5_REG CANIE2 +#define IEMOB6_REG CANIE2 +#define IEMOB7_REG CANIE2 + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* CANIE1 */ +#define IEMOB8_REG CANIE1 +#define IEMOB9_REG CANIE1 +#define IEMOB10_REG CANIE1 +#define IEMOB11_REG CANIE1 +#define IEMOB12_REG CANIE1 +#define IEMOB13_REG CANIE1 +#define IEMOB14_REG CANIE1 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* CANIDT4 */ +#define RB0TAG_REG CANIDT4 +#define RB1TAG_REG CANIDT4 +#define RTRTAG_REG CANIDT4 +#define IDT0_REG CANIDT4 +#define IDT1_REG CANIDT4 +#define IDT2_REG CANIDT4 +#define IDT3_REG CANIDT4 +#define IDT4_REG CANIDT4 + +/* CANIDT2 */ +#define IDT13_REG CANIDT2 +#define IDT14_REG CANIDT2 +#define IDT15_REG CANIDT2 +#define IDT16_REG CANIDT2 +#define IDT17_REG CANIDT2 +#define IDT18_REG CANIDT2 +#define IDT19_REG CANIDT2 +#define IDT20_REG CANIDT2 + +/* CANIDT3 */ +#define IDT5_REG CANIDT3 +#define IDT6_REG CANIDT3 +#define IDT7_REG CANIDT3 +#define IDT8_REG CANIDT3 +#define IDT9_REG CANIDT3 +#define IDT10_REG CANIDT3 +#define IDT11_REG CANIDT3 +#define IDT12_REG CANIDT3 + +/* CANIDT1 */ +#define IDT21_REG CANIDT1 +#define IDT22_REG CANIDT1 +#define IDT23_REG CANIDT1 +#define IDT24_REG CANIDT1 +#define IDT25_REG CANIDT1 +#define IDT26_REG CANIDT1 +#define IDT27_REG CANIDT1 +#define IDT28_REG CANIDT1 + +/* CANSIT1 */ +#define SIT8_REG CANSIT1 +#define SIT9_REG CANSIT1 +#define SIT10_REG CANSIT1 +#define SIT11_REG CANSIT1 +#define SIT12_REG CANSIT1 +#define SIT13_REG CANSIT1 +#define SIT14_REG CANSIT1 + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* CANCDMOB */ +#define DLC0_REG CANCDMOB +#define DLC1_REG CANCDMOB +#define DLC2_REG CANCDMOB +#define DLC3_REG CANCDMOB +#define IDE_REG CANCDMOB +#define RPLV_REG CANCDMOB +#define CONMOB0_REG CANCDMOB +#define CONMOB1_REG CANCDMOB + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* CANSIT2 */ +#define SIT0_REG CANSIT2 +#define SIT1_REG CANSIT2 +#define SIT2_REG CANSIT2 +#define SIT3_REG CANSIT2 +#define SIT4_REG CANSIT2 +#define SIT5_REG CANSIT2 +#define SIT6_REG CANSIT2 +#define SIT7_REG CANSIT2 + +/* CANHPMOB */ +#define CGP0_REG CANHPMOB +#define CGP1_REG CANHPMOB +#define CGP2_REG CANHPMOB +#define CGP3_REG CANHPMOB +#define HPMOB0_REG CANHPMOB +#define HPMOB1_REG CANHPMOB +#define HPMOB2_REG CANHPMOB +#define HPMOB3_REG CANHPMOB + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* CANPAGE */ +#define INDX0_REG CANPAGE +#define INDX1_REG CANPAGE +#define INDX2_REG CANPAGE +#define AINC_REG CANPAGE +#define MOBNB0_REG CANPAGE +#define MOBNB1_REG CANPAGE +#define MOBNB2_REG CANPAGE +#define MOBNB3_REG CANPAGE + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* CANSTMOB */ +#define AERR_REG CANSTMOB +#define FERR_REG CANSTMOB +#define CERR_REG CANSTMOB +#define SERR_REG CANSTMOB +#define BERR_REG CANSTMOB +#define RXOK_REG CANSTMOB +#define TXOK_REG CANSTMOB +#define DLCW_REG CANSTMOB + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* CANEN2 */ +#define ENMOB0_REG CANEN2 +#define ENMOB1_REG CANEN2 +#define ENMOB2_REG CANEN2 +#define ENMOB3_REG CANEN2 +#define ENMOB4_REG CANEN2 +#define ENMOB5_REG CANEN2 +#define ENMOB6_REG CANEN2 +#define ENMOB7_REG CANEN2 + +/* CANEN1 */ +#define ENMOB8_REG CANEN1 +#define ENMOB9_REG CANEN1 +#define ENMOB10_REG CANEN1 +#define ENMOB11_REG CANEN1 +#define ENMOB12_REG CANEN1 +#define ENMOB13_REG CANEN1 +#define ENMOB14_REG CANEN1 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* CANBT2 */ +#define PRS0_REG CANBT2 +#define PRS1_REG CANBT2 +#define PRS2_REG CANBT2 +#define SJW0_REG CANBT2 +#define SJW1_REG CANBT2 + +/* CANBT3 */ +#define SMP_REG CANBT3 +#define PHS10_REG CANBT3 +#define PHS11_REG CANBT3 +#define PHS12_REG CANBT3 +#define PHS20_REG CANBT3 +#define PHS21_REG CANBT3 +#define PHS22_REG CANBT3 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* CANBT1 */ +#define BRP0_REG CANBT1 +#define BRP1_REG CANBT1 +#define BRP2_REG CANBT1 +#define BRP3_REG CANBT1 +#define BRP4_REG CANBT1 +#define BRP5_REG CANBT1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/AT90CAN64.h b/include/aversive/parts/AT90CAN64.h new file mode 100644 index 0000000..84fee1a --- /dev/null +++ b/include/aversive/parts/AT90CAN64.h @@ -0,0 +1,1622 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* CANGSTA */ +#define ERRP_REG CANGSTA +#define BOFF_REG CANGSTA +#define ENFG_REG CANGSTA +#define RXBSY_REG CANGSTA +#define TXBSY_REG CANGSTA +#define OVRG_REG CANGSTA + +/* CANGCON */ +#define SWRES_REG CANGCON +#define ENASTB_REG CANGCON +#define TEST_REG CANGCON +#define LISTEN_REG CANGCON +#define SYNTTC_REG CANGCON +#define TTC_REG CANGCON +#define OVRQ_REG CANGCON +#define ABRQ_REG CANGCON + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* CANIDM1 */ +#define IDMSK21_REG CANIDM1 +#define IDMSK22_REG CANIDM1 +#define IDMSK23_REG CANIDM1 +#define IDMSK24_REG CANIDM1 +#define IDMSK25_REG CANIDM1 +#define IDMSK26_REG CANIDM1 +#define IDMSK27_REG CANIDM1 +#define IDMSK28_REG CANIDM1 + +/* CANIDM3 */ +#define IDMSK5_REG CANIDM3 +#define IDMSK6_REG CANIDM3 +#define IDMSK7_REG CANIDM3 +#define IDMSK8_REG CANIDM3 +#define IDMSK9_REG CANIDM3 +#define IDMSK10_REG CANIDM3 +#define IDMSK11_REG CANIDM3 +#define IDMSK12_REG CANIDM3 + +/* CANIDM2 */ +#define IDMSK13_REG CANIDM2 +#define IDMSK14_REG CANIDM2 +#define IDMSK15_REG CANIDM2 +#define IDMSK16_REG CANIDM2 +#define IDMSK17_REG CANIDM2 +#define IDMSK18_REG CANIDM2 +#define IDMSK19_REG CANIDM2 +#define IDMSK20_REG CANIDM2 + +/* CANIDM4 */ +#define IDEMSK_REG CANIDM4 +#define RTRMSK_REG CANIDM4 +#define IDMSK0_REG CANIDM4 +#define IDMSK1_REG CANIDM4 +#define IDMSK2_REG CANIDM4 +#define IDMSK3_REG CANIDM4 +#define IDMSK4_REG CANIDM4 + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* CANGIT */ +#define AERG_REG CANGIT +#define FERG_REG CANGIT +#define CERG_REG CANGIT +#define SERG_REG CANGIT +#define BXOK_REG CANGIT +#define OVRTIM_REG CANGIT +#define BOFFIT_REG CANGIT +#define CANIT_REG CANGIT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* CANGIE */ +#define ENOVRT_REG CANGIE +#define ENERG_REG CANGIE +#define ENBX_REG CANGIE +#define ENERR_REG CANGIE +#define ENTX_REG CANGIE +#define ENRX_REG CANGIE +#define ENBOFF_REG CANGIE +#define ENIT_REG CANGIE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* CANIE2 */ +#define IEMOB0_REG CANIE2 +#define IEMOB1_REG CANIE2 +#define IEMOB2_REG CANIE2 +#define IEMOB3_REG CANIE2 +#define IEMOB4_REG CANIE2 +#define IEMOB5_REG CANIE2 +#define IEMOB6_REG CANIE2 +#define IEMOB7_REG CANIE2 + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* CANIE1 */ +#define IEMOB8_REG CANIE1 +#define IEMOB9_REG CANIE1 +#define IEMOB10_REG CANIE1 +#define IEMOB11_REG CANIE1 +#define IEMOB12_REG CANIE1 +#define IEMOB13_REG CANIE1 +#define IEMOB14_REG CANIE1 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* CANIDT4 */ +#define RB0TAG_REG CANIDT4 +#define RB1TAG_REG CANIDT4 +#define RTRTAG_REG CANIDT4 +#define IDT0_REG CANIDT4 +#define IDT1_REG CANIDT4 +#define IDT2_REG CANIDT4 +#define IDT3_REG CANIDT4 +#define IDT4_REG CANIDT4 + +/* CANIDT2 */ +#define IDT13_REG CANIDT2 +#define IDT14_REG CANIDT2 +#define IDT15_REG CANIDT2 +#define IDT16_REG CANIDT2 +#define IDT17_REG CANIDT2 +#define IDT18_REG CANIDT2 +#define IDT19_REG CANIDT2 +#define IDT20_REG CANIDT2 + +/* CANIDT3 */ +#define IDT5_REG CANIDT3 +#define IDT6_REG CANIDT3 +#define IDT7_REG CANIDT3 +#define IDT8_REG CANIDT3 +#define IDT9_REG CANIDT3 +#define IDT10_REG CANIDT3 +#define IDT11_REG CANIDT3 +#define IDT12_REG CANIDT3 + +/* CANIDT1 */ +#define IDT21_REG CANIDT1 +#define IDT22_REG CANIDT1 +#define IDT23_REG CANIDT1 +#define IDT24_REG CANIDT1 +#define IDT25_REG CANIDT1 +#define IDT26_REG CANIDT1 +#define IDT27_REG CANIDT1 +#define IDT28_REG CANIDT1 + +/* CANSIT1 */ +#define SIT8_REG CANSIT1 +#define SIT9_REG CANSIT1 +#define SIT10_REG CANSIT1 +#define SIT11_REG CANSIT1 +#define SIT12_REG CANSIT1 +#define SIT13_REG CANSIT1 +#define SIT14_REG CANSIT1 + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* CANCDMOB */ +#define DLC0_REG CANCDMOB +#define DLC1_REG CANCDMOB +#define DLC2_REG CANCDMOB +#define DLC3_REG CANCDMOB +#define IDE_REG CANCDMOB +#define RPLV_REG CANCDMOB +#define CONMOB0_REG CANCDMOB +#define CONMOB1_REG CANCDMOB + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* CANSIT2 */ +#define SIT0_REG CANSIT2 +#define SIT1_REG CANSIT2 +#define SIT2_REG CANSIT2 +#define SIT3_REG CANSIT2 +#define SIT4_REG CANSIT2 +#define SIT5_REG CANSIT2 +#define SIT6_REG CANSIT2 +#define SIT7_REG CANSIT2 + +/* CANHPMOB */ +#define CGP0_REG CANHPMOB +#define CGP1_REG CANHPMOB +#define CGP2_REG CANHPMOB +#define CGP3_REG CANHPMOB +#define HPMOB0_REG CANHPMOB +#define HPMOB1_REG CANHPMOB +#define HPMOB2_REG CANHPMOB +#define HPMOB3_REG CANHPMOB + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* CANPAGE */ +#define INDX0_REG CANPAGE +#define INDX1_REG CANPAGE +#define INDX2_REG CANPAGE +#define AINC_REG CANPAGE +#define MOBNB0_REG CANPAGE +#define MOBNB1_REG CANPAGE +#define MOBNB2_REG CANPAGE +#define MOBNB3_REG CANPAGE + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* CANSTMOB */ +#define AERR_REG CANSTMOB +#define FERR_REG CANSTMOB +#define CERR_REG CANSTMOB +#define SERR_REG CANSTMOB +#define BERR_REG CANSTMOB +#define RXOK_REG CANSTMOB +#define TXOK_REG CANSTMOB +#define DLCW_REG CANSTMOB + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* CANEN2 */ +#define ENMOB0_REG CANEN2 +#define ENMOB1_REG CANEN2 +#define ENMOB2_REG CANEN2 +#define ENMOB3_REG CANEN2 +#define ENMOB4_REG CANEN2 +#define ENMOB5_REG CANEN2 +#define ENMOB6_REG CANEN2 +#define ENMOB7_REG CANEN2 + +/* CANEN1 */ +#define ENMOB8_REG CANEN1 +#define ENMOB9_REG CANEN1 +#define ENMOB10_REG CANEN1 +#define ENMOB11_REG CANEN1 +#define ENMOB12_REG CANEN1 +#define ENMOB13_REG CANEN1 +#define ENMOB14_REG CANEN1 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* CANBT2 */ +#define PRS0_REG CANBT2 +#define PRS1_REG CANBT2 +#define PRS2_REG CANBT2 +#define SJW0_REG CANBT2 +#define SJW1_REG CANBT2 + +/* CANBT3 */ +#define SMP_REG CANBT3 +#define PHS10_REG CANBT3 +#define PHS11_REG CANBT3 +#define PHS12_REG CANBT3 +#define PHS20_REG CANBT3 +#define PHS21_REG CANBT3 +#define PHS22_REG CANBT3 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* CANBT1 */ +#define BRP0_REG CANBT1 +#define BRP1_REG CANBT1 +#define BRP2_REG CANBT1 +#define BRP3_REG CANBT1 +#define BRP4_REG CANBT1 +#define BRP5_REG CANBT1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/AT90PWM2.h b/include/aversive/parts/AT90PWM2.h new file mode 100644 index 0000000..cc50cf2 --- /dev/null +++ b/include/aversive/parts/AT90PWM2.h @@ -0,0 +1,1226 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* EUDR */ +#define EUDR0_REG EUDR +#define EUDR1_REG EUDR +#define EUDR2_REG EUDR +#define EUDR3_REG EUDR +#define EUDR4_REG EUDR +#define EUDR5_REG EUDR +#define EUDR6_REG EUDR +#define EUDR7_REG EUDR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* OCR2SBH */ +#define OCR2SB_8_REG OCR2SBH +#define OCR2SB_9_REG OCR2SBH +#define OCR2SB_10_REG OCR2SBH +#define OCR2SB_11_REG OCR2SBH + +/* OCR2SBL */ +#define OCR2SB_0_REG OCR2SBL +#define OCR2SB_1_REG OCR2SBL +#define OCR2SB_2_REG OCR2SBL +#define OCR2SB_3_REG OCR2SBL +#define OCR2SB_4_REG OCR2SBL +#define OCR2SB_5_REG OCR2SBL +#define OCR2SB_6_REG OCR2SBL +#define OCR2SB_7_REG OCR2SBL + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* OCR0SAL */ +#define OCR0SA_0_REG OCR0SAL +#define OCR0SA_1_REG OCR0SAL +#define OCR0SA_2_REG OCR0SAL +#define OCR0SA_3_REG OCR0SAL +#define OCR0SA_4_REG OCR0SAL +#define OCR0SA_5_REG OCR0SAL +#define OCR0SA_6_REG OCR0SAL +#define OCR0SA_7_REG OCR0SAL + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL0_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC0_REG PRR +#define PRPSC1_REG PRR +#define PRPSC2_REG PRR + +/* PCNF0 */ +#define PCLKSEL0_REG PCNF0 +#define POP0_REG PCNF0 +#define PMODE00_REG PCNF0 +#define PMODE01_REG PCNF0 +#define PLOCK0_REG PCNF0 +#define PALOCK0_REG PCNF0 +#define PFIFTY0_REG PCNF0 + +/* PCNF2 */ +#define POME2_REG PCNF2 +#define PCLKSEL2_REG PCNF2 +#define POP2_REG PCNF2 +#define PMODE20_REG PCNF2 +#define PMODE21_REG PCNF2 +#define PLOCK2_REG PCNF2 +#define PALOCK2_REG PCNF2 +#define PFIFTY2_REG PCNF2 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* PFRC0A */ +#define PRFM0A0_REG PFRC0A +#define PRFM0A1_REG PFRC0A +#define PRFM0A2_REG PFRC0A +#define PRFM0A3_REG PFRC0A +#define PFLTE0A_REG PFRC0A +#define PELEV0A_REG PFRC0A +#define PISEL0A_REG PFRC0A +#define PCAE0A_REG PFRC0A + +/* PFRC0B */ +#define PRFM0B0_REG PFRC0B +#define PRFM0B1_REG PFRC0B +#define PRFM0B2_REG PFRC0B +#define PRFM0B3_REG PFRC0B +#define PFLTE0B_REG PFRC0B +#define PELEV0B_REG PFRC0B +#define PISEL0B_REG PFRC0B +#define PCAE0B_REG PFRC0B + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0RBH */ +#define OCR0RB_8_REG OCR0RBH +#define OCR0RB_9_REG OCR0RBH +#define OCR0RB_00_REG OCR0RBH +#define OCR0RB_01_REG OCR0RBH +#define OCR0RB_02_REG OCR0RBH +#define OCR0RB_03_REG OCR0RBH +#define OCR0RB_04_REG OCR0RBH +#define OCR0RB_05_REG OCR0RBH + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* PIM2 */ +#define PEOPE2_REG PIM2 +#define PEVE2A_REG PIM2 +#define PEVE2B_REG PIM2 +#define PSEIE2_REG PIM2 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* OCR0RAL */ +#define OCR0RA_0_REG OCR0RAL +#define OCR0RA_1_REG OCR0RAL +#define OCR0RA_2_REG OCR0RAL +#define OCR0RA_3_REG OCR0RAL +#define OCR0RA_4_REG OCR0RAL +#define OCR0RA_5_REG OCR0RAL +#define OCR0RA_6_REG OCR0RAL +#define OCR0RA_7_REG OCR0RAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR3 */ +#define GPIOR30_REG GPIOR3 +#define GPIOR31_REG GPIOR3 +#define GPIOR32_REG GPIOR3 +#define GPIOR33_REG GPIOR3 +#define GPIOR34_REG GPIOR3 +#define GPIOR35_REG GPIOR3 +#define GPIOR36_REG GPIOR3 +#define GPIOR37_REG GPIOR3 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PIFR0 */ +#define PEOP0_REG PIFR0 +#define PRN00_REG PIFR0 +#define PRN01_REG PIFR0 +#define PEV0A_REG PIFR0 +#define PEV0B_REG PIFR0 +#define PSEI0_REG PIFR0 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* PFRC2B */ +#define PRFM2B0_REG PFRC2B +#define PRFM2B1_REG PFRC2B +#define PRFM2B2_REG PFRC2B +#define PRFM2B3_REG PFRC2B +#define PFLTE2B_REG PFRC2B +#define PELEV2B_REG PFRC2B +#define PISEL2B_REG PFRC2B +#define PCAE2B_REG PFRC2B + +/* PFRC2A */ +#define PRFM2A0_REG PFRC2A +#define PRFM2A1_REG PFRC2A +#define PRFM2A2_REG PFRC2A +#define PRFM2A3_REG PFRC2A +#define PFLTE2A_REG PFRC2A +#define PELEV2A_REG PFRC2A +#define PISEL2A_REG PFRC2A +#define PCAE2A_REG PFRC2A + +/* OCR2SAL */ +#define OCR2SA_0_REG OCR2SAL +#define OCR2SA_1_REG OCR2SAL +#define OCR2SA_2_REG OCR2SAL +#define OCR2SA_3_REG OCR2SAL +#define OCR2SA_4_REG OCR2SAL +#define OCR2SA_5_REG OCR2SAL +#define OCR2SA_6_REG OCR2SAL +#define OCR2SA_7_REG OCR2SAL + +/* EUCSRA */ +#define URxS0_REG EUCSRA +#define URxS1_REG EUCSRA +#define URxS2_REG EUCSRA +#define URxS3_REG EUCSRA +#define UTxS0_REG EUCSRA +#define UTxS1_REG EUCSRA +#define UTxS2_REG EUCSRA +#define UTxS3_REG EUCSRA + +/* EUCSRB */ +#define BODR_REG EUCSRB +#define EMCH_REG EUCSRB +#define EUSBS_REG EUCSRB +#define EUSART_REG EUCSRB + +/* EUCSRC */ +#define STP0_REG EUCSRC +#define STP1_REG EUCSRC +#define F1617_REG EUCSRC +#define FEM_REG EUCSRC + +/* PCTL0 */ +#define PRUN0_REG PCTL0 +#define PCCYC0_REG PCTL0 +#define PARUN0_REG PCTL0 +#define PAOC0A_REG PCTL0 +#define PAOC0B_REG PCTL0 +#define PBFM0_REG PCTL0 +#define PPRE00_REG PCTL0 +#define PPRE01_REG PCTL0 + +/* PCTL2 */ +#define PRUN2_REG PCTL2 +#define PCCYC2_REG PCTL2 +#define PARUN2_REG PCTL2 +#define PAOC2A_REG PCTL2 +#define PAOC2B_REG PCTL2 +#define PBFM2_REG PCTL2 +#define PPRE20_REG PCTL2 +#define PPRE21_REG PCTL2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* POM2 */ +#define POMV2A0_REG POM2 +#define POMV2A1_REG POM2 +#define POMV2A2_REG POM2 +#define POMV2A3_REG POM2 +#define POMV2B0_REG POM2 +#define POMV2B1_REG POM2 +#define POMV2B2_REG POM2 +#define POMV2B3_REG POM2 + +/* OCR2RBL */ +#define OCR2RB_0_REG OCR2RBL +#define OCR2RB_1_REG OCR2RBL +#define OCR2RB_2_REG OCR2RBL +#define OCR2RB_3_REG OCR2RBL +#define OCR2RB_4_REG OCR2RBL +#define OCR2RB_5_REG OCR2RBL +#define OCR2RB_6_REG OCR2RBL +#define OCR2RB_7_REG OCR2RBL + +/* PICR2H */ +#define PICR2_8_REG PICR2H +#define PICR2_9_REG PICR2H +#define PICR2_10_REG PICR2H +#define PICR2_11_REG PICR2H + +/* OCR2RBH */ +#define OCR2RB_8_REG OCR2RBH +#define OCR2RB_9_REG OCR2RBH +#define OCR2RB_10_REG OCR2RBH +#define OCR2RB_11_REG OCR2RBH +#define OCR2RB_12_REG OCR2RBH +#define OCR2RB_13_REG OCR2RBH +#define OCR2RB_14_REG OCR2RBH +#define OCR2RB_15_REG OCR2RBH + +/* PICR2L */ +#define PICR2_0_REG PICR2L +#define PICR2_1_REG PICR2L +#define PICR2_2_REG PICR2L +#define PICR2_3_REG PICR2L +#define PICR2_4_REG PICR2L +#define PICR2_5_REG PICR2L +#define PICR2_6_REG PICR2L +#define PICR2_7_REG PICR2L + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* OCR2RAH */ +#define OCR2RA_8_REG OCR2RAH +#define OCR2RA_9_REG OCR2RAH +#define OCR2RA_10_REG OCR2RAH +#define OCR2RA_11_REG OCR2RAH + +/* OCR2RAL */ +#define OCR2RA_0_REG OCR2RAL +#define OCR2RA_1_REG OCR2RAL +#define OCR2RA_2_REG OCR2RAL +#define OCR2RA_3_REG OCR2RAL +#define OCR2RA_4_REG OCR2RAL +#define OCR2RA_5_REG OCR2RAL +#define OCR2RA_6_REG OCR2RAL +#define OCR2RA_7_REG OCR2RAL + +/* OCR0RBL */ +#define OCR0RB_0_REG OCR0RBL +#define OCR0RB_1_REG OCR0RBL +#define OCR0RB_2_REG OCR0RBL +#define OCR0RB_3_REG OCR0RBL +#define OCR0RB_4_REG OCR0RBL +#define OCR0RB_5_REG OCR0RBL +#define OCR0RB_6_REG OCR0RBL +#define OCR0RB_7_REG OCR0RBL + +/* OCR0SAH */ +#define OCR0SA_8_REG OCR0SAH +#define OCR0SA_9_REG OCR0SAH +#define OCR0SA_00_REG OCR0SAH +#define OCR0SA_01_REG OCR0SAH + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* PICR0H */ +#define PICR0_8_REG PICR0H +#define PICR0_9_REG PICR0H +#define PICR0_10_REG PICR0H +#define PICR0_11_REG PICR0H + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* MUBRRL */ +#define MUBRR0_REG MUBRRL +#define MUBRR1_REG MUBRRL +#define MUBRR2_REG MUBRRL +#define MUBRR3_REG MUBRRL +#define MUBRR4_REG MUBRRL +#define MUBRR5_REG MUBRRL +#define MUBRR6_REG MUBRRL +#define MUBRR7_REG MUBRRL + +/* MUBRRH */ +#define MUBRR8_REG MUBRRH +#define MUBRR9_REG MUBRRH +#define MUBRR10_REG MUBRRH +#define MUBRR11_REG MUBRRH +#define MUBRR12_REG MUBRRH +#define MUBRR13_REG MUBRRH +#define MUBRR14_REG MUBRRH +#define MUBRR15_REG MUBRRH + +/* OCR2SAH */ +#define OCR2SA_8_REG OCR2SAH +#define OCR2SA_9_REG OCR2SAH +#define OCR2SA_10_REG OCR2SAH +#define OCR2SA_11_REG OCR2SAH + +/* OCR0SBL */ +#define OCR0SB_0_REG OCR0SBL +#define OCR0SB_1_REG OCR0SBL +#define OCR0SB_2_REG OCR0SBL +#define OCR0SB_3_REG OCR0SBL +#define OCR0SB_4_REG OCR0SBL +#define OCR0SB_5_REG OCR0SBL +#define OCR0SB_6_REG OCR0SBL +#define OCR0SB_7_REG OCR0SBL + +/* OCR0SBH */ +#define OCR0SB_8_REG OCR0SBH +#define OCR0SB_9_REG OCR0SBH +#define OCR0SB_00_REG OCR0SBH +#define OCR0SB_01_REG OCR0SBH + +/* PICR0L */ +#define PICR0_0_REG PICR0L +#define PICR0_1_REG PICR0L +#define PICR0_2_REG PICR0L +#define PICR0_3_REG PICR0L +#define PICR0_4_REG PICR0L +#define PICR0_5_REG PICR0L +#define PICR0_6_REG PICR0L +#define PICR0_7_REG PICR0L + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* PSOC0 */ +#define POEN0A_REG PSOC0 +#define POEN0B_REG PSOC0 +#define PSYNC00_REG PSOC0 +#define PSYNC01_REG PSOC0 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define ADASCR_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define ACCKDIV_REG ACSR + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* OCR0RAH */ +#define OCR0RA_8_REG OCR0RAH +#define OCR0RA_9_REG OCR0RAH +#define OCR0RA_00_REG OCR0RAH +#define OCR0RA_01_REG OCR0RAH + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PIM0 */ +#define PEOPE0_REG PIM0 +#define PEVE0A_REG PIM0 +#define PEVE0B_REG PIM0 +#define PSEIE0_REG PIM0 + +/* PIFR2 */ +#define PEOP2_REG PIFR2 +#define PRN20_REG PIFR2 +#define PRN21_REG PIFR2 +#define PEV2A_REG PIFR2 +#define PEV2B_REG PIFR2 +#define PSEI2_REG PIFR2 + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PSOC2 */ +#define POEN2A_REG PSOC2 +#define POEN2C_REG PSOC2 +#define POEN2B_REG PSOC2 +#define POEN2D_REG PSOC2 +#define PSYNC2_0_REG PSOC2 +#define PSYNC2_1_REG PSOC2 +#define POS22_REG PSOC2 +#define POS23_REG PSOC2 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT20_PORT PORTB +#define PSCOUT20_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT21_PORT PORTB +#define PSCOUT21_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT11_PORT PORTB +#define PSCOUT11_BIT 6 +#define ICP1B_PORT PORTB +#define ICP1B_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT01_PORT PORTB +#define PSCOUT01_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define PSCOUT00_PORT PORTD +#define PSCOUT00_BIT 0 +#define XCK_PORT PORTD +#define XCK_BIT 0 +#define SSA_PORT PORTD +#define SSA_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define DALI_PORT PORTD +#define DALI_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define DALI_PORT PORTD +#define DALI_BIT 4 +#define ICP1_PORT PORTD +#define ICP1_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACMP2_PORT PORTD +#define ACMP2_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPM_PORT PORTD +#define ACMPM_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 + + diff --git a/include/aversive/parts/AT90PWM216.h b/include/aversive/parts/AT90PWM216.h new file mode 100644 index 0000000..05b892b --- /dev/null +++ b/include/aversive/parts/AT90PWM216.h @@ -0,0 +1,1232 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* EUDR */ +#define EUDR0_REG EUDR +#define EUDR1_REG EUDR +#define EUDR2_REG EUDR +#define EUDR3_REG EUDR +#define EUDR4_REG EUDR +#define EUDR5_REG EUDR +#define EUDR6_REG EUDR +#define EUDR7_REG EUDR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* OCR2SBH */ +#define OCR2SB_8_REG OCR2SBH +#define OCR2SB_9_REG OCR2SBH +#define OCR2SB_10_REG OCR2SBH +#define OCR2SB_11_REG OCR2SBH + +/* OCR2SBL */ +#define OCR2SB_0_REG OCR2SBL +#define OCR2SB_1_REG OCR2SBL +#define OCR2SB_2_REG OCR2SBL +#define OCR2SB_3_REG OCR2SBL +#define OCR2SB_4_REG OCR2SBL +#define OCR2SB_5_REG OCR2SBL +#define OCR2SB_6_REG OCR2SBL +#define OCR2SB_7_REG OCR2SBL + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* OCR0SAL */ +#define OCR0SA_0_REG OCR0SAL +#define OCR0SA_1_REG OCR0SAL +#define OCR0SA_2_REG OCR0SAL +#define OCR0SA_3_REG OCR0SAL +#define OCR0SA_4_REG OCR0SAL +#define OCR0SA_5_REG OCR0SAL +#define OCR0SA_6_REG OCR0SAL +#define OCR0SA_7_REG OCR0SAL + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL0_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC0_REG PRR +#define PRPSC1_REG PRR +#define PRPSC2_REG PRR + +/* PCNF0 */ +#define PCLKSEL0_REG PCNF0 +#define POP0_REG PCNF0 +#define PMODE00_REG PCNF0 +#define PMODE01_REG PCNF0 +#define PLOCK0_REG PCNF0 +#define PALOCK0_REG PCNF0 +#define PFIFTY0_REG PCNF0 + +/* PCNF2 */ +#define POME2_REG PCNF2 +#define PCLKSEL2_REG PCNF2 +#define POP2_REG PCNF2 +#define PMODE20_REG PCNF2 +#define PMODE21_REG PCNF2 +#define PLOCK2_REG PCNF2 +#define PALOCK2_REG PCNF2 +#define PFIFTY2_REG PCNF2 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* PFRC0A */ +#define PRFM0A0_REG PFRC0A +#define PRFM0A1_REG PFRC0A +#define PRFM0A2_REG PFRC0A +#define PRFM0A3_REG PFRC0A +#define PFLTE0A_REG PFRC0A +#define PELEV0A_REG PFRC0A +#define PISEL0A_REG PFRC0A +#define PCAE0A_REG PFRC0A + +/* PFRC0B */ +#define PRFM0B0_REG PFRC0B +#define PRFM0B1_REG PFRC0B +#define PRFM0B2_REG PFRC0B +#define PRFM0B3_REG PFRC0B +#define PFLTE0B_REG PFRC0B +#define PELEV0B_REG PFRC0B +#define PISEL0B_REG PFRC0B +#define PCAE0B_REG PFRC0B + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0RBH */ +#define OCR0RB_8_REG OCR0RBH +#define OCR0RB_9_REG OCR0RBH +#define OCR0RB_00_REG OCR0RBH +#define OCR0RB_01_REG OCR0RBH +#define OCR0RB_02_REG OCR0RBH +#define OCR0RB_03_REG OCR0RBH +#define OCR0RB_04_REG OCR0RBH +#define OCR0RB_05_REG OCR0RBH + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* PIM2 */ +#define PEOPE2_REG PIM2 +#define PEVE2A_REG PIM2 +#define PEVE2B_REG PIM2 +#define PSEIE2_REG PIM2 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* OCR0RAL */ +#define OCR0RA_0_REG OCR0RAL +#define OCR0RA_1_REG OCR0RAL +#define OCR0RA_2_REG OCR0RAL +#define OCR0RA_3_REG OCR0RAL +#define OCR0RA_4_REG OCR0RAL +#define OCR0RA_5_REG OCR0RAL +#define OCR0RA_6_REG OCR0RAL +#define OCR0RA_7_REG OCR0RAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR3 */ +#define GPIOR30_REG GPIOR3 +#define GPIOR31_REG GPIOR3 +#define GPIOR32_REG GPIOR3 +#define GPIOR33_REG GPIOR3 +#define GPIOR34_REG GPIOR3 +#define GPIOR35_REG GPIOR3 +#define GPIOR36_REG GPIOR3 +#define GPIOR37_REG GPIOR3 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PIFR0 */ +#define PEOP0_REG PIFR0 +#define PRN00_REG PIFR0 +#define PRN01_REG PIFR0 +#define PEV0A_REG PIFR0 +#define PEV0B_REG PIFR0 +#define PSEI0_REG PIFR0 +#define POAC0A_REG PIFR0 +#define POAC0B_REG PIFR0 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* PFRC2B */ +#define PRFM2B0_REG PFRC2B +#define PRFM2B1_REG PFRC2B +#define PRFM2B2_REG PFRC2B +#define PRFM2B3_REG PFRC2B +#define PFLTE2B_REG PFRC2B +#define PELEV2B_REG PFRC2B +#define PISEL2B_REG PFRC2B +#define PCAE2B_REG PFRC2B + +/* PFRC2A */ +#define PRFM2A0_REG PFRC2A +#define PRFM2A1_REG PFRC2A +#define PRFM2A2_REG PFRC2A +#define PRFM2A3_REG PFRC2A +#define PFLTE2A_REG PFRC2A +#define PELEV2A_REG PFRC2A +#define PISEL2A_REG PFRC2A +#define PCAE2A_REG PFRC2A + +/* OCR2SAL */ +#define OCR2SA_0_REG OCR2SAL +#define OCR2SA_1_REG OCR2SAL +#define OCR2SA_2_REG OCR2SAL +#define OCR2SA_3_REG OCR2SAL +#define OCR2SA_4_REG OCR2SAL +#define OCR2SA_5_REG OCR2SAL +#define OCR2SA_6_REG OCR2SAL +#define OCR2SA_7_REG OCR2SAL + +/* EUCSRA */ +#define URxS0_REG EUCSRA +#define URxS1_REG EUCSRA +#define URxS2_REG EUCSRA +#define URxS3_REG EUCSRA +#define UTxS0_REG EUCSRA +#define UTxS1_REG EUCSRA +#define UTxS2_REG EUCSRA +#define UTxS3_REG EUCSRA + +/* EUCSRB */ +#define BODR_REG EUCSRB +#define EMCH_REG EUCSRB +#define EUSBS_REG EUCSRB +#define EUSART_REG EUCSRB + +/* EUCSRC */ +#define STP0_REG EUCSRC +#define STP1_REG EUCSRC +#define F1617_REG EUCSRC +#define FEM_REG EUCSRC + +/* PCTL0 */ +#define PRUN0_REG PCTL0 +#define PCCYC0_REG PCTL0 +#define PARUN0_REG PCTL0 +#define PAOC0A_REG PCTL0 +#define PAOC0B_REG PCTL0 +#define PBFM0_REG PCTL0 +#define PPRE00_REG PCTL0 +#define PPRE01_REG PCTL0 + +/* PCTL2 */ +#define PRUN2_REG PCTL2 +#define PCCYC2_REG PCTL2 +#define PARUN2_REG PCTL2 +#define PAOC2A_REG PCTL2 +#define PAOC2B_REG PCTL2 +#define PBFM2_REG PCTL2 +#define PPRE20_REG PCTL2 +#define PPRE21_REG PCTL2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* POM2 */ +#define POMV2A0_REG POM2 +#define POMV2A1_REG POM2 +#define POMV2A2_REG POM2 +#define POMV2A3_REG POM2 +#define POMV2B0_REG POM2 +#define POMV2B1_REG POM2 +#define POMV2B2_REG POM2 +#define POMV2B3_REG POM2 + +/* OCR2RBL */ +#define OCR2RB_0_REG OCR2RBL +#define OCR2RB_1_REG OCR2RBL +#define OCR2RB_2_REG OCR2RBL +#define OCR2RB_3_REG OCR2RBL +#define OCR2RB_4_REG OCR2RBL +#define OCR2RB_5_REG OCR2RBL +#define OCR2RB_6_REG OCR2RBL +#define OCR2RB_7_REG OCR2RBL + +/* PICR2H */ +#define PICR2_8_REG PICR2H +#define PICR2_9_REG PICR2H +#define PICR2_10_REG PICR2H +#define PICR2_11_REG PICR2H +#define PCST2_REG PICR2H + +/* OCR2RBH */ +#define OCR2RB_8_REG OCR2RBH +#define OCR2RB_9_REG OCR2RBH +#define OCR2RB_10_REG OCR2RBH +#define OCR2RB_11_REG OCR2RBH +#define OCR2RB_12_REG OCR2RBH +#define OCR2RB_13_REG OCR2RBH +#define OCR2RB_14_REG OCR2RBH +#define OCR2RB_15_REG OCR2RBH + +/* PICR2L */ +#define PICR2_0_REG PICR2L +#define PICR2_1_REG PICR2L +#define PICR2_2_REG PICR2L +#define PICR2_3_REG PICR2L +#define PICR2_4_REG PICR2L +#define PICR2_5_REG PICR2L +#define PICR2_6_REG PICR2L +#define PICR2_7_REG PICR2L + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* OCR2RAH */ +#define OCR2RA_8_REG OCR2RAH +#define OCR2RA_9_REG OCR2RAH +#define OCR2RA_10_REG OCR2RAH +#define OCR2RA_11_REG OCR2RAH + +/* OCR2RAL */ +#define OCR2RA_0_REG OCR2RAL +#define OCR2RA_1_REG OCR2RAL +#define OCR2RA_2_REG OCR2RAL +#define OCR2RA_3_REG OCR2RAL +#define OCR2RA_4_REG OCR2RAL +#define OCR2RA_5_REG OCR2RAL +#define OCR2RA_6_REG OCR2RAL +#define OCR2RA_7_REG OCR2RAL + +/* OCR0RBL */ +#define OCR0RB_0_REG OCR0RBL +#define OCR0RB_1_REG OCR0RBL +#define OCR0RB_2_REG OCR0RBL +#define OCR0RB_3_REG OCR0RBL +#define OCR0RB_4_REG OCR0RBL +#define OCR0RB_5_REG OCR0RBL +#define OCR0RB_6_REG OCR0RBL +#define OCR0RB_7_REG OCR0RBL + +/* OCR0SAH */ +#define OCR0SA_8_REG OCR0SAH +#define OCR0SA_9_REG OCR0SAH +#define OCR0SA_00_REG OCR0SAH +#define OCR0SA_01_REG OCR0SAH + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* PICR0H */ +#define PICR0_8_REG PICR0H +#define PICR0_9_REG PICR0H +#define PICR0_10_REG PICR0H +#define PICR0_11_REG PICR0H +#define PCST0_REG PICR0H + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* MUBRRL */ +#define MUBRR0_REG MUBRRL +#define MUBRR1_REG MUBRRL +#define MUBRR2_REG MUBRRL +#define MUBRR3_REG MUBRRL +#define MUBRR4_REG MUBRRL +#define MUBRR5_REG MUBRRL +#define MUBRR6_REG MUBRRL +#define MUBRR7_REG MUBRRL + +/* MUBRRH */ +#define MUBRR8_REG MUBRRH +#define MUBRR9_REG MUBRRH +#define MUBRR10_REG MUBRRH +#define MUBRR11_REG MUBRRH +#define MUBRR12_REG MUBRRH +#define MUBRR13_REG MUBRRH +#define MUBRR14_REG MUBRRH +#define MUBRR15_REG MUBRRH + +/* OCR2SAH */ +#define OCR2SA_8_REG OCR2SAH +#define OCR2SA_9_REG OCR2SAH +#define OCR2SA_10_REG OCR2SAH +#define OCR2SA_11_REG OCR2SAH + +/* OCR0SBL */ +#define OCR0SB_0_REG OCR0SBL +#define OCR0SB_1_REG OCR0SBL +#define OCR0SB_2_REG OCR0SBL +#define OCR0SB_3_REG OCR0SBL +#define OCR0SB_4_REG OCR0SBL +#define OCR0SB_5_REG OCR0SBL +#define OCR0SB_6_REG OCR0SBL +#define OCR0SB_7_REG OCR0SBL + +/* OCR0SBH */ +#define OCR0SB_8_REG OCR0SBH +#define OCR0SB_9_REG OCR0SBH +#define OCR0SB_00_REG OCR0SBH +#define OCR0SB_01_REG OCR0SBH + +/* PICR0L */ +#define PICR0_0_REG PICR0L +#define PICR0_1_REG PICR0L +#define PICR0_2_REG PICR0L +#define PICR0_3_REG PICR0L +#define PICR0_4_REG PICR0L +#define PICR0_5_REG PICR0L +#define PICR0_6_REG PICR0L +#define PICR0_7_REG PICR0L + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* PSOC0 */ +#define POEN0A_REG PSOC0 +#define POEN0B_REG PSOC0 +#define PSYNC00_REG PSOC0 +#define PSYNC01_REG PSOC0 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define ADASCR_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define ACCKDIV_REG ACSR + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* OCR0RAH */ +#define OCR0RA_8_REG OCR0RAH +#define OCR0RA_9_REG OCR0RAH +#define OCR0RA_00_REG OCR0RAH +#define OCR0RA_01_REG OCR0RAH + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PIM0 */ +#define PEOPE0_REG PIM0 +#define PEVE0A_REG PIM0 +#define PEVE0B_REG PIM0 +#define PSEIE0_REG PIM0 + +/* PIFR2 */ +#define PEOP2_REG PIFR2 +#define PRN20_REG PIFR2 +#define PRN21_REG PIFR2 +#define PEV2A_REG PIFR2 +#define PEV2B_REG PIFR2 +#define PSEI2_REG PIFR2 +#define POAC2A_REG PIFR2 +#define POAC2B_REG PIFR2 + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PSOC2 */ +#define POEN2A_REG PSOC2 +#define POEN2C_REG PSOC2 +#define POEN2B_REG PSOC2 +#define POEN2D_REG PSOC2 +#define PSYNC2_0_REG PSOC2 +#define PSYNC2_1_REG PSOC2 +#define POS22_REG PSOC2 +#define POS23_REG PSOC2 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT20_PORT PORTB +#define PSCOUT20_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT21_PORT PORTB +#define PSCOUT21_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT11_PORT PORTB +#define PSCOUT11_BIT 6 +#define ICP1B_PORT PORTB +#define ICP1B_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT01_PORT PORTB +#define PSCOUT01_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define PSCOUT00_PORT PORTD +#define PSCOUT00_BIT 0 +#define XCK_PORT PORTD +#define XCK_BIT 0 +#define SSA_PORT PORTD +#define SSA_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define DALI_PORT PORTD +#define DALI_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define DALI_PORT PORTD +#define DALI_BIT 4 +#define ICP1_PORT PORTD +#define ICP1_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACMP2_PORT PORTD +#define ACMP2_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPM_PORT PORTD +#define ACMPM_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 + + diff --git a/include/aversive/parts/AT90PWM2B.h b/include/aversive/parts/AT90PWM2B.h new file mode 100644 index 0000000..05b892b --- /dev/null +++ b/include/aversive/parts/AT90PWM2B.h @@ -0,0 +1,1232 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* EUDR */ +#define EUDR0_REG EUDR +#define EUDR1_REG EUDR +#define EUDR2_REG EUDR +#define EUDR3_REG EUDR +#define EUDR4_REG EUDR +#define EUDR5_REG EUDR +#define EUDR6_REG EUDR +#define EUDR7_REG EUDR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* OCR2SBH */ +#define OCR2SB_8_REG OCR2SBH +#define OCR2SB_9_REG OCR2SBH +#define OCR2SB_10_REG OCR2SBH +#define OCR2SB_11_REG OCR2SBH + +/* OCR2SBL */ +#define OCR2SB_0_REG OCR2SBL +#define OCR2SB_1_REG OCR2SBL +#define OCR2SB_2_REG OCR2SBL +#define OCR2SB_3_REG OCR2SBL +#define OCR2SB_4_REG OCR2SBL +#define OCR2SB_5_REG OCR2SBL +#define OCR2SB_6_REG OCR2SBL +#define OCR2SB_7_REG OCR2SBL + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* OCR0SAL */ +#define OCR0SA_0_REG OCR0SAL +#define OCR0SA_1_REG OCR0SAL +#define OCR0SA_2_REG OCR0SAL +#define OCR0SA_3_REG OCR0SAL +#define OCR0SA_4_REG OCR0SAL +#define OCR0SA_5_REG OCR0SAL +#define OCR0SA_6_REG OCR0SAL +#define OCR0SA_7_REG OCR0SAL + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL0_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC0_REG PRR +#define PRPSC1_REG PRR +#define PRPSC2_REG PRR + +/* PCNF0 */ +#define PCLKSEL0_REG PCNF0 +#define POP0_REG PCNF0 +#define PMODE00_REG PCNF0 +#define PMODE01_REG PCNF0 +#define PLOCK0_REG PCNF0 +#define PALOCK0_REG PCNF0 +#define PFIFTY0_REG PCNF0 + +/* PCNF2 */ +#define POME2_REG PCNF2 +#define PCLKSEL2_REG PCNF2 +#define POP2_REG PCNF2 +#define PMODE20_REG PCNF2 +#define PMODE21_REG PCNF2 +#define PLOCK2_REG PCNF2 +#define PALOCK2_REG PCNF2 +#define PFIFTY2_REG PCNF2 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* PFRC0A */ +#define PRFM0A0_REG PFRC0A +#define PRFM0A1_REG PFRC0A +#define PRFM0A2_REG PFRC0A +#define PRFM0A3_REG PFRC0A +#define PFLTE0A_REG PFRC0A +#define PELEV0A_REG PFRC0A +#define PISEL0A_REG PFRC0A +#define PCAE0A_REG PFRC0A + +/* PFRC0B */ +#define PRFM0B0_REG PFRC0B +#define PRFM0B1_REG PFRC0B +#define PRFM0B2_REG PFRC0B +#define PRFM0B3_REG PFRC0B +#define PFLTE0B_REG PFRC0B +#define PELEV0B_REG PFRC0B +#define PISEL0B_REG PFRC0B +#define PCAE0B_REG PFRC0B + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0RBH */ +#define OCR0RB_8_REG OCR0RBH +#define OCR0RB_9_REG OCR0RBH +#define OCR0RB_00_REG OCR0RBH +#define OCR0RB_01_REG OCR0RBH +#define OCR0RB_02_REG OCR0RBH +#define OCR0RB_03_REG OCR0RBH +#define OCR0RB_04_REG OCR0RBH +#define OCR0RB_05_REG OCR0RBH + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* PIM2 */ +#define PEOPE2_REG PIM2 +#define PEVE2A_REG PIM2 +#define PEVE2B_REG PIM2 +#define PSEIE2_REG PIM2 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* OCR0RAL */ +#define OCR0RA_0_REG OCR0RAL +#define OCR0RA_1_REG OCR0RAL +#define OCR0RA_2_REG OCR0RAL +#define OCR0RA_3_REG OCR0RAL +#define OCR0RA_4_REG OCR0RAL +#define OCR0RA_5_REG OCR0RAL +#define OCR0RA_6_REG OCR0RAL +#define OCR0RA_7_REG OCR0RAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR3 */ +#define GPIOR30_REG GPIOR3 +#define GPIOR31_REG GPIOR3 +#define GPIOR32_REG GPIOR3 +#define GPIOR33_REG GPIOR3 +#define GPIOR34_REG GPIOR3 +#define GPIOR35_REG GPIOR3 +#define GPIOR36_REG GPIOR3 +#define GPIOR37_REG GPIOR3 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PIFR0 */ +#define PEOP0_REG PIFR0 +#define PRN00_REG PIFR0 +#define PRN01_REG PIFR0 +#define PEV0A_REG PIFR0 +#define PEV0B_REG PIFR0 +#define PSEI0_REG PIFR0 +#define POAC0A_REG PIFR0 +#define POAC0B_REG PIFR0 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* PFRC2B */ +#define PRFM2B0_REG PFRC2B +#define PRFM2B1_REG PFRC2B +#define PRFM2B2_REG PFRC2B +#define PRFM2B3_REG PFRC2B +#define PFLTE2B_REG PFRC2B +#define PELEV2B_REG PFRC2B +#define PISEL2B_REG PFRC2B +#define PCAE2B_REG PFRC2B + +/* PFRC2A */ +#define PRFM2A0_REG PFRC2A +#define PRFM2A1_REG PFRC2A +#define PRFM2A2_REG PFRC2A +#define PRFM2A3_REG PFRC2A +#define PFLTE2A_REG PFRC2A +#define PELEV2A_REG PFRC2A +#define PISEL2A_REG PFRC2A +#define PCAE2A_REG PFRC2A + +/* OCR2SAL */ +#define OCR2SA_0_REG OCR2SAL +#define OCR2SA_1_REG OCR2SAL +#define OCR2SA_2_REG OCR2SAL +#define OCR2SA_3_REG OCR2SAL +#define OCR2SA_4_REG OCR2SAL +#define OCR2SA_5_REG OCR2SAL +#define OCR2SA_6_REG OCR2SAL +#define OCR2SA_7_REG OCR2SAL + +/* EUCSRA */ +#define URxS0_REG EUCSRA +#define URxS1_REG EUCSRA +#define URxS2_REG EUCSRA +#define URxS3_REG EUCSRA +#define UTxS0_REG EUCSRA +#define UTxS1_REG EUCSRA +#define UTxS2_REG EUCSRA +#define UTxS3_REG EUCSRA + +/* EUCSRB */ +#define BODR_REG EUCSRB +#define EMCH_REG EUCSRB +#define EUSBS_REG EUCSRB +#define EUSART_REG EUCSRB + +/* EUCSRC */ +#define STP0_REG EUCSRC +#define STP1_REG EUCSRC +#define F1617_REG EUCSRC +#define FEM_REG EUCSRC + +/* PCTL0 */ +#define PRUN0_REG PCTL0 +#define PCCYC0_REG PCTL0 +#define PARUN0_REG PCTL0 +#define PAOC0A_REG PCTL0 +#define PAOC0B_REG PCTL0 +#define PBFM0_REG PCTL0 +#define PPRE00_REG PCTL0 +#define PPRE01_REG PCTL0 + +/* PCTL2 */ +#define PRUN2_REG PCTL2 +#define PCCYC2_REG PCTL2 +#define PARUN2_REG PCTL2 +#define PAOC2A_REG PCTL2 +#define PAOC2B_REG PCTL2 +#define PBFM2_REG PCTL2 +#define PPRE20_REG PCTL2 +#define PPRE21_REG PCTL2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* POM2 */ +#define POMV2A0_REG POM2 +#define POMV2A1_REG POM2 +#define POMV2A2_REG POM2 +#define POMV2A3_REG POM2 +#define POMV2B0_REG POM2 +#define POMV2B1_REG POM2 +#define POMV2B2_REG POM2 +#define POMV2B3_REG POM2 + +/* OCR2RBL */ +#define OCR2RB_0_REG OCR2RBL +#define OCR2RB_1_REG OCR2RBL +#define OCR2RB_2_REG OCR2RBL +#define OCR2RB_3_REG OCR2RBL +#define OCR2RB_4_REG OCR2RBL +#define OCR2RB_5_REG OCR2RBL +#define OCR2RB_6_REG OCR2RBL +#define OCR2RB_7_REG OCR2RBL + +/* PICR2H */ +#define PICR2_8_REG PICR2H +#define PICR2_9_REG PICR2H +#define PICR2_10_REG PICR2H +#define PICR2_11_REG PICR2H +#define PCST2_REG PICR2H + +/* OCR2RBH */ +#define OCR2RB_8_REG OCR2RBH +#define OCR2RB_9_REG OCR2RBH +#define OCR2RB_10_REG OCR2RBH +#define OCR2RB_11_REG OCR2RBH +#define OCR2RB_12_REG OCR2RBH +#define OCR2RB_13_REG OCR2RBH +#define OCR2RB_14_REG OCR2RBH +#define OCR2RB_15_REG OCR2RBH + +/* PICR2L */ +#define PICR2_0_REG PICR2L +#define PICR2_1_REG PICR2L +#define PICR2_2_REG PICR2L +#define PICR2_3_REG PICR2L +#define PICR2_4_REG PICR2L +#define PICR2_5_REG PICR2L +#define PICR2_6_REG PICR2L +#define PICR2_7_REG PICR2L + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* OCR2RAH */ +#define OCR2RA_8_REG OCR2RAH +#define OCR2RA_9_REG OCR2RAH +#define OCR2RA_10_REG OCR2RAH +#define OCR2RA_11_REG OCR2RAH + +/* OCR2RAL */ +#define OCR2RA_0_REG OCR2RAL +#define OCR2RA_1_REG OCR2RAL +#define OCR2RA_2_REG OCR2RAL +#define OCR2RA_3_REG OCR2RAL +#define OCR2RA_4_REG OCR2RAL +#define OCR2RA_5_REG OCR2RAL +#define OCR2RA_6_REG OCR2RAL +#define OCR2RA_7_REG OCR2RAL + +/* OCR0RBL */ +#define OCR0RB_0_REG OCR0RBL +#define OCR0RB_1_REG OCR0RBL +#define OCR0RB_2_REG OCR0RBL +#define OCR0RB_3_REG OCR0RBL +#define OCR0RB_4_REG OCR0RBL +#define OCR0RB_5_REG OCR0RBL +#define OCR0RB_6_REG OCR0RBL +#define OCR0RB_7_REG OCR0RBL + +/* OCR0SAH */ +#define OCR0SA_8_REG OCR0SAH +#define OCR0SA_9_REG OCR0SAH +#define OCR0SA_00_REG OCR0SAH +#define OCR0SA_01_REG OCR0SAH + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* PICR0H */ +#define PICR0_8_REG PICR0H +#define PICR0_9_REG PICR0H +#define PICR0_10_REG PICR0H +#define PICR0_11_REG PICR0H +#define PCST0_REG PICR0H + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* MUBRRL */ +#define MUBRR0_REG MUBRRL +#define MUBRR1_REG MUBRRL +#define MUBRR2_REG MUBRRL +#define MUBRR3_REG MUBRRL +#define MUBRR4_REG MUBRRL +#define MUBRR5_REG MUBRRL +#define MUBRR6_REG MUBRRL +#define MUBRR7_REG MUBRRL + +/* MUBRRH */ +#define MUBRR8_REG MUBRRH +#define MUBRR9_REG MUBRRH +#define MUBRR10_REG MUBRRH +#define MUBRR11_REG MUBRRH +#define MUBRR12_REG MUBRRH +#define MUBRR13_REG MUBRRH +#define MUBRR14_REG MUBRRH +#define MUBRR15_REG MUBRRH + +/* OCR2SAH */ +#define OCR2SA_8_REG OCR2SAH +#define OCR2SA_9_REG OCR2SAH +#define OCR2SA_10_REG OCR2SAH +#define OCR2SA_11_REG OCR2SAH + +/* OCR0SBL */ +#define OCR0SB_0_REG OCR0SBL +#define OCR0SB_1_REG OCR0SBL +#define OCR0SB_2_REG OCR0SBL +#define OCR0SB_3_REG OCR0SBL +#define OCR0SB_4_REG OCR0SBL +#define OCR0SB_5_REG OCR0SBL +#define OCR0SB_6_REG OCR0SBL +#define OCR0SB_7_REG OCR0SBL + +/* OCR0SBH */ +#define OCR0SB_8_REG OCR0SBH +#define OCR0SB_9_REG OCR0SBH +#define OCR0SB_00_REG OCR0SBH +#define OCR0SB_01_REG OCR0SBH + +/* PICR0L */ +#define PICR0_0_REG PICR0L +#define PICR0_1_REG PICR0L +#define PICR0_2_REG PICR0L +#define PICR0_3_REG PICR0L +#define PICR0_4_REG PICR0L +#define PICR0_5_REG PICR0L +#define PICR0_6_REG PICR0L +#define PICR0_7_REG PICR0L + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* PSOC0 */ +#define POEN0A_REG PSOC0 +#define POEN0B_REG PSOC0 +#define PSYNC00_REG PSOC0 +#define PSYNC01_REG PSOC0 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define ADASCR_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define ACCKDIV_REG ACSR + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* OCR0RAH */ +#define OCR0RA_8_REG OCR0RAH +#define OCR0RA_9_REG OCR0RAH +#define OCR0RA_00_REG OCR0RAH +#define OCR0RA_01_REG OCR0RAH + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PIM0 */ +#define PEOPE0_REG PIM0 +#define PEVE0A_REG PIM0 +#define PEVE0B_REG PIM0 +#define PSEIE0_REG PIM0 + +/* PIFR2 */ +#define PEOP2_REG PIFR2 +#define PRN20_REG PIFR2 +#define PRN21_REG PIFR2 +#define PEV2A_REG PIFR2 +#define PEV2B_REG PIFR2 +#define PSEI2_REG PIFR2 +#define POAC2A_REG PIFR2 +#define POAC2B_REG PIFR2 + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PSOC2 */ +#define POEN2A_REG PSOC2 +#define POEN2C_REG PSOC2 +#define POEN2B_REG PSOC2 +#define POEN2D_REG PSOC2 +#define PSYNC2_0_REG PSOC2 +#define PSYNC2_1_REG PSOC2 +#define POS22_REG PSOC2 +#define POS23_REG PSOC2 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT20_PORT PORTB +#define PSCOUT20_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT21_PORT PORTB +#define PSCOUT21_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT11_PORT PORTB +#define PSCOUT11_BIT 6 +#define ICP1B_PORT PORTB +#define ICP1B_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT01_PORT PORTB +#define PSCOUT01_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define PSCOUT00_PORT PORTD +#define PSCOUT00_BIT 0 +#define XCK_PORT PORTD +#define XCK_BIT 0 +#define SSA_PORT PORTD +#define SSA_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define DALI_PORT PORTD +#define DALI_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define DALI_PORT PORTD +#define DALI_BIT 4 +#define ICP1_PORT PORTD +#define ICP1_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACMP2_PORT PORTD +#define ACMP2_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPM_PORT PORTD +#define ACMPM_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 + + diff --git a/include/aversive/parts/AT90PWM3.h b/include/aversive/parts/AT90PWM3.h new file mode 100644 index 0000000..3d1452f --- /dev/null +++ b/include/aversive/parts/AT90PWM3.h @@ -0,0 +1,1441 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* EUDR */ +#define EUDR0_REG EUDR +#define EUDR1_REG EUDR +#define EUDR2_REG EUDR +#define EUDR3_REG EUDR +#define EUDR4_REG EUDR +#define EUDR5_REG EUDR +#define EUDR6_REG EUDR +#define EUDR7_REG EUDR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* OCR2SBH */ +#define OCR2SB_8_REG OCR2SBH +#define OCR2SB_9_REG OCR2SBH +#define OCR2SB_10_REG OCR2SBH +#define OCR2SB_11_REG OCR2SBH + +/* OCR2SBL */ +#define OCR2SB_0_REG OCR2SBL +#define OCR2SB_1_REG OCR2SBL +#define OCR2SB_2_REG OCR2SBL +#define OCR2SB_3_REG OCR2SBL +#define OCR2SB_4_REG OCR2SBL +#define OCR2SB_5_REG OCR2SBL +#define OCR2SB_6_REG OCR2SBL +#define OCR2SB_7_REG OCR2SBL + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL0_REG UCSRC + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC0_REG PRR +#define PRPSC1_REG PRR +#define PRPSC2_REG PRR + +/* PCNF0 */ +#define PCLKSEL0_REG PCNF0 +#define POP0_REG PCNF0 +#define PMODE00_REG PCNF0 +#define PMODE01_REG PCNF0 +#define PLOCK0_REG PCNF0 +#define PALOCK0_REG PCNF0 +#define PFIFTY0_REG PCNF0 + +/* PCNF1 */ +#define PCLKSEL1_REG PCNF1 +#define POP1_REG PCNF1 +#define PMODE10_REG PCNF1 +#define PMODE11_REG PCNF1 +#define PLOCK1_REG PCNF1 +#define PALOCK1_REG PCNF1 +#define PFIFTY1_REG PCNF1 + +/* PCNF2 */ +#define POME2_REG PCNF2 +#define PCLKSEL2_REG PCNF2 +#define POP2_REG PCNF2 +#define PMODE20_REG PCNF2 +#define PMODE21_REG PCNF2 +#define PLOCK2_REG PCNF2 +#define PALOCK2_REG PCNF2 +#define PFIFTY2_REG PCNF2 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* PFRC0A */ +#define PRFM0A0_REG PFRC0A +#define PRFM0A1_REG PFRC0A +#define PRFM0A2_REG PFRC0A +#define PRFM0A3_REG PFRC0A +#define PFLTE0A_REG PFRC0A +#define PELEV0A_REG PFRC0A +#define PISEL0A_REG PFRC0A +#define PCAE0A_REG PFRC0A + +/* PFRC0B */ +#define PRFM0B0_REG PFRC0B +#define PRFM0B1_REG PFRC0B +#define PRFM0B2_REG PFRC0B +#define PRFM0B3_REG PFRC0B +#define PFLTE0B_REG PFRC0B +#define PELEV0B_REG PFRC0B +#define PISEL0B_REG PFRC0B +#define PCAE0B_REG PFRC0B + +/* PICR1H */ +#define PICR1_8_REG PICR1H +#define PICR1_9_REG PICR1H +#define PICR1_10_REG PICR1H +#define PICR1_11_REG PICR1H + +/* PICR1L */ +#define PICR1_0_REG PICR1L +#define PICR1_1_REG PICR1L +#define PICR1_2_REG PICR1L +#define PICR1_3_REG PICR1L +#define PICR1_4_REG PICR1L +#define PICR1_5_REG PICR1L +#define PICR1_6_REG PICR1L +#define PICR1_7_REG PICR1L + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 + +/* OCR1RAH */ +#define OCR1RA_8_REG OCR1RAH +#define OCR1RA_9_REG OCR1RAH +#define OCR1RA_10_REG OCR1RAH +#define OCR1RA_11_REG OCR1RAH + +/* OCR1RAL */ +#define OCR1RA_0_REG OCR1RAL +#define OCR1RA_1_REG OCR1RAL +#define OCR1RA_2_REG OCR1RAL +#define OCR1RA_3_REG OCR1RAL +#define OCR1RA_4_REG OCR1RAL +#define OCR1RA_5_REG OCR1RAL +#define OCR1RA_6_REG OCR1RAL +#define OCR1RA_7_REG OCR1RAL + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0RBH */ +#define OCR0RB_8_REG OCR0RBH +#define OCR0RB_9_REG OCR0RBH +#define OCR0RB_00_REG OCR0RBH +#define OCR0RB_01_REG OCR0RBH +#define OCR0RB_02_REG OCR0RBH +#define OCR0RB_03_REG OCR0RBH +#define OCR0RB_04_REG OCR0RBH +#define OCR0RB_05_REG OCR0RBH + +/* OCR0RBL */ +#define OCR0RB_0_REG OCR0RBL +#define OCR0RB_1_REG OCR0RBL +#define OCR0RB_2_REG OCR0RBL +#define OCR0RB_3_REG OCR0RBL +#define OCR0RB_4_REG OCR0RBL +#define OCR0RB_5_REG OCR0RBL +#define OCR0RB_6_REG OCR0RBL +#define OCR0RB_7_REG OCR0RBL + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* OCR0RAL */ +#define OCR0RA_0_REG OCR0RAL +#define OCR0RA_1_REG OCR0RAL +#define OCR0RA_2_REG OCR0RAL +#define OCR0RA_3_REG OCR0RAL +#define OCR0RA_4_REG OCR0RAL +#define OCR0RA_5_REG OCR0RAL +#define OCR0RA_6_REG OCR0RAL +#define OCR0RA_7_REG OCR0RAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR3 */ +#define GPIOR30_REG GPIOR3 +#define GPIOR31_REG GPIOR3 +#define GPIOR32_REG GPIOR3 +#define GPIOR33_REG GPIOR3 +#define GPIOR34_REG GPIOR3 +#define GPIOR35_REG GPIOR3 +#define GPIOR36_REG GPIOR3 +#define GPIOR37_REG GPIOR3 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* PFRC2B */ +#define PRFM2B0_REG PFRC2B +#define PRFM2B1_REG PFRC2B +#define PRFM2B2_REG PFRC2B +#define PRFM2B3_REG PFRC2B +#define PFLTE2B_REG PFRC2B +#define PELEV2B_REG PFRC2B +#define PISEL2B_REG PFRC2B +#define PCAE2B_REG PFRC2B + +/* PFRC2A */ +#define PRFM2A0_REG PFRC2A +#define PRFM2A1_REG PFRC2A +#define PRFM2A2_REG PFRC2A +#define PRFM2A3_REG PFRC2A +#define PFLTE2A_REG PFRC2A +#define PELEV2A_REG PFRC2A +#define PISEL2A_REG PFRC2A +#define PCAE2A_REG PFRC2A + +/* OCR2SAL */ +#define OCR2SA_0_REG OCR2SAL +#define OCR2SA_1_REG OCR2SAL +#define OCR2SA_2_REG OCR2SAL +#define OCR2SA_3_REG OCR2SAL +#define OCR2SA_4_REG OCR2SAL +#define OCR2SA_5_REG OCR2SAL +#define OCR2SA_6_REG OCR2SAL +#define OCR2SA_7_REG OCR2SAL + +/* EUCSRA */ +#define URxS0_REG EUCSRA +#define URxS1_REG EUCSRA +#define URxS2_REG EUCSRA +#define URxS3_REG EUCSRA +#define UTxS0_REG EUCSRA +#define UTxS1_REG EUCSRA +#define UTxS2_REG EUCSRA +#define UTxS3_REG EUCSRA + +/* EUCSRB */ +#define BODR_REG EUCSRB +#define EMCH_REG EUCSRB +#define EUSBS_REG EUCSRB +#define EUSART_REG EUCSRB + +/* EUCSRC */ +#define STP0_REG EUCSRC +#define STP1_REG EUCSRC +#define F1617_REG EUCSRC +#define FEM_REG EUCSRC + +/* PCTL0 */ +#define PRUN0_REG PCTL0 +#define PCCYC0_REG PCTL0 +#define PARUN0_REG PCTL0 +#define PAOC0A_REG PCTL0 +#define PAOC0B_REG PCTL0 +#define PBFM0_REG PCTL0 +#define PPRE00_REG PCTL0 +#define PPRE01_REG PCTL0 + +/* PCTL1 */ +#define PRUN1_REG PCTL1 +#define PCCYC1_REG PCTL1 +#define PARUN1_REG PCTL1 +#define PAOC1A_REG PCTL1 +#define PAOC1B_REG PCTL1 +#define PBFM1_REG PCTL1 +#define PPRE10_REG PCTL1 +#define PPRE11_REG PCTL1 + +/* PCTL2 */ +#define PRUN2_REG PCTL2 +#define PCCYC2_REG PCTL2 +#define PARUN2_REG PCTL2 +#define PAOC2A_REG PCTL2 +#define PAOC2B_REG PCTL2 +#define PBFM2_REG PCTL2 +#define PPRE20_REG PCTL2 +#define PPRE21_REG PCTL2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* POM2 */ +#define POMV2A0_REG POM2 +#define POMV2A1_REG POM2 +#define POMV2A2_REG POM2 +#define POMV2A3_REG POM2 +#define POMV2B0_REG POM2 +#define POMV2B1_REG POM2 +#define POMV2B2_REG POM2 +#define POMV2B3_REG POM2 + +/* OCR2RBL */ +#define OCR2RB_0_REG OCR2RBL +#define OCR2RB_1_REG OCR2RBL +#define OCR2RB_2_REG OCR2RBL +#define OCR2RB_3_REG OCR2RBL +#define OCR2RB_4_REG OCR2RBL +#define OCR2RB_5_REG OCR2RBL +#define OCR2RB_6_REG OCR2RBL +#define OCR2RB_7_REG OCR2RBL + +/* PICR2H */ +#define PICR2_8_REG PICR2H +#define PICR2_9_REG PICR2H +#define PICR2_10_REG PICR2H +#define PICR2_11_REG PICR2H + +/* OCR2RBH */ +#define OCR2RB_8_REG OCR2RBH +#define OCR2RB_9_REG OCR2RBH +#define OCR2RB_10_REG OCR2RBH +#define OCR2RB_11_REG OCR2RBH +#define OCR2RB_12_REG OCR2RBH +#define OCR2RB_13_REG OCR2RBH +#define OCR2RB_14_REG OCR2RBH +#define OCR2RB_15_REG OCR2RBH + +/* PICR2L */ +#define PICR2_0_REG PICR2L +#define PICR2_1_REG PICR2L +#define PICR2_2_REG PICR2L +#define PICR2_3_REG PICR2L +#define PICR2_4_REG PICR2L +#define PICR2_5_REG PICR2L +#define PICR2_6_REG PICR2L +#define PICR2_7_REG PICR2L + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* OCR2RAH */ +#define OCR2RA_8_REG OCR2RAH +#define OCR2RA_9_REG OCR2RAH +#define OCR2RA_10_REG OCR2RAH +#define OCR2RA_11_REG OCR2RAH + +/* OCR2RAL */ +#define OCR2RA_0_REG OCR2RAL +#define OCR2RA_1_REG OCR2RAL +#define OCR2RA_2_REG OCR2RAL +#define OCR2RA_3_REG OCR2RAL +#define OCR2RA_4_REG OCR2RAL +#define OCR2RA_5_REG OCR2RAL +#define OCR2RA_6_REG OCR2RAL +#define OCR2RA_7_REG OCR2RAL + +/* OCR0SAL */ +#define OCR0SA_0_REG OCR0SAL +#define OCR0SA_1_REG OCR0SAL +#define OCR0SA_2_REG OCR0SAL +#define OCR0SA_3_REG OCR0SAL +#define OCR0SA_4_REG OCR0SAL +#define OCR0SA_5_REG OCR0SAL +#define OCR0SA_6_REG OCR0SAL +#define OCR0SA_7_REG OCR0SAL + +/* OCR0SAH */ +#define OCR0SA_8_REG OCR0SAH +#define OCR0SA_9_REG OCR0SAH +#define OCR0SA_00_REG OCR0SAH +#define OCR0SA_01_REG OCR0SAH + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* PICR0H */ +#define PICR0_8_REG PICR0H +#define PICR0_9_REG PICR0H +#define PICR0_10_REG PICR0H +#define PICR0_11_REG PICR0H + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* MUBRRL */ +#define MUBRR0_REG MUBRRL +#define MUBRR1_REG MUBRRL +#define MUBRR2_REG MUBRRL +#define MUBRR3_REG MUBRRL +#define MUBRR4_REG MUBRRL +#define MUBRR5_REG MUBRRL +#define MUBRR6_REG MUBRRL +#define MUBRR7_REG MUBRRL + +/* MUBRRH */ +#define MUBRR8_REG MUBRRH +#define MUBRR9_REG MUBRRH +#define MUBRR10_REG MUBRRH +#define MUBRR11_REG MUBRRH +#define MUBRR12_REG MUBRRH +#define MUBRR13_REG MUBRRH +#define MUBRR14_REG MUBRRH +#define MUBRR15_REG MUBRRH + +/* OCR2SAH */ +#define OCR2SA_8_REG OCR2SAH +#define OCR2SA_9_REG OCR2SAH +#define OCR2SA_10_REG OCR2SAH +#define OCR2SA_11_REG OCR2SAH + +/* OCR0SBL */ +#define OCR0SB_0_REG OCR0SBL +#define OCR0SB_1_REG OCR0SBL +#define OCR0SB_2_REG OCR0SBL +#define OCR0SB_3_REG OCR0SBL +#define OCR0SB_4_REG OCR0SBL +#define OCR0SB_5_REG OCR0SBL +#define OCR0SB_6_REG OCR0SBL +#define OCR0SB_7_REG OCR0SBL + +/* OCR0SBH */ +#define OCR0SB_8_REG OCR0SBH +#define OCR0SB_9_REG OCR0SBH +#define OCR0SB_00_REG OCR0SBH +#define OCR0SB_01_REG OCR0SBH + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* PFRC1B */ +#define PRFM1B0_REG PFRC1B +#define PRFM1B1_REG PFRC1B +#define PRFM1B2_REG PFRC1B +#define PRFM1B3_REG PFRC1B +#define PFLTE1B_REG PFRC1B +#define PELEV1B_REG PFRC1B +#define PISEL1B_REG PFRC1B +#define PCAE1B_REG PFRC1B + +/* PFRC1A */ +#define PRFM1A0_REG PFRC1A +#define PRFM1A1_REG PFRC1A +#define PRFM1A2_REG PFRC1A +#define PRFM1A3_REG PFRC1A +#define PFLTE1A_REG PFRC1A +#define PELEV1A_REG PFRC1A +#define PISEL1A_REG PFRC1A +#define PCAE1A_REG PFRC1A + +/* PICR0L */ +#define PICR0_0_REG PICR0L +#define PICR0_1_REG PICR0L +#define PICR0_2_REG PICR0L +#define PICR0_3_REG PICR0L +#define PICR0_4_REG PICR0L +#define PICR0_5_REG PICR0L +#define PICR0_6_REG PICR0L +#define PICR0_7_REG PICR0L + +/* OCR1SAL */ +#define OCR1SA_0_REG OCR1SAL +#define OCR1SA_1_REG OCR1SAL +#define OCR1SA_2_REG OCR1SAL +#define OCR1SA_3_REG OCR1SAL +#define OCR1SA_4_REG OCR1SAL +#define OCR1SA_5_REG OCR1SAL +#define OCR1SA_6_REG OCR1SAL +#define OCR1SA_7_REG OCR1SAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* PSOC0 */ +#define POEN0A_REG PSOC0 +#define POEN0B_REG PSOC0 +#define PSYNC00_REG PSOC0 +#define PSYNC01_REG PSOC0 + +/* PSOC1 */ +#define POEN1A_REG PSOC1 +#define POEN1B_REG PSOC1 +#define PSYNC1_0_REG PSOC1 +#define PSYNC1_1_REG PSOC1 + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define ACCKDIV_REG ACSR + +/* OCR1RBL */ +#define OCR1RB_0_REG OCR1RBL +#define OCR1RB_1_REG OCR1RBL +#define OCR1RB_2_REG OCR1RBL +#define OCR1RB_3_REG OCR1RBL +#define OCR1RB_4_REG OCR1RBL +#define OCR1RB_5_REG OCR1RBL +#define OCR1RB_6_REG OCR1RBL +#define OCR1RB_7_REG OCR1RBL + +/* OCR1SBH */ +#define OCR1SB_8_REG OCR1SBH +#define OCR1SB_9_REG OCR1SBH +#define OCR1SB_10_REG OCR1SBH +#define OCR1SB_11_REG OCR1SBH + +/* OCR1RBH */ +#define OCR1RB_8_REG OCR1RBH +#define OCR1RB_9_REG OCR1RBH +#define OCR1RB_10_REG OCR1RBH +#define OCR1RB_11_REG OCR1RBH +#define OCR1RB_12_REG OCR1RBH +#define OCR1RB_13_REG OCR1RBH +#define OCR1RB_14_REG OCR1RBH +#define OCR1RB_15_REG OCR1RBH + +/* OCR1SBL */ +#define OCR1SB_0_REG OCR1SBL +#define OCR1SB_1_REG OCR1SBL +#define OCR1SB_2_REG OCR1SBL +#define OCR1SB_3_REG OCR1SBL +#define OCR1SB_4_REG OCR1SBL +#define OCR1SB_5_REG OCR1SBL +#define OCR1SB_6_REG OCR1SBL +#define OCR1SB_7_REG OCR1SBL + +/* OCR1SAH */ +#define OCR1SA_8_REG OCR1SAH +#define OCR1SA_9_REG OCR1SAH +#define OCR1SA_10_REG OCR1SAH +#define OCR1SA_11_REG OCR1SAH + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* OCR0RAH */ +#define OCR0RA_8_REG OCR0RAH +#define OCR0RA_9_REG OCR0RAH +#define OCR0RA_00_REG OCR0RAH +#define OCR0RA_01_REG OCR0RAH + +/* PIM2 */ +#define PEOPE2_REG PIM2 +#define PEVE2A_REG PIM2 +#define PEVE2B_REG PIM2 +#define PSEIE2_REG PIM2 + +/* PIM0 */ +#define PEOPE0_REG PIM0 +#define PEVE0A_REG PIM0 +#define PEVE0B_REG PIM0 +#define PSEIE0_REG PIM0 + +/* PIM1 */ +#define PEOPE1_REG PIM1 +#define PEVE1A_REG PIM1 +#define PEVE1B_REG PIM1 +#define PSEIE1_REG PIM1 + +/* PIFR2 */ +#define PEOP2_REG PIFR2 +#define PRN20_REG PIFR2 +#define PRN21_REG PIFR2 +#define PEV2A_REG PIFR2 +#define PEV2B_REG PIFR2 +#define PSEI2_REG PIFR2 + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PIFR0 */ +#define PEOP0_REG PIFR0 +#define PRN00_REG PIFR0 +#define PRN01_REG PIFR0 +#define PEV0A_REG PIFR0 +#define PEV0B_REG PIFR0 +#define PSEI0_REG PIFR0 + +/* PIFR1 */ +#define PEOP1_REG PIFR1 +#define PRN10_REG PIFR1 +#define PRN11_REG PIFR1 +#define PEV1A_REG PIFR1 +#define PEV1B_REG PIFR1 +#define PSEI1_REG PIFR1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PSOC2 */ +#define POEN2A_REG PSOC2 +#define POEN2C_REG PSOC2 +#define POEN2B_REG PSOC2 +#define POEN2D_REG PSOC2 +#define PSYNC2_0_REG PSOC2 +#define PSYNC2_1_REG PSOC2 +#define POS22_REG PSOC2 +#define POS23_REG PSOC2 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define ADASCR_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT20_PORT PORTB +#define PSCOUT20_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT21_PORT PORTB +#define PSCOUT21_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT11_PORT PORTB +#define PSCOUT11_BIT 6 +#define ICP1B_PORT PORTB +#define ICP1B_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT01_PORT PORTB +#define PSCOUT01_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define INT3_PORT PORTC +#define INT3_BIT 0 +#define PSCOUT10_PORT PORTC +#define PSCOUT10_BIT 0 + +#define PSCIN1_PORT PORTC +#define PSCIN1_BIT 1 +#define OC1B_PORT PORTC +#define OC1B_BIT 1 + +#define T0_PORT PORTC +#define T0_BIT 2 +#define PSCOUT22_PORT PORTC +#define PSCOUT22_BIT 2 + +#define T1_PORT PORTC +#define T1_BIT 3 +#define PSCOUT23_PORT PORTC +#define PSCOUT23_BIT 3 + +#define ADC8_PORT PORTC +#define ADC8_BIT 4 +#define AMP1-_PORT PORTC +#define AMP1-_BIT 4 + +#define ADC9_PORT PORTC +#define ADC9_BIT 5 +#define AMP1+_PORT PORTC +#define AMP1+_BIT 5 + +#define ADC10_PORT PORTC +#define ADC10_BIT 6 +#define ACMP1_PORT PORTC +#define ACMP1_BIT 6 + +#define D2A_PORT PORTC +#define D2A_BIT 7 + +#define PSCOUT00_PORT PORTD +#define PSCOUT00_BIT 0 +#define XCK_PORT PORTD +#define XCK_BIT 0 +#define SSA_PORT PORTD +#define SSA_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define DALI_PORT PORTD +#define DALI_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define DALI_PORT PORTD +#define DALI_BIT 4 +#define ICP1_PORT PORTD +#define ICP1_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACOMP2_PORT PORTD +#define ACOMP2_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPM_PORT PORTD +#define ACMPM_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 + + diff --git a/include/aversive/parts/AT90PWM316.h b/include/aversive/parts/AT90PWM316.h new file mode 100644 index 0000000..4ed1173 --- /dev/null +++ b/include/aversive/parts/AT90PWM316.h @@ -0,0 +1,1450 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* EUDR */ +#define EUDR0_REG EUDR +#define EUDR1_REG EUDR +#define EUDR2_REG EUDR +#define EUDR3_REG EUDR +#define EUDR4_REG EUDR +#define EUDR5_REG EUDR +#define EUDR6_REG EUDR +#define EUDR7_REG EUDR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* OCR2SBH */ +#define OCR2SB_8_REG OCR2SBH +#define OCR2SB_9_REG OCR2SBH +#define OCR2SB_10_REG OCR2SBH +#define OCR2SB_11_REG OCR2SBH + +/* OCR2SBL */ +#define OCR2SB_0_REG OCR2SBL +#define OCR2SB_1_REG OCR2SBL +#define OCR2SB_2_REG OCR2SBL +#define OCR2SB_3_REG OCR2SBL +#define OCR2SB_4_REG OCR2SBL +#define OCR2SB_5_REG OCR2SBL +#define OCR2SB_6_REG OCR2SBL +#define OCR2SB_7_REG OCR2SBL + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL0_REG UCSRC + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC0_REG PRR +#define PRPSC1_REG PRR +#define PRPSC2_REG PRR + +/* PCNF0 */ +#define PCLKSEL0_REG PCNF0 +#define POP0_REG PCNF0 +#define PMODE00_REG PCNF0 +#define PMODE01_REG PCNF0 +#define PLOCK0_REG PCNF0 +#define PALOCK0_REG PCNF0 +#define PFIFTY0_REG PCNF0 + +/* PCNF1 */ +#define PCLKSEL1_REG PCNF1 +#define POP1_REG PCNF1 +#define PMODE10_REG PCNF1 +#define PMODE11_REG PCNF1 +#define PLOCK1_REG PCNF1 +#define PALOCK1_REG PCNF1 +#define PFIFTY1_REG PCNF1 + +/* PCNF2 */ +#define POME2_REG PCNF2 +#define PCLKSEL2_REG PCNF2 +#define POP2_REG PCNF2 +#define PMODE20_REG PCNF2 +#define PMODE21_REG PCNF2 +#define PLOCK2_REG PCNF2 +#define PALOCK2_REG PCNF2 +#define PFIFTY2_REG PCNF2 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* PFRC0A */ +#define PRFM0A0_REG PFRC0A +#define PRFM0A1_REG PFRC0A +#define PRFM0A2_REG PFRC0A +#define PRFM0A3_REG PFRC0A +#define PFLTE0A_REG PFRC0A +#define PELEV0A_REG PFRC0A +#define PISEL0A_REG PFRC0A +#define PCAE0A_REG PFRC0A + +/* PFRC0B */ +#define PRFM0B0_REG PFRC0B +#define PRFM0B1_REG PFRC0B +#define PRFM0B2_REG PFRC0B +#define PRFM0B3_REG PFRC0B +#define PFLTE0B_REG PFRC0B +#define PELEV0B_REG PFRC0B +#define PISEL0B_REG PFRC0B +#define PCAE0B_REG PFRC0B + +/* PICR1H */ +#define PICR1_8_REG PICR1H +#define PICR1_9_REG PICR1H +#define PICR1_10_REG PICR1H +#define PICR1_11_REG PICR1H +#define PCST1_REG PICR1H + +/* PICR1L */ +#define PICR1_0_REG PICR1L +#define PICR1_1_REG PICR1L +#define PICR1_2_REG PICR1L +#define PICR1_3_REG PICR1L +#define PICR1_4_REG PICR1L +#define PICR1_5_REG PICR1L +#define PICR1_6_REG PICR1L +#define PICR1_7_REG PICR1L + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 + +/* OCR1RAH */ +#define OCR1RA_8_REG OCR1RAH +#define OCR1RA_9_REG OCR1RAH +#define OCR1RA_10_REG OCR1RAH +#define OCR1RA_11_REG OCR1RAH + +/* OCR1RAL */ +#define OCR1RA_0_REG OCR1RAL +#define OCR1RA_1_REG OCR1RAL +#define OCR1RA_2_REG OCR1RAL +#define OCR1RA_3_REG OCR1RAL +#define OCR1RA_4_REG OCR1RAL +#define OCR1RA_5_REG OCR1RAL +#define OCR1RA_6_REG OCR1RAL +#define OCR1RA_7_REG OCR1RAL + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0RBH */ +#define OCR0RB_8_REG OCR0RBH +#define OCR0RB_9_REG OCR0RBH +#define OCR0RB_00_REG OCR0RBH +#define OCR0RB_01_REG OCR0RBH +#define OCR0RB_02_REG OCR0RBH +#define OCR0RB_03_REG OCR0RBH +#define OCR0RB_04_REG OCR0RBH +#define OCR0RB_05_REG OCR0RBH + +/* OCR0RBL */ +#define OCR0RB_0_REG OCR0RBL +#define OCR0RB_1_REG OCR0RBL +#define OCR0RB_2_REG OCR0RBL +#define OCR0RB_3_REG OCR0RBL +#define OCR0RB_4_REG OCR0RBL +#define OCR0RB_5_REG OCR0RBL +#define OCR0RB_6_REG OCR0RBL +#define OCR0RB_7_REG OCR0RBL + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* OCR0RAL */ +#define OCR0RA_0_REG OCR0RAL +#define OCR0RA_1_REG OCR0RAL +#define OCR0RA_2_REG OCR0RAL +#define OCR0RA_3_REG OCR0RAL +#define OCR0RA_4_REG OCR0RAL +#define OCR0RA_5_REG OCR0RAL +#define OCR0RA_6_REG OCR0RAL +#define OCR0RA_7_REG OCR0RAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR3 */ +#define GPIOR30_REG GPIOR3 +#define GPIOR31_REG GPIOR3 +#define GPIOR32_REG GPIOR3 +#define GPIOR33_REG GPIOR3 +#define GPIOR34_REG GPIOR3 +#define GPIOR35_REG GPIOR3 +#define GPIOR36_REG GPIOR3 +#define GPIOR37_REG GPIOR3 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* PFRC2B */ +#define PRFM2B0_REG PFRC2B +#define PRFM2B1_REG PFRC2B +#define PRFM2B2_REG PFRC2B +#define PRFM2B3_REG PFRC2B +#define PFLTE2B_REG PFRC2B +#define PELEV2B_REG PFRC2B +#define PISEL2B_REG PFRC2B +#define PCAE2B_REG PFRC2B + +/* PFRC2A */ +#define PRFM2A0_REG PFRC2A +#define PRFM2A1_REG PFRC2A +#define PRFM2A2_REG PFRC2A +#define PRFM2A3_REG PFRC2A +#define PFLTE2A_REG PFRC2A +#define PELEV2A_REG PFRC2A +#define PISEL2A_REG PFRC2A +#define PCAE2A_REG PFRC2A + +/* OCR2SAL */ +#define OCR2SA_0_REG OCR2SAL +#define OCR2SA_1_REG OCR2SAL +#define OCR2SA_2_REG OCR2SAL +#define OCR2SA_3_REG OCR2SAL +#define OCR2SA_4_REG OCR2SAL +#define OCR2SA_5_REG OCR2SAL +#define OCR2SA_6_REG OCR2SAL +#define OCR2SA_7_REG OCR2SAL + +/* EUCSRA */ +#define URxS0_REG EUCSRA +#define URxS1_REG EUCSRA +#define URxS2_REG EUCSRA +#define URxS3_REG EUCSRA +#define UTxS0_REG EUCSRA +#define UTxS1_REG EUCSRA +#define UTxS2_REG EUCSRA +#define UTxS3_REG EUCSRA + +/* EUCSRB */ +#define BODR_REG EUCSRB +#define EMCH_REG EUCSRB +#define EUSBS_REG EUCSRB +#define EUSART_REG EUCSRB + +/* EUCSRC */ +#define STP0_REG EUCSRC +#define STP1_REG EUCSRC +#define F1617_REG EUCSRC +#define FEM_REG EUCSRC + +/* PCTL0 */ +#define PRUN0_REG PCTL0 +#define PCCYC0_REG PCTL0 +#define PARUN0_REG PCTL0 +#define PAOC0A_REG PCTL0 +#define PAOC0B_REG PCTL0 +#define PBFM0_REG PCTL0 +#define PPRE00_REG PCTL0 +#define PPRE01_REG PCTL0 + +/* PCTL1 */ +#define PRUN1_REG PCTL1 +#define PCCYC1_REG PCTL1 +#define PARUN1_REG PCTL1 +#define PAOC1A_REG PCTL1 +#define PAOC1B_REG PCTL1 +#define PBFM1_REG PCTL1 +#define PPRE10_REG PCTL1 +#define PPRE11_REG PCTL1 + +/* PCTL2 */ +#define PRUN2_REG PCTL2 +#define PCCYC2_REG PCTL2 +#define PARUN2_REG PCTL2 +#define PAOC2A_REG PCTL2 +#define PAOC2B_REG PCTL2 +#define PBFM2_REG PCTL2 +#define PPRE20_REG PCTL2 +#define PPRE21_REG PCTL2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* POM2 */ +#define POMV2A0_REG POM2 +#define POMV2A1_REG POM2 +#define POMV2A2_REG POM2 +#define POMV2A3_REG POM2 +#define POMV2B0_REG POM2 +#define POMV2B1_REG POM2 +#define POMV2B2_REG POM2 +#define POMV2B3_REG POM2 + +/* OCR2RBL */ +#define OCR2RB_0_REG OCR2RBL +#define OCR2RB_1_REG OCR2RBL +#define OCR2RB_2_REG OCR2RBL +#define OCR2RB_3_REG OCR2RBL +#define OCR2RB_4_REG OCR2RBL +#define OCR2RB_5_REG OCR2RBL +#define OCR2RB_6_REG OCR2RBL +#define OCR2RB_7_REG OCR2RBL + +/* PICR2H */ +#define PICR2_8_REG PICR2H +#define PICR2_9_REG PICR2H +#define PICR2_10_REG PICR2H +#define PICR2_11_REG PICR2H +#define PCST2_REG PICR2H + +/* OCR2RBH */ +#define OCR2RB_8_REG OCR2RBH +#define OCR2RB_9_REG OCR2RBH +#define OCR2RB_10_REG OCR2RBH +#define OCR2RB_11_REG OCR2RBH +#define OCR2RB_12_REG OCR2RBH +#define OCR2RB_13_REG OCR2RBH +#define OCR2RB_14_REG OCR2RBH +#define OCR2RB_15_REG OCR2RBH + +/* PICR2L */ +#define PICR2_0_REG PICR2L +#define PICR2_1_REG PICR2L +#define PICR2_2_REG PICR2L +#define PICR2_3_REG PICR2L +#define PICR2_4_REG PICR2L +#define PICR2_5_REG PICR2L +#define PICR2_6_REG PICR2L +#define PICR2_7_REG PICR2L + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* OCR2RAH */ +#define OCR2RA_8_REG OCR2RAH +#define OCR2RA_9_REG OCR2RAH +#define OCR2RA_10_REG OCR2RAH +#define OCR2RA_11_REG OCR2RAH + +/* OCR2RAL */ +#define OCR2RA_0_REG OCR2RAL +#define OCR2RA_1_REG OCR2RAL +#define OCR2RA_2_REG OCR2RAL +#define OCR2RA_3_REG OCR2RAL +#define OCR2RA_4_REG OCR2RAL +#define OCR2RA_5_REG OCR2RAL +#define OCR2RA_6_REG OCR2RAL +#define OCR2RA_7_REG OCR2RAL + +/* OCR0SAL */ +#define OCR0SA_0_REG OCR0SAL +#define OCR0SA_1_REG OCR0SAL +#define OCR0SA_2_REG OCR0SAL +#define OCR0SA_3_REG OCR0SAL +#define OCR0SA_4_REG OCR0SAL +#define OCR0SA_5_REG OCR0SAL +#define OCR0SA_6_REG OCR0SAL +#define OCR0SA_7_REG OCR0SAL + +/* OCR0SAH */ +#define OCR0SA_8_REG OCR0SAH +#define OCR0SA_9_REG OCR0SAH +#define OCR0SA_00_REG OCR0SAH +#define OCR0SA_01_REG OCR0SAH + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* PICR0H */ +#define PICR0_8_REG PICR0H +#define PICR0_9_REG PICR0H +#define PICR0_10_REG PICR0H +#define PICR0_11_REG PICR0H +#define PCST0_REG PICR0H + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* MUBRRL */ +#define MUBRR0_REG MUBRRL +#define MUBRR1_REG MUBRRL +#define MUBRR2_REG MUBRRL +#define MUBRR3_REG MUBRRL +#define MUBRR4_REG MUBRRL +#define MUBRR5_REG MUBRRL +#define MUBRR6_REG MUBRRL +#define MUBRR7_REG MUBRRL + +/* MUBRRH */ +#define MUBRR8_REG MUBRRH +#define MUBRR9_REG MUBRRH +#define MUBRR10_REG MUBRRH +#define MUBRR11_REG MUBRRH +#define MUBRR12_REG MUBRRH +#define MUBRR13_REG MUBRRH +#define MUBRR14_REG MUBRRH +#define MUBRR15_REG MUBRRH + +/* OCR2SAH */ +#define OCR2SA_8_REG OCR2SAH +#define OCR2SA_9_REG OCR2SAH +#define OCR2SA_10_REG OCR2SAH +#define OCR2SA_11_REG OCR2SAH + +/* OCR0SBL */ +#define OCR0SB_0_REG OCR0SBL +#define OCR0SB_1_REG OCR0SBL +#define OCR0SB_2_REG OCR0SBL +#define OCR0SB_3_REG OCR0SBL +#define OCR0SB_4_REG OCR0SBL +#define OCR0SB_5_REG OCR0SBL +#define OCR0SB_6_REG OCR0SBL +#define OCR0SB_7_REG OCR0SBL + +/* OCR0SBH */ +#define OCR0SB_8_REG OCR0SBH +#define OCR0SB_9_REG OCR0SBH +#define OCR0SB_00_REG OCR0SBH +#define OCR0SB_01_REG OCR0SBH + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* PFRC1B */ +#define PRFM1B0_REG PFRC1B +#define PRFM1B1_REG PFRC1B +#define PRFM1B2_REG PFRC1B +#define PRFM1B3_REG PFRC1B +#define PFLTE1B_REG PFRC1B +#define PELEV1B_REG PFRC1B +#define PISEL1B_REG PFRC1B +#define PCAE1B_REG PFRC1B + +/* PFRC1A */ +#define PRFM1A0_REG PFRC1A +#define PRFM1A1_REG PFRC1A +#define PRFM1A2_REG PFRC1A +#define PRFM1A3_REG PFRC1A +#define PFLTE1A_REG PFRC1A +#define PELEV1A_REG PFRC1A +#define PISEL1A_REG PFRC1A +#define PCAE1A_REG PFRC1A + +/* PICR0L */ +#define PICR0_0_REG PICR0L +#define PICR0_1_REG PICR0L +#define PICR0_2_REG PICR0L +#define PICR0_3_REG PICR0L +#define PICR0_4_REG PICR0L +#define PICR0_5_REG PICR0L +#define PICR0_6_REG PICR0L +#define PICR0_7_REG PICR0L + +/* OCR1SAL */ +#define OCR1SA_0_REG OCR1SAL +#define OCR1SA_1_REG OCR1SAL +#define OCR1SA_2_REG OCR1SAL +#define OCR1SA_3_REG OCR1SAL +#define OCR1SA_4_REG OCR1SAL +#define OCR1SA_5_REG OCR1SAL +#define OCR1SA_6_REG OCR1SAL +#define OCR1SA_7_REG OCR1SAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* PSOC0 */ +#define POEN0A_REG PSOC0 +#define POEN0B_REG PSOC0 +#define PSYNC00_REG PSOC0 +#define PSYNC01_REG PSOC0 + +/* PSOC1 */ +#define POEN1A_REG PSOC1 +#define POEN1B_REG PSOC1 +#define PSYNC1_0_REG PSOC1 +#define PSYNC1_1_REG PSOC1 + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define ACCKDIV_REG ACSR + +/* OCR1RBL */ +#define OCR1RB_0_REG OCR1RBL +#define OCR1RB_1_REG OCR1RBL +#define OCR1RB_2_REG OCR1RBL +#define OCR1RB_3_REG OCR1RBL +#define OCR1RB_4_REG OCR1RBL +#define OCR1RB_5_REG OCR1RBL +#define OCR1RB_6_REG OCR1RBL +#define OCR1RB_7_REG OCR1RBL + +/* OCR1SBH */ +#define OCR1SB_8_REG OCR1SBH +#define OCR1SB_9_REG OCR1SBH +#define OCR1SB_10_REG OCR1SBH +#define OCR1SB_11_REG OCR1SBH + +/* OCR1RBH */ +#define OCR1RB_8_REG OCR1RBH +#define OCR1RB_9_REG OCR1RBH +#define OCR1RB_10_REG OCR1RBH +#define OCR1RB_11_REG OCR1RBH +#define OCR1RB_12_REG OCR1RBH +#define OCR1RB_13_REG OCR1RBH +#define OCR1RB_14_REG OCR1RBH +#define OCR1RB_15_REG OCR1RBH + +/* OCR1SBL */ +#define OCR1SB_0_REG OCR1SBL +#define OCR1SB_1_REG OCR1SBL +#define OCR1SB_2_REG OCR1SBL +#define OCR1SB_3_REG OCR1SBL +#define OCR1SB_4_REG OCR1SBL +#define OCR1SB_5_REG OCR1SBL +#define OCR1SB_6_REG OCR1SBL +#define OCR1SB_7_REG OCR1SBL + +/* OCR1SAH */ +#define OCR1SA_8_REG OCR1SAH +#define OCR1SA_9_REG OCR1SAH +#define OCR1SA_10_REG OCR1SAH +#define OCR1SA_11_REG OCR1SAH + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* OCR0RAH */ +#define OCR0RA_8_REG OCR0RAH +#define OCR0RA_9_REG OCR0RAH +#define OCR0RA_00_REG OCR0RAH +#define OCR0RA_01_REG OCR0RAH + +/* PIM2 */ +#define PEOPE2_REG PIM2 +#define PEVE2A_REG PIM2 +#define PEVE2B_REG PIM2 +#define PSEIE2_REG PIM2 + +/* PIM0 */ +#define PEOPE0_REG PIM0 +#define PEVE0A_REG PIM0 +#define PEVE0B_REG PIM0 +#define PSEIE0_REG PIM0 + +/* PIM1 */ +#define PEOPE1_REG PIM1 +#define PEVE1A_REG PIM1 +#define PEVE1B_REG PIM1 +#define PSEIE1_REG PIM1 + +/* PIFR2 */ +#define PEOP2_REG PIFR2 +#define PRN20_REG PIFR2 +#define PRN21_REG PIFR2 +#define PEV2A_REG PIFR2 +#define PEV2B_REG PIFR2 +#define PSEI2_REG PIFR2 +#define POAC2A_REG PIFR2 +#define POAC2B_REG PIFR2 + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PIFR0 */ +#define PEOP0_REG PIFR0 +#define PRN00_REG PIFR0 +#define PRN01_REG PIFR0 +#define PEV0A_REG PIFR0 +#define PEV0B_REG PIFR0 +#define PSEI0_REG PIFR0 +#define POAC0A_REG PIFR0 +#define POAC0B_REG PIFR0 + +/* PIFR1 */ +#define PEOP1_REG PIFR1 +#define PRN10_REG PIFR1 +#define PRN11_REG PIFR1 +#define PEV1A_REG PIFR1 +#define PEV1B_REG PIFR1 +#define PSEI1_REG PIFR1 +#define POAC1A_REG PIFR1 +#define POAC1B_REG PIFR1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PSOC2 */ +#define POEN2A_REG PSOC2 +#define POEN2C_REG PSOC2 +#define POEN2B_REG PSOC2 +#define POEN2D_REG PSOC2 +#define PSYNC2_0_REG PSOC2 +#define PSYNC2_1_REG PSOC2 +#define POS22_REG PSOC2 +#define POS23_REG PSOC2 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define ADASCR_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT20_PORT PORTB +#define PSCOUT20_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT21_PORT PORTB +#define PSCOUT21_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT11_PORT PORTB +#define PSCOUT11_BIT 6 +#define ICP1B_PORT PORTB +#define ICP1B_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT01_PORT PORTB +#define PSCOUT01_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define INT3_PORT PORTC +#define INT3_BIT 0 +#define PSCOUT10_PORT PORTC +#define PSCOUT10_BIT 0 + +#define PSCIN1_PORT PORTC +#define PSCIN1_BIT 1 +#define OC1B_PORT PORTC +#define OC1B_BIT 1 + +#define T0_PORT PORTC +#define T0_BIT 2 +#define PSCOUT22_PORT PORTC +#define PSCOUT22_BIT 2 + +#define T1_PORT PORTC +#define T1_BIT 3 +#define PSCOUT23_PORT PORTC +#define PSCOUT23_BIT 3 + +#define ADC8_PORT PORTC +#define ADC8_BIT 4 +#define AMP1-_PORT PORTC +#define AMP1-_BIT 4 + +#define ADC9_PORT PORTC +#define ADC9_BIT 5 +#define AMP1+_PORT PORTC +#define AMP1+_BIT 5 + +#define ADC10_PORT PORTC +#define ADC10_BIT 6 +#define ACMP1_PORT PORTC +#define ACMP1_BIT 6 + +#define D2A_PORT PORTC +#define D2A_BIT 7 + +#define PSCOUT00_PORT PORTD +#define PSCOUT00_BIT 0 +#define XCK_PORT PORTD +#define XCK_BIT 0 +#define SSA_PORT PORTD +#define SSA_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define DALI_PORT PORTD +#define DALI_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define DALI_PORT PORTD +#define DALI_BIT 4 +#define ICP1_PORT PORTD +#define ICP1_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACOMP2_PORT PORTD +#define ACOMP2_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPM_PORT PORTD +#define ACMPM_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 + + diff --git a/include/aversive/parts/AT90PWM3B.h b/include/aversive/parts/AT90PWM3B.h new file mode 100644 index 0000000..4ed1173 --- /dev/null +++ b/include/aversive/parts/AT90PWM3B.h @@ -0,0 +1,1450 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* EUDR */ +#define EUDR0_REG EUDR +#define EUDR1_REG EUDR +#define EUDR2_REG EUDR +#define EUDR3_REG EUDR +#define EUDR4_REG EUDR +#define EUDR5_REG EUDR +#define EUDR6_REG EUDR +#define EUDR7_REG EUDR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* OCR2SBH */ +#define OCR2SB_8_REG OCR2SBH +#define OCR2SB_9_REG OCR2SBH +#define OCR2SB_10_REG OCR2SBH +#define OCR2SB_11_REG OCR2SBH + +/* OCR2SBL */ +#define OCR2SB_0_REG OCR2SBL +#define OCR2SB_1_REG OCR2SBL +#define OCR2SB_2_REG OCR2SBL +#define OCR2SB_3_REG OCR2SBL +#define OCR2SB_4_REG OCR2SBL +#define OCR2SB_5_REG OCR2SBL +#define OCR2SB_6_REG OCR2SBL +#define OCR2SB_7_REG OCR2SBL + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL0_REG UCSRC + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC0_REG PRR +#define PRPSC1_REG PRR +#define PRPSC2_REG PRR + +/* PCNF0 */ +#define PCLKSEL0_REG PCNF0 +#define POP0_REG PCNF0 +#define PMODE00_REG PCNF0 +#define PMODE01_REG PCNF0 +#define PLOCK0_REG PCNF0 +#define PALOCK0_REG PCNF0 +#define PFIFTY0_REG PCNF0 + +/* PCNF1 */ +#define PCLKSEL1_REG PCNF1 +#define POP1_REG PCNF1 +#define PMODE10_REG PCNF1 +#define PMODE11_REG PCNF1 +#define PLOCK1_REG PCNF1 +#define PALOCK1_REG PCNF1 +#define PFIFTY1_REG PCNF1 + +/* PCNF2 */ +#define POME2_REG PCNF2 +#define PCLKSEL2_REG PCNF2 +#define POP2_REG PCNF2 +#define PMODE20_REG PCNF2 +#define PMODE21_REG PCNF2 +#define PLOCK2_REG PCNF2 +#define PALOCK2_REG PCNF2 +#define PFIFTY2_REG PCNF2 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* PFRC0A */ +#define PRFM0A0_REG PFRC0A +#define PRFM0A1_REG PFRC0A +#define PRFM0A2_REG PFRC0A +#define PRFM0A3_REG PFRC0A +#define PFLTE0A_REG PFRC0A +#define PELEV0A_REG PFRC0A +#define PISEL0A_REG PFRC0A +#define PCAE0A_REG PFRC0A + +/* PFRC0B */ +#define PRFM0B0_REG PFRC0B +#define PRFM0B1_REG PFRC0B +#define PRFM0B2_REG PFRC0B +#define PRFM0B3_REG PFRC0B +#define PFLTE0B_REG PFRC0B +#define PELEV0B_REG PFRC0B +#define PISEL0B_REG PFRC0B +#define PCAE0B_REG PFRC0B + +/* PICR1H */ +#define PICR1_8_REG PICR1H +#define PICR1_9_REG PICR1H +#define PICR1_10_REG PICR1H +#define PICR1_11_REG PICR1H +#define PCST1_REG PICR1H + +/* PICR1L */ +#define PICR1_0_REG PICR1L +#define PICR1_1_REG PICR1L +#define PICR1_2_REG PICR1L +#define PICR1_3_REG PICR1L +#define PICR1_4_REG PICR1L +#define PICR1_5_REG PICR1L +#define PICR1_6_REG PICR1L +#define PICR1_7_REG PICR1L + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 + +/* OCR1RAH */ +#define OCR1RA_8_REG OCR1RAH +#define OCR1RA_9_REG OCR1RAH +#define OCR1RA_10_REG OCR1RAH +#define OCR1RA_11_REG OCR1RAH + +/* OCR1RAL */ +#define OCR1RA_0_REG OCR1RAL +#define OCR1RA_1_REG OCR1RAL +#define OCR1RA_2_REG OCR1RAL +#define OCR1RA_3_REG OCR1RAL +#define OCR1RA_4_REG OCR1RAL +#define OCR1RA_5_REG OCR1RAL +#define OCR1RA_6_REG OCR1RAL +#define OCR1RA_7_REG OCR1RAL + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0RBH */ +#define OCR0RB_8_REG OCR0RBH +#define OCR0RB_9_REG OCR0RBH +#define OCR0RB_00_REG OCR0RBH +#define OCR0RB_01_REG OCR0RBH +#define OCR0RB_02_REG OCR0RBH +#define OCR0RB_03_REG OCR0RBH +#define OCR0RB_04_REG OCR0RBH +#define OCR0RB_05_REG OCR0RBH + +/* OCR0RBL */ +#define OCR0RB_0_REG OCR0RBL +#define OCR0RB_1_REG OCR0RBL +#define OCR0RB_2_REG OCR0RBL +#define OCR0RB_3_REG OCR0RBL +#define OCR0RB_4_REG OCR0RBL +#define OCR0RB_5_REG OCR0RBL +#define OCR0RB_6_REG OCR0RBL +#define OCR0RB_7_REG OCR0RBL + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* OCR0RAL */ +#define OCR0RA_0_REG OCR0RAL +#define OCR0RA_1_REG OCR0RAL +#define OCR0RA_2_REG OCR0RAL +#define OCR0RA_3_REG OCR0RAL +#define OCR0RA_4_REG OCR0RAL +#define OCR0RA_5_REG OCR0RAL +#define OCR0RA_6_REG OCR0RAL +#define OCR0RA_7_REG OCR0RAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR3 */ +#define GPIOR30_REG GPIOR3 +#define GPIOR31_REG GPIOR3 +#define GPIOR32_REG GPIOR3 +#define GPIOR33_REG GPIOR3 +#define GPIOR34_REG GPIOR3 +#define GPIOR35_REG GPIOR3 +#define GPIOR36_REG GPIOR3 +#define GPIOR37_REG GPIOR3 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* PFRC2B */ +#define PRFM2B0_REG PFRC2B +#define PRFM2B1_REG PFRC2B +#define PRFM2B2_REG PFRC2B +#define PRFM2B3_REG PFRC2B +#define PFLTE2B_REG PFRC2B +#define PELEV2B_REG PFRC2B +#define PISEL2B_REG PFRC2B +#define PCAE2B_REG PFRC2B + +/* PFRC2A */ +#define PRFM2A0_REG PFRC2A +#define PRFM2A1_REG PFRC2A +#define PRFM2A2_REG PFRC2A +#define PRFM2A3_REG PFRC2A +#define PFLTE2A_REG PFRC2A +#define PELEV2A_REG PFRC2A +#define PISEL2A_REG PFRC2A +#define PCAE2A_REG PFRC2A + +/* OCR2SAL */ +#define OCR2SA_0_REG OCR2SAL +#define OCR2SA_1_REG OCR2SAL +#define OCR2SA_2_REG OCR2SAL +#define OCR2SA_3_REG OCR2SAL +#define OCR2SA_4_REG OCR2SAL +#define OCR2SA_5_REG OCR2SAL +#define OCR2SA_6_REG OCR2SAL +#define OCR2SA_7_REG OCR2SAL + +/* EUCSRA */ +#define URxS0_REG EUCSRA +#define URxS1_REG EUCSRA +#define URxS2_REG EUCSRA +#define URxS3_REG EUCSRA +#define UTxS0_REG EUCSRA +#define UTxS1_REG EUCSRA +#define UTxS2_REG EUCSRA +#define UTxS3_REG EUCSRA + +/* EUCSRB */ +#define BODR_REG EUCSRB +#define EMCH_REG EUCSRB +#define EUSBS_REG EUCSRB +#define EUSART_REG EUCSRB + +/* EUCSRC */ +#define STP0_REG EUCSRC +#define STP1_REG EUCSRC +#define F1617_REG EUCSRC +#define FEM_REG EUCSRC + +/* PCTL0 */ +#define PRUN0_REG PCTL0 +#define PCCYC0_REG PCTL0 +#define PARUN0_REG PCTL0 +#define PAOC0A_REG PCTL0 +#define PAOC0B_REG PCTL0 +#define PBFM0_REG PCTL0 +#define PPRE00_REG PCTL0 +#define PPRE01_REG PCTL0 + +/* PCTL1 */ +#define PRUN1_REG PCTL1 +#define PCCYC1_REG PCTL1 +#define PARUN1_REG PCTL1 +#define PAOC1A_REG PCTL1 +#define PAOC1B_REG PCTL1 +#define PBFM1_REG PCTL1 +#define PPRE10_REG PCTL1 +#define PPRE11_REG PCTL1 + +/* PCTL2 */ +#define PRUN2_REG PCTL2 +#define PCCYC2_REG PCTL2 +#define PARUN2_REG PCTL2 +#define PAOC2A_REG PCTL2 +#define PAOC2B_REG PCTL2 +#define PBFM2_REG PCTL2 +#define PPRE20_REG PCTL2 +#define PPRE21_REG PCTL2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* POM2 */ +#define POMV2A0_REG POM2 +#define POMV2A1_REG POM2 +#define POMV2A2_REG POM2 +#define POMV2A3_REG POM2 +#define POMV2B0_REG POM2 +#define POMV2B1_REG POM2 +#define POMV2B2_REG POM2 +#define POMV2B3_REG POM2 + +/* OCR2RBL */ +#define OCR2RB_0_REG OCR2RBL +#define OCR2RB_1_REG OCR2RBL +#define OCR2RB_2_REG OCR2RBL +#define OCR2RB_3_REG OCR2RBL +#define OCR2RB_4_REG OCR2RBL +#define OCR2RB_5_REG OCR2RBL +#define OCR2RB_6_REG OCR2RBL +#define OCR2RB_7_REG OCR2RBL + +/* PICR2H */ +#define PICR2_8_REG PICR2H +#define PICR2_9_REG PICR2H +#define PICR2_10_REG PICR2H +#define PICR2_11_REG PICR2H +#define PCST2_REG PICR2H + +/* OCR2RBH */ +#define OCR2RB_8_REG OCR2RBH +#define OCR2RB_9_REG OCR2RBH +#define OCR2RB_10_REG OCR2RBH +#define OCR2RB_11_REG OCR2RBH +#define OCR2RB_12_REG OCR2RBH +#define OCR2RB_13_REG OCR2RBH +#define OCR2RB_14_REG OCR2RBH +#define OCR2RB_15_REG OCR2RBH + +/* PICR2L */ +#define PICR2_0_REG PICR2L +#define PICR2_1_REG PICR2L +#define PICR2_2_REG PICR2L +#define PICR2_3_REG PICR2L +#define PICR2_4_REG PICR2L +#define PICR2_5_REG PICR2L +#define PICR2_6_REG PICR2L +#define PICR2_7_REG PICR2L + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* OCR2RAH */ +#define OCR2RA_8_REG OCR2RAH +#define OCR2RA_9_REG OCR2RAH +#define OCR2RA_10_REG OCR2RAH +#define OCR2RA_11_REG OCR2RAH + +/* OCR2RAL */ +#define OCR2RA_0_REG OCR2RAL +#define OCR2RA_1_REG OCR2RAL +#define OCR2RA_2_REG OCR2RAL +#define OCR2RA_3_REG OCR2RAL +#define OCR2RA_4_REG OCR2RAL +#define OCR2RA_5_REG OCR2RAL +#define OCR2RA_6_REG OCR2RAL +#define OCR2RA_7_REG OCR2RAL + +/* OCR0SAL */ +#define OCR0SA_0_REG OCR0SAL +#define OCR0SA_1_REG OCR0SAL +#define OCR0SA_2_REG OCR0SAL +#define OCR0SA_3_REG OCR0SAL +#define OCR0SA_4_REG OCR0SAL +#define OCR0SA_5_REG OCR0SAL +#define OCR0SA_6_REG OCR0SAL +#define OCR0SA_7_REG OCR0SAL + +/* OCR0SAH */ +#define OCR0SA_8_REG OCR0SAH +#define OCR0SA_9_REG OCR0SAH +#define OCR0SA_00_REG OCR0SAH +#define OCR0SA_01_REG OCR0SAH + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* PICR0H */ +#define PICR0_8_REG PICR0H +#define PICR0_9_REG PICR0H +#define PICR0_10_REG PICR0H +#define PICR0_11_REG PICR0H +#define PCST0_REG PICR0H + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* MUBRRL */ +#define MUBRR0_REG MUBRRL +#define MUBRR1_REG MUBRRL +#define MUBRR2_REG MUBRRL +#define MUBRR3_REG MUBRRL +#define MUBRR4_REG MUBRRL +#define MUBRR5_REG MUBRRL +#define MUBRR6_REG MUBRRL +#define MUBRR7_REG MUBRRL + +/* MUBRRH */ +#define MUBRR8_REG MUBRRH +#define MUBRR9_REG MUBRRH +#define MUBRR10_REG MUBRRH +#define MUBRR11_REG MUBRRH +#define MUBRR12_REG MUBRRH +#define MUBRR13_REG MUBRRH +#define MUBRR14_REG MUBRRH +#define MUBRR15_REG MUBRRH + +/* OCR2SAH */ +#define OCR2SA_8_REG OCR2SAH +#define OCR2SA_9_REG OCR2SAH +#define OCR2SA_10_REG OCR2SAH +#define OCR2SA_11_REG OCR2SAH + +/* OCR0SBL */ +#define OCR0SB_0_REG OCR0SBL +#define OCR0SB_1_REG OCR0SBL +#define OCR0SB_2_REG OCR0SBL +#define OCR0SB_3_REG OCR0SBL +#define OCR0SB_4_REG OCR0SBL +#define OCR0SB_5_REG OCR0SBL +#define OCR0SB_6_REG OCR0SBL +#define OCR0SB_7_REG OCR0SBL + +/* OCR0SBH */ +#define OCR0SB_8_REG OCR0SBH +#define OCR0SB_9_REG OCR0SBH +#define OCR0SB_00_REG OCR0SBH +#define OCR0SB_01_REG OCR0SBH + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* PFRC1B */ +#define PRFM1B0_REG PFRC1B +#define PRFM1B1_REG PFRC1B +#define PRFM1B2_REG PFRC1B +#define PRFM1B3_REG PFRC1B +#define PFLTE1B_REG PFRC1B +#define PELEV1B_REG PFRC1B +#define PISEL1B_REG PFRC1B +#define PCAE1B_REG PFRC1B + +/* PFRC1A */ +#define PRFM1A0_REG PFRC1A +#define PRFM1A1_REG PFRC1A +#define PRFM1A2_REG PFRC1A +#define PRFM1A3_REG PFRC1A +#define PFLTE1A_REG PFRC1A +#define PELEV1A_REG PFRC1A +#define PISEL1A_REG PFRC1A +#define PCAE1A_REG PFRC1A + +/* PICR0L */ +#define PICR0_0_REG PICR0L +#define PICR0_1_REG PICR0L +#define PICR0_2_REG PICR0L +#define PICR0_3_REG PICR0L +#define PICR0_4_REG PICR0L +#define PICR0_5_REG PICR0L +#define PICR0_6_REG PICR0L +#define PICR0_7_REG PICR0L + +/* OCR1SAL */ +#define OCR1SA_0_REG OCR1SAL +#define OCR1SA_1_REG OCR1SAL +#define OCR1SA_2_REG OCR1SAL +#define OCR1SA_3_REG OCR1SAL +#define OCR1SA_4_REG OCR1SAL +#define OCR1SA_5_REG OCR1SAL +#define OCR1SA_6_REG OCR1SAL +#define OCR1SA_7_REG OCR1SAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* PSOC0 */ +#define POEN0A_REG PSOC0 +#define POEN0B_REG PSOC0 +#define PSYNC00_REG PSOC0 +#define PSYNC01_REG PSOC0 + +/* PSOC1 */ +#define POEN1A_REG PSOC1 +#define POEN1B_REG PSOC1 +#define PSYNC1_0_REG PSOC1 +#define PSYNC1_1_REG PSOC1 + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define ACCKDIV_REG ACSR + +/* OCR1RBL */ +#define OCR1RB_0_REG OCR1RBL +#define OCR1RB_1_REG OCR1RBL +#define OCR1RB_2_REG OCR1RBL +#define OCR1RB_3_REG OCR1RBL +#define OCR1RB_4_REG OCR1RBL +#define OCR1RB_5_REG OCR1RBL +#define OCR1RB_6_REG OCR1RBL +#define OCR1RB_7_REG OCR1RBL + +/* OCR1SBH */ +#define OCR1SB_8_REG OCR1SBH +#define OCR1SB_9_REG OCR1SBH +#define OCR1SB_10_REG OCR1SBH +#define OCR1SB_11_REG OCR1SBH + +/* OCR1RBH */ +#define OCR1RB_8_REG OCR1RBH +#define OCR1RB_9_REG OCR1RBH +#define OCR1RB_10_REG OCR1RBH +#define OCR1RB_11_REG OCR1RBH +#define OCR1RB_12_REG OCR1RBH +#define OCR1RB_13_REG OCR1RBH +#define OCR1RB_14_REG OCR1RBH +#define OCR1RB_15_REG OCR1RBH + +/* OCR1SBL */ +#define OCR1SB_0_REG OCR1SBL +#define OCR1SB_1_REG OCR1SBL +#define OCR1SB_2_REG OCR1SBL +#define OCR1SB_3_REG OCR1SBL +#define OCR1SB_4_REG OCR1SBL +#define OCR1SB_5_REG OCR1SBL +#define OCR1SB_6_REG OCR1SBL +#define OCR1SB_7_REG OCR1SBL + +/* OCR1SAH */ +#define OCR1SA_8_REG OCR1SAH +#define OCR1SA_9_REG OCR1SAH +#define OCR1SA_10_REG OCR1SAH +#define OCR1SA_11_REG OCR1SAH + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* OCR0RAH */ +#define OCR0RA_8_REG OCR0RAH +#define OCR0RA_9_REG OCR0RAH +#define OCR0RA_00_REG OCR0RAH +#define OCR0RA_01_REG OCR0RAH + +/* PIM2 */ +#define PEOPE2_REG PIM2 +#define PEVE2A_REG PIM2 +#define PEVE2B_REG PIM2 +#define PSEIE2_REG PIM2 + +/* PIM0 */ +#define PEOPE0_REG PIM0 +#define PEVE0A_REG PIM0 +#define PEVE0B_REG PIM0 +#define PSEIE0_REG PIM0 + +/* PIM1 */ +#define PEOPE1_REG PIM1 +#define PEVE1A_REG PIM1 +#define PEVE1B_REG PIM1 +#define PSEIE1_REG PIM1 + +/* PIFR2 */ +#define PEOP2_REG PIFR2 +#define PRN20_REG PIFR2 +#define PRN21_REG PIFR2 +#define PEV2A_REG PIFR2 +#define PEV2B_REG PIFR2 +#define PSEI2_REG PIFR2 +#define POAC2A_REG PIFR2 +#define POAC2B_REG PIFR2 + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PIFR0 */ +#define PEOP0_REG PIFR0 +#define PRN00_REG PIFR0 +#define PRN01_REG PIFR0 +#define PEV0A_REG PIFR0 +#define PEV0B_REG PIFR0 +#define PSEI0_REG PIFR0 +#define POAC0A_REG PIFR0 +#define POAC0B_REG PIFR0 + +/* PIFR1 */ +#define PEOP1_REG PIFR1 +#define PRN10_REG PIFR1 +#define PRN11_REG PIFR1 +#define PEV1A_REG PIFR1 +#define PEV1B_REG PIFR1 +#define PSEI1_REG PIFR1 +#define POAC1A_REG PIFR1 +#define POAC1B_REG PIFR1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PSOC2 */ +#define POEN2A_REG PSOC2 +#define POEN2C_REG PSOC2 +#define POEN2B_REG PSOC2 +#define POEN2D_REG PSOC2 +#define PSYNC2_0_REG PSOC2 +#define PSYNC2_1_REG PSOC2 +#define POS22_REG PSOC2 +#define POS23_REG PSOC2 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define ADASCR_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT20_PORT PORTB +#define PSCOUT20_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT21_PORT PORTB +#define PSCOUT21_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT11_PORT PORTB +#define PSCOUT11_BIT 6 +#define ICP1B_PORT PORTB +#define ICP1B_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT01_PORT PORTB +#define PSCOUT01_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define INT3_PORT PORTC +#define INT3_BIT 0 +#define PSCOUT10_PORT PORTC +#define PSCOUT10_BIT 0 + +#define PSCIN1_PORT PORTC +#define PSCIN1_BIT 1 +#define OC1B_PORT PORTC +#define OC1B_BIT 1 + +#define T0_PORT PORTC +#define T0_BIT 2 +#define PSCOUT22_PORT PORTC +#define PSCOUT22_BIT 2 + +#define T1_PORT PORTC +#define T1_BIT 3 +#define PSCOUT23_PORT PORTC +#define PSCOUT23_BIT 3 + +#define ADC8_PORT PORTC +#define ADC8_BIT 4 +#define AMP1-_PORT PORTC +#define AMP1-_BIT 4 + +#define ADC9_PORT PORTC +#define ADC9_BIT 5 +#define AMP1+_PORT PORTC +#define AMP1+_BIT 5 + +#define ADC10_PORT PORTC +#define ADC10_BIT 6 +#define ACMP1_PORT PORTC +#define ACMP1_BIT 6 + +#define D2A_PORT PORTC +#define D2A_BIT 7 + +#define PSCOUT00_PORT PORTD +#define PSCOUT00_BIT 0 +#define XCK_PORT PORTD +#define XCK_BIT 0 +#define SSA_PORT PORTD +#define SSA_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define DALI_PORT PORTD +#define DALI_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define DALI_PORT PORTD +#define DALI_BIT 4 +#define ICP1_PORT PORTD +#define ICP1_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACOMP2_PORT PORTD +#define ACOMP2_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPM_PORT PORTD +#define ACMPM_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 + + diff --git a/include/aversive/parts/AT90S1200.h b/include/aversive/parts/AT90S1200.h new file mode 100644 index 0000000..16df827 --- /dev/null +++ b/include/aversive/parts/AT90S1200.h @@ -0,0 +1,228 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* TIMSK */ +#define TOIE0_REG TIMSK + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TIFR */ +#define TOV0_REG TIFR + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD + +/* pins mapping */ +#define AIN0_PORT PORTB +#define AIN0_BIT 0 + +#define AIN1_PORT PORTB +#define AIN1_BIT 1 + + + + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + + + +#define INT0_PORT PORTD +#define INT0_BIT 2 + + +#define T0_PORT PORTD +#define T0_BIT 4 + + + + diff --git a/include/aversive/parts/AT90S2313.h b/include/aversive/parts/AT90S2313.h new file mode 100644 index 0000000..a9d4c0e --- /dev/null +++ b/include/aversive/parts/AT90S2313.h @@ -0,0 +1,401 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1_NUM 0 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1 + +/* Pwm nums */ +#define PWM1_NUM 0 +#define PWM_TOTAL_NUM 1 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* USR */ +#define OR_REG USR +#define FE_REG USR +#define UDRE_REG USR +#define TXC_REG USR +#define RXC_REG USR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TICIE1_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK + +/* UCR */ +#define TXB8_REG UCR +#define RXB8_REG UCR +#define CHR9_REG UCR +#define TXEN_REG UCR +#define RXEN_REG UCR +#define UDRIE_REG UCR +#define TXCIE_REG UCR +#define RXCIE_REG UCR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* TIFR */ +#define TOV0_REG TIFR +#define ICF1_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* pins mapping */ +#define AIN0_PORT PORTB +#define AIN0_BIT 0 + +#define AIN1_PORT PORTB +#define AIN1_BIT 1 + + +#define OC1_PORT PORTB +#define OC1_BIT 3 + + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define T0_PORT PORTD +#define T0_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + + diff --git a/include/aversive/parts/AT90S2323.h b/include/aversive/parts/AT90S2323.h new file mode 100644 index 0000000..92e212f --- /dev/null +++ b/include/aversive/parts/AT90S2323.h @@ -0,0 +1,181 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* GIFR */ +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* TIFR */ +#define TOV0_REG TIFR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 + + diff --git a/include/aversive/parts/AT90S2343.h b/include/aversive/parts/AT90S2343.h new file mode 100644 index 0000000..86cc1e3 --- /dev/null +++ b/include/aversive/parts/AT90S2343.h @@ -0,0 +1,191 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* GIFR */ +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* TIFR */ +#define TOV0_REG TIFR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 + +#define CLOCK_PORT PORTB +#define CLOCK_BIT 3 + + + diff --git a/include/aversive/parts/AT90S4414.h b/include/aversive/parts/AT90S4414.h new file mode 100644 index 0000000..8157784 --- /dev/null +++ b/include/aversive/parts/AT90S4414.h @@ -0,0 +1,566 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ + + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 2 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM_TOTAL_NUM 2 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* USR */ +#define OR_REG USR +#define FE_REG USR +#define UDRE_REG USR +#define TXC_REG USR +#define RXC_REG USR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK +#define TOIE0_REG TIMSK + +/* UCR */ +#define TXB8_REG UCR +#define RXB8_REG UCR +#define CHR9_REG UCR +#define TXEN_REG UCR +#define RXEN_REG UCR +#define UDRIE_REG UCR +#define TXCIE_REG UCR +#define RXCIE_REG UCR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR +#define EEAR7_REG EEAR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* TIFR */ +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR +#define TOV0_REG TIFR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR +#define SRW_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + + diff --git a/include/aversive/parts/AT90S4433.h b/include/aversive/parts/AT90S4433.h new file mode 100644 index 0000000..dd2a1af --- /dev/null +++ b/include/aversive/parts/AT90S4433.h @@ -0,0 +1,478 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1_NUM 0 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1 + +/* Pwm nums */ +#define PWM1_NUM 0 +#define PWM_TOTAL_NUM 1 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define ADCBG_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM10_REG TCCR1A +#define COM11_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TICIE1_REG TIMSK +#define OCIE1_REG TIMSK +#define TOIE1_REG TIMSK + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* UBRRHI */ +#define UBRRHI0_REG UBRRHI +#define UBRRHI1_REG UBRRHI +#define UBRRHI2_REG UBRRHI +#define UBRRHI3_REG UBRRHI + +/* SPSR */ +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define AINBG_REG ACSR +#define ACD_REG ACSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSRA */ +#define MPCM_REG UCSRA +#define OR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define CHR9_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* ADCL */ +#define ADC0_REG ADCL +#define ADC1_REG ADCL +#define ADC2_REG ADCL +#define ADC3_REG ADCL +#define ADC4_REG ADCL +#define ADC5_REG ADCL +#define ADC6_REG ADCL +#define ADC7_REG ADCL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR +#define EEAR7_REG EEAR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC + +/* ADCH */ +#define ADC8_REG ADCH +#define ADC9_REG ADCH + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* TIFR */ +#define TOV0_REG TIFR +#define ICF1_REG TIFR +#define OCF1_REG TIFR +#define TOV1_REG TIFR + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* OCR1L */ +#define OCR1AL0_REG OCR1L +#define OCR1AL1_REG OCR1L +#define OCR1AL2_REG OCR1L +#define OCR1AL3_REG OCR1L +#define OCR1AL4_REG OCR1L +#define OCR1AL5_REG OCR1L +#define OCR1AL6_REG OCR1L +#define OCR1AL7_REG OCR1L + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* OCR1H */ +#define OCR1AH0_REG OCR1H +#define OCR1AH1_REG OCR1H +#define OCR1AH2_REG OCR1H +#define OCR1AH3_REG OCR1H +#define OCR1AH4_REG OCR1H +#define OCR1AH5_REG OCR1H +#define OCR1AH6_REG OCR1H +#define OCR1AH7_REG OCR1H + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* SP */ +#define SP0_REG SP +#define SP1_REG SP +#define SP2_REG SP +#define SP3_REG SP +#define SP4_REG SP +#define SP5_REG SP +#define SP6_REG SP +#define SP7_REG SP + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ADC0_PORT PORTC +#define ADC0_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + + diff --git a/include/aversive/parts/AT90S4434.h b/include/aversive/parts/AT90S4434.h new file mode 100644 index 0000000..bb6714b --- /dev/null +++ b/include/aversive/parts/AT90S4434.h @@ -0,0 +1,662 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE2_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM2_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define CTC2_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define PWM2_REG TCCR2 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* USR */ +#define OR_REG USR +#define FE_REG USR +#define UDRE_REG USR +#define TXC_REG USR +#define RXC_REG USR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* UCR */ +#define TXB8_REG UCR +#define RXB8_REG UCR +#define CHR9_REG UCR +#define TXEN_REG UCR +#define RXEN_REG UCR +#define UDRIE_REG UCR +#define TXCIE_REG UCR +#define RXCIE_REG UCR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ADCL */ +#define ADC0_REG ADCL +#define ADC1_REG ADCL +#define ADC2_REG ADCL +#define ADC3_REG ADCL +#define ADC4_REG ADCL +#define ADC5_REG ADCL +#define ADC6_REG ADCL +#define ADC7_REG ADCL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADC8_REG ADCH +#define ADC9_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + + + + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/AT90S8515.h b/include/aversive/parts/AT90S8515.h new file mode 100644 index 0000000..15e77c7 --- /dev/null +++ b/include/aversive/parts/AT90S8515.h @@ -0,0 +1,569 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ + + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 2 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM_TOTAL_NUM 2 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* USR */ +#define OR_REG USR +#define FE_REG USR +#define UDRE_REG USR +#define TXC_REG USR +#define RXC_REG USR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK +#define TOIE0_REG TIMSK + +/* UCR */ +#define TXB8_REG UCR +#define RXB8_REG UCR +#define CHR9_REG UCR +#define TXEN_REG UCR +#define RXEN_REG UCR +#define UDRIE_REG UCR +#define TXCIE_REG UCR +#define RXCIE_REG UCR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* TIFR */ +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR +#define TOV0_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR +#define SRW_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + + diff --git a/include/aversive/parts/AT90S8515comp.h b/include/aversive/parts/AT90S8515comp.h new file mode 100644 index 0000000..3335db2 --- /dev/null +++ b/include/aversive/parts/AT90S8515comp.h @@ -0,0 +1,708 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +/* #define URSEL_REG UCSRC */ /* dup in UBRRH */ + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define OCIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PUD_REG SFIOR +#define XMM0_REG SFIOR +#define XMM1_REG SFIOR +#define XMM2_REG SFIOR +#define XMBK_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* EMCUCR */ +#define ISC2_REG EMCUCR +#define SRW11_REG EMCUCR +#define SRW00_REG EMCUCR +#define SRW01_REG EMCUCR +#define SRL0_REG EMCUCR +#define SRL1_REG EMCUCR +#define SRL2_REG EMCUCR +#define SM0_REG EMCUCR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH +/* #define URSEL_REG UBRRH */ /* dup in UCSRC */ + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define SM2_REG MCUCSR + +/* TIFR */ +#define OCF0_REG TIFR +#define TOV0_REG TIFR +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define OC0_PORT PORTB +#define OC0_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + +#define ICP_PORT PORTE +#define ICP_BIT 0 +#define INT2_PORT PORTE +#define INT2_BIT 0 + +#define ALE_PORT PORTE +#define ALE_BIT 1 + +#define OC1B_PORT PORTE +#define OC1B_BIT 2 + + diff --git a/include/aversive/parts/AT90S8535.h b/include/aversive/parts/AT90S8535.h new file mode 100644 index 0000000..bb6714b --- /dev/null +++ b/include/aversive/parts/AT90S8535.h @@ -0,0 +1,662 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE2_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM2_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define CTC2_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define PWM2_REG TCCR2 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* USR */ +#define OR_REG USR +#define FE_REG USR +#define UDRE_REG USR +#define TXC_REG USR +#define RXC_REG USR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* UCR */ +#define TXB8_REG UCR +#define RXB8_REG UCR +#define CHR9_REG UCR +#define TXEN_REG UCR +#define RXEN_REG UCR +#define UDRIE_REG UCR +#define TXCIE_REG UCR +#define RXCIE_REG UCR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ADCL */ +#define ADC0_REG ADCL +#define ADC1_REG ADCL +#define ADC2_REG ADCL +#define ADC3_REG ADCL +#define ADC4_REG ADCL +#define ADC5_REG ADCL +#define ADC6_REG ADCL +#define ADC7_REG ADCL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADC8_REG ADCH +#define ADC9_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + + + + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/AT90S8535comp.h b/include/aversive/parts/AT90S8535comp.h new file mode 100644 index 0000000..23cae03 --- /dev/null +++ b/include/aversive/parts/AT90S8535comp.h @@ -0,0 +1,815 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ADTS0_REG SFIOR +#define ADTS1_REG SFIOR +#define ADTS2_REG SFIOR +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define ACME_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +/* #define URSEL_REG UCSRC */ /* dup in UBRRH */ + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH +/* #define URSEL_REG UBRRH */ /* dup in UCSRC */ + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define ISC2_REG MCUCSR +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SM2_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0_PORT PORTB +#define OC0_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/AT90USB1286.h b/include/aversive/parts/AT90USB1286.h new file mode 100644 index 0000000..cbccdad --- /dev/null +++ b/include/aversive/parts/AT90USB1286.h @@ -0,0 +1,1381 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM_TOTAL_NUM 10 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* UEBCHX */ +#define UEBCHX_0_REG UEBCHX +#define UEBCHX_1_REG UEBCHX +#define UEBCHX_2_REG UEBCHX + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* UECFG1X */ +#define ALLOC_REG UECFG1X +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define UEDATX_0_REG UEDATX +#define UEDATX_1_REG UEDATX +#define UEDATX_2_REG UEDATX +#define UEDATX_3_REG UEDATX +#define UEDATX_4_REG UEDATX +#define UEDATX_5_REG UEDATX +#define UEDATX_6_REG UEDATX +#define UEDATX_7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT +#define IDTI_REG USBINT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* UHWCON */ +#define UVREGE_REG UHWCON +#define UVCONE_REG UHWCON +#define UIDE_REG UHWCON +#define UIMOD_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* UEBCLX */ +#define UEBCLX_0_REG UEBCLX +#define UEBCLX_1_REG UEBCLX +#define UEBCLX_2_REG UEBCLX +#define UEBCLX_3_REG UEBCLX +#define UEBCLX_4_REG UEBCLX +#define UEBCLX_5_REG UEBCLX +#define UEBCLX_6_REG UEBCLX +#define UEBCLX_7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +#define RWAL_REG UEINTX +#define NAKINI_REG UEINTX +#define FIFOCON_REG UEINTX + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USBCON */ +#define VBUSTE_REG USBCON +#define IDTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define HOST_REG USBCON +#define USBE_REG USBCON + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UECONX */ +#define EPEN_REG UECONX +#define RSTDT_REG UECONX +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USBSTA */ +#define VBUS_REG USBSTA +#define ID_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +#define FLERRE_REG UEIENX + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define UDFNUML_0_REG UDFNUML +#define UDFNUML_1_REG UDFNUML +#define UDFNUML_2_REG UDFNUML +#define UDFNUML_3_REG UDFNUML +#define UDFNUML_4_REG UDFNUML +#define UDFNUML_5_REG UDFNUML +#define UDFNUML_6_REG UDFNUML +#define UDFNUML_7_REG UDFNUML + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* UDFNUMH */ +#define UDFNUMH_0_REG UDFNUMH +#define UDFNUMH_1_REG UDFNUMH +#define UDFNUMH_2_REG UDFNUMH + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +#define DTSEQ0_REG UESTA0X +#define DTSEQ1_REG UESTA0X +#define UNDERFI_REG UESTA0X +#define OVERFI_REG UESTA0X +#define CFGOK_REG UESTA0X + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/AT90USB1287.h b/include/aversive/parts/AT90USB1287.h new file mode 100644 index 0000000..21be664 --- /dev/null +++ b/include/aversive/parts/AT90USB1287.h @@ -0,0 +1,1599 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM_TOTAL_NUM 10 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* UEBCHX */ +#define UEBCHX_0_REG UEBCHX +#define UEBCHX_1_REG UEBCHX +#define UEBCHX_2_REG UEBCHX + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UPIENX */ +#define RXINE_REG UPIENX +#define RXSTALLE_REG UPIENX +#define TXOUTE_REG UPIENX +#define TXSTPE_REG UPIENX +#define PERRE_REG UPIENX +#define NAKEDE_REG UPIENX +/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */ + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* UECFG1X */ +/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */ +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* UECONX */ +#define EPEN_REG UECONX +/* #define RSTDT_REG UECONX */ /* dup in UPCONX */ +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OTGIEN */ +#define SRPE_REG OTGIEN +#define VBERRE_REG OTGIEN +#define BCERRE_REG OTGIEN +#define ROLEEXE_REG OTGIEN +#define HNPERRE_REG OTGIEN +#define STOE_REG OTGIEN + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* OTGTCON */ +#define VALUE_20_REG OTGTCON +#define VALUE_21_REG OTGTCON +#define VALUE_22_REG OTGTCON +#define PAGE0_REG OTGTCON +#define PAGE1_REG OTGTCON +#define OTGTCON_7_REG OTGTCON + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UPBCHX */ +#define PBYCT8_REG UPBCHX +#define PBYCT9_REG UPBCHX +#define PBYCT10_REG UPBCHX + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define UEDATX_0_REG UEDATX +#define UEDATX_1_REG UEDATX +#define UEDATX_2_REG UEDATX +#define UEDATX_3_REG UEDATX +#define UEDATX_4_REG UEDATX +#define UEDATX_5_REG UEDATX +#define UEDATX_6_REG UEDATX +#define UEDATX_7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* OTGINT */ +#define SRPI_REG OTGINT +#define VBERRI_REG OTGINT +#define BCERRI_REG OTGINT +#define ROLEEXI_REG OTGINT +#define HNPERRI_REG OTGINT +#define STOI_REG OTGINT + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* UHIEN */ +#define DCONNE_REG UHIEN +#define DDISCE_REG UHIEN +#define RSTE_REG UHIEN +#define RSMEDE_REG UHIEN +#define RXRSME_REG UHIEN +#define HSOFE_REG UHIEN +#define HWUPE_REG UHIEN + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* UHADDR */ +#define UHADDR_0_REG UHADDR +#define UHADDR_1_REG UHADDR +#define UHADDR_2_REG UHADDR +#define UHADDR_3_REG UHADDR +#define UHADDR_4_REG UHADDR +#define UHADDR_5_REG UHADDR +#define UHADDR_6_REG UHADDR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON + +/* UHFLEN */ +#define UHFLEN_0_REG UHFLEN +#define UHFLEN_1_REG UHFLEN +#define UHFLEN_2_REG UHFLEN +#define UHFLEN_3_REG UHFLEN +#define UHFLEN_4_REG UHFLEN +#define UHFLEN_5_REG UHFLEN +#define UHFLEN_6_REG UHFLEN +#define UHFLEN_7_REG UHFLEN + +/* UHFNUMH */ +#define UHFNUMH_0_REG UHFNUMH +#define UHFNUMH_1_REG UHFNUMH +#define UHFNUMH_2_REG UHFNUMH + +/* UHFNUML */ +#define UHFNUML_0_REG UHFNUML +#define UHFNUML_1_REG UHFNUML +#define UHFNUML_2_REG UHFNUML +#define UHFNUML_3_REG UHFNUML +#define UHFNUML_4_REG UHFNUML +#define UHFNUML_5_REG UHFNUML +#define UHFNUML_6_REG UHFNUML +#define UHFNUML_7_REG UHFNUML + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT +#define IDTI_REG USBINT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* UHWCON */ +#define UVREGE_REG UHWCON +#define UVCONE_REG UHWCON +#define UIDE_REG UHWCON +#define UIMOD_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UPDATX */ +#define PDAT0_REG UPDATX +#define PDAT1_REG UPDATX +#define PDAT2_REG UPDATX +#define PDAT3_REG UPDATX +#define PDAT4_REG UPDATX +#define PDAT5_REG UPDATX +#define PDAT6_REG UPDATX +#define PDAT7_REG UPDATX + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* UHCON */ +#define SOFEN_REG UHCON +#define RESET_REG UHCON +#define RESUME_REG UHCON + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* UPINT */ +#define PINT0_REG UPINT +#define PINT1_REG UPINT +#define PINT2_REG UPINT +#define PINT3_REG UPINT +#define PINT4_REG UPINT +#define PINT5_REG UPINT +#define PINT6_REG UPINT + +/* UEBCLX */ +#define UEBCLX_0_REG UEBCLX +#define UEBCLX_1_REG UEBCLX +#define UEBCLX_2_REG UEBCLX +#define UEBCLX_3_REG UEBCLX +#define UEBCLX_4_REG UEBCLX +#define UEBCLX_5_REG UEBCLX +#define UEBCLX_6_REG UEBCLX +#define UEBCLX_7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* UPSTAX */ +#define NBUSYK0_REG UPSTAX +#define NBUSYK1_REG UPSTAX +/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */ +/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */ +/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */ +/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */ +/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +/* #define RWAL_REG UEINTX */ /* dup in UPINTX */ +#define NAKINI_REG UEINTX +/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */ + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* UPCFG0X */ +#define PEPNUM0_REG UPCFG0X +#define PEPNUM1_REG UPCFG0X +#define PEPNUM2_REG UPCFG0X +#define PEPNUM3_REG UPCFG0X +#define PTOKEN0_REG UPCFG0X +#define PTOKEN1_REG UPCFG0X +#define PTYPE0_REG UPCFG0X +#define PTYPE1_REG UPCFG0X + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* UPERRX */ +#define DATATGL_REG UPERRX +#define DATAPID_REG UPERRX +#define PID_REG UPERRX +#define TIMEOUT_REG UPERRX +#define CRC16_REG UPERRX +#define COUNTER0_REG UPERRX +#define COUNTER1_REG UPERRX + +/* USBCON */ +#define VBUSTE_REG USBCON +#define IDTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define HOST_REG USBCON +#define USBE_REG USBCON + +/* UPCONX */ +#define PEN_REG UPCONX +/* #define RSTDT_REG UPCONX */ /* dup in UECONX */ +#define INMODE_REG UPCONX +#define PFREEZE_REG UPCONX + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* UPBCLX */ +#define PBYCT0_REG UPBCLX +#define PBYCT1_REG UPBCLX +#define PBYCT2_REG UPBCLX +#define PBYCT3_REG UPBCLX +#define PBYCT4_REG UPBCLX +#define PBYCT5_REG UPBCLX +#define PBYCT6_REG UPBCLX +#define PBYCT7_REG UPBCLX + +/* UHINT */ +#define DCONNI_REG UHINT +#define DDISCI_REG UHINT +#define RSTI_REG UHINT +#define RSMEDI_REG UHINT +#define RXRSMI_REG UHINT +#define HSOFI_REG UHINT +#define UHUPI_REG UHINT + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UPNUM */ +#define PNUM0_REG UPNUM +#define PNUM1_REG UPNUM +#define PNUM2_REG UPNUM + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* UPCFG1X */ +/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */ +#define PBK0_REG UPCFG1X +#define PBK1_REG UPCFG1X +#define PSIZE0_REG UPCFG1X +#define PSIZE1_REG UPCFG1X +#define PSIZE2_REG UPCFG1X + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USBSTA */ +#define VBUS_REG USBSTA +#define ID_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */ + +/* OTGCON */ +#define VBUSRQC_REG OTGCON +#define VBUSREQ_REG OTGCON +#define VBUSHWC_REG OTGCON +#define SRPSEL_REG OTGCON +#define SRPREQ_REG OTGCON +#define HNPREQ_REG OTGCON + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* UPINRQX */ +#define INRQ0_REG UPINRQX +#define INRQ1_REG UPINRQX +#define INRQ2_REG UPINRQX +#define INRQ3_REG UPINRQX +#define INRQ4_REG UPINRQX +#define INRQ5_REG UPINRQX +#define INRQ6_REG UPINRQX +#define INRQ7_REG UPINRQX + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define UDFNUML_0_REG UDFNUML +#define UDFNUML_1_REG UDFNUML +#define UDFNUML_2_REG UDFNUML +#define UDFNUML_3_REG UDFNUML +#define UDFNUML_4_REG UDFNUML +#define UDFNUML_5_REG UDFNUML +#define UDFNUML_6_REG UDFNUML +#define UDFNUML_7_REG UDFNUML + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* UDFNUMH */ +#define UDFNUMH_0_REG UDFNUMH +#define UDFNUMH_1_REG UDFNUMH +#define UDFNUMH_2_REG UDFNUMH + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* UPINTX */ +#define RXINI_REG UPINTX +#define RXSTALLI_REG UPINTX +#define TXOUTI_REG UPINTX +#define TXSTPI_REG UPINTX +#define PERRI_REG UPINTX +/* #define RWAL_REG UPINTX */ /* dup in UEINTX */ +#define NAKEDI_REG UPINTX +/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */ + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* UPCFG2X */ +#define UPCFG2X_0_REG UPCFG2X +#define UPCFG2X_1_REG UPCFG2X +#define UPCFG2X_2_REG UPCFG2X +#define UPCFG2X_3_REG UPCFG2X +#define UPCFG2X_4_REG UPCFG2X +#define UPCFG2X_5_REG UPCFG2X +#define UPCFG2X_6_REG UPCFG2X +#define UPCFG2X_7_REG UPCFG2X + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */ +/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */ +/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */ +/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */ +/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */ + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* UPRST */ +#define PRST0_REG UPRST +#define PRST1_REG UPRST +#define PRST2_REG UPRST +#define PRST3_REG UPRST +#define PRST4_REG UPRST +#define PRST5_REG UPRST +#define PRST6_REG UPRST + +/* pins mapping */ + diff --git a/include/aversive/parts/AT90USB162.h b/include/aversive/parts/AT90USB162.h new file mode 100644 index 0000000..9eb8f03 --- /dev/null +++ b/include/aversive/parts/AT90USB162.h @@ -0,0 +1,918 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM_TOTAL_NUM 5 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PS2CON */ +#define PS2EN_REG PS2CON + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST + +/* UECFG1X */ +#define ALLOC_REG UECFG1X +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* REGCR */ +#define REGDIS_REG REGCR + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define DAT0_REG UEDATX +#define DAT1_REG UEDATX +#define DAT2_REG UEDATX +#define DAT3_REG UEDATX +#define DAT4_REG UEDATX +#define DAT5_REG UEDATX +#define DAT6_REG UEDATX +#define DAT7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* CLKSEL1 */ +#define EXCKSEL0_REG CLKSEL1 +#define EXCKSEL1_REG CLKSEL1 +#define EXCKSEL2_REG CLKSEL1 +#define EXCKSEL3_REG CLKSEL1 +#define RCCKSEL0_REG CLKSEL1 +#define RCCKSEL1_REG CLKSEL1 +#define RCCKSEL2_REG CLKSEL1 +#define RCCKSEL3_REG CLKSEL1 + +/* CLKSEL0 */ +#define CLKS_REG CLKSEL0 +#define EXTE_REG CLKSEL0 +#define RCE_REG CLKSEL0 +#define EXSUT0_REG CLKSEL0 +#define EXSUT1_REG CLKSEL0 +#define RCSUT0_REG CLKSEL0 +#define RCSUT1_REG CLKSEL0 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* UPOE */ +#define DMI_REG UPOE +#define DPI_REG UPOE +#define DATAI_REG UPOE +#define SCKI_REG UPOE +#define UPDRV0_REG UPOE +#define UPDRV1_REG UPOE +#define UPWE0_REG UPOE +#define UPWE1_REG UPOE + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define EPNUM0_REG UENUM +#define EPNUM1_REG UENUM +#define EPNUM2_REG UENUM + +/* UBRR1L */ +#define UBRR1_0_REG UBRR1L +#define UBRR1_1_REG UBRR1L +#define UBRR1_2_REG UBRR1L +#define UBRR1_3_REG UBRR1L +#define UBRR1_4_REG UBRR1L +#define UBRR1_5_REG UBRR1L +#define UBRR1_6_REG UBRR1L +#define UBRR1_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define RSTCPU_REG UDCON + +/* WDTCKD */ +#define WCLKD0_REG WDTCKD +#define WCLKD1_REG WDTCKD +#define WDEWIE_REG WDTCKD +#define WDEWIF_REG WDTCKD + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* UEBCLX */ +#define BYCT0_REG UEBCLX +#define BYCT1_REG UEBCLX +#define BYCT2_REG UEBCLX +#define BYCT3_REG UEBCLX +#define BYCT4_REG UEBCLX +#define BYCT5_REG UEBCLX +#define BYCT6_REG UEBCLX +#define BYCT7_REG UEBCLX + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +#define RWAL_REG UEINTX +#define NAKINI_REG UEINTX +#define FIFOCON_REG UEINTX + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USBCON */ +#define FRZCLK_REG USBCON +#define USBE_REG USBCON + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define USBRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR + +/* UECONX */ +#define EPEN_REG UECONX +#define RSTDT_REG UECONX +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +#define FLERRE_REG UEIENX + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* UCSR1D */ +#define RTSEN_REG UCSR1D +#define CTSEN_REG UCSR1D + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define FNUM0_REG UDFNUML +#define FNUM1_REG UDFNUML +#define FNUM2_REG UDFNUML +#define FNUM3_REG UDFNUML +#define FNUM4_REG UDFNUML +#define FNUM5_REG UDFNUML +#define FNUM6_REG UDFNUML +#define FNUM7_REG UDFNUML + +/* UDFNUMH */ +#define FNUM8_REG UDFNUMH +#define FNUM9_REG UDFNUMH +#define FNUM10_REG UDFNUMH + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* PRR0 */ +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 + +/* UBRR1H */ +#define UBRR1_8_REG UBRR1H +#define UBRR1_9_REG UBRR1H +#define UBRR1_10_REG UBRR1H +#define UBRR1_11_REG UBRR1H + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +#define DTSEQ0_REG UESTA0X +#define DTSEQ1_REG UESTA0X +#define UNDERFI_REG UESTA0X +#define OVERFI_REG UESTA0X +#define CFGOK_REG UESTA0X + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* CLKSTA */ +#define EXTON_REG CLKSTA +#define RCON_REG CLKSTA + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSB_REG PRR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/AT90USB646.h b/include/aversive/parts/AT90USB646.h new file mode 100644 index 0000000..21be664 --- /dev/null +++ b/include/aversive/parts/AT90USB646.h @@ -0,0 +1,1599 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM_TOTAL_NUM 10 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* UEBCHX */ +#define UEBCHX_0_REG UEBCHX +#define UEBCHX_1_REG UEBCHX +#define UEBCHX_2_REG UEBCHX + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UPIENX */ +#define RXINE_REG UPIENX +#define RXSTALLE_REG UPIENX +#define TXOUTE_REG UPIENX +#define TXSTPE_REG UPIENX +#define PERRE_REG UPIENX +#define NAKEDE_REG UPIENX +/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */ + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* UECFG1X */ +/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */ +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* UECONX */ +#define EPEN_REG UECONX +/* #define RSTDT_REG UECONX */ /* dup in UPCONX */ +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OTGIEN */ +#define SRPE_REG OTGIEN +#define VBERRE_REG OTGIEN +#define BCERRE_REG OTGIEN +#define ROLEEXE_REG OTGIEN +#define HNPERRE_REG OTGIEN +#define STOE_REG OTGIEN + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* OTGTCON */ +#define VALUE_20_REG OTGTCON +#define VALUE_21_REG OTGTCON +#define VALUE_22_REG OTGTCON +#define PAGE0_REG OTGTCON +#define PAGE1_REG OTGTCON +#define OTGTCON_7_REG OTGTCON + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UPBCHX */ +#define PBYCT8_REG UPBCHX +#define PBYCT9_REG UPBCHX +#define PBYCT10_REG UPBCHX + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define UEDATX_0_REG UEDATX +#define UEDATX_1_REG UEDATX +#define UEDATX_2_REG UEDATX +#define UEDATX_3_REG UEDATX +#define UEDATX_4_REG UEDATX +#define UEDATX_5_REG UEDATX +#define UEDATX_6_REG UEDATX +#define UEDATX_7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* OTGINT */ +#define SRPI_REG OTGINT +#define VBERRI_REG OTGINT +#define BCERRI_REG OTGINT +#define ROLEEXI_REG OTGINT +#define HNPERRI_REG OTGINT +#define STOI_REG OTGINT + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* UHIEN */ +#define DCONNE_REG UHIEN +#define DDISCE_REG UHIEN +#define RSTE_REG UHIEN +#define RSMEDE_REG UHIEN +#define RXRSME_REG UHIEN +#define HSOFE_REG UHIEN +#define HWUPE_REG UHIEN + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* UHADDR */ +#define UHADDR_0_REG UHADDR +#define UHADDR_1_REG UHADDR +#define UHADDR_2_REG UHADDR +#define UHADDR_3_REG UHADDR +#define UHADDR_4_REG UHADDR +#define UHADDR_5_REG UHADDR +#define UHADDR_6_REG UHADDR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON + +/* UHFLEN */ +#define UHFLEN_0_REG UHFLEN +#define UHFLEN_1_REG UHFLEN +#define UHFLEN_2_REG UHFLEN +#define UHFLEN_3_REG UHFLEN +#define UHFLEN_4_REG UHFLEN +#define UHFLEN_5_REG UHFLEN +#define UHFLEN_6_REG UHFLEN +#define UHFLEN_7_REG UHFLEN + +/* UHFNUMH */ +#define UHFNUMH_0_REG UHFNUMH +#define UHFNUMH_1_REG UHFNUMH +#define UHFNUMH_2_REG UHFNUMH + +/* UHFNUML */ +#define UHFNUML_0_REG UHFNUML +#define UHFNUML_1_REG UHFNUML +#define UHFNUML_2_REG UHFNUML +#define UHFNUML_3_REG UHFNUML +#define UHFNUML_4_REG UHFNUML +#define UHFNUML_5_REG UHFNUML +#define UHFNUML_6_REG UHFNUML +#define UHFNUML_7_REG UHFNUML + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT +#define IDTI_REG USBINT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* UHWCON */ +#define UVREGE_REG UHWCON +#define UVCONE_REG UHWCON +#define UIDE_REG UHWCON +#define UIMOD_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UPDATX */ +#define PDAT0_REG UPDATX +#define PDAT1_REG UPDATX +#define PDAT2_REG UPDATX +#define PDAT3_REG UPDATX +#define PDAT4_REG UPDATX +#define PDAT5_REG UPDATX +#define PDAT6_REG UPDATX +#define PDAT7_REG UPDATX + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* UHCON */ +#define SOFEN_REG UHCON +#define RESET_REG UHCON +#define RESUME_REG UHCON + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* UPINT */ +#define PINT0_REG UPINT +#define PINT1_REG UPINT +#define PINT2_REG UPINT +#define PINT3_REG UPINT +#define PINT4_REG UPINT +#define PINT5_REG UPINT +#define PINT6_REG UPINT + +/* UEBCLX */ +#define UEBCLX_0_REG UEBCLX +#define UEBCLX_1_REG UEBCLX +#define UEBCLX_2_REG UEBCLX +#define UEBCLX_3_REG UEBCLX +#define UEBCLX_4_REG UEBCLX +#define UEBCLX_5_REG UEBCLX +#define UEBCLX_6_REG UEBCLX +#define UEBCLX_7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* UPSTAX */ +#define NBUSYK0_REG UPSTAX +#define NBUSYK1_REG UPSTAX +/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */ +/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */ +/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */ +/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */ +/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +/* #define RWAL_REG UEINTX */ /* dup in UPINTX */ +#define NAKINI_REG UEINTX +/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */ + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* UPCFG0X */ +#define PEPNUM0_REG UPCFG0X +#define PEPNUM1_REG UPCFG0X +#define PEPNUM2_REG UPCFG0X +#define PEPNUM3_REG UPCFG0X +#define PTOKEN0_REG UPCFG0X +#define PTOKEN1_REG UPCFG0X +#define PTYPE0_REG UPCFG0X +#define PTYPE1_REG UPCFG0X + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* UPERRX */ +#define DATATGL_REG UPERRX +#define DATAPID_REG UPERRX +#define PID_REG UPERRX +#define TIMEOUT_REG UPERRX +#define CRC16_REG UPERRX +#define COUNTER0_REG UPERRX +#define COUNTER1_REG UPERRX + +/* USBCON */ +#define VBUSTE_REG USBCON +#define IDTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define HOST_REG USBCON +#define USBE_REG USBCON + +/* UPCONX */ +#define PEN_REG UPCONX +/* #define RSTDT_REG UPCONX */ /* dup in UECONX */ +#define INMODE_REG UPCONX +#define PFREEZE_REG UPCONX + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* UPBCLX */ +#define PBYCT0_REG UPBCLX +#define PBYCT1_REG UPBCLX +#define PBYCT2_REG UPBCLX +#define PBYCT3_REG UPBCLX +#define PBYCT4_REG UPBCLX +#define PBYCT5_REG UPBCLX +#define PBYCT6_REG UPBCLX +#define PBYCT7_REG UPBCLX + +/* UHINT */ +#define DCONNI_REG UHINT +#define DDISCI_REG UHINT +#define RSTI_REG UHINT +#define RSMEDI_REG UHINT +#define RXRSMI_REG UHINT +#define HSOFI_REG UHINT +#define UHUPI_REG UHINT + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UPNUM */ +#define PNUM0_REG UPNUM +#define PNUM1_REG UPNUM +#define PNUM2_REG UPNUM + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* UPCFG1X */ +/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */ +#define PBK0_REG UPCFG1X +#define PBK1_REG UPCFG1X +#define PSIZE0_REG UPCFG1X +#define PSIZE1_REG UPCFG1X +#define PSIZE2_REG UPCFG1X + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USBSTA */ +#define VBUS_REG USBSTA +#define ID_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */ + +/* OTGCON */ +#define VBUSRQC_REG OTGCON +#define VBUSREQ_REG OTGCON +#define VBUSHWC_REG OTGCON +#define SRPSEL_REG OTGCON +#define SRPREQ_REG OTGCON +#define HNPREQ_REG OTGCON + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* UPINRQX */ +#define INRQ0_REG UPINRQX +#define INRQ1_REG UPINRQX +#define INRQ2_REG UPINRQX +#define INRQ3_REG UPINRQX +#define INRQ4_REG UPINRQX +#define INRQ5_REG UPINRQX +#define INRQ6_REG UPINRQX +#define INRQ7_REG UPINRQX + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define UDFNUML_0_REG UDFNUML +#define UDFNUML_1_REG UDFNUML +#define UDFNUML_2_REG UDFNUML +#define UDFNUML_3_REG UDFNUML +#define UDFNUML_4_REG UDFNUML +#define UDFNUML_5_REG UDFNUML +#define UDFNUML_6_REG UDFNUML +#define UDFNUML_7_REG UDFNUML + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* UDFNUMH */ +#define UDFNUMH_0_REG UDFNUMH +#define UDFNUMH_1_REG UDFNUMH +#define UDFNUMH_2_REG UDFNUMH + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* UPINTX */ +#define RXINI_REG UPINTX +#define RXSTALLI_REG UPINTX +#define TXOUTI_REG UPINTX +#define TXSTPI_REG UPINTX +#define PERRI_REG UPINTX +/* #define RWAL_REG UPINTX */ /* dup in UEINTX */ +#define NAKEDI_REG UPINTX +/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */ + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* UPCFG2X */ +#define UPCFG2X_0_REG UPCFG2X +#define UPCFG2X_1_REG UPCFG2X +#define UPCFG2X_2_REG UPCFG2X +#define UPCFG2X_3_REG UPCFG2X +#define UPCFG2X_4_REG UPCFG2X +#define UPCFG2X_5_REG UPCFG2X +#define UPCFG2X_6_REG UPCFG2X +#define UPCFG2X_7_REG UPCFG2X + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */ +/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */ +/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */ +/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */ +/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */ + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* UPRST */ +#define PRST0_REG UPRST +#define PRST1_REG UPRST +#define PRST2_REG UPRST +#define PRST3_REG UPRST +#define PRST4_REG UPRST +#define PRST5_REG UPRST +#define PRST6_REG UPRST + +/* pins mapping */ + diff --git a/include/aversive/parts/AT90USB647.h b/include/aversive/parts/AT90USB647.h new file mode 100644 index 0000000..21be664 --- /dev/null +++ b/include/aversive/parts/AT90USB647.h @@ -0,0 +1,1599 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM_TOTAL_NUM 10 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* UEBCHX */ +#define UEBCHX_0_REG UEBCHX +#define UEBCHX_1_REG UEBCHX +#define UEBCHX_2_REG UEBCHX + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UPIENX */ +#define RXINE_REG UPIENX +#define RXSTALLE_REG UPIENX +#define TXOUTE_REG UPIENX +#define TXSTPE_REG UPIENX +#define PERRE_REG UPIENX +#define NAKEDE_REG UPIENX +/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */ + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* UECFG1X */ +/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */ +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* UECONX */ +#define EPEN_REG UECONX +/* #define RSTDT_REG UECONX */ /* dup in UPCONX */ +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OTGIEN */ +#define SRPE_REG OTGIEN +#define VBERRE_REG OTGIEN +#define BCERRE_REG OTGIEN +#define ROLEEXE_REG OTGIEN +#define HNPERRE_REG OTGIEN +#define STOE_REG OTGIEN + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* OTGTCON */ +#define VALUE_20_REG OTGTCON +#define VALUE_21_REG OTGTCON +#define VALUE_22_REG OTGTCON +#define PAGE0_REG OTGTCON +#define PAGE1_REG OTGTCON +#define OTGTCON_7_REG OTGTCON + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UPBCHX */ +#define PBYCT8_REG UPBCHX +#define PBYCT9_REG UPBCHX +#define PBYCT10_REG UPBCHX + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define UEDATX_0_REG UEDATX +#define UEDATX_1_REG UEDATX +#define UEDATX_2_REG UEDATX +#define UEDATX_3_REG UEDATX +#define UEDATX_4_REG UEDATX +#define UEDATX_5_REG UEDATX +#define UEDATX_6_REG UEDATX +#define UEDATX_7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* OTGINT */ +#define SRPI_REG OTGINT +#define VBERRI_REG OTGINT +#define BCERRI_REG OTGINT +#define ROLEEXI_REG OTGINT +#define HNPERRI_REG OTGINT +#define STOI_REG OTGINT + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* UHIEN */ +#define DCONNE_REG UHIEN +#define DDISCE_REG UHIEN +#define RSTE_REG UHIEN +#define RSMEDE_REG UHIEN +#define RXRSME_REG UHIEN +#define HSOFE_REG UHIEN +#define HWUPE_REG UHIEN + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* UHADDR */ +#define UHADDR_0_REG UHADDR +#define UHADDR_1_REG UHADDR +#define UHADDR_2_REG UHADDR +#define UHADDR_3_REG UHADDR +#define UHADDR_4_REG UHADDR +#define UHADDR_5_REG UHADDR +#define UHADDR_6_REG UHADDR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON + +/* UHFLEN */ +#define UHFLEN_0_REG UHFLEN +#define UHFLEN_1_REG UHFLEN +#define UHFLEN_2_REG UHFLEN +#define UHFLEN_3_REG UHFLEN +#define UHFLEN_4_REG UHFLEN +#define UHFLEN_5_REG UHFLEN +#define UHFLEN_6_REG UHFLEN +#define UHFLEN_7_REG UHFLEN + +/* UHFNUMH */ +#define UHFNUMH_0_REG UHFNUMH +#define UHFNUMH_1_REG UHFNUMH +#define UHFNUMH_2_REG UHFNUMH + +/* UHFNUML */ +#define UHFNUML_0_REG UHFNUML +#define UHFNUML_1_REG UHFNUML +#define UHFNUML_2_REG UHFNUML +#define UHFNUML_3_REG UHFNUML +#define UHFNUML_4_REG UHFNUML +#define UHFNUML_5_REG UHFNUML +#define UHFNUML_6_REG UHFNUML +#define UHFNUML_7_REG UHFNUML + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT +#define IDTI_REG USBINT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* UHWCON */ +#define UVREGE_REG UHWCON +#define UVCONE_REG UHWCON +#define UIDE_REG UHWCON +#define UIMOD_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UPDATX */ +#define PDAT0_REG UPDATX +#define PDAT1_REG UPDATX +#define PDAT2_REG UPDATX +#define PDAT3_REG UPDATX +#define PDAT4_REG UPDATX +#define PDAT5_REG UPDATX +#define PDAT6_REG UPDATX +#define PDAT7_REG UPDATX + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* UHCON */ +#define SOFEN_REG UHCON +#define RESET_REG UHCON +#define RESUME_REG UHCON + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* UPINT */ +#define PINT0_REG UPINT +#define PINT1_REG UPINT +#define PINT2_REG UPINT +#define PINT3_REG UPINT +#define PINT4_REG UPINT +#define PINT5_REG UPINT +#define PINT6_REG UPINT + +/* UEBCLX */ +#define UEBCLX_0_REG UEBCLX +#define UEBCLX_1_REG UEBCLX +#define UEBCLX_2_REG UEBCLX +#define UEBCLX_3_REG UEBCLX +#define UEBCLX_4_REG UEBCLX +#define UEBCLX_5_REG UEBCLX +#define UEBCLX_6_REG UEBCLX +#define UEBCLX_7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* UPSTAX */ +#define NBUSYK0_REG UPSTAX +#define NBUSYK1_REG UPSTAX +/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */ +/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */ +/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */ +/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */ +/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +/* #define RWAL_REG UEINTX */ /* dup in UPINTX */ +#define NAKINI_REG UEINTX +/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */ + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* UPCFG0X */ +#define PEPNUM0_REG UPCFG0X +#define PEPNUM1_REG UPCFG0X +#define PEPNUM2_REG UPCFG0X +#define PEPNUM3_REG UPCFG0X +#define PTOKEN0_REG UPCFG0X +#define PTOKEN1_REG UPCFG0X +#define PTYPE0_REG UPCFG0X +#define PTYPE1_REG UPCFG0X + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* UPERRX */ +#define DATATGL_REG UPERRX +#define DATAPID_REG UPERRX +#define PID_REG UPERRX +#define TIMEOUT_REG UPERRX +#define CRC16_REG UPERRX +#define COUNTER0_REG UPERRX +#define COUNTER1_REG UPERRX + +/* USBCON */ +#define VBUSTE_REG USBCON +#define IDTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define HOST_REG USBCON +#define USBE_REG USBCON + +/* UPCONX */ +#define PEN_REG UPCONX +/* #define RSTDT_REG UPCONX */ /* dup in UECONX */ +#define INMODE_REG UPCONX +#define PFREEZE_REG UPCONX + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* UPBCLX */ +#define PBYCT0_REG UPBCLX +#define PBYCT1_REG UPBCLX +#define PBYCT2_REG UPBCLX +#define PBYCT3_REG UPBCLX +#define PBYCT4_REG UPBCLX +#define PBYCT5_REG UPBCLX +#define PBYCT6_REG UPBCLX +#define PBYCT7_REG UPBCLX + +/* UHINT */ +#define DCONNI_REG UHINT +#define DDISCI_REG UHINT +#define RSTI_REG UHINT +#define RSMEDI_REG UHINT +#define RXRSMI_REG UHINT +#define HSOFI_REG UHINT +#define UHUPI_REG UHINT + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UPNUM */ +#define PNUM0_REG UPNUM +#define PNUM1_REG UPNUM +#define PNUM2_REG UPNUM + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* UPCFG1X */ +/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */ +#define PBK0_REG UPCFG1X +#define PBK1_REG UPCFG1X +#define PSIZE0_REG UPCFG1X +#define PSIZE1_REG UPCFG1X +#define PSIZE2_REG UPCFG1X + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USBSTA */ +#define VBUS_REG USBSTA +#define ID_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */ + +/* OTGCON */ +#define VBUSRQC_REG OTGCON +#define VBUSREQ_REG OTGCON +#define VBUSHWC_REG OTGCON +#define SRPSEL_REG OTGCON +#define SRPREQ_REG OTGCON +#define HNPREQ_REG OTGCON + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* UPINRQX */ +#define INRQ0_REG UPINRQX +#define INRQ1_REG UPINRQX +#define INRQ2_REG UPINRQX +#define INRQ3_REG UPINRQX +#define INRQ4_REG UPINRQX +#define INRQ5_REG UPINRQX +#define INRQ6_REG UPINRQX +#define INRQ7_REG UPINRQX + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define UDFNUML_0_REG UDFNUML +#define UDFNUML_1_REG UDFNUML +#define UDFNUML_2_REG UDFNUML +#define UDFNUML_3_REG UDFNUML +#define UDFNUML_4_REG UDFNUML +#define UDFNUML_5_REG UDFNUML +#define UDFNUML_6_REG UDFNUML +#define UDFNUML_7_REG UDFNUML + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* UDFNUMH */ +#define UDFNUMH_0_REG UDFNUMH +#define UDFNUMH_1_REG UDFNUMH +#define UDFNUMH_2_REG UDFNUMH + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* UPINTX */ +#define RXINI_REG UPINTX +#define RXSTALLI_REG UPINTX +#define TXOUTI_REG UPINTX +#define TXSTPI_REG UPINTX +#define PERRI_REG UPINTX +/* #define RWAL_REG UPINTX */ /* dup in UEINTX */ +#define NAKEDI_REG UPINTX +/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */ + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* UPCFG2X */ +#define UPCFG2X_0_REG UPCFG2X +#define UPCFG2X_1_REG UPCFG2X +#define UPCFG2X_2_REG UPCFG2X +#define UPCFG2X_3_REG UPCFG2X +#define UPCFG2X_4_REG UPCFG2X +#define UPCFG2X_5_REG UPCFG2X +#define UPCFG2X_6_REG UPCFG2X +#define UPCFG2X_7_REG UPCFG2X + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */ +/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */ +/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */ +/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */ +/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */ + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* UPRST */ +#define PRST0_REG UPRST +#define PRST1_REG UPRST +#define PRST2_REG UPRST +#define PRST3_REG UPRST +#define PRST4_REG UPRST +#define PRST5_REG UPRST +#define PRST6_REG UPRST + +/* pins mapping */ + diff --git a/include/aversive/parts/AT90USB82.h b/include/aversive/parts/AT90USB82.h new file mode 100644 index 0000000..9eb8f03 --- /dev/null +++ b/include/aversive/parts/AT90USB82.h @@ -0,0 +1,918 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM_TOTAL_NUM 5 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PS2CON */ +#define PS2EN_REG PS2CON + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST + +/* UECFG1X */ +#define ALLOC_REG UECFG1X +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* REGCR */ +#define REGDIS_REG REGCR + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define DAT0_REG UEDATX +#define DAT1_REG UEDATX +#define DAT2_REG UEDATX +#define DAT3_REG UEDATX +#define DAT4_REG UEDATX +#define DAT5_REG UEDATX +#define DAT6_REG UEDATX +#define DAT7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* CLKSEL1 */ +#define EXCKSEL0_REG CLKSEL1 +#define EXCKSEL1_REG CLKSEL1 +#define EXCKSEL2_REG CLKSEL1 +#define EXCKSEL3_REG CLKSEL1 +#define RCCKSEL0_REG CLKSEL1 +#define RCCKSEL1_REG CLKSEL1 +#define RCCKSEL2_REG CLKSEL1 +#define RCCKSEL3_REG CLKSEL1 + +/* CLKSEL0 */ +#define CLKS_REG CLKSEL0 +#define EXTE_REG CLKSEL0 +#define RCE_REG CLKSEL0 +#define EXSUT0_REG CLKSEL0 +#define EXSUT1_REG CLKSEL0 +#define RCSUT0_REG CLKSEL0 +#define RCSUT1_REG CLKSEL0 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* UPOE */ +#define DMI_REG UPOE +#define DPI_REG UPOE +#define DATAI_REG UPOE +#define SCKI_REG UPOE +#define UPDRV0_REG UPOE +#define UPDRV1_REG UPOE +#define UPWE0_REG UPOE +#define UPWE1_REG UPOE + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define EPNUM0_REG UENUM +#define EPNUM1_REG UENUM +#define EPNUM2_REG UENUM + +/* UBRR1L */ +#define UBRR1_0_REG UBRR1L +#define UBRR1_1_REG UBRR1L +#define UBRR1_2_REG UBRR1L +#define UBRR1_3_REG UBRR1L +#define UBRR1_4_REG UBRR1L +#define UBRR1_5_REG UBRR1L +#define UBRR1_6_REG UBRR1L +#define UBRR1_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define RSTCPU_REG UDCON + +/* WDTCKD */ +#define WCLKD0_REG WDTCKD +#define WCLKD1_REG WDTCKD +#define WDEWIE_REG WDTCKD +#define WDEWIF_REG WDTCKD + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* UEBCLX */ +#define BYCT0_REG UEBCLX +#define BYCT1_REG UEBCLX +#define BYCT2_REG UEBCLX +#define BYCT3_REG UEBCLX +#define BYCT4_REG UEBCLX +#define BYCT5_REG UEBCLX +#define BYCT6_REG UEBCLX +#define BYCT7_REG UEBCLX + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +#define RWAL_REG UEINTX +#define NAKINI_REG UEINTX +#define FIFOCON_REG UEINTX + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USBCON */ +#define FRZCLK_REG USBCON +#define USBE_REG USBCON + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define USBRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR + +/* UECONX */ +#define EPEN_REG UECONX +#define RSTDT_REG UECONX +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +#define FLERRE_REG UEIENX + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* UCSR1D */ +#define RTSEN_REG UCSR1D +#define CTSEN_REG UCSR1D + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define FNUM0_REG UDFNUML +#define FNUM1_REG UDFNUML +#define FNUM2_REG UDFNUML +#define FNUM3_REG UDFNUML +#define FNUM4_REG UDFNUML +#define FNUM5_REG UDFNUML +#define FNUM6_REG UDFNUML +#define FNUM7_REG UDFNUML + +/* UDFNUMH */ +#define FNUM8_REG UDFNUMH +#define FNUM9_REG UDFNUMH +#define FNUM10_REG UDFNUMH + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* PRR0 */ +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 + +/* UBRR1H */ +#define UBRR1_8_REG UBRR1H +#define UBRR1_9_REG UBRR1H +#define UBRR1_10_REG UBRR1H +#define UBRR1_11_REG UBRR1H + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +#define DTSEQ0_REG UESTA0X +#define DTSEQ1_REG UESTA0X +#define UNDERFI_REG UESTA0X +#define OVERFI_REG UESTA0X +#define CFGOK_REG UESTA0X + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* CLKSTA */ +#define EXTON_REG CLKSTA +#define RCON_REG CLKSTA + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSB_REG PRR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega103.h b/include/aversive/parts/ATmega103.h new file mode 100644 index 0000000..a2c465a --- /dev/null +++ b/include/aversive/parts/ATmega103.h @@ -0,0 +1,811 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_64 3 +#define TIMER2_PRESCALER_DIV_256 4 +#define TIMER2_PRESCALER_DIV_1024 5 +#define TIMER2_PRESCALER_DIV_FALL 6 +#define TIMER2_PRESCALER_DIV_RISE 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 64 +#define TIMER2_PRESCALER_REG_4 256 +#define TIMER2_PRESCALER_REG_5 1024 +#define TIMER2_PRESCALER_REG_6 -1 +#define TIMER2_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define CTC0_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define PWM0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* XDIV */ +#define XDIV0_REG XDIV +#define XDIV1_REG XDIV +#define XDIV2_REG XDIV +#define XDIV3_REG XDIV +#define XDIV4_REG XDIV +#define XDIV5_REG XDIV +#define XDIV6_REG XDIV +#define XDIVEN_REG XDIV + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* TIMSK */ +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* EICR */ +#define ISC40_REG EICR +#define ISC41_REG EICR +#define ISC50_REG EICR +#define ISC51_REG EICR +#define ISC60_REG EICR +#define ISC61_REG EICR +#define ISC70_REG EICR +#define ISC71_REG EICR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* ADCL */ +#define ADC0_REG ADCL +#define ADC1_REG ADCL +#define ADC2_REG ADCL +#define ADC3_REG ADCL +#define ADC4_REG ADCL +#define ADC5_REG ADCL +#define ADC6_REG ADCL +#define ADC7_REG ADCL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADC8_REG ADCH +#define ADC9_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define CTC2_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define PWM2_REG TCCR2 + +/* TIFR */ +#define TOV2_REG TIFR +#define OCF2_REG TIFR +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR + +/* UCR */ +#define TXB8_REG UCR +#define RXB8_REG UCR +#define CHR9_REG UCR +#define TXEN_REG UCR +#define RXEN_REG UCR +#define UDRIE_REG UCR +#define TXCIE_REG UCR +#define RXCIE_REG UCR + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* MCUCR */ +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USR */ +#define OR_REG USR +#define FE_REG USR +#define UDRE_REG USR +#define TXC_REG USR +#define RXC_REG USR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR0UB_REG ASSR +#define OCR0UB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define AC+_PORT PORTE +#define AC+_BIT 2 + +#define AC-_PORT PORTE +#define AC-_BIT 3 + +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 + + diff --git a/include/aversive/parts/ATmega103comp.h b/include/aversive/parts/ATmega103comp.h new file mode 100644 index 0000000..57b5ed6 --- /dev/null +++ b/include/aversive/parts/ATmega103comp.h @@ -0,0 +1,902 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_64 3 +#define TIMER2_PRESCALER_DIV_256 4 +#define TIMER2_PRESCALER_DIV_1024 5 +#define TIMER2_PRESCALER_DIV_FALL 6 +#define TIMER2_PRESCALER_DIV_RISE 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 64 +#define TIMER2_PRESCALER_REG_4 256 +#define TIMER2_PRESCALER_REG_5 1024 +#define TIMER2_PRESCALER_REG_6 -1 +#define TIMER2_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define CTC0_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define PWM0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* XDIV */ +#define XDIV0_REG XDIV +#define XDIV1_REG XDIV +#define XDIV2_REG XDIV +#define XDIV3_REG XDIV +#define XDIV4_REG XDIV +#define XDIV5_REG XDIV +#define XDIV6_REG XDIV +#define XDIVEN_REG XDIV + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* TIMSK */ +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR321_REG SFIOR +#define PSR0_REG SFIOR +#define PUD_REG SFIOR +#define TSM_REG SFIOR + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define CTC2_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define PWM2_REG TCCR2 + +/* TIFR */ +#define TOV2_REG TIFR +#define OCF2_REG TIFR +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define SM2_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR0UB_REG ASSR +#define OCR0UB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/ATmega128.h b/include/aversive/parts/ATmega128.h new file mode 100644 index 0000000..ce7bb16 --- /dev/null +++ b/include/aversive/parts/ATmega128.h @@ -0,0 +1,1327 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_64 3 +#define TIMER2_PRESCALER_DIV_256 4 +#define TIMER2_PRESCALER_DIV_1024 5 +#define TIMER2_PRESCALER_DIV_FALL 6 +#define TIMER2_PRESCALER_DIV_RISE 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 64 +#define TIMER2_PRESCALER_REG_4 256 +#define TIMER2_PRESCALER_REG_5 1024 +#define TIMER2_PRESCALER_REG_6 -1 +#define TIMER2_PRESCALER_REG_7 -2 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* ASSR */ +#define TCR0UB_REG ASSR +#define OCR0UB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR321_REG SFIOR +#define PSR0_REG SFIOR +#define PUD_REG SFIOR +#define TSM_REG SFIOR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* ETIFR */ +#define OCF1C_REG ETIFR +#define OCF3C_REG ETIFR +#define TOV3_REG ETIFR +#define OCF3B_REG ETIFR +#define OCF3A_REG ETIFR +#define ICF3_REG ETIFR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* XDIV */ +#define XDIV0_REG XDIV +#define XDIV1_REG XDIV +#define XDIV2_REG XDIV +#define XDIV3_REG XDIV +#define XDIV4_REG XDIV +#define XDIV5_REG XDIV +#define XDIV6_REG XDIV +#define XDIVEN_REG XDIV + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* ETIMSK */ +#define OCIE1C_REG ETIMSK +#define OCIE3C_REG ETIMSK +#define TOIE3_REG ETIMSK +#define OCIE3B_REG ETIMSK +#define OCIE3A_REG ETIMSK +#define TICIE3_REG ETIMSK + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCN3L0_REG TCNT3L +#define TCN3L1_REG TCNT3L +#define TCN3L2_REG TCNT3L +#define TCN3L3_REG TCNT3L +#define TCN3L4_REG TCNT3L +#define TCN3L5_REG TCNT3L +#define TCN3L6_REG TCNT3L +#define TCN3L7_REG TCNT3L + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define SM2_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADFR_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW11_REG XMCRA +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/ATmega1280.h b/include/aversive/parts/ATmega1280.h new file mode 100644 index 0000000..b3838b0 --- /dev/null +++ b/include/aversive/parts/ATmega1280.h @@ -0,0 +1,2188 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ +#define TIMER4_PRESCALER_DIV_0 0 +#define TIMER4_PRESCALER_DIV_1 1 +#define TIMER4_PRESCALER_DIV_8 2 +#define TIMER4_PRESCALER_DIV_64 3 +#define TIMER4_PRESCALER_DIV_256 4 +#define TIMER4_PRESCALER_DIV_1024 5 +#define TIMER4_PRESCALER_DIV_FALL 6 +#define TIMER4_PRESCALER_DIV_RISE 7 + +#define TIMER4_PRESCALER_REG_0 0 +#define TIMER4_PRESCALER_REG_1 1 +#define TIMER4_PRESCALER_REG_2 8 +#define TIMER4_PRESCALER_REG_3 64 +#define TIMER4_PRESCALER_REG_4 256 +#define TIMER4_PRESCALER_REG_5 1024 +#define TIMER4_PRESCALER_REG_6 -1 +#define TIMER4_PRESCALER_REG_7 -2 + +/* prescalers timer 5 */ +#define TIMER5_PRESCALER_DIV_0 0 +#define TIMER5_PRESCALER_DIV_1 1 +#define TIMER5_PRESCALER_DIV_8 2 +#define TIMER5_PRESCALER_DIV_64 3 +#define TIMER5_PRESCALER_DIV_256 4 +#define TIMER5_PRESCALER_DIV_1024 5 +#define TIMER5_PRESCALER_DIV_FALL 6 +#define TIMER5_PRESCALER_DIV_RISE 7 + +#define TIMER5_PRESCALER_REG_0 0 +#define TIMER5_PRESCALER_REG_1 1 +#define TIMER5_PRESCALER_REG_2 8 +#define TIMER5_PRESCALER_REG_3 64 +#define TIMER5_PRESCALER_REG_4 256 +#define TIMER5_PRESCALER_REG_5 1024 +#define TIMER5_PRESCALER_REG_6 -1 +#define TIMER5_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE +#define TIMER4C_AVAILABLE +#define TIMER5_AVAILABLE +#define TIMER5A_AVAILABLE +#define TIMER5B_AVAILABLE +#define TIMER5C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW4_NUM 4 +#define SIG_OVERFLOW5_NUM 5 +#define SIG_OVERFLOW_TOTAL_NUM 6 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE4A_NUM 10 +#define SIG_OUTPUT_COMPARE4B_NUM 11 +#define SIG_OUTPUT_COMPARE4C_NUM 12 +#define SIG_OUTPUT_COMPARE5A_NUM 13 +#define SIG_OUTPUT_COMPARE5B_NUM 14 +#define SIG_OUTPUT_COMPARE5C_NUM 15 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM4A_NUM 10 +#define PWM4B_NUM 11 +#define PWM4C_NUM 12 +#define PWM5A_NUM 13 +#define PWM5B_NUM 14 +#define PWM5C_NUM 15 +#define PWM_TOTAL_NUM 16 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE4_NUM 2 +#define SIG_INPUT_CAPTURE5_NUM 3 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 4 + + +/* UBRR3H */ +/* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ + +/* UBRR3L */ +/* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UCSR3A */ +#define MPCM3_REG UCSR3A +#define U2X3_REG UCSR3A +#define UPE3_REG UCSR3A +#define DOR3_REG UCSR3A +#define FE3_REG UCSR3A +#define UDRE3_REG UCSR3A +#define TXC3_REG UCSR3A +#define RXC3_REG UCSR3A + +/* UCSR3B */ +#define TXB83_REG UCSR3B +#define RXB83_REG UCSR3B +#define UCSZ32_REG UCSR3B +#define TXEN3_REG UCSR3B +#define RXEN3_REG UCSR3B +#define UDRIE3_REG UCSR3B +#define TXCIE3_REG UCSR3B +#define RXCIE3_REG UCSR3B + +/* UCSR3C */ +#define UCPOL3_REG UCSR3C +#define UCSZ30_REG UCSR3C +#define UCSZ31_REG UCSR3C +#define USBS3_REG UCSR3C +#define UPM30_REG UCSR3C +#define UPM31_REG UCSR3C +#define UMSEL30_REG UCSR3C +#define UMSEL31_REG UCSR3C + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ +#define RAMPZ1_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* PORTL */ +#define PORTL0_REG PORTL +#define PORTL1_REG PORTL +#define PORTL2_REG PORTL +#define PORTL3_REG PORTL +#define PORTL4_REG PORTL +#define PORTL5_REG PORTL +#define PORTL6_REG PORTL +#define PORTL7_REG PORTL + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ +#define PORTJ7_REG PORTJ + +/* PORTK */ +#define PORTK0_REG PORTK +#define PORTK1_REG PORTK +#define PORTK2_REG PORTK +#define PORTK3_REG PORTK +#define PORTK4_REG PORTK +#define PORTK5_REG PORTK +#define PORTK6_REG PORTK +#define PORTK7_REG PORTK + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG +#define PORTG5_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* UDR3 */ +#define UDR3_0_REG UDR3 +#define UDR3_1_REG UDR3 +#define UDR3_2_REG UDR3 +#define UDR3_3_REG UDR3 +#define UDR3_4_REG UDR3 +#define UDR3_5_REG UDR3 +#define UDR3_6_REG UDR3 +#define UDR3_7_REG UDR3 + +/* UDR2 */ +#define UDR2_0_REG UDR2 +#define UDR2_1_REG UDR2 +#define UDR2_2_REG UDR2 +#define UDR2_3_REG UDR2 +#define UDR2_4_REG UDR2 +#define UDR2_5_REG UDR2 +#define UDR2_6_REG UDR2 +#define UDR2_7_REG UDR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 +#define ADC14D_REG DIDR2 +#define ADC15D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ +#define DDJ7_REG DDRJ + +/* DDRK */ +#define DDK0_REG DDRK +#define DDK1_REG DDRK +#define DDK2_REG DDRK +#define DDK3_REG DDRK +#define DDK4_REG DDRK +#define DDK5_REG DDRK +#define DDK6_REG DDRK +#define DDK7_REG DDRK + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRL */ +#define DDL0_REG DDRL +#define DDL1_REG DDRL +#define DDL2_REG DDRL +#define DDL3_REG DDRL +#define DDL4_REG DDRL +#define DDL5_REG DDRL +#define DDL6_REG DDRL +#define DDL7_REG DDRL + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG +#define DDG5_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCNT5H */ +#define TCNT5H0_REG TCNT5H +#define TCNT5H1_REG TCNT5H +#define TCNT5H2_REG TCNT5H +#define TCNT5H3_REG TCNT5H +#define TCNT5H4_REG TCNT5H +#define TCNT5H5_REG TCNT5H +#define TCNT5H6_REG TCNT5H +#define TCNT5H7_REG TCNT5H + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* TCNT5L */ +#define TCNT5L0_REG TCNT5L +#define TCNT5L1_REG TCNT5L +#define TCNT5L2_REG TCNT5L +#define TCNT5L3_REG TCNT5L +#define TCNT5L4_REG TCNT5L +#define TCNT5L5_REG TCNT5L +#define TCNT5L6_REG TCNT5L +#define TCNT5L7_REG TCNT5L + +/* UBRR2H */ +/* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ + +/* UBRR2L */ +/* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UCSR2B */ +#define TXB82_REG UCSR2B +#define RXB82_REG UCSR2B +#define UCSZ22_REG UCSR2B +#define TXEN2_REG UCSR2B +#define RXEN2_REG UCSR2B +#define UDRIE2_REG UCSR2B +#define TXCIE2_REG UCSR2B +#define RXCIE2_REG UCSR2B + +/* UCSR2A */ +#define MPCM2_REG UCSR2A +#define U2X2_REG UCSR2A +#define UPE2_REG UCSR2A +#define DOR2_REG UCSR2A +#define FE2_REG UCSR2A +#define UDRE2_REG UCSR2A +#define TXC2_REG UCSR2A +#define RXC2_REG UCSR2A + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UCSR2C */ +#define UCPOL2_REG UCSR2C +#define UCSZ20_REG UCSR2C +#define UCSZ21_REG UCSR2C +#define USBS2_REG UCSR2C +#define UPM20_REG UCSR2C +#define UPM21_REG UCSR2C +#define UMSEL20_REG UCSR2C +#define UMSEL21_REG UCSR2C + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4C_REG TIFR4 +#define ICF4_REG TIFR4 + +/* TIFR5 */ +#define TOV5_REG TIFR5 +#define OCF5A_REG TIFR5 +#define OCF5B_REG TIFR5 +#define OCF5C_REG TIFR5 +#define ICF5_REG TIFR5 + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* OCR4AH */ +#define OCR4AH0_REG OCR4AH +#define OCR4AH1_REG OCR4AH +#define OCR4AH2_REG OCR4AH +#define OCR4AH3_REG OCR4AH +#define OCR4AH4_REG OCR4AH +#define OCR4AH5_REG OCR4AH +#define OCR4AH6_REG OCR4AH +#define OCR4AH7_REG OCR4AH + +/* OCR5CH */ +#define OCR5CH0_REG OCR5CH +#define OCR5CH1_REG OCR5CH +#define OCR5CH2_REG OCR5CH +#define OCR5CH3_REG OCR5CH +#define OCR5CH4_REG OCR5CH +#define OCR5CH5_REG OCR5CH +#define OCR5CH6_REG OCR5CH +#define OCR5CH7_REG OCR5CH + +/* OCR4AL */ +#define OCR4AL0_REG OCR4AL +#define OCR4AL1_REG OCR4AL +#define OCR4AL2_REG OCR4AL +#define OCR4AL3_REG OCR4AL +#define OCR4AL4_REG OCR4AL +#define OCR4AL5_REG OCR4AL +#define OCR4AL6_REG OCR4AL +#define OCR4AL7_REG OCR4AL + +/* OCR5CL */ +#define OCR5CL0_REG OCR5CL +#define OCR5CL1_REG OCR5CL +#define OCR5CL2_REG OCR5CL +#define OCR5CL3_REG OCR5CL +#define OCR5CL4_REG OCR5CL +#define OCR5CL5_REG OCR5CL +#define OCR5CL6_REG OCR5CL +#define OCR5CL7_REG OCR5CL + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* ICR5L */ +#define ICR5L0_REG ICR5L +#define ICR5L1_REG ICR5L +#define ICR5L2_REG ICR5L +#define ICR5L3_REG ICR5L +#define ICR5L4_REG ICR5L +#define ICR5L5_REG ICR5L +#define ICR5L6_REG ICR5L +#define ICR5L7_REG ICR5L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ICR5H */ +#define ICR5H0_REG ICR5H +#define ICR5H1_REG ICR5H +#define ICR5H2_REG ICR5H +#define ICR5H3_REG ICR5H +#define ICR5H4_REG ICR5H +#define ICR5H5_REG ICR5H +#define ICR5H6_REG ICR5H +#define ICR5H7_REG ICR5H + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* PINK */ +#define PINK0_REG PINK +#define PINK1_REG PINK +#define PINK2_REG PINK +#define PINK3_REG PINK +#define PINK4_REG PINK +#define PINK5_REG PINK +#define PINK6_REG PINK +#define PINK7_REG PINK + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ +#define PINJ7_REG PINJ + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* ICR4H */ +#define ICR4H0_REG ICR4H +#define ICR4H1_REG ICR4H +#define ICR4H2_REG ICR4H +#define ICR4H3_REG ICR4H +#define ICR4H4_REG ICR4H +#define ICR4H5_REG ICR4H +#define ICR4H6_REG ICR4H +#define ICR4H7_REG ICR4H + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* ICR4L */ +#define ICR4L0_REG ICR4L +#define ICR4L1_REG ICR4L +#define ICR4L2_REG ICR4L +#define ICR4L3_REG ICR4L +#define ICR4L4_REG ICR4L +#define ICR4L5_REG ICR4L +#define ICR4L6_REG ICR4L +#define ICR4L7_REG ICR4L + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* TCNT4L */ +#define TCNT4L0_REG TCNT4L +#define TCNT4L1_REG TCNT4L +#define TCNT4L2_REG TCNT4L +#define TCNT4L3_REG TCNT4L +#define TCNT4L4_REG TCNT4L +#define TCNT4L5_REG TCNT4L +#define TCNT4L6_REG TCNT4L +#define TCNT4L7_REG TCNT4L + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* TCNT4H */ +#define TCNT4H0_REG TCNT4H +#define TCNT4H1_REG TCNT4H +#define TCNT4H2_REG TCNT4H +#define TCNT4H3_REG TCNT4H +#define TCNT4H4_REG TCNT4H +#define TCNT4H5_REG TCNT4H +#define TCNT4H6_REG TCNT4H +#define TCNT4H7_REG TCNT4H + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TCCR5A */ +#define WGM50_REG TCCR5A +#define WGM51_REG TCCR5A +#define COM5C0_REG TCCR5A +#define COM5C1_REG TCCR5A +#define COM5B0_REG TCCR5A +#define COM5B1_REG TCCR5A +#define COM5A0_REG TCCR5A +#define COM5A1_REG TCCR5A + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* TCCR5C */ +#define FOC5C_REG TCCR5C +#define FOC5B_REG TCCR5C +#define FOC5A_REG TCCR5C + +/* TCCR5B */ +#define CS50_REG TCCR5B +#define CS51_REG TCCR5B +#define CS52_REG TCCR5B +#define WGM52_REG TCCR5B +#define WGM53_REG TCCR5B +#define ICES5_REG TCCR5B +#define ICNC5_REG TCCR5B + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB + +/* OCR5AL */ +#define OCR5AL0_REG OCR5AL +#define OCR5AL1_REG OCR5AL +#define OCR5AL2_REG OCR5AL +#define OCR5AL3_REG OCR5AL +#define OCR5AL4_REG OCR5AL +#define OCR5AL5_REG OCR5AL +#define OCR5AL6_REG OCR5AL +#define OCR5AL7_REG OCR5AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR4CH */ +#define OCR4CH0_REG OCR4CH +#define OCR4CH1_REG OCR4CH +#define OCR4CH2_REG OCR4CH +#define OCR4CH3_REG OCR4CH +#define OCR4CH4_REG OCR4CH +#define OCR4CH5_REG OCR4CH +#define OCR4CH6_REG OCR4CH +#define OCR4CH7_REG OCR4CH + +/* OCR5AH */ +#define OCR5AH0_REG OCR5AH +#define OCR5AH1_REG OCR5AH +#define OCR5AH2_REG OCR5AH +#define OCR5AH3_REG OCR5AH +#define OCR5AH4_REG OCR5AH +#define OCR5AH5_REG OCR5AH +#define OCR5AH6_REG OCR5AH +#define OCR5AH7_REG OCR5AH + +/* OCR4CL */ +#define OCR4CL0_REG OCR4CL +#define OCR4CL1_REG OCR4CL +#define OCR4CL2_REG OCR4CL +#define OCR4CL3_REG OCR4CL +#define OCR4CL4_REG OCR4CL +#define OCR4CL5_REG OCR4CL +#define OCR4CL6_REG OCR4CL +#define OCR4CL7_REG OCR4CL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR5BH */ +#define OCR5BH0_REG OCR5BH +#define OCR5BH1_REG OCR5BH +#define OCR5BH2_REG OCR5BH +#define OCR5BH3_REG OCR5BH +#define OCR5BH4_REG OCR5BH +#define OCR5BH5_REG OCR5BH +#define OCR5BH6_REG OCR5BH +#define OCR5BH7_REG OCR5BH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR5BL */ +#define OCR5BL0_REG OCR5BL +#define OCR5BL1_REG OCR5BL +#define OCR5BL2_REG OCR5BL +#define OCR5BL3_REG OCR5BL +#define OCR5BL4_REG OCR5BL +#define OCR5BL5_REG OCR5BL +#define OCR5BL6_REG OCR5BL +#define OCR5BL7_REG OCR5BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4C_REG TIMSK4 +#define ICIE4_REG TIMSK4 + +/* TIMSK5 */ +#define TOIE5_REG TIMSK5 +#define OCIE5A_REG TIMSK5 +#define OCIE5B_REG TIMSK5 +#define OCIE5C_REG TIMSK5 +#define ICIE5_REG TIMSK5 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define WGM42_REG TCCR4B +#define WGM43_REG TCCR4B +#define ICES4_REG TCCR4B +#define ICNC4_REG TCCR4B + +/* TCCR4C */ +#define FOC4C_REG TCCR4C +#define FOC4B_REG TCCR4C +#define FOC4A_REG TCCR4C + +/* TCCR4A */ +#define WGM40_REG TCCR4A +#define WGM41_REG TCCR4A +#define COM4C0_REG TCCR4A +#define COM4C1_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINL */ +#define PINL0_REG PINL +#define PINL1_REG PINL +#define PINL2_REG PINL +#define PINL3_REG PINL +#define PINL4_REG PINL +#define PINL5_REG PINL +#define PINL6_REG PINL +#define PINL7_REG PINL + +/* OCR4BL */ +#define OCR4BL0_REG OCR4BL +#define OCR4BL1_REG OCR4BL +#define OCR4BL2_REG OCR4BL +#define OCR4BL3_REG OCR4BL +#define OCR4BL4_REG OCR4BL +#define OCR4BL5_REG OCR4BL +#define OCR4BL6_REG OCR4BL +#define OCR4BL7_REG OCR4BL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* OCR4BH */ +#define OCR4BH0_REG OCR4BH +#define OCR4BH1_REG OCR4BH +#define OCR4BH2_REG OCR4BH +#define OCR4BH3_REG OCR4BH +#define OCR4BH4_REG OCR4BH +#define OCR4BH5_REG OCR4BH +#define OCR4BH6_REG OCR4BH +#define OCR4BH7_REG OCR4BH + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSART2_REG PRR1 +#define PRUSART3_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRTIM4_REG PRR1 +#define PRTIM5_REG PRR1 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define OC0A_PORT PORTB +#define OC0A_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define OC0A_PORT PORTB +#define OC0A_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define ICP1_PORT PORTD +#define ICP1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T0_PORT PORTD +#define T0_BIT 7 + +#define RXD_PORT PORTE +#define RXD_BIT 0 +#define PCINT8_PORT PORTE +#define PCINT8_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 + +#define XCK_PORT PORTE +#define XCK_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define CLKO_PORT PORTE +#define CLKO_BIT 7 +#define ICP3_PORT PORTE +#define ICP3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TDO_PORT PORTF +#define TDO_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + +#define OC0B_PORT PORTG +#define OC0B_BIT 5 + +#define RXD2_PORT PORTH +#define RXD2_BIT 0 + +#define TXD2_PORT PORTH +#define TXD2_BIT 1 + +#define XCK2_PORT PORTH +#define XCK2_BIT 2 + +#define OC4A_PORT PORTH +#define OC4A_BIT 3 + +#define OC4B_PORT PORTH +#define OC4B_BIT 4 + +#define OC2B_PORT PORTH +#define OC2B_BIT 6 + +#define T4_PORT PORTH +#define T4_BIT 7 + +#define RXD3_PORT PORTJ +#define RXD3_BIT 0 +#define PCINT9_PORT PORTJ +#define PCINT9_BIT 0 + +#define TXD3_PORT PORTJ +#define TXD3_BIT 1 +#define PCINT10_PORT PORTJ +#define PCINT10_BIT 1 + +#define XCK3_PORT PORTJ +#define XCK3_BIT 2 +#define PCINT11_PORT PORTJ +#define PCINT11_BIT 2 + +#define PCINT12_PORT PORTJ +#define PCINT12_BIT 3 + +#define PCINT13_PORT PORTJ +#define PCINT13_BIT 4 + +#define PCINT15_PORT PORTJ +#define PCINT15_BIT 6 + +#define ADC8_PORT PORTK +#define ADC8_BIT 0 +#define PCINT16_PORT PORTK +#define PCINT16_BIT 0 + +#define ADC9_PORT PORTK +#define ADC9_BIT 1 +#define PCINT17_PORT PORTK +#define PCINT17_BIT 1 + +#define ADC10_PORT PORTK +#define ADC10_BIT 2 +#define PCINT18_PORT PORTK +#define PCINT18_BIT 2 + +#define ADC11_PORT PORTK +#define ADC11_BIT 3 +#define PCINT19_PORT PORTK +#define PCINT19_BIT 3 + +#define ADC12_PORT PORTK +#define ADC12_BIT 4 +#define PCINT20_PORT PORTK +#define PCINT20_BIT 4 + +#define ADC13_PORT PORTK +#define ADC13_BIT 5 +#define PCINT21_PORT PORTK +#define PCINT21_BIT 5 + +#define ADC14_PORT PORTK +#define ADC14_BIT 6 +#define PCINT22_PORT PORTK +#define PCINT22_BIT 6 + +#define ADC15_PORT PORTK +#define ADC15_BIT 7 +#define PCINT23_PORT PORTK +#define PCINT23_BIT 7 + +#define ICP4_PORT PORTL +#define ICP4_BIT 0 + +#define ICP5_PORT PORTL +#define ICP5_BIT 1 + +#define T5_PORT PORTL +#define T5_BIT 2 + +#define OC5A_PORT PORTL +#define OC5A_BIT 3 + +#define OC5B_PORT PORTL +#define OC5B_BIT 4 + + diff --git a/include/aversive/parts/ATmega1281.h b/include/aversive/parts/ATmega1281.h new file mode 100644 index 0000000..7f0a45c --- /dev/null +++ b/include/aversive/parts/ATmega1281.h @@ -0,0 +1,1872 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ +#define TIMER4_PRESCALER_DIV_0 0 +#define TIMER4_PRESCALER_DIV_1 1 +#define TIMER4_PRESCALER_DIV_8 2 +#define TIMER4_PRESCALER_DIV_64 3 +#define TIMER4_PRESCALER_DIV_256 4 +#define TIMER4_PRESCALER_DIV_1024 5 +#define TIMER4_PRESCALER_DIV_FALL 6 +#define TIMER4_PRESCALER_DIV_RISE 7 + +#define TIMER4_PRESCALER_REG_0 0 +#define TIMER4_PRESCALER_REG_1 1 +#define TIMER4_PRESCALER_REG_2 8 +#define TIMER4_PRESCALER_REG_3 64 +#define TIMER4_PRESCALER_REG_4 256 +#define TIMER4_PRESCALER_REG_5 1024 +#define TIMER4_PRESCALER_REG_6 -1 +#define TIMER4_PRESCALER_REG_7 -2 + +/* prescalers timer 5 */ +#define TIMER5_PRESCALER_DIV_0 0 +#define TIMER5_PRESCALER_DIV_1 1 +#define TIMER5_PRESCALER_DIV_8 2 +#define TIMER5_PRESCALER_DIV_64 3 +#define TIMER5_PRESCALER_DIV_256 4 +#define TIMER5_PRESCALER_DIV_1024 5 +#define TIMER5_PRESCALER_DIV_FALL 6 +#define TIMER5_PRESCALER_DIV_RISE 7 + +#define TIMER5_PRESCALER_REG_0 0 +#define TIMER5_PRESCALER_REG_1 1 +#define TIMER5_PRESCALER_REG_2 8 +#define TIMER5_PRESCALER_REG_3 64 +#define TIMER5_PRESCALER_REG_4 256 +#define TIMER5_PRESCALER_REG_5 1024 +#define TIMER5_PRESCALER_REG_6 -1 +#define TIMER5_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE +#define TIMER4C_AVAILABLE +#define TIMER5_AVAILABLE +#define TIMER5A_AVAILABLE +#define TIMER5B_AVAILABLE +#define TIMER5C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW4_NUM 4 +#define SIG_OVERFLOW5_NUM 5 +#define SIG_OVERFLOW_TOTAL_NUM 6 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE4A_NUM 10 +#define SIG_OUTPUT_COMPARE4B_NUM 11 +#define SIG_OUTPUT_COMPARE4C_NUM 12 +#define SIG_OUTPUT_COMPARE5A_NUM 13 +#define SIG_OUTPUT_COMPARE5B_NUM 14 +#define SIG_OUTPUT_COMPARE5C_NUM 15 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM4A_NUM 10 +#define PWM4B_NUM 11 +#define PWM4C_NUM 12 +#define PWM5A_NUM 13 +#define PWM5B_NUM 14 +#define PWM5C_NUM 15 +#define PWM_TOTAL_NUM 16 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE4_NUM 2 +#define SIG_INPUT_CAPTURE5_NUM 3 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 4 + + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ +#define RAMPZ1_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG +#define PORTG5_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 +#define ADC14D_REG DIDR2 +#define ADC15D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG +#define DDG5_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCNT5H */ +#define TCNT5H0_REG TCNT5H +#define TCNT5H1_REG TCNT5H +#define TCNT5H2_REG TCNT5H +#define TCNT5H3_REG TCNT5H +#define TCNT5H4_REG TCNT5H +#define TCNT5H5_REG TCNT5H +#define TCNT5H6_REG TCNT5H +#define TCNT5H7_REG TCNT5H + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* TCNT5L */ +#define TCNT5L0_REG TCNT5L +#define TCNT5L1_REG TCNT5L +#define TCNT5L2_REG TCNT5L +#define TCNT5L3_REG TCNT5L +#define TCNT5L4_REG TCNT5L +#define TCNT5L5_REG TCNT5L +#define TCNT5L6_REG TCNT5L +#define TCNT5L7_REG TCNT5L + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4C_REG TIFR4 +#define ICF4_REG TIFR4 + +/* TIFR5 */ +#define TOV5_REG TIFR5 +#define OCF5A_REG TIFR5 +#define OCF5B_REG TIFR5 +#define OCF5C_REG TIFR5 +#define ICF5_REG TIFR5 + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* OCR4AH */ +#define OCR4AH0_REG OCR4AH +#define OCR4AH1_REG OCR4AH +#define OCR4AH2_REG OCR4AH +#define OCR4AH3_REG OCR4AH +#define OCR4AH4_REG OCR4AH +#define OCR4AH5_REG OCR4AH +#define OCR4AH6_REG OCR4AH +#define OCR4AH7_REG OCR4AH + +/* OCR5CH */ +#define OCR5CH0_REG OCR5CH +#define OCR5CH1_REG OCR5CH +#define OCR5CH2_REG OCR5CH +#define OCR5CH3_REG OCR5CH +#define OCR5CH4_REG OCR5CH +#define OCR5CH5_REG OCR5CH +#define OCR5CH6_REG OCR5CH +#define OCR5CH7_REG OCR5CH + +/* OCR4AL */ +#define OCR4AL0_REG OCR4AL +#define OCR4AL1_REG OCR4AL +#define OCR4AL2_REG OCR4AL +#define OCR4AL3_REG OCR4AL +#define OCR4AL4_REG OCR4AL +#define OCR4AL5_REG OCR4AL +#define OCR4AL6_REG OCR4AL +#define OCR4AL7_REG OCR4AL + +/* OCR5CL */ +#define OCR5CL0_REG OCR5CL +#define OCR5CL1_REG OCR5CL +#define OCR5CL2_REG OCR5CL +#define OCR5CL3_REG OCR5CL +#define OCR5CL4_REG OCR5CL +#define OCR5CL5_REG OCR5CL +#define OCR5CL6_REG OCR5CL +#define OCR5CL7_REG OCR5CL + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* ICR5L */ +#define ICR5L0_REG ICR5L +#define ICR5L1_REG ICR5L +#define ICR5L2_REG ICR5L +#define ICR5L3_REG ICR5L +#define ICR5L4_REG ICR5L +#define ICR5L5_REG ICR5L +#define ICR5L6_REG ICR5L +#define ICR5L7_REG ICR5L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ICR5H */ +#define ICR5H0_REG ICR5H +#define ICR5H1_REG ICR5H +#define ICR5H2_REG ICR5H +#define ICR5H3_REG ICR5H +#define ICR5H4_REG ICR5H +#define ICR5H5_REG ICR5H +#define ICR5H6_REG ICR5H +#define ICR5H7_REG ICR5H + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* ICR4H */ +#define ICR4H0_REG ICR4H +#define ICR4H1_REG ICR4H +#define ICR4H2_REG ICR4H +#define ICR4H3_REG ICR4H +#define ICR4H4_REG ICR4H +#define ICR4H5_REG ICR4H +#define ICR4H6_REG ICR4H +#define ICR4H7_REG ICR4H + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* ICR4L */ +#define ICR4L0_REG ICR4L +#define ICR4L1_REG ICR4L +#define ICR4L2_REG ICR4L +#define ICR4L3_REG ICR4L +#define ICR4L4_REG ICR4L +#define ICR4L5_REG ICR4L +#define ICR4L6_REG ICR4L +#define ICR4L7_REG ICR4L + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* TCNT4L */ +#define TCNT4L0_REG TCNT4L +#define TCNT4L1_REG TCNT4L +#define TCNT4L2_REG TCNT4L +#define TCNT4L3_REG TCNT4L +#define TCNT4L4_REG TCNT4L +#define TCNT4L5_REG TCNT4L +#define TCNT4L6_REG TCNT4L +#define TCNT4L7_REG TCNT4L + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* TCNT4H */ +#define TCNT4H0_REG TCNT4H +#define TCNT4H1_REG TCNT4H +#define TCNT4H2_REG TCNT4H +#define TCNT4H3_REG TCNT4H +#define TCNT4H4_REG TCNT4H +#define TCNT4H5_REG TCNT4H +#define TCNT4H6_REG TCNT4H +#define TCNT4H7_REG TCNT4H + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TCCR5A */ +#define WGM50_REG TCCR5A +#define WGM51_REG TCCR5A +#define COM5C0_REG TCCR5A +#define COM5C1_REG TCCR5A +#define COM5B0_REG TCCR5A +#define COM5B1_REG TCCR5A +#define COM5A0_REG TCCR5A +#define COM5A1_REG TCCR5A + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* TCCR5C */ +#define FOC5C_REG TCCR5C +#define FOC5B_REG TCCR5C +#define FOC5A_REG TCCR5C + +/* TCCR5B */ +#define CS50_REG TCCR5B +#define CS51_REG TCCR5B +#define CS52_REG TCCR5B +#define WGM52_REG TCCR5B +#define WGM53_REG TCCR5B +#define ICES5_REG TCCR5B +#define ICNC5_REG TCCR5B + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB + +/* OCR5AL */ +#define OCR5AL0_REG OCR5AL +#define OCR5AL1_REG OCR5AL +#define OCR5AL2_REG OCR5AL +#define OCR5AL3_REG OCR5AL +#define OCR5AL4_REG OCR5AL +#define OCR5AL5_REG OCR5AL +#define OCR5AL6_REG OCR5AL +#define OCR5AL7_REG OCR5AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR4CH */ +#define OCR4CH0_REG OCR4CH +#define OCR4CH1_REG OCR4CH +#define OCR4CH2_REG OCR4CH +#define OCR4CH3_REG OCR4CH +#define OCR4CH4_REG OCR4CH +#define OCR4CH5_REG OCR4CH +#define OCR4CH6_REG OCR4CH +#define OCR4CH7_REG OCR4CH + +/* OCR5AH */ +#define OCR5AH0_REG OCR5AH +#define OCR5AH1_REG OCR5AH +#define OCR5AH2_REG OCR5AH +#define OCR5AH3_REG OCR5AH +#define OCR5AH4_REG OCR5AH +#define OCR5AH5_REG OCR5AH +#define OCR5AH6_REG OCR5AH +#define OCR5AH7_REG OCR5AH + +/* OCR4CL */ +#define OCR4CL0_REG OCR4CL +#define OCR4CL1_REG OCR4CL +#define OCR4CL2_REG OCR4CL +#define OCR4CL3_REG OCR4CL +#define OCR4CL4_REG OCR4CL +#define OCR4CL5_REG OCR4CL +#define OCR4CL6_REG OCR4CL +#define OCR4CL7_REG OCR4CL + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR5BH */ +#define OCR5BH0_REG OCR5BH +#define OCR5BH1_REG OCR5BH +#define OCR5BH2_REG OCR5BH +#define OCR5BH3_REG OCR5BH +#define OCR5BH4_REG OCR5BH +#define OCR5BH5_REG OCR5BH +#define OCR5BH6_REG OCR5BH +#define OCR5BH7_REG OCR5BH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR5BL */ +#define OCR5BL0_REG OCR5BL +#define OCR5BL1_REG OCR5BL +#define OCR5BL2_REG OCR5BL +#define OCR5BL3_REG OCR5BL +#define OCR5BL4_REG OCR5BL +#define OCR5BL5_REG OCR5BL +#define OCR5BL6_REG OCR5BL +#define OCR5BL7_REG OCR5BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4C_REG TIMSK4 +#define ICIE4_REG TIMSK4 + +/* TIMSK5 */ +#define TOIE5_REG TIMSK5 +#define OCIE5A_REG TIMSK5 +#define OCIE5B_REG TIMSK5 +#define OCIE5C_REG TIMSK5 +#define ICIE5_REG TIMSK5 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define WGM42_REG TCCR4B +#define WGM43_REG TCCR4B +#define ICES4_REG TCCR4B +#define ICNC4_REG TCCR4B + +/* TCCR4C */ +#define FOC4C_REG TCCR4C +#define FOC4B_REG TCCR4C +#define FOC4A_REG TCCR4C + +/* TCCR4A */ +#define WGM40_REG TCCR4A +#define WGM41_REG TCCR4A +#define COM4C0_REG TCCR4A +#define COM4C1_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* OCR4BL */ +#define OCR4BL0_REG OCR4BL +#define OCR4BL1_REG OCR4BL +#define OCR4BL2_REG OCR4BL +#define OCR4BL3_REG OCR4BL +#define OCR4BL4_REG OCR4BL +#define OCR4BL5_REG OCR4BL +#define OCR4BL6_REG OCR4BL +#define OCR4BL7_REG OCR4BL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* OCR4BH */ +#define OCR4BH0_REG OCR4BH +#define OCR4BH1_REG OCR4BH +#define OCR4BH2_REG OCR4BH +#define OCR4BH3_REG OCR4BH +#define OCR4BH4_REG OCR4BH +#define OCR4BH5_REG OCR4BH +#define OCR4BH6_REG OCR4BH +#define OCR4BH7_REG OCR4BH + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSART2_REG PRR1 +#define PRUSART3_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRTIM4_REG PRR1 +#define PRTIM5_REG PRR1 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define OC2_PORT PORTB +#define OC2_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define OC0A_PORT PORTB +#define OC0A_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define ICP1_PORT PORTD +#define ICP1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T0_PORT PORTD +#define T0_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 +#define PCINT8_PORT PORTE +#define PCINT8_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define ICP3_PORT PORTE +#define ICP3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 +#define CLKO_PORT PORTE +#define CLKO_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + +#define OC0B_PORT PORTG +#define OC0B_BIT 5 + + diff --git a/include/aversive/parts/ATmega1284P.h b/include/aversive/parts/ATmega1284P.h new file mode 100644 index 0000000..0ed6330 --- /dev/null +++ b/include/aversive/parts/ATmega1284P.h @@ -0,0 +1,1316 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE3A_NUM 6 +#define SIG_OUTPUT_COMPARE3B_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM3A_NUM 6 +#define PWM3B_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +/* #define OCR3AL0_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL1_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL2_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL3_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL4_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL5_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL6_REG OCR3AL */ /* dup in OCR3BL */ +/* #define OCR3AL7_REG OCR3AL */ /* dup in OCR3BL */ + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR3AH */ +/* #define OCR3AH0_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH1_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH2_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH3_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH4_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH5_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH6_REG OCR3AH */ /* dup in OCR3BH */ +/* #define OCR3AH7_REG OCR3AH */ /* dup in OCR3BH */ + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR3C */ +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRUSART1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +/* #define OCR3AL0_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL1_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL2_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL3_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL4_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL5_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL6_REG OCR3BL */ /* dup in OCR3AL */ +/* #define OCR3AL7_REG OCR3BL */ /* dup in OCR3AL */ + +/* OCR3BH */ +/* #define OCR3AH0_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH1_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH2_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH3_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH4_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH5_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH6_REG OCR3BH */ /* dup in OCR3AH */ +/* #define OCR3AH7_REG OCR3BH */ /* dup in OCR3AH */ + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 +#define PCINT31_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRTIM3_REG PRR1 + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 +#define CLKO_PORT PORTB +#define CLKO_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0A_PORT PORTB +#define OC0A_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 +#define OC0B_PORT PORTB +#define OC0B_BIT 4 +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 +#define PCINT16_PORT PORTC +#define PCINT16_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 +#define PCINT17_PORT PORTC +#define PCINT17_BIT 1 + +#define TCK_PORT PORTC +#define TCK_BIT 2 +#define PCINT18_PORT PORTC +#define PCINT18_BIT 2 + +#define TMS_PORT PORTC +#define TMS_BIT 3 +#define PCINT19_PORT PORTC +#define PCINT19_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 +#define PCINT20_PORT PORTC +#define PCINT20_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 +#define PCINT21_PORT PORTC +#define PCINT21_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 +#define PCINT22_PORT PORTC +#define PCINT22_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 +#define PCINT23_PORT PORTC +#define PCINT23_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT24_PORT PORTD +#define PCINT24_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT25_PORT PORTD +#define PCINT25_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define RDX1_PORT PORTD +#define RDX1_BIT 2 +#define PCINT26_PORT PORTD +#define PCINT26_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define PCINT27_PORT PORTD +#define PCINT27_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 +#define XCK1_PORT PORTD +#define XCK1_BIT 4 +#define PCINT28_PORT PORTD +#define PCINT28_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define PCINT29_PORT PORTD +#define PCINT29_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 +#define OC2B_PORT PORTD +#define OC2B_BIT 6 +#define PCINT30_PORT PORTD +#define PCINT30_BIT 6 + +#define OC2A_PORT PORTD +#define OC2A_BIT 7 +#define PCINT31_PORT PORTD +#define PCINT31_BIT 7 + + diff --git a/include/aversive/parts/ATmega128A.h b/include/aversive/parts/ATmega128A.h new file mode 100644 index 0000000..ce7bb16 --- /dev/null +++ b/include/aversive/parts/ATmega128A.h @@ -0,0 +1,1327 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_64 3 +#define TIMER2_PRESCALER_DIV_256 4 +#define TIMER2_PRESCALER_DIV_1024 5 +#define TIMER2_PRESCALER_DIV_FALL 6 +#define TIMER2_PRESCALER_DIV_RISE 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 64 +#define TIMER2_PRESCALER_REG_4 256 +#define TIMER2_PRESCALER_REG_5 1024 +#define TIMER2_PRESCALER_REG_6 -1 +#define TIMER2_PRESCALER_REG_7 -2 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* ASSR */ +#define TCR0UB_REG ASSR +#define OCR0UB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR321_REG SFIOR +#define PSR0_REG SFIOR +#define PUD_REG SFIOR +#define TSM_REG SFIOR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* ETIFR */ +#define OCF1C_REG ETIFR +#define OCF3C_REG ETIFR +#define TOV3_REG ETIFR +#define OCF3B_REG ETIFR +#define OCF3A_REG ETIFR +#define ICF3_REG ETIFR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* XDIV */ +#define XDIV0_REG XDIV +#define XDIV1_REG XDIV +#define XDIV2_REG XDIV +#define XDIV3_REG XDIV +#define XDIV4_REG XDIV +#define XDIV5_REG XDIV +#define XDIV6_REG XDIV +#define XDIVEN_REG XDIV + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* ETIMSK */ +#define OCIE1C_REG ETIMSK +#define OCIE3C_REG ETIMSK +#define TOIE3_REG ETIMSK +#define OCIE3B_REG ETIMSK +#define OCIE3A_REG ETIMSK +#define TICIE3_REG ETIMSK + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCN3L0_REG TCNT3L +#define TCN3L1_REG TCNT3L +#define TCN3L2_REG TCNT3L +#define TCN3L3_REG TCNT3L +#define TCN3L4_REG TCNT3L +#define TCN3L5_REG TCNT3L +#define TCN3L6_REG TCNT3L +#define TCN3L7_REG TCNT3L + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define SM2_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADFR_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW11_REG XMCRA +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/ATmega16.h b/include/aversive/parts/ATmega16.h new file mode 100644 index 0000000..e2b16f5 --- /dev/null +++ b/include/aversive/parts/ATmega16.h @@ -0,0 +1,825 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define ACME_REG SFIOR +#define ADTS0_REG SFIOR +#define ADTS1_REG SFIOR +#define ADTS2_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define ISC2_REG MCUCSR +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SM2_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + +#define TMS_PORT PORTC +#define TMS_BIT 2 + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega161.h b/include/aversive/parts/ATmega161.h new file mode 100644 index 0000000..9147951 --- /dev/null +++ b/include/aversive/parts/ATmega161.h @@ -0,0 +1,781 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT2_REG GIMSK +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define CHR91_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDR1IE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define OR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* UBRR1 */ +#define UBRR10_REG UBRR1 +#define UBRR11_REG UBRR1 +#define UBRR12_REG UBRR1 +#define UBRR13_REG UBRR1 +#define UBRR14_REG UBRR1 +#define UBRR15_REG UBRR1 +#define UBRR16_REG UBRR1 +#define UBRR17_REG UBRR1 + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define OCIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE2_REG TIMSK +#define TOIE2_REG TIMSK +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UBRRHI */ +#define UBRRHI00_REG UBRRHI +#define UBRRHI01_REG UBRRHI +#define UBRRHI02_REG UBRRHI +#define UBRRHI03_REG UBRRHI +#define UBRRHI10_REG UBRRHI +#define UBRRHI11_REG UBRRHI +#define UBRRHI12_REG UBRRHI +#define UBRRHI13_REG UBRRHI + +/* EMCUCR */ +#define ISC2_REG EMCUCR +#define SRW11_REG EMCUCR +#define SRW00_REG EMCUCR +#define SRW01_REG EMCUCR +#define SRL0_REG EMCUCR +#define SRL1_REG EMCUCR +#define SRL2_REG EMCUCR +#define SM0_REG EMCUCR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define AINBG_REG ACSR +#define ACD_REG ACSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* UBRR0 */ +#define UBRR00_REG UBRR0 +#define UBRR01_REG UBRR0 +#define UBRR02_REG UBRR0 +#define UBRR03_REG UBRR0 +#define UBRR04_REG UBRR0 +#define UBRR05_REG UBRR0 +#define UBRR06_REG UBRR0 +#define UBRR07_REG UBRR0 + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define CHR90_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDR0IE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define OR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define CTC2_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define PWM2_REG TCCR2 +#define FOC2_REG TCCR2 + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* TIFR */ +#define OCF0_REG TIFR +#define TOV0_REG TIFR +#define OCF2_REG TIFR +#define TOV2_REG TIFR +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define OC0/T0_PORT PORTB +#define OC0/T0_BIT 0 + +#define OC2/T1_PORT PORTB +#define OC2/T1_BIT 1 + +#define RXD1_PORT PORTB +#define RXD1_BIT 2 +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define TXD1_PORT PORTB +#define TXD1_BIT 3 +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define TOSC2_PORT PORTD +#define TOSC2_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + +#define ICP/INT2_PORT PORTE +#define ICP/INT2_BIT 0 + +#define ALE_PORT PORTE +#define ALE_BIT 1 + +#define OC1B_PORT PORTE +#define OC1B_BIT 2 + + diff --git a/include/aversive/parts/ATmega161comp.h b/include/aversive/parts/ATmega161comp.h new file mode 100644 index 0000000..984b508 --- /dev/null +++ b/include/aversive/parts/ATmega161comp.h @@ -0,0 +1,861 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C +#define URSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define PCIE0_REG GICR +#define PCIE1_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define PCIF0_REG GIFR +#define PCIF1_REG GIFR +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define OCIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ +/* #define URSEL0_REG UBRR0H */ /* dup in UCSR0C */ + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PSR310_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define XMM0_REG SFIOR +#define XMM1_REG SFIOR +#define XMM2_REG SFIOR +#define XMBK_REG SFIOR +#define TSM_REG SFIOR + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* EMCUCR */ +#define ISC2_REG EMCUCR +#define SRW11_REG EMCUCR +#define SRW00_REG EMCUCR +#define SRW01_REG EMCUCR +#define SRL0_REG EMCUCR +#define SRL1_REG EMCUCR +#define SRL2_REG EMCUCR +#define SM0_REG EMCUCR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C +/* #define URSEL0_REG UCSR0C */ /* dup in UBRR0H */ + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define SM2_REG MCUCSR +#define JDT_REG MCUCSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* UBRR1L */ +#define UBRR1L0_REG UBRR1L +#define UBRR1L1_REG UBRR1L +#define UBRR1L2_REG UBRR1L +#define UBRR1L3_REG UBRR1L +#define UBRR1L4_REG UBRR1L +#define UBRR1L5_REG UBRR1L +#define UBRR1L6_REG UBRR1L +#define UBRR1L7_REG UBRR1L + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* TIFR */ +#define OCF0_REG TIFR +#define TOV0_REG TIFR +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define OC0/T0_PORT PORTB +#define OC0/T0_BIT 0 + +#define OC2/T1_PORT PORTB +#define OC2/T1_BIT 1 + +#define RXD1_PORT PORTB +#define RXD1_BIT 2 +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define TXD1_PORT PORTB +#define TXD1_BIT 3 +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define TOSC2_PORT PORTD +#define TOSC2_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + +#define ICP/INT2_PORT PORTE +#define ICP/INT2_BIT 0 + +#define ALE_PORT PORTE +#define ALE_BIT 1 + +#define OC1B_PORT PORTE +#define OC1B_BIT 2 + + diff --git a/include/aversive/parts/ATmega162.h b/include/aversive/parts/ATmega162.h new file mode 100644 index 0000000..29bb545 --- /dev/null +++ b/include/aversive/parts/ATmega162.h @@ -0,0 +1,1065 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_16 6 +#define TIMER3_PRESCALER_DIV_32 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 16 +#define TIMER3_PRESCALER_REG_7 32 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE3A_NUM 4 +#define SIG_OUTPUT_COMPARE3B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM3A_NUM 4 +#define PWM3B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C +#define URSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define PCIE0_REG GICR +#define PCIE1_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ETIMSK */ +#define TOIE3_REG ETIMSK +#define OCIE3B_REG ETIMSK +#define OCIE3A_REG ETIMSK +#define TICIE3_REG ETIMSK + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define PCIF0_REG GIFR +#define PCIF1_REG GIFR +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE0_REG TIMSK + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ +/* #define URSEL0_REG UBRR0H */ /* dup in UCSR0C */ + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define FOC3B_REG TCCR3A +#define FOC3A_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* SFIOR */ +#define PSR310_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define XMM0_REG SFIOR +#define XMM1_REG SFIOR +#define XMM2_REG SFIOR +#define XMBK_REG SFIOR +#define TSM_REG SFIOR + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* EMCUCR */ +#define ISC2_REG EMCUCR +#define SRW11_REG EMCUCR +#define SRW00_REG EMCUCR +#define SRW01_REG EMCUCR +#define SRL0_REG EMCUCR +#define SRL1_REG EMCUCR +#define SRL2_REG EMCUCR +#define SM0_REG EMCUCR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C +/* #define URSEL0_REG UCSR0C */ /* dup in UBRR0H */ + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define SM2_REG MCUCSR +#define JDT_REG MCUCSR +#define JTD_REG MCUCSR + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* UBRR1L */ +#define UBRR1L0_REG UBRR1L +#define UBRR1L1_REG UBRR1L +#define UBRR1L2_REG UBRR1L +#define UBRR1L3_REG UBRR1L +#define UBRR1L4_REG UBRR1L +#define UBRR1L5_REG UBRR1L +#define UBRR1L6_REG UBRR1L +#define UBRR1L7_REG UBRR1L + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* TIFR */ +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR +#define OCF0_REG TIFR +#define TOV0_REG TIFR + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* ETIFR */ +#define TOV3_REG ETIFR +#define OCF3B_REG ETIFR +#define OCF3A_REG ETIFR +#define ICF3_REG ETIFR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define OC0_PORT PORTB +#define OC0_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define OC2_PORT PORTB +#define OC2_BIT 1 +#define T1_PORT PORTB +#define T1_BIT 1 + +#define RXD1_PORT PORTB +#define RXD1_BIT 2 +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define TXD1_PORT PORTB +#define TXD1_BIT 3 +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define OC3B_PORT PORTB +#define OC3B_BIT 4 +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 +#define A8_PORT PORTC +#define A8_BIT 0 + +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 +#define A9_PORT PORTC +#define A9_BIT 1 + +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 +#define A10_PORT PORTC +#define A10_BIT 2 + +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 +#define A11_PORT PORTC +#define A11_BIT 3 + +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 +#define A12_PORT PORTC +#define A12_BIT 4 +#define TCK_PORT PORTC +#define TCK_BIT 4 + +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 +#define A13_PORT PORTC +#define A13_BIT 5 +#define TMS_PORT PORTC +#define TMS_BIT 5 + +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 +#define A14_PORT PORTC +#define A14_BIT 6 +#define TDO_PORT PORTC +#define TDO_BIT 6 + +#define PCINT15_PORT PORTC +#define PCINT15_BIT 7 +#define A15_PORT PORTC +#define A15_BIT 7 +#define TDI_PORT PORTC +#define TDI_BIT 7 + +#define TXD0_PORT PORTD +#define TXD0_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define XCK1_PORT PORTD +#define XCK1_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define XCK1_PORT PORTD +#define XCK1_BIT 3 + +#define TOSC1_PORT PORTD +#define TOSC1_BIT 4 +#define XCK0_PORT PORTD +#define XCK0_BIT 4 +#define OC3A_PORT PORTD +#define OC3A_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define TOSC2_PORT PORTD +#define TOSC2_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + +#define ICP1_PORT PORTE +#define ICP1_BIT 0 +#define INT2_PORT PORTE +#define INT2_BIT 0 + +#define ALE_PORT PORTE +#define ALE_BIT 1 + +#define OC1B_PORT PORTE +#define OC1B_BIT 2 + + diff --git a/include/aversive/parts/ATmega163.h b/include/aversive/parts/ATmega163.h new file mode 100644 index 0000000..bf32886 --- /dev/null +++ b/include/aversive/parts/ATmega163.h @@ -0,0 +1,763 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE2_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM2_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define PWM10_REG TCCR1A +#define PWM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define OR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define CHR9_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define ACME_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UBRRHI */ +#define UBRRHI0_REG UBRRHI +#define UBRRHI1_REG UBRRHI +#define UBRRHI2_REG UBRRHI +#define UBRRHI3_REG UBRRHI + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define ASRE_REG SPMCR +#define ASB_REG SPMCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* UBRR */ +#define UBRR0_REG UBRR +#define UBRR1_REG UBRR +#define UBRR2_REG UBRR +#define UBRR3_REG UBRR +#define UBRR4_REG UBRR +#define UBRR5_REG UBRR +#define UBRR6_REG UBRR +#define UBRR7_REG UBRR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega164P.h b/include/aversive/parts/ATmega164P.h new file mode 100644 index 0000000..78f09a9 --- /dev/null +++ b/include/aversive/parts/ATmega164P.h @@ -0,0 +1,1163 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPCR0 */ +#define SPR00_REG SPCR0 +#define SPR10_REG SPCR0 +#define CPHA0_REG SPCR0 +#define CPOL0_REG SPCR0 +#define MSTR0_REG SPCR0 +#define DORD0_REG SPCR0 +#define SPE0_REG SPCR0 +#define SPIE0_REG SPCR0 + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* SPDR0 */ +#define SPDRB0_REG SPDR0 +#define SPDRB1_REG SPDR0 +#define SPDRB2_REG SPDR0 +#define SPDRB3_REG SPDR0 +#define SPDRB4_REG SPDR0 +#define SPDRB5_REG SPDR0 +#define SPDRB6_REG SPDR0 +#define SPDRB7_REG SPDR0 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* SPSR0 */ +#define SPI2X0_REG SPSR0 +#define WCOL0_REG SPSR0 +#define SPIF0_REG SPSR0 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRUSART1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 +#define PCINT31_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 +#define CLKO_PORT PORTB +#define CLKO_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0A_PORT PORTB +#define OC0A_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 +#define OC0B_PORT PORTB +#define OC0B_BIT 4 +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 +#define PCINT16_PORT PORTC +#define PCINT16_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 +#define PCINT17_PORT PORTC +#define PCINT17_BIT 1 + +#define TCK_PORT PORTC +#define TCK_BIT 2 +#define PCINT18_PORT PORTC +#define PCINT18_BIT 2 + +#define TMS_PORT PORTC +#define TMS_BIT 3 +#define PCINT19_PORT PORTC +#define PCINT19_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 +#define PCINT20_PORT PORTC +#define PCINT20_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 +#define PCINT21_PORT PORTC +#define PCINT21_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 +#define PCINT22_PORT PORTC +#define PCINT22_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 +#define PCINT23_PORT PORTC +#define PCINT23_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT24_PORT PORTD +#define PCINT24_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT25_PORT PORTD +#define PCINT25_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT26_PORT PORTD +#define PCINT26_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define PCINT27_PORT PORTD +#define PCINT27_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 +#define PCINT28_PORT PORTD +#define PCINT28_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define PCINT29_PORT PORTD +#define PCINT29_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 +#define OC2B_PORT PORTD +#define OC2B_BIT 6 +#define PCINT30_PORT PORTD +#define PCINT30_BIT 6 + +#define OC2A_PORT PORTD +#define OC2A_BIT 7 +#define PCINT31_PORT PORTD +#define PCINT31_BIT 7 + + diff --git a/include/aversive/parts/ATmega165.h b/include/aversive/parts/ATmega165.h new file mode 100644 index 0000000..5e29de8 --- /dev/null +++ b/include/aversive/parts/ATmega165.h @@ -0,0 +1,892 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega165P.h b/include/aversive/parts/ATmega165P.h new file mode 100644 index 0000000..5e29de8 --- /dev/null +++ b/include/aversive/parts/ATmega165P.h @@ -0,0 +1,892 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega168.h b/include/aversive/parts/ATmega168.h new file mode 100644 index 0000000..cb95de2 --- /dev/null +++ b/include/aversive/parts/ATmega168.h @@ -0,0 +1,995 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega168P.h b/include/aversive/parts/ATmega168P.h new file mode 100644 index 0000000..d9de6d0 --- /dev/null +++ b/include/aversive/parts/ATmega168P.h @@ -0,0 +1,997 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega168PA.h b/include/aversive/parts/ATmega168PA.h new file mode 100644 index 0000000..d9de6d0 --- /dev/null +++ b/include/aversive/parts/ATmega168PA.h @@ -0,0 +1,997 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega169.h b/include/aversive/parts/ATmega169.h new file mode 100644 index 0000000..87038dd --- /dev/null +++ b/include/aversive/parts/ATmega169.h @@ -0,0 +1,1052 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega169P.h b/include/aversive/parts/ATmega169P.h new file mode 100644 index 0000000..6cacbff --- /dev/null +++ b/include/aversive/parts/ATmega169P.h @@ -0,0 +1,1058 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG +#define PORTG5_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG +#define DDG5_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDCCD_REG LCDCRA +#define LCDBD_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDMDT_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega16A.h b/include/aversive/parts/ATmega16A.h new file mode 100644 index 0000000..e2b16f5 --- /dev/null +++ b/include/aversive/parts/ATmega16A.h @@ -0,0 +1,825 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define ACME_REG SFIOR +#define ADTS0_REG SFIOR +#define ADTS1_REG SFIOR +#define ADTS2_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define ISC2_REG MCUCSR +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SM2_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + +#define TMS_PORT PORTC +#define TMS_BIT 2 + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega16HVA.h b/include/aversive/parts/ATmega16HVA.h new file mode 100644 index 0000000..cf64578 --- /dev/null +++ b/include/aversive/parts/ATmega16HVA.h @@ -0,0 +1,683 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ + + +/* prescalers timer 1 */ + + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CADAC2 */ +#define CADAC16_REG CADAC2 +#define CADAC17_REG CADAC2 +#define CADAC18_REG CADAC2 +#define CADAC19_REG CADAC2 +#define CADAC20_REG CADAC2 +#define CADAC21_REG CADAC2 +#define CADAC22_REG CADAC2 +#define CADAC23_REG CADAC2 + +/* CADAC3 */ +#define CADAC24_REG CADAC3 +#define CADAC25_REG CADAC3 +#define CADAC26_REG CADAC3 +#define CADAC27_REG CADAC3 +#define CADAC28_REG CADAC3 +#define CADAC29_REG CADAC3 +#define CADAC30_REG CADAC3 +#define CADAC31_REG CADAC3 + +/* CADAC0 */ +#define CADAC00_REG CADAC0 +#define CADAC01_REG CADAC0 +#define CADAC02_REG CADAC0 +#define CADAC03_REG CADAC0 +#define CADAC04_REG CADAC0 +#define CADAC05_REG CADAC0 +#define CADAC06_REG CADAC0 +#define CADAC07_REG CADAC0 + +/* CADAC1 */ +#define CADAC08_REG CADAC1 +#define CADAC09_REG CADAC1 +#define CADAC10_REG CADAC1 +#define CADAC11_REG CADAC1 +#define CADAC12_REG CADAC1 +#define CADAC13_REG CADAC1 +#define CADAC14_REG CADAC1 +#define CADAC15_REG CADAC1 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA + +/* BPIMSK */ +#define CHCIE_REG BPIMSK +#define DHCIE_REG BPIMSK +#define COCIE_REG BPIMSK +#define DOCIE_REG BPIMSK +#define SCIE_REG BPIMSK + +/* DIDR0 */ +#define PA0DID_REG DIDR0 +#define PA1DID_REG DIDR0 + +/* TCNT0H */ +#define TCNT0H0_REG TCNT0H +#define TCNT0H1_REG TCNT0H +#define TCNT0H2_REG TCNT0H +#define TCNT0H3_REG TCNT0H +#define TCNT0H4_REG TCNT0H +#define TCNT0H5_REG TCNT0H +#define TCNT0H6_REG TCNT0H +#define TCNT0H7_REG TCNT0H + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPCE_REG CLKPR + +/* BPCR */ +#define CHCD_REG BPCR +#define DHCD_REG BPCR +#define COCD_REG BPCR +#define DOCD_REG BPCR +#define SCD_REG BPCR + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* BPSCTR */ +#define SCPT0_REG BPSCTR +#define SCPT1_REG BPSCTR +#define SCPT2_REG BPSCTR +#define SCPT3_REG BPSCTR +#define SCPT4_REG BPSCTR +#define SCPT5_REG BPSCTR +#define SCPT6_REG BPSCTR + +/* MCUCR */ +#define PUD_REG MCUCR +#define CKOE_REG MCUCR + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define ICS1_REG TCCR1A +#define ICES1_REG TCCR1A +#define ICNC1_REG TCCR1A +#define ICEN1_REG TCCR1A +#define TCW1_REG TCCR1A + +/* BPHCTR */ +#define HCPT0_REG BPHCTR +#define HCPT1_REG BPHCTR +#define HCPT2_REG BPHCTR +#define HCPT3_REG BPHCTR +#define HCPT4_REG BPHCTR +#define HCPT5_REG BPHCTR + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* BGCRR */ +#define BGCR0_REG BGCRR +#define BGCR1_REG BGCRR +#define BGCR2_REG BGCRR +#define BGCR3_REG BGCRR +#define BGCR4_REG BGCRR +#define BGCR5_REG BGCRR +#define BGCR6_REG BGCRR +#define BGCR7_REG BGCRR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA + +/* BPCHCD */ +#define CHCDL0_REG BPCHCD +#define CHCDL1_REG BPCHCD +#define CHCDL2_REG BPCHCD +#define CHCDL3_REG BPCHCD +#define CHCDL4_REG BPCHCD +#define CHCDL5_REG BPCHCD +#define CHCDL6_REG BPCHCD +#define CHCDL7_REG BPCHCD + +/* PRR0 */ +#define PRVADC_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRSPI_REG PRR0 +#define PRVRM_REG PRR0 + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ROCR */ +#define ROCWIE_REG ROCR +#define ROCWIF_REG ROCR +#define ROCS_REG ROCR + +/* OCR0B */ +#define OCR0B0_REG OCR0B +#define OCR0B1_REG OCR0B +#define OCR0B2_REG OCR0B +#define OCR0B3_REG OCR0B +#define OCR0B4_REG OCR0B +#define OCR0B5_REG OCR0B +#define OCR0B6_REG OCR0B +#define OCR0B7_REG OCR0B + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* CADICH */ +#define CADICH0_REG CADICH +#define CADICH1_REG CADICH +#define CADICH2_REG CADICH +#define CADICH3_REG CADICH +#define CADICH4_REG CADICH +#define CADICH5_REG CADICH +#define CADICH6_REG CADICH +#define CADICH7_REG CADICH + +/* FCSR */ +#define CFE_REG FCSR +#define DFE_REG FCSR +#define CPS_REG FCSR +#define DUVRD_REG FCSR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* CADCSRB */ +#define CADICIF_REG CADCSRB +#define CADRCIF_REG CADCSRB +#define CADACIF_REG CADCSRB +#define CADICIE_REG CADCSRB +#define CADRCIE_REG CADCSRB +#define CADACIE_REG CADCSRB + +/* CADICL */ +#define CADICL0_REG CADICL +#define CADICL1_REG CADICL +#define CADICL2_REG CADICL +#define CADICL3_REG CADICL +#define CADICL4_REG CADICL +#define CADICL5_REG CADICL +#define CADICL6_REG CADICL +#define CADICL7_REG CADICL + +/* BPCOCD */ +#define COCDL0_REG BPCOCD +#define COCDL1_REG BPCOCD +#define COCDL2_REG BPCOCD +#define COCDL3_REG BPCOCD +#define COCDL4_REG BPCOCD +#define COCDL5_REG BPCOCD +#define COCDL6_REG BPCOCD +#define COCDL7_REG BPCOCD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* BPPLR */ +#define BPPL_REG BPPLR +#define BPPLE_REG BPPLR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BODRF_REG MCUSR +#define WDRF_REG MCUSR +#define OCDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR +#define EEAR7_REG EEAR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR +#define SIGRD_REG SPMCSR + +/* CADCSRA */ +#define CADSE_REG CADCSRA +#define CADSI0_REG CADCSRA +#define CADSI1_REG CADCSRA +#define CADAS0_REG CADCSRA +#define CADAS1_REG CADCSRA +#define CADUB_REG CADCSRA +#define CADPOL_REG CADCSRA +#define CADEN_REG CADCSRA + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 +#define ICF0_REG TIFR0 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA + +/* BPSCD */ +#define SCDL0_REG BPSCD +#define SCDL1_REG BPSCD +#define SCDL2_REG BPSCD +#define SCDL3_REG BPSCD +#define SCDL4_REG BPSCD +#define SCDL5_REG BPSCD +#define SCDL6_REG BPSCD +#define SCDL7_REG BPSCD + +/* OSICSR */ +#define OSIEN_REG OSICSR +#define OSIST_REG OSICSR +#define OSISEL0_REG OSICSR + +/* CADRC */ +#define CADRC0_REG CADRC +#define CADRC1_REG CADRC +#define CADRC2_REG CADRC +#define CADRC3_REG CADRC +#define CADRC4_REG CADRC +#define CADRC5_REG CADRC +#define CADRC6_REG CADRC +#define CADRC7_REG CADRC + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 +#define ICIE0_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B + +/* BGCCR */ +#define BGCC0_REG BGCCR +#define BGCC1_REG BGCCR +#define BGCC2_REG BGCCR +#define BGCC3_REG BGCCR +#define BGCC4_REG BGCCR +#define BGCC5_REG BGCCR +#define BGD_REG BGCCR + +/* VADMUX */ +#define VADMUX0_REG VADMUX +#define VADMUX1_REG VADMUX +#define VADMUX2_REG VADMUX +#define VADMUX3_REG VADMUX + +/* VADCH */ +#define VADC8_REG VADCH +#define VADC9_REG VADCH +#define VADC10_REG VADCH +#define VADC11_REG VADCH + +/* BPIFR */ +#define CHCIF_REG BPIFR +#define DHCIF_REG BPIFR +#define COCIF_REG BPIFR +#define DOCIF_REG BPIFR +#define SCIF_REG BPIFR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* BPDHCD */ +#define DHCDL0_REG BPDHCD +#define DHCDL1_REG BPDHCD +#define DHCDL2_REG BPDHCD +#define DHCDL3_REG BPDHCD +#define DHCDL4_REG BPDHCD +#define DHCDL5_REG BPDHCD +#define DHCDL6_REG BPDHCD +#define DHCDL7_REG BPDHCD + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* PINC */ +#define PINC0_REG PINC + +/* VADCSR */ +#define VADCCIE_REG VADCSR +#define VADCCIF_REG VADCSR +#define VADSC_REG VADCSR +#define VADEN_REG VADCSR + +/* FOSCCAL */ +#define FCAL0_REG FOSCCAL +#define FCAL1_REG FOSCCAL +#define FCAL2_REG FOSCCAL +#define FCAL3_REG FOSCCAL +#define FCAL4_REG FOSCCAL +#define FCAL5_REG FOSCCAL +#define FCAL6_REG FOSCCAL +#define FCAL7_REG FOSCCAL + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define ICS0_REG TCCR0A +#define ICES0_REG TCCR0A +#define ICNC0_REG TCCR0A +#define ICEN0_REG TCCR0A +#define TCW0_REG TCCR0A + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB + +/* TCNT0L */ +#define TCNT0L0_REG TCNT0L +#define TCNT0L1_REG TCNT0L +#define TCNT0L2_REG TCNT0L +#define TCNT0L3_REG TCNT0L +#define TCNT0L4_REG TCNT0L +#define TCNT0L5_REG TCNT0L +#define TCNT0L6_REG TCNT0L +#define TCNT0L7_REG TCNT0L + +/* BPOCTR */ +#define OCPT0_REG BPOCTR +#define OCPT1_REG BPOCTR +#define OCPT2_REG BPOCTR +#define OCPT3_REG BPOCTR +#define OCPT4_REG BPOCTR +#define OCPT5_REG BPOCTR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* BPDOCD */ +#define DOCDL0_REG BPDOCD +#define DOCDL1_REG BPDOCD +#define DOCDL2_REG BPDOCD +#define DOCDL3_REG BPDOCD +#define DOCDL4_REG BPDOCD +#define DOCDL5_REG BPDOCD +#define DOCDL6_REG BPDOCD +#define DOCDL7_REG BPDOCD + +/* VADCL */ +#define VADC0_REG VADCL +#define VADC1_REG VADCL +#define VADC2_REG VADCL +#define VADC3_REG VADCL +#define VADC4_REG VADCL +#define VADC5_REG VADCL +#define VADC6_REG VADCL +#define VADC7_REG VADCL + +/* pins mapping */ + + + + + + + + + + + diff --git a/include/aversive/parts/ATmega16U4.h b/include/aversive/parts/ATmega16U4.h new file mode 100644 index 0000000..37b04dc --- /dev/null +++ b/include/aversive/parts/ATmega16U4.h @@ -0,0 +1,1317 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ + + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW3_NUM 2 +#define SIG_OVERFLOW4_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE4_NUM 8 +#define SIG_OUTPUT_COMPARE4A_NUM 9 +#define SIG_OUTPUT_COMPARE4B_NUM 10 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 11 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM4_NUM 8 +#define PWM4A_NUM 9 +#define PWM4B_NUM 10 +#define PWM_TOTAL_NUM 11 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* UECFG1X */ +#define ALLOC_REG UECFG1X +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE2_REG PORTE +#define PORTE6_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define DAT0_REG UEDATX +#define DAT1_REG UEDATX +#define DAT2_REG UEDATX +#define DAT3_REG UEDATX +#define DAT4_REG UEDATX +#define DAT5_REG UEDATX +#define DAT6_REG UEDATX +#define DAT7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* CLKSEL1 */ +#define EXCKSEL0_REG CLKSEL1 +#define EXCKSEL1_REG CLKSEL1 +#define EXCKSEL2_REG CLKSEL1 +#define EXCKSEL3_REG CLKSEL1 +#define RCCKSEL0_REG CLKSEL1 +#define RCCKSEL1_REG CLKSEL1 +#define RCCKSEL2_REG CLKSEL1 +#define RCCKSEL3_REG CLKSEL1 + +/* CLKSEL0 */ +#define CLKS_REG CLKSEL0 +#define EXTE_REG CLKSEL0 +#define RCE_REG CLKSEL0 +#define EXSUT0_REG CLKSEL0 +#define EXSUT1_REG CLKSEL0 +#define RCSUT0_REG CLKSEL0 +#define RCSUT1_REG CLKSEL0 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* OCR4A */ +#define OCR4A0_REG OCR4A +#define OCR4A1_REG OCR4A +#define OCR4A2_REG OCR4A +#define OCR4A3_REG OCR4A +#define OCR4A4_REG OCR4A +#define OCR4A5_REG OCR4A +#define OCR4A6_REG OCR4A +#define OCR4A7_REG OCR4A + +/* OCR4C */ +#define OCR4C0_REG OCR4C +#define OCR4C1_REG OCR4C +#define OCR4C2_REG OCR4C +#define OCR4C3_REG OCR4C +#define OCR4C4_REG OCR4C +#define OCR4C5_REG OCR4C +#define OCR4C6_REG OCR4C +#define OCR4C7_REG OCR4C + +/* OCR4B */ +#define OCR4B0_REG OCR4B +#define OCR4B1_REG OCR4B +#define OCR4B2_REG OCR4B +#define OCR4B3_REG OCR4B +#define OCR4B4_REG OCR4B +#define OCR4B5_REG OCR4B +#define OCR4B6_REG OCR4B +#define OCR4B7_REG OCR4B + +/* OCR4D */ +#define OCR4D0_REG OCR4D +#define OCR4D1_REG OCR4D +#define OCR4D2_REG OCR4D +#define OCR4D3_REG OCR4D +#define OCR4D4_REG OCR4D +#define OCR4D5_REG OCR4D +#define OCR4D6_REG OCR4D +#define OCR4D7_REG OCR4D + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* RCCTRL */ +#define RCFREQ_REG RCCTRL + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON +#define RSTCPU_REG UDCON + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCNT4 */ +#define TC40_REG TCNT4 +#define TC41_REG TCNT4 +#define TC42_REG TCNT4 +#define TC43_REG TCNT4 +#define TC44_REG TCNT4 +#define TC45_REG TCNT4 +#define TC46_REG TCNT4 +#define TC47_REG TCNT4 + +/* TC4H */ +#define TC48_REG TC4H +#define TC49_REG TC4H +#define TC410_REG TC4H + +/* UHWCON */ +#define UVREGE_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4D_REG TIFR4 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* UEBCLX */ +#define BYCT0_REG UEBCLX +#define BYCT1_REG UEBCLX +#define BYCT2_REG UEBCLX +#define BYCT3_REG UEBCLX +#define BYCT4_REG UEBCLX +#define BYCT5_REG UEBCLX +#define BYCT6_REG UEBCLX +#define BYCT7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +#define RWAL_REG UEINTX +#define NAKINI_REG UEINTX +#define FIFOCON_REG UEINTX + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USBCON */ +#define VBUSTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define USBE_REG USBCON + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* UECONX */ +#define EPEN_REG UECONX +#define RSTDT_REG UECONX +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* PLLFRQ */ +#define PDIV0_REG PLLFRQ +#define PDIV1_REG PLLFRQ +#define PDIV2_REG PLLFRQ +#define PDIV3_REG PLLFRQ +#define PLLTM0_REG PLLFRQ +#define PLLTM1_REG PLLFRQ +#define PLLUSB_REG PLLFRQ +#define PINMUX_REG PLLFRQ + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* USBSTA */ +#define VBUS_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +#define FLERRE_REG UEIENX + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define FNUM0_REG UDFNUML +#define FNUM1_REG UDFNUML +#define FNUM2_REG UDFNUML +#define FNUM3_REG UDFNUML +#define FNUM4_REG UDFNUML +#define FNUM5_REG UDFNUML +#define FNUM6_REG UDFNUML +#define FNUM7_REG UDFNUML + +/* UDFNUMH */ +#define FNUM8_REG UDFNUMH +#define FNUM9_REG UDFNUMH +#define FNUM10_REG UDFNUMH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define MUX5_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE2_REG DDRE +#define DDE6_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +#define DTSEQ0_REG UESTA0X +#define DTSEQ1_REG UESTA0X +#define UNDERFI_REG UESTA0X +#define OVERFI_REG UESTA0X +#define CFGOK_REG UESTA0X + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* CLKSTA */ +#define EXTON_REG CLKSTA +#define RCON_REG CLKSTA + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4D_REG TIMSK4 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define CS43_REG TCCR4B +#define DTPS40_REG TCCR4B +#define DTPS41_REG TCCR4B +#define PSR4_REG TCCR4B +#define PWM4X_REG TCCR4B + +/* TCCR4C */ +#define PWM4D_REG TCCR4C +#define FOC4D_REG TCCR4C +#define COM4D0_REG TCCR4C +#define COM4D1_REG TCCR4C +#define COM4B0S_REG TCCR4C +#define COM4B1S_REG TCCR4C +#define COM4A0S_REG TCCR4C +#define COM4A1S_REG TCCR4C + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PINDIV_REG PLLCSR + +/* TCCR4A */ +#define PWM4B_REG TCCR4A +#define PWM4A_REG TCCR4A +#define FOC4B_REG TCCR4A +#define FOC4A_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* TCCR4D */ +#define WGM40_REG TCCR4D +#define WGM41_REG TCCR4D +#define FPF4_REG TCCR4D +#define FPAC4_REG TCCR4D +#define FPES4_REG TCCR4D +#define FPNC4_REG TCCR4D +#define FPEN4_REG TCCR4D +#define FPIE4_REG TCCR4D + +/* TCCR4E */ +#define OC4OE0_REG TCCR4E +#define OC4OE1_REG TCCR4E +#define OC4OE2_REG TCCR4E +#define OC4OE3_REG TCCR4E +#define OC4OE4_REG TCCR4E +#define OC4OE5_REG TCCR4E +#define ENHC4_REG TCCR4E +#define TLOCK4_REG TCCR4E + +/* PINC */ +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE2_REG PINE +#define PINE6_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* DT4 */ +#define DT4L0_REG DT4 +#define DT4L1_REG DT4 +#define DT4L2_REG DT4 +#define DT4L3_REG DT4 +#define DT4L4_REG DT4 +#define DT4L5_REG DT4 +#define DT4L6_REG DT4 +#define DT4L7_REG DT4 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega2560.h b/include/aversive/parts/ATmega2560.h new file mode 100644 index 0000000..02efe04 --- /dev/null +++ b/include/aversive/parts/ATmega2560.h @@ -0,0 +1,2209 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ +#define TIMER4_PRESCALER_DIV_0 0 +#define TIMER4_PRESCALER_DIV_1 1 +#define TIMER4_PRESCALER_DIV_8 2 +#define TIMER4_PRESCALER_DIV_64 3 +#define TIMER4_PRESCALER_DIV_256 4 +#define TIMER4_PRESCALER_DIV_1024 5 +#define TIMER4_PRESCALER_DIV_FALL 6 +#define TIMER4_PRESCALER_DIV_RISE 7 + +#define TIMER4_PRESCALER_REG_0 0 +#define TIMER4_PRESCALER_REG_1 1 +#define TIMER4_PRESCALER_REG_2 8 +#define TIMER4_PRESCALER_REG_3 64 +#define TIMER4_PRESCALER_REG_4 256 +#define TIMER4_PRESCALER_REG_5 1024 +#define TIMER4_PRESCALER_REG_6 -1 +#define TIMER4_PRESCALER_REG_7 -2 + +/* prescalers timer 5 */ +#define TIMER5_PRESCALER_DIV_0 0 +#define TIMER5_PRESCALER_DIV_1 1 +#define TIMER5_PRESCALER_DIV_8 2 +#define TIMER5_PRESCALER_DIV_64 3 +#define TIMER5_PRESCALER_DIV_256 4 +#define TIMER5_PRESCALER_DIV_1024 5 +#define TIMER5_PRESCALER_DIV_FALL 6 +#define TIMER5_PRESCALER_DIV_RISE 7 + +#define TIMER5_PRESCALER_REG_0 0 +#define TIMER5_PRESCALER_REG_1 1 +#define TIMER5_PRESCALER_REG_2 8 +#define TIMER5_PRESCALER_REG_3 64 +#define TIMER5_PRESCALER_REG_4 256 +#define TIMER5_PRESCALER_REG_5 1024 +#define TIMER5_PRESCALER_REG_6 -1 +#define TIMER5_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE +#define TIMER4C_AVAILABLE +#define TIMER5_AVAILABLE +#define TIMER5A_AVAILABLE +#define TIMER5B_AVAILABLE +#define TIMER5C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW4_NUM 4 +#define SIG_OVERFLOW5_NUM 5 +#define SIG_OVERFLOW_TOTAL_NUM 6 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE4A_NUM 10 +#define SIG_OUTPUT_COMPARE4B_NUM 11 +#define SIG_OUTPUT_COMPARE4C_NUM 12 +#define SIG_OUTPUT_COMPARE5A_NUM 13 +#define SIG_OUTPUT_COMPARE5B_NUM 14 +#define SIG_OUTPUT_COMPARE5C_NUM 15 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM4A_NUM 10 +#define PWM4B_NUM 11 +#define PWM4C_NUM 12 +#define PWM5A_NUM 13 +#define PWM5B_NUM 14 +#define PWM5C_NUM 15 +#define PWM_TOTAL_NUM 16 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE4_NUM 2 +#define SIG_INPUT_CAPTURE5_NUM 3 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 4 + + +/* UBRR3H */ +/* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ + +/* UBRR3L */ +/* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UCSR3A */ +#define MPCM3_REG UCSR3A +#define U2X3_REG UCSR3A +#define UPE3_REG UCSR3A +#define DOR3_REG UCSR3A +#define FE3_REG UCSR3A +#define UDRE3_REG UCSR3A +#define TXC3_REG UCSR3A +#define RXC3_REG UCSR3A + +/* UCSR3B */ +#define TXB83_REG UCSR3B +#define RXB83_REG UCSR3B +#define UCSZ32_REG UCSR3B +#define TXEN3_REG UCSR3B +#define RXEN3_REG UCSR3B +#define UDRIE3_REG UCSR3B +#define TXCIE3_REG UCSR3B +#define RXCIE3_REG UCSR3B + +/* UCSR3C */ +#define UCPOL3_REG UCSR3C +#define UCSZ30_REG UCSR3C +#define UCSZ31_REG UCSR3C +#define USBS3_REG UCSR3C +#define UPM30_REG UCSR3C +#define UPM31_REG UCSR3C +#define UMSEL30_REG UCSR3C +#define UMSEL31_REG UCSR3C + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ +#define RAMPZ1_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* PORTL */ +#define PORTL0_REG PORTL +#define PORTL1_REG PORTL +#define PORTL2_REG PORTL +#define PORTL3_REG PORTL +#define PORTL4_REG PORTL +#define PORTL5_REG PORTL +#define PORTL6_REG PORTL +#define PORTL7_REG PORTL + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ +#define PORTJ7_REG PORTJ + +/* PORTK */ +#define PORTK0_REG PORTK +#define PORTK1_REG PORTK +#define PORTK2_REG PORTK +#define PORTK3_REG PORTK +#define PORTK4_REG PORTK +#define PORTK5_REG PORTK +#define PORTK6_REG PORTK +#define PORTK7_REG PORTK + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG +#define PORTG5_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* UDR3 */ +#define UDR3_0_REG UDR3 +#define UDR3_1_REG UDR3 +#define UDR3_2_REG UDR3 +#define UDR3_3_REG UDR3 +#define UDR3_4_REG UDR3 +#define UDR3_5_REG UDR3 +#define UDR3_6_REG UDR3 +#define UDR3_7_REG UDR3 + +/* UDR2 */ +#define UDR2_0_REG UDR2 +#define UDR2_1_REG UDR2 +#define UDR2_2_REG UDR2 +#define UDR2_3_REG UDR2 +#define UDR2_4_REG UDR2 +#define UDR2_5_REG UDR2 +#define UDR2_6_REG UDR2 +#define UDR2_7_REG UDR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 +#define ADC14D_REG DIDR2 +#define ADC15D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ +#define DDJ7_REG DDRJ + +/* DDRK */ +#define DDK0_REG DDRK +#define DDK1_REG DDRK +#define DDK2_REG DDRK +#define DDK3_REG DDRK +#define DDK4_REG DDRK +#define DDK5_REG DDRK +#define DDK6_REG DDRK +#define DDK7_REG DDRK + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRL */ +#define DDL0_REG DDRL +#define DDL1_REG DDRL +#define DDL2_REG DDRL +#define DDL3_REG DDRL +#define DDL4_REG DDRL +#define DDL5_REG DDRL +#define DDL6_REG DDRL +#define DDL7_REG DDRL + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG +#define DDG5_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCNT5H */ +#define TCNT5H0_REG TCNT5H +#define TCNT5H1_REG TCNT5H +#define TCNT5H2_REG TCNT5H +#define TCNT5H3_REG TCNT5H +#define TCNT5H4_REG TCNT5H +#define TCNT5H5_REG TCNT5H +#define TCNT5H6_REG TCNT5H +#define TCNT5H7_REG TCNT5H + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* TCNT5L */ +#define TCNT5L0_REG TCNT5L +#define TCNT5L1_REG TCNT5L +#define TCNT5L2_REG TCNT5L +#define TCNT5L3_REG TCNT5L +#define TCNT5L4_REG TCNT5L +#define TCNT5L5_REG TCNT5L +#define TCNT5L6_REG TCNT5L +#define TCNT5L7_REG TCNT5L + +/* UBRR2H */ +/* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ + +/* UBRR2L */ +/* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UCSR2B */ +#define TXB82_REG UCSR2B +#define RXB82_REG UCSR2B +#define UCSZ22_REG UCSR2B +#define TXEN2_REG UCSR2B +#define RXEN2_REG UCSR2B +#define UDRIE2_REG UCSR2B +#define TXCIE2_REG UCSR2B +#define RXCIE2_REG UCSR2B + +/* UCSR2A */ +#define MPCM2_REG UCSR2A +#define U2X2_REG UCSR2A +#define UPE2_REG UCSR2A +#define DOR2_REG UCSR2A +#define FE2_REG UCSR2A +#define UDRE2_REG UCSR2A +#define TXC2_REG UCSR2A +#define RXC2_REG UCSR2A + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UCSR2C */ +#define UCPOL2_REG UCSR2C +#define UCSZ20_REG UCSR2C +#define UCSZ21_REG UCSR2C +#define USBS2_REG UCSR2C +#define UPM20_REG UCSR2C +#define UPM21_REG UCSR2C +#define UMSEL20_REG UCSR2C +#define UMSEL21_REG UCSR2C + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4C_REG TIFR4 +#define ICF4_REG TIFR4 + +/* TIFR5 */ +#define TOV5_REG TIFR5 +#define OCF5A_REG TIFR5 +#define OCF5B_REG TIFR5 +#define OCF5C_REG TIFR5 +#define ICF5_REG TIFR5 + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* OCR4AH */ +#define OCR4AH0_REG OCR4AH +#define OCR4AH1_REG OCR4AH +#define OCR4AH2_REG OCR4AH +#define OCR4AH3_REG OCR4AH +#define OCR4AH4_REG OCR4AH +#define OCR4AH5_REG OCR4AH +#define OCR4AH6_REG OCR4AH +#define OCR4AH7_REG OCR4AH + +/* OCR5CH */ +#define OCR5CH0_REG OCR5CH +#define OCR5CH1_REG OCR5CH +#define OCR5CH2_REG OCR5CH +#define OCR5CH3_REG OCR5CH +#define OCR5CH4_REG OCR5CH +#define OCR5CH5_REG OCR5CH +#define OCR5CH6_REG OCR5CH +#define OCR5CH7_REG OCR5CH + +/* OCR4AL */ +#define OCR4AL0_REG OCR4AL +#define OCR4AL1_REG OCR4AL +#define OCR4AL2_REG OCR4AL +#define OCR4AL3_REG OCR4AL +#define OCR4AL4_REG OCR4AL +#define OCR4AL5_REG OCR4AL +#define OCR4AL6_REG OCR4AL +#define OCR4AL7_REG OCR4AL + +/* OCR5CL */ +#define OCR5CL0_REG OCR5CL +#define OCR5CL1_REG OCR5CL +#define OCR5CL2_REG OCR5CL +#define OCR5CL3_REG OCR5CL +#define OCR5CL4_REG OCR5CL +#define OCR5CL5_REG OCR5CL +#define OCR5CL6_REG OCR5CL +#define OCR5CL7_REG OCR5CL + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* ICR5L */ +#define ICR5L0_REG ICR5L +#define ICR5L1_REG ICR5L +#define ICR5L2_REG ICR5L +#define ICR5L3_REG ICR5L +#define ICR5L4_REG ICR5L +#define ICR5L5_REG ICR5L +#define ICR5L6_REG ICR5L +#define ICR5L7_REG ICR5L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ICR5H */ +#define ICR5H0_REG ICR5H +#define ICR5H1_REG ICR5H +#define ICR5H2_REG ICR5H +#define ICR5H3_REG ICR5H +#define ICR5H4_REG ICR5H +#define ICR5H5_REG ICR5H +#define ICR5H6_REG ICR5H +#define ICR5H7_REG ICR5H + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* PINK */ +#define PINK0_REG PINK +#define PINK1_REG PINK +#define PINK2_REG PINK +#define PINK3_REG PINK +#define PINK4_REG PINK +#define PINK5_REG PINK +#define PINK6_REG PINK +#define PINK7_REG PINK + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ +#define PINJ7_REG PINJ + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* ICR4H */ +#define ICR4H0_REG ICR4H +#define ICR4H1_REG ICR4H +#define ICR4H2_REG ICR4H +#define ICR4H3_REG ICR4H +#define ICR4H4_REG ICR4H +#define ICR4H5_REG ICR4H +#define ICR4H6_REG ICR4H +#define ICR4H7_REG ICR4H + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* ICR4L */ +#define ICR4L0_REG ICR4L +#define ICR4L1_REG ICR4L +#define ICR4L2_REG ICR4L +#define ICR4L3_REG ICR4L +#define ICR4L4_REG ICR4L +#define ICR4L5_REG ICR4L +#define ICR4L6_REG ICR4L +#define ICR4L7_REG ICR4L + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* TCNT4L */ +#define TCNT4L0_REG TCNT4L +#define TCNT4L1_REG TCNT4L +#define TCNT4L2_REG TCNT4L +#define TCNT4L3_REG TCNT4L +#define TCNT4L4_REG TCNT4L +#define TCNT4L5_REG TCNT4L +#define TCNT4L6_REG TCNT4L +#define TCNT4L7_REG TCNT4L + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* TCNT4H */ +#define TCNT4H0_REG TCNT4H +#define TCNT4H1_REG TCNT4H +#define TCNT4H2_REG TCNT4H +#define TCNT4H3_REG TCNT4H +#define TCNT4H4_REG TCNT4H +#define TCNT4H5_REG TCNT4H +#define TCNT4H6_REG TCNT4H +#define TCNT4H7_REG TCNT4H + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TCCR5A */ +#define WGM50_REG TCCR5A +#define WGM51_REG TCCR5A +#define COM5C0_REG TCCR5A +#define COM5C1_REG TCCR5A +#define COM5B0_REG TCCR5A +#define COM5B1_REG TCCR5A +#define COM5A0_REG TCCR5A +#define COM5A1_REG TCCR5A + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* TCCR5C */ +#define FOC5C_REG TCCR5C +#define FOC5B_REG TCCR5C +#define FOC5A_REG TCCR5C + +/* TCCR5B */ +#define CS50_REG TCCR5B +#define CS51_REG TCCR5B +#define CS52_REG TCCR5B +#define WGM52_REG TCCR5B +#define WGM53_REG TCCR5B +#define ICES5_REG TCCR5B +#define ICNC5_REG TCCR5B + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB + +/* OCR5AL */ +#define OCR5AL0_REG OCR5AL +#define OCR5AL1_REG OCR5AL +#define OCR5AL2_REG OCR5AL +#define OCR5AL3_REG OCR5AL +#define OCR5AL4_REG OCR5AL +#define OCR5AL5_REG OCR5AL +#define OCR5AL6_REG OCR5AL +#define OCR5AL7_REG OCR5AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR4CH */ +#define OCR4CH0_REG OCR4CH +#define OCR4CH1_REG OCR4CH +#define OCR4CH2_REG OCR4CH +#define OCR4CH3_REG OCR4CH +#define OCR4CH4_REG OCR4CH +#define OCR4CH5_REG OCR4CH +#define OCR4CH6_REG OCR4CH +#define OCR4CH7_REG OCR4CH + +/* OCR5AH */ +#define OCR5AH0_REG OCR5AH +#define OCR5AH1_REG OCR5AH +#define OCR5AH2_REG OCR5AH +#define OCR5AH3_REG OCR5AH +#define OCR5AH4_REG OCR5AH +#define OCR5AH5_REG OCR5AH +#define OCR5AH6_REG OCR5AH +#define OCR5AH7_REG OCR5AH + +/* OCR4CL */ +#define OCR4CL0_REG OCR4CL +#define OCR4CL1_REG OCR4CL +#define OCR4CL2_REG OCR4CL +#define OCR4CL3_REG OCR4CL +#define OCR4CL4_REG OCR4CL +#define OCR4CL5_REG OCR4CL +#define OCR4CL6_REG OCR4CL +#define OCR4CL7_REG OCR4CL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR5BH */ +#define OCR5BH0_REG OCR5BH +#define OCR5BH1_REG OCR5BH +#define OCR5BH2_REG OCR5BH +#define OCR5BH3_REG OCR5BH +#define OCR5BH4_REG OCR5BH +#define OCR5BH5_REG OCR5BH +#define OCR5BH6_REG OCR5BH +#define OCR5BH7_REG OCR5BH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR5BL */ +#define OCR5BL0_REG OCR5BL +#define OCR5BL1_REG OCR5BL +#define OCR5BL2_REG OCR5BL +#define OCR5BL3_REG OCR5BL +#define OCR5BL4_REG OCR5BL +#define OCR5BL5_REG OCR5BL +#define OCR5BL6_REG OCR5BL +#define OCR5BL7_REG OCR5BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4C_REG TIMSK4 +#define ICIE4_REG TIMSK4 + +/* TIMSK5 */ +#define TOIE5_REG TIMSK5 +#define OCIE5A_REG TIMSK5 +#define OCIE5B_REG TIMSK5 +#define OCIE5C_REG TIMSK5 +#define ICIE5_REG TIMSK5 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define WGM42_REG TCCR4B +#define WGM43_REG TCCR4B +#define ICES4_REG TCCR4B +#define ICNC4_REG TCCR4B + +/* TCCR4C */ +#define FOC4C_REG TCCR4C +#define FOC4B_REG TCCR4C +#define FOC4A_REG TCCR4C + +/* TCCR4A */ +#define WGM40_REG TCCR4A +#define WGM41_REG TCCR4A +#define COM4C0_REG TCCR4A +#define COM4C1_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINL */ +#define PINL0_REG PINL +#define PINL1_REG PINL +#define PINL2_REG PINL +#define PINL3_REG PINL +#define PINL4_REG PINL +#define PINL5_REG PINL +#define PINL6_REG PINL +#define PINL7_REG PINL + +/* OCR4BL */ +#define OCR4BL0_REG OCR4BL +#define OCR4BL1_REG OCR4BL +#define OCR4BL2_REG OCR4BL +#define OCR4BL3_REG OCR4BL +#define OCR4BL4_REG OCR4BL +#define OCR4BL5_REG OCR4BL +#define OCR4BL6_REG OCR4BL +#define OCR4BL7_REG OCR4BL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* OCR4BH */ +#define OCR4BH0_REG OCR4BH +#define OCR4BH1_REG OCR4BH +#define OCR4BH2_REG OCR4BH +#define OCR4BH3_REG OCR4BH +#define OCR4BH4_REG OCR4BH +#define OCR4BH5_REG OCR4BH +#define OCR4BH6_REG OCR4BH +#define OCR4BH7_REG OCR4BH + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSART2_REG PRR1 +#define PRUSART3_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRTIM4_REG PRR1 +#define PRTIM5_REG PRR1 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define OC2A_PORT PORTB +#define OC2A_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define OC0A_PORT PORTB +#define OC0A_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define ICP1_PORT PORTD +#define ICP1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T0_PORT PORTD +#define T0_BIT 7 + +#define RXD_PORT PORTE +#define RXD_BIT 0 +#define PCINT8_PORT PORTE +#define PCINT8_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 + +#define XCK_PORT PORTE +#define XCK_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define CLKO_PORT PORTE +#define CLKO_BIT 7 +#define ICP3_PORT PORTE +#define ICP3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TDO_PORT PORTF +#define TDO_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + +#define OC0B_PORT PORTG +#define OC0B_BIT 5 + +#define RXD2_PORT PORTH +#define RXD2_BIT 0 + +#define TXD2_PORT PORTH +#define TXD2_BIT 1 + +#define XCK2_PORT PORTH +#define XCK2_BIT 2 + +#define OC4A_PORT PORTH +#define OC4A_BIT 3 + +#define OC4B_PORT PORTH +#define OC4B_BIT 4 + +#define OC2B_PORT PORTH +#define OC2B_BIT 6 + +#define T4_PORT PORTH +#define T4_BIT 7 + +#define RXD3_PORT PORTJ +#define RXD3_BIT 0 +#define PCINT9_PORT PORTJ +#define PCINT9_BIT 0 + +#define TXD3_PORT PORTJ +#define TXD3_BIT 1 +#define PCINT10_PORT PORTJ +#define PCINT10_BIT 1 + +#define XCK3_PORT PORTJ +#define XCK3_BIT 2 +#define PCINT11_PORT PORTJ +#define PCINT11_BIT 2 + +#define PCINT12_PORT PORTJ +#define PCINT12_BIT 3 + +#define PCINT13_PORT PORTJ +#define PCINT13_BIT 4 + +#define PCINT14_PORT PORTJ +#define PCINT14_BIT 5 + +#define PCINT15_PORT PORTJ +#define PCINT15_BIT 6 + +#define ADC8_PORT PORTK +#define ADC8_BIT 0 +#define PCINT16_PORT PORTK +#define PCINT16_BIT 0 + +#define ADC9_PORT PORTK +#define ADC9_BIT 1 +#define PCINT17_PORT PORTK +#define PCINT17_BIT 1 + +#define ADC10_PORT PORTK +#define ADC10_BIT 2 +#define PCINT18_PORT PORTK +#define PCINT18_BIT 2 + +#define ADC11_PORT PORTK +#define ADC11_BIT 3 +#define PCINT19_PORT PORTK +#define PCINT19_BIT 3 + +#define ADC12_PORT PORTK +#define ADC12_BIT 4 +#define PCINT20_PORT PORTK +#define PCINT20_BIT 4 + +#define ADC13_PORT PORTK +#define ADC13_BIT 5 +#define PCINT21_PORT PORTK +#define PCINT21_BIT 5 + +#define ADC14_PORT PORTK +#define ADC14_BIT 6 +#define PCINT22_PORT PORTK +#define PCINT22_BIT 6 + +#define ADC15_PORT PORTK +#define ADC15_BIT 7 +#define PCINT23_PORT PORTK +#define PCINT23_BIT 7 + +#define ICP4_PORT PORTL +#define ICP4_BIT 0 + +#define ICP5_PORT PORTL +#define ICP5_BIT 1 + +#define T5_PORT PORTL +#define T5_BIT 2 + +#define OC5A_PORT PORTL +#define OC5A_BIT 3 + +#define OC5B_PORT PORTL +#define OC5B_BIT 4 + +#define OC5C_PORT PORTL +#define OC5C_BIT 5 + + diff --git a/include/aversive/parts/ATmega2561.h b/include/aversive/parts/ATmega2561.h new file mode 100644 index 0000000..55840fb --- /dev/null +++ b/include/aversive/parts/ATmega2561.h @@ -0,0 +1,1875 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ +#define TIMER4_PRESCALER_DIV_0 0 +#define TIMER4_PRESCALER_DIV_1 1 +#define TIMER4_PRESCALER_DIV_8 2 +#define TIMER4_PRESCALER_DIV_64 3 +#define TIMER4_PRESCALER_DIV_256 4 +#define TIMER4_PRESCALER_DIV_1024 5 +#define TIMER4_PRESCALER_DIV_FALL 6 +#define TIMER4_PRESCALER_DIV_RISE 7 + +#define TIMER4_PRESCALER_REG_0 0 +#define TIMER4_PRESCALER_REG_1 1 +#define TIMER4_PRESCALER_REG_2 8 +#define TIMER4_PRESCALER_REG_3 64 +#define TIMER4_PRESCALER_REG_4 256 +#define TIMER4_PRESCALER_REG_5 1024 +#define TIMER4_PRESCALER_REG_6 -1 +#define TIMER4_PRESCALER_REG_7 -2 + +/* prescalers timer 5 */ +#define TIMER5_PRESCALER_DIV_0 0 +#define TIMER5_PRESCALER_DIV_1 1 +#define TIMER5_PRESCALER_DIV_8 2 +#define TIMER5_PRESCALER_DIV_64 3 +#define TIMER5_PRESCALER_DIV_256 4 +#define TIMER5_PRESCALER_DIV_1024 5 +#define TIMER5_PRESCALER_DIV_FALL 6 +#define TIMER5_PRESCALER_DIV_RISE 7 + +#define TIMER5_PRESCALER_REG_0 0 +#define TIMER5_PRESCALER_REG_1 1 +#define TIMER5_PRESCALER_REG_2 8 +#define TIMER5_PRESCALER_REG_3 64 +#define TIMER5_PRESCALER_REG_4 256 +#define TIMER5_PRESCALER_REG_5 1024 +#define TIMER5_PRESCALER_REG_6 -1 +#define TIMER5_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE +#define TIMER4C_AVAILABLE +#define TIMER5_AVAILABLE +#define TIMER5A_AVAILABLE +#define TIMER5B_AVAILABLE +#define TIMER5C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW4_NUM 4 +#define SIG_OVERFLOW5_NUM 5 +#define SIG_OVERFLOW_TOTAL_NUM 6 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE4A_NUM 10 +#define SIG_OUTPUT_COMPARE4B_NUM 11 +#define SIG_OUTPUT_COMPARE4C_NUM 12 +#define SIG_OUTPUT_COMPARE5A_NUM 13 +#define SIG_OUTPUT_COMPARE5B_NUM 14 +#define SIG_OUTPUT_COMPARE5C_NUM 15 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM4A_NUM 10 +#define PWM4B_NUM 11 +#define PWM4C_NUM 12 +#define PWM5A_NUM 13 +#define PWM5B_NUM 14 +#define PWM5C_NUM 15 +#define PWM_TOTAL_NUM 16 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE4_NUM 2 +#define SIG_INPUT_CAPTURE5_NUM 3 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 4 + + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ +#define RAMPZ1_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG +#define PORTG5_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 +#define ADC14D_REG DIDR2 +#define ADC15D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG +#define DDG5_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCNT5H */ +#define TCNT5H0_REG TCNT5H +#define TCNT5H1_REG TCNT5H +#define TCNT5H2_REG TCNT5H +#define TCNT5H3_REG TCNT5H +#define TCNT5H4_REG TCNT5H +#define TCNT5H5_REG TCNT5H +#define TCNT5H6_REG TCNT5H +#define TCNT5H7_REG TCNT5H + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* TCNT5L */ +#define TCNT5L0_REG TCNT5L +#define TCNT5L1_REG TCNT5L +#define TCNT5L2_REG TCNT5L +#define TCNT5L3_REG TCNT5L +#define TCNT5L4_REG TCNT5L +#define TCNT5L5_REG TCNT5L +#define TCNT5L6_REG TCNT5L +#define TCNT5L7_REG TCNT5L + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4C_REG TIFR4 +#define ICF4_REG TIFR4 + +/* TIFR5 */ +#define TOV5_REG TIFR5 +#define OCF5A_REG TIFR5 +#define OCF5B_REG TIFR5 +#define OCF5C_REG TIFR5 +#define ICF5_REG TIFR5 + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* OCR4AH */ +#define OCR4AH0_REG OCR4AH +#define OCR4AH1_REG OCR4AH +#define OCR4AH2_REG OCR4AH +#define OCR4AH3_REG OCR4AH +#define OCR4AH4_REG OCR4AH +#define OCR4AH5_REG OCR4AH +#define OCR4AH6_REG OCR4AH +#define OCR4AH7_REG OCR4AH + +/* OCR5CH */ +#define OCR5CH0_REG OCR5CH +#define OCR5CH1_REG OCR5CH +#define OCR5CH2_REG OCR5CH +#define OCR5CH3_REG OCR5CH +#define OCR5CH4_REG OCR5CH +#define OCR5CH5_REG OCR5CH +#define OCR5CH6_REG OCR5CH +#define OCR5CH7_REG OCR5CH + +/* OCR4AL */ +#define OCR4AL0_REG OCR4AL +#define OCR4AL1_REG OCR4AL +#define OCR4AL2_REG OCR4AL +#define OCR4AL3_REG OCR4AL +#define OCR4AL4_REG OCR4AL +#define OCR4AL5_REG OCR4AL +#define OCR4AL6_REG OCR4AL +#define OCR4AL7_REG OCR4AL + +/* OCR5CL */ +#define OCR5CL0_REG OCR5CL +#define OCR5CL1_REG OCR5CL +#define OCR5CL2_REG OCR5CL +#define OCR5CL3_REG OCR5CL +#define OCR5CL4_REG OCR5CL +#define OCR5CL5_REG OCR5CL +#define OCR5CL6_REG OCR5CL +#define OCR5CL7_REG OCR5CL + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* ICR5L */ +#define ICR5L0_REG ICR5L +#define ICR5L1_REG ICR5L +#define ICR5L2_REG ICR5L +#define ICR5L3_REG ICR5L +#define ICR5L4_REG ICR5L +#define ICR5L5_REG ICR5L +#define ICR5L6_REG ICR5L +#define ICR5L7_REG ICR5L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ICR5H */ +#define ICR5H0_REG ICR5H +#define ICR5H1_REG ICR5H +#define ICR5H2_REG ICR5H +#define ICR5H3_REG ICR5H +#define ICR5H4_REG ICR5H +#define ICR5H5_REG ICR5H +#define ICR5H6_REG ICR5H +#define ICR5H7_REG ICR5H + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* ICR4H */ +#define ICR4H0_REG ICR4H +#define ICR4H1_REG ICR4H +#define ICR4H2_REG ICR4H +#define ICR4H3_REG ICR4H +#define ICR4H4_REG ICR4H +#define ICR4H5_REG ICR4H +#define ICR4H6_REG ICR4H +#define ICR4H7_REG ICR4H + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* ICR4L */ +#define ICR4L0_REG ICR4L +#define ICR4L1_REG ICR4L +#define ICR4L2_REG ICR4L +#define ICR4L3_REG ICR4L +#define ICR4L4_REG ICR4L +#define ICR4L5_REG ICR4L +#define ICR4L6_REG ICR4L +#define ICR4L7_REG ICR4L + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* TCNT4L */ +#define TCNT4L0_REG TCNT4L +#define TCNT4L1_REG TCNT4L +#define TCNT4L2_REG TCNT4L +#define TCNT4L3_REG TCNT4L +#define TCNT4L4_REG TCNT4L +#define TCNT4L5_REG TCNT4L +#define TCNT4L6_REG TCNT4L +#define TCNT4L7_REG TCNT4L + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* TCNT4H */ +#define TCNT4H0_REG TCNT4H +#define TCNT4H1_REG TCNT4H +#define TCNT4H2_REG TCNT4H +#define TCNT4H3_REG TCNT4H +#define TCNT4H4_REG TCNT4H +#define TCNT4H5_REG TCNT4H +#define TCNT4H6_REG TCNT4H +#define TCNT4H7_REG TCNT4H + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TCCR5A */ +#define WGM50_REG TCCR5A +#define WGM51_REG TCCR5A +#define COM5C0_REG TCCR5A +#define COM5C1_REG TCCR5A +#define COM5B0_REG TCCR5A +#define COM5B1_REG TCCR5A +#define COM5A0_REG TCCR5A +#define COM5A1_REG TCCR5A + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* TCCR5C */ +#define FOC5C_REG TCCR5C +#define FOC5B_REG TCCR5C +#define FOC5A_REG TCCR5C + +/* TCCR5B */ +#define CS50_REG TCCR5B +#define CS51_REG TCCR5B +#define CS52_REG TCCR5B +#define WGM52_REG TCCR5B +#define WGM53_REG TCCR5B +#define ICES5_REG TCCR5B +#define ICNC5_REG TCCR5B + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB + +/* OCR5AL */ +#define OCR5AL0_REG OCR5AL +#define OCR5AL1_REG OCR5AL +#define OCR5AL2_REG OCR5AL +#define OCR5AL3_REG OCR5AL +#define OCR5AL4_REG OCR5AL +#define OCR5AL5_REG OCR5AL +#define OCR5AL6_REG OCR5AL +#define OCR5AL7_REG OCR5AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR4CH */ +#define OCR4CH0_REG OCR4CH +#define OCR4CH1_REG OCR4CH +#define OCR4CH2_REG OCR4CH +#define OCR4CH3_REG OCR4CH +#define OCR4CH4_REG OCR4CH +#define OCR4CH5_REG OCR4CH +#define OCR4CH6_REG OCR4CH +#define OCR4CH7_REG OCR4CH + +/* OCR5AH */ +#define OCR5AH0_REG OCR5AH +#define OCR5AH1_REG OCR5AH +#define OCR5AH2_REG OCR5AH +#define OCR5AH3_REG OCR5AH +#define OCR5AH4_REG OCR5AH +#define OCR5AH5_REG OCR5AH +#define OCR5AH6_REG OCR5AH +#define OCR5AH7_REG OCR5AH + +/* OCR4CL */ +#define OCR4CL0_REG OCR4CL +#define OCR4CL1_REG OCR4CL +#define OCR4CL2_REG OCR4CL +#define OCR4CL3_REG OCR4CL +#define OCR4CL4_REG OCR4CL +#define OCR4CL5_REG OCR4CL +#define OCR4CL6_REG OCR4CL +#define OCR4CL7_REG OCR4CL + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR5BH */ +#define OCR5BH0_REG OCR5BH +#define OCR5BH1_REG OCR5BH +#define OCR5BH2_REG OCR5BH +#define OCR5BH3_REG OCR5BH +#define OCR5BH4_REG OCR5BH +#define OCR5BH5_REG OCR5BH +#define OCR5BH6_REG OCR5BH +#define OCR5BH7_REG OCR5BH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR5BL */ +#define OCR5BL0_REG OCR5BL +#define OCR5BL1_REG OCR5BL +#define OCR5BL2_REG OCR5BL +#define OCR5BL3_REG OCR5BL +#define OCR5BL4_REG OCR5BL +#define OCR5BL5_REG OCR5BL +#define OCR5BL6_REG OCR5BL +#define OCR5BL7_REG OCR5BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4C_REG TIMSK4 +#define ICIE4_REG TIMSK4 + +/* TIMSK5 */ +#define TOIE5_REG TIMSK5 +#define OCIE5A_REG TIMSK5 +#define OCIE5B_REG TIMSK5 +#define OCIE5C_REG TIMSK5 +#define ICIE5_REG TIMSK5 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define WGM42_REG TCCR4B +#define WGM43_REG TCCR4B +#define ICES4_REG TCCR4B +#define ICNC4_REG TCCR4B + +/* TCCR4C */ +#define FOC4C_REG TCCR4C +#define FOC4B_REG TCCR4C +#define FOC4A_REG TCCR4C + +/* TCCR4A */ +#define WGM40_REG TCCR4A +#define WGM41_REG TCCR4A +#define COM4C0_REG TCCR4A +#define COM4C1_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* OCR4BL */ +#define OCR4BL0_REG OCR4BL +#define OCR4BL1_REG OCR4BL +#define OCR4BL2_REG OCR4BL +#define OCR4BL3_REG OCR4BL +#define OCR4BL4_REG OCR4BL +#define OCR4BL5_REG OCR4BL +#define OCR4BL6_REG OCR4BL +#define OCR4BL7_REG OCR4BL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* OCR4BH */ +#define OCR4BH0_REG OCR4BH +#define OCR4BH1_REG OCR4BH +#define OCR4BH2_REG OCR4BH +#define OCR4BH3_REG OCR4BH +#define OCR4BH4_REG OCR4BH +#define OCR4BH5_REG OCR4BH +#define OCR4BH6_REG OCR4BH +#define OCR4BH7_REG OCR4BH + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSART2_REG PRR1 +#define PRUSART3_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRTIM4_REG PRR1 +#define PRTIM5_REG PRR1 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define OC2_PORT PORTB +#define OC2_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define OC0A_PORT PORTB +#define OC0A_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define ICP1_PORT PORTD +#define ICP1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T0_PORT PORTD +#define T0_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 +#define PCINT8_PORT PORTE +#define PCINT8_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define ICP3_PORT PORTE +#define ICP3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 +#define CLKO_PORT PORTE +#define CLKO_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + +#define OC0B_PORT PORTG +#define OC0B_BIT 5 + + diff --git a/include/aversive/parts/ATmega32.h b/include/aversive/parts/ATmega32.h new file mode 100644 index 0000000..729dadf --- /dev/null +++ b/include/aversive/parts/ATmega32.h @@ -0,0 +1,824 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ACME_REG SFIOR +#define ADTS0_REG SFIOR +#define ADTS1_REG SFIOR +#define ADTS2_REG SFIOR +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define ISC2_REG MCUCSR +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SM2_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0_PORT PORTB +#define OC0_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + +#define TMS_PORT PORTC +#define TMS_BIT 2 + +#define TCK_PORT PORTC +#define TCK_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega323.h b/include/aversive/parts/ATmega323.h new file mode 100644 index 0000000..39a6182 --- /dev/null +++ b/include/aversive/parts/ATmega323.h @@ -0,0 +1,817 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define PWM0_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define ASRE_REG SPMCR +#define ASB_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define ISC2_REG MCUCSR +#define JDT_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADATE_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define CTC2_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define PWM2_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SM2_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0_PORT PORTB +#define OC0_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + +#define TMS_PORT PORTC +#define TMS_BIT 2 + +#define TCK_PORT PORTC +#define TCK_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega324P.h b/include/aversive/parts/ATmega324P.h new file mode 100644 index 0000000..78f09a9 --- /dev/null +++ b/include/aversive/parts/ATmega324P.h @@ -0,0 +1,1163 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPCR0 */ +#define SPR00_REG SPCR0 +#define SPR10_REG SPCR0 +#define CPHA0_REG SPCR0 +#define CPOL0_REG SPCR0 +#define MSTR0_REG SPCR0 +#define DORD0_REG SPCR0 +#define SPE0_REG SPCR0 +#define SPIE0_REG SPCR0 + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* SPDR0 */ +#define SPDRB0_REG SPDR0 +#define SPDRB1_REG SPDR0 +#define SPDRB2_REG SPDR0 +#define SPDRB3_REG SPDR0 +#define SPDRB4_REG SPDR0 +#define SPDRB5_REG SPDR0 +#define SPDRB6_REG SPDR0 +#define SPDRB7_REG SPDR0 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* SPSR0 */ +#define SPI2X0_REG SPSR0 +#define WCOL0_REG SPSR0 +#define SPIF0_REG SPSR0 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRUSART1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 +#define PCINT31_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 +#define CLKO_PORT PORTB +#define CLKO_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0A_PORT PORTB +#define OC0A_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 +#define OC0B_PORT PORTB +#define OC0B_BIT 4 +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 +#define PCINT16_PORT PORTC +#define PCINT16_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 +#define PCINT17_PORT PORTC +#define PCINT17_BIT 1 + +#define TCK_PORT PORTC +#define TCK_BIT 2 +#define PCINT18_PORT PORTC +#define PCINT18_BIT 2 + +#define TMS_PORT PORTC +#define TMS_BIT 3 +#define PCINT19_PORT PORTC +#define PCINT19_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 +#define PCINT20_PORT PORTC +#define PCINT20_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 +#define PCINT21_PORT PORTC +#define PCINT21_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 +#define PCINT22_PORT PORTC +#define PCINT22_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 +#define PCINT23_PORT PORTC +#define PCINT23_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT24_PORT PORTD +#define PCINT24_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT25_PORT PORTD +#define PCINT25_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT26_PORT PORTD +#define PCINT26_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define PCINT27_PORT PORTD +#define PCINT27_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 +#define PCINT28_PORT PORTD +#define PCINT28_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define PCINT29_PORT PORTD +#define PCINT29_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 +#define OC2B_PORT PORTD +#define OC2B_BIT 6 +#define PCINT30_PORT PORTD +#define PCINT30_BIT 6 + +#define OC2A_PORT PORTD +#define OC2A_BIT 7 +#define PCINT31_PORT PORTD +#define PCINT31_BIT 7 + + diff --git a/include/aversive/parts/ATmega324PA.h b/include/aversive/parts/ATmega324PA.h new file mode 100644 index 0000000..78f09a9 --- /dev/null +++ b/include/aversive/parts/ATmega324PA.h @@ -0,0 +1,1163 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPCR0 */ +#define SPR00_REG SPCR0 +#define SPR10_REG SPCR0 +#define CPHA0_REG SPCR0 +#define CPOL0_REG SPCR0 +#define MSTR0_REG SPCR0 +#define DORD0_REG SPCR0 +#define SPE0_REG SPCR0 +#define SPIE0_REG SPCR0 + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* SPDR0 */ +#define SPDRB0_REG SPDR0 +#define SPDRB1_REG SPDR0 +#define SPDRB2_REG SPDR0 +#define SPDRB3_REG SPDR0 +#define SPDRB4_REG SPDR0 +#define SPDRB5_REG SPDR0 +#define SPDRB6_REG SPDR0 +#define SPDRB7_REG SPDR0 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* SPSR0 */ +#define SPI2X0_REG SPSR0 +#define WCOL0_REG SPSR0 +#define SPIF0_REG SPSR0 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRUSART1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 +#define PCINT31_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 +#define CLKO_PORT PORTB +#define CLKO_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0A_PORT PORTB +#define OC0A_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 +#define OC0B_PORT PORTB +#define OC0B_BIT 4 +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 +#define PCINT16_PORT PORTC +#define PCINT16_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 +#define PCINT17_PORT PORTC +#define PCINT17_BIT 1 + +#define TCK_PORT PORTC +#define TCK_BIT 2 +#define PCINT18_PORT PORTC +#define PCINT18_BIT 2 + +#define TMS_PORT PORTC +#define TMS_BIT 3 +#define PCINT19_PORT PORTC +#define PCINT19_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 +#define PCINT20_PORT PORTC +#define PCINT20_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 +#define PCINT21_PORT PORTC +#define PCINT21_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 +#define PCINT22_PORT PORTC +#define PCINT22_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 +#define PCINT23_PORT PORTC +#define PCINT23_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT24_PORT PORTD +#define PCINT24_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT25_PORT PORTD +#define PCINT25_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT26_PORT PORTD +#define PCINT26_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define PCINT27_PORT PORTD +#define PCINT27_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 +#define PCINT28_PORT PORTD +#define PCINT28_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define PCINT29_PORT PORTD +#define PCINT29_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 +#define OC2B_PORT PORTD +#define OC2B_BIT 6 +#define PCINT30_PORT PORTD +#define PCINT30_BIT 6 + +#define OC2A_PORT PORTD +#define OC2A_BIT 7 +#define PCINT31_PORT PORTD +#define PCINT31_BIT 7 + + diff --git a/include/aversive/parts/ATmega325.h b/include/aversive/parts/ATmega325.h new file mode 100644 index 0000000..c6e1d99 --- /dev/null +++ b/include/aversive/parts/ATmega325.h @@ -0,0 +1,897 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega3250.h b/include/aversive/parts/ATmega3250.h new file mode 100644 index 0000000..cfde1f1 --- /dev/null +++ b/include/aversive/parts/ATmega3250.h @@ -0,0 +1,974 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega3250P.h b/include/aversive/parts/ATmega3250P.h new file mode 100644 index 0000000..eb00606 --- /dev/null +++ b/include/aversive/parts/ATmega3250P.h @@ -0,0 +1,976 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega325P.h b/include/aversive/parts/ATmega325P.h new file mode 100644 index 0000000..b980cc4 --- /dev/null +++ b/include/aversive/parts/ATmega325P.h @@ -0,0 +1,900 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega328P.h b/include/aversive/parts/ATmega328P.h new file mode 100644 index 0000000..12f5193 --- /dev/null +++ b/include/aversive/parts/ATmega328P.h @@ -0,0 +1,999 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega329.h b/include/aversive/parts/ATmega329.h new file mode 100644 index 0000000..ca186bb --- /dev/null +++ b/include/aversive/parts/ATmega329.h @@ -0,0 +1,1064 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDPM3_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega3290.h b/include/aversive/parts/ATmega3290.h new file mode 100644 index 0000000..84230d3 --- /dev/null +++ b/include/aversive/parts/ATmega3290.h @@ -0,0 +1,1208 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 +#define SEG025_REG LCDDR3 +#define SEG026_REG LCDDR3 +#define SEG027_REG LCDDR3 +#define SEG028_REG LCDDR3 +#define SEG029_REG LCDDR3 +#define SEG030_REG LCDDR3 +#define SEG031_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* LCDDR4 */ +#define SEG032_REG LCDDR4 +#define SEG033_REG LCDDR4 +#define SEG034_REG LCDDR4 +#define SEG035_REG LCDDR4 +#define SEG036_REG LCDDR4 +#define SEG037_REG LCDDR4 +#define SEG038_REG LCDDR4 +#define SEG039_REG LCDDR4 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR9 */ +#define SEG132_REG LCDDR9 +#define SEG133_REG LCDDR9 +#define SEG134_REG LCDDR9 +#define SEG135_REG LCDDR9 +#define SEG136_REG LCDDR9 +#define SEG137_REG LCDDR9 +#define SEG138_REG LCDDR9 +#define SEG139_REG LCDDR9 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 +#define SEG125_REG LCDDR8 +#define SEG126_REG LCDDR8 +#define SEG127_REG LCDDR8 +#define SEG128_REG LCDDR8 +#define SEG129_REG LCDDR8 +#define SEG130_REG LCDDR8 +#define SEG131_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDPM3_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDDR19 */ +#define SEG332_REG LCDDR19 +#define SEG333_REG LCDDR19 +#define SEG334_REG LCDDR19 +#define SEG335_REG LCDDR19 +#define SEG336_REG LCDDR19 +#define SEG337_REG LCDDR19 +#define SEG338_REG LCDDR19 +#define SEG339_REG LCDDR19 + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 +#define SEG325_REG LCDDR18 +#define SEG326_REG LCDDR18 +#define SEG327_REG LCDDR18 +#define SEG328_REG LCDDR18 +#define SEG329_REG LCDDR18 +#define SEG330_REG LCDDR18 +#define SEG331_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 +#define SEG225_REG LCDDR13 +#define SEG226_REG LCDDR13 +#define SEG227_REG LCDDR13 +#define SEG228_REG LCDDR13 +#define SEG229_REG LCDDR13 +#define SEG230_REG LCDDR13 +#define SEG231_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* LCDDR14 */ +#define SEG232_REG LCDDR14 +#define SEG233_REG LCDDR14 +#define SEG234_REG LCDDR14 +#define SEG235_REG LCDDR14 +#define SEG236_REG LCDDR14 +#define SEG237_REG LCDDR14 +#define SEG238_REG LCDDR14 +#define SEG239_REG LCDDR14 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega3290P.h b/include/aversive/parts/ATmega3290P.h new file mode 100644 index 0000000..da8f3f2 --- /dev/null +++ b/include/aversive/parts/ATmega3290P.h @@ -0,0 +1,1213 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 +#define SEG025_REG LCDDR3 +#define SEG026_REG LCDDR3 +#define SEG027_REG LCDDR3 +#define SEG028_REG LCDDR3 +#define SEG029_REG LCDDR3 +#define SEG030_REG LCDDR3 +#define SEG031_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* LCDDR4 */ +#define SEG032_REG LCDDR4 +#define SEG033_REG LCDDR4 +#define SEG034_REG LCDDR4 +#define SEG035_REG LCDDR4 +#define SEG036_REG LCDDR4 +#define SEG037_REG LCDDR4 +#define SEG038_REG LCDDR4 +#define SEG039_REG LCDDR4 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR9 */ +#define SEG132_REG LCDDR9 +#define SEG133_REG LCDDR9 +#define SEG134_REG LCDDR9 +#define SEG135_REG LCDDR9 +#define SEG136_REG LCDDR9 +#define SEG137_REG LCDDR9 +#define SEG138_REG LCDDR9 +#define SEG139_REG LCDDR9 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 +#define SEG125_REG LCDDR8 +#define SEG126_REG LCDDR8 +#define SEG127_REG LCDDR8 +#define SEG128_REG LCDDR8 +#define SEG129_REG LCDDR8 +#define SEG130_REG LCDDR8 +#define SEG131_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDCCD_REG LCDCRA +#define LCDBD_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDPM3_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDDR19 */ +#define SEG332_REG LCDDR19 +#define SEG333_REG LCDDR19 +#define SEG334_REG LCDDR19 +#define SEG335_REG LCDDR19 +#define SEG336_REG LCDDR19 +#define SEG337_REG LCDDR19 +#define SEG338_REG LCDDR19 +#define SEG339_REG LCDDR19 + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 +#define SEG325_REG LCDDR18 +#define SEG326_REG LCDDR18 +#define SEG327_REG LCDDR18 +#define SEG328_REG LCDDR18 +#define SEG329_REG LCDDR18 +#define SEG330_REG LCDDR18 +#define SEG331_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 +#define SEG225_REG LCDDR13 +#define SEG226_REG LCDDR13 +#define SEG227_REG LCDDR13 +#define SEG228_REG LCDDR13 +#define SEG229_REG LCDDR13 +#define SEG230_REG LCDDR13 +#define SEG231_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* LCDDR14 */ +#define SEG232_REG LCDDR14 +#define SEG233_REG LCDDR14 +#define SEG234_REG LCDDR14 +#define SEG235_REG LCDDR14 +#define SEG236_REG LCDDR14 +#define SEG237_REG LCDDR14 +#define SEG238_REG LCDDR14 +#define SEG239_REG LCDDR14 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDMDT_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega329P.h b/include/aversive/parts/ATmega329P.h new file mode 100644 index 0000000..d6efc0d --- /dev/null +++ b/include/aversive/parts/ATmega329P.h @@ -0,0 +1,1069 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDCCD_REG LCDCRA +#define LCDBD_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDPM3_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDMDT_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega32A.h b/include/aversive/parts/ATmega32A.h new file mode 100644 index 0000000..729dadf --- /dev/null +++ b/include/aversive/parts/ATmega32A.h @@ -0,0 +1,824 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ACME_REG SFIOR +#define ADTS0_REG SFIOR +#define ADTS1_REG SFIOR +#define ADTS2_REG SFIOR +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define ISC2_REG MCUCSR +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR00_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SM2_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0_PORT PORTB +#define OC0_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + +#define TMS_PORT PORTC +#define TMS_BIT 2 + +#define TCK_PORT PORTC +#define TCK_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega32C1.h b/include/aversive/parts/ATmega32C1.h new file mode 100644 index 0000000..da9a428 --- /dev/null +++ b/include/aversive/parts/ATmega32C1.h @@ -0,0 +1,1304 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* LINBTR */ +#define LBT0_REG LINBTR +#define LBT1_REG LINBTR +#define LBT2_REG LINBTR +#define LBT3_REG LINBTR +#define LBT4_REG LINBTR +#define LBT5_REG LINBTR +#define LDISR_REG LINBTR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* LINIDR */ +#define LID0_REG LINIDR +#define LID1_REG LINIDR +#define LID2_REG LINIDR +#define LID3_REG LINIDR +#define LID4_REG LINIDR +#define LID5_REG LINIDR +#define LP0_REG LINIDR +#define LP1_REG LINIDR + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC3O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define AC3IF_REG ACSR + +/* LINSEL */ +#define LINDX0_REG LINSEL +#define LINDX1_REG LINSEL +#define LINDX2_REG LINSEL +#define LAINC_REG LINSEL + +/* LINCR */ +#define LCMD0_REG LINCR +#define LCMD1_REG LINCR +#define LCMD2_REG LINCR +#define LENA_REG LINCR +#define LCONF0_REG LINCR +#define LCONF1_REG LINCR +#define LIN13_REG LINCR +#define LSWRES_REG LINCR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRLIN_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC_REG PRR +#define PRCAN_REG PRR + +/* LINBRRL */ +#define LDIV0_REG LINBRRL +#define LDIV1_REG LINBRRL +#define LDIV2_REG LINBRRL +#define LDIV3_REG LINBRRL +#define LDIV4_REG LINBRRL +#define LDIV5_REG LINBRRL +#define LDIV6_REG LINBRRL +#define LDIV7_REG LINBRRL + +/* LINBRRH */ +#define LDIV8_REG LINBRRH +#define LDIV9_REG LINBRRH +#define LDIV10_REG LINBRRH +#define LDIV11_REG LINBRRH + +/* CANGSTA */ +#define ERRP_REG CANGSTA +#define BOFF_REG CANGSTA +#define ENFG_REG CANGSTA +#define RXBSY_REG CANGSTA +#define TXBSY_REG CANGSTA +#define OVFG_REG CANGSTA + +/* CANGCON */ +#define SWRES_REG CANGCON +#define ENASTB_REG CANGCON +#define TEST_REG CANGCON +#define LISTEN_REG CANGCON +#define SYNTTC_REG CANGCON +#define TTC_REG CANGCON +#define OVRQ_REG CANGCON +#define ABRQ_REG CANGCON + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1TS2_REG AMP1CSR +#define AMPCMP1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* LINSIR */ +#define LRXOK_REG LINSIR +#define LTXOK_REG LINSIR +#define LIDOK_REG LINSIR +#define LERR_REG LINSIR +#define LBUSY_REG LINSIR +#define LIDST0_REG LINSIR +#define LIDST1_REG LINSIR +#define LIDST2_REG LINSIR + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 +#define AMP2PD_REG DIDR1 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* CANIDM1 */ +#define IDMSK21_REG CANIDM1 +#define IDMSK22_REG CANIDM1 +#define IDMSK23_REG CANIDM1 +#define IDMSK24_REG CANIDM1 +#define IDMSK25_REG CANIDM1 +#define IDMSK26_REG CANIDM1 +#define IDMSK27_REG CANIDM1 +#define IDMSK28_REG CANIDM1 + +/* CANIDM3 */ +#define IDMSK5_REG CANIDM3 +#define IDMSK6_REG CANIDM3 +#define IDMSK7_REG CANIDM3 +#define IDMSK8_REG CANIDM3 +#define IDMSK9_REG CANIDM3 +#define IDMSK10_REG CANIDM3 +#define IDMSK11_REG CANIDM3 +#define IDMSK12_REG CANIDM3 + +/* CANIDM2 */ +#define IDMSK13_REG CANIDM2 +#define IDMSK14_REG CANIDM2 +#define IDMSK15_REG CANIDM2 +#define IDMSK16_REG CANIDM2 +#define IDMSK17_REG CANIDM2 +#define IDMSK18_REG CANIDM2 +#define IDMSK19_REG CANIDM2 +#define IDMSK20_REG CANIDM2 + +/* CANIDM4 */ +#define IDEMSK_REG CANIDM4 +#define RTRMSK_REG CANIDM4 +#define IDMSK0_REG CANIDM4 +#define IDMSK1_REG CANIDM4 +#define IDMSK2_REG CANIDM4 +#define IDMSK3_REG CANIDM4 +#define IDMSK4_REG CANIDM4 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* CANGIT */ +#define AERG_REG CANGIT +#define FERG_REG CANGIT +#define CERG_REG CANGIT +#define SERG_REG CANGIT +#define BXOK_REG CANGIT +#define OVRTIM_REG CANGIT +#define BOFFIT_REG CANGIT +#define CANIT_REG CANGIT + +/* AC3CON */ +#define AC3M0_REG AC3CON +#define AC3M1_REG AC3CON +#define AC3M2_REG AC3CON +#define AC3IS0_REG AC3CON +#define AC3IS1_REG AC3CON +#define AC3IE_REG AC3CON +#define AC3EN_REG AC3CON + +/* LINERR */ +#define LBERR_REG LINERR +#define LCERR_REG LINERR +#define LPERR_REG LINERR +#define LSERR_REG LINERR +#define LFERR_REG LINERR +#define LOVERR_REG LINERR +#define LTOERR_REG LINERR +#define LABORT_REG LINERR + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* CANGIE */ +#define ENOVRT_REG CANGIE +#define ENERG_REG CANGIE +#define ENBX_REG CANGIE +#define ENERR_REG CANGIE +#define ENTX_REG CANGIE +#define ENRX_REG CANGIE +#define ENBOFF_REG CANGIE +#define ENIT_REG CANGIE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* CANIE2 */ +#define IEMOB0_REG CANIE2 +#define IEMOB1_REG CANIE2 +#define IEMOB2_REG CANIE2 +#define IEMOB3_REG CANIE2 +#define IEMOB4_REG CANIE2 +#define IEMOB5_REG CANIE2 + +/* CANSIT2 */ +#define SIT0_REG CANSIT2 +#define SIT1_REG CANSIT2 +#define SIT2_REG CANSIT2 +#define SIT3_REG CANSIT2 +#define SIT4_REG CANSIT2 +#define SIT5_REG CANSIT2 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* CANIDT4 */ +#define RB0TAG_REG CANIDT4 +#define RB1TAG_REG CANIDT4 +#define RTRTAG_REG CANIDT4 +#define IDT0_REG CANIDT4 +#define IDT1_REG CANIDT4 +#define IDT2_REG CANIDT4 +#define IDT3_REG CANIDT4 +#define IDT4_REG CANIDT4 + +/* CANIDT2 */ +#define IDT13_REG CANIDT2 +#define IDT14_REG CANIDT2 +#define IDT15_REG CANIDT2 +#define IDT16_REG CANIDT2 +#define IDT17_REG CANIDT2 +#define IDT18_REG CANIDT2 +#define IDT19_REG CANIDT2 +#define IDT20_REG CANIDT2 + +/* CANIDT3 */ +#define IDT5_REG CANIDT3 +#define IDT6_REG CANIDT3 +#define IDT7_REG CANIDT3 +#define IDT8_REG CANIDT3 +#define IDT9_REG CANIDT3 +#define IDT10_REG CANIDT3 +#define IDT11_REG CANIDT3 +#define IDT12_REG CANIDT3 + +/* CANIDT1 */ +#define IDT21_REG CANIDT1 +#define IDT22_REG CANIDT1 +#define IDT23_REG CANIDT1 +#define IDT24_REG CANIDT1 +#define IDT25_REG CANIDT1 +#define IDT26_REG CANIDT1 +#define IDT27_REG CANIDT1 +#define IDT28_REG CANIDT1 + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* CANCDMOB */ +#define DLC0_REG CANCDMOB +#define DLC1_REG CANCDMOB +#define DLC2_REG CANCDMOB +#define DLC3_REG CANCDMOB +#define IDE_REG CANCDMOB +#define RPLV_REG CANCDMOB +#define CONMOB0_REG CANCDMOB +#define CONMOB1_REG CANCDMOB + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* CANHPMOB */ +#define CGP0_REG CANHPMOB +#define CGP1_REG CANHPMOB +#define CGP2_REG CANHPMOB +#define CGP3_REG CANHPMOB +#define HPMOB0_REG CANHPMOB +#define HPMOB1_REG CANHPMOB +#define HPMOB2_REG CANHPMOB +#define HPMOB3_REG CANHPMOB + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* LINENIR */ +#define LENRXOK_REG LINENIR +#define LENTXOK_REG LINENIR +#define LENIDOK_REG LINENIR +#define LENERR_REG LINENIR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* AMP2CSR */ +#define AMP2TS0_REG AMP2CSR +#define AMP2TS1_REG AMP2CSR +#define AMP2TS2_REG AMP2CSR +#define AMPCMP2_REG AMP2CSR +#define AMP2G0_REG AMP2CSR +#define AMP2G1_REG AMP2CSR +#define AMP2IS_REG AMP2CSR +#define AMP2EN_REG AMP2CSR + +/* LINDAT */ +#define LDATA0_REG LINDAT +#define LDATA1_REG LINDAT +#define LDATA2_REG LINDAT +#define LDATA3_REG LINDAT +#define LDATA4_REG LINDAT +#define LDATA5_REG LINDAT +#define LDATA6_REG LINDAT +#define LDATA7_REG LINDAT + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* CANPAGE */ +#define INDX0_REG CANPAGE +#define INDX1_REG CANPAGE +#define INDX2_REG CANPAGE +#define AINC_REG CANPAGE +#define MOBNB0_REG CANPAGE +#define MOBNB1_REG CANPAGE +#define MOBNB2_REG CANPAGE +#define MOBNB3_REG CANPAGE + +/* LINDLR */ +#define LRXDL0_REG LINDLR +#define LRXDL1_REG LINDLR +#define LRXDL2_REG LINDLR +#define LRXDL3_REG LINDLR +#define LTXDL0_REG LINDLR +#define LTXDL1_REG LINDLR +#define LTXDL2_REG LINDLR +#define LTXDL3_REG LINDLR + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* CANSTMOB */ +#define AERR_REG CANSTMOB +#define FERR_REG CANSTMOB +#define CERR_REG CANSTMOB +#define SERR_REG CANSTMOB +#define BERR_REG CANSTMOB +#define RXOK_REG CANSTMOB +#define TXOK_REG CANSTMOB +#define DLCW_REG CANSTMOB + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* CANEN2 */ +#define ENMOB0_REG CANEN2 +#define ENMOB1_REG CANEN2 +#define ENMOB2_REG CANEN2 +#define ENMOB3_REG CANEN2 +#define ENMOB4_REG CANEN2 +#define ENMOB5_REG CANEN2 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define AREFEN_REG ADCSRB +#define ISRCEN_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* CANBT2 */ +#define PRS0_REG CANBT2 +#define PRS1_REG CANBT2 +#define PRS2_REG CANBT2 +#define SJW0_REG CANBT2 +#define SJW1_REG CANBT2 + +/* CANBT3 */ +#define SMP_REG CANBT3 +#define PHS10_REG CANBT3 +#define PHS11_REG CANBT3 +#define PHS12_REG CANBT3 +#define PHS20_REG CANBT3 +#define PHS21_REG CANBT3 +#define PHS22_REG CANBT3 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* CANBT1 */ +#define BRP0_REG CANBT1 +#define BRP1_REG CANBT1 +#define BRP2_REG CANBT1 +#define BRP3_REG CANBT1 +#define BRP4_REG CANBT1 +#define BRP5_REG CANBT1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0TS2_REG AMP0CSR +#define AMPCMP0_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define ACCKSEL_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 +#define ACMPN0_PORT PORTB +#define ACMPN0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 +#define ACMPN1_PORT PORTB +#define ACMPN1_BIT 5 +#define AMP2-_PORT PORTB +#define AMP2-_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define INT3_PORT PORTC +#define INT3_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define OC1B_PORT PORTC +#define OC1B_BIT 1 +#define SS_A_PORT PORTC +#define SS_A_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define T0_PORT PORTC +#define T0_BIT 2 +#define TXCAN_PORT PORTC +#define TXCAN_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define T1_PORT PORTC +#define T1_BIT 3 +#define RXCAN_PORT PORTC +#define RXCAN_BIT 3 +#define ICP1B_PORT PORTC +#define ICP1B_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC8_PORT PORTC +#define ADC8_BIT 4 +#define AMP1-_PORT PORTC +#define AMP1-_BIT 4 +#define ACMPN3_PORT PORTC +#define ACMPN3_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC9_PORT PORTC +#define ADC9_BIT 5 +#define AMP1+_PORT PORTC +#define AMP1+_BIT 5 +#define ACMP3_PORT PORTC +#define ACMP3_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define ADC10_PORT PORTC +#define ADC10_BIT 6 +#define ACMP1_PORT PORTC +#define ACMP1_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define D2A_PORT PORTC +#define D2A_BIT 7 +#define AMP2+_PORT PORTC +#define AMP2+_BIT 7 +#define PCINT15_PORT PORTC +#define PCINT15_BIT 7 + +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define CLK0_PORT PORTD +#define CLK0_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define TXLIN_PORT PORTD +#define TXLIN_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define RXLIN_PORT PORTD +#define RXLIN_BIT 4 +#define ICP1A_PORT PORTD +#define ICP1A_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACMP2_PORT PORTD +#define ACMP2_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPN2_PORT PORTD +#define ACMPN2_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 +#define PCINT24_PORT PORTE +#define PCINT24_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 +#define PCINT25_PORT PORTE +#define PCINT25_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 +#define PCINT26_PORT PORTE +#define PCINT26_BIT 2 + + diff --git a/include/aversive/parts/ATmega32HVB.h b/include/aversive/parts/ATmega32HVB.h new file mode 100644 index 0000000..96c42b4 --- /dev/null +++ b/include/aversive/parts/ATmega32HVB.h @@ -0,0 +1,882 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CADAC2 */ +#define CADAC16_REG CADAC2 +#define CADAC17_REG CADAC2 +#define CADAC18_REG CADAC2 +#define CADAC19_REG CADAC2 +#define CADAC20_REG CADAC2 +#define CADAC21_REG CADAC2 +#define CADAC22_REG CADAC2 +#define CADAC23_REG CADAC2 + +/* CADAC3 */ +#define CADAC24_REG CADAC3 +#define CADAC25_REG CADAC3 +#define CADAC26_REG CADAC3 +#define CADAC27_REG CADAC3 +#define CADAC28_REG CADAC3 +#define CADAC29_REG CADAC3 +#define CADAC30_REG CADAC3 +#define CADAC31_REG CADAC3 + +/* CADAC0 */ +#define CADAC00_REG CADAC0 +#define CADAC01_REG CADAC0 +#define CADAC02_REG CADAC0 +#define CADAC03_REG CADAC0 +#define CADAC04_REG CADAC0 +#define CADAC05_REG CADAC0 +#define CADAC06_REG CADAC0 +#define CADAC07_REG CADAC0 + +/* CADAC1 */ +#define CADAC08_REG CADAC1 +#define CADAC09_REG CADAC1 +#define CADAC10_REG CADAC1 +#define CADAC11_REG CADAC1 +#define CADAC12_REG CADAC1 +#define CADAC13_REG CADAC1 +#define CADAC14_REG CADAC1 +#define CADAC15_REG CADAC1 + +/* BPIMSK */ +#define CHCIE_REG BPIMSK +#define DHCIE_REG BPIMSK +#define COCIE_REG BPIMSK +#define DOCIE_REG BPIMSK +#define SCIE_REG BPIMSK + +/* TCNT0H */ +#define TCNT0H0_REG TCNT0H +#define TCNT0H1_REG TCNT0H +#define TCNT0H2_REG TCNT0H +#define TCNT0H3_REG TCNT0H +#define TCNT0H4_REG TCNT0H +#define TCNT0H5_REG TCNT0H +#define TCNT0H6_REG TCNT0H +#define TCNT0H7_REG TCNT0H + +/* TCNT0L */ +#define TCNT0L0_REG TCNT0L +#define TCNT0L1_REG TCNT0L +#define TCNT0L2_REG TCNT0L +#define TCNT0L3_REG TCNT0L +#define TCNT0L4_REG TCNT0L +#define TCNT0L5_REG TCNT0L +#define TCNT0L6_REG TCNT0L +#define TCNT0L7_REG TCNT0L + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* BPCOCD */ +#define COCDL0_REG BPCOCD +#define COCDL1_REG BPCOCD +#define COCDL2_REG BPCOCD +#define COCDL3_REG BPCOCD +#define COCDL4_REG BPCOCD +#define COCDL5_REG BPCOCD +#define COCDL6_REG BPCOCD +#define COCDL7_REG BPCOCD + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA + +/* BPSCD */ +#define SCDL0_REG BPSCD +#define SCDL1_REG BPSCD +#define SCDL2_REG BPSCD +#define SCDL3_REG BPSCD +#define SCDL4_REG BPSCD +#define SCDL5_REG BPSCD +#define SCDL6_REG BPSCD +#define SCDL7_REG BPSCD + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* VADCH */ +#define VADC8_REG VADCH +#define VADC9_REG VADCH +#define VADC10_REG VADCH +#define VADC11_REG VADCH + +/* VADCL */ +#define VADC0_REG VADCL +#define VADC1_REG VADCL +#define VADC2_REG VADCL +#define VADC3_REG VADCL +#define VADC4_REG VADCL +#define VADC5_REG VADCL +#define VADC6_REG VADCL +#define VADC7_REG VADCL + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* FOSCCAL */ +#define FCAL0_REG FOSCCAL +#define FCAL1_REG FOSCCAL +#define FCAL2_REG FOSCCAL +#define FCAL3_REG FOSCCAL +#define FCAL4_REG FOSCCAL +#define FCAL5_REG FOSCCAL +#define FCAL6_REG FOSCCAL +#define FCAL7_REG FOSCCAL + +/* DIDR0 */ +#define PA0DID_REG DIDR0 +#define PA1DID_REG DIDR0 + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* BPCR */ +#define CHCD_REG BPCR +#define DHCD_REG BPCR +#define COCD_REG BPCR +#define DOCD_REG BPCR +#define SCD_REG BPCR +#define EPID_REG BPCR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define ICS1_REG TCCR1A +#define ICES1_REG TCCR1A +#define ICNC1_REG TCCR1A +#define ICEN1_REG TCCR1A +#define TCW1_REG TCCR1A + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B + +/* BPCHCD */ +#define CHCDL0_REG BPCHCD +#define CHCDL1_REG BPCHCD +#define CHCDL2_REG BPCHCD +#define CHCDL3_REG BPCHCD +#define CHCDL4_REG BPCHCD +#define CHCDL5_REG BPCHCD +#define CHCDL6_REG BPCHCD +#define CHCDL7_REG BPCHCD + +/* CADCSRC */ +#define CADVSE_REG CADCSRC + +/* CADCSRB */ +#define CADICIF_REG CADCSRB +#define CADRCIF_REG CADCSRB +#define CADACIF_REG CADCSRB +#define CADICIE_REG CADCSRB +#define CADRCIE_REG CADCSRB +#define CADACIE_REG CADCSRB + +/* CADCSRA */ +#define CADSE_REG CADCSRA +#define CADSI0_REG CADCSRA +#define CADSI1_REG CADCSRA +#define CADAS0_REG CADCSRA +#define CADAS1_REG CADCSRA +#define CADUB_REG CADCSRA +#define CADPOL_REG CADCSRA +#define CADEN_REG CADCSRA + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* BPPLR */ +#define BPPL_REG BPPLR +#define BPPLE_REG BPPLR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* CADRDC */ +#define CADRDC0_REG CADRDC +#define CADRDC1_REG CADRDC +#define CADRDC2_REG CADRDC +#define CADRDC3_REG CADRDC +#define CADRDC4_REG CADRDC +#define CADRDC5_REG CADRDC +#define CADRDC6_REG CADRDC +#define CADRDC7_REG CADRDC + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define ICS0_REG TCCR0A +#define ICES0_REG TCCR0A +#define ICNC0_REG TCCR0A +#define ICEN0_REG TCCR0A +#define TCW0_REG TCCR0A + +/* BPDHCD */ +#define DHCDL0_REG BPDHCD +#define DHCDL1_REG BPDHCD +#define DHCDL2_REG BPDHCD +#define DHCDL3_REG BPDHCD +#define DHCDL4_REG BPDHCD +#define DHCDL5_REG BPDHCD +#define DHCDL6_REG BPDHCD +#define DHCDL7_REG BPDHCD + +/* TWBCSR */ +#define TWBCIP_REG TWBCSR +#define TWBDT0_REG TWBCSR +#define TWBDT1_REG TWBCSR +#define TWBCIE_REG TWBCSR +#define TWBCIF_REG TWBCSR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* BGCRR */ +#define BGCR0_REG BGCRR +#define BGCR1_REG BGCRR +#define BGCR2_REG BGCRR +#define BGCR3_REG BGCRR +#define BGCR4_REG BGCRR +#define BGCR5_REG BGCRR +#define BGCR6_REG BGCRR +#define BGCR7_REG BGCRR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR + +/* FCSR */ +#define CFE_REG FCSR +#define DFE_REG FCSR +#define CPS_REG FCSR +#define DUVRD_REG FCSR + +/* VADMUX */ +#define VADMUX0_REG VADMUX +#define VADMUX1_REG VADMUX +#define VADMUX2_REG VADMUX +#define VADMUX3_REG VADMUX + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BODRF_REG MCUSR +#define WDRF_REG MCUSR +#define OCDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* BPIFR */ +#define CHCIF_REG BPIFR +#define DHCIF_REG BPIFR +#define COCIF_REG BPIFR +#define DOCIF_REG BPIFR +#define SCIF_REG BPIFR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* VADCSR */ +#define VADCCIE_REG VADCSR +#define VADCCIF_REG VADCSR +#define VADSC_REG VADCSR +#define VADEN_REG VADCSR + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define CKOE_REG MCUCR + +/* CBCR */ +#define CBE1_REG CBCR +#define CBE2_REG CBCR +#define CBE3_REG CBCR +#define CBE4_REG CBCR + +/* CADRCC */ +#define CADRCC0_REG CADRCC +#define CADRCC1_REG CADRCC +#define CADRCC2_REG CADRCC +#define CADRCC3_REG CADRCC +#define CADRCC4_REG CADRCC +#define CADRCC5_REG CADRCC +#define CADRCC6_REG CADRCC +#define CADRCC7_REG CADRCC + +/* BPOCTR */ +#define OCPT0_REG BPOCTR +#define OCPT1_REG BPOCTR +#define OCPT2_REG BPOCTR +#define OCPT3_REG BPOCTR +#define OCPT4_REG BPOCTR +#define OCPT5_REG BPOCTR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA + +/* BPDOCD */ +#define DOCDL0_REG BPDOCD +#define DOCDL1_REG BPDOCD +#define DOCDL2_REG BPDOCD +#define DOCDL3_REG BPDOCD +#define DOCDL4_REG BPDOCD +#define DOCDL5_REG BPDOCD +#define DOCDL6_REG BPDOCD +#define DOCDL7_REG BPDOCD + +/* BPSCTR */ +#define SCPT0_REG BPSCTR +#define SCPT1_REG BPSCTR +#define SCPT2_REG BPSCTR +#define SCPT3_REG BPSCTR +#define SCPT4_REG BPSCTR +#define SCPT5_REG BPSCTR +#define SCPT6_REG BPSCTR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* BPHCTR */ +#define HCPT0_REG BPHCTR +#define HCPT1_REG BPHCTR +#define HCPT2_REG BPHCTR +#define HCPT3_REG BPHCTR +#define HCPT4_REG BPHCTR +#define HCPT5_REG BPHCTR + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* PRR0 */ +#define PRVADC_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRSPI_REG PRR0 +#define PRVRM_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ROCR */ +#define ROCWIE_REG ROCR +#define ROCWIF_REG ROCR +#define ROCD_REG ROCR +#define ROCS_REG ROCR + +/* OCR0B */ +#define OCR0B0_REG OCR0B +#define OCR0B1_REG OCR0B +#define OCR0B2_REG OCR0B +#define OCR0B3_REG OCR0B +#define OCR0B4_REG OCR0B +#define OCR0B5_REG OCR0B +#define OCR0B6_REG OCR0B +#define OCR0B7_REG OCR0B + +/* CADICH */ +#define CADICH0_REG CADICH +#define CADICH1_REG CADICH +#define CADICH2_REG CADICH +#define CADICH3_REG CADICH +#define CADICH4_REG CADICH +#define CADICH5_REG CADICH +#define CADICH6_REG CADICH +#define CADICH7_REG CADICH + +/* CADICL */ +#define CADICL0_REG CADICL +#define CADICL1_REG CADICL +#define CADICL2_REG CADICL +#define CADICL3_REG CADICL +#define CADICL4_REG CADICL +#define CADICL5_REG CADICL +#define CADICL6_REG CADICL +#define CADICL7_REG CADICL + +/* OSICSR */ +#define OSIEN_REG OSICSR +#define OSIST_REG OSICSR +#define OSISEL0_REG OSICSR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define LBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* CHGDCSR */ +#define CHGDIE_REG CHGDCSR +#define CHGDIF_REG CHGDCSR +#define CHGDISC0_REG CHGDCSR +#define CHGDISC1_REG CHGDCSR +#define BATTPVL_REG CHGDCSR + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 +#define ICIE0_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* BGCCR */ +#define BGCC0_REG BGCCR +#define BGCC1_REG BGCCR +#define BGCC2_REG BGCCR +#define BGCC3_REG BGCCR +#define BGCC4_REG BGCCR +#define BGCC5_REG BGCCR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT4_REG PCMSK1 +#define PCINT5_REG PCMSK1 +#define PCINT6_REG PCMSK1 +#define PCINT7_REG PCMSK1 +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* BGCSR */ +#define BGSCDIE_REG BGCSR +#define BGSCDIF_REG BGCSR +#define BGSCDE_REG BGCSR +#define BGD_REG BGCSR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 +#define ICF0_REG TIFR0 + +/* pins mapping */ + + + + + + + + + + + diff --git a/include/aversive/parts/ATmega32M1.h b/include/aversive/parts/ATmega32M1.h new file mode 100644 index 0000000..a234d60 --- /dev/null +++ b/include/aversive/parts/ATmega32M1.h @@ -0,0 +1,1553 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* LINBTR */ +#define LBT0_REG LINBTR +#define LBT1_REG LINBTR +#define LBT2_REG LINBTR +#define LBT3_REG LINBTR +#define LBT4_REG LINBTR +#define LBT5_REG LINBTR +#define LDISR_REG LINBTR + +/* POCR1RAL */ +#define POCR1RA_0_REG POCR1RAL +#define POCR1RA_1_REG POCR1RAL +#define POCR1RA_2_REG POCR1RAL +#define POCR1RA_3_REG POCR1RAL +#define POCR1RA_4_REG POCR1RAL +#define POCR1RA_5_REG POCR1RAL +#define POCR1RA_6_REG POCR1RAL +#define POCR1RA_7_REG POCR1RAL + +/* LINIDR */ +#define LID0_REG LINIDR +#define LID1_REG LINIDR +#define LID2_REG LINIDR +#define LID3_REG LINIDR +#define LID4_REG LINIDR +#define LID5_REG LINIDR +#define LP0_REG LINIDR +#define LP1_REG LINIDR + +/* POCR1RAH */ +#define POCR1RA_8_REG POCR1RAH +#define POCR1RA_9_REG POCR1RAH +#define POCR1RA_00_REG POCR1RAH +#define POCR1RA_01_REG POCR1RAH + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* LINSEL */ +#define LINDX0_REG LINSEL +#define LINDX1_REG LINSEL +#define LINDX2_REG LINSEL +#define LAINC_REG LINSEL + +/* LINCR */ +#define LCMD0_REG LINCR +#define LCMD1_REG LINCR +#define LCMD2_REG LINCR +#define LENA_REG LINCR +#define LCONF0_REG LINCR +#define LCONF1_REG LINCR +#define LIN13_REG LINCR +#define LSWRES_REG LINCR + +/* PIM */ +#define PEOPE_REG PIM +#define PEVE0_REG PIM +#define PEVE1_REG PIM +#define PEVE2_REG PIM + +/* POCR2SBL */ +#define POCR2SB_0_REG POCR2SBL +#define POCR2SB_1_REG POCR2SBL +#define POCR2SB_2_REG POCR2SBL +#define POCR2SB_3_REG POCR2SBL +#define POCR2SB_4_REG POCR2SBL +#define POCR2SB_5_REG POCR2SBL +#define POCR2SB_6_REG POCR2SBL +#define POCR2SB_7_REG POCR2SBL + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* POCR2SBH */ +#define POCR2SB_8_REG POCR2SBH +#define POCR2SB_9_REG POCR2SBH +#define POCR2SB_00_REG POCR2SBH +#define POCR2SB_01_REG POCR2SBH + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* AC1CON */ +#define AC1M0_REG AC1CON +#define AC1M1_REG AC1CON +#define AC1M2_REG AC1CON +#define AC1ICE_REG AC1CON +#define AC1IS0_REG AC1CON +#define AC1IS1_REG AC1CON +#define AC1IE_REG AC1CON +#define AC1EN_REG AC1CON + +/* PRR */ +#define PRADC_REG PRR +#define PRLIN_REG PRR +#define PRSPI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRPSC_REG PRR +#define PRCAN_REG PRR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* LINBRRL */ +#define LDIV0_REG LINBRRL +#define LDIV1_REG LINBRRL +#define LDIV2_REG LINBRRL +#define LDIV3_REG LINBRRL +#define LDIV4_REG LINBRRL +#define LDIV5_REG LINBRRL +#define LDIV6_REG LINBRRL +#define LDIV7_REG LINBRRL + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH + +/* LINBRRH */ +#define LDIV8_REG LINBRRH +#define LDIV9_REG LINBRRH +#define LDIV10_REG LINBRRH +#define LDIV11_REG LINBRRH + +/* CANGSTA */ +#define ERRP_REG CANGSTA +#define BOFF_REG CANGSTA +#define ENFG_REG CANGSTA +#define RXBSY_REG CANGSTA +#define TXBSY_REG CANGSTA +#define OVFG_REG CANGSTA + +/* CANGCON */ +#define SWRES_REG CANGCON +#define ENASTB_REG CANGCON +#define TEST_REG CANGCON +#define LISTEN_REG CANGCON +#define SYNTTC_REG CANGCON +#define TTC_REG CANGCON +#define OVRQ_REG CANGCON +#define ABRQ_REG CANGCON + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* AMP1CSR */ +#define AMP1TS0_REG AMP1CSR +#define AMP1TS1_REG AMP1CSR +#define AMP1TS2_REG AMP1CSR +#define AMPCMP1_REG AMP1CSR +#define AMP1G0_REG AMP1CSR +#define AMP1G1_REG AMP1CSR +#define AMP1IS_REG AMP1CSR +#define AMP1EN_REG AMP1CSR + +/* AC2CON */ +#define AC2M0_REG AC2CON +#define AC2M1_REG AC2CON +#define AC2M2_REG AC2CON +#define AC2IS0_REG AC2CON +#define AC2IS1_REG AC2CON +#define AC2IE_REG AC2CON +#define AC2EN_REG AC2CON + +/* CANPAGE */ +#define INDX0_REG CANPAGE +#define INDX1_REG CANPAGE +#define INDX2_REG CANPAGE +#define AINC_REG CANPAGE +#define MOBNB0_REG CANPAGE +#define MOBNB1_REG CANPAGE +#define MOBNB2_REG CANPAGE +#define MOBNB3_REG CANPAGE + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* LINENIR */ +#define LENRXOK_REG LINENIR +#define LENTXOK_REG LINENIR +#define LENIDOK_REG LINENIR +#define LENERR_REG LINENIR + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* POCR2RAL */ +#define POCR2RA_0_REG POCR2RAL +#define POCR2RA_1_REG POCR2RAL +#define POCR2RA_2_REG POCR2RAL +#define POCR2RA_3_REG POCR2RAL +#define POCR2RA_4_REG POCR2RAL +#define POCR2RA_5_REG POCR2RAL +#define POCR2RA_6_REG POCR2RAL +#define POCR2RA_7_REG POCR2RAL + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 +#define AMP0ND_REG DIDR1 +#define AMP0PD_REG DIDR1 +#define ACMP0D_REG DIDR1 +#define AMP2PD_REG DIDR1 + +/* POCR2RAH */ +#define POCR2RA_8_REG POCR2RAH +#define POCR2RA_9_REG POCR2RAH +#define POCR2RA_00_REG POCR2RAH +#define POCR2RA_01_REG POCR2RAH + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* POCR1SAH */ +#define POCR1SA_8_REG POCR1SAH +#define POCR1SA_9_REG POCR1SAH +#define POCR1SA_00_REG POCR1SAH +#define POCR1SA_01_REG POCR1SAH + +/* POCR1SAL */ +#define POCR1SA_0_REG POCR1SAL +#define POCR1SA_1_REG POCR1SAL +#define POCR1SA_2_REG POCR1SAL +#define POCR1SA_3_REG POCR1SAL +#define POCR1SA_4_REG POCR1SAL +#define POCR1SA_5_REG POCR1SAL +#define POCR1SA_6_REG POCR1SAL +#define POCR1SA_7_REG POCR1SAL + +/* CANIDM1 */ +#define IDMSK21_REG CANIDM1 +#define IDMSK22_REG CANIDM1 +#define IDMSK23_REG CANIDM1 +#define IDMSK24_REG CANIDM1 +#define IDMSK25_REG CANIDM1 +#define IDMSK26_REG CANIDM1 +#define IDMSK27_REG CANIDM1 +#define IDMSK28_REG CANIDM1 + +/* CANIDM3 */ +#define IDMSK5_REG CANIDM3 +#define IDMSK6_REG CANIDM3 +#define IDMSK7_REG CANIDM3 +#define IDMSK8_REG CANIDM3 +#define IDMSK9_REG CANIDM3 +#define IDMSK10_REG CANIDM3 +#define IDMSK11_REG CANIDM3 +#define IDMSK12_REG CANIDM3 + +/* CANIDM2 */ +#define IDMSK13_REG CANIDM2 +#define IDMSK14_REG CANIDM2 +#define IDMSK15_REG CANIDM2 +#define IDMSK16_REG CANIDM2 +#define IDMSK17_REG CANIDM2 +#define IDMSK18_REG CANIDM2 +#define IDMSK19_REG CANIDM2 +#define IDMSK20_REG CANIDM2 + +/* CANIDM4 */ +#define IDEMSK_REG CANIDM4 +#define RTRMSK_REG CANIDM4 +#define IDMSK0_REG CANIDM4 +#define IDMSK1_REG CANIDM4 +#define IDMSK2_REG CANIDM4 +#define IDMSK3_REG CANIDM4 +#define IDMSK4_REG CANIDM4 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* PMIC2 */ +#define PRFM20_REG PMIC2 +#define PRFM21_REG PMIC2 +#define PRFM22_REG PMIC2 +#define PAOC2_REG PMIC2 +#define PFLTE2_REG PMIC2 +#define PELEV2_REG PMIC2 +#define PISEL2_REG PMIC2 +#define POVEN2_REG PMIC2 + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* PMIC1 */ +#define PRFM10_REG PMIC1 +#define PRFM11_REG PMIC1 +#define PRFM12_REG PMIC1 +#define PAOC1_REG PMIC1 +#define PFLTE1_REG PMIC1 +#define PELEV1_REG PMIC1 +#define PISEL1_REG PMIC1 +#define POVEN1_REG PMIC1 + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* PCTL */ +#define PRUN_REG PCTL +#define PCCYC_REG PCTL +#define PCLKSEL_REG PCTL +#define PPRE0_REG PCTL +#define PPRE1_REG PCTL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* CANGIT */ +#define AERG_REG CANGIT +#define FERG_REG CANGIT +#define CERG_REG CANGIT +#define SERG_REG CANGIT +#define BXOK_REG CANGIT +#define OVRTIM_REG CANGIT +#define BOFFIT_REG CANGIT +#define CANIT_REG CANGIT + +/* AC3CON */ +#define AC3M0_REG AC3CON +#define AC3M1_REG AC3CON +#define AC3M2_REG AC3CON +#define AC3IS0_REG AC3CON +#define AC3IS1_REG AC3CON +#define AC3IE_REG AC3CON +#define AC3EN_REG AC3CON + +/* LINERR */ +#define LBERR_REG LINERR +#define LCERR_REG LINERR +#define LPERR_REG LINERR +#define LSERR_REG LINERR +#define LFERR_REG LINERR +#define LOVERR_REG LINERR +#define LTOERR_REG LINERR +#define LABORT_REG LINERR + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* CANGIE */ +#define ENOVRT_REG CANGIE +#define ENERG_REG CANGIE +#define ENBX_REG CANGIE +#define ENERR_REG CANGIE +#define ENTX_REG CANGIE +#define ENRX_REG CANGIE +#define ENBOFF_REG CANGIE +#define ENIT_REG CANGIE + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* CANIE2 */ +#define IEMOB0_REG CANIE2 +#define IEMOB1_REG CANIE2 +#define IEMOB2_REG CANIE2 +#define IEMOB3_REG CANIE2 +#define IEMOB4_REG CANIE2 +#define IEMOB5_REG CANIE2 + +/* POCR0RAL */ +#define POCR0RA_0_REG POCR0RAL +#define POCR0RA_1_REG POCR0RAL +#define POCR0RA_2_REG POCR0RAL +#define POCR0RA_3_REG POCR0RAL +#define POCR0RA_4_REG POCR0RAL +#define POCR0RA_5_REG POCR0RAL +#define POCR0RA_6_REG POCR0RAL +#define POCR0RA_7_REG POCR0RAL + +/* CANSIT2 */ +#define SIT0_REG CANSIT2 +#define SIT1_REG CANSIT2 +#define SIT2_REG CANSIT2 +#define SIT3_REG CANSIT2 +#define SIT4_REG CANSIT2 +#define SIT5_REG CANSIT2 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* POCR0RAH */ +#define POCR0RA_8_REG POCR0RAH +#define POCR0RA_9_REG POCR0RAH +#define POCR0RA_00_REG POCR0RAH +#define POCR0RA_01_REG POCR0RAH + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* POCR2SAH */ +#define POCR2SA_8_REG POCR2SAH +#define POCR2SA_9_REG POCR2SAH +#define POCR2SA_00_REG POCR2SAH +#define POCR2SA_01_REG POCR2SAH + +/* POCR2SAL */ +#define POCR2SA_0_REG POCR2SAL +#define POCR2SA_1_REG POCR2SAL +#define POCR2SA_2_REG POCR2SAL +#define POCR2SA_3_REG POCR2SAL +#define POCR2SA_4_REG POCR2SAL +#define POCR2SA_5_REG POCR2SAL +#define POCR2SA_6_REG POCR2SAL +#define POCR2SA_7_REG POCR2SAL + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* CANIDT4 */ +#define RB0TAG_REG CANIDT4 +#define RB1TAG_REG CANIDT4 +#define RTRTAG_REG CANIDT4 +#define IDT0_REG CANIDT4 +#define IDT1_REG CANIDT4 +#define IDT2_REG CANIDT4 +#define IDT3_REG CANIDT4 +#define IDT4_REG CANIDT4 + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* CANIDT2 */ +#define IDT13_REG CANIDT2 +#define IDT14_REG CANIDT2 +#define IDT15_REG CANIDT2 +#define IDT16_REG CANIDT2 +#define IDT17_REG CANIDT2 +#define IDT18_REG CANIDT2 +#define IDT19_REG CANIDT2 +#define IDT20_REG CANIDT2 + +/* CANIDT3 */ +#define IDT5_REG CANIDT3 +#define IDT6_REG CANIDT3 +#define IDT7_REG CANIDT3 +#define IDT8_REG CANIDT3 +#define IDT9_REG CANIDT3 +#define IDT10_REG CANIDT3 +#define IDT11_REG CANIDT3 +#define IDT12_REG CANIDT3 + +/* CANIDT1 */ +#define IDT21_REG CANIDT1 +#define IDT22_REG CANIDT1 +#define IDT23_REG CANIDT1 +#define IDT24_REG CANIDT1 +#define IDT25_REG CANIDT1 +#define IDT26_REG CANIDT1 +#define IDT27_REG CANIDT1 +#define IDT28_REG CANIDT1 + +/* PSYNC */ +#define PSYNC00_REG PSYNC +#define PSYNC01_REG PSYNC +#define PSYNC10_REG PSYNC +#define PSYNC11_REG PSYNC +#define PSYNC20_REG PSYNC +#define PSYNC21_REG PSYNC + +/* GTCCR */ +#define PSR10_REG GTCCR +#define ICPSEL1_REG GTCCR +#define TSM_REG GTCCR +#define PSRSYNC_REG GTCCR + +/* CANCDMOB */ +#define DLC0_REG CANCDMOB +#define DLC1_REG CANCDMOB +#define DLC2_REG CANCDMOB +#define DLC3_REG CANCDMOB +#define IDE_REG CANCDMOB +#define RPLV_REG CANCDMOB +#define CONMOB0_REG CANCDMOB +#define CONMOB1_REG CANCDMOB + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* CANHPMOB */ +#define CGP0_REG CANHPMOB +#define CGP1_REG CANHPMOB +#define CGP2_REG CANHPMOB +#define CGP3_REG CANHPMOB +#define HPMOB0_REG CANHPMOB +#define HPMOB1_REG CANHPMOB +#define HPMOB2_REG CANHPMOB +#define HPMOB3_REG CANHPMOB + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* POCR1SBL */ +#define POCR1SB_0_REG POCR1SBL +#define POCR1SB_1_REG POCR1SBL +#define POCR1SB_2_REG POCR1SBL +#define POCR1SB_3_REG POCR1SBL +#define POCR1SB_4_REG POCR1SBL +#define POCR1SB_5_REG POCR1SBL +#define POCR1SB_6_REG POCR1SBL +#define POCR1SB_7_REG POCR1SBL + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLF_REG PLLCSR + +/* POCR1SBH */ +#define POCR1SB_8_REG POCR1SBH +#define POCR1SB_9_REG POCR1SBH +#define POCR1SB_00_REG POCR1SBH +#define POCR1SB_01_REG POCR1SBH + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* AMP2CSR */ +#define AMP2TS0_REG AMP2CSR +#define AMP2TS1_REG AMP2CSR +#define AMP2TS2_REG AMP2CSR +#define AMPCMP2_REG AMP2CSR +#define AMP2G0_REG AMP2CSR +#define AMP2G1_REG AMP2CSR +#define AMP2IS_REG AMP2CSR +#define AMP2EN_REG AMP2CSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* LINDAT */ +#define LDATA0_REG LINDAT +#define LDATA1_REG LINDAT +#define LDATA2_REG LINDAT +#define LDATA3_REG LINDAT +#define LDATA4_REG LINDAT +#define LDATA5_REG LINDAT +#define LDATA6_REG LINDAT +#define LDATA7_REG LINDAT + +/* POCR0SAH */ +#define POCR0SA_8_REG POCR0SAH +#define POCR0SA_9_REG POCR0SAH +#define POCR0SA_00_REG POCR0SAH +#define POCR0SA_01_REG POCR0SAH + +/* POCR_RBL */ +#define POCR_RB_0_REG POCR_RBL +#define POCR_RB_1_REG POCR_RBL +#define POCR_RB_2_REG POCR_RBL +#define POCR_RB_3_REG POCR_RBL +#define POCR_RB_4_REG POCR_RBL +#define POCR_RB_5_REG POCR_RBL +#define POCR_RB_6_REG POCR_RBL +#define POCR_RB_7_REG POCR_RBL + +/* POCR0SAL */ +#define POCR0SA_0_REG POCR0SAL +#define POCR0SA_1_REG POCR0SAL +#define POCR0SA_2_REG POCR0SAL +#define POCR0SA_3_REG POCR0SAL +#define POCR0SA_4_REG POCR0SAL +#define POCR0SA_5_REG POCR0SAL +#define POCR0SA_6_REG POCR0SAL +#define POCR0SA_7_REG POCR0SAL + +/* POCR_RBH */ +#define POCR_RB_8_REG POCR_RBH +#define POCR_RB_9_REG POCR_RBH +#define POCR_RB_00_REG POCR_RBH +#define POCR_RB_01_REG POCR_RBH + +/* LINDLR */ +#define LRXDL0_REG LINDLR +#define LRXDL1_REG LINDLR +#define LRXDL2_REG LINDLR +#define LRXDL3_REG LINDLR +#define LTXDL0_REG LINDLR +#define LTXDL1_REG LINDLR +#define LTXDL2_REG LINDLR +#define LTXDL3_REG LINDLR + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define SPIPS_REG MCUCR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* CANSTMOB */ +#define AERR_REG CANSTMOB +#define FERR_REG CANSTMOB +#define CERR_REG CANSTMOB +#define SERR_REG CANSTMOB +#define BERR_REG CANSTMOB +#define RXOK_REG CANSTMOB +#define TXOK_REG CANSTMOB +#define DLCW_REG CANSTMOB + +/* PIFR */ +#define PEOP_REG PIFR +#define PEV0_REG PIFR +#define PEV1_REG PIFR +#define PEV2_REG PIFR + +/* LINSIR */ +#define LRXOK_REG LINSIR +#define LTXOK_REG LINSIR +#define LIDOK_REG LINSIR +#define LERR_REG LINSIR +#define LBUSY_REG LINSIR +#define LIDST0_REG LINSIR +#define LIDST1_REG LINSIR +#define LIDST2_REG LINSIR + +/* DACH */ +#define DACH0_REG DACH +#define DACH1_REG DACH +#define DACH2_REG DACH +#define DACH3_REG DACH +#define DACH4_REG DACH +#define DACH5_REG DACH +#define DACH6_REG DACH +#define DACH7_REG DACH + +/* DACL */ +#define DACL0_REG DACL +#define DACL1_REG DACL +#define DACL2_REG DACL +#define DACL3_REG DACL +#define DACL4_REG DACL +#define DACL5_REG DACL +#define DACL6_REG DACL +#define DACL7_REG DACL + +/* CANEN2 */ +#define ENMOB0_REG CANEN2 +#define ENMOB1_REG CANEN2 +#define ENMOB2_REG CANEN2 +#define ENMOB3_REG CANEN2 +#define ENMOB4_REG CANEN2 +#define ENMOB5_REG CANEN2 + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define AREFEN_REG ADCSRB +#define ISRCEN_REG ADCSRB +#define ADHSM_REG ADCSRB + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* POCR0SBL */ +#define POCR0SB_0_REG POCR0SBL +#define POCR0SB_1_REG POCR0SBL +#define POCR0SB_2_REG POCR0SBL +#define POCR0SB_3_REG POCR0SBL +#define POCR0SB_4_REG POCR0SBL +#define POCR0SB_5_REG POCR0SBL +#define POCR0SB_6_REG POCR0SBL +#define POCR0SB_7_REG POCR0SBL + +/* ACSR */ +#define AC0O_REG ACSR +#define AC1O_REG ACSR +#define AC2O_REG ACSR +#define AC3O_REG ACSR +#define AC0IF_REG ACSR +#define AC1IF_REG ACSR +#define AC2IF_REG ACSR +#define AC3IF_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PMIC0 */ +#define PRFM00_REG PMIC0 +#define PRFM01_REG PMIC0 +#define PRFM02_REG PMIC0 +#define PAOC0_REG PMIC0 +#define PFLTE0_REG PMIC0 +#define PELEV0_REG PMIC0 +#define PISEL0_REG PMIC0 +#define POVEN0_REG PMIC0 + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* POC */ +#define POEN0A_REG POC +#define POEN0B_REG POC +#define POEN1A_REG POC +#define POEN1B_REG POC +#define POEN2A_REG POC +#define POEN2B_REG POC + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PCNF */ +#define POPA_REG PCNF +#define POPB_REG PCNF +#define PMODE_REG PCNF +#define PULOCK_REG PCNF + +/* CANBT2 */ +#define PRS0_REG CANBT2 +#define PRS1_REG CANBT2 +#define PRS2_REG CANBT2 +#define SJW0_REG CANBT2 +#define SJW1_REG CANBT2 + +/* CANBT3 */ +#define SMP_REG CANBT3 +#define PHS10_REG CANBT3 +#define PHS11_REG CANBT3 +#define PHS12_REG CANBT3 +#define PHS20_REG CANBT3 +#define PHS21_REG CANBT3 +#define PHS22_REG CANBT3 + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* CANBT1 */ +#define BRP0_REG CANBT1 +#define BRP1_REG CANBT1 +#define BRP2_REG CANBT1 +#define BRP3_REG CANBT1 +#define BRP4_REG CANBT1 +#define BRP5_REG CANBT1 + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* AMP0CSR */ +#define AMP0TS0_REG AMP0CSR +#define AMP0TS1_REG AMP0CSR +#define AMP0TS2_REG AMP0CSR +#define AMPCMP0_REG AMP0CSR +#define AMP0G0_REG AMP0CSR +#define AMP0G1_REG AMP0CSR +#define AMP0IS_REG AMP0CSR +#define AMP0EN_REG AMP0CSR + +/* DACON */ +#define DAEN_REG DACON +#define DALA_REG DACON +#define DATS0_REG DACON +#define DATS1_REG DACON +#define DATS2_REG DACON +#define DAATE_REG DACON + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* AC0CON */ +#define AC0M0_REG AC0CON +#define AC0M1_REG AC0CON +#define AC0M2_REG AC0CON +#define ACCKSEL_REG AC0CON +#define AC0IS0_REG AC0CON +#define AC0IS1_REG AC0CON +#define AC0IE_REG AC0CON +#define AC0EN_REG AC0CON + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* POCR0SBH */ +#define POCR0SB_8_REG POCR0SBH +#define POCR0SB_9_REG POCR0SBH +#define POCR0SB_00_REG POCR0SBH +#define POCR0SB_01_REG POCR0SBH + +/* pins mapping */ +#define MISO_PORT PORTB +#define MISO_BIT 0 +#define PSCOUT2A_PORT PORTB +#define PSCOUT2A_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MOSI_PORT PORTB +#define MOSI_BIT 1 +#define PSCOUT2B_PORT PORTB +#define PSCOUT2B_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define ADC5_PORT PORTB +#define ADC5_BIT 2 +#define INT1_PORT PORTB +#define INT1_BIT 2 +#define ACMPN0_PORT PORTB +#define ACMPN0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define AMP0-_PORT PORTB +#define AMP0-_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define AMP0+_PORT PORTB +#define AMP0+_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define ADC6_PORT PORTB +#define ADC6_BIT 5 +#define INT2_PORT PORTB +#define INT2_BIT 5 +#define ACMPN1_PORT PORTB +#define ACMPN1_BIT 5 +#define AMP2-_PORT PORTB +#define AMP2-_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define ADC7_PORT PORTB +#define ADC7_BIT 6 +#define PSCOUT1B_PORT PORTB +#define PSCOUT1B_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define ADC4_PORT PORTB +#define ADC4_BIT 7 +#define PSCOUT0B_PORT PORTB +#define PSCOUT0B_BIT 7 +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define INT3_PORT PORTC +#define INT3_BIT 0 +#define PSCOUT1A_PORT PORTC +#define PSCOUT1A_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define PSCIN1_PORT PORTC +#define PSCIN1_BIT 1 +#define OC1B_PORT PORTC +#define OC1B_BIT 1 +#define SS_A_PORT PORTC +#define SS_A_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define T0_PORT PORTC +#define T0_BIT 2 +#define TXCAN_PORT PORTC +#define TXCAN_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define T1_PORT PORTC +#define T1_BIT 3 +#define RXCAN_PORT PORTC +#define RXCAN_BIT 3 +#define ICP1B_PORT PORTC +#define ICP1B_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC8_PORT PORTC +#define ADC8_BIT 4 +#define AMP1-_PORT PORTC +#define AMP1-_BIT 4 +#define ACMPN3_PORT PORTC +#define ACMPN3_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC9_PORT PORTC +#define ADC9_BIT 5 +#define AMP1+_PORT PORTC +#define AMP1+_BIT 5 +#define ACMP3_PORT PORTC +#define ACMP3_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define ADC10_PORT PORTC +#define ADC10_BIT 6 +#define ACMP1_PORT PORTC +#define ACMP1_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define D2A_PORT PORTC +#define D2A_BIT 7 +#define AMP2+_PORT PORTC +#define AMP2+_BIT 7 +#define PCINT15_PORT PORTC +#define PCINT15_BIT 7 + +#define PSCOUT0A_PORT PORTD +#define PSCOUT0A_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define PSCIN0_PORT PORTD +#define PSCIN0_BIT 1 +#define CLK0_PORT PORTD +#define CLK0_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define PSCIN2_PORT PORTD +#define PSCIN2_BIT 2 +#define OC1A_PORT PORTD +#define OC1A_BIT 2 +#define MISO_A_PORT PORTD +#define MISO_A_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define TXD_PORT PORTD +#define TXD_BIT 3 +#define TXLIN_PORT PORTD +#define TXLIN_BIT 3 +#define OC0A_PORT PORTD +#define OC0A_BIT 3 +#define SS_PORT PORTD +#define SS_BIT 3 +#define MOSI_A_PORT PORTD +#define MOSI_A_BIT 3 +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 + +#define ADC1_PORT PORTD +#define ADC1_BIT 4 +#define RXD_PORT PORTD +#define RXD_BIT 4 +#define RXLIN_PORT PORTD +#define RXLIN_BIT 4 +#define ICP1A_PORT PORTD +#define ICP1A_BIT 4 +#define SCK_A_PORT PORTD +#define SCK_A_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define ADC2_PORT PORTD +#define ADC2_BIT 5 +#define ACMP2_PORT PORTD +#define ACMP2_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define ADC3_PORT PORTD +#define ADC3_BIT 6 +#define ACMPN2_PORT PORTD +#define ACMPN2_BIT 6 +#define INT0_PORT PORTD +#define INT0_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define ACMP0_PORT PORTD +#define ACMP0_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + +#define RESET_PORT PORTE +#define RESET_BIT 0 +#define OCD_PORT PORTE +#define OCD_BIT 0 +#define PCINT24_PORT PORTE +#define PCINT24_BIT 0 + +#define OC0B_PORT PORTE +#define OC0B_BIT 1 +#define XTAL1_PORT PORTE +#define XTAL1_BIT 1 +#define PCINT25_PORT PORTE +#define PCINT25_BIT 1 + +#define ADC0_PORT PORTE +#define ADC0_BIT 2 +#define XTAL2_PORT PORTE +#define XTAL2_BIT 2 +#define PCINT26_PORT PORTE +#define PCINT26_BIT 2 + + diff --git a/include/aversive/parts/ATmega32U4.h b/include/aversive/parts/ATmega32U4.h new file mode 100644 index 0000000..37b04dc --- /dev/null +++ b/include/aversive/parts/ATmega32U4.h @@ -0,0 +1,1317 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ + + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW3_NUM 2 +#define SIG_OVERFLOW4_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE4_NUM 8 +#define SIG_OUTPUT_COMPARE4A_NUM 9 +#define SIG_OUTPUT_COMPARE4B_NUM 10 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 11 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM4_NUM 8 +#define PWM4A_NUM 9 +#define PWM4B_NUM 10 +#define PWM_TOTAL_NUM 11 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* UECFG1X */ +#define ALLOC_REG UECFG1X +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE2_REG PORTE +#define PORTE6_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define DAT0_REG UEDATX +#define DAT1_REG UEDATX +#define DAT2_REG UEDATX +#define DAT3_REG UEDATX +#define DAT4_REG UEDATX +#define DAT5_REG UEDATX +#define DAT6_REG UEDATX +#define DAT7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* CLKSEL1 */ +#define EXCKSEL0_REG CLKSEL1 +#define EXCKSEL1_REG CLKSEL1 +#define EXCKSEL2_REG CLKSEL1 +#define EXCKSEL3_REG CLKSEL1 +#define RCCKSEL0_REG CLKSEL1 +#define RCCKSEL1_REG CLKSEL1 +#define RCCKSEL2_REG CLKSEL1 +#define RCCKSEL3_REG CLKSEL1 + +/* CLKSEL0 */ +#define CLKS_REG CLKSEL0 +#define EXTE_REG CLKSEL0 +#define RCE_REG CLKSEL0 +#define EXSUT0_REG CLKSEL0 +#define EXSUT1_REG CLKSEL0 +#define RCSUT0_REG CLKSEL0 +#define RCSUT1_REG CLKSEL0 + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* OCR4A */ +#define OCR4A0_REG OCR4A +#define OCR4A1_REG OCR4A +#define OCR4A2_REG OCR4A +#define OCR4A3_REG OCR4A +#define OCR4A4_REG OCR4A +#define OCR4A5_REG OCR4A +#define OCR4A6_REG OCR4A +#define OCR4A7_REG OCR4A + +/* OCR4C */ +#define OCR4C0_REG OCR4C +#define OCR4C1_REG OCR4C +#define OCR4C2_REG OCR4C +#define OCR4C3_REG OCR4C +#define OCR4C4_REG OCR4C +#define OCR4C5_REG OCR4C +#define OCR4C6_REG OCR4C +#define OCR4C7_REG OCR4C + +/* OCR4B */ +#define OCR4B0_REG OCR4B +#define OCR4B1_REG OCR4B +#define OCR4B2_REG OCR4B +#define OCR4B3_REG OCR4B +#define OCR4B4_REG OCR4B +#define OCR4B5_REG OCR4B +#define OCR4B6_REG OCR4B +#define OCR4B7_REG OCR4B + +/* OCR4D */ +#define OCR4D0_REG OCR4D +#define OCR4D1_REG OCR4D +#define OCR4D2_REG OCR4D +#define OCR4D3_REG OCR4D +#define OCR4D4_REG OCR4D +#define OCR4D5_REG OCR4D +#define OCR4D6_REG OCR4D +#define OCR4D7_REG OCR4D + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* RCCTRL */ +#define RCFREQ_REG RCCTRL + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON +#define RSTCPU_REG UDCON + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCNT4 */ +#define TC40_REG TCNT4 +#define TC41_REG TCNT4 +#define TC42_REG TCNT4 +#define TC43_REG TCNT4 +#define TC44_REG TCNT4 +#define TC45_REG TCNT4 +#define TC46_REG TCNT4 +#define TC47_REG TCNT4 + +/* TC4H */ +#define TC48_REG TC4H +#define TC49_REG TC4H +#define TC410_REG TC4H + +/* UHWCON */ +#define UVREGE_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4D_REG TIFR4 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* UEBCLX */ +#define BYCT0_REG UEBCLX +#define BYCT1_REG UEBCLX +#define BYCT2_REG UEBCLX +#define BYCT3_REG UEBCLX +#define BYCT4_REG UEBCLX +#define BYCT5_REG UEBCLX +#define BYCT6_REG UEBCLX +#define BYCT7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +#define RWAL_REG UEINTX +#define NAKINI_REG UEINTX +#define FIFOCON_REG UEINTX + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USBCON */ +#define VBUSTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define USBE_REG USBCON + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* UECONX */ +#define EPEN_REG UECONX +#define RSTDT_REG UECONX +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* PLLFRQ */ +#define PDIV0_REG PLLFRQ +#define PDIV1_REG PLLFRQ +#define PDIV2_REG PLLFRQ +#define PDIV3_REG PLLFRQ +#define PLLTM0_REG PLLFRQ +#define PLLTM1_REG PLLFRQ +#define PLLUSB_REG PLLFRQ +#define PINMUX_REG PLLFRQ + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* USBSTA */ +#define VBUS_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +#define FLERRE_REG UEIENX + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* UDFNUML */ +#define FNUM0_REG UDFNUML +#define FNUM1_REG UDFNUML +#define FNUM2_REG UDFNUML +#define FNUM3_REG UDFNUML +#define FNUM4_REG UDFNUML +#define FNUM5_REG UDFNUML +#define FNUM6_REG UDFNUML +#define FNUM7_REG UDFNUML + +/* UDFNUMH */ +#define FNUM8_REG UDFNUMH +#define FNUM9_REG UDFNUMH +#define FNUM10_REG UDFNUMH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADTS3_REG ADCSRB +#define MUX5_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE2_REG DDRE +#define DDE6_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +#define DTSEQ0_REG UESTA0X +#define DTSEQ1_REG UESTA0X +#define UNDERFI_REG UESTA0X +#define OVERFI_REG UESTA0X +#define CFGOK_REG UESTA0X + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* CLKSTA */ +#define EXTON_REG CLKSTA +#define RCON_REG CLKSTA + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4D_REG TIMSK4 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define CS43_REG TCCR4B +#define DTPS40_REG TCCR4B +#define DTPS41_REG TCCR4B +#define PSR4_REG TCCR4B +#define PWM4X_REG TCCR4B + +/* TCCR4C */ +#define PWM4D_REG TCCR4C +#define FOC4D_REG TCCR4C +#define COM4D0_REG TCCR4C +#define COM4D1_REG TCCR4C +#define COM4B0S_REG TCCR4C +#define COM4B1S_REG TCCR4C +#define COM4A0S_REG TCCR4C +#define COM4A1S_REG TCCR4C + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PINDIV_REG PLLCSR + +/* TCCR4A */ +#define PWM4B_REG TCCR4A +#define PWM4A_REG TCCR4A +#define FOC4B_REG TCCR4A +#define FOC4A_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* TCCR4D */ +#define WGM40_REG TCCR4D +#define WGM41_REG TCCR4D +#define FPF4_REG TCCR4D +#define FPAC4_REG TCCR4D +#define FPES4_REG TCCR4D +#define FPNC4_REG TCCR4D +#define FPEN4_REG TCCR4D +#define FPIE4_REG TCCR4D + +/* TCCR4E */ +#define OC4OE0_REG TCCR4E +#define OC4OE1_REG TCCR4E +#define OC4OE2_REG TCCR4E +#define OC4OE3_REG TCCR4E +#define OC4OE4_REG TCCR4E +#define OC4OE5_REG TCCR4E +#define ENHC4_REG TCCR4E +#define TLOCK4_REG TCCR4E + +/* PINC */ +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE2_REG PINE +#define PINE6_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* DT4 */ +#define DT4L0_REG DT4 +#define DT4L1_REG DT4 +#define DT4L2_REG DT4 +#define DT4L3_REG DT4 +#define DT4L4_REG DT4 +#define DT4L5_REG DT4 +#define DT4L6_REG DT4 +#define DT4L7_REG DT4 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega32U6.h b/include/aversive/parts/ATmega32U6.h new file mode 100644 index 0000000..57c0bd1 --- /dev/null +++ b/include/aversive/parts/ATmega32U6.h @@ -0,0 +1,1375 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM_TOTAL_NUM 10 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* UEBCHX */ +#define UEBCHX_0_REG UEBCHX +#define UEBCHX_1_REG UEBCHX +#define UEBCHX_2_REG UEBCHX + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UDIEN */ +#define SUSPE_REG UDIEN +#define SOFE_REG UDIEN +#define EORSTE_REG UDIEN +#define WAKEUPE_REG UDIEN +#define EORSME_REG UDIEN +#define UPRSME_REG UDIEN + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* UDINT */ +#define SUSPI_REG UDINT +#define SOFI_REG UDINT +#define EORSTI_REG UDINT +#define WAKEUPI_REG UDINT +#define EORSMI_REG UDINT +#define UPRSMI_REG UDINT + +/* UERST */ +#define EPRST0_REG UERST +#define EPRST1_REG UERST +#define EPRST2_REG UERST +#define EPRST3_REG UERST +#define EPRST4_REG UERST +#define EPRST5_REG UERST +#define EPRST6_REG UERST + +/* UECFG1X */ +#define ALLOC_REG UECFG1X +#define EPBK0_REG UECFG1X +#define EPBK1_REG UECFG1X +#define EPSIZE0_REG UECFG1X +#define EPSIZE1_REG UECFG1X +#define EPSIZE2_REG UECFG1X + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UEINT */ +#define EPINT0_REG UEINT +#define EPINT1_REG UEINT +#define EPINT2_REG UEINT +#define EPINT3_REG UEINT +#define EPINT4_REG UEINT +#define EPINT5_REG UEINT +#define EPINT6_REG UEINT + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* UEDATX */ +#define UEDATX_0_REG UEDATX +#define UEDATX_1_REG UEDATX +#define UEDATX_2_REG UEDATX +#define UEDATX_3_REG UEDATX +#define UEDATX_4_REG UEDATX +#define UEDATX_5_REG UEDATX +#define UEDATX_6_REG UEDATX +#define UEDATX_7_REG UEDATX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* UECFG0X */ +#define EPDIR_REG UECFG0X +#define EPTYPE0_REG UECFG0X +#define EPTYPE1_REG UECFG0X + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UENUM */ +#define UENUM_0_REG UENUM +#define UENUM_1_REG UENUM +#define UENUM_2_REG UENUM + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* UDCON */ +#define DETACH_REG UDCON +#define RMWKUP_REG UDCON +#define LSM_REG UDCON + +/* PCICR */ +#define PCIE0_REG PCICR + +/* USBINT */ +#define VBUSTI_REG USBINT +#define IDTI_REG USBINT + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* UHWCON */ +#define UVREGE_REG UHWCON +#define UVCONE_REG UHWCON +#define UIDE_REG UHWCON +#define UIMOD_REG UHWCON + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* UDMFN */ +#define FNCERR_REG UDMFN + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* UEBCLX */ +#define UEBCLX_0_REG UEBCLX +#define UEBCLX_1_REG UEBCLX +#define UEBCLX_2_REG UEBCLX +#define UEBCLX_3_REG UEBCLX +#define UEBCLX_4_REG UEBCLX +#define UEBCLX_5_REG UEBCLX +#define UEBCLX_6_REG UEBCLX +#define UEBCLX_7_REG UEBCLX + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* UESTA1X */ +#define CURRBK0_REG UESTA1X +#define CURRBK1_REG UESTA1X +#define CTRLDIR_REG UESTA1X + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* UEINTX */ +#define TXINI_REG UEINTX +#define STALLEDI_REG UEINTX +#define RXOUTI_REG UEINTX +#define RXSTPI_REG UEINTX +#define NAKOUTI_REG UEINTX +#define RWAL_REG UEINTX +#define NAKINI_REG UEINTX +#define FIFOCON_REG UEINTX + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USBCON */ +#define VBUSTE_REG USBCON +#define IDTE_REG USBCON +#define OTGPADE_REG USBCON +#define FRZCLK_REG USBCON +#define HOST_REG USBCON +#define USBE_REG USBCON + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UECONX */ +#define EPEN_REG UECONX +#define RSTDT_REG UECONX +#define STALLRQC_REG UECONX +#define STALLRQ_REG UECONX + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USBSTA */ +#define VBUS_REG USBSTA +#define ID_REG USBSTA +#define SPEED_REG USBSTA + +/* UEIENX */ +#define TXINE_REG UEIENX +#define STALLEDE_REG UEIENX +#define RXOUTE_REG UEIENX +#define RXSTPE_REG UEIENX +#define NAKOUTE_REG UEIENX +#define NAKINE_REG UEIENX +#define FLERRE_REG UEIENX + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* UDFNUML */ +#define UDFNUML_0_REG UDFNUML +#define UDFNUML_1_REG UDFNUML +#define UDFNUML_2_REG UDFNUML +#define UDFNUML_3_REG UDFNUML +#define UDFNUML_4_REG UDFNUML +#define UDFNUML_5_REG UDFNUML +#define UDFNUML_6_REG UDFNUML +#define UDFNUML_7_REG UDFNUML + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* UDFNUMH */ +#define UDFNUMH_0_REG UDFNUMH +#define UDFNUMH_1_REG UDFNUMH +#define UDFNUMH_2_REG UDFNUMH + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADHSM_REG ADCSRB +#define ACME_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* UDADDR */ +#define UADD0_REG UDADDR +#define UADD1_REG UDADDR +#define UADD2_REG UDADDR +#define UADD3_REG UDADDR +#define UADD4_REG UDADDR +#define UADD5_REG UDADDR +#define UADD6_REG UDADDR +#define ADDEN_REG UDADDR + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* UESTA0X */ +#define NBUSYBK0_REG UESTA0X +#define NBUSYBK1_REG UESTA0X +#define DTSEQ0_REG UESTA0X +#define DTSEQ1_REG UESTA0X +#define UNDERFI_REG UESTA0X +#define OVERFI_REG UESTA0X +#define CFGOK_REG UESTA0X + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PLLP0_REG PLLCSR +#define PLLP1_REG PLLCSR +#define PLLP2_REG PLLCSR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRUSB_REG PRR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega406.h b/include/aversive/parts/ATmega406.h new file mode 100644 index 0000000..e4a8e1b --- /dev/null +++ b/include/aversive/parts/ATmega406.h @@ -0,0 +1,850 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_32 3 +#define TIMER1_PRESCALER_DIV_64 4 +#define TIMER1_PRESCALER_DIV_128 5 +#define TIMER1_PRESCALER_DIV_256 6 +#define TIMER1_PRESCALER_DIV_1024 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 32 +#define TIMER1_PRESCALER_REG_4 64 +#define TIMER1_PRESCALER_REG_5 128 +#define TIMER1_PRESCALER_REG_6 256 +#define TIMER1_PRESCALER_REG_7 1024 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CADAC2 */ +#define CADAC16_REG CADAC2 +#define CADAC17_REG CADAC2 +#define CADAC18_REG CADAC2 +#define CADAC19_REG CADAC2 +#define CADAC20_REG CADAC2 +#define CADAC21_REG CADAC2 +#define CADAC22_REG CADAC2 +#define CADAC23_REG CADAC2 + +/* CADAC3 */ +#define CADAC24_REG CADAC3 +#define CADAC25_REG CADAC3 +#define CADAC26_REG CADAC3 +#define CADAC27_REG CADAC3 +#define CADAC28_REG CADAC3 +#define CADAC29_REG CADAC3 +#define CADAC30_REG CADAC3 +#define CADAC31_REG CADAC3 + +/* CADAC0 */ +#define CADAC00_REG CADAC0 +#define CADAC01_REG CADAC0 +#define CADAC02_REG CADAC0 +#define CADAC03_REG CADAC0 +#define CADAC04_REG CADAC0 +#define CADAC05_REG CADAC0 +#define CADAC06_REG CADAC0 +#define CADAC07_REG CADAC0 + +/* CADAC1 */ +#define CADAC08_REG CADAC1 +#define CADAC09_REG CADAC1 +#define CADAC10_REG CADAC1 +#define CADAC11_REG CADAC1 +#define CADAC12_REG CADAC1 +#define CADAC13_REG CADAC1 +#define CADAC14_REG CADAC1 +#define CADAC15_REG CADAC1 + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR + +/* WUTCSR */ +#define WUTP0_REG WUTCSR +#define WUTP1_REG WUTCSR +#define WUTP2_REG WUTCSR +#define WUTE_REG WUTCSR +#define WUTR_REG WUTCSR +#define WUTCF_REG WUTCSR +#define WUTIE_REG WUTCSR +#define WUTIF_REG WUTCSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* BPCR */ +#define CCD_REG BPCR +#define DCD_REG BPCR +#define SCD_REG BPCR +#define DUVD_REG BPCR + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* BGCRR */ +#define BGCR0_REG BGCRR +#define BGCR1_REG BGCRR +#define BGCR2_REG BGCRR +#define BGCR3_REG BGCRR +#define BGCR4_REG BGCRR +#define BGCR5_REG BGCRR +#define BGCR6_REG BGCRR +#define BGCR7_REG BGCRR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK + +/* PRR0 */ +#define PRVADC_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTWI_REG PRR0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* BPOCD */ +#define CCDL0_REG BPOCD +#define CCDL1_REG BPOCD +#define CCDL2_REG BPOCD +#define CCDL3_REG BPOCD +#define DCDL0_REG BPOCD +#define DCDL1_REG BPOCD +#define DCDL2_REG BPOCD +#define DCDL3_REG BPOCD + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD + +/* OCR0B */ +#define OCR0B0_REG OCR0B +#define OCR0B1_REG OCR0B +#define OCR0B2_REG OCR0B +#define OCR0B3_REG OCR0B +#define OCR0B4_REG OCR0B +#define OCR0B5_REG OCR0B +#define OCR0B6_REG OCR0B +#define OCR0B7_REG OCR0B + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* CCSR */ +#define ACS_REG CCSR +#define XOE_REG CCSR + +/* CADICH */ +#define CADICH0_REG CADICH +#define CADICH1_REG CADICH +#define CADICH2_REG CADICH +#define CADICH3_REG CADICH +#define CADICH4_REG CADICH +#define CADICH5_REG CADICH +#define CADICH6_REG CADICH +#define CADICH7_REG CADICH + +/* FCSR */ +#define PFD_REG FCSR +#define CFE_REG FCSR +#define DFE_REG FCSR +#define CPS_REG FCSR +#define PWMOPC_REG FCSR +#define PWMOC_REG FCSR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* CADCSRB */ +#define CADICIF_REG CADCSRB +#define CADRCIF_REG CADCSRB +#define CADACIF_REG CADCSRB +#define CADICIE_REG CADCSRB +#define CADRCIE_REG CADCSRB +#define CADACIE_REG CADCSRB + +/* CADICL */ +#define CADICL0_REG CADICL +#define CADICL1_REG CADICL +#define CADICL2_REG CADICL +#define CADICL3_REG CADICL +#define CADICL4_REG CADICL +#define CADICL5_REG CADICL +#define CADICL6_REG CADICL +#define CADICL7_REG CADICL + +/* BPIR */ +#define SCIE_REG BPIR +#define DOCIE_REG BPIR +#define COCIE_REG BPIR +#define DUVIE_REG BPIR +#define SCIF_REG BPIR +#define DOCIF_REG BPIR +#define COCIF_REG BPIR +#define DUVIF_REG BPIR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* BPPLR */ +#define BPPL_REG BPPLR +#define BPPLE_REG BPPLR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CTC1_REG TCCR1B + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BODRF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* CBPTR */ +#define OCPT0_REG CBPTR +#define OCPT1_REG CBPTR +#define OCPT2_REG CBPTR +#define OCPT3_REG CBPTR +#define SCPT0_REG CBPTR +#define SCPT1_REG CBPTR +#define SCPT2_REG CBPTR +#define SCPT3_REG CBPTR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* CADCSRA */ +#define CADSE_REG CADCSRA +#define CADSI0_REG CADCSRA +#define CADSI1_REG CADCSRA +#define CADAS0_REG CADCSRA +#define CADAS1_REG CADCSRA +#define CADUB_REG CADCSRA +#define CADEN_REG CADCSRA + +/* BPDUV */ +#define DUDL0_REG BPDUV +#define DUDL1_REG BPDUV +#define DUDL2_REG BPDUV +#define DUDL3_REG BPDUV +#define DUVT0_REG BPDUV +#define DUVT1_REG BPDUV + +/* CADRDC */ +#define CADRDC0_REG CADRDC +#define CADRDC1_REG CADRDC +#define CADRDC2_REG CADRDC +#define CADRDC3_REG CADRDC +#define CADRDC4_REG CADRDC +#define CADRDC5_REG CADRDC +#define CADRDC6_REG CADRDC +#define CADRDC7_REG CADRDC + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* BPSCD */ +#define SCDL0_REG BPSCD +#define SCDL1_REG BPSCD +#define SCDL2_REG BPSCD +#define SCDL3_REG BPSCD + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* BGCCR */ +#define BGCC0_REG BGCCR +#define BGCC1_REG BGCCR +#define BGCC2_REG BGCCR +#define BGCC3_REG BGCCR +#define BGCC4_REG BGCCR +#define BGCC5_REG BGCCR +#define BGD_REG BGCCR + +/* VADMUX */ +#define VADMUX0_REG VADMUX +#define VADMUX1_REG VADMUX +#define VADMUX2_REG VADMUX +#define VADMUX3_REG VADMUX + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* VADCH */ +#define VADC8_REG VADCH +#define VADC9_REG VADCH +#define VADC10_REG VADCH +#define VADC11_REG VADCH + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* VADCL */ +#define VADC0_REG VADCL +#define VADC1_REG VADCL +#define VADC2_REG VADCL +#define VADC3_REG VADCL +#define VADC4_REG VADCL +#define VADC5_REG VADCL +#define VADC6_REG VADCL +#define VADC7_REG VADCL + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* VADCSR */ +#define VADCCIE_REG VADCSR +#define VADCCIF_REG VADCSR +#define VADSC_REG VADCSR +#define VADEN_REG VADCSR + +/* FOSCCAL */ +#define FCAL0_REG FOSCCAL +#define FCAL1_REG FOSCCAL +#define FCAL2_REG FOSCCAL +#define FCAL3_REG FOSCCAL +#define FCAL4_REG FOSCCAL +#define FCAL5_REG FOSCCAL +#define FCAL6_REG FOSCCAL +#define FCAL7_REG FOSCCAL + +/* DIDR0 */ +#define VADC0D_REG DIDR0 +#define VADC1D_REG DIDR0 +#define VADC2D_REG DIDR0 +#define VADC3D_REG DIDR0 + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* CBCR */ +#define CBE1_REG CBCR +#define CBE2_REG CBCR +#define CBE3_REG CBCR +#define CBE4_REG CBCR + +/* TWBCSR */ +#define TWBCIP_REG TWBCSR +#define TWBDT0_REG TWBCSR +#define TWBDT1_REG TWBCSR +#define TWBCIE_REG TWBCSR +#define TWBCIF_REG TWBCSR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* CADRCC */ +#define CADRCC0_REG CADRCC +#define CADRCC1_REG CADRCC +#define CADRCC2_REG CADRCC +#define CADRCC3_REG CADRCC +#define CADRCC4_REG CADRCC +#define CADRCC5_REG CADRCC +#define CADRCC6_REG CADRCC +#define CADRCC7_REG CADRCC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define INT0_PORT PORTA +#define INT0_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define INT1_PORT PORTA +#define INT1_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define INT2_PORT PORTA +#define INT2_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define INT3_PORT PORTA +#define INT3_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define TDO_PORT PORTB +#define TDO_BIT 0 +#define PCINT8_PORT PORTB +#define PCINT8_BIT 0 + +#define TDI_PORT PORTB +#define TDI_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define TMS_PORT PORTB +#define TMS_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define TCK_PORT PORTB +#define TCK_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define OC0A_PORT PORTB +#define OC0A_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define OC0B_PORT PORTB +#define OC0B_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + + +#define T0_PORT PORTD +#define T0_BIT 0 + + + + + + + diff --git a/include/aversive/parts/ATmega48.h b/include/aversive/parts/ATmega48.h new file mode 100644 index 0000000..77e16ba --- /dev/null +++ b/include/aversive/parts/ATmega48.h @@ -0,0 +1,989 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define PUD_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega48P.h b/include/aversive/parts/ATmega48P.h new file mode 100644 index 0000000..67c3167 --- /dev/null +++ b/include/aversive/parts/ATmega48P.h @@ -0,0 +1,991 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega64.h b/include/aversive/parts/ATmega64.h new file mode 100644 index 0000000..4a622c2 --- /dev/null +++ b/include/aversive/parts/ATmega64.h @@ -0,0 +1,1328 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_64 3 +#define TIMER2_PRESCALER_DIV_256 4 +#define TIMER2_PRESCALER_DIV_1024 5 +#define TIMER2_PRESCALER_DIV_FALL 6 +#define TIMER2_PRESCALER_DIV_RISE 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 64 +#define TIMER2_PRESCALER_REG_4 256 +#define TIMER2_PRESCALER_REG_5 1024 +#define TIMER2_PRESCALER_REG_6 -1 +#define TIMER2_PRESCALER_REG_7 -2 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* ASSR */ +#define TCR0UB_REG ASSR +#define OCR0UB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR321_REG SFIOR +#define PSR0_REG SFIOR +#define PUD_REG SFIOR +#define TSM_REG SFIOR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* ETIFR */ +#define OCF1C_REG ETIFR +#define OCF3C_REG ETIFR +#define TOV3_REG ETIFR +#define OCF3B_REG ETIFR +#define OCF3A_REG ETIFR +#define ICF3_REG ETIFR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* XDIV */ +#define XDIV0_REG XDIV +#define XDIV1_REG XDIV +#define XDIV2_REG XDIV +#define XDIV3_REG XDIV +#define XDIV4_REG XDIV +#define XDIV5_REG XDIV +#define XDIV6_REG XDIV +#define XDIVEN_REG XDIV + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* ETIMSK */ +#define OCIE1C_REG ETIMSK +#define OCIE3C_REG ETIMSK +#define TOIE3_REG ETIMSK +#define OCIE3B_REG ETIMSK +#define OCIE3A_REG ETIMSK +#define TICIE3_REG ETIMSK + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCN3L0_REG TCNT3L +#define TCN3L1_REG TCNT3L +#define TCN3L2_REG TCNT3L +#define TCN3L3_REG TCNT3L +#define TCN3L4_REG TCNT3L +#define TCN3L5_REG TCNT3L +#define TCN3L6_REG TCNT3L +#define TCN3L7_REG TCNT3L + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define SM2_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW11_REG XMCRA +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/ATmega640.h b/include/aversive/parts/ATmega640.h new file mode 100644 index 0000000..b3838b0 --- /dev/null +++ b/include/aversive/parts/ATmega640.h @@ -0,0 +1,2188 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + +/* prescalers timer 4 */ +#define TIMER4_PRESCALER_DIV_0 0 +#define TIMER4_PRESCALER_DIV_1 1 +#define TIMER4_PRESCALER_DIV_8 2 +#define TIMER4_PRESCALER_DIV_64 3 +#define TIMER4_PRESCALER_DIV_256 4 +#define TIMER4_PRESCALER_DIV_1024 5 +#define TIMER4_PRESCALER_DIV_FALL 6 +#define TIMER4_PRESCALER_DIV_RISE 7 + +#define TIMER4_PRESCALER_REG_0 0 +#define TIMER4_PRESCALER_REG_1 1 +#define TIMER4_PRESCALER_REG_2 8 +#define TIMER4_PRESCALER_REG_3 64 +#define TIMER4_PRESCALER_REG_4 256 +#define TIMER4_PRESCALER_REG_5 1024 +#define TIMER4_PRESCALER_REG_6 -1 +#define TIMER4_PRESCALER_REG_7 -2 + +/* prescalers timer 5 */ +#define TIMER5_PRESCALER_DIV_0 0 +#define TIMER5_PRESCALER_DIV_1 1 +#define TIMER5_PRESCALER_DIV_8 2 +#define TIMER5_PRESCALER_DIV_64 3 +#define TIMER5_PRESCALER_DIV_256 4 +#define TIMER5_PRESCALER_DIV_1024 5 +#define TIMER5_PRESCALER_DIV_FALL 6 +#define TIMER5_PRESCALER_DIV_RISE 7 + +#define TIMER5_PRESCALER_REG_0 0 +#define TIMER5_PRESCALER_REG_1 1 +#define TIMER5_PRESCALER_REG_2 8 +#define TIMER5_PRESCALER_REG_3 64 +#define TIMER5_PRESCALER_REG_4 256 +#define TIMER5_PRESCALER_REG_5 1024 +#define TIMER5_PRESCALER_REG_6 -1 +#define TIMER5_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE +#define TIMER4_AVAILABLE +#define TIMER4A_AVAILABLE +#define TIMER4B_AVAILABLE +#define TIMER4C_AVAILABLE +#define TIMER5_AVAILABLE +#define TIMER5A_AVAILABLE +#define TIMER5B_AVAILABLE +#define TIMER5C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW4_NUM 4 +#define SIG_OVERFLOW5_NUM 5 +#define SIG_OVERFLOW_TOTAL_NUM 6 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE1C_NUM 4 +#define SIG_OUTPUT_COMPARE2A_NUM 5 +#define SIG_OUTPUT_COMPARE2B_NUM 6 +#define SIG_OUTPUT_COMPARE3A_NUM 7 +#define SIG_OUTPUT_COMPARE3B_NUM 8 +#define SIG_OUTPUT_COMPARE3C_NUM 9 +#define SIG_OUTPUT_COMPARE4A_NUM 10 +#define SIG_OUTPUT_COMPARE4B_NUM 11 +#define SIG_OUTPUT_COMPARE4C_NUM 12 +#define SIG_OUTPUT_COMPARE5A_NUM 13 +#define SIG_OUTPUT_COMPARE5B_NUM 14 +#define SIG_OUTPUT_COMPARE5C_NUM 15 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM1C_NUM 4 +#define PWM2A_NUM 5 +#define PWM2B_NUM 6 +#define PWM3A_NUM 7 +#define PWM3B_NUM 8 +#define PWM3C_NUM 9 +#define PWM4A_NUM 10 +#define PWM4B_NUM 11 +#define PWM4C_NUM 12 +#define PWM5A_NUM 13 +#define PWM5B_NUM 14 +#define PWM5C_NUM 15 +#define PWM_TOTAL_NUM 16 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE4_NUM 2 +#define SIG_INPUT_CAPTURE5_NUM 3 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 4 + + +/* UBRR3H */ +/* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ +/* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */ + +/* UBRR3L */ +/* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ +/* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */ + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* UCSR3A */ +#define MPCM3_REG UCSR3A +#define U2X3_REG UCSR3A +#define UPE3_REG UCSR3A +#define DOR3_REG UCSR3A +#define FE3_REG UCSR3A +#define UDRE3_REG UCSR3A +#define TXC3_REG UCSR3A +#define RXC3_REG UCSR3A + +/* UCSR3B */ +#define TXB83_REG UCSR3B +#define RXB83_REG UCSR3B +#define UCSZ32_REG UCSR3B +#define TXEN3_REG UCSR3B +#define RXEN3_REG UCSR3B +#define UDRIE3_REG UCSR3B +#define TXCIE3_REG UCSR3B +#define RXCIE3_REG UCSR3B + +/* UCSR3C */ +#define UCPOL3_REG UCSR3C +#define UCSZ30_REG UCSR3C +#define UCSZ31_REG UCSR3C +#define USBS3_REG UCSR3C +#define UPM30_REG UCSR3C +#define UPM31_REG UCSR3C +#define UMSEL30_REG UCSR3C +#define UMSEL31_REG UCSR3C + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ +#define RAMPZ1_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* PORTL */ +#define PORTL0_REG PORTL +#define PORTL1_REG PORTL +#define PORTL2_REG PORTL +#define PORTL3_REG PORTL +#define PORTL4_REG PORTL +#define PORTL5_REG PORTL +#define PORTL6_REG PORTL +#define PORTL7_REG PORTL + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ +#define PORTJ7_REG PORTJ + +/* PORTK */ +#define PORTK0_REG PORTK +#define PORTK1_REG PORTK +#define PORTK2_REG PORTK +#define PORTK3_REG PORTK +#define PORTK4_REG PORTK +#define PORTK5_REG PORTK +#define PORTK6_REG PORTK +#define PORTK7_REG PORTK + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG +#define PORTG5_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* UDR3 */ +#define UDR3_0_REG UDR3 +#define UDR3_1_REG UDR3 +#define UDR3_2_REG UDR3 +#define UDR3_3_REG UDR3 +#define UDR3_4_REG UDR3 +#define UDR3_5_REG UDR3 +#define UDR3_6_REG UDR3 +#define UDR3_7_REG UDR3 + +/* UDR2 */ +#define UDR2_0_REG UDR2 +#define UDR2_1_REG UDR2 +#define UDR2_2_REG UDR2 +#define UDR2_3_REG UDR2 +#define UDR2_4_REG UDR2 +#define UDR2_5_REG UDR2 +#define UDR2_6_REG UDR2 +#define UDR2_7_REG UDR2 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* DIDR2 */ +#define ADC8D_REG DIDR2 +#define ADC9D_REG DIDR2 +#define ADC10D_REG DIDR2 +#define ADC11D_REG DIDR2 +#define ADC12D_REG DIDR2 +#define ADC13D_REG DIDR2 +#define ADC14D_REG DIDR2 +#define ADC15D_REG DIDR2 + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ +#define DDJ7_REG DDRJ + +/* DDRK */ +#define DDK0_REG DDRK +#define DDK1_REG DDRK +#define DDK2_REG DDRK +#define DDK3_REG DDRK +#define DDK4_REG DDRK +#define DDK5_REG DDRK +#define DDK6_REG DDRK +#define DDK7_REG DDRK + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRL */ +#define DDL0_REG DDRL +#define DDL1_REG DDRL +#define DDL2_REG DDRL +#define DDL3_REG DDRL +#define DDL4_REG DDRL +#define DDL5_REG DDRL +#define DDL6_REG DDRL +#define DDL7_REG DDRL + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG +#define DDG5_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCNT5H */ +#define TCNT5H0_REG TCNT5H +#define TCNT5H1_REG TCNT5H +#define TCNT5H2_REG TCNT5H +#define TCNT5H3_REG TCNT5H +#define TCNT5H4_REG TCNT5H +#define TCNT5H5_REG TCNT5H +#define TCNT5H6_REG TCNT5H +#define TCNT5H7_REG TCNT5H + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* TCNT5L */ +#define TCNT5L0_REG TCNT5L +#define TCNT5L1_REG TCNT5L +#define TCNT5L2_REG TCNT5L +#define TCNT5L3_REG TCNT5L +#define TCNT5L4_REG TCNT5L +#define TCNT5L5_REG TCNT5L +#define TCNT5L6_REG TCNT5L +#define TCNT5L7_REG TCNT5L + +/* UBRR2H */ +/* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ +/* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */ + +/* UBRR2L */ +/* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ +/* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */ + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UCSR2B */ +#define TXB82_REG UCSR2B +#define RXB82_REG UCSR2B +#define UCSZ22_REG UCSR2B +#define TXEN2_REG UCSR2B +#define RXEN2_REG UCSR2B +#define UDRIE2_REG UCSR2B +#define TXCIE2_REG UCSR2B +#define RXCIE2_REG UCSR2B + +/* UCSR2A */ +#define MPCM2_REG UCSR2A +#define U2X2_REG UCSR2A +#define UPE2_REG UCSR2A +#define DOR2_REG UCSR2A +#define FE2_REG UCSR2A +#define UDRE2_REG UCSR2A +#define TXC2_REG UCSR2A +#define RXC2_REG UCSR2A + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UCSR2C */ +#define UCPOL2_REG UCSR2C +#define UCSZ20_REG UCSR2C +#define UCSZ21_REG UCSR2C +#define USBS2_REG UCSR2C +#define UPM20_REG UCSR2C +#define UPM21_REG UCSR2C +#define UMSEL20_REG UCSR2C +#define UMSEL21_REG UCSR2C + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TIFR4 */ +#define TOV4_REG TIFR4 +#define OCF4A_REG TIFR4 +#define OCF4B_REG TIFR4 +#define OCF4C_REG TIFR4 +#define ICF4_REG TIFR4 + +/* TIFR5 */ +#define TOV5_REG TIFR5 +#define OCF5A_REG TIFR5 +#define OCF5B_REG TIFR5 +#define OCF5C_REG TIFR5 +#define ICF5_REG TIFR5 + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR3 */ +#define TOV3_REG TIFR3 +#define OCF3A_REG TIFR3 +#define OCF3B_REG TIFR3 +#define OCF3C_REG TIFR3 +#define ICF3_REG TIFR3 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define OCF1C_REG TIFR1 +#define ICF1_REG TIFR1 + +/* OCR4AH */ +#define OCR4AH0_REG OCR4AH +#define OCR4AH1_REG OCR4AH +#define OCR4AH2_REG OCR4AH +#define OCR4AH3_REG OCR4AH +#define OCR4AH4_REG OCR4AH +#define OCR4AH5_REG OCR4AH +#define OCR4AH6_REG OCR4AH +#define OCR4AH7_REG OCR4AH + +/* OCR5CH */ +#define OCR5CH0_REG OCR5CH +#define OCR5CH1_REG OCR5CH +#define OCR5CH2_REG OCR5CH +#define OCR5CH3_REG OCR5CH +#define OCR5CH4_REG OCR5CH +#define OCR5CH5_REG OCR5CH +#define OCR5CH6_REG OCR5CH +#define OCR5CH7_REG OCR5CH + +/* OCR4AL */ +#define OCR4AL0_REG OCR4AL +#define OCR4AL1_REG OCR4AL +#define OCR4AL2_REG OCR4AL +#define OCR4AL3_REG OCR4AL +#define OCR4AL4_REG OCR4AL +#define OCR4AL5_REG OCR4AL +#define OCR4AL6_REG OCR4AL +#define OCR4AL7_REG OCR4AL + +/* OCR5CL */ +#define OCR5CL0_REG OCR5CL +#define OCR5CL1_REG OCR5CL +#define OCR5CL2_REG OCR5CL +#define OCR5CL3_REG OCR5CL +#define OCR5CL4_REG OCR5CL +#define OCR5CL5_REG OCR5CL +#define OCR5CL6_REG OCR5CL +#define OCR5CL7_REG OCR5CL + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCNT3L0_REG TCNT3L +#define TCNT3L1_REG TCNT3L +#define TCNT3L2_REG TCNT3L +#define TCNT3L3_REG TCNT3L +#define TCNT3L4_REG TCNT3L +#define TCNT3L5_REG TCNT3L +#define TCNT3L6_REG TCNT3L +#define TCNT3L7_REG TCNT3L + +/* ICR5L */ +#define ICR5L0_REG ICR5L +#define ICR5L1_REG ICR5L +#define ICR5L2_REG ICR5L +#define ICR5L3_REG ICR5L +#define ICR5L4_REG ICR5L +#define ICR5L5_REG ICR5L +#define ICR5L6_REG ICR5L +#define ICR5L7_REG ICR5L + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* ICR5H */ +#define ICR5H0_REG ICR5H +#define ICR5H1_REG ICR5H +#define ICR5H2_REG ICR5H +#define ICR5H3_REG ICR5H +#define ICR5H4_REG ICR5H +#define ICR5H5_REG ICR5H +#define ICR5H6_REG ICR5H +#define ICR5H7_REG ICR5H + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* PINK */ +#define PINK0_REG PINK +#define PINK1_REG PINK +#define PINK2_REG PINK +#define PINK3_REG PINK +#define PINK4_REG PINK +#define PINK5_REG PINK +#define PINK6_REG PINK +#define PINK7_REG PINK + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ +#define PINJ7_REG PINJ + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */ + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */ + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* ICR4H */ +#define ICR4H0_REG ICR4H +#define ICR4H1_REG ICR4H +#define ICR4H2_REG ICR4H +#define ICR4H3_REG ICR4H +#define ICR4H4_REG ICR4H +#define ICR4H5_REG ICR4H +#define ICR4H6_REG ICR4H +#define ICR4H7_REG ICR4H + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* ICR4L */ +#define ICR4L0_REG ICR4L +#define ICR4L1_REG ICR4L +#define ICR4L2_REG ICR4L +#define ICR4L3_REG ICR4L +#define ICR4L4_REG ICR4L +#define ICR4L5_REG ICR4L +#define ICR4L6_REG ICR4L +#define ICR4L7_REG ICR4L + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* TCNT4L */ +#define TCNT4L0_REG TCNT4L +#define TCNT4L1_REG TCNT4L +#define TCNT4L2_REG TCNT4L +#define TCNT4L3_REG TCNT4L +#define TCNT4L4_REG TCNT4L +#define TCNT4L5_REG TCNT4L +#define TCNT4L6_REG TCNT4L +#define TCNT4L7_REG TCNT4L + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* TCNT4H */ +#define TCNT4H0_REG TCNT4H +#define TCNT4H1_REG TCNT4H +#define TCNT4H2_REG TCNT4H +#define TCNT4H3_REG TCNT4H +#define TCNT4H4_REG TCNT4H +#define TCNT4H5_REG TCNT4H +#define TCNT4H6_REG TCNT4H +#define TCNT4H7_REG TCNT4H + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EIND */ +#define EIND0_REG EIND + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TCCR5A */ +#define WGM50_REG TCCR5A +#define WGM51_REG TCCR5A +#define COM5C0_REG TCCR5A +#define COM5C1_REG TCCR5A +#define COM5B0_REG TCCR5A +#define COM5B1_REG TCCR5A +#define COM5A0_REG TCCR5A +#define COM5A1_REG TCCR5A + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* TCCR5C */ +#define FOC5C_REG TCCR5C +#define FOC5B_REG TCCR5C +#define FOC5A_REG TCCR5C + +/* TCCR5B */ +#define CS50_REG TCCR5B +#define CS51_REG TCCR5B +#define CS52_REG TCCR5B +#define WGM52_REG TCCR5B +#define WGM53_REG TCCR5B +#define ICES5_REG TCCR5B +#define ICNC5_REG TCCR5B + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB + +/* OCR5AL */ +#define OCR5AL0_REG OCR5AL +#define OCR5AL1_REG OCR5AL +#define OCR5AL2_REG OCR5AL +#define OCR5AL3_REG OCR5AL +#define OCR5AL4_REG OCR5AL +#define OCR5AL5_REG OCR5AL +#define OCR5AL6_REG OCR5AL +#define OCR5AL7_REG OCR5AL + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR4CH */ +#define OCR4CH0_REG OCR4CH +#define OCR4CH1_REG OCR4CH +#define OCR4CH2_REG OCR4CH +#define OCR4CH3_REG OCR4CH +#define OCR4CH4_REG OCR4CH +#define OCR4CH5_REG OCR4CH +#define OCR4CH6_REG OCR4CH +#define OCR4CH7_REG OCR4CH + +/* OCR5AH */ +#define OCR5AH0_REG OCR5AH +#define OCR5AH1_REG OCR5AH +#define OCR5AH2_REG OCR5AH +#define OCR5AH3_REG OCR5AH +#define OCR5AH4_REG OCR5AH +#define OCR5AH5_REG OCR5AH +#define OCR5AH6_REG OCR5AH +#define OCR5AH7_REG OCR5AH + +/* OCR4CL */ +#define OCR4CL0_REG OCR4CL +#define OCR4CL1_REG OCR4CL +#define OCR4CL2_REG OCR4CL +#define OCR4CL3_REG OCR4CL +#define OCR4CL4_REG OCR4CL +#define OCR4CL5_REG OCR4CL +#define OCR4CL6_REG OCR4CL +#define OCR4CL7_REG OCR4CL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR5BH */ +#define OCR5BH0_REG OCR5BH +#define OCR5BH1_REG OCR5BH +#define OCR5BH2_REG OCR5BH +#define OCR5BH3_REG OCR5BH +#define OCR5BH4_REG OCR5BH +#define OCR5BH5_REG OCR5BH +#define OCR5BH6_REG OCR5BH +#define OCR5BH7_REG OCR5BH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR5BL */ +#define OCR5BL0_REG OCR5BL +#define OCR5BL1_REG OCR5BL +#define OCR5BL2_REG OCR5BL +#define OCR5BL3_REG OCR5BL +#define OCR5BL4_REG OCR5BL +#define OCR5BL5_REG OCR5BL +#define OCR5BL6_REG OCR5BL +#define OCR5BL7_REG OCR5BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* TIMSK3 */ +#define TOIE3_REG TIMSK3 +#define OCIE3A_REG TIMSK3 +#define OCIE3B_REG TIMSK3 +#define OCIE3C_REG TIMSK3 +#define ICIE3_REG TIMSK3 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define OCIE1C_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TIMSK4 */ +#define TOIE4_REG TIMSK4 +#define OCIE4A_REG TIMSK4 +#define OCIE4B_REG TIMSK4 +#define OCIE4C_REG TIMSK4 +#define ICIE4_REG TIMSK4 + +/* TIMSK5 */ +#define TOIE5_REG TIMSK5 +#define OCIE5A_REG TIMSK5 +#define OCIE5B_REG TIMSK5 +#define OCIE5C_REG TIMSK5 +#define ICIE5_REG TIMSK5 + +/* TCCR4B */ +#define CS40_REG TCCR4B +#define CS41_REG TCCR4B +#define CS42_REG TCCR4B +#define WGM42_REG TCCR4B +#define WGM43_REG TCCR4B +#define ICES4_REG TCCR4B +#define ICNC4_REG TCCR4B + +/* TCCR4C */ +#define FOC4C_REG TCCR4C +#define FOC4B_REG TCCR4C +#define FOC4A_REG TCCR4C + +/* TCCR4A */ +#define WGM40_REG TCCR4A +#define WGM41_REG TCCR4A +#define COM4C0_REG TCCR4A +#define COM4C1_REG TCCR4A +#define COM4B0_REG TCCR4A +#define COM4B1_REG TCCR4A +#define COM4A0_REG TCCR4A +#define COM4A1_REG TCCR4A + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRW10_REG XMCRA +#define SRW11_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA +#define SRE_REG XMCRA + +/* PINL */ +#define PINL0_REG PINL +#define PINL1_REG PINL +#define PINL2_REG PINL +#define PINL3_REG PINL +#define PINL4_REG PINL +#define PINL5_REG PINL +#define PINL6_REG PINL +#define PINL7_REG PINL + +/* OCR4BL */ +#define OCR4BL0_REG OCR4BL +#define OCR4BL1_REG OCR4BL +#define OCR4BL2_REG OCR4BL +#define OCR4BL3_REG OCR4BL +#define OCR4BL4_REG OCR4BL +#define OCR4BL5_REG OCR4BL +#define OCR4BL6_REG OCR4BL +#define OCR4BL7_REG OCR4BL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* OCR4BH */ +#define OCR4BH0_REG OCR4BH +#define OCR4BH1_REG OCR4BH +#define OCR4BH2_REG OCR4BH +#define OCR4BH3_REG OCR4BH +#define OCR4BH4_REG OCR4BH +#define OCR4BH5_REG OCR4BH +#define OCR4BH6_REG OCR4BH +#define OCR4BH7_REG OCR4BH + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PRR1 */ +#define PRUSART1_REG PRR1 +#define PRUSART2_REG PRR1 +#define PRUSART3_REG PRR1 +#define PRTIM3_REG PRR1 +#define PRTIM4_REG PRR1 +#define PRTIM5_REG PRR1 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define OC0A_PORT PORTB +#define OC0A_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define OC0A_PORT PORTB +#define OC0A_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define ICP1_PORT PORTD +#define ICP1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T0_PORT PORTD +#define T0_BIT 7 + +#define RXD_PORT PORTE +#define RXD_BIT 0 +#define PCINT8_PORT PORTE +#define PCINT8_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 + +#define XCK_PORT PORTE +#define XCK_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define CLKO_PORT PORTE +#define CLKO_BIT 7 +#define ICP3_PORT PORTE +#define ICP3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TDO_PORT PORTF +#define TDO_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + +#define OC0B_PORT PORTG +#define OC0B_BIT 5 + +#define RXD2_PORT PORTH +#define RXD2_BIT 0 + +#define TXD2_PORT PORTH +#define TXD2_BIT 1 + +#define XCK2_PORT PORTH +#define XCK2_BIT 2 + +#define OC4A_PORT PORTH +#define OC4A_BIT 3 + +#define OC4B_PORT PORTH +#define OC4B_BIT 4 + +#define OC2B_PORT PORTH +#define OC2B_BIT 6 + +#define T4_PORT PORTH +#define T4_BIT 7 + +#define RXD3_PORT PORTJ +#define RXD3_BIT 0 +#define PCINT9_PORT PORTJ +#define PCINT9_BIT 0 + +#define TXD3_PORT PORTJ +#define TXD3_BIT 1 +#define PCINT10_PORT PORTJ +#define PCINT10_BIT 1 + +#define XCK3_PORT PORTJ +#define XCK3_BIT 2 +#define PCINT11_PORT PORTJ +#define PCINT11_BIT 2 + +#define PCINT12_PORT PORTJ +#define PCINT12_BIT 3 + +#define PCINT13_PORT PORTJ +#define PCINT13_BIT 4 + +#define PCINT15_PORT PORTJ +#define PCINT15_BIT 6 + +#define ADC8_PORT PORTK +#define ADC8_BIT 0 +#define PCINT16_PORT PORTK +#define PCINT16_BIT 0 + +#define ADC9_PORT PORTK +#define ADC9_BIT 1 +#define PCINT17_PORT PORTK +#define PCINT17_BIT 1 + +#define ADC10_PORT PORTK +#define ADC10_BIT 2 +#define PCINT18_PORT PORTK +#define PCINT18_BIT 2 + +#define ADC11_PORT PORTK +#define ADC11_BIT 3 +#define PCINT19_PORT PORTK +#define PCINT19_BIT 3 + +#define ADC12_PORT PORTK +#define ADC12_BIT 4 +#define PCINT20_PORT PORTK +#define PCINT20_BIT 4 + +#define ADC13_PORT PORTK +#define ADC13_BIT 5 +#define PCINT21_PORT PORTK +#define PCINT21_BIT 5 + +#define ADC14_PORT PORTK +#define ADC14_BIT 6 +#define PCINT22_PORT PORTK +#define PCINT22_BIT 6 + +#define ADC15_PORT PORTK +#define ADC15_BIT 7 +#define PCINT23_PORT PORTK +#define PCINT23_BIT 7 + +#define ICP4_PORT PORTL +#define ICP4_BIT 0 + +#define ICP5_PORT PORTL +#define ICP5_BIT 1 + +#define T5_PORT PORTL +#define T5_BIT 2 + +#define OC5A_PORT PORTL +#define OC5A_BIT 3 + +#define OC5B_PORT PORTL +#define OC5B_BIT 4 + + diff --git a/include/aversive/parts/ATmega644.h b/include/aversive/parts/ATmega644.h new file mode 100644 index 0000000..688a7b1 --- /dev/null +++ b/include/aversive/parts/ATmega644.h @@ -0,0 +1,1104 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 +#define PCINT31_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 +#define CLKO_PORT PORTB +#define CLKO_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0A_PORT PORTB +#define OC0A_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 +#define OC0B_PORT PORTB +#define OC0B_BIT 4 +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 +#define PCINT16_PORT PORTC +#define PCINT16_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 +#define PCINT17_PORT PORTC +#define PCINT17_BIT 1 + +#define TCK_PORT PORTC +#define TCK_BIT 2 +#define PCINT18_PORT PORTC +#define PCINT18_BIT 2 + +#define TMS_PORT PORTC +#define TMS_BIT 3 +#define PCINT19_PORT PORTC +#define PCINT19_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 +#define PCINT20_PORT PORTC +#define PCINT20_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 +#define PCINT21_PORT PORTC +#define PCINT21_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 +#define PCINT22_PORT PORTC +#define PCINT22_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 +#define PCINT23_PORT PORTC +#define PCINT23_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT24_PORT PORTD +#define PCINT24_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT25_PORT PORTD +#define PCINT25_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT26_PORT PORTD +#define PCINT26_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define PCINT27_PORT PORTD +#define PCINT27_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 +#define PCINT28_PORT PORTD +#define PCINT28_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define PCINT29_PORT PORTD +#define PCINT29_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 +#define OC2B_PORT PORTD +#define OC2B_BIT 6 +#define PCINT30_PORT PORTD +#define PCINT30_BIT 6 + +#define OC2A_PORT PORTD +#define OC2A_BIT 7 +#define PCINT31_PORT PORTD +#define PCINT31_BIT 7 + + diff --git a/include/aversive/parts/ATmega644P.h b/include/aversive/parts/ATmega644P.h new file mode 100644 index 0000000..c55a8f3 --- /dev/null +++ b/include/aversive/parts/ATmega644P.h @@ -0,0 +1,1169 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* RAMPZ */ +#define RAMPZ0_REG RAMPZ + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR1_0_REG UDR1 +#define UDR1_1_REG UDR1 +#define UDR1_2_REG UDR1 +#define UDR1_3_REG UDR1 +#define UDR1_4_REG UDR1 +#define UDR1_5_REG UDR1 +#define UDR1_6_REG UDR1 +#define UDR1_7_REG UDR1 + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +#define UBRR_0_REG UBRR1L +#define UBRR_1_REG UBRR1L +#define UBRR_2_REG UBRR1L +#define UBRR_3_REG UBRR1L +#define UBRR_4_REG UBRR1L +#define UBRR_5_REG UBRR1L +#define UBRR_6_REG UBRR1L +#define UBRR_7_REG UBRR1L + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* UBRR1H */ +#define UBRR_8_REG UBRR1H +#define UBRR_9_REG UBRR1H +#define UBRR_10_REG UBRR1H +#define UBRR_11_REG UBRR1H + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH +#define EEAR11_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define JTD_REG MCUCR +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define JTRF_REG MCUSR +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL10_REG UCSR1C +#define UMSEL11_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* PRR0 */ +#define PRADC_REG PRR0 +#define PRUSART0_REG PRR0 +#define PRSPI_REG PRR0 +#define PRTIM1_REG PRR0 +#define PRUSART1_REG PRR0 +#define PRTIM0_REG PRR0 +#define PRTIM2_REG PRR0 +#define PRTWI_REG PRR0 + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 +#define PCINT31_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 +#define CLKO_PORT PORTB +#define CLKO_BIT 1 +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0A_PORT PORTB +#define OC0A_BIT 3 +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 +#define OC0B_PORT PORTB +#define OC0B_BIT 4 +#define PCINT12_PORT PORTB +#define PCINT12_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define PCINT13_PORT PORTB +#define PCINT13_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define PCINT14_PORT PORTB +#define PCINT14_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define PCINT15_PORT PORTB +#define PCINT15_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 +#define PCINT16_PORT PORTC +#define PCINT16_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 +#define PCINT17_PORT PORTC +#define PCINT17_BIT 1 + +#define TCK_PORT PORTC +#define TCK_BIT 2 +#define PCINT18_PORT PORTC +#define PCINT18_BIT 2 + +#define TMS_PORT PORTC +#define TMS_BIT 3 +#define PCINT19_PORT PORTC +#define PCINT19_BIT 3 + +#define TDO_PORT PORTC +#define TDO_BIT 4 +#define PCINT20_PORT PORTC +#define PCINT20_BIT 4 + +#define TDI_PORT PORTC +#define TDI_BIT 5 +#define PCINT21_PORT PORTC +#define PCINT21_BIT 5 + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 +#define PCINT22_PORT PORTC +#define PCINT22_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 +#define PCINT23_PORT PORTC +#define PCINT23_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT24_PORT PORTD +#define PCINT24_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT25_PORT PORTD +#define PCINT25_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define RDX1_PORT PORTD +#define RDX1_BIT 2 +#define PCINT26_PORT PORTD +#define PCINT26_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define PCINT27_PORT PORTD +#define PCINT27_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 +#define XCK1_PORT PORTD +#define XCK1_BIT 4 +#define PCINT28_PORT PORTD +#define PCINT28_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 +#define PCINT29_PORT PORTD +#define PCINT29_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 +#define OC2B_PORT PORTD +#define OC2B_BIT 6 +#define PCINT30_PORT PORTD +#define PCINT30_BIT 6 + +#define OC2A_PORT PORTD +#define OC2A_BIT 7 +#define PCINT31_PORT PORTD +#define PCINT31_BIT 7 + + diff --git a/include/aversive/parts/ATmega645.h b/include/aversive/parts/ATmega645.h new file mode 100644 index 0000000..743512d --- /dev/null +++ b/include/aversive/parts/ATmega645.h @@ -0,0 +1,899 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega6450.h b/include/aversive/parts/ATmega6450.h new file mode 100644 index 0000000..16c0e0a --- /dev/null +++ b/include/aversive/parts/ATmega6450.h @@ -0,0 +1,975 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega649.h b/include/aversive/parts/ATmega649.h new file mode 100644 index 0000000..f5d488f --- /dev/null +++ b/include/aversive/parts/ATmega649.h @@ -0,0 +1,1065 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDPM3_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega6490.h b/include/aversive/parts/ATmega6490.h new file mode 100644 index 0000000..983e879 --- /dev/null +++ b/include/aversive/parts/ATmega6490.h @@ -0,0 +1,1209 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR2A */ +#define OCR2A0_REG OCR2A +#define OCR2A1_REG OCR2A +#define OCR2A2_REG OCR2A +#define OCR2A3_REG OCR2A +#define OCR2A4_REG OCR2A +#define OCR2A5_REG OCR2A +#define OCR2A6_REG OCR2A +#define OCR2A7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRLCD_REG PRR + +/* PORTJ */ +#define PORTJ0_REG PORTJ +#define PORTJ1_REG PORTJ +#define PORTJ2_REG PORTJ +#define PORTJ3_REG PORTJ +#define PORTJ4_REG PORTJ +#define PORTJ5_REG PORTJ +#define PORTJ6_REG PORTJ + +/* PORTH */ +#define PORTH0_REG PORTH +#define PORTH1_REG PORTH +#define PORTH2_REG PORTH +#define PORTH3_REG PORTH +#define PORTH4_REG PORTH +#define PORTH5_REG PORTH +#define PORTH6_REG PORTH +#define PORTH7_REG PORTH + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRJ */ +#define DDJ0_REG DDRJ +#define DDJ1_REG DDRJ +#define DDJ2_REG DDRJ +#define DDJ3_REG DDRJ +#define DDJ4_REG DDRJ +#define DDJ5_REG DDRJ +#define DDJ6_REG DDRJ + +/* DDRH */ +#define DDH0_REG DDRH +#define DDH1_REG DDRH +#define DDH2_REG DDRH +#define DDH3_REG DDRH +#define DDH4_REG DDRH +#define DDH5_REG DDRH +#define DDH6_REG DDRH +#define DDH7_REG DDRH + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* LCDDR3 */ +#define SEG024_REG LCDDR3 +#define SEG025_REG LCDDR3 +#define SEG026_REG LCDDR3 +#define SEG027_REG LCDDR3 +#define SEG028_REG LCDDR3 +#define SEG029_REG LCDDR3 +#define SEG030_REG LCDDR3 +#define SEG031_REG LCDDR3 + +/* LCDDR2 */ +#define SEG016_REG LCDDR2 +#define SEG017_REG LCDDR2 +#define SEG018_REG LCDDR2 +#define SEG019_REG LCDDR2 +#define SEG020_REG LCDDR2 +#define SEG021_REG LCDDR2 +#define SEG022_REG LCDDR2 +#define SEG023_REG LCDDR2 + +/* LCDDR1 */ +#define SEG008_REG LCDDR1 +#define SEG009_REG LCDDR1 +#define SEG010_REG LCDDR1 +#define SEG011_REG LCDDR1 +#define SEG012_REG LCDDR1 +#define SEG013_REG LCDDR1 +#define SEG014_REG LCDDR1 +#define SEG015_REG LCDDR1 + +/* LCDDR0 */ +#define SEG000_REG LCDDR0 +#define SEG001_REG LCDDR0 +#define SEG002_REG LCDDR0 +#define SEG003_REG LCDDR0 +#define SEG004_REG LCDDR0 +#define SEG005_REG LCDDR0 +#define SEG006_REG LCDDR0 +#define SEG007_REG LCDDR0 + +/* LCDDR7 */ +#define SEG116_REG LCDDR7 +#define SEG117_REG LCDDR7 +#define SEG118_REG LCDDR7 +#define SEG119_REG LCDDR7 +#define SEG120_REG LCDDR7 +#define SEG121_REG LCDDR7 +#define SEG122_REG LCDDR7 +#define SEG123_REG LCDDR7 + +/* LCDDR6 */ +#define SEG108_REG LCDDR6 +#define SEG109_REG LCDDR6 +#define SEG110_REG LCDDR6 +#define SEG111_REG LCDDR6 +#define SEG112_REG LCDDR6 +#define SEG113_REG LCDDR6 +#define SEG114_REG LCDDR6 +#define SEG115_REG LCDDR6 + +/* LCDDR5 */ +#define SEG100_REG LCDDR5 +#define SEG101_REG LCDDR5 +#define SEG102_REG LCDDR5 +#define SEG103_REG LCDDR5 +#define SEG104_REG LCDDR5 +#define SEG105_REG LCDDR5 +#define SEG106_REG LCDDR5 +#define SEG107_REG LCDDR5 + +/* LCDDR4 */ +#define SEG032_REG LCDDR4 +#define SEG033_REG LCDDR4 +#define SEG034_REG LCDDR4 +#define SEG035_REG LCDDR4 +#define SEG036_REG LCDDR4 +#define SEG037_REG LCDDR4 +#define SEG038_REG LCDDR4 +#define SEG039_REG LCDDR4 + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* LCDDR9 */ +#define SEG132_REG LCDDR9 +#define SEG133_REG LCDDR9 +#define SEG134_REG LCDDR9 +#define SEG135_REG LCDDR9 +#define SEG136_REG LCDDR9 +#define SEG137_REG LCDDR9 +#define SEG138_REG LCDDR9 +#define SEG139_REG LCDDR9 + +/* LCDDR8 */ +#define SEG124_REG LCDDR8 +#define SEG125_REG LCDDR8 +#define SEG126_REG LCDDR8 +#define SEG127_REG LCDDR8 +#define SEG128_REG LCDDR8 +#define SEG129_REG LCDDR8 +#define SEG130_REG LCDDR8 +#define SEG131_REG LCDDR8 + +/* LCDCRA */ +#define LCDBL_REG LCDCRA +#define LCDIE_REG LCDCRA +#define LCDIF_REG LCDCRA +#define LCDAB_REG LCDCRA +#define LCDEN_REG LCDCRA + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* LCDCRB */ +#define LCDPM0_REG LCDCRB +#define LCDPM1_REG LCDCRB +#define LCDPM2_REG LCDCRB +#define LCDPM3_REG LCDCRB +#define LCDMUX0_REG LCDCRB +#define LCDMUX1_REG LCDCRB +#define LCD2B_REG LCDCRB +#define LCDCS_REG LCDCRB + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A +#define WGM00_REG TCCR0A +#define FOC0A_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSR310_REG GTCCR +#define TSM_REG GTCCR +#define PSR2_REG GTCCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* LCDDR19 */ +#define SEG332_REG LCDDR19 +#define SEG333_REG LCDDR19 +#define SEG334_REG LCDDR19 +#define SEG335_REG LCDDR19 +#define SEG336_REG LCDDR19 +#define SEG337_REG LCDDR19 +#define SEG338_REG LCDDR19 +#define SEG339_REG LCDDR19 + +/* LCDDR18 */ +#define SEG324_REG LCDDR18 +#define SEG325_REG LCDDR18 +#define SEG326_REG LCDDR18 +#define SEG327_REG LCDDR18 +#define SEG328_REG LCDDR18 +#define SEG329_REG LCDDR18 +#define SEG330_REG LCDDR18 +#define SEG331_REG LCDDR18 + +/* LCDDR13 */ +#define SEG224_REG LCDDR13 +#define SEG225_REG LCDDR13 +#define SEG226_REG LCDDR13 +#define SEG227_REG LCDDR13 +#define SEG228_REG LCDDR13 +#define SEG229_REG LCDDR13 +#define SEG230_REG LCDDR13 +#define SEG231_REG LCDDR13 + +/* LCDDR12 */ +#define SEG216_REG LCDDR12 +#define SEG217_REG LCDDR12 +#define SEG218_REG LCDDR12 +#define SEG219_REG LCDDR12 +#define SEG220_REG LCDDR12 +#define SEG221_REG LCDDR12 +#define SEG222_REG LCDDR12 +#define SEG223_REG LCDDR12 + +/* LCDDR11 */ +#define SEG208_REG LCDDR11 +#define SEG209_REG LCDDR11 +#define SEG210_REG LCDDR11 +#define SEG211_REG LCDDR11 +#define SEG212_REG LCDDR11 +#define SEG213_REG LCDDR11 +#define SEG214_REG LCDDR11 +#define SEG215_REG LCDDR11 + +/* LCDDR10 */ +#define SEG200_REG LCDDR10 +#define SEG201_REG LCDDR10 +#define SEG202_REG LCDDR10 +#define SEG203_REG LCDDR10 +#define SEG204_REG LCDDR10 +#define SEG205_REG LCDDR10 +#define SEG206_REG LCDDR10 +#define SEG207_REG LCDDR10 + +/* LCDDR17 */ +#define SEG316_REG LCDDR17 +#define SEG317_REG LCDDR17 +#define SEG318_REG LCDDR17 +#define SEG319_REG LCDDR17 +#define SEG320_REG LCDDR17 +#define SEG321_REG LCDDR17 +#define SEG322_REG LCDDR17 +#define SEG323_REG LCDDR17 + +/* LCDDR16 */ +#define SEG308_REG LCDDR16 +#define SEG309_REG LCDDR16 +#define SEG310_REG LCDDR16 +#define SEG311_REG LCDDR16 +#define SEG312_REG LCDDR16 +#define SEG313_REG LCDDR16 +#define SEG314_REG LCDDR16 +#define SEG315_REG LCDDR16 + +/* LCDDR15 */ +#define SEG300_REG LCDDR15 +#define SEG301_REG LCDDR15 +#define SEG302_REG LCDDR15 +#define SEG303_REG LCDDR15 +#define SEG304_REG LCDDR15 +#define SEG305_REG LCDDR15 +#define SEG306_REG LCDDR15 +#define SEG307_REG LCDDR15 + +/* LCDDR14 */ +#define SEG232_REG LCDDR14 +#define SEG233_REG LCDDR14 +#define SEG234_REG LCDDR14 +#define SEG235_REG LCDDR14 +#define SEG236_REG LCDDR14 +#define SEG237_REG LCDDR14 +#define SEG238_REG LCDDR14 +#define SEG239_REG LCDDR14 + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR +#define JTRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TCCR2A */ +#define CS20_REG TCCR2A +#define CS21_REG TCCR2A +#define CS22_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A +#define WGM20_REG TCCR2A +#define FOC2A_REG TCCR2A + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define JTD_REG MCUCR + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* LCDCCR */ +#define LCDCC0_REG LCDCCR +#define LCDCC1_REG LCDCCR +#define LCDCC2_REG LCDCCR +#define LCDCC3_REG LCDCCR +#define LCDDC0_REG LCDCCR +#define LCDDC1_REG LCDCCR +#define LCDDC2_REG LCDCCR + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* OCR0A */ +#define OCR0A0_REG OCR0A +#define OCR0A1_REG OCR0A +#define OCR0A2_REG OCR0A +#define OCR0A3_REG OCR0A +#define OCR0A4_REG OCR0A +#define OCR0A5_REG OCR0A +#define OCR0A6_REG OCR0A +#define OCR0A7_REG OCR0A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* LCDFRR */ +#define LCDCD0_REG LCDFRR +#define LCDCD1_REG LCDFRR +#define LCDCD2_REG LCDFRR +#define LCDPS0_REG LCDFRR +#define LCDPS1_REG LCDFRR +#define LCDPS2_REG LCDFRR + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define PCIE0_REG EIMSK +#define PCIE1_REG EIMSK +#define PCIE2_REG EIMSK +#define PCIE3_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PINJ */ +#define PINJ0_REG PINJ +#define PINJ1_REG PINJ +#define PINJ2_REG PINJ +#define PINJ3_REG PINJ +#define PINJ4_REG PINJ +#define PINJ5_REG PINJ +#define PINJ6_REG PINJ + +/* PINH */ +#define PINH0_REG PINH +#define PINH1_REG PINH +#define PINH2_REG PINH +#define PINH3_REG PINH +#define PINH4_REG PINH +#define PINH5_REG PINH +#define PINH6_REG PINH +#define PINH7_REG PINH + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 +#define PCINT28_REG PCMSK3 +#define PCINT29_REG PCMSK3 +#define PCINT30_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define PCIF0_REG EIFR +#define PCIF1_REG EIFR +#define PCIF2_REG EIFR +#define PCIF3_REG EIFR + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING +#define PING5_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATmega64A.h b/include/aversive/parts/ATmega64A.h new file mode 100644 index 0000000..4a622c2 --- /dev/null +++ b/include/aversive/parts/ATmega64A.h @@ -0,0 +1,1328 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_64 3 +#define TIMER2_PRESCALER_DIV_256 4 +#define TIMER2_PRESCALER_DIV_1024 5 +#define TIMER2_PRESCALER_DIV_FALL 6 +#define TIMER2_PRESCALER_DIV_RISE 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 64 +#define TIMER2_PRESCALER_REG_4 256 +#define TIMER2_PRESCALER_REG_5 1024 +#define TIMER2_PRESCALER_REG_6 -1 +#define TIMER2_PRESCALER_REG_7 -2 + +/* prescalers timer 3 */ +#define TIMER3_PRESCALER_DIV_0 0 +#define TIMER3_PRESCALER_DIV_1 1 +#define TIMER3_PRESCALER_DIV_8 2 +#define TIMER3_PRESCALER_DIV_64 3 +#define TIMER3_PRESCALER_DIV_256 4 +#define TIMER3_PRESCALER_DIV_1024 5 +#define TIMER3_PRESCALER_DIV_FALL 6 +#define TIMER3_PRESCALER_DIV_RISE 7 + +#define TIMER3_PRESCALER_REG_0 0 +#define TIMER3_PRESCALER_REG_1 1 +#define TIMER3_PRESCALER_REG_2 8 +#define TIMER3_PRESCALER_REG_3 64 +#define TIMER3_PRESCALER_REG_4 256 +#define TIMER3_PRESCALER_REG_5 1024 +#define TIMER3_PRESCALER_REG_6 -1 +#define TIMER3_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER1C_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER3_AVAILABLE +#define TIMER3A_AVAILABLE +#define TIMER3B_AVAILABLE +#define TIMER3C_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW3_NUM 3 +#define SIG_OVERFLOW_TOTAL_NUM 4 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE1C_NUM 3 +#define SIG_OUTPUT_COMPARE2_NUM 4 +#define SIG_OUTPUT_COMPARE3A_NUM 5 +#define SIG_OUTPUT_COMPARE3B_NUM 6 +#define SIG_OUTPUT_COMPARE3C_NUM 7 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM1C_NUM 3 +#define PWM2_NUM 4 +#define PWM3A_NUM 5 +#define PWM3B_NUM 6 +#define PWM3C_NUM 7 +#define PWM_TOTAL_NUM 8 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE3_NUM 1 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTG */ +#define PORTG0_REG PORTG +#define PORTG1_REG PORTG +#define PORTG2_REG PORTG +#define PORTG3_REG PORTG +#define PORTG4_REG PORTG + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL0_REG UCSR0C + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* UDR1 */ +#define UDR10_REG UDR1 +#define UDR11_REG UDR1 +#define UDR12_REG UDR1 +#define UDR13_REG UDR1 +#define UDR14_REG UDR1 +#define UDR15_REG UDR1 +#define UDR16_REG UDR1 +#define UDR17_REG UDR1 + +/* UDR0 */ +#define UDR00_REG UDR0 +#define UDR01_REG UDR0 +#define UDR02_REG UDR0 +#define UDR03_REG UDR0 +#define UDR04_REG UDR0 +#define UDR05_REG UDR0 +#define UDR06_REG UDR0 +#define UDR07_REG UDR0 + +/* EICRB */ +#define ISC40_REG EICRB +#define ISC41_REG EICRB +#define ISC50_REG EICRB +#define ISC51_REG EICRB +#define ISC60_REG EICRB +#define ISC61_REG EICRB +#define ISC70_REG EICRB +#define ISC71_REG EICRB + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA +#define ISC20_REG EICRA +#define ISC21_REG EICRA +#define ISC30_REG EICRA +#define ISC31_REG EICRA + +/* ASSR */ +#define TCR0UB_REG ASSR +#define OCR0UB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* UBRR1L */ +/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */ +/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */ + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* OCR3AL */ +#define OCR3AL0_REG OCR3AL +#define OCR3AL1_REG OCR3AL +#define OCR3AL2_REG OCR3AL +#define OCR3AL3_REG OCR3AL +#define OCR3AL4_REG OCR3AL +#define OCR3AL5_REG OCR3AL +#define OCR3AL6_REG OCR3AL +#define OCR3AL7_REG OCR3AL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* DDRF */ +#define DDF0_REG DDRF +#define DDF1_REG DDRF +#define DDF2_REG DDRF +#define DDF3_REG DDRF +#define DDF4_REG DDRF +#define DDF5_REG DDRF +#define DDF6_REG DDRF +#define DDF7_REG DDRF + +/* DDRG */ +#define DDG0_REG DDRG +#define DDG1_REG DDRG +#define DDG2_REG DDRG +#define DDG3_REG DDRG +#define DDG4_REG DDRG + +/* OCR3AH */ +#define OCR3AH0_REG OCR3AH +#define OCR3AH1_REG OCR3AH +#define OCR3AH2_REG OCR3AH +#define OCR3AH3_REG OCR3AH +#define OCR3AH4_REG OCR3AH +#define OCR3AH5_REG OCR3AH +#define OCR3AH6_REG OCR3AH +#define OCR3AH7_REG OCR3AH + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR321_REG SFIOR +#define PSR0_REG SFIOR +#define PUD_REG SFIOR +#define TSM_REG SFIOR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* UBRR1H */ +/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */ +/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */ + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* ETIFR */ +#define OCF1C_REG ETIFR +#define OCF3C_REG ETIFR +#define TOV3_REG ETIFR +#define OCF3B_REG ETIFR +#define OCF3A_REG ETIFR +#define ICF3_REG ETIFR + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* XDIV */ +#define XDIV0_REG XDIV +#define XDIV1_REG XDIV +#define XDIV2_REG XDIV +#define XDIV3_REG XDIV +#define XDIV4_REG XDIV +#define XDIV5_REG XDIV +#define XDIV6_REG XDIV +#define XDIVEN_REG XDIV + +/* OCR3CH */ +#define OCR3CH0_REG OCR3CH +#define OCR3CH1_REG OCR3CH +#define OCR3CH2_REG OCR3CH +#define OCR3CH3_REG OCR3CH +#define OCR3CH4_REG OCR3CH +#define OCR3CH5_REG OCR3CH +#define OCR3CH6_REG OCR3CH +#define OCR3CH7_REG OCR3CH + +/* ETIMSK */ +#define OCIE1C_REG ETIMSK +#define OCIE3C_REG ETIMSK +#define TOIE3_REG ETIMSK +#define OCIE3B_REG ETIMSK +#define OCIE3A_REG ETIMSK +#define TICIE3_REG ETIMSK + +/* OCR3CL */ +#define OCR3CL0_REG OCR3CL +#define OCR3CL1_REG OCR3CL +#define OCR3CL2_REG OCR3CL +#define OCR3CL3_REG OCR3CL +#define OCR3CL4_REG OCR3CL +#define OCR3CL5_REG OCR3CL +#define OCR3CL6_REG OCR3CL +#define OCR3CL7_REG OCR3CL + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* TCCR3C */ +#define FOC3C_REG TCCR3C +#define FOC3B_REG TCCR3C +#define FOC3A_REG TCCR3C + +/* TCCR3B */ +#define CS30_REG TCCR3B +#define CS31_REG TCCR3B +#define CS32_REG TCCR3B +#define WGM32_REG TCCR3B +#define WGM33_REG TCCR3B +#define ICES3_REG TCCR3B +#define ICNC3_REG TCCR3B + +/* TCCR3A */ +#define WGM30_REG TCCR3A +#define WGM31_REG TCCR3A +#define COM3C0_REG TCCR3A +#define COM3C1_REG TCCR3A +#define COM3B0_REG TCCR3A +#define COM3B1_REG TCCR3A +#define COM3A0_REG TCCR3A +#define COM3A1_REG TCCR3A + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* TCNT3H */ +#define TCNT3H0_REG TCNT3H +#define TCNT3H1_REG TCNT3H +#define TCNT3H2_REG TCNT3H +#define TCNT3H3_REG TCNT3H +#define TCNT3H4_REG TCNT3H +#define TCNT3H5_REG TCNT3H +#define TCNT3H6_REG TCNT3H +#define TCNT3H7_REG TCNT3H + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* TCNT3L */ +#define TCN3L0_REG TCNT3L +#define TCN3L1_REG TCNT3L +#define TCN3L2_REG TCNT3L +#define TCN3L3_REG TCNT3L +#define TCN3L4_REG TCNT3L +#define TCN3L5_REG TCNT3L +#define TCN3L6_REG TCNT3L +#define TCN3L7_REG TCNT3L + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define JTRF_REG MCUCSR +#define JTD_REG MCUCSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* UBRR0H */ +/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */ +/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */ + +/* UBRR0L */ +/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */ +/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */ + +/* EEARH */ +#define EEAR8_REG EEARH +#define EEAR9_REG EEARH +#define EEAR10_REG EEARH + +/* EEARL */ +#define EEARL0_REG EEARL +#define EEARL1_REG EEARL +#define EEARL2_REG EEARL +#define EEARL3_REG EEARL +#define EEARL4_REG EEARL +#define EEARL5_REG EEARL +#define EEARL6_REG EEARL +#define EEARL7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define SM2_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1CL */ +#define OCR1CL0_REG OCR1CL +#define OCR1CL1_REG OCR1CL +#define OCR1CL2_REG OCR1CL +#define OCR1CL3_REG OCR1CL +#define OCR1CL4_REG OCR1CL +#define OCR1CL5_REG OCR1CL +#define OCR1CL6_REG OCR1CL +#define OCR1CL7_REG OCR1CL + +/* OCR1CH */ +#define OCR1CH0_REG OCR1CH +#define OCR1CH1_REG OCR1CH +#define OCR1CH2_REG OCR1CH +#define OCR1CH3_REG OCR1CH +#define OCR1CH4_REG OCR1CH +#define OCR1CH5_REG OCR1CH +#define OCR1CH6_REG OCR1CH +#define OCR1CH7_REG OCR1CH + +/* OCDR */ +#define OCDR0_REG OCDR +#define OCDR1_REG OCDR +#define OCDR2_REG OCDR +#define OCDR3_REG OCDR +#define OCDR4_REG OCDR +#define OCDR5_REG OCDR +#define OCDR6_REG OCDR +#define OCDR7_REG OCDR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR +#define INTF2_REG EIFR +#define INTF3_REG EIFR +#define INTF4_REG EIFR +#define INTF5_REG EIFR +#define INTF6_REG EIFR +#define INTF7_REG EIFR + +/* UCSR1B */ +#define TXB81_REG UCSR1B +#define RXB81_REG UCSR1B +#define UCSZ12_REG UCSR1B +#define TXEN1_REG UCSR1B +#define RXEN1_REG UCSR1B +#define UDRIE1_REG UCSR1B +#define TXCIE1_REG UCSR1B +#define RXCIE1_REG UCSR1B + +/* UCSR1C */ +#define UCPOL1_REG UCSR1C +#define UCSZ10_REG UCSR1C +#define UCSZ11_REG UCSR1C +#define USBS1_REG UCSR1C +#define UPM10_REG UCSR1C +#define UPM11_REG UCSR1C +#define UMSEL1_REG UCSR1C + +/* UCSR1A */ +#define MPCM1_REG UCSR1A +#define U2X1_REG UCSR1A +#define UPE1_REG UCSR1A +#define DOR1_REG UCSR1A +#define FE1_REG UCSR1A +#define UDRE1_REG UCSR1A +#define TXC1_REG UCSR1A +#define RXC1_REG UCSR1A + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK +#define INT2_REG EIMSK +#define INT3_REG EIMSK +#define INT4_REG EIMSK +#define INT5_REG EIMSK +#define INT6_REG EIMSK +#define INT7_REG EIMSK + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1C0_REG TCCR1A +#define COM1C1_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PORTF */ +#define PORTF0_REG PORTF +#define PORTF1_REG PORTF +#define PORTF2_REG PORTF +#define PORTF3_REG PORTF +#define PORTF4_REG PORTF +#define PORTF5_REG PORTF +#define PORTF6_REG PORTF +#define PORTF7_REG PORTF + +/* TCCR1C */ +#define FOC1C_REG TCCR1C +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* ICR3H */ +#define ICR3H0_REG ICR3H +#define ICR3H1_REG ICR3H +#define ICR3H2_REG ICR3H +#define ICR3H3_REG ICR3H +#define ICR3H4_REG ICR3H +#define ICR3H5_REG ICR3H +#define ICR3H6_REG ICR3H +#define ICR3H7_REG ICR3H + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE +#define DDE3_REG DDRE +#define DDE4_REG DDRE +#define DDE5_REG DDRE +#define DDE6_REG DDRE +#define DDE7_REG DDRE + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* ICR3L */ +#define ICR3L0_REG ICR3L +#define ICR3L1_REG ICR3L +#define ICR3L2_REG ICR3L +#define ICR3L3_REG ICR3L +#define ICR3L4_REG ICR3L +#define ICR3L5_REG ICR3L +#define ICR3L6_REG ICR3L +#define ICR3L7_REG ICR3L + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE +#define PORTE3_REG PORTE +#define PORTE4_REG PORTE +#define PORTE5_REG PORTE +#define PORTE6_REG PORTE +#define PORTE7_REG PORTE + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* OCR3BL */ +#define OCR3BL0_REG OCR3BL +#define OCR3BL1_REG OCR3BL +#define OCR3BL2_REG OCR3BL +#define OCR3BL3_REG OCR3BL +#define OCR3BL4_REG OCR3BL +#define OCR3BL5_REG OCR3BL +#define OCR3BL6_REG OCR3BL +#define OCR3BL7_REG OCR3BL + +/* OCR3BH */ +#define OCR3BH0_REG OCR3BH +#define OCR3BH1_REG OCR3BH +#define OCR3BH2_REG OCR3BH +#define OCR3BH3_REG OCR3BH +#define OCR3BH4_REG OCR3BH +#define OCR3BH5_REG OCR3BH +#define OCR3BH6_REG OCR3BH +#define OCR3BH7_REG OCR3BH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* XMCRB */ +#define XMM0_REG XMCRB +#define XMM1_REG XMCRB +#define XMM2_REG XMCRB +#define XMBK_REG XMCRB + +/* XMCRA */ +#define SRW11_REG XMCRA +#define SRW00_REG XMCRA +#define SRW01_REG XMCRA +#define SRL0_REG XMCRA +#define SRL1_REG XMCRA +#define SRL2_REG XMCRA + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PING */ +#define PING0_REG PING +#define PING1_REG PING +#define PING2_REG PING +#define PING3_REG PING +#define PING4_REG PING + +/* PINF */ +#define PINF0_REG PINF +#define PINF1_REG PINF +#define PINF2_REG PINF +#define PINF3_REG PINF +#define PINF4_REG PINF +#define PINF5_REG PINF +#define PINF6_REG PINF +#define PINF7_REG PINF + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE +#define PINE3_REG PINE +#define PINE4_REG PINE +#define PINE5_REG PINE +#define PINE6_REG PINE +#define PINE7_REG PINE + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define SS_PORT PORTB +#define SS_BIT 0 + +#define SCK_PORT PORTB +#define SCK_BIT 1 + +#define MOSI_PORT PORTB +#define MOSI_BIT 2 + +#define MISO_PORT PORTB +#define MISO_BIT 3 + +#define OC0_PORT PORTB +#define OC0_BIT 4 +#define PWM0_PORT PORTB +#define PWM0_BIT 4 + +#define OC1A_PORT PORTB +#define OC1A_BIT 5 +#define PWM1A_PORT PORTB +#define PWM1A_BIT 5 + +#define OC1B_PORT PORTB +#define OC1B_BIT 6 +#define PWM1B_PORT PORTB +#define PWM1B_BIT 6 + +#define OC2_PORT PORTB +#define OC2_BIT 7 +#define PWM2_PORT PORTB +#define PWM2_BIT 7 +#define OC1C_PORT PORTB +#define OC1C_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define SCL_PORT PORTD +#define SCL_BIT 0 +#define INT0_PORT PORTD +#define INT0_BIT 0 + +#define SDA_PORT PORTD +#define SDA_BIT 1 +#define INT1_PORT PORTD +#define INT1_BIT 1 + +#define RXD1_PORT PORTD +#define RXD1_BIT 2 +#define INT2_PORT PORTD +#define INT2_BIT 2 + +#define TXD1_PORT PORTD +#define TXD1_BIT 3 +#define INT3_PORT PORTD +#define INT3_BIT 3 + +#define IC1_PORT PORTD +#define IC1_BIT 4 + +#define XCK1_PORT PORTD +#define XCK1_BIT 5 + +#define T1_PORT PORTD +#define T1_BIT 6 + +#define T2_PORT PORTD +#define T2_BIT 7 + +#define RXD0_PORT PORTE +#define RXD0_BIT 0 +#define PDI_PORT PORTE +#define PDI_BIT 0 + +#define TXD0_PORT PORTE +#define TXD0_BIT 1 +#define PDO_PORT PORTE +#define PDO_BIT 1 + +#define XCK0_PORT PORTE +#define XCK0_BIT 2 +#define AIN0_PORT PORTE +#define AIN0_BIT 2 + +#define OC3A_PORT PORTE +#define OC3A_BIT 3 +#define AIN1_PORT PORTE +#define AIN1_BIT 3 + +#define OC3B_PORT PORTE +#define OC3B_BIT 4 +#define INT4_PORT PORTE +#define INT4_BIT 4 + +#define OC3C_PORT PORTE +#define OC3C_BIT 5 +#define INT5_PORT PORTE +#define INT5_BIT 5 + +#define T3_PORT PORTE +#define T3_BIT 6 +#define INT6_PORT PORTE +#define INT6_BIT 6 + +#define IC3_PORT PORTE +#define IC3_BIT 7 +#define INT7_PORT PORTE +#define INT7_BIT 7 + +#define ADC0_PORT PORTF +#define ADC0_BIT 0 + +#define ADC1_PORT PORTF +#define ADC1_BIT 1 + +#define ADC2_PORT PORTF +#define ADC2_BIT 2 + +#define ADC3_PORT PORTF +#define ADC3_BIT 3 + +#define ADC4_PORT PORTF +#define ADC4_BIT 4 +#define TCK_PORT PORTF +#define TCK_BIT 4 + +#define ADC5_PORT PORTF +#define ADC5_BIT 5 +#define TMS_PORT PORTF +#define TMS_BIT 5 + +#define ADC6_PORT PORTF +#define ADC6_BIT 6 +#define TD0_PORT PORTF +#define TD0_BIT 6 + +#define ADC7_PORT PORTF +#define ADC7_BIT 7 +#define TDI_PORT PORTF +#define TDI_BIT 7 + +#define WR_PORT PORTG +#define WR_BIT 0 + +#define RD_PORT PORTG +#define RD_BIT 1 + +#define ALE_PORT PORTG +#define ALE_BIT 2 + +#define TOSC2_PORT PORTG +#define TOSC2_BIT 3 + +#define TOSC1_PORT PORTG +#define TOSC1_BIT 4 + + diff --git a/include/aversive/parts/ATmega8.h b/include/aversive/parts/ATmega8.h new file mode 100644 index 0000000..9717237 --- /dev/null +++ b/include/aversive/parts/ATmega8.h @@ -0,0 +1,745 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE2_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM2_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADFR_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR2_REG SFIOR +#define PSR10_REG SFIOR +#define PUD_REG SFIOR +#define ADHSM_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SM2_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ICP_PORT PORTB +#define ICP_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2_PORT PORTB +#define OC2_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define IN1_PORT PORTD +#define IN1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 + + diff --git a/include/aversive/parts/ATmega8515.h b/include/aversive/parts/ATmega8515.h new file mode 100644 index 0000000..3335db2 --- /dev/null +++ b/include/aversive/parts/ATmega8515.h @@ -0,0 +1,708 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +/* #define URSEL_REG UCSRC */ /* dup in UBRRH */ + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define OCIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define TICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define PSR10_REG SFIOR +#define PUD_REG SFIOR +#define XMM0_REG SFIOR +#define XMM1_REG SFIOR +#define XMM2_REG SFIOR +#define XMBK_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* EMCUCR */ +#define ISC2_REG EMCUCR +#define SRW11_REG EMCUCR +#define SRW00_REG EMCUCR +#define SRW01_REG EMCUCR +#define SRL0_REG EMCUCR +#define SRL1_REG EMCUCR +#define SRL2_REG EMCUCR +#define SM0_REG EMCUCR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH +/* #define URSEL_REG UBRRH */ /* dup in UCSRC */ + +/* DDRE */ +#define DDE0_REG DDRE +#define DDE1_REG DDRE +#define DDE2_REG DDRE + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* PORTE */ +#define PORTE0_REG PORTE +#define PORTE1_REG PORTE +#define PORTE2_REG PORTE + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR +#define SM2_REG MCUCSR + +/* TIFR */ +#define OCF0_REG TIFR +#define TOV0_REG TIFR +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* PINE */ +#define PINE0_REG PINE +#define PINE1_REG PINE +#define PINE2_REG PINE + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SRW10_REG MCUCR +#define SRE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define AD0_PORT PORTA +#define AD0_BIT 0 + +#define AD1_PORT PORTA +#define AD1_BIT 1 + +#define AD2_PORT PORTA +#define AD2_BIT 2 + +#define AD3_PORT PORTA +#define AD3_BIT 3 + +#define AD4_PORT PORTA +#define AD4_BIT 4 + +#define AD5_PORT PORTA +#define AD5_BIT 5 + +#define AD6_PORT PORTA +#define AD6_BIT 6 + +#define AD7_PORT PORTA +#define AD7_BIT 7 + +#define OC0_PORT PORTB +#define OC0_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define A8_PORT PORTC +#define A8_BIT 0 + +#define A9_PORT PORTC +#define A9_BIT 1 + +#define A10_PORT PORTC +#define A10_BIT 2 + +#define A11_PORT PORTC +#define A11_BIT 3 + +#define A12_PORT PORTC +#define A12_BIT 4 + +#define A13_PORT PORTC +#define A13_BIT 5 + +#define A14_PORT PORTC +#define A14_BIT 6 + +#define A15_PORT PORTC +#define A15_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define WR_PORT PORTD +#define WR_BIT 6 + +#define RD_PORT PORTD +#define RD_BIT 7 + +#define ICP_PORT PORTE +#define ICP_BIT 0 +#define INT2_PORT PORTE +#define INT2_BIT 0 + +#define ALE_PORT PORTE +#define ALE_BIT 1 + +#define OC1B_PORT PORTE +#define OC1B_BIT 2 + + diff --git a/include/aversive/parts/ATmega8535.h b/include/aversive/parts/ATmega8535.h new file mode 100644 index 0000000..23cae03 --- /dev/null +++ b/include/aversive/parts/ATmega8535.h @@ -0,0 +1,815 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE2_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM2_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define WGM01_REG TCCR0 +#define COM00_REG TCCR0 +#define COM01_REG TCCR0 +#define WGM00_REG TCCR0 +#define FOC0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT2_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF2_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ADTS0_REG SFIOR +#define ADTS1_REG SFIOR +#define ADTS2_REG SFIOR +#define PSR10_REG SFIOR +#define PSR2_REG SFIOR +#define PUD_REG SFIOR +#define ACME_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +/* #define URSEL_REG UCSRC */ /* dup in UBRRH */ + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH +/* #define URSEL_REG UBRRH */ /* dup in UCSRC */ + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* MCUCSR */ +#define ISC2_REG MCUCSR +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define SM2_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR0 */ +#define OCR0_0_REG OCR0 +#define OCR0_1_REG OCR0 +#define OCR0_2_REG OCR0 +#define OCR0_3_REG OCR0 +#define OCR0_4_REG OCR0 +#define OCR0_5_REG OCR0 +#define OCR0_6_REG OCR0 +#define OCR0_7_REG OCR0 + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 + +#define ADc5_PORT PORTA +#define ADc5_BIT 5 + +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define XCK_PORT PORTB +#define XCK_BIT 0 +#define T0_PORT PORTB +#define T0_BIT 0 + +#define T1_PORT PORTB +#define T1_BIT 1 + +#define AIN0_PORT PORTB +#define AIN0_BIT 2 +#define INT2_PORT PORTB +#define INT2_BIT 2 + +#define AIN1_PORT PORTB +#define AIN1_BIT 3 +#define OC0_PORT PORTB +#define OC0_BIT 3 + +#define SS_PORT PORTB +#define SS_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 + +#define SCL_PORT PORTC +#define SCL_BIT 0 + +#define SDA_PORT PORTC +#define SDA_BIT 1 + + + + + +#define TOSC1_PORT PORTC +#define TOSC1_BIT 6 + +#define TOSC2_PORT PORTC +#define TOSC2_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define OC1B_PORT PORTD +#define OC1B_BIT 4 + +#define OC1A_PORT PORTD +#define OC1A_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + +#define OC2_PORT PORTD +#define OC2_BIT 7 + + diff --git a/include/aversive/parts/ATmega88.h b/include/aversive/parts/ATmega88.h new file mode 100644 index 0000000..cb95de2 --- /dev/null +++ b/include/aversive/parts/ATmega88.h @@ -0,0 +1,995 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega88P.h b/include/aversive/parts/ATmega88P.h new file mode 100644 index 0000000..d9de6d0 --- /dev/null +++ b/include/aversive/parts/ATmega88P.h @@ -0,0 +1,997 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega88PA.h b/include/aversive/parts/ATmega88PA.h new file mode 100644 index 0000000..d9de6d0 --- /dev/null +++ b/include/aversive/parts/ATmega88PA.h @@ -0,0 +1,997 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE +#define TIMER2A_AVAILABLE +#define TIMER2B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE2A_NUM 4 +#define SIG_OUTPUT_COMPARE2B_NUM 5 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM2A_NUM 4 +#define PWM2B_NUM 5 +#define PWM_TOTAL_NUM 6 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* OCR2B */ +#define OCR2B_0_REG OCR2B +#define OCR2B_1_REG OCR2B +#define OCR2B_2_REG OCR2B +#define OCR2B_3_REG OCR2B +#define OCR2B_4_REG OCR2B +#define OCR2B_5_REG OCR2B +#define OCR2B_6_REG OCR2B +#define OCR2B_7_REG OCR2B + +/* OCR2A */ +#define OCR2A_0_REG OCR2A +#define OCR2A_1_REG OCR2A +#define OCR2A_2_REG OCR2A +#define OCR2A_3_REG OCR2A +#define OCR2A_4_REG OCR2A +#define OCR2A_5_REG OCR2A +#define OCR2A_6_REG OCR2A +#define OCR2A_7_REG OCR2A + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* PRR */ +#define PRADC_REG PRR +#define PRUSART0_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTIM2_REG PRR +#define PRTWI_REG PRR + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* UCSR0A */ +#define MPCM0_REG UCSR0A +#define U2X0_REG UCSR0A +#define UPE0_REG UCSR0A +#define DOR0_REG UCSR0A +#define FE0_REG UCSR0A +#define UDRE0_REG UCSR0A +#define TXC0_REG UCSR0A +#define RXC0_REG UCSR0A + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* UCSR0B */ +#define TXB80_REG UCSR0B +#define RXB80_REG UCSR0B +#define UCSZ02_REG UCSR0B +#define TXEN0_REG UCSR0B +#define RXEN0_REG UCSR0B +#define UDRIE0_REG UCSR0B +#define TXCIE0_REG UCSR0B +#define RXCIE0_REG UCSR0B + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* UDR0 */ +#define UDR0_0_REG UDR0 +#define UDR0_1_REG UDR0 +#define UDR0_2_REG UDR0 +#define UDR0_3_REG UDR0 +#define UDR0_4_REG UDR0 +#define UDR0_5_REG UDR0 +#define UDR0_6_REG UDR0 +#define UDR0_7_REG UDR0 + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 + +/* ASSR */ +#define TCR2BUB_REG ASSR +#define TCR2AUB_REG ASSR +#define OCR2BUB_REG ASSR +#define OCR2AUB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR +#define EXCLK_REG ASSR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* TIFR2 */ +#define TOV2_REG TIFR2 +#define OCF2A_REG TIFR2 +#define OCF2B_REG TIFR2 + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR +#define PSRASY_REG GTCCR + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCCR2A */ +#define WGM20_REG TCCR2A +#define WGM21_REG TCCR2A +#define COM2B0_REG TCCR2A +#define COM2B1_REG TCCR2A +#define COM2A0_REG TCCR2A +#define COM2A1_REG TCCR2A + +/* TCCR2B */ +#define CS20_REG TCCR2B +#define CS21_REG TCCR2B +#define CS22_REG TCCR2B +#define WGM22_REG TCCR2B +#define FOC2B_REG TCCR2B +#define FOC2A_REG TCCR2B + +/* UBRR0H */ +#define UBRR8_REG UBRR0H +#define UBRR9_REG UBRR0H +#define UBRR10_REG UBRR0H +#define UBRR11_REG UBRR0H + +/* UBRR0L */ +#define UBRR0_REG UBRR0L +#define UBRR1_REG UBRR0L +#define UBRR2_REG UBRR0L +#define UBRR3_REG UBRR0L +#define UBRR4_REG UBRR0L +#define UBRR5_REG UBRR0L +#define UBRR6_REG UBRR0L +#define UBRR7_REG UBRR0L + +/* EEARH */ +#define EEAR8_REG EEARH + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* MCUCR */ +#define IVCE_REG MCUCR +#define IVSEL_REG MCUCR +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCROA_0_REG OCR0A +#define OCROA_1_REG OCR0A +#define OCROA_2_REG OCR0A +#define OCROA_3_REG OCR0A +#define OCROA_4_REG OCR0A +#define OCROA_5_REG OCR0A +#define OCROA_6_REG OCR0A +#define OCROA_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* UCSR0C */ +#define UCPOL0_REG UCSR0C +#define UCSZ00_REG UCSR0C +#define UCSZ01_REG UCSR0C +#define USBS0_REG UCSR0C +#define UPM00_REG UCSR0C +#define UPM01_REG UCSR0C +#define UMSEL00_REG UCSR0C +#define UMSEL01_REG UCSR0C + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define BLBSET_REG SPMCSR +#define RWWSRE_REG SPMCSR +#define RWWSB_REG SPMCSR +#define SPMIE_REG SPMCSR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TIMSK2 */ +#define TOIE2_REG TIMSK2 +#define OCIE2A_REG TIMSK2 +#define OCIE2B_REG TIMSK2 + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATmega8A.h b/include/aversive/parts/ATmega8A.h new file mode 100644 index 0000000..9717237 --- /dev/null +++ b/include/aversive/parts/ATmega8A.h @@ -0,0 +1,745 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + +/* prescalers timer 2 */ +#define TIMER2_PRESCALER_DIV_0 0 +#define TIMER2_PRESCALER_DIV_1 1 +#define TIMER2_PRESCALER_DIV_8 2 +#define TIMER2_PRESCALER_DIV_32 3 +#define TIMER2_PRESCALER_DIV_64 4 +#define TIMER2_PRESCALER_DIV_128 5 +#define TIMER2_PRESCALER_DIV_256 6 +#define TIMER2_PRESCALER_DIV_1024 7 + +#define TIMER2_PRESCALER_REG_0 0 +#define TIMER2_PRESCALER_REG_1 1 +#define TIMER2_PRESCALER_REG_2 8 +#define TIMER2_PRESCALER_REG_3 32 +#define TIMER2_PRESCALER_REG_4 64 +#define TIMER2_PRESCALER_REG_5 128 +#define TIMER2_PRESCALER_REG_6 256 +#define TIMER2_PRESCALER_REG_7 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE +#define TIMER2_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW2_NUM 2 +#define SIG_OVERFLOW_TOTAL_NUM 3 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1A_NUM 0 +#define SIG_OUTPUT_COMPARE1B_NUM 1 +#define SIG_OUTPUT_COMPARE2_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM1A_NUM 0 +#define PWM1B_NUM 1 +#define PWM2_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* GICR */ +#define IVCE_REG GICR +#define IVSEL_REG GICR +#define INT0_REG GICR +#define INT1_REG GICR + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TICIE1_REG TIMSK +#define TOIE2_REG TIMSK +#define OCIE2_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADFR_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* SFIOR */ +#define ACME_REG SFIOR +#define PSR2_REG SFIOR +#define PSR10_REG SFIOR +#define PUD_REG SFIOR +#define ADHSM_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC +#define URSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* SPMCR */ +#define SPMEN_REG SPMCR +#define PGERS_REG SPMCR +#define PGWRT_REG SPMCR +#define BLBSET_REG SPMCR +#define RWWSRE_REG SPMCR +#define RWWSB_REG SPMCR +#define SPMIE_REG SPMCR + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* MCUCSR */ +#define PORF_REG MCUCSR +#define EXTRF_REG MCUCSR +#define BORF_REG MCUCSR +#define WDRF_REG MCUCSR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* TCCR2 */ +#define CS20_REG TCCR2 +#define CS21_REG TCCR2 +#define CS22_REG TCCR2 +#define WGM21_REG TCCR2 +#define COM20_REG TCCR2 +#define COM21_REG TCCR2 +#define WGM20_REG TCCR2 +#define FOC2_REG TCCR2 + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define ICF1_REG TIFR +#define TOV2_REG TIFR +#define OCF2_REG TIFR + +/* EEARH */ +#define EEAR8_REG EEARH + +/* TCNT2 */ +#define TCNT2_0_REG TCNT2 +#define TCNT2_1_REG TCNT2 +#define TCNT2_2_REG TCNT2 +#define TCNT2_3_REG TCNT2 +#define TCNT2_4_REG TCNT2 +#define TCNT2_5_REG TCNT2 +#define TCNT2_6_REG TCNT2 +#define TCNT2_7_REG TCNT2 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SM2_REG MCUCR +#define SE_REG MCUCR + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* ASSR */ +#define TCR2UB_REG ASSR +#define OCR2UB_REG ASSR +#define TCN2UB_REG ASSR +#define AS2_REG ASSR + +/* OCR2 */ +#define OCR2_0_REG OCR2 +#define OCR2_1_REG OCR2 +#define OCR2_2_REG OCR2 +#define OCR2_3_REG OCR2 +#define OCR2_4_REG OCR2 +#define OCR2_5_REG OCR2 +#define OCR2_6_REG OCR2 +#define OCR2_7_REG OCR2 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* pins mapping */ +#define ICP_PORT PORTB +#define ICP_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2_PORT PORTB +#define OC2_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 + +#define IN1_PORT PORTD +#define IN1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 + + diff --git a/include/aversive/parts/ATtiny10.h b/include/aversive/parts/ATtiny10.h new file mode 100644 index 0000000..2300581 --- /dev/null +++ b/include/aversive/parts/ATtiny10.h @@ -0,0 +1,376 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPSR */ +#define CLKPS0_REG CLKPSR +#define CLKPS1_REG CLKPSR +#define CLKPS2_REG CLKPSR +#define CLKPS3_REG CLKPSR + +/* VLMCSR */ +#define VLM0_REG VLMCSR +#define VLM1_REG VLMCSR +#define VLMIE_REG VLMCSR +#define VLMF_REG VLMCSR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX + +/* TCNT0H */ +#define TCNT0_8_REG TCNT0H +#define TCNT0_9_REG TCNT0H +#define TCNT0_10_REG TCNT0H +#define TCNT0_11_REG TCNT0H +#define TCNT0_12_REG TCNT0H +#define TCNT0_13_REG TCNT0H +#define TCNT0_14_REG TCNT0H +#define TCNT0_15_REG TCNT0H + +/* PORTCR */ +#define BBMB_REG PORTCR + +/* CCP */ +#define CCP0_REG CCP +#define CCP1_REG CCP +#define CCP2_REG CCP +#define CCP3_REG CCP +#define CCP4_REG CCP +#define CCP5_REG CCP +#define CCP6_REG CCP +#define CCP7_REG CCP + +/* TCNT0L */ +#define TCNT0_0_REG TCNT0L +#define TCNT0_1_REG TCNT0L +#define TCNT0_2_REG TCNT0L +#define TCNT0_3_REG TCNT0L +#define TCNT0_4_REG TCNT0L +#define TCNT0_5_REG TCNT0L +#define TCNT0_6_REG TCNT0L +#define TCNT0_7_REG TCNT0L + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* GTCCR */ +#define PSR_REG GTCCR +#define TSM_REG GTCCR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB + +/* RSTFLR */ +#define PORF_REG RSTFLR +#define EXTRF_REG RSTFLR +#define WDRF_REG RSTFLR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PCIFR */ +#define PCIF0_REG PCIFR + +/* PRR */ +#define PRTIM0_REG PRR +#define PRADC_REG PRR + +/* OCR0BL */ +#define OCR0B0_REG OCR0BL +#define OCR0B1_REG OCR0BL +#define OCR0B2_REG OCR0BL +#define OCR0B3_REG OCR0BL +#define OCR0B4_REG OCR0BL +#define OCR0B5_REG OCR0BL +#define OCR0B6_REG OCR0BL +#define OCR0B7_REG OCR0BL + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK + +/* ADCL */ +#define ADC0_REG ADCL +#define ADC1_REG ADCL +#define ADC2_REG ADCL +#define ADC3_REG ADCL +#define ADC4_REG ADCL +#define ADC5_REG ADCL +#define ADC6_REG ADCL +#define ADC7_REG ADCL + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR +#define SM2_REG SMCR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB + +/* PCICR */ +#define PCIE0_REG PCICR + +/* NVMCSR */ +#define NVMBSY_REG NVMCSR + +/* EIMSK */ +#define INT0_REG EIMSK + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 +#define ICIE0_REG TIMSK0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define WGM03_REG TCCR0B +#define ICES0_REG TCCR0B +#define ICNC0_REG TCCR0B + +/* TCCR0C */ +#define FOC0B_REG TCCR0C +#define FOC0A_REG TCCR0C + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* CLKMSR */ +#define CLKMS0_REG CLKMSR +#define CLKMS1_REG CLKMSR + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB + +/* EIFR */ +#define INTF0_REG EIFR + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 + +/* OCR0AL */ +#define OCR0A0_REG OCR0AL +#define OCR0A1_REG OCR0AL +#define OCR0A2_REG OCR0AL +#define OCR0A3_REG OCR0AL +#define OCR0A4_REG OCR0AL +#define OCR0A5_REG OCR0AL +#define OCR0A6_REG OCR0AL +#define OCR0A7_REG OCR0AL + +/* NVMCMD */ +#define NVMCMD0_REG NVMCMD +#define NVMCMD1_REG NVMCMD +#define NVMCMD2_REG NVMCMD +#define NVMCMD3_REG NVMCMD +#define NVMCMD4_REG NVMCMD +#define NVMCMD5_REG NVMCMD + +/* ICR0L */ +#define ICR0_0_REG ICR0L +#define ICR0_1_REG ICR0L +#define ICR0_2_REG ICR0L +#define ICR0_3_REG ICR0L +#define ICR0_4_REG ICR0L +#define ICR0_5_REG ICR0L +#define ICR0_6_REG ICR0L +#define ICR0_7_REG ICR0L + +/* OCR0AH */ +#define OCR0A8_REG OCR0AH +#define OCR0A9_REG OCR0AH +#define OCR0A10_REG OCR0AH +#define OCR0A11_REG OCR0AH +#define OCR0A12_REG OCR0AH +#define OCR0A13_REG OCR0AH +#define OCR0A14_REG OCR0AH +#define OCR0A15_REG OCR0AH + +/* ICR0H */ +#define ICR0_8_REG ICR0H +#define ICR0_9_REG ICR0H +#define ICR0_10_REG ICR0H +#define ICR0_11_REG ICR0H +#define ICR0_12_REG ICR0H +#define ICR0_13_REG ICR0H +#define ICR0_14_REG ICR0H +#define ICR0_15_REG ICR0H + +/* PUEB */ +#define PUEB0_REG PUEB +#define PUEB1_REG PUEB +#define PUEB2_REG PUEB +#define PUEB3_REG PUEB + +/* OCR0BH */ +#define OCR0B8_REG OCR0BH +#define OCR0B9_REG OCR0BH +#define OCR0B10_REG OCR0BH +#define OCR0B11_REG OCR0BH +#define OCR0B12_REG OCR0BH +#define OCR0B13_REG OCR0BH +#define OCR0B14_REG OCR0BH +#define OCR0B15_REG OCR0BH + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 +#define ICF0_REG TIFR0 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny11.h b/include/aversive/parts/ATtiny11.h new file mode 100644 index 0000000..7dd6238 --- /dev/null +++ b/include/aversive/parts/ATtiny11.h @@ -0,0 +1,171 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TIFR */ +#define TOV0_REG TIFR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* pins mapping */ +#define AIN0_PORT PORTB +#define AIN0_BIT 0 + +#define INT0_PORT PORTB +#define INT0_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 + +#define T0_PORT PORTB +#define T0_BIT 2 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 3 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 4 + +#define RESET_PORT PORTB +#define RESET_BIT 5 + + diff --git a/include/aversive/parts/ATtiny12.h b/include/aversive/parts/ATtiny12.h new file mode 100644 index 0000000..df71674 --- /dev/null +++ b/include/aversive/parts/ATtiny12.h @@ -0,0 +1,207 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define AINBG_REG ACSR +#define ACD_REG ACSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TIFR */ +#define TOV0_REG TIFR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 + +#define CLOCK_PORT PORTB +#define CLOCK_BIT 3 + + + diff --git a/include/aversive/parts/ATtiny13.h b/include/aversive/parts/ATtiny13.h new file mode 100644 index 0000000..0c1eaeb --- /dev/null +++ b/include/aversive/parts/ATtiny13.h @@ -0,0 +1,360 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDTIE_REG WDTCR +#define WDTIF_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* GTCCR */ +#define PSR10_REG GTCCR +#define TSM_REG GTCCR + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCR0A_0_REG OCR0A +#define OCR0A_1_REG OCR0A +#define OCR0A_2_REG OCR0A +#define OCR0A_3_REG OCR0A +#define OCR0A_4_REG OCR0A +#define OCR0A_5_REG OCR0A +#define OCR0A_6_REG OCR0A +#define OCR0A_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK +#define PCINT4_REG PCMSK +#define PCINT5_REG PCMSK + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* DIDR0 */ +#define ADC1D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC0D_REG DIDR0 +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 +#define AIN0_PORT PORTB +#define AIN0_BIT 0 +#define OC0A_PORT PORTB +#define OC0A_BIT 0 +#define TXD_PORT PORTB +#define TXD_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 +#define OC0B_PORT PORTB +#define OC0B_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 +#define RXD_PORT PORTB +#define RXD_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define ADC1_PORT PORTB +#define ADC1_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + + diff --git a/include/aversive/parts/ATtiny13A.h b/include/aversive/parts/ATtiny13A.h new file mode 100644 index 0000000..076baae --- /dev/null +++ b/include/aversive/parts/ATtiny13A.h @@ -0,0 +1,368 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDTIE_REG WDTCR +#define WDTIF_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* GTCCR */ +#define PSR10_REG GTCCR +#define TSM_REG GTCCR + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* OCR0A */ +#define OCR0A_0_REG OCR0A +#define OCR0A_1_REG OCR0A +#define OCR0A_2_REG OCR0A +#define OCR0A_3_REG OCR0A +#define OCR0A_4_REG OCR0A +#define OCR0A_5_REG OCR0A +#define OCR0A_6_REG OCR0A +#define OCR0A_7_REG OCR0A + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRTIM0_REG PRR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK +#define PCINT4_REG PCMSK +#define PCINT5_REG PCMSK + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB + +/* BODCR */ +#define BPDSE_REG BODCR +#define BPDS_REG BODCR + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* DIDR0 */ +#define ADC1D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC0D_REG DIDR0 +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 +#define AIN0_PORT PORTB +#define AIN0_BIT 0 +#define OC0A_PORT PORTB +#define OC0A_BIT 0 +#define TXD_PORT PORTB +#define TXD_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 +#define OC0B_PORT PORTB +#define OC0B_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 +#define RXD_PORT PORTB +#define RXD_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define ADC1_PORT PORTB +#define ADC1_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + + diff --git a/include/aversive/parts/ATtiny15.h b/include/aversive/parts/ATtiny15.h new file mode 100644 index 0000000..43acbd6 --- /dev/null +++ b/include/aversive/parts/ATtiny15.h @@ -0,0 +1,351 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_-3 1 +#define TIMER1_PRESCALER_DIV_-3 2 +#define TIMER1_PRESCALER_DIV_-3 3 +#define TIMER1_PRESCALER_DIV_-3 4 +#define TIMER1_PRESCALER_DIV_1 5 +#define TIMER1_PRESCALER_DIV_2 6 +#define TIMER1_PRESCALER_DIV_4 7 +#define TIMER1_PRESCALER_DIV_8 8 +#define TIMER1_PRESCALER_DIV_16 9 +#define TIMER1_PRESCALER_DIV_32 10 +#define TIMER1_PRESCALER_DIV_64 11 +#define TIMER1_PRESCALER_DIV_128 12 +#define TIMER1_PRESCALER_DIV_256 13 +#define TIMER1_PRESCALER_DIV_512 14 +#define TIMER1_PRESCALER_DIV_1024 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 -3 +#define TIMER1_PRESCALER_REG_2 -3 +#define TIMER1_PRESCALER_REG_3 -3 +#define TIMER1_PRESCALER_REG_4 -3 +#define TIMER1_PRESCALER_REG_5 1 +#define TIMER1_PRESCALER_REG_6 2 +#define TIMER1_PRESCALER_REG_7 4 +#define TIMER1_PRESCALER_REG_8 8 +#define TIMER1_PRESCALER_REG_9 16 +#define TIMER1_PRESCALER_REG_10 32 +#define TIMER1_PRESCALER_REG_11 64 +#define TIMER1_PRESCALER_REG_12 128 +#define TIMER1_PRESCALER_REG_13 256 +#define TIMER1_PRESCALER_REG_14 512 +#define TIMER1_PRESCALER_REG_15 1024 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE1_NUM 0 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1 + +/* Pwm nums */ +#define PWM1_NUM 0 +#define PWM_TOTAL_NUM 1 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR1 */ +#define CS10_REG TCCR1 +#define CS11_REG TCCR1 +#define CS12_REG TCCR1 +#define CS13_REG TCCR1 +#define COM1A0_REG TCCR1 +#define COM1A1_REG TCCR1 +#define PWM1_REG TCCR1 +#define CTC1_REG TCCR1 + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1A_REG TIMSK + +/* SFIOR */ +#define PSR0_REG SFIOR +#define PSR1_REG SFIOR +#define FOC1A_REG SFIOR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* TCNT1 */ +#define TCNT1_0_REG TCNT1 +#define TCNT1_1_REG TCNT1 +#define TCNT1_2_REG TCNT1 +#define TCNT1_3_REG TCNT1 +#define TCNT1_4_REG TCNT1 +#define TCNT1_5_REG TCNT1 +#define TCNT1_6_REG TCNT1 +#define TCNT1_7_REG TCNT1 + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1A_REG TIFR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 +#define AIN0_PORT PORTB +#define AIN0_BIT 0 +#define AREF_PORT PORTB +#define AREF_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 +#define OCP_PORT PORTB +#define OCP_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define ADC1_PORT PORTB +#define ADC1_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 + +#define ADC2_PORT PORTB +#define ADC2_BIT 3 + +#define ADC3_PORT PORTB +#define ADC3_BIT 4 + +#define RESET_PORT PORTB +#define RESET_BIT 5 +#define ADC0_PORT PORTB +#define ADC0_BIT 5 + + diff --git a/include/aversive/parts/ATtiny167.h b/include/aversive/parts/ATtiny167.h new file mode 100644 index 0000000..c8a7266 --- /dev/null +++ b/include/aversive/parts/ATtiny167.h @@ -0,0 +1,797 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_32 3 +#define TIMER0_PRESCALER_DIV_64 4 +#define TIMER0_PRESCALER_DIV_128 5 +#define TIMER0_PRESCALER_DIV_256 6 +#define TIMER0_PRESCALER_DIV_1024 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 32 +#define TIMER0_PRESCALER_REG_4 64 +#define TIMER0_PRESCALER_REG_5 128 +#define TIMER0_PRESCALER_REG_6 256 +#define TIMER0_PRESCALER_REG_7 1024 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE1A_NUM 1 +#define SIG_OUTPUT_COMPARE1B_NUM 2 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM1A_NUM 1 +#define PWM1B_NUM 2 +#define PWM_TOTAL_NUM 3 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* LINIDR */ +#define LID0_REG LINIDR +#define LID1_REG LINIDR +#define LID2_REG LINIDR +#define LID3_REG LINIDR +#define LID4_REG LINIDR +#define LID5_REG LINIDR +#define LP0_REG LINIDR +#define LP1_REG LINIDR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR + +/* LINBTR */ +#define LBT0_REG LINBTR +#define LBT1_REG LINBTR +#define LBT2_REG LINBTR +#define LBT3_REG LINBTR +#define LBT4_REG LINBTR +#define LBT5_REG LINBTR +#define LDISR_REG LINBTR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* PORTCR */ +#define PUDA_REG PORTCR +#define PUDB_REG PORTCR +#define BBMA_REG PORTCR +#define BBMB_REG PORTCR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* AMISCR */ +#define XREFEN_REG AMISCR +#define AREFEN_REG AMISCR +#define ISRCEN_REG AMISCR + +/* CLKSELR */ +#define CSEL0_REG CLKSELR +#define CSEL1_REG CLKSELR +#define CSEL2_REG CLKSELR +#define CSEL3_REG CLKSELR +#define CSUT0_REG CLKSELR +#define CSUT1_REG CLKSELR +#define COUT_REG CLKSELR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TCCR1D */ +#define OC1AU_REG TCCR1D +#define OC1AV_REG TCCR1D +#define OC1AW_REG TCCR1D +#define OC1AX_REG TCCR1D +#define OC1BU_REG TCCR1D +#define OC1BV_REG TCCR1D +#define OC1BW_REG TCCR1D +#define OC1BX_REG TCCR1D + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* LINSEL */ +#define LINDX0_REG LINSEL +#define LINDX1_REG LINSEL +#define LINDX2_REG LINSEL +#define LAINC_REG LINSEL + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* LINCR */ +#define LCMD0_REG LINCR +#define LCMD1_REG LINCR +#define LCMD2_REG LINCR +#define LENA_REG LINCR +#define LCONF0_REG LINCR +#define LCONF1_REG LINCR +#define LIN13_REG LINCR +#define LSWRES_REG LINCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* GTCCR */ +#define PSR1_REG GTCCR +#define PSR0_REG GTCCR +#define TSM_REG GTCCR + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define BIN_REG ADCSRB +#define ACIR0_REG ADCSRB +#define ACIR1_REG ADCSRB +#define ACME_REG ADCSRB + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OCR0A */ +#define OCR00_REG OCR0A +#define OCR01_REG OCR0A +#define OCR02_REG OCR0A +#define OCR03_REG OCR0A +#define OCR04_REG OCR0A +#define OCR05_REG OCR0A +#define OCR06_REG OCR0A +#define OCR07_REG OCR0A + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACIRS_REG ACSR +#define ACD_REG ACSR + +/* USIPP */ +#define USIPOS_REG USIPP + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR +#define PRSPI_REG PRR +#define PRLIN_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR +#define SIGRD_REG SPMCSR +#define RWWSB_REG SPMCSR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* LINBRRL */ +#define LDIV0_REG LINBRRL +#define LDIV1_REG LINBRRL +#define LDIV2_REG LINBRRL +#define LDIV3_REG LINBRRL +#define LDIV4_REG LINBRRL +#define LDIV5_REG LINBRRL +#define LDIV6_REG LINBRRL +#define LDIV7_REG LINBRRL + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR + +/* LINBRRH */ +#define LDIV8_REG LINBRRH +#define LDIV9_REG LINBRRH +#define LDIV10_REG LINBRRH +#define LDIV11_REG LINBRRH + +/* LINDAT */ +#define LDATA0_REG LINDAT +#define LDATA1_REG LINDAT +#define LDATA2_REG LINDAT +#define LDATA3_REG LINDAT +#define LDATA4_REG LINDAT +#define LDATA5_REG LINDAT +#define LDATA6_REG LINDAT +#define LDATA7_REG LINDAT + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* LINENIR */ +#define LENRXOK_REG LINENIR +#define LENTXOK_REG LINENIR +#define LENIDOK_REG LINENIR +#define LENERR_REG LINENIR + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* LINERR */ +#define LBERR_REG LINERR +#define LCERR_REG LINERR +#define LPERR_REG LINERR +#define LSERR_REG LINERR +#define LFERR_REG LINERR +#define LOVERR_REG LINERR +#define LTOERR_REG LINERR +#define LABORT_REG LINERR + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* LINDLR */ +#define LRXDL0_REG LINDLR +#define LRXDL1_REG LINDLR +#define LRXDL2_REG LINDLR +#define LRXDL3_REG LINDLR +#define LTXDL0_REG LINDLR +#define LTXDL1_REG LINDLR +#define LTXDL2_REG LINDLR +#define LTXDL3_REG LINDLR + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* LINSIR */ +#define LRXOK_REG LINSIR +#define LTXOK_REG LINSIR +#define LIDOK_REG LINSIR +#define LERR_REG LINSIR +#define LBUSY_REG LINSIR +#define LIDST0_REG LINSIR +#define LIDST1_REG LINSIR +#define LIDST2_REG LINSIR + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 + +/* CLKCSR */ +#define CLKC0_REG CLKCSR +#define CLKC1_REG CLKCSR +#define CLKC2_REG CLKCSR +#define CLKC3_REG CLKCSR +#define CLKRDY_REG CLKCSR +#define CLKCCE_REG CLKCSR + +/* MCUCR */ +#define PUD_REG MCUCR +#define BODS_REG MCUCR +#define BODSE_REG MCUCR + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* ASSR */ +#define TCR0BUB_REG ASSR +#define TCR0AUB_REG ASSR +#define OCR0AUB_REG ASSR +#define TCN0UB_REG ASSR +#define AS0_REG ASSR +#define EXCLK_REG ASSR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny22.h b/include/aversive/parts/ATtiny22.h new file mode 100644 index 0000000..ff39c90 --- /dev/null +++ b/include/aversive/parts/ATtiny22.h @@ -0,0 +1,186 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* TIMSK */ +#define TOIE0_REG TIMSK + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR +#define EEAR7_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM_REG MCUCR +#define SE_REG MCUCR + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TIFR */ +#define TOV0_REG TIFR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define INT0_PORT PORTB +#define INT0_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 + +#define CLOCK_PORT PORTB +#define CLOCK_BIT 3 + + + diff --git a/include/aversive/parts/ATtiny2313.h b/include/aversive/parts/ATtiny2313.h new file mode 100644 index 0000000..b7a1507 --- /dev/null +++ b/include/aversive/parts/ATtiny2313.h @@ -0,0 +1,641 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* DIDR */ +#define AIN0D_REG DIDR +#define AIN1D_REG DIDR + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* GTCCR */ +#define PSR10_REG GTCCR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* TIMSK */ +#define OCIE0A_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define ICIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define TOIE1_REG TIMSK + +/* UCSRA */ +#define MPCM_REG UCSRA +#define U2X_REG UCSRA +#define UPE_REG UCSRA +#define DOR_REG UCSRA +#define FE_REG UCSRA +#define UDRE_REG UCSRA +#define TXC_REG UCSRA +#define RXC_REG UCSRA + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* UCSRB */ +#define TXB8_REG UCSRB +#define RXB8_REG UCSRB +#define UCSZ2_REG UCSRB +#define TXEN_REG UCSRB +#define RXEN_REG UCSRB +#define UDRIE_REG UCSRB +#define TXCIE_REG UCSRB +#define RXCIE_REG UCSRB + +/* UCSRC */ +#define UCPOL_REG UCSRC +#define UCSZ0_REG UCSRC +#define UCSZ1_REG UCSRC +#define USBS_REG UCSRC +#define UPM0_REG UCSRC +#define UPM1_REG UCSRC +#define UMSEL_REG UCSRC + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* UBRRH */ +#define UBRR8_REG UBRRH +#define UBRR9_REG UBRRH +#define UBRR10_REG UBRRH +#define UBRR11_REG UBRRH + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* UBRRL */ +#define UBRR0_REG UBRRL +#define UBRR1_REG UBRRL +#define UBRR2_REG UBRRL +#define UBRR3_REG UBRRL +#define UBRR4_REG UBRRL +#define UBRR5_REG UBRRL +#define UBRR6_REG UBRRL +#define UBRR7_REG UBRRL + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK +#define PCINT4_REG PCMSK +#define PCINT5_REG PCMSK +#define PCINT6_REG PCMSK +#define PCINT7_REG PCMSK + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TIFR */ +#define OCF0A_REG TIFR +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define ICF1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define TOV1_REG TIFR + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* UDR */ +#define UDR0_REG UDR +#define UDR1_REG UDR +#define UDR2_REG UDR +#define UDR3_REG UDR +#define UDR4_REG UDR +#define UDR5_REG UDR +#define UDR6_REG UDR +#define UDR7_REG UDR + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* EIFR */ +#define PCIF_REG EIFR +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define ISC10_REG MCUCR +#define ISC11_REG MCUCR +#define SM0_REG MCUCR +#define SE_REG MCUCR +#define SM1_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ +#define AIN0_PORT PORTB +#define AIN0_BIT 0 + +#define AIN1_PORT PORTB +#define AIN1_BIT 1 + +#define OC0A_PORT PORTB +#define OC0A_BIT 2 + +#define OC1A_PORT PORTB +#define OC1A_BIT 3 + +#define OC1B_PORT PORTB +#define OC1B_BIT 4 + +#define MOSI_PORT PORTB +#define MOSI_BIT 5 +#define DI_PORT PORTB +#define DI_BIT 5 + +#define MISO_PORT PORTB +#define MISO_BIT 6 +#define DO_PORT PORTB +#define DO_BIT 6 + +#define SCK_PORT PORTB +#define SCK_BIT 7 +#define SCL_PORT PORTB +#define SCL_BIT 7 + +#define RXD_PORT PORTD +#define RXD_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define XCK_PORT PORTD +#define XCK_BIT 2 +#define CKOUT_PORT PORTD +#define CKOUT_BIT 2 + +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define T0_PORT PORTD +#define T0_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 + +#define ICP_PORT PORTD +#define ICP_BIT 6 + + diff --git a/include/aversive/parts/ATtiny24.h b/include/aversive/parts/ATtiny24.h new file mode 100644 index 0000000..2614cfa --- /dev/null +++ b/include/aversive/parts/ATtiny24.h @@ -0,0 +1,670 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define MUX5_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* GTCCR */ +#define PSR10_REG GTCCR +#define TSM_REG GTCCR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define PCIF0_REG GIFR +#define PCIF1_REG GIFR +#define INTF0_REG GIFR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADLAR_REG ADCSRB +#define BIN_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define AREF_PORT PORTA +#define AREF_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define AIN0_PORT PORTA +#define AIN0_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define AIN1_PORT PORTA +#define AIN1_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define T0_PORT PORTA +#define T0_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define USCK_PORT PORTA +#define USCK_BIT 4 +#define SCL_PORT PORTA +#define SCL_BIT 4 +#define T1_PORT PORTA +#define T1_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define DO_PORT PORTA +#define DO_BIT 5 +#define MISO_PORT PORTA +#define MISO_BIT 5 +#define OC1B_PORT PORTA +#define OC1B_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 +#define OC1A_PORT PORTA +#define OC1A_BIT 6 +#define DI_PORT PORTA +#define DI_BIT 6 +#define SDA_PORT PORTA +#define SDA_BIT 6 +#define MOSI_PORT PORTA +#define MOSI_BIT 6 +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 +#define ICP1_PORT PORTA +#define ICP1_BIT 7 +#define OC0B_PORT PORTA +#define OC0B_BIT 7 +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define PCINT8_PORT PORTB +#define PCINT8_BIT 0 +#define XTAL1_PORT PORTB +#define XTAL1_BIT 0 + +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 +#define XTAL2_PORT PORTB +#define XTAL2_BIT 1 + +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 +#define OC0A_PORT PORTB +#define OC0A_BIT 2 +#define CKOUT_PORT PORTB +#define CKOUT_BIT 2 + +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 +#define RESET_PORT PORTB +#define RESET_BIT 3 +#define dW_PORT PORTB +#define dW_BIT 3 + + diff --git a/include/aversive/parts/ATtiny25.h b/include/aversive/parts/ATtiny25.h new file mode 100644 index 0000000..b838579 --- /dev/null +++ b/include/aversive/parts/ATtiny25.h @@ -0,0 +1,628 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* DIDR0 */ +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC0D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define REFS2_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR1 */ +#define CS10_REG TCCR1 +#define CS11_REG TCCR1 +#define CS12_REG TCCR1 +#define CS13_REG TCCR1 +#define COM1A0_REG TCCR1 +#define COM1A1_REG TCCR1 +#define PWM1A_REG TCCR1 +#define CTC1_REG TCCR1 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* GTCCR */ +#define PSR0_REG GTCCR +#define TSM_REG GTCCR +#define PSR1_REG GTCCR +#define FOC1A_REG GTCCR +#define FOC1B_REG GTCCR +#define COM1B0_REG GTCCR +#define COM1B1_REG GTCCR +#define PWM1B_REG GTCCR + +/* DTPS */ +#define DTPS0_REG DTPS +#define DTPS1_REG DTPS + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define OCIE0A_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* DT1B */ +/* #define DTVL0_REG DT1B */ /* dup in DT1A */ +/* #define DTVL1_REG DT1B */ /* dup in DT1A */ +/* #define DTVL2_REG DT1B */ /* dup in DT1A */ +/* #define DTVL3_REG DT1B */ /* dup in DT1A */ +/* #define DTVH0_REG DT1B */ /* dup in DT1A */ +/* #define DTVH1_REG DT1B */ /* dup in DT1A */ +/* #define DTVH2_REG DT1B */ /* dup in DT1A */ +/* #define DTVH3_REG DT1B */ /* dup in DT1A */ + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK +#define PCINT4_REG PCMSK +#define PCINT5_REG PCMSK + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCNT1 */ +#define TCNT1_0_REG TCNT1 +#define TCNT1_1_REG TCNT1 +#define TCNT1_2_REG TCNT1 +#define TCNT1_3_REG TCNT1 +#define TCNT1_4_REG TCNT1 +#define TCNT1_5_REG TCNT1 +#define TCNT1_6_REG TCNT1 +#define TCNT1_7_REG TCNT1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define OCF0A_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR +#define LSM_REG PLLCSR + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define IPR_REG ADCSRB +#define BIN_REG ADCSRB + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +#define OCR1C7_REG OCR1C + +/* DT1A */ +/* #define DTVL0_REG DT1A */ /* dup in DT1B */ +/* #define DTVL1_REG DT1A */ /* dup in DT1B */ +/* #define DTVL2_REG DT1A */ /* dup in DT1B */ +/* #define DTVL3_REG DT1A */ /* dup in DT1B */ +/* #define DTVH0_REG DT1A */ /* dup in DT1B */ +/* #define DTVH1_REG DT1A */ /* dup in DT1B */ +/* #define DTVH2_REG DT1A */ /* dup in DT1B */ +/* #define DTVH3_REG DT1A */ /* dup in DT1B */ + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 +#define DI_PORT PORTB +#define DI_BIT 0 +#define SDA_PORT PORTB +#define SDA_BIT 0 +#define AIN0_PORT PORTB +#define AIN0_BIT 0 +#define OC0A_PORT PORTB +#define OC0A_BIT 0 +#define OC1A_PORT PORTB +#define OC1A_BIT 0 +#define AREF_PORT PORTB +#define AREF_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define DO_PORT PORTB +#define DO_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 +#define OC0B_PORT PORTB +#define OC0B_BIT 1 +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define USCK_PORT PORTB +#define USCK_BIT 2 +#define SCL_PORT PORTB +#define SCL_BIT 2 +#define ADC1_PORT PORTB +#define ADC1_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTB +#define ADC3_BIT 3 +#define OC1B_PORT PORTB +#define OC1B_BIT 3 +#define XTAL1_PORT PORTB +#define XTAL1_BIT 3 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 3 + +#define ADC2_PORT PORTB +#define ADC2_BIT 4 +#define OC1B_PORT PORTB +#define OC1B_BIT 4 +#define XTAL2_PORT PORTB +#define XTAL2_BIT 4 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 4 + +#define RESET_PORT PORTB +#define RESET_BIT 5 +#define ADC0_PORT PORTB +#define ADC0_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 +#define dW_PORT PORTB +#define dW_BIT 5 + + diff --git a/include/aversive/parts/ATtiny26.h b/include/aversive/parts/ATtiny26.h new file mode 100644 index 0000000..18c9890 --- /dev/null +++ b/include/aversive/parts/ATtiny26.h @@ -0,0 +1,418 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER1_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define PSR0_REG TCCR0 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* TCCR1A */ +#define PWM1B_REG TCCR1A +#define PWM1A_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CS13_REG TCCR1B +#define PSR1_REG TCCR1B +#define CTC1_REG TCCR1B + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACME_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEWE_REG EECR +#define EEMWE_REG EECR +#define EERIE_REG EECR + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR +#define EEAR6_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* TCNT1 */ +#define TCNT1_0_REG TCNT1 +#define TCNT1_1_REG TCNT1 +#define TCNT1_2_REG TCNT1 +#define TCNT1_3_REG TCNT1 +#define TCNT1_4_REG TCNT1 +#define TCNT1_5_REG TCNT1 +#define TCNT1_6_REG TCNT1 +#define TCNT1_7_REG TCNT1 + +/* TIFR */ +#define TOV0_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR + +/* ADCSR */ +#define ADPS0_REG ADCSR +#define ADPS1_REG ADCSR +#define ADPS2_REG ADCSR +#define ADIE_REG ADCSR +#define ADIF_REG ADCSR +#define ADFR_REG ADCSR +#define ADSC_REG ADCSR +#define ADEN_REG ADCSR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* SP */ +#define SP0_REG SP +#define SP1_REG SP +#define SP2_REG SP +#define SP3_REG SP +#define SP4_REG SP +#define SP5_REG SP +#define SP6_REG SP +#define SP7_REG SP + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +#define OCR1C7_REG OCR1C + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny261.h b/include/aversive/parts/ATtiny261.h new file mode 100644 index 0000000..deae71d --- /dev/null +++ b/include/aversive/parts/ATtiny261.h @@ -0,0 +1,671 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1_NUM 2 +#define SIG_OUTPUT_COMPARE1A_NUM 3 +#define SIG_OUTPUT_COMPARE1B_NUM 4 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1_NUM 2 +#define PWM1A_NUM 3 +#define PWM1B_NUM 4 +#define PWM_TOTAL_NUM 5 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE0_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define AREFD_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCNT0H */ +/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */ + +/* TCNT0L */ +/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */ + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TCCR1D */ +#define WGM10_REG TCCR1D +#define WGM11_REG TCCR1D +#define FPF1_REG TCCR1D +#define FPAC1_REG TCCR1D +#define FPES1_REG TCCR1D +#define FPNC1_REG TCCR1D +#define FPEN1_REG TCCR1D +#define FPIE1_REG TCCR1D + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* TCCR1A */ +#define PWM1B_REG TCCR1A +#define PWM1A_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define PWM1D_REG TCCR1C +#define FOC1D_REG TCCR1C +#define COM1D0_REG TCCR1C +#define COM1D1_REG TCCR1C +#define COM1B0S_REG TCCR1C +#define COM1B1S_REG TCCR1C +#define COM1A0S_REG TCCR1C +#define COM1A1S_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CS13_REG TCCR1B +#define DTPS10_REG TCCR1B +#define DTPS11_REG TCCR1B +#define PSR1_REG TCCR1B + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TICIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define OCIE0A_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define OCIE1D_REG TIMSK + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ACSRB */ +#define ACM0_REG ACSRB +#define ACM1_REG ACSRB +#define ACM2_REG ACSRB +#define HLEV_REG ACSRB +#define HSEL_REG ACSRB + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB +#define REFS2_REG ADCSRB +#define IPR_REG ADCSRB +#define GSEL_REG ADCSRB +#define BIN_REG ADCSRB + +/* TC1H */ +#define TC18_REG TC1H +#define TC19_REG TC1H + +/* TCCR1E */ +#define OC1OE0_REG TCCR1E +#define OC1OE1_REG TCCR1E +#define OC1OE2_REG TCCR1E +#define OC1OE3_REG TCCR1E +#define OC1OE4_REG TCCR1E +#define OC1OE5_REG TCCR1E + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* USIPP */ +#define USIPOS_REG USIPP + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* ACSRA */ +#define ACIS0_REG ACSRA +#define ACIS1_REG ACSRA +#define ACME_REG ACSRA +#define ACIE_REG ACSRA +#define ACI_REG ACSRA +#define ACO_REG ACSRA +#define ACBG_REG ACSRA +#define ACD_REG ACSRA + +/* TCNT1 */ +#define TC1H_0_REG TCNT1 +#define TC1H_1_REG TCNT1 +#define TC1H_2_REG TCNT1 +#define TC1H_3_REG TCNT1 +#define TC1H_4_REG TCNT1 +#define TC1H_5_REG TCNT1 +#define TC1H_6_REG TCNT1 +#define TC1H_7_REG TCNT1 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define PSR0_REG TCCR0B +#define TSM_REG TCCR0B + +/* TIFR */ +#define ICF0_REG TIFR +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define OCF0A_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define OCF1D_REG TIFR + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define ACIC0_REG TCCR0A +#define ICES0_REG TCCR0A +#define ICNC0_REG TCCR0A +#define ICEN0_REG TCCR0A +#define TCW0_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR +#define LSM_REG PLLCSR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* OCR1D */ +#define OCR1D0_REG OCR1D +#define OCR1D1_REG OCR1D +#define OCR1D2_REG OCR1D +#define OCR1D3_REG OCR1D +#define OCR1D4_REG OCR1D +#define OCR1D5_REG OCR1D +#define OCR1D6_REG OCR1D +/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */ + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */ + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* DT1 */ +#define DT1L0_REG DT1 +#define DT1L1_REG DT1 +#define DT1L2_REG DT1 +#define DT1L3_REG DT1 +#define DT1H0_REG DT1 +#define DT1H1_REG DT1 +#define DT1H2_REG DT1 +#define DT1H3_REG DT1 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* DIDR1 */ +#define ADC7D_REG DIDR1 +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny28.h b/include/aversive/parts/ATtiny28.h new file mode 100644 index 0000000..744bb72 --- /dev/null +++ b/include/aversive/parts/ATtiny28.h @@ -0,0 +1,225 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_-3 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 -3 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW_TOTAL_NUM 1 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACD_REG ACSR + +/* PACR */ +#define DDA0_REG PACR +#define DDA1_REG PACR +#define PA2HC_REG PACR +#define DDA3_REG PACR + +/* MODCR */ +#define MCONF0_REG MODCR +#define MCONF1_REG MODCR +#define MCONF2_REG MODCR +#define ONTIM0_REG MODCR +#define ONTIM1_REG MODCR +#define ONTIM2_REG MODCR +#define OTIM3_REG MODCR +#define ONTIM4_REG MODCR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA3_REG PINA + +/* TCCR0 */ +#define CS00_REG TCCR0 +#define CS01_REG TCCR0 +#define CS02_REG TCCR0 +#define OOM00_REG TCCR0 +#define OOM01_REG TCCR0 +#define FOV0_REG TCCR0 + +/* MCUCS */ +#define PORF_REG MCUCS +#define EXTRF_REG MCUCS +#define WDRF_REG MCUCS +#define SM_REG MCUCS +#define SE_REG MCUCS +#define PLUPB_REG MCUCS + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA + +/* TCNT0 */ +#define TCNT00_REG TCNT0 +#define TCNT01_REG TCNT0 +#define TCNT02_REG TCNT0 +#define TCNT03_REG TCNT0 +#define TCNT04_REG TCNT0 +#define TCNT05_REG TCNT0 +#define TCNT06_REG TCNT0 +#define TCNT07_REG TCNT0 + +/* IFR */ +#define TOV0_REG IFR +#define INTF0_REG IFR +#define INTF1_REG IFR + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* ICR */ +#define ISC00_REG ICR +#define ISC01_REG ICR +#define ICS10_REG ICR +#define ICS11_REG ICR +#define TOIE0_REG ICR +#define LLIE_REG ICR +#define INT0_REG ICR +#define INT1_REG ICR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDTOE_REG WDTCR + +/* pins mapping */ + + +#define IR_PORT PORTA +#define IR_BIT 2 + + + + + + + + + + + + + + diff --git a/include/aversive/parts/ATtiny43U.h b/include/aversive/parts/ATtiny43U.h new file mode 100644 index 0000000..9bb6c69 --- /dev/null +++ b/include/aversive/parts/ATtiny43U.h @@ -0,0 +1,524 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define REFS_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* OCR1A */ +/* #define OCR1_0_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_1_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_2_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_3_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_4_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_5_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_6_REG OCR1A */ /* dup in OCR1B */ +/* #define OCR1_7_REG OCR1A */ /* dup in OCR1B */ + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* GTCCR */ +#define PSR10_REG GTCCR +#define TSM_REG GTCCR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define FOC1B_REG TCCR1B +#define FOC1A_REG TCCR1B + +/* GIFR */ +#define PCIF0_REG GIFR +#define PCIF1_REG GIFR +#define INTF0_REG GIFR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADLAR_REG ADCSRB +#define BVRON_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* EEAR */ +#define EEAR0_REG EEAR +#define EEAR1_REG EEAR +#define EEAR2_REG EEAR +#define EEAR3_REG EEAR +#define EEAR4_REG EEAR +#define EEAR5_REG EEAR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCNT1 */ +#define TCNT1_0_REG TCNT1 +#define TCNT1_1_REG TCNT1 +#define TCNT1_2_REG TCNT1 +#define TCNT1_3_REG TCNT1 +#define TCNT1_4_REG TCNT1 +#define TCNT1_5_REG TCNT1 +#define TCNT1_6_REG TCNT1 +#define TCNT1_7_REG TCNT1 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* OCR1B */ +/* #define OCR1_0_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_1_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_2_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_3_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_4_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_5_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_6_REG OCR1B */ /* dup in OCR1A */ +/* #define OCR1_7_REG OCR1B */ /* dup in OCR1A */ + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define BODSE_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR +#define BODS_REG MCUCR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny44.h b/include/aversive/parts/ATtiny44.h new file mode 100644 index 0000000..2d70d72 --- /dev/null +++ b/include/aversive/parts/ATtiny44.h @@ -0,0 +1,673 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define MUX5_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* GTCCR */ +#define PSR10_REG GTCCR +#define TSM_REG GTCCR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define PCIF0_REG GIFR +#define PCIF1_REG GIFR +#define INTF0_REG GIFR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADLAR_REG ADCSRB +#define BIN_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define AREF_PORT PORTA +#define AREF_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define AIN0_PORT PORTA +#define AIN0_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define AIN1_PORT PORTA +#define AIN1_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define T0_PORT PORTA +#define T0_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define USCK_PORT PORTA +#define USCK_BIT 4 +#define SCL_PORT PORTA +#define SCL_BIT 4 +#define T1_PORT PORTA +#define T1_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define DO_PORT PORTA +#define DO_BIT 5 +#define MISO_PORT PORTA +#define MISO_BIT 5 +#define OC1B_PORT PORTA +#define OC1B_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 +#define OC1A_PORT PORTA +#define OC1A_BIT 6 +#define DI_PORT PORTA +#define DI_BIT 6 +#define SDA_PORT PORTA +#define SDA_BIT 6 +#define MOSI_PORT PORTA +#define MOSI_BIT 6 +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 +#define ICP1_PORT PORTA +#define ICP1_BIT 7 +#define OC0B_PORT PORTA +#define OC0B_BIT 7 +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define PCINT8_PORT PORTB +#define PCINT8_BIT 0 +#define XTAL1_PORT PORTB +#define XTAL1_BIT 0 + +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 +#define XTAL2_PORT PORTB +#define XTAL2_BIT 1 + +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 +#define OC0A_PORT PORTB +#define OC0A_BIT 2 +#define CKOUT_PORT PORTB +#define CKOUT_BIT 2 + +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 +#define RESET_PORT PORTB +#define RESET_BIT 3 +#define dW_PORT PORTB +#define dW_BIT 3 + + diff --git a/include/aversive/parts/ATtiny45.h b/include/aversive/parts/ATtiny45.h new file mode 100644 index 0000000..fdc13ec --- /dev/null +++ b/include/aversive/parts/ATtiny45.h @@ -0,0 +1,634 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* DIDR0 */ +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC0D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define REFS2_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR1 */ +#define CS10_REG TCCR1 +#define CS11_REG TCCR1 +#define CS12_REG TCCR1 +#define CS13_REG TCCR1 +#define COM1A0_REG TCCR1 +#define COM1A1_REG TCCR1 +#define PWM1A_REG TCCR1 +#define CTC1_REG TCCR1 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define BODSE_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR +#define BODS_REG MCUCR + +/* GTCCR */ +#define PSR0_REG GTCCR +#define TSM_REG GTCCR +#define PSR1_REG GTCCR +#define FOC1A_REG GTCCR +#define FOC1B_REG GTCCR +#define COM1B0_REG GTCCR +#define COM1B1_REG GTCCR +#define PWM1B_REG GTCCR + +/* DTPS */ +#define DTPS0_REG DTPS +#define DTPS1_REG DTPS + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define OCIE0A_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* DT1B */ +/* #define DTVL0_REG DT1B */ /* dup in DT1A */ +/* #define DTVL1_REG DT1B */ /* dup in DT1A */ +/* #define DTVL2_REG DT1B */ /* dup in DT1A */ +/* #define DTVL3_REG DT1B */ /* dup in DT1A */ +/* #define DTVH0_REG DT1B */ /* dup in DT1A */ +/* #define DTVH1_REG DT1B */ /* dup in DT1A */ +/* #define DTVH2_REG DT1B */ /* dup in DT1A */ +/* #define DTVH3_REG DT1B */ /* dup in DT1A */ + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK +#define PCINT4_REG PCMSK +#define PCINT5_REG PCMSK + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCNT1 */ +#define TCNT1_0_REG TCNT1 +#define TCNT1_1_REG TCNT1 +#define TCNT1_2_REG TCNT1 +#define TCNT1_3_REG TCNT1 +#define TCNT1_4_REG TCNT1 +#define TCNT1_5_REG TCNT1 +#define TCNT1_6_REG TCNT1 +#define TCNT1_7_REG TCNT1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define OCF0A_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR +#define LSM_REG PLLCSR + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define IPR_REG ADCSRB +#define BIN_REG ADCSRB + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +#define OCR1C7_REG OCR1C + +/* DT1A */ +/* #define DTVL0_REG DT1A */ /* dup in DT1B */ +/* #define DTVL1_REG DT1A */ /* dup in DT1B */ +/* #define DTVL2_REG DT1A */ /* dup in DT1B */ +/* #define DTVL3_REG DT1A */ /* dup in DT1B */ +/* #define DTVH0_REG DT1A */ /* dup in DT1B */ +/* #define DTVH1_REG DT1A */ /* dup in DT1B */ +/* #define DTVH2_REG DT1A */ /* dup in DT1B */ +/* #define DTVH3_REG DT1A */ /* dup in DT1B */ + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 +#define DI_PORT PORTB +#define DI_BIT 0 +#define SDA_PORT PORTB +#define SDA_BIT 0 +#define AIN0_PORT PORTB +#define AIN0_BIT 0 +#define OC0A_PORT PORTB +#define OC0A_BIT 0 +#define OC1A_PORT PORTB +#define OC1A_BIT 0 +#define AREF_PORT PORTB +#define AREF_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define DO_PORT PORTB +#define DO_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 +#define OC0B_PORT PORTB +#define OC0B_BIT 1 +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define USCK_PORT PORTB +#define USCK_BIT 2 +#define SCL_PORT PORTB +#define SCL_BIT 2 +#define ADC1_PORT PORTB +#define ADC1_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTB +#define ADC3_BIT 3 +#define OC1B_PORT PORTB +#define OC1B_BIT 3 +#define XTAL1_PORT PORTB +#define XTAL1_BIT 3 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 3 + +#define ADC2_PORT PORTB +#define ADC2_BIT 4 +#define OC1B_PORT PORTB +#define OC1B_BIT 4 +#define XTAL2_PORT PORTB +#define XTAL2_BIT 4 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 4 + +#define RESET_PORT PORTB +#define RESET_BIT 5 +#define ADC0_PORT PORTB +#define ADC0_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 +#define dW_PORT PORTB +#define dW_BIT 5 + + diff --git a/include/aversive/parts/ATtiny461.h b/include/aversive/parts/ATtiny461.h new file mode 100644 index 0000000..6a4465c --- /dev/null +++ b/include/aversive/parts/ATtiny461.h @@ -0,0 +1,674 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1_NUM 2 +#define SIG_OUTPUT_COMPARE1A_NUM 3 +#define SIG_OUTPUT_COMPARE1B_NUM 4 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1_NUM 2 +#define PWM1A_NUM 3 +#define PWM1B_NUM 4 +#define PWM_TOTAL_NUM 5 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE0_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define AREFD_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCNT0H */ +/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */ + +/* TCNT0L */ +/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */ + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TCCR1D */ +#define WGM10_REG TCCR1D +#define WGM11_REG TCCR1D +#define FPF1_REG TCCR1D +#define FPAC1_REG TCCR1D +#define FPES1_REG TCCR1D +#define FPNC1_REG TCCR1D +#define FPEN1_REG TCCR1D +#define FPIE1_REG TCCR1D + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* TCCR1A */ +#define PWM1B_REG TCCR1A +#define PWM1A_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define PWM1D_REG TCCR1C +#define FOC1D_REG TCCR1C +#define COM1D0_REG TCCR1C +#define COM1D1_REG TCCR1C +#define COM1B0S_REG TCCR1C +#define COM1B1S_REG TCCR1C +#define COM1A0S_REG TCCR1C +#define COM1A1S_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CS13_REG TCCR1B +#define DTPS10_REG TCCR1B +#define DTPS11_REG TCCR1B +#define PSR1_REG TCCR1B + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TICIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define OCIE0A_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define OCIE1D_REG TIMSK + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ACSRB */ +#define ACM0_REG ACSRB +#define ACM1_REG ACSRB +#define ACM2_REG ACSRB +#define HLEV_REG ACSRB +#define HSEL_REG ACSRB + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB +#define REFS2_REG ADCSRB +#define IPR_REG ADCSRB +#define GSEL_REG ADCSRB +#define BIN_REG ADCSRB + +/* TC1H */ +#define TC18_REG TC1H +#define TC19_REG TC1H + +/* TCCR1E */ +#define OC1OE0_REG TCCR1E +#define OC1OE1_REG TCCR1E +#define OC1OE2_REG TCCR1E +#define OC1OE3_REG TCCR1E +#define OC1OE4_REG TCCR1E +#define OC1OE5_REG TCCR1E + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* ACSRA */ +#define ACIS0_REG ACSRA +#define ACIS1_REG ACSRA +#define ACME_REG ACSRA +#define ACIE_REG ACSRA +#define ACI_REG ACSRA +#define ACO_REG ACSRA +#define ACBG_REG ACSRA +#define ACD_REG ACSRA + +/* TCNT1 */ +#define TC1H_0_REG TCNT1 +#define TC1H_1_REG TCNT1 +#define TC1H_2_REG TCNT1 +#define TC1H_3_REG TCNT1 +#define TC1H_4_REG TCNT1 +#define TC1H_5_REG TCNT1 +#define TC1H_6_REG TCNT1 +#define TC1H_7_REG TCNT1 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define PSR0_REG TCCR0B +#define TSM_REG TCCR0B + +/* TIFR */ +#define ICF0_REG TIFR +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define OCF0A_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define OCF1D_REG TIFR + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define ACIC0_REG TCCR0A +#define ICES0_REG TCCR0A +#define ICNC0_REG TCCR0A +#define ICEN0_REG TCCR0A +#define TCW0_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR +#define LSM_REG PLLCSR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* OCR1D */ +#define OCR1D0_REG OCR1D +#define OCR1D1_REG OCR1D +#define OCR1D2_REG OCR1D +#define OCR1D3_REG OCR1D +#define OCR1D4_REG OCR1D +#define OCR1D5_REG OCR1D +#define OCR1D6_REG OCR1D +/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */ + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */ + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* USIPP */ +#define USIPOS_REG USIPP + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* DT1 */ +#define DT1L0_REG DT1 +#define DT1L1_REG DT1 +#define DT1L2_REG DT1 +#define DT1L3_REG DT1 +#define DT1H0_REG DT1 +#define DT1H1_REG DT1 +#define DT1H2_REG DT1 +#define DT1H3_REG DT1 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* DIDR1 */ +#define ADC7D_REG DIDR1 +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny48.h b/include/aversive/parts/ATtiny48.h new file mode 100644 index 0000000..f7f662b --- /dev/null +++ b/include/aversive/parts/ATtiny48.h @@ -0,0 +1,873 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SPH */ +#define SP8_REG SPH + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* PORTCR */ +#define PUDA_REG PORTCR +#define PUDB_REG PORTCR +#define PUDC_REG PORTCR +#define PUDD_REG PORTCR +#define BBMA_REG PORTCR +#define BBMB_REG PORTCR +#define BBMC_REG PORTCR +#define BBMD_REG PORTCR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OCR0A */ +#define OCR0A_0_REG OCR0A +#define OCR0A_1_REG OCR0A +#define OCR0A_2_REG OCR0A +#define OCR0A_3_REG OCR0A +#define OCR0A_4_REG OCR0A +#define OCR0A_5_REG OCR0A +#define OCR0A_6_REG OCR0A +#define OCR0A_7_REG OCR0A + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PRR */ +#define PRADC_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTWI_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR +#define RWWSB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TWHSR */ +#define TWIHS_REG TWHSR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define CTC0_REG TCCR0A + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 +#define AREFD_REG DIDR1 + +/* MCUCR */ +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATtiny84.h b/include/aversive/parts/ATtiny84.h new file mode 100644 index 0000000..686d6a7 --- /dev/null +++ b/include/aversive/parts/ATtiny84.h @@ -0,0 +1,674 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define MUX5_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* GTCCR */ +#define PSR10_REG GTCCR +#define TSM_REG GTCCR + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* GIFR */ +#define PCIF0_REG GIFR +#define PCIF1_REG GIFR +#define INTF0_REG GIFR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ADLAR_REG ADCSRB +#define BIN_REG ADCSRB + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* OCR1BL */ +/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */ +/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */ + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* OCR1BH */ +/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */ +/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */ + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* OCR1AH */ +/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */ +/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */ + +/* OCR1AL */ +/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */ +/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */ + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* pins mapping */ +#define ADC0_PORT PORTA +#define ADC0_BIT 0 +#define AREF_PORT PORTA +#define AREF_BIT 0 +#define PCINT0_PORT PORTA +#define PCINT0_BIT 0 + +#define ADC1_PORT PORTA +#define ADC1_BIT 1 +#define AIN0_PORT PORTA +#define AIN0_BIT 1 +#define PCINT1_PORT PORTA +#define PCINT1_BIT 1 + +#define ADC2_PORT PORTA +#define ADC2_BIT 2 +#define AIN1_PORT PORTA +#define AIN1_BIT 2 +#define PCINT2_PORT PORTA +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTA +#define ADC3_BIT 3 +#define T0_PORT PORTA +#define T0_BIT 3 +#define PCINT3_PORT PORTA +#define PCINT3_BIT 3 + +#define ADC4_PORT PORTA +#define ADC4_BIT 4 +#define USCK_PORT PORTA +#define USCK_BIT 4 +#define SCL_PORT PORTA +#define SCL_BIT 4 +#define T1_PORT PORTA +#define T1_BIT 4 +#define PCINT4_PORT PORTA +#define PCINT4_BIT 4 + +#define ADC5_PORT PORTA +#define ADC5_BIT 5 +#define DO_PORT PORTA +#define DO_BIT 5 +#define MISO_PORT PORTA +#define MISO_BIT 5 +#define OC1B_PORT PORTA +#define OC1B_BIT 5 +#define PCINT5_PORT PORTA +#define PCINT5_BIT 5 + +#define PCINT6_PORT PORTA +#define PCINT6_BIT 6 +#define OC1A_PORT PORTA +#define OC1A_BIT 6 +#define DI_PORT PORTA +#define DI_BIT 6 +#define SDA_PORT PORTA +#define SDA_BIT 6 +#define MOSI_PORT PORTA +#define MOSI_BIT 6 +#define ADC6_PORT PORTA +#define ADC6_BIT 6 + +#define PCINT7_PORT PORTA +#define PCINT7_BIT 7 +#define ICP1_PORT PORTA +#define ICP1_BIT 7 +#define OC0B_PORT PORTA +#define OC0B_BIT 7 +#define ADC7_PORT PORTA +#define ADC7_BIT 7 + +#define PCINT8_PORT PORTB +#define PCINT8_BIT 0 +#define XTAL1_PORT PORTB +#define XTAL1_BIT 0 + +#define PCINT9_PORT PORTB +#define PCINT9_BIT 1 +#define XTAL2_PORT PORTB +#define XTAL2_BIT 1 + +#define PCINT10_PORT PORTB +#define PCINT10_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 +#define OC0A_PORT PORTB +#define OC0A_BIT 2 +#define CKOUT_PORT PORTB +#define CKOUT_BIT 2 + +#define PCINT11_PORT PORTB +#define PCINT11_BIT 3 +#define RESET_PORT PORTB +#define RESET_BIT 3 +#define dW_PORT PORTB +#define dW_BIT 3 + + diff --git a/include/aversive/parts/ATtiny85.h b/include/aversive/parts/ATtiny85.h new file mode 100644 index 0000000..82c3eb3 --- /dev/null +++ b/include/aversive/parts/ATtiny85.h @@ -0,0 +1,632 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE_REG GIMSK +#define INT0_REG GIMSK + +/* DIDR0 */ +#define AIN0D_REG DIDR0 +#define AIN1D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC0D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define REFS2_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCCR1 */ +#define CS10_REG TCCR1 +#define CS11_REG TCCR1 +#define CS12_REG TCCR1 +#define CS13_REG TCCR1 +#define COM1A0_REG TCCR1 +#define COM1A1_REG TCCR1 +#define PWM1A_REG TCCR1 +#define CTC1_REG TCCR1 + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* GTCCR */ +#define PSR0_REG GTCCR +#define TSM_REG GTCCR +#define PSR1_REG GTCCR +#define FOC1A_REG GTCCR +#define FOC1B_REG GTCCR +#define COM1B0_REG GTCCR +#define COM1B1_REG GTCCR +#define PWM1B_REG GTCCR + +/* DTPS */ +#define DTPS0_REG DTPS +#define DTPS1_REG DTPS + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR + +/* TIMSK */ +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define OCIE0A_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* DT1B */ +/* #define DTVL0_REG DT1B */ /* dup in DT1A */ +/* #define DTVL1_REG DT1B */ /* dup in DT1A */ +/* #define DTVL2_REG DT1B */ /* dup in DT1A */ +/* #define DTVL3_REG DT1B */ /* dup in DT1A */ +/* #define DTVH0_REG DT1B */ /* dup in DT1A */ +/* #define DTVH1_REG DT1B */ /* dup in DT1A */ +/* #define DTVH2_REG DT1B */ /* dup in DT1A */ +/* #define DTVH3_REG DT1B */ /* dup in DT1A */ + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* PCMSK */ +#define PCINT0_REG PCMSK +#define PCINT1_REG PCMSK +#define PCINT2_REG PCMSK +#define PCINT3_REG PCMSK +#define PCINT4_REG PCMSK +#define PCINT5_REG PCMSK + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* TCNT1 */ +#define TCNT1_0_REG TCNT1 +#define TCNT1_1_REG TCNT1 +#define TCNT1_2_REG TCNT1 +#define TCNT1_3_REG TCNT1 +#define TCNT1_4_REG TCNT1 +#define TCNT1_5_REG TCNT1 +#define TCNT1_6_REG TCNT1 +#define TCNT1_7_REG TCNT1 + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define WGM02_REG TCCR0B +#define FOC0B_REG TCCR0B +#define FOC0A_REG TCCR0B + +/* TIFR */ +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define OCF0A_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define WGM01_REG TCCR0A +#define COM0B0_REG TCCR0A +#define COM0B1_REG TCCR0A +#define COM0A0_REG TCCR0A +#define COM0A1_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR +#define LSM_REG PLLCSR + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* ADCSRB */ +#define ACME_REG ADCSRB +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define IPR_REG ADCSRB +#define BIN_REG ADCSRB + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +#define OCR1C7_REG OCR1C + +/* DT1A */ +/* #define DTVL0_REG DT1A */ /* dup in DT1B */ +/* #define DTVL1_REG DT1A */ /* dup in DT1B */ +/* #define DTVL2_REG DT1A */ /* dup in DT1B */ +/* #define DTVL3_REG DT1A */ /* dup in DT1B */ +/* #define DTVH0_REG DT1A */ /* dup in DT1B */ +/* #define DTVH1_REG DT1A */ /* dup in DT1B */ +/* #define DTVH2_REG DT1A */ /* dup in DT1B */ +/* #define DTVH3_REG DT1A */ /* dup in DT1B */ + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* pins mapping */ +#define MOSI_PORT PORTB +#define MOSI_BIT 0 +#define DI_PORT PORTB +#define DI_BIT 0 +#define SDA_PORT PORTB +#define SDA_BIT 0 +#define AIN0_PORT PORTB +#define AIN0_BIT 0 +#define OC0A_PORT PORTB +#define OC0A_BIT 0 +#define OC1A_PORT PORTB +#define OC1A_BIT 0 +#define AREF_PORT PORTB +#define AREF_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define MISO_PORT PORTB +#define MISO_BIT 1 +#define DO_PORT PORTB +#define DO_BIT 1 +#define AIN1_PORT PORTB +#define AIN1_BIT 1 +#define OC0B_PORT PORTB +#define OC0B_BIT 1 +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SCK_PORT PORTB +#define SCK_BIT 2 +#define USCK_PORT PORTB +#define USCK_BIT 2 +#define SCL_PORT PORTB +#define SCL_BIT 2 +#define ADC1_PORT PORTB +#define ADC1_BIT 2 +#define T0_PORT PORTB +#define T0_BIT 2 +#define INT0_PORT PORTB +#define INT0_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define ADC3_PORT PORTB +#define ADC3_BIT 3 +#define OC1B_PORT PORTB +#define OC1B_BIT 3 +#define XTAL1_PORT PORTB +#define XTAL1_BIT 3 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 3 + +#define ADC2_PORT PORTB +#define ADC2_BIT 4 +#define OC1B_PORT PORTB +#define OC1B_BIT 4 +#define XTAL2_PORT PORTB +#define XTAL2_BIT 4 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 4 + +#define RESET_PORT PORTB +#define RESET_BIT 5 +#define ADC0_PORT PORTB +#define ADC0_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 +#define dW_PORT PORTB +#define dW_BIT 5 + + diff --git a/include/aversive/parts/ATtiny861.h b/include/aversive/parts/ATtiny861.h new file mode 100644 index 0000000..a75363d --- /dev/null +++ b/include/aversive/parts/ATtiny861.h @@ -0,0 +1,675 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_2 2 +#define TIMER1_PRESCALER_DIV_4 3 +#define TIMER1_PRESCALER_DIV_8 4 +#define TIMER1_PRESCALER_DIV_16 5 +#define TIMER1_PRESCALER_DIV_32 6 +#define TIMER1_PRESCALER_DIV_64 7 +#define TIMER1_PRESCALER_DIV_128 8 +#define TIMER1_PRESCALER_DIV_256 9 +#define TIMER1_PRESCALER_DIV_512 10 +#define TIMER1_PRESCALER_DIV_1024 11 +#define TIMER1_PRESCALER_DIV_2048 12 +#define TIMER1_PRESCALER_DIV_4096 13 +#define TIMER1_PRESCALER_DIV_8192 14 +#define TIMER1_PRESCALER_DIV_16384 15 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 2 +#define TIMER1_PRESCALER_REG_3 4 +#define TIMER1_PRESCALER_REG_4 8 +#define TIMER1_PRESCALER_REG_5 16 +#define TIMER1_PRESCALER_REG_6 32 +#define TIMER1_PRESCALER_REG_7 64 +#define TIMER1_PRESCALER_REG_8 128 +#define TIMER1_PRESCALER_REG_9 256 +#define TIMER1_PRESCALER_REG_10 512 +#define TIMER1_PRESCALER_REG_11 1024 +#define TIMER1_PRESCALER_REG_12 2048 +#define TIMER1_PRESCALER_REG_13 4096 +#define TIMER1_PRESCALER_REG_14 8192 +#define TIMER1_PRESCALER_REG_15 16384 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1_NUM 2 +#define SIG_OUTPUT_COMPARE1A_NUM 3 +#define SIG_OUTPUT_COMPARE1B_NUM 4 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1_NUM 2 +#define PWM1A_NUM 3 +#define PWM1B_NUM 4 +#define PWM_TOTAL_NUM 5 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE0_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* WDTCR */ +#define WDP0_REG WDTCR +#define WDP1_REG WDTCR +#define WDP2_REG WDTCR +#define WDE_REG WDTCR +#define WDCE_REG WDTCR +#define WDP3_REG WDTCR +#define WDIE_REG WDTCR +#define WDIF_REG WDTCR + +/* GIMSK */ +#define PCIE0_REG GIMSK +#define PCIE1_REG GIMSK +#define INT0_REG GIMSK +#define INT1_REG GIMSK + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define AREFD_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define MUX4_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* TCNT0H */ +/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */ +/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */ + +/* TCNT0L */ +/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */ +/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */ + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TCCR1D */ +#define WGM10_REG TCCR1D +#define WGM11_REG TCCR1D +#define FPF1_REG TCCR1D +#define FPAC1_REG TCCR1D +#define FPES1_REG TCCR1D +#define FPNC1_REG TCCR1D +#define FPEN1_REG TCCR1D +#define FPIE1_REG TCCR1D + +/* MCUCR */ +#define ISC00_REG MCUCR +#define ISC01_REG MCUCR +#define SM0_REG MCUCR +#define SM1_REG MCUCR +#define SE_REG MCUCR +#define PUD_REG MCUCR + +/* TCCR1A */ +#define PWM1B_REG TCCR1A +#define PWM1A_REG TCCR1A +#define FOC1B_REG TCCR1A +#define FOC1A_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define PWM1D_REG TCCR1C +#define FOC1D_REG TCCR1C +#define COM1D0_REG TCCR1C +#define COM1D1_REG TCCR1C +#define COM1B0S_REG TCCR1C +#define COM1B1S_REG TCCR1C +#define COM1A0S_REG TCCR1C +#define COM1A1S_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define CS13_REG TCCR1B +#define DTPS10_REG TCCR1B +#define DTPS11_REG TCCR1B +#define PSR1_REG TCCR1B + +/* GIFR */ +#define PCIF_REG GIFR +#define INTF0_REG GIFR +#define INTF1_REG GIFR + +/* TIMSK */ +#define TICIE0_REG TIMSK +#define TOIE0_REG TIMSK +#define OCIE0B_REG TIMSK +#define OCIE0A_REG TIMSK +#define TOIE1_REG TIMSK +#define OCIE1B_REG TIMSK +#define OCIE1A_REG TIMSK +#define OCIE1D_REG TIMSK + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA +#define DDA4_REG DDRA +#define DDA5_REG DDRA +#define DDA6_REG DDRA +#define DDA7_REG DDRA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ACSRB */ +#define ACM0_REG ACSRB +#define ACM1_REG ACSRB +#define ACM2_REG ACSRB +#define HLEV_REG ACSRB +#define HSEL_REG ACSRB + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define MUX5_REG ADCSRB +#define REFS2_REG ADCSRB +#define IPR_REG ADCSRB +#define GSEL_REG ADCSRB +#define BIN_REG ADCSRB + +/* TC1H */ +#define TC18_REG TC1H +#define TC19_REG TC1H + +/* TCCR1E */ +#define OC1OE0_REG TCCR1E +#define OC1OE1_REG TCCR1E +#define OC1OE2_REG TCCR1E +#define OC1OE3_REG TCCR1E +#define OC1OE4_REG TCCR1E +#define OC1OE5_REG TCCR1E + +/* OCR0A */ +/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ +/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ + +/* OCR0B */ +/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ +/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* PRR */ +#define PRADC_REG PRR +#define PRUSI_REG PRR +#define PRTIM0_REG PRR +#define PRTIM1_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* USICR */ +#define USITC_REG USICR +#define USICLK_REG USICR +#define USICS0_REG USICR +#define USICS1_REG USICR +#define USIWM0_REG USICR +#define USIWM1_REG USICR +#define USIOIE_REG USICR +#define USISIE_REG USICR + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SPMEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* USISR */ +#define USICNT0_REG USISR +#define USICNT1_REG USISR +#define USICNT2_REG USISR +#define USICNT3_REG USISR +#define USIDC_REG USISR +#define USIPF_REG USISR +#define USIOIF_REG USISR +#define USISIF_REG USISR + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA +#define PORTA4_REG PORTA +#define PORTA5_REG PORTA +#define PORTA6_REG PORTA +#define PORTA7_REG PORTA + +/* ACSRA */ +#define ACIS0_REG ACSRA +#define ACIS1_REG ACSRA +#define ACME_REG ACSRA +#define ACIE_REG ACSRA +#define ACI_REG ACSRA +#define ACO_REG ACSRA +#define ACBG_REG ACSRA +#define ACD_REG ACSRA + +/* TCNT1 */ +#define TC1H_0_REG TCNT1 +#define TC1H_1_REG TCNT1 +#define TC1H_2_REG TCNT1 +#define TC1H_3_REG TCNT1 +#define TC1H_4_REG TCNT1 +#define TC1H_5_REG TCNT1 +#define TC1H_6_REG TCNT1 +#define TC1H_7_REG TCNT1 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* TCCR0B */ +#define CS00_REG TCCR0B +#define CS01_REG TCCR0B +#define CS02_REG TCCR0B +#define PSR0_REG TCCR0B +#define TSM_REG TCCR0B + +/* TIFR */ +#define ICF0_REG TIFR +#define TOV0_REG TIFR +#define OCF0B_REG TIFR +#define OCF0A_REG TIFR +#define TOV1_REG TIFR +#define OCF1B_REG TIFR +#define OCF1A_REG TIFR +#define OCF1D_REG TIFR + +/* TCCR0A */ +#define WGM00_REG TCCR0A +#define ACIC0_REG TCCR0A +#define ICES0_REG TCCR0A +#define ICNC0_REG TCCR0A +#define ICEN0_REG TCCR0A +#define TCW0_REG TCCR0A + +/* EEARH */ +#define EEAR8_REG EEARH + +/* PLLCSR */ +#define PLOCK_REG PLLCSR +#define PLLE_REG PLLCSR +#define PCKE_REG PLLCSR +#define LSM_REG PLLCSR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* DWDR */ +#define DWDR0_REG DWDR +#define DWDR1_REG DWDR +#define DWDR2_REG DWDR +#define DWDR3_REG DWDR +#define DWDR4_REG DWDR +#define DWDR5_REG DWDR +#define DWDR6_REG DWDR +#define DWDR7_REG DWDR + +/* OCR1D */ +#define OCR1D0_REG OCR1D +#define OCR1D1_REG OCR1D +#define OCR1D2_REG OCR1D +#define OCR1D3_REG OCR1D +#define OCR1D4_REG OCR1D +#define OCR1D5_REG OCR1D +#define OCR1D6_REG OCR1D +/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */ + +/* OCR1B */ +#define OCR1B0_REG OCR1B +#define OCR1B1_REG OCR1B +#define OCR1B2_REG OCR1B +#define OCR1B3_REG OCR1B +#define OCR1B4_REG OCR1B +#define OCR1B5_REG OCR1B +#define OCR1B6_REG OCR1B +#define OCR1B7_REG OCR1B + +/* OCR1C */ +#define OCR1C0_REG OCR1C +#define OCR1C1_REG OCR1C +#define OCR1C2_REG OCR1C +#define OCR1C3_REG OCR1C +#define OCR1C4_REG OCR1C +#define OCR1C5_REG OCR1C +#define OCR1C6_REG OCR1C +/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */ + +/* OCR1A */ +#define OCR1A0_REG OCR1A +#define OCR1A1_REG OCR1A +#define OCR1A2_REG OCR1A +#define OCR1A3_REG OCR1A +#define OCR1A4_REG OCR1A +#define OCR1A5_REG OCR1A +#define OCR1A6_REG OCR1A +#define OCR1A7_REG OCR1A + +/* USIPP */ +#define USIPOS_REG USIPP + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* USIBR */ +#define USIBR0_REG USIBR +#define USIBR1_REG USIBR +#define USIBR2_REG USIBR +#define USIBR3_REG USIBR +#define USIBR4_REG USIBR +#define USIBR5_REG USIBR +#define USIBR6_REG USIBR +#define USIBR7_REG USIBR + +/* DT1 */ +#define DT1L0_REG DT1 +#define DT1L1_REG DT1 +#define DT1L2_REG DT1 +#define DT1L3_REG DT1 +#define DT1H0_REG DT1 +#define DT1H1_REG DT1 +#define DT1H2_REG DT1 +#define DT1H3_REG DT1 + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA +#define PINA4_REG PINA +#define PINA5_REG PINA +#define PINA6_REG PINA +#define PINA7_REG PINA + +/* USIDR */ +#define USIDR0_REG USIDR +#define USIDR1_REG USIDR +#define USIDR2_REG USIDR +#define USIDR3_REG USIDR +#define USIDR4_REG USIDR +#define USIDR5_REG USIDR +#define USIDR6_REG USIDR +#define USIDR7_REG USIDR + +/* DIDR1 */ +#define ADC7D_REG DIDR1 +#define ADC8D_REG DIDR1 +#define ADC9D_REG DIDR1 +#define ADC10D_REG DIDR1 + +/* pins mapping */ + diff --git a/include/aversive/parts/ATtiny88.h b/include/aversive/parts/ATtiny88.h new file mode 100644 index 0000000..6ec6cdb --- /dev/null +++ b/include/aversive/parts/ATtiny88.h @@ -0,0 +1,874 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + +/* prescalers timer 0 */ +#define TIMER0_PRESCALER_DIV_0 0 +#define TIMER0_PRESCALER_DIV_1 1 +#define TIMER0_PRESCALER_DIV_8 2 +#define TIMER0_PRESCALER_DIV_64 3 +#define TIMER0_PRESCALER_DIV_256 4 +#define TIMER0_PRESCALER_DIV_1024 5 +#define TIMER0_PRESCALER_DIV_FALL 6 +#define TIMER0_PRESCALER_DIV_RISE 7 + +#define TIMER0_PRESCALER_REG_0 0 +#define TIMER0_PRESCALER_REG_1 1 +#define TIMER0_PRESCALER_REG_2 8 +#define TIMER0_PRESCALER_REG_3 64 +#define TIMER0_PRESCALER_REG_4 256 +#define TIMER0_PRESCALER_REG_5 1024 +#define TIMER0_PRESCALER_REG_6 -1 +#define TIMER0_PRESCALER_REG_7 -2 + +/* prescalers timer 1 */ +#define TIMER1_PRESCALER_DIV_0 0 +#define TIMER1_PRESCALER_DIV_1 1 +#define TIMER1_PRESCALER_DIV_8 2 +#define TIMER1_PRESCALER_DIV_64 3 +#define TIMER1_PRESCALER_DIV_256 4 +#define TIMER1_PRESCALER_DIV_1024 5 +#define TIMER1_PRESCALER_DIV_FALL 6 +#define TIMER1_PRESCALER_DIV_RISE 7 + +#define TIMER1_PRESCALER_REG_0 0 +#define TIMER1_PRESCALER_REG_1 1 +#define TIMER1_PRESCALER_REG_2 8 +#define TIMER1_PRESCALER_REG_3 64 +#define TIMER1_PRESCALER_REG_4 256 +#define TIMER1_PRESCALER_REG_5 1024 +#define TIMER1_PRESCALER_REG_6 -1 +#define TIMER1_PRESCALER_REG_7 -2 + + +/* available timers */ +#define TIMER0_AVAILABLE +#define TIMER0A_AVAILABLE +#define TIMER0B_AVAILABLE +#define TIMER1_AVAILABLE +#define TIMER1A_AVAILABLE +#define TIMER1B_AVAILABLE + +/* overflow interrupt number */ +#define SIG_OVERFLOW0_NUM 0 +#define SIG_OVERFLOW1_NUM 1 +#define SIG_OVERFLOW_TOTAL_NUM 2 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE0A_NUM 0 +#define SIG_OUTPUT_COMPARE0B_NUM 1 +#define SIG_OUTPUT_COMPARE1A_NUM 2 +#define SIG_OUTPUT_COMPARE1B_NUM 3 +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4 + +/* Pwm nums */ +#define PWM0A_NUM 0 +#define PWM0B_NUM 1 +#define PWM1A_NUM 2 +#define PWM1B_NUM 3 +#define PWM_TOTAL_NUM 4 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE1_NUM 0 +#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 + + +/* CLKPR */ +#define CLKPS0_REG CLKPR +#define CLKPS1_REG CLKPR +#define CLKPS2_REG CLKPR +#define CLKPS3_REG CLKPR +#define CLKPCE_REG CLKPR + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH + +/* PCIFR */ +#define PCIF0_REG PCIFR +#define PCIF1_REG PCIFR +#define PCIF2_REG PCIFR +#define PCIF3_REG PCIFR + +/* ADMUX */ +#define MUX0_REG ADMUX +#define MUX1_REG ADMUX +#define MUX2_REG ADMUX +#define MUX3_REG ADMUX +#define ADLAR_REG ADMUX +#define REFS0_REG ADMUX +#define REFS1_REG ADMUX + +/* PORTCR */ +#define PUDA_REG PORTCR +#define PUDB_REG PORTCR +#define PUDC_REG PORTCR +#define PUDD_REG PORTCR +#define BBMA_REG PORTCR +#define BBMB_REG PORTCR +#define BBMC_REG PORTCR +#define BBMD_REG PORTCR + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* DDRB */ +#define DDB0_REG DDRB +#define DDB1_REG DDRB +#define DDB2_REG DDRB +#define DDB3_REG DDRB +#define DDB4_REG DDRB +#define DDB5_REG DDRB +#define DDB6_REG DDRB +#define DDB7_REG DDRB + +/* WDTCSR */ +#define WDP0_REG WDTCSR +#define WDP1_REG WDTCSR +#define WDP2_REG WDTCSR +#define WDE_REG WDTCSR +#define WDCE_REG WDTCSR +#define WDP3_REG WDTCSR +#define WDIE_REG WDTCSR +#define WDIF_REG WDTCSR + +/* EEDR */ +#define EEDR0_REG EEDR +#define EEDR1_REG EEDR +#define EEDR2_REG EEDR +#define EEDR3_REG EEDR +#define EEDR4_REG EEDR +#define EEDR5_REG EEDR +#define EEDR6_REG EEDR +#define EEDR7_REG EEDR + +/* TWDR */ +#define TWD0_REG TWDR +#define TWD1_REG TWDR +#define TWD2_REG TWDR +#define TWD3_REG TWDR +#define TWD4_REG TWDR +#define TWD5_REG TWDR +#define TWD6_REG TWDR +#define TWD7_REG TWDR + +/* OCR0B */ +#define OCR0B_0_REG OCR0B +#define OCR0B_1_REG OCR0B +#define OCR0B_2_REG OCR0B +#define OCR0B_3_REG OCR0B +#define OCR0B_4_REG OCR0B +#define OCR0B_5_REG OCR0B +#define OCR0B_6_REG OCR0B +#define OCR0B_7_REG OCR0B + +/* TCCR1A */ +#define WGM10_REG TCCR1A +#define WGM11_REG TCCR1A +#define COM1B0_REG TCCR1A +#define COM1B1_REG TCCR1A +#define COM1A0_REG TCCR1A +#define COM1A1_REG TCCR1A + +/* TCCR1C */ +#define FOC1B_REG TCCR1C +#define FOC1A_REG TCCR1C + +/* TCCR1B */ +#define CS10_REG TCCR1B +#define CS11_REG TCCR1B +#define CS12_REG TCCR1B +#define WGM12_REG TCCR1B +#define WGM13_REG TCCR1B +#define ICES1_REG TCCR1B +#define ICNC1_REG TCCR1B + +/* OCR1AH */ +#define OCR1AH0_REG OCR1AH +#define OCR1AH1_REG OCR1AH +#define OCR1AH2_REG OCR1AH +#define OCR1AH3_REG OCR1AH +#define OCR1AH4_REG OCR1AH +#define OCR1AH5_REG OCR1AH +#define OCR1AH6_REG OCR1AH +#define OCR1AH7_REG OCR1AH + +/* GTCCR */ +#define PSRSYNC_REG GTCCR +#define TSM_REG GTCCR + +/* DDRA */ +#define DDA0_REG DDRA +#define DDA1_REG DDRA +#define DDA2_REG DDRA +#define DDA3_REG DDRA + +/* ADCSRA */ +#define ADPS0_REG ADCSRA +#define ADPS1_REG ADCSRA +#define ADPS2_REG ADCSRA +#define ADIE_REG ADCSRA +#define ADIF_REG ADCSRA +#define ADATE_REG ADCSRA +#define ADSC_REG ADCSRA +#define ADEN_REG ADCSRA + +/* ADCSRB */ +#define ADTS0_REG ADCSRB +#define ADTS1_REG ADCSRB +#define ADTS2_REG ADCSRB +#define ACME_REG ADCSRB + +/* SPDR */ +#define SPDR0_REG SPDR +#define SPDR1_REG SPDR +#define SPDR2_REG SPDR +#define SPDR3_REG SPDR +#define SPDR4_REG SPDR +#define SPDR5_REG SPDR +#define SPDR6_REG SPDR +#define SPDR7_REG SPDR + +/* OCR0A */ +#define OCR0A_0_REG OCR0A +#define OCR0A_1_REG OCR0A +#define OCR0A_2_REG OCR0A +#define OCR0A_3_REG OCR0A +#define OCR0A_4_REG OCR0A +#define OCR0A_5_REG OCR0A +#define OCR0A_6_REG OCR0A +#define OCR0A_7_REG OCR0A + +/* SPSR */ +#define SPI2X_REG SPSR +#define WCOL_REG SPSR +#define SPIF_REG SPSR + +/* ACSR */ +#define ACIS0_REG ACSR +#define ACIS1_REG ACSR +#define ACIC_REG ACSR +#define ACIE_REG ACSR +#define ACI_REG ACSR +#define ACO_REG ACSR +#define ACBG_REG ACSR +#define ACD_REG ACSR + +/* ICR1H */ +#define ICR1H0_REG ICR1H +#define ICR1H1_REG ICR1H +#define ICR1H2_REG ICR1H +#define ICR1H3_REG ICR1H +#define ICR1H4_REG ICR1H +#define ICR1H5_REG ICR1H +#define ICR1H6_REG ICR1H +#define ICR1H7_REG ICR1H + +/* OCR1BL */ +#define OCR1BL0_REG OCR1BL +#define OCR1BL1_REG OCR1BL +#define OCR1BL2_REG OCR1BL +#define OCR1BL3_REG OCR1BL +#define OCR1BL4_REG OCR1BL +#define OCR1BL5_REG OCR1BL +#define OCR1BL6_REG OCR1BL +#define OCR1BL7_REG OCR1BL + +/* ICR1L */ +#define ICR1L0_REG ICR1L +#define ICR1L1_REG ICR1L +#define ICR1L2_REG ICR1L +#define ICR1L3_REG ICR1L +#define ICR1L4_REG ICR1L +#define ICR1L5_REG ICR1L +#define ICR1L6_REG ICR1L +#define ICR1L7_REG ICR1L + +/* OCR1BH */ +#define OCR1BH0_REG OCR1BH +#define OCR1BH1_REG OCR1BH +#define OCR1BH2_REG OCR1BH +#define OCR1BH3_REG OCR1BH +#define OCR1BH4_REG OCR1BH +#define OCR1BH5_REG OCR1BH +#define OCR1BH6_REG OCR1BH +#define OCR1BH7_REG OCR1BH + +/* PRR */ +#define PRADC_REG PRR +#define PRSPI_REG PRR +#define PRTIM1_REG PRR +#define PRTIM0_REG PRR +#define PRTWI_REG PRR + +/* GPIOR1 */ +#define GPIOR10_REG GPIOR1 +#define GPIOR11_REG GPIOR1 +#define GPIOR12_REG GPIOR1 +#define GPIOR13_REG GPIOR1 +#define GPIOR14_REG GPIOR1 +#define GPIOR15_REG GPIOR1 +#define GPIOR16_REG GPIOR1 +#define GPIOR17_REG GPIOR1 + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* TWBR */ +#define TWBR0_REG TWBR +#define TWBR1_REG TWBR +#define TWBR2_REG TWBR +#define TWBR3_REG TWBR +#define TWBR4_REG TWBR +#define TWBR5_REG TWBR +#define TWBR6_REG TWBR +#define TWBR7_REG TWBR + +/* PORTD */ +#define PORTD0_REG PORTD +#define PORTD1_REG PORTD +#define PORTD2_REG PORTD +#define PORTD3_REG PORTD +#define PORTD4_REG PORTD +#define PORTD5_REG PORTD +#define PORTD6_REG PORTD +#define PORTD7_REG PORTD + +/* MCUSR */ +#define PORF_REG MCUSR +#define EXTRF_REG MCUSR +#define BORF_REG MCUSR +#define WDRF_REG MCUSR + +/* EIMSK */ +#define INT0_REG EIMSK +#define INT1_REG EIMSK + +/* EECR */ +#define EERE_REG EECR +#define EEPE_REG EECR +#define EEMPE_REG EECR +#define EERIE_REG EECR +#define EEPM0_REG EECR +#define EEPM1_REG EECR + +/* SPMCSR */ +#define SELFPRGEN_REG SPMCSR +#define PGERS_REG SPMCSR +#define PGWRT_REG SPMCSR +#define RFLB_REG SPMCSR +#define CTPB_REG SPMCSR +#define RWWSB_REG SPMCSR + +/* OSCCAL */ +#define CAL0_REG OSCCAL +#define CAL1_REG OSCCAL +#define CAL2_REG OSCCAL +#define CAL3_REG OSCCAL +#define CAL4_REG OSCCAL +#define CAL5_REG OSCCAL +#define CAL6_REG OSCCAL +#define CAL7_REG OSCCAL + +/* TCNT1L */ +#define TCNT1L0_REG TCNT1L +#define TCNT1L1_REG TCNT1L +#define TCNT1L2_REG TCNT1L +#define TCNT1L3_REG TCNT1L +#define TCNT1L4_REG TCNT1L +#define TCNT1L5_REG TCNT1L +#define TCNT1L6_REG TCNT1L +#define TCNT1L7_REG TCNT1L + +/* PORTB */ +#define PORTB0_REG PORTB +#define PORTB1_REG PORTB +#define PORTB2_REG PORTB +#define PORTB3_REG PORTB +#define PORTB4_REG PORTB +#define PORTB5_REG PORTB +#define PORTB6_REG PORTB +#define PORTB7_REG PORTB + +/* ADCL */ +#define ADCL0_REG ADCL +#define ADCL1_REG ADCL +#define ADCL2_REG ADCL +#define ADCL3_REG ADCL +#define ADCL4_REG ADCL +#define ADCL5_REG ADCL +#define ADCL6_REG ADCL +#define ADCL7_REG ADCL + +/* SMCR */ +#define SE_REG SMCR +#define SM0_REG SMCR +#define SM1_REG SMCR + +/* TCNT1H */ +#define TCNT1H0_REG TCNT1H +#define TCNT1H1_REG TCNT1H +#define TCNT1H2_REG TCNT1H +#define TCNT1H3_REG TCNT1H +#define TCNT1H4_REG TCNT1H +#define TCNT1H5_REG TCNT1H +#define TCNT1H6_REG TCNT1H +#define TCNT1H7_REG TCNT1H + +/* PORTC */ +#define PORTC0_REG PORTC +#define PORTC1_REG PORTC +#define PORTC2_REG PORTC +#define PORTC3_REG PORTC +#define PORTC4_REG PORTC +#define PORTC5_REG PORTC +#define PORTC6_REG PORTC +#define PORTC7_REG PORTC + +/* ADCH */ +#define ADCH0_REG ADCH +#define ADCH1_REG ADCH +#define ADCH2_REG ADCH +#define ADCH3_REG ADCH +#define ADCH4_REG ADCH +#define ADCH5_REG ADCH +#define ADCH6_REG ADCH +#define ADCH7_REG ADCH + +/* TWHSR */ +#define TWIHS_REG TWHSR + +/* TWCR */ +#define TWIE_REG TWCR +#define TWEN_REG TWCR +#define TWWC_REG TWCR +#define TWSTO_REG TWCR +#define TWSTA_REG TWCR +#define TWEA_REG TWCR +#define TWINT_REG TWCR + +/* TCNT0 */ +#define TCNT0_0_REG TCNT0 +#define TCNT0_1_REG TCNT0 +#define TCNT0_2_REG TCNT0 +#define TCNT0_3_REG TCNT0 +#define TCNT0_4_REG TCNT0 +#define TCNT0_5_REG TCNT0 +#define TCNT0_6_REG TCNT0 +#define TCNT0_7_REG TCNT0 + +/* PCICR */ +#define PCIE0_REG PCICR +#define PCIE1_REG PCICR +#define PCIE2_REG PCICR +#define PCIE3_REG PCICR + +/* TWAR */ +#define TWGCE_REG TWAR +#define TWA0_REG TWAR +#define TWA1_REG TWAR +#define TWA2_REG TWAR +#define TWA3_REG TWAR +#define TWA4_REG TWAR +#define TWA5_REG TWAR +#define TWA6_REG TWAR + +/* GPIOR0 */ +#define GPIOR00_REG GPIOR0 +#define GPIOR01_REG GPIOR0 +#define GPIOR02_REG GPIOR0 +#define GPIOR03_REG GPIOR0 +#define GPIOR04_REG GPIOR0 +#define GPIOR05_REG GPIOR0 +#define GPIOR06_REG GPIOR0 +#define GPIOR07_REG GPIOR0 + +/* EEARL */ +#define EEAR0_REG EEARL +#define EEAR1_REG EEARL +#define EEAR2_REG EEARL +#define EEAR3_REG EEARL +#define EEAR4_REG EEARL +#define EEAR5_REG EEARL +#define EEAR6_REG EEARL +#define EEAR7_REG EEARL + +/* TIMSK0 */ +#define TOIE0_REG TIMSK0 +#define OCIE0A_REG TIMSK0 +#define OCIE0B_REG TIMSK0 + +/* TIMSK1 */ +#define TOIE1_REG TIMSK1 +#define OCIE1A_REG TIMSK1 +#define OCIE1B_REG TIMSK1 +#define ICIE1_REG TIMSK1 + +/* TCCR0A */ +#define CS00_REG TCCR0A +#define CS01_REG TCCR0A +#define CS02_REG TCCR0A +#define CTC0_REG TCCR0A + +/* TWSR */ +#define TWPS0_REG TWSR +#define TWPS1_REG TWSR +#define TWS3_REG TWSR +#define TWS4_REG TWSR +#define TWS5_REG TWSR +#define TWS6_REG TWSR +#define TWS7_REG TWSR + +/* GPIOR2 */ +#define GPIOR20_REG GPIOR2 +#define GPIOR21_REG GPIOR2 +#define GPIOR22_REG GPIOR2 +#define GPIOR23_REG GPIOR2 +#define GPIOR24_REG GPIOR2 +#define GPIOR25_REG GPIOR2 +#define GPIOR26_REG GPIOR2 +#define GPIOR27_REG GPIOR2 + +/* PCMSK0 */ +#define PCINT0_REG PCMSK0 +#define PCINT1_REG PCMSK0 +#define PCINT2_REG PCMSK0 +#define PCINT3_REG PCMSK0 +#define PCINT4_REG PCMSK0 +#define PCINT5_REG PCMSK0 +#define PCINT6_REG PCMSK0 +#define PCINT7_REG PCMSK0 + +/* PCMSK1 */ +#define PCINT8_REG PCMSK1 +#define PCINT9_REG PCMSK1 +#define PCINT10_REG PCMSK1 +#define PCINT11_REG PCMSK1 +#define PCINT12_REG PCMSK1 +#define PCINT13_REG PCMSK1 +#define PCINT14_REG PCMSK1 +#define PCINT15_REG PCMSK1 + +/* PCMSK2 */ +#define PCINT16_REG PCMSK2 +#define PCINT17_REG PCMSK2 +#define PCINT18_REG PCMSK2 +#define PCINT19_REG PCMSK2 +#define PCINT20_REG PCMSK2 +#define PCINT21_REG PCMSK2 +#define PCINT22_REG PCMSK2 +#define PCINT23_REG PCMSK2 + +/* PCMSK3 */ +#define PCINT24_REG PCMSK3 +#define PCINT25_REG PCMSK3 +#define PCINT26_REG PCMSK3 +#define PCINT27_REG PCMSK3 + +/* PINC */ +#define PINC0_REG PINC +#define PINC1_REG PINC +#define PINC2_REG PINC +#define PINC3_REG PINC +#define PINC4_REG PINC +#define PINC5_REG PINC +#define PINC6_REG PINC +#define PINC7_REG PINC + +/* DDRC */ +#define DDC0_REG DDRC +#define DDC1_REG DDRC +#define DDC2_REG DDRC +#define DDC3_REG DDRC +#define DDC4_REG DDRC +#define DDC5_REG DDRC +#define DDC6_REG DDRC +#define DDC7_REG DDRC + +/* EIFR */ +#define INTF0_REG EIFR +#define INTF1_REG EIFR + +/* EICRA */ +#define ISC00_REG EICRA +#define ISC01_REG EICRA +#define ISC10_REG EICRA +#define ISC11_REG EICRA + +/* DIDR0 */ +#define ADC0D_REG DIDR0 +#define ADC1D_REG DIDR0 +#define ADC2D_REG DIDR0 +#define ADC3D_REG DIDR0 +#define ADC4D_REG DIDR0 +#define ADC5D_REG DIDR0 +#define ADC6D_REG DIDR0 +#define ADC7D_REG DIDR0 + +/* DIDR1 */ +#define AIN0D_REG DIDR1 +#define AIN1D_REG DIDR1 +#define AREFD_REG DIDR1 + +/* MCUCR */ +#define PUD_REG MCUCR +#define BODSE_REG MCUCR +#define BODS_REG MCUCR + +/* TWAMR */ +#define TWAM0_REG TWAMR +#define TWAM1_REG TWAMR +#define TWAM2_REG TWAMR +#define TWAM3_REG TWAMR +#define TWAM4_REG TWAMR +#define TWAM5_REG TWAMR +#define TWAM6_REG TWAMR + +/* DDRD */ +#define DDD0_REG DDRD +#define DDD1_REG DDRD +#define DDD2_REG DDRD +#define DDD3_REG DDRD +#define DDD4_REG DDRD +#define DDD5_REG DDRD +#define DDD6_REG DDRD +#define DDD7_REG DDRD + +/* OCR1AL */ +#define OCR1AL0_REG OCR1AL +#define OCR1AL1_REG OCR1AL +#define OCR1AL2_REG OCR1AL +#define OCR1AL3_REG OCR1AL +#define OCR1AL4_REG OCR1AL +#define OCR1AL5_REG OCR1AL +#define OCR1AL6_REG OCR1AL +#define OCR1AL7_REG OCR1AL + +/* TIFR0 */ +#define TOV0_REG TIFR0 +#define OCF0A_REG TIFR0 +#define OCF0B_REG TIFR0 + +/* PINB */ +#define PINB0_REG PINB +#define PINB1_REG PINB +#define PINB2_REG PINB +#define PINB3_REG PINB +#define PINB4_REG PINB +#define PINB5_REG PINB +#define PINB6_REG PINB +#define PINB7_REG PINB + +/* PORTA */ +#define PORTA0_REG PORTA +#define PORTA1_REG PORTA +#define PORTA2_REG PORTA +#define PORTA3_REG PORTA + +/* PIND */ +#define PIND0_REG PIND +#define PIND1_REG PIND +#define PIND2_REG PIND +#define PIND3_REG PIND +#define PIND4_REG PIND +#define PIND5_REG PIND +#define PIND6_REG PIND +#define PIND7_REG PIND + +/* PINA */ +#define PINA0_REG PINA +#define PINA1_REG PINA +#define PINA2_REG PINA +#define PINA3_REG PINA + +/* SPCR */ +#define SPR0_REG SPCR +#define SPR1_REG SPCR +#define CPHA_REG SPCR +#define CPOL_REG SPCR +#define MSTR_REG SPCR +#define DORD_REG SPCR +#define SPE_REG SPCR +#define SPIE_REG SPCR + +/* TIFR1 */ +#define TOV1_REG TIFR1 +#define OCF1A_REG TIFR1 +#define OCF1B_REG TIFR1 +#define ICF1_REG TIFR1 + +/* pins mapping */ +#define ICP1_PORT PORTB +#define ICP1_BIT 0 +#define CLKO_PORT PORTB +#define CLKO_BIT 0 +#define PCINT0_PORT PORTB +#define PCINT0_BIT 0 + +#define OC1A_PORT PORTB +#define OC1A_BIT 1 +#define PCINT1_PORT PORTB +#define PCINT1_BIT 1 + +#define SS_PORT PORTB +#define SS_BIT 2 +#define OC1B_PORT PORTB +#define OC1B_BIT 2 +#define PCINT2_PORT PORTB +#define PCINT2_BIT 2 + +#define MOSI_PORT PORTB +#define MOSI_BIT 3 +#define OC2A_PORT PORTB +#define OC2A_BIT 3 +#define PCINT3_PORT PORTB +#define PCINT3_BIT 3 + +#define MISO_PORT PORTB +#define MISO_BIT 4 +#define PCINT4_PORT PORTB +#define PCINT4_BIT 4 + +#define SCK_PORT PORTB +#define SCK_BIT 5 +#define PCINT5_PORT PORTB +#define PCINT5_BIT 5 + +#define XTAL1_PORT PORTB +#define XTAL1_BIT 6 +#define TOSC1_PORT PORTB +#define TOSC1_BIT 6 +#define PCINT6_PORT PORTB +#define PCINT6_BIT 6 + +#define XTAL2_PORT PORTB +#define XTAL2_BIT 7 +#define TOSC2_PORT PORTB +#define TOSC2_BIT 7 +#define PCINT7_PORT PORTB +#define PCINT7_BIT 7 + +#define ADC0_PORT PORTC +#define ADC0_BIT 0 +#define PCINT8_PORT PORTC +#define PCINT8_BIT 0 + +#define ADC1_PORT PORTC +#define ADC1_BIT 1 +#define PCINT9_PORT PORTC +#define PCINT9_BIT 1 + +#define ADC2_PORT PORTC +#define ADC2_BIT 2 +#define PCINT10_PORT PORTC +#define PCINT10_BIT 2 + +#define ADC3_PORT PORTC +#define ADC3_BIT 3 +#define PCINT11_PORT PORTC +#define PCINT11_BIT 3 + +#define ADC4_PORT PORTC +#define ADC4_BIT 4 +#define SDA_PORT PORTC +#define SDA_BIT 4 +#define PCINT12_PORT PORTC +#define PCINT12_BIT 4 + +#define ADC5_PORT PORTC +#define ADC5_BIT 5 +#define SCL_PORT PORTC +#define SCL_BIT 5 +#define PCINT13_PORT PORTC +#define PCINT13_BIT 5 + +#define RESET_PORT PORTC +#define RESET_BIT 6 +#define PCINT14_PORT PORTC +#define PCINT14_BIT 6 + +#define RXD_PORT PORTD +#define RXD_BIT 0 +#define PCINT16_PORT PORTD +#define PCINT16_BIT 0 + +#define TXD_PORT PORTD +#define TXD_BIT 1 +#define PCINT17_PORT PORTD +#define PCINT17_BIT 1 + +#define INT0_PORT PORTD +#define INT0_BIT 2 +#define PCINT18_PORT PORTD +#define PCINT18_BIT 2 + +#define PCINT19_PORT PORTD +#define PCINT19_BIT 3 +#define OC2B_PORT PORTD +#define OC2B_BIT 3 +#define INT1_PORT PORTD +#define INT1_BIT 3 + +#define XCK_PORT PORTD +#define XCK_BIT 4 +#define T0_PORT PORTD +#define T0_BIT 4 +#define PCINT20_PORT PORTD +#define PCINT20_BIT 4 + +#define T1_PORT PORTD +#define T1_BIT 5 +#define OC0B_PORT PORTD +#define OC0B_BIT 5 +#define PCINT21_PORT PORTD +#define PCINT21_BIT 5 + +#define AIN0_PORT PORTD +#define AIN0_BIT 6 +#define OC0A_PORT PORTD +#define OC0A_BIT 6 +#define PCINT22_PORT PORTD +#define PCINT22_BIT 6 + +#define AIN1_PORT PORTD +#define AIN1_BIT 7 +#define PCINT23_PORT PORTD +#define PCINT23_BIT 7 + + diff --git a/include/aversive/parts/ATxmega128A1.h b/include/aversive/parts/ATxmega128A1.h new file mode 100644 index 0000000..0ea8e2b --- /dev/null +++ b/include/aversive/parts/ATxmega128A1.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* pins mapping */ + diff --git a/include/aversive/parts/ATxmega128A3.h b/include/aversive/parts/ATxmega128A3.h new file mode 100644 index 0000000..0ea8e2b --- /dev/null +++ b/include/aversive/parts/ATxmega128A3.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* pins mapping */ + diff --git a/include/aversive/parts/ATxmega256A3.h b/include/aversive/parts/ATxmega256A3.h new file mode 100644 index 0000000..0ea8e2b --- /dev/null +++ b/include/aversive/parts/ATxmega256A3.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* pins mapping */ + diff --git a/include/aversive/parts/ATxmega256A3B.h b/include/aversive/parts/ATxmega256A3B.h new file mode 100644 index 0000000..0ea8e2b --- /dev/null +++ b/include/aversive/parts/ATxmega256A3B.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* pins mapping */ + diff --git a/include/aversive/parts/ATxmega64A1.h b/include/aversive/parts/ATxmega64A1.h new file mode 100644 index 0000000..0ea8e2b --- /dev/null +++ b/include/aversive/parts/ATxmega64A1.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* pins mapping */ + diff --git a/include/aversive/parts/ATxmega64A3.h b/include/aversive/parts/ATxmega64A3.h new file mode 100644 index 0000000..0ea8e2b --- /dev/null +++ b/include/aversive/parts/ATxmega64A3.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id $ + * + */ + +/* WARNING : this file is automatically generated by scripts. + * You should not edit it. If you find something wrong in it, + * write to zer0@droids-corp.org */ + + + +/* available timers */ + +/* overflow interrupt number */ +#define SIG_OVERFLOW_TOTAL_NUM 0 + +/* output compare interrupt number */ +#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 + +/* Pwm nums */ +#define PWM_TOTAL_NUM 0 + +/* input capture interrupt number */ +#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 + + +/* SPH */ +#define SP8_REG SPH +#define SP9_REG SPH +#define SP10_REG SPH +#define SP11_REG SPH +#define SP12_REG SPH +#define SP13_REG SPH +#define SP14_REG SPH +#define SP15_REG SPH + +/* SPL */ +#define SP0_REG SPL +#define SP1_REG SPL +#define SP2_REG SPL +#define SP3_REG SPL +#define SP4_REG SPL +#define SP5_REG SPL +#define SP6_REG SPL +#define SP7_REG SPL + +/* SREG */ +#define C_REG SREG +#define Z_REG SREG +#define N_REG SREG +#define V_REG SREG +#define S_REG SREG +#define H_REG SREG +#define T_REG SREG +#define I_REG SREG + +/* pins mapping */ + diff --git a/include/aversive/parts/CVS/Entries b/include/aversive/parts/CVS/Entries new file mode 100644 index 0000000..f578ed9 --- /dev/null +++ b/include/aversive/parts/CVS/Entries @@ -0,0 +1,122 @@ +/AT86RF401.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT89S51.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT89S52.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90CAN128.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90CAN32.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90CAN64.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90PWM2.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90PWM216.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90PWM2B.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90PWM3.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90PWM316.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90PWM3B.h/1.1.2.1/Fri Jan 23 22:53:08 2009//Tb_zer0 +/AT90S1200.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S2313.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S2323.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S2343.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S4414.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S4433.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S4434.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S8515.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S8515comp.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S8535.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90S8535comp.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90USB1286.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90USB1287.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90USB162.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90USB646.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90USB647.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/AT90USB82.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega103.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega103comp.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega128.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega1280.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega1281.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega1284P.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega128A.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega16.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega161.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega161comp.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega162.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega163.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega164P.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega165.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega165P.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega168.h/1.1.2.2/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega168P.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega168PA.h/1.1.2.1/Fri Jan 23 22:53:07 2009//Tb_zer0 +/ATmega169.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega169P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega16A.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega16HVA.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega16U4.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega2560.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega2561.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega323.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega324P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega324PA.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega325.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega3250.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega3250P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega325P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega328P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega329.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega3290.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega3290P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega329P.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32A.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32C1.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32HVB.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32M1.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32U4.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega32U6.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega406.h/1.1.2.2/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega48.h/1.1.2.1/Fri Jan 23 22:53:06 2009//Tb_zer0 +/ATmega48P.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega64.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega640.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega644.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega644P.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega645.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega6450.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega649.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega6490.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega64A.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega8.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega8515.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega8535.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega88.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega88P.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega88PA.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATmega8A.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny10.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny11.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny12.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny13.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny13A.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny15.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny167.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny22.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny2313.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny24.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny25.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny26.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny261.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny28.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny43U.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny44.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny45.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny461.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny48.h/1.1.2.1/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny84.h/1.1.2.2/Fri Jan 23 22:53:05 2009//Tb_zer0 +/ATtiny85.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATtiny861.h/1.1.2.2/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATtiny88.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATxmega128A1.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATxmega128A3.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATxmega256A3.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATxmega256A3B.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATxmega64A1.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +/ATxmega64A3.h/1.1.2.1/Fri Jan 23 22:53:04 2009//Tb_zer0 +D diff --git a/include/aversive/parts/CVS/Repository b/include/aversive/parts/CVS/Repository new file mode 100644 index 0000000..df794b2 --- /dev/null +++ b/include/aversive/parts/CVS/Repository @@ -0,0 +1 @@ +aversive/include/aversive/parts diff --git a/include/aversive/parts/CVS/Root b/include/aversive/parts/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/include/aversive/parts/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/include/aversive/parts/CVS/Tag b/include/aversive/parts/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/include/aversive/parts/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/include/aversive/parts/CVS/Template b/include/aversive/parts/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/include/aversive/pgmspace.h b/include/aversive/pgmspace.h new file mode 100644 index 0000000..d6dadb8 --- /dev/null +++ b/include/aversive/pgmspace.h @@ -0,0 +1,70 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pgmspace.h,v 1.1.2.4 2007-11-21 21:54:38 zer0 Exp $ + * + */ + +/** + * This file is used for compatibility between host and avr : with + * this we can emulate pgmspace on a host. + */ + +#ifndef _AVERSIVE_PGMSPACE_H_ +#define _AVERSIVE_PGMSPACE_H_ + +#ifndef HOST_VERSION + +#include <avr/pgmspace.h> + + +#else + +#include <stdint.h> + +#define printf_P printf +#define memcmp_P memcmp +#define strcat_P strcat +#define strcmp_P strcmp +#define strncmp_P strncmp +#define strlen_P strlen +#define vfprintf_P vfprintf +#define vsprintf_P vsprintf +#define PGM_P const char * +#define PSTR(x) x +#define PROGMEM + +/* XXX don't define it, it's dangerous because it can be used to read + * an address that have not the same size */ +/* #define pgm_read_word(x) (*(x)) */ +/* #define pgm_read_byte(x) (*(x)) */ + +typedef void prog_void; +typedef char prog_char; +typedef unsigned char prog_uchar; +typedef int8_t prog_int8_t; +typedef uint8_t prog_uint8_t; +typedef int16_t prog_int16_t; +typedef uint16_t prog_uint16_t; +typedef int32_t prog_int32_t; +typedef uint32_t prog_uint32_t; +typedef int64_t prog_int64_t; + +#endif /* HOST_VERSION */ +#endif /* _AVERSIVE_PGMSPACE_H_ */ + + diff --git a/include/aversive/queue.h b/include/aversive/queue.h new file mode 100644 index 0000000..bad0753 --- /dev/null +++ b/include/aversive/queue.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: src/sys/sys/queue.h,v 1.32.2.7 2002/04/17 14:21:02 des Exp $ + */ + +#ifndef _AVERSIVE_QUEUE_H_ +#define _AVERSIVE_QUEUE_H_ + +#ifndef __offsetof +#define __offsetof(type, field) ((size_t)(&(type *)0)->field)) +#endif + +/* + * This file defines five types of data structures: singly-linked lists, + * singly-linked tail queues, lists, tail queues, and circular queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * A circle queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or after + * an existing element, at the head of the list, or at the end of the list. + * A circle queue may be traversed in either direction, but has a more + * complex end of list detection. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ CIRCLEQ + * _HEAD + + + + + + * _HEAD_INITIALIZER + + + + + + * _ENTRY + + + + + + * _INIT + + + + + + * _EMPTY + + + + + + * _FIRST + + + + + + * _NEXT + + + + + + * _PREV - - - + + + * _LAST - - + + + + * _FOREACH + + + + + + * _FOREACH_REVERSE - - - + + + * _INSERT_HEAD + + + + + + * _INSERT_BEFORE - + - + + + * _INSERT_AFTER + + + + + + * _INSERT_TAIL - - + + + + * _REMOVE_HEAD + - + - - + * _REMOVE + + + + + + * + */ + +/* + * Singly-linked List declarations. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for ((var) = SLIST_FIRST((head)); \ + (var); \ + (var) = SLIST_NEXT((var), field)) + +#define SLIST_INIT(head) do { \ + SLIST_FIRST((head)) = NULL; \ +} while (0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ + SLIST_NEXT((slistelm), field) = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ + SLIST_FIRST((head)) = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if (SLIST_FIRST((head)) == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = SLIST_FIRST((head)); \ + while (SLIST_NEXT(curelm, field) != (elm)) \ + curelm = SLIST_NEXT(curelm, field); \ + SLIST_NEXT(curelm, field) = \ + SLIST_NEXT(SLIST_NEXT(curelm, field), field); \ + } \ +} while (0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ +} while (0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = STAILQ_FIRST((head)); \ + (var); \ + (var) = STAILQ_NEXT((var), field)) + +#define STAILQ_INIT(head) do { \ + STAILQ_FIRST((head)) = NULL; \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_NEXT((tqelm), field) = (elm); \ +} while (0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_FIRST((head)) = (elm); \ +} while (0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + STAILQ_NEXT((elm), field) = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY(head) ? \ + NULL : \ + ((struct type *) \ + ((char *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if (STAILQ_FIRST((head)) == (elm)) { \ + STAILQ_REMOVE_HEAD(head, field); \ + } \ + else { \ + struct type *curelm = STAILQ_FIRST((head)); \ + while (STAILQ_NEXT(curelm, field) != (elm)) \ + curelm = STAILQ_NEXT(curelm, field); \ + if ((STAILQ_NEXT(curelm, field) = \ + STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((curelm), field);\ + } \ +} while (0) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if ((STAILQ_FIRST((head)) = \ + STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \ + if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +/* + * List declarations. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = LIST_FIRST((head)); \ + (var); \ + (var) = LIST_NEXT((var), field)) + +#define LIST_INIT(head) do { \ + LIST_FIRST((head)) = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ + LIST_NEXT((listelm), field)->field.le_prev = \ + &LIST_NEXT((elm), field); \ + LIST_NEXT((listelm), field) = (elm); \ + (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + LIST_NEXT((elm), field) = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ + LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ + LIST_FIRST((head)) = (elm); \ + (elm)->field.le_prev = &LIST_FIRST((head)); \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_REMOVE(elm, field) do { \ + if (LIST_NEXT((elm), field) != NULL) \ + LIST_NEXT((elm), field)->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = LIST_NEXT((elm), field); \ +} while (0) + +/* + * Tail queue declarations. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ +} + +/* + * Tail queue functions. + */ +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = TAILQ_FIRST((head)); \ + (var); \ + (var) = TAILQ_NEXT((var), field)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_INIT(head) do { \ + TAILQ_FIRST((head)) = NULL; \ + (head)->tqh_last = &TAILQ_FIRST((head)); \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + TAILQ_NEXT((listelm), field) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + TAILQ_NEXT((elm), field) = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ + TAILQ_FIRST((head))->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + TAILQ_FIRST((head)) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + TAILQ_NEXT((elm), field) = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ +} while (0) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_REMOVE(head, elm, field) do { \ + if ((TAILQ_NEXT((elm), field)) != NULL) \ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ +} while (0) + +/* + * Circular queue declarations. + */ +#define CIRCLEQ_HEAD(name, type) \ +struct name { \ + struct type *cqh_first; /* first element */ \ + struct type *cqh_last; /* last element */ \ +} + +#define CIRCLEQ_HEAD_INITIALIZER(head) \ + { (void *)&(head), (void *)&(head) } + +#define CIRCLEQ_ENTRY(type) \ +struct { \ + struct type *cqe_next; /* next element */ \ + struct type *cqe_prev; /* previous element */ \ +} + +/* + * Circular queue functions. + */ +#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) + +#define CIRCLEQ_FIRST(head) ((head)->cqh_first) + +#define CIRCLEQ_FOREACH(var, head, field) \ + for ((var) = CIRCLEQ_FIRST((head)); \ + (var) != (void *)(head) || ((var) = NULL); \ + (var) = CIRCLEQ_NEXT((var), field)) + +#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \ + for ((var) = CIRCLEQ_LAST((head)); \ + (var) != (void *)(head) || ((var) = NULL); \ + (var) = CIRCLEQ_PREV((var), field)) + +#define CIRCLEQ_INIT(head) do { \ + CIRCLEQ_FIRST((head)) = (void *)(head); \ + CIRCLEQ_LAST((head)) = (void *)(head); \ +} while (0) + +#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + CIRCLEQ_NEXT((elm), field) = CIRCLEQ_NEXT((listelm), field); \ + CIRCLEQ_PREV((elm), field) = (listelm); \ + if (CIRCLEQ_NEXT((listelm), field) == (void *)(head)) \ + CIRCLEQ_LAST((head)) = (elm); \ + else \ + CIRCLEQ_PREV(CIRCLEQ_NEXT((listelm), field), field) = (elm);\ + CIRCLEQ_NEXT((listelm), field) = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + CIRCLEQ_NEXT((elm), field) = (listelm); \ + CIRCLEQ_PREV((elm), field) = CIRCLEQ_PREV((listelm), field); \ + if (CIRCLEQ_PREV((listelm), field) == (void *)(head)) \ + CIRCLEQ_FIRST((head)) = (elm); \ + else \ + CIRCLEQ_NEXT(CIRCLEQ_PREV((listelm), field), field) = (elm);\ + CIRCLEQ_PREV((listelm), field) = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ + CIRCLEQ_NEXT((elm), field) = CIRCLEQ_FIRST((head)); \ + CIRCLEQ_PREV((elm), field) = (void *)(head); \ + if (CIRCLEQ_LAST((head)) == (void *)(head)) \ + CIRCLEQ_LAST((head)) = (elm); \ + else \ + CIRCLEQ_PREV(CIRCLEQ_FIRST((head)), field) = (elm); \ + CIRCLEQ_FIRST((head)) = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ + CIRCLEQ_NEXT((elm), field) = (void *)(head); \ + CIRCLEQ_PREV((elm), field) = CIRCLEQ_LAST((head)); \ + if (CIRCLEQ_FIRST((head)) == (void *)(head)) \ + CIRCLEQ_FIRST((head)) = (elm); \ + else \ + CIRCLEQ_NEXT(CIRCLEQ_LAST((head)), field) = (elm); \ + CIRCLEQ_LAST((head)) = (elm); \ +} while (0) + +#define CIRCLEQ_LAST(head) ((head)->cqh_last) + +#define CIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next) + +#define CIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev) + +#define CIRCLEQ_REMOVE(head, elm, field) do { \ + if (CIRCLEQ_NEXT((elm), field) == (void *)(head)) \ + CIRCLEQ_LAST((head)) = CIRCLEQ_PREV((elm), field); \ + else \ + CIRCLEQ_PREV(CIRCLEQ_NEXT((elm), field), field) = \ + CIRCLEQ_PREV((elm), field); \ + if (CIRCLEQ_PREV((elm), field) == (void *)(head)) \ + CIRCLEQ_FIRST((head)) = CIRCLEQ_NEXT((elm), field); \ + else \ + CIRCLEQ_NEXT(CIRCLEQ_PREV((elm), field), field) = \ + CIRCLEQ_NEXT((elm), field); \ +} while (0) + + +#endif /* !_AVERSIVE_QUEUE_H_ */ diff --git a/include/aversive/timers.h b/include/aversive/timers.h new file mode 100644 index 0000000..892c81e --- /dev/null +++ b/include/aversive/timers.h @@ -0,0 +1,196 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timers.h,v 1.1.2.4 2009-01-23 23:54:16 zer0 Exp $ + * + */ + +/* + * This file contains definitions used for timer use + * + * In the future, most of definitions will be added in autogenerated + * files from atmel's documentation (aversive/parts.h and + * aversive/parts/ATxxxx.h) which are not timer specific. + */ + +/* XXX won't be needed : use parts.h */ + +#ifndef _AVERSIVE_TIMERS_H_ +#define _AVERSIVE_TIMERS_H_ + +// Timer WGM bits +#define TIMER_8_MODE_NORMAL 0 +#define TIMER_8_MODE_PWM_PC 1 // phase correct PWM +#define TIMER_8_MODE_CTC 2 +#define TIMER_8_MODE_PWM 3 // fast PWM + +#define TIMER_16_MODE_NORMAL 0 +#define TIMER_16_MODE_PWM_PC_8 1 // phase correct PWM 8 bits +#define TIMER_16_MODE_PWM_PC_9 2 // phase correct PWM 9 bits +#define TIMER_16_MODE_PWM_PC_10 3 // phase correct PWM 10 bits +#define TIMER_16_MODE_CTC1 4 // clear on compare, TOP = OCRA +#define TIMER_16_MODE_PWM_8 5 // fast PWM 8 bits +#define TIMER_16_MODE_PWM_9 6 // fast PWM 9 bits +#define TIMER_16_MODE_PWM_10 7 // fast PWM 10 bits +#define TIMER_16_MODE_PWM_PFC1 8 // PWM, Phase & Freq Correct +#define TIMER_16_MODE_PWM_PFC2 9 // PWM, Phase & Freq Correct +#define TIMER_16_MODE_PWM_PC1 10 // PWM, Phase Correct +#define TIMER_16_MODE_PWM_PC2 11 // PWM, Phase Correct +#define TIMER_16_MODE_CTC2 12 // clear on compare, TOP = ICR +#define TIMER_16_MODE_PWM_F1 14 // fast PWM +#define TIMER_16_MODE_PWM_F2 15 // fast PWM + + +// ATMEGA128 //////////////////////////////////////// +#if defined (__AVR_ATmega128__) + +// OCR_BITS +#define OCR0_DDR DDRB +#define OCR0_BIT 4 +#define OCR1A_DDR DDRB +#define OCR1A_BIT 5 +#define OCR1B_DDR DDRB +#define OCR1B_BIT 6 +#define OCR1C_DDR DDRB +#define OCR1C_BIT 7 +#define OCR2_DDR DDRB +#define OCR2_BIT 7 +#define OCR3A_DDR DDRE +#define OCR3A_BIT 3 +#define OCR3B_DDR DDRE +#define OCR3B_BIT 4 +#define OCR3C_DDR DDRE +#define OCR3C_BIT 5 + + + + +// ATMEGA1281 //////////////////////////////////////// +#elif defined (__AVR_ATmega1281__) + +// OCR_BITS +#define OCR0A_DDR DDRB +#define OCR0A_BIT 7 +#define OCR0B_DDR DDRG +#define OCR0B_BIT 5 +#define OCR1A_DDR DDRB +#define OCR1A_BIT 5 +#define OCR1B_DDR DDRB +#define OCR1B_BIT 6 +#define OCR1C_DDR DDRB +#define OCR1C_BIT 7 +#define OCR2A_DDR DDRB +#define OCR2A_BIT 4 +#define OCR3A_DDR DDRE +#define OCR3A_BIT 3 +#define OCR3B_DDR DDRE +#define OCR3B_BIT 4 +#define OCR3C_DDR DDRE +#define OCR3C_BIT 5 + + + +// ATMEGA32 //////////////////////////////////////// +#elif defined (__AVR_ATmega32__) || defined (__AVR_ATmega323__) + +#ifdef __AVR_ATmega323__ + +// renamed bits +#define WGM20 PWM2 +#define WGM21 CTC2 + +#define WGM10 PWM10 +#define WGM11 PWM11 +#define WGM12 3//CTC1 +#define WGM13 4 // reserve bit + +#define WGM00 PWM0 +#define WGM01 CTC0 + +#endif // mega323 + + +// OCR_BITS +#define OCR0_DDR DDRB +#define OCR0_BIT 3 +#define OCR1A_DDR DDRD +#define OCR1A_BIT 5 +#define OCR1B_DDR DDRD +#define OCR1B_BIT 4 +#define OCR2_DDR DDRD +#define OCR2_BIT 7 + + +// ATMEGA8 //////////////////////////////////////// +#elif defined (__AVR_ATmega8__) + +// OCR_BITS +#define OCR1A_DDR DDRB +#define OCR1A_BIT 1 +#define OCR1B_DDR DDRB +#define OCR1B_BIT 2 +#define OCR2_DDR DDRB +#define OCR2_BIT 3 + + + +// ATMEGA163 //////////////////////////////////////// +#elif defined (__AVR_ATmega163__) + +// renamed bits +#define WGM20 PWM2 +#define WGM21 CTC2 + +#define WGM10 PWM10 +#define WGM11 PWM11 +#define WGM12 CTC1 +#define WGM13 4 // reserve bit + +// OCR_BITS +#define OCR1A_DDR DDRD +#define OCR1A_BIT 5 +#define OCR1B_DDR DDRD +#define OCR1B_BIT 4 +#define OCR2_DDR DDRD +#define OCR2_BIT 7 + + +// ATMEGAx8 //////////////////////////////////////// +#elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) + +// OCR_BITS +#define OCR0A_DDR DDRD +#define OCR0A_BIT 6 +#define OCR0B_DDR DDRD +#define OCR0B_BIT 5 + +#define OCR1A_DDR DDRB +#define OCR1A_BIT 1 +#define OCR1B_DDR DDRB +#define OCR1B_BIT 2 + +#define OCR2A_DDR DDRB +#define OCR2A_BIT 3 +#define OCR2B_DDR DDRD +#define OCR2B_BIT 3 + + +#else +//#error No timer/prescaler definitions for your AVR type +#endif + +#endif diff --git a/include/aversive/types.h b/include/aversive/types.h new file mode 100644 index 0000000..6eb3cca --- /dev/null +++ b/include/aversive/types.h @@ -0,0 +1,57 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: types.h,v 1.1.2.1 2007-05-23 17:18:09 zer0 Exp $ + * + */ + +#ifndef _AVERSIVE_TYPES_H_ +#define _AVERSIVE_TYPES_H_ + +#include <inttypes.h> + +#define U08_MIN 0x00 +#define U08_MAX 0xFF +#define U16_MIN 0x0000 +#define U16_MAX 0xFFFF +#define U32_MIN 0x00000000 +#define U32_MAX 0xFFFFFFFF +#define U64_MIN 0x0000000000000000 +#define U64_MAX 0xFFFFFFFFFFFFFFFF +#define S08_MIN 0x80 +#define S08_MAX 0x7F +#define S16_MIN 0x8000 +#define S16_MAX 0x7FFF +#define S32_MIN 0x80000000 +#define S32_MAX 0x7FFFFFFF +#define S64_MIN 0x8000000000000000 +#define S64_MAX 0x7FFFFFFFFFFFFFFF + +/* you should use uintXX_t instead of uXX which is more standard */ + +/* explicit types u = unsigned, s = signed */ +typedef uint8_t u08; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; +typedef int8_t s08; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; + + +#endif /* _AVERSIVE_TYPES_H_ */ diff --git a/include/aversive/wait.h b/include/aversive/wait.h new file mode 100644 index 0000000..176152d --- /dev/null +++ b/include/aversive/wait.h @@ -0,0 +1,67 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: wait.h,v 1.1.2.1 2007-05-23 17:18:09 zer0 Exp $ + * + */ + +/** + * This file is an interface for wait functions, in order to put the + * microcontroller in a loop state. + */ + +/**********************************************************/ + +#ifndef _AVERSIVE_WAIT_H_ +#define _AVERSIVE_WAIT_H_ + +#include <aversive.h> + +#ifdef HOST_VERSION + +#define wait_3cyc(n) do {} while(0) +#define wait_4cyc(n) do {} while(0) +#define wait_ms(n) do {} while(0) + +#else /* HOST_VERSION */ + +#if __AVR_LIBC_VERSION__ < 10403UL +#include <avr/delay.h> +#else +#include <util/delay.h> +#endif + +/** wait n "3 cycles time" + * n is 8 bits */ +#define wait_3cyc(n) _delay_loop_1(n) + +/** wait n "4 cycles time" + * n is 16 bits */ +#define wait_4cyc(n) _delay_loop_2(n) + +/** wait n milliseconds + * n is 16 bits + */ +static inline void wait_ms(uint16_t n) +{ + while ( n -- ) + wait_4cyc(F_CPU/4000); +} + +#endif /* else HOST_VERSION */ + +#endif /* _AVERSIVE_WAIT_ */ diff --git a/mk/CVS/Entries b/mk/CVS/Entries new file mode 100644 index 0000000..a30f81a --- /dev/null +++ b/mk/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile_module.template/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/Makefile_project.template/1.3.6.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/aversive_module.mk/1.12.4.3/Sat May 12 16:42:38 2007//Tb_zer0 +/aversive_project.mk/1.32.4.16/Sat May 2 09:42:46 2009//Tb_zer0 +D diff --git a/mk/CVS/Repository b/mk/CVS/Repository new file mode 100644 index 0000000..1909d2d --- /dev/null +++ b/mk/CVS/Repository @@ -0,0 +1 @@ +aversive/mk diff --git a/mk/CVS/Root b/mk/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/mk/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/mk/CVS/Tag b/mk/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/mk/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/mk/CVS/Template b/mk/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/mk/Makefile_module.template b/mk/Makefile_module.template new file mode 100644 index 0000000..d195f38 --- /dev/null +++ b/mk/Makefile_module.template @@ -0,0 +1,10 @@ +-include .config + +TARGET = # VALUE, name of the module # + +# List C source files here. (C dependencies are automatically generated.) +SRC = + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/mk/Makefile_project.template b/mk/Makefile_project.template new file mode 100644 index 0000000..921e065 --- /dev/null +++ b/mk/Makefile_project.template @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = # VALUE, absolute or relative path : example ../.. # + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/mk/aversive_module.mk b/mk/aversive_module.mk new file mode 100644 index 0000000..9bc8a60 --- /dev/null +++ b/mk/aversive_module.mk @@ -0,0 +1,75 @@ +# Microb Technology, Eirbot, Droids-corp 2005 - Zer0 +# Makefile for projects +# +# Inspired by the WinAVR Sample makefile written by Eric +# B. Weddington, J÷rg Wunsch, et al. +# + +MSG_COMPILING = Compiling: +MSG_PREPROC = Preprocessing: + +# default HOST is avr +ifeq ($(H),) +HOST=avr +else +HOST=host +endif + +OBJ = $(addprefix compiler_files/,$(SRC:.c=.$(HOST).o) $(ASRC:.S=.$(HOST).o)) +LST = $(OBJ:.o=.lst) +DEPS = $(addprefix compiler_files/,$(SRC:.c=.$(HOST).d)) +ifneq ($(P),) +PREPROC= $(addprefix compiler_files/,$(SRC:.c=.$(HOST).preproc)) +else +PREPROC= +endif + +# Default target. +all: compiler_files/$(TARGET).$(HOST).a + +# Module library file +compiler_files/$(TARGET).$(HOST).a: $(PREPROC) $(OBJ) + ${AR} rs $@ $(OBJ) 2>&1 + +# Automatically generate C source code dependencies. +compiler_files/%.$(HOST).d : %.c + @echo Generating $@ + @set -e; rm -f $@; \ + $(CC) -M $(CFLAGS) $< > $@.$$$$; \ + sed 's,\($*\)\.o[ :]*,compiler_files/\1.$(HOST).o $@ : ,g' < $@.$$$$ > $@; \ + rm -f $@.$$$$ + +compiler_files/%.$(HOST).o : %.c + @echo $(MSG_COMPILING) $< + $(CC) $(CFLAGS) $< -c -o $@ + +compiler_files/%.$(HOST).preproc : %.c + @echo $(MSG_PREPROC) $< + $(CC) $(CFLAGS) $< -E -o $@ + +# Compile: create assembler files from C source files. +compiler_files/%.$(HOST).s : %.c + $(CC) -S $(CFLAGS) $< -o $@ + +# Assemble: create object files from assembler source files. +compiler_files/%.$(HOST).o : %.S + $(CC) -c -Wa,-adhlns=$(@:.o=.lst) $(ASFLAGS) $< -o $@ + + +# Remove the '-' if you want to see the dependency files generated. +ifeq (,$(findstring clean,$(MAKECMDGOALS))) +-include $(DEPS) +endif + +# Clean all objects +clean: + $(REMOVE) compiler_files/$(TARGET).$(HOST).a + $(REMOVE) $(OBJ) + $(REMOVE) $(LST) + $(REMOVE) $(PREPROC) + +depclean: + $(REMOVE) $(DEPS) + +# Listing of phony targets. +.PHONY : all clean deps diff --git a/mk/aversive_project.mk b/mk/aversive_project.mk new file mode 100644 index 0000000..cf9c938 --- /dev/null +++ b/mk/aversive_project.mk @@ -0,0 +1,509 @@ +# Microb Technology, Eirbot, Droids-corp 2007 - Zer0 +# Makefile for projects +# +# Inspired by the WinAVR Sample makefile written by Eric +# B. Weddington, J÷rg Wunsch, et al. +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device, using avrdude/avarice. Please +# customize the settings below first! +# +# make filename.s = Just compile filename.c into the assembler code only +# +# To rebuild project do "make clean" then "make all". +# + +# default HOST is avr +ifeq ($(H),) +export HOST=avr +else +export HOST=host +endif + +# absolute path to avoid some editors from beeing confused with vpath when +# searching files +ABS_AVERSIVE_DIR:=$(shell cd $(AVERSIVE_DIR) ; pwd) +ABS_PROJECT_DIR:=$(shell pwd) + +# includes for modules +MODULES_INC = $(addprefix $(ABS_AVERSIVE_DIR)/modules/,$(MODULES)) + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS += . $(ABS_AVERSIVE_DIR)/include $(ABS_AVERSIVE_DIR)/modules $(MODULES_INC) +# base/utils, base/wait and base/list are deprecated dirs, we need them for compatibility +EXTRAINCDIRS += $(ABS_AVERSIVE_DIR)/modules/base/utils +EXTRAINCDIRS += $(ABS_AVERSIVE_DIR)/modules/base/wait +EXTRAINCDIRS += $(ABS_AVERSIVE_DIR)/modules/base/list + + +# Optional compiler flags. +# -g: generate debugging information +# -O*: optimization level +# -f...: tuning, see gcc manual and avr-libc documentation +# -Wall...: warning level +CFLAGS += -g +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wstrict-prototypes +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += -std=gnu99 + +# specific arch flags +ifeq ($(HOST),avr) +CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums -mmcu=$(MCU) +else +CFLAGS += -DHOST_VERSION +endif + + +ALL_CFLAGS += $(CFLAGS) +# specific arch flags +ifeq ($(HOST),avr) +# Combine all necessary flags and optional flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create assembler listing +ALL_CFLAGS += -Wa,-adhlns=$(addprefix compiler_files/,$(<:.c=.$(HOST).lst)) +else +ALL_CFLAGS += +endif + + + +#common asflags +ASFLAGS += + +ifeq ($(HOST),avr) +# Optional assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create listing +# -gstabs: have the assembler create line number information +ASFLAGS += -mmcu=$(MCU) $(patsubst %,-I%,$(EXTRAINCDIRS)) +ASFLAGS += -Wa,-gstabs +ASFLAGS += -x assembler-with-cpp +else +ASFLAGS += +endif + + + + +# Optional linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +# Some variables are generated by config, see in .aversive_conf +ifeq ($(HOST),avr) +LDFLAGS += -mmcu=$(MCU) $(PRINTF_LDFLAGS) +LDFLAGS += -Wl,-Map=$(addprefix compiler_files/,$(TARGET).map),--cref +else +LDFLAGS += +endif + +LDFLAGS += $(MATH_LIB) + + +# AVRDUDE does not know the ATMEGA1281 for now, consider it a 128. +ifeq ($(MCU),atmega1281) +AVRDUDE_MCU = atmega128 +else +AVRDUDE_MCU = $(MCU) +endif + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).$(FORMAT_EXTENSION) +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + +# Optional AVRDUDE flags can be added in the makefile of the project +# (to adjust the baud rate, ...) +AVRDUDE_FLAGS_OPT += + +AVRDUDE_FLAGS = -p $(AVRDUDE_MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) $(AVRDUDE_FLAGS_OPT) + +ifneq ($(AVRDUDE_DELAY),) +AVRDUDE_FLAGS += -i $(AVRDUDE_DELAY) +endif + +export AVRDUDE_FLAGS + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE += -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_FLAGS += -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See <http://savannah.nongnu.org/projects/avrdude> +# to submit bug reports. +#AVRDUDE_FLAGS += -v -v + + +# Sets the baudrate. Comment this if you want to have the default baudrate +AVRDUDE_FLAGS += -b $(AVRDUDE_BAUDRATE) + +AVARICE_WRITE_FLASH = --erase --program --file $(TARGET).$(FORMAT_EXTENSION) +#AVARICE_WRITE_EEPROM = XXX + +export AVARICE_FLAGS = -P $(MCU) --jtag $(AVARICE_PORT) --$(AVARICE_PROGRAMMER) + + +# --------------------------------------------------------------------------- + + +# Define programs and commands. +ifeq ($(HOST),avr) +export CC = avr-gcc +export AS = avr-as +export AR = avr-ar +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size +NM = avr-nm +OUTPUT = $(TARGET).elf +OTHER_OUTPUT = $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep compiler_files/$(TARGET).lss compiler_files/$(TARGET).sym +else +export CC = gcc +export AS = as +export AR = ar +OBJCOPY = objcopy +OBJDUMP = objdump +SIZE = size --format=Berkeley +NM = nm +OUTPUT = $(TARGET) +endif +export HOSTCC = gcc +export REMOVE = rm -f +export COPY = cp +export SHELL = bash +DATE=`date` +MD5 = md5sum +export AVRDUDE = avrdude +export AVARICE = avarice +HEXSIZE = $(SIZE) --target=$(FORMAT) $(OUTPUT) +ELFSIZE = $(SIZE) $(OUTPUT) +ELFMD5 = $(MD5) $(OUTPUT) | cut -b1-4 +export AVRDUDE_PORT +export AVRDUDE_PROGRAMMER +export MCU +export PROGRAMMER + + + +# --------------------------------------------------------------------------- + + +# Define Messages +# English +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling: +MSG_PREPROC = Preprocessing: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: +MSG_MD5_BEFORE = Processing MD5: +MSG_MD5_AFTER = Processing MD5: +MSG_DEPCLEAN = Cleaning deps: +MSG_MODULE = ------ Compiling Module: + + +# --------------------------------------------------------------------------- + +OBJ = $(addprefix compiler_files/,$(SRC:.c=.$(HOST).o) $(ASRC:.S=.$(HOST).o)) +DEPS = $(addprefix compiler_files/,$(SRC:.c=.$(HOST).d)) +LST = $(OBJ:.o=.lst) +MODULES_LIB = $(addprefix compiler_files/,$(notdir $(MODULES:=.$(HOST).a))) +ifneq ($(P),) +PREPROC= $(addprefix compiler_files/,$(SRC:.c=.$(HOST).preproc)) +else +PREPROC= +endif + +# Variables n{\'e}cessaires pour les Makefile des modules +export AVERSIVE_DIR ABS_AVERSIVE_DIR +export CFLAGS EXTRAINCDIRS + + +# Default target. +all: compiler_files gccversion sizebefore md5sumbefore modules $(OUTPUT) $(OTHER_OUTPUT) sizeafter md5sumafter + +# only compile project files +project: compiler_files gccversion sizebefore md5sumbefore $(OUTPUT) $(OTHER_OUTPUT) sizeafter md5sumafter + +compiler_files: + @mkdir -p compiler_files + + +# ------ Compilation/link/assemble targets + +# Compile modules and create a library for each +modules: $(MODULES) + + +$(MODULES): + @echo + @echo $(MSG_MODULE) $@ + @$(MAKE) VPATH=$(ABS_AVERSIVE_DIR)/modules/$@ -f $(AVERSIVE_DIR)/modules/$@/Makefile + +# Link: create ELF output file from object files. +$(OUTPUT): $(PREPROC) $(OBJ) $(MODULES_LIB) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(OBJ) $(MODULES_LIB) --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +compiler_files/%.$(HOST).preproc : %.c + @echo + @echo $(MSG_PREPROC) $< + $(CC) -E $(ALL_CFLAGS) $< -o $@ + +# Compile: create object files from C source files. +compiler_files/%.$(HOST).o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $(ABS_PROJECT_DIR)/$< -o $@ + + +# Compile: create assembler files from C source files. +compiler_files/%.$(HOST).s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +compiler_files/%.$(HOST).o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ASFLAGS) $< -o $@ + + + +# ------ Conversion/listings targets + +# Create final output files (.hex, .eep) from ELF output file. +%.$(FORMAT_EXTENSION): %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 -O $(FORMAT) $< $@ + +# Create extended listing file from ELF output file. +compiler_files/%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +compiler_files/%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# ------ utils targets + +# Display size/md5 of file. +sizebefore: + @if [ -f $(OUTPUT) ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(OUTPUT) ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + +md5sumbefore: + @if [ -f $(OUTPUT) ]; then echo; echo $(MSG_MD5_BEFORE); $(ELFMD5); echo; fi + +md5sumafter: + @if [ -f $(OUTPUT) ]; then echo; echo $(MSG_MD5_AFTER); $(ELFMD5); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + +# Program the device. +program: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + @if [ "$(PROGRAMMER)" = "avrdude" ]; then \ + echo $(AVRDUDE) -e $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -e $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) $(AVRDUDE_FLAGS_SIGNATURE_CHECK) ;\ + fi + @if [ "$(PROGRAMMER)" = "avarice" ]; then \ + echo $(AVARICE) $(AVARICE_FLAGS) $(AVARICE_WRITE_FLASH) $(AVARICE_WRITE_EEPROM) ;\ + $(AVARICE) $(AVARICE_FLAGS) $(AVARICE_WRITE_FLASH) $(AVARICE_WRITE_EEPROM) ;\ + fi + +# Program the device. +erase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + @if [ "$(PROGRAMMER)" = "avrdude" ]; then \ + echo $(AVRDUDE) $(AVRDUDE_FLAGS) -e ;\ + $(AVRDUDE) $(AVRDUDE_FLAGS) -e ;\ + fi + @if [ "$(PROGRAMMER)" = "avarice" ]; then \ + echo "Not supported now." ; \ + fi + +# reset the device. +reset: + @if [ "$(PROGRAMMER)" = "avrdude" ]; then \ + echo $(AVRDUDE) $(AVRDUDE_FLAGS) ;\ + $(AVRDUDE) $(AVRDUDE_FLAGS) ;\ + fi + @if [ "$(PROGRAMMER)" = "avarice" ]; then \ + echo "Not supported now." ; \ + fi + +debug: $(TARGET).$(FORMAT_EXTENSION) + @if [ "$(PROGRAMMER)" = "avrdude" ]; then \ + echo "Cannot debug with avrdude" ; \ + fi + @if [ "$(PROGRAMMER)" = "avarice" ]; then \ + echo $(AVARICE) $(AVARICE_FLAGS) :$(AVARICE_DEBUG_PORT) ;\ + $(AVARICE) $(AVARICE_FLAGS) :$(AVARICE_DEBUG_PORT) ;\ + fi + +fuse: + @$(AVERSIVE_DIR)/config/prog_fuses.sh $(AVERSIVE_DIR)/config/fuses_defs/$(MCU) + + +# ------ config targets + +config: + @${SHELL} -n $(AVERSIVE_DIR)/config/config.in + @HELP_FILE=$(AVERSIVE_DIR)/config/Configure.help \ + AUTOCONF_FILE=autoconf.h \ + ${SHELL} $(AVERSIVE_DIR)/config/scripts/Configure $(AVERSIVE_DIR)/config/config.in + +noconfig: + @${SHELL} -n $(AVERSIVE_DIR)/config/config.in + @HELP_FILE=$(AVERSIVE_DIR)/config/Configure.help \ + AUTOCONF_FILE=autoconf.h \ + ${SHELL} $(AVERSIVE_DIR)/config/scripts/Configure -d $(AVERSIVE_DIR)/config/config.in + +menuconfig: + @${SHELL} -n $(AVERSIVE_DIR)/config/config.in + @make -C $(AVERSIVE_DIR)/config/scripts/lxdialog all + @HELP_FILE=$(AVERSIVE_DIR)/config/Configure.help \ + AUTOCONF_FILE=autoconf.h \ + ${SHELL} $(AVERSIVE_DIR)/config/scripts/Menuconfig $(AVERSIVE_DIR)/config/config.in + +# ------ clean targets + +mrproper: clean_list + $(REMOVE) compiler_files/* + + +clean: depclean clean_list modules_clean + + +# clean modules files +modules_clean: $(patsubst %,%_clean,$(MODULES)) + + +$(patsubst %,%_clean,$(MODULES)): + @$(MAKE) VPATH=$(ABS_AVERSIVE_DIR)/modules/$(@:_clean=) -f $(ABS_AVERSIVE_DIR)/modules/$(@:_clean=)/Makefile clean + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(OUTPUT) $(OTHER_OUTPUT) + $(REMOVE) compiler_files/$(TARGET).map + $(REMOVE) $(OBJ) + $(REMOVE) $(PREPROC) + $(REMOVE) $(LST) + + + + +# ------ dependencies targets + +depclean: dep_list modules_depclean + + +modules_depclean: $(patsubst %,%_depclean,$(MODULES)) + + +$(patsubst %,%_depclean,$(MODULES)): + @$(MAKE) VPATH=$(ABS_AVERSIVE_DIR)/modules/$(@:_depclean=) -f $(ABS_AVERSIVE_DIR)/modules/$(@:_depclean=)/Makefile depclean + + +dep_list: + @echo + @echo $(MSG_DEPCLEAN) + $(REMOVE) $(DEPS) + + +# Automatically generate C source code dependencies. +compiler_files/%.$(HOST).d: %.c + @mkdir -p compiler_files ; \ + error=0; \ + for conf_file in .config autoconf.h .aversive_conf; do \ + if [ ! -f $$conf_file ]; then \ + echo "$$conf_file file is missing"; \ + error=1; \ + fi ; \ + done; \ + for module in `echo $(MODULES)`; do \ + conf=`basename $$module"_config.h"`; \ + if [ -f $$module/config/$$conf ]; then \ + if [ ! -f $$conf ]; then \ + echo "$$conf file is missing"; \ + error=1; \ + fi ; \ + fi ; \ + done; \ + if [ $$error -eq 1 ]; then \ + echo "Missing config files, please run make menuconfig or make config"; \ + exit 1; \ + fi + @echo Generating $@ + @set -e; rm -f $@; \ + $(CC) -M $(CFLAGS) $< > $@.$$$$; \ + sed 's,\($*\)\.o[ :]*,compiler_files/\1.$(HOST).o $@ : ,g' < $@.$$$$ > $@; \ + rm -f $@.$$$$ + + + +# include the deps file only for other targets than menuconfig or config +ifeq (,$(findstring config,$(MAKECMDGOALS))) +ifeq (,$(wildcard .config)) +$(error You need to call make config or make menuconfig first) +endif +ifeq (,$(wildcard autoconf.h)) +$(error Missing autoconf.h -- You need to call make noconfig) +endif +ifeq (,$(wildcard .aversive_conf)) +$(error Missing .aversive_conf -- You need to call make noconfig) +endif + +ifeq (,$(findstring mrproper,$(MAKECMDGOALS))) +-include $(addprefix compiler_files/,$(SRC:.c=.$(HOST).d)) +endif +else +ifneq (1,$(words $(MAKECMDGOALS))) +$(error You need to call make config or make menuconfig without other targets) +endif +endif + + +# ------ Listing of phony targets. + +.PHONY : all sizebefore sizeafter gccversion \ + clean clean_list program md5sumafter md5sumbefore \ + depclean dep_list modules $(MODULES) \ + menuconfig config + diff --git a/modules/CVS/Entries b/modules/CVS/Entries new file mode 100644 index 0000000..3f5fba3 --- /dev/null +++ b/modules/CVS/Entries @@ -0,0 +1,8 @@ +D/base//// +D/comm//// +D/crypto//// +D/debug//// +D/devices//// +D/encoding//// +D/hardware//// +D/ihm//// diff --git a/modules/CVS/Repository b/modules/CVS/Repository new file mode 100644 index 0000000..3b300ae --- /dev/null +++ b/modules/CVS/Repository @@ -0,0 +1 @@ +aversive/modules diff --git a/modules/CVS/Root b/modules/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/CVS/Tag b/modules/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/CVS/Template b/modules/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/CVS/Entries b/modules/base/CVS/Entries new file mode 100644 index 0000000..f063098 --- /dev/null +++ b/modules/base/CVS/Entries @@ -0,0 +1,8 @@ +D/cirbuf//// +D/list//// +D/math//// +D/scheduler//// +D/time//// +D/time_ext//// +D/utils//// +D/wait//// diff --git a/modules/base/CVS/Repository b/modules/base/CVS/Repository new file mode 100644 index 0000000..27e6015 --- /dev/null +++ b/modules/base/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base diff --git a/modules/base/CVS/Root b/modules/base/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/CVS/Tag b/modules/base/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/CVS/Template b/modules/base/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/cirbuf/CVS/Entries b/modules/base/cirbuf/CVS/Entries new file mode 100644 index 0000000..5274201 --- /dev/null +++ b/modules/base/cirbuf/CVS/Entries @@ -0,0 +1,17 @@ +/Makefile/1.1.2.2/Thu Sep 6 08:12:03 2007//Tb_zer0 +/cirbuf.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf.h/1.1.2.5/Sat Jan 3 16:24:50 2009//Tb_zer0 +/cirbuf_add_buf_head.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_add_buf_tail.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_add_head.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_add_tail.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_align.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_del_buf_head.c/1.1.2.3/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_del_buf_tail.c/1.1.2.3/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_del_head.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_del_tail.c/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_get_buf_head.c/1.1.2.3/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_get_buf_tail.c/1.1.2.3/Wed Sep 12 17:52:20 2007//Tb_zer0 +/cirbuf_get_head.c/1.1.2.1/Sun Aug 19 10:33:55 2007//Tb_zer0 +/cirbuf_get_tail.c/1.1.2.1/Sun Aug 19 10:33:55 2007//Tb_zer0 +D/test//// diff --git a/modules/base/cirbuf/CVS/Repository b/modules/base/cirbuf/CVS/Repository new file mode 100644 index 0000000..e81240b --- /dev/null +++ b/modules/base/cirbuf/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/cirbuf diff --git a/modules/base/cirbuf/CVS/Root b/modules/base/cirbuf/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/cirbuf/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/cirbuf/CVS/Tag b/modules/base/cirbuf/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/cirbuf/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/cirbuf/CVS/Template b/modules/base/cirbuf/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/cirbuf/Makefile b/modules/base/cirbuf/Makefile new file mode 100644 index 0000000..361ceb2 --- /dev/null +++ b/modules/base/cirbuf/Makefile @@ -0,0 +1,12 @@ +TARGET = cirbuf + +SRC = cirbuf_add_buf_head.c cirbuf_add_head.c cirbuf.c +SRC += cirbuf_del_buf_tail.c cirbuf_del_tail.c cirbuf_get_buf_tail.c +SRC += cirbuf_get_tail.c cirbuf_add_buf_tail.c cirbuf_add_tail.c +SRC += cirbuf_del_buf_head.c cirbuf_del_head.c cirbuf_get_buf_head.c +SRC += cirbuf_get_head.c cirbuf_align.c + + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/cirbuf/cirbuf.c b/modules/base/cirbuf/cirbuf.c new file mode 100644 index 0000000..fb1816e --- /dev/null +++ b/modules/base/cirbuf/cirbuf.c @@ -0,0 +1,37 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + + +void +cirbuf_init(struct cirbuf * cbuf, char * buf, cirbuf_uint start, cirbuf_uint maxlen) +{ + cbuf->maxlen = maxlen; + cbuf->len = 0; + cbuf->start = start; + cbuf->end = start; + cbuf->buf = buf; +} + diff --git a/modules/base/cirbuf/cirbuf.h b/modules/base/cirbuf/cirbuf.h new file mode 100644 index 0000000..ad16a8f --- /dev/null +++ b/modules/base/cirbuf/cirbuf.h @@ -0,0 +1,223 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf.h,v 1.1.2.5 2009-01-03 16:24:50 zer0 Exp $ + * + * + */ + +/** + * Circular buffer implementation. You should not use a circular buffer + * size > 127. + * + * Funcs are not atomic, so if * necessary, each call should be + * protected by IRQ_LOCKs. + */ + + +#ifndef _CIRBUF_H_ +#define _CIRBUF_H_ + +#include <aversive.h> +#include <stdio.h> + +#ifdef CONFIG_MODULE_CIRBUF_LARGE +typedef signed int cirbuf_int; +typedef unsigned int cirbuf_uint; +#else +typedef signed char cirbuf_int; +typedef unsigned char cirbuf_uint; +#endif + +/** + * This structure is the header of a cirbuf type. + */ +struct cirbuf { + cirbuf_uint maxlen; /**< total len of the fifo (number of elements) */ + volatile cirbuf_uint start; /**< indice of the first elt */ + volatile cirbuf_uint end; /**< indice of the last elt */ + volatile cirbuf_uint len; /**< current len of fifo */ + char *buf; +}; + +/* #define CIRBUF_DEBUG */ + +#ifdef CIRBUF_DEBUG +#define dprintf(fmt, ...) printf("line %3.3d - " fmt, __LINE__, ##__VA_ARGS__) +#else +#define dprintf(args...) do {} while(0) +#endif + + +/** + * Init the circular buffer + */ +void cirbuf_init(struct cirbuf *cbuf, char *buf, cirbuf_uint start, cirbuf_uint maxlen); + + +/** + * Return 1 if the circular buffer is full + */ +#define CIRBUF_IS_FULL(cirbuf) ((cirbuf)->maxlen == (cirbuf)->len) + +/** + * Return 1 if the circular buffer is empty + */ +#define CIRBUF_IS_EMPTY(cirbuf) ((cirbuf)->len == 0) + +/** + * return current size of the circular buffer (number of used elements) + */ +#define CIRBUF_GET_LEN(cirbuf) ((cirbuf)->len) + +/** + * return size of the circular buffer (used + free elements) + */ +#define CIRBUF_GET_MAXLEN(cirbuf) ((cirbuf)->maxlen) + +/** + * return the number of free elts + */ +#define CIRBUF_GET_FREELEN(cirbuf) ((cirbuf)->maxlen - (cirbuf)->len) + +/** + * Iterator for a circular buffer + * c: struct cirbuf pointer + * i: an integer type (cirbuf_uint is enough) internally used in the macro + * e: char that takes the value for each iteration + */ +#define CIRBUF_FOREACH(c, i, e) \ + for ( i=0, e=(c)->buf[(c)->start] ; \ + i<((c)->len) ; \ + i ++, e=(c)->buf[((c)->start+i)%((c)->maxlen)]) + + +/** + * Add a character at head of the circular buffer. Return 0 on success, or + * a negative value on error. + */ +cirbuf_int cirbuf_add_head_safe(struct cirbuf *cbuf, char c); + +/** + * Add a character at head of the circular buffer. You _must_ check that you + * have enough free space in the buffer before calling this func. + */ +void cirbuf_add_head(struct cirbuf *cbuf, char c); + +/** + * Add a character at tail of the circular buffer. Return 0 on success, or + * a negative value on error. + */ +cirbuf_int cirbuf_add_tail_safe(struct cirbuf *cbuf, char c); + +/** + * Add a character at tail of the circular buffer. You _must_ check that you + * have enough free space in the buffer before calling this func. + */ +void cirbuf_add_tail(struct cirbuf *cbuf, char c); + +/** + * Remove a char at the head of the circular buffer. Return 0 on + * success, or a negative value on error. + */ +cirbuf_int cirbuf_del_head_safe(struct cirbuf *cbuf); + +/** + * Remove a char at the head of the circular buffer. You _must_ check + * that buffer is not empty before calling the function. + */ +void cirbuf_del_head(struct cirbuf *cbuf); + +/** + * Remove a char at the tail of the circular buffer. Return 0 on + * success, or a negative value on error. + */ +cirbuf_int cirbuf_del_tail_safe(struct cirbuf *cbuf); + +/** + * Remove a char at the tail of the circular buffer. You _must_ check + * that buffer is not empty before calling the function. + */ +void cirbuf_del_tail(struct cirbuf *cbuf); + +/** + * Return the head of the circular buffer. You _must_ check that + * buffer is not empty before calling the function. + */ +char cirbuf_get_head(struct cirbuf *cbuf); + +/** + * Return the tail of the circular buffer. You _must_ check that + * buffer is not empty before calling the function. + */ +char cirbuf_get_tail(struct cirbuf *cbuf); + + + +/** + * Add a buffer at head of the circular buffer. 'c' is a pointer to a + * buffer, and n is the number of char to add. Return the number of + * copied bytes on success, or a negative value on error. + */ +cirbuf_int cirbuf_add_buf_head(struct cirbuf *cbuf, const char *c, cirbuf_uint n); + +/** + * Add a buffer at tail of the circular buffer. 'c' is a pointer to a + * buffer, and n is the number of char to add. Return the number of + * copied bytes on success, or a negative value on error. + */ +cirbuf_int cirbuf_add_buf_tail(struct cirbuf *cbuf, const char *c, cirbuf_uint n); + +/** + * Remove chars at the head of the circular buffer. Return 0 on + * success, or a negative value on error. + */ +cirbuf_int cirbuf_del_buf_head(struct cirbuf *cbuf, cirbuf_uint size); + +/** + * Remove chars at the tail of the circular buffer. Return 0 on + * success, or a negative value on error. + */ +cirbuf_int cirbuf_del_buf_tail(struct cirbuf *cbuf, cirbuf_uint size); + +/** + * Copy a maximum of 'size' characters from the head of the circular + * buffer to a flat one pointed by 'c'. Return the number of copied + * chars. + */ +cirbuf_int cirbuf_get_buf_head(struct cirbuf *cbuf, char *c, cirbuf_uint size); + +/** + * Copy a maximum of 'size' characters from the tail of the circular + * buffer to a flat one pointed by 'c'. Return the number of copied + * chars. + */ +cirbuf_int cirbuf_get_buf_tail(struct cirbuf *cbuf, char *c, cirbuf_uint size); + + +/** + * Set the start of the data to the index 0 of the internal buffer. + */ +void cirbuf_align_left(struct cirbuf *cbuf); + +/** + * Set the end of the data to the last index of the internal buffer. + */ +void cirbuf_align_right(struct cirbuf *cbuf); + +#endif /* _CIRBUF_H_ */ diff --git a/modules/base/cirbuf/cirbuf_add_buf_head.c b/modules/base/cirbuf/cirbuf_add_buf_head.c new file mode 100644 index 0000000..c4eb595 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_add_buf_head.c @@ -0,0 +1,55 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_add_buf_head.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + + +/* multiple add */ + +cirbuf_int +cirbuf_add_buf_head(struct cirbuf * cbuf, const char * c, cirbuf_uint n) +{ + cirbuf_uint e; + + if (!n || n > CIRBUF_GET_FREELEN(cbuf)) + return -EINVAL; + + e = CIRBUF_IS_EMPTY(cbuf) ? 1 : 0; + + if (n < cbuf->start + e) { + dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->start - n + e, n); + memcpy(cbuf->buf + cbuf->start - n + e, c, n); + } + else { + dprintf("s[%d] -> d[%d] (%d)\n", + n - (cbuf->start + e), 0, cbuf->start + e); + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->maxlen - n + (cbuf->start + e), 0, n - (cbuf->start + e)); + memcpy(cbuf->buf, c + n - (cbuf->start + e) , cbuf->start + e); + memcpy(cbuf->buf + cbuf->maxlen - n + (cbuf->start + e), c, n - (cbuf->start + e)); + } + cbuf->len += n; + cbuf->start += (cbuf->maxlen - n + e); + cbuf->start %= cbuf->maxlen; + return n; +} + diff --git a/modules/base/cirbuf/cirbuf_add_buf_tail.c b/modules/base/cirbuf/cirbuf_add_buf_tail.c new file mode 100644 index 0000000..d301b3e --- /dev/null +++ b/modules/base/cirbuf/cirbuf_add_buf_tail.c @@ -0,0 +1,55 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_add_buf_tail.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + + +/* multiple add */ + +cirbuf_int +cirbuf_add_buf_tail(struct cirbuf * cbuf, const char * c, cirbuf_uint n) +{ + cirbuf_uint e; + + if (!n || n > CIRBUF_GET_FREELEN(cbuf)) + return -EINVAL; + + e = CIRBUF_IS_EMPTY(cbuf) ? 1 : 0; + + if (n < cbuf->maxlen - cbuf->end - 1 + e) { + dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->end + !e, n); + memcpy(cbuf->buf + cbuf->end + !e, c, n); + } + else { + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->end + !e, 0, cbuf->maxlen - cbuf->end - 1 + e); + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->maxlen - cbuf->end - 1 + e, 0, n - cbuf->maxlen + cbuf->end + 1 - e); + memcpy(cbuf->buf + cbuf->end + !e, c, cbuf->maxlen - cbuf->end - 1 + e); + memcpy(cbuf->buf, c + cbuf->maxlen - cbuf->end - 1 + e, n - cbuf->maxlen + cbuf->end + 1 - e); + } + cbuf->len += n; + cbuf->end += n - e; + cbuf->end %= cbuf->maxlen; + return n; +} + diff --git a/modules/base/cirbuf/cirbuf_add_head.c b/modules/base/cirbuf/cirbuf_add_head.c new file mode 100644 index 0000000..f093e85 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_add_head.c @@ -0,0 +1,56 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_add_head.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + + +/* add at head */ + +static inline void +__cirbuf_add_head(struct cirbuf * cbuf, char c) +{ + if (!CIRBUF_IS_EMPTY(cbuf)) { + cbuf->start += (cbuf->maxlen - 1); + cbuf->start %= cbuf->maxlen; + } + cbuf->buf[cbuf->start] = c; + cbuf->len ++; +} + +cirbuf_int +cirbuf_add_head_safe(struct cirbuf * cbuf, char c) +{ + if (cbuf && !CIRBUF_IS_FULL(cbuf)) { + __cirbuf_add_head(cbuf, c); + return 0; + } + return -EINVAL; +} + +void +cirbuf_add_head(struct cirbuf * cbuf, char c) +{ + __cirbuf_add_head(cbuf, c); +} + diff --git a/modules/base/cirbuf/cirbuf_add_tail.c b/modules/base/cirbuf/cirbuf_add_tail.c new file mode 100644 index 0000000..4e55313 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_add_tail.c @@ -0,0 +1,58 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_add_tail.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + + +/* add at tail */ + + +static inline void +__cirbuf_add_tail(struct cirbuf * cbuf, char c) +{ + if (!CIRBUF_IS_EMPTY(cbuf)) { + cbuf->end ++; + cbuf->end %= cbuf->maxlen; + } + cbuf->buf[cbuf->end] = c; + cbuf->len ++; +} + +cirbuf_int +cirbuf_add_tail_safe(struct cirbuf * cbuf, char c) +{ + if (cbuf && !CIRBUF_IS_FULL(cbuf)) { + __cirbuf_add_tail(cbuf, c); + return 0; + } + return -EINVAL; +} + +void +cirbuf_add_tail(struct cirbuf * cbuf, char c) +{ + __cirbuf_add_tail(cbuf, c); +} + + diff --git a/modules/base/cirbuf/cirbuf_align.c b/modules/base/cirbuf/cirbuf_align.c new file mode 100644 index 0000000..3ebfe57 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_align.c @@ -0,0 +1,90 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_align.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +static inline void +__cirbuf_shift_left(struct cirbuf * cbuf) +{ + cirbuf_uint i; + char tmp = cbuf->buf[cbuf->start]; + + for (i=0 ; i<cbuf->len ; i++) { + cbuf->buf[(cbuf->start+i)%cbuf->maxlen] = + cbuf->buf[(cbuf->start+i+1)%cbuf->maxlen]; + } + cbuf->buf[(cbuf->start-1+cbuf->maxlen)%cbuf->maxlen] = tmp; + cbuf->start += (cbuf->maxlen - 1); + cbuf->start %= cbuf->maxlen; + cbuf->end += (cbuf->maxlen - 1); + cbuf->end %= cbuf->maxlen; +} + +static inline void +__cirbuf_shift_right(struct cirbuf * cbuf) +{ + cirbuf_uint i; + char tmp = cbuf->buf[cbuf->end]; + + for (i=0 ; i<cbuf->len ; i++) { + cbuf->buf[(cbuf->end+cbuf->maxlen-i)%cbuf->maxlen] = + cbuf->buf[(cbuf->end+cbuf->maxlen-i-1)%cbuf->maxlen]; + } + cbuf->buf[(cbuf->end+1)%cbuf->maxlen] = tmp; + cbuf->start += 1; + cbuf->start %= cbuf->maxlen; + cbuf->end += 1; + cbuf->end %= cbuf->maxlen; +} + +/* XXX we could do a better algorithm here... */ +void cirbuf_align_left(struct cirbuf * cbuf) +{ + if (cbuf->start < cbuf->maxlen/2) { + while (cbuf->start != 0) { + __cirbuf_shift_left(cbuf); + } + } + else { + while (cbuf->start != 0) { + __cirbuf_shift_right(cbuf); + } + } +} + +/* XXX we could do a better algorithm here... */ +void cirbuf_align_right(struct cirbuf * cbuf) +{ + if (cbuf->start >= cbuf->maxlen/2) { + while (cbuf->end != cbuf->maxlen-1) { + __cirbuf_shift_left(cbuf); + } + } + else { + while (cbuf->start != cbuf->maxlen-1) { + __cirbuf_shift_right(cbuf); + } + } +} + diff --git a/modules/base/cirbuf/cirbuf_del_buf_head.c b/modules/base/cirbuf/cirbuf_del_buf_head.c new file mode 100644 index 0000000..df67d23 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_del_buf_head.c @@ -0,0 +1,45 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_del_buf_head.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* buffer del */ + +cirbuf_int +cirbuf_del_buf_head(struct cirbuf * cbuf, cirbuf_uint size) +{ + if (!size || size > CIRBUF_GET_LEN(cbuf)) + return -EINVAL; + + cbuf->len -= size; + if (CIRBUF_IS_EMPTY(cbuf)) { + cbuf->start += size - 1; + cbuf->start %= cbuf->maxlen; + } + else { + cbuf->start += size; + cbuf->start %= cbuf->maxlen; + } + return 0; +} diff --git a/modules/base/cirbuf/cirbuf_del_buf_tail.c b/modules/base/cirbuf/cirbuf_del_buf_tail.c new file mode 100644 index 0000000..159b853 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_del_buf_tail.c @@ -0,0 +1,45 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_del_buf_tail.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* buffer del */ + +cirbuf_int +cirbuf_del_buf_tail(struct cirbuf * cbuf, cirbuf_uint size) +{ + if (!size || size > CIRBUF_GET_LEN(cbuf)) + return -EINVAL; + + cbuf->len -= size; + if (CIRBUF_IS_EMPTY(cbuf)) { + cbuf->end += (cbuf->maxlen - size + 1); + cbuf->end %= cbuf->maxlen; + } + else { + cbuf->end += (cbuf->maxlen - size); + cbuf->end %= cbuf->maxlen; + } + return 0; +} diff --git a/modules/base/cirbuf/cirbuf_del_head.c b/modules/base/cirbuf/cirbuf_del_head.c new file mode 100644 index 0000000..7ebca5a --- /dev/null +++ b/modules/base/cirbuf/cirbuf_del_head.c @@ -0,0 +1,54 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_del_head.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* del at head */ + +static inline void +__cirbuf_del_head(struct cirbuf * cbuf) +{ + cbuf->len --; + if (!CIRBUF_IS_EMPTY(cbuf)) { + cbuf->start ++; + cbuf->start %= cbuf->maxlen; + } +} + +cirbuf_int +cirbuf_del_head_safe(struct cirbuf * cbuf) +{ + if (cbuf && !CIRBUF_IS_EMPTY(cbuf)) { + __cirbuf_del_head(cbuf); + return 0; + } + return -EINVAL; +} + +void +cirbuf_del_head(struct cirbuf * cbuf) +{ + __cirbuf_del_head(cbuf); +} + diff --git a/modules/base/cirbuf/cirbuf_del_tail.c b/modules/base/cirbuf/cirbuf_del_tail.c new file mode 100644 index 0000000..18cbe8a --- /dev/null +++ b/modules/base/cirbuf/cirbuf_del_tail.c @@ -0,0 +1,56 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_del_tail.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + + +/* del at tail */ + +static inline void +__cirbuf_del_tail(struct cirbuf * cbuf) +{ + cbuf->len --; + if (!CIRBUF_IS_EMPTY(cbuf)) { + cbuf->end += (cbuf->maxlen - 1); + cbuf->end %= cbuf->maxlen; + } +} + +cirbuf_int +cirbuf_del_tail_safe(struct cirbuf * cbuf) +{ + if (cbuf && !CIRBUF_IS_EMPTY(cbuf)) { + __cirbuf_del_tail(cbuf); + return 0; + } + return -EINVAL; +} + +void +cirbuf_del_tail(struct cirbuf * cbuf) +{ + __cirbuf_del_tail(cbuf); +} + + diff --git a/modules/base/cirbuf/cirbuf_get_buf_head.c b/modules/base/cirbuf/cirbuf_get_buf_head.c new file mode 100644 index 0000000..75bace8 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_get_buf_head.c @@ -0,0 +1,49 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_get_buf_head.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* convert to buffer */ + +cirbuf_int +cirbuf_get_buf_head(struct cirbuf * cbuf, char * c, cirbuf_uint size) +{ + cirbuf_uint n = (size < CIRBUF_GET_LEN(cbuf)) ? size : CIRBUF_GET_LEN(cbuf); + + if (!n) + return 0; + + if (cbuf->start <= cbuf->end) { + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->start, 0, n); + memcpy(c, cbuf->buf + cbuf->start , n); + } + else { + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->start, 0, cbuf->maxlen - cbuf->start); + dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->maxlen - cbuf->start, n - cbuf->maxlen + cbuf->start); + memcpy(c, cbuf->buf + cbuf->start , cbuf->maxlen - cbuf->start); + memcpy(c + cbuf->maxlen - cbuf->start, cbuf->buf, n - cbuf->maxlen + cbuf->start); + } + return n; +} + diff --git a/modules/base/cirbuf/cirbuf_get_buf_tail.c b/modules/base/cirbuf/cirbuf_get_buf_tail.c new file mode 100644 index 0000000..68b7eb3 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_get_buf_tail.c @@ -0,0 +1,51 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_get_buf_tail.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* convert to buffer */ + + +cirbuf_int +cirbuf_get_buf_tail(struct cirbuf * cbuf, char * c, cirbuf_uint size) +{ + cirbuf_uint n = (size < CIRBUF_GET_LEN(cbuf)) ? size : CIRBUF_GET_LEN(cbuf); + + if (!n) + return 0; + + if (cbuf->start <= cbuf->end) { + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->end - n + 1, 0, n); + memcpy(c, cbuf->buf + cbuf->end - n + 1, n); + } + else { + dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->maxlen - cbuf->start, cbuf->end + 1); + dprintf("s[%d] -> d[%d] (%d)\n", cbuf->maxlen - n + cbuf->end + 1, 0, n - cbuf->end - 1); + + memcpy(c + cbuf->maxlen - cbuf->start, cbuf->buf, cbuf->end + 1); + memcpy(c, cbuf->buf + cbuf->maxlen - n + cbuf->end +1, n - cbuf->end - 1); + } + return n; +} + diff --git a/modules/base/cirbuf/cirbuf_get_head.c b/modules/base/cirbuf/cirbuf_get_head.c new file mode 100644 index 0000000..9a1c200 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_get_head.c @@ -0,0 +1,34 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_get_head.c,v 1.1.2.1 2007-08-19 10:33:55 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* get head or get tail */ + +char +cirbuf_get_head(struct cirbuf * cbuf) +{ + return cbuf->buf[cbuf->start]; +} + diff --git a/modules/base/cirbuf/cirbuf_get_tail.c b/modules/base/cirbuf/cirbuf_get_tail.c new file mode 100644 index 0000000..c1a5a35 --- /dev/null +++ b/modules/base/cirbuf/cirbuf_get_tail.c @@ -0,0 +1,34 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cirbuf_get_tail.c,v 1.1.2.1 2007-08-19 10:33:55 zer0 Exp $ + * + */ + +#include <string.h> + +#include <cirbuf.h> + +/* get head or get tail */ + +char +cirbuf_get_tail(struct cirbuf * cbuf) +{ + return cbuf->buf[cbuf->end]; +} + diff --git a/modules/base/cirbuf/test/.config b/modules/base/cirbuf/test/.config new file mode 100644 index 0000000..0b21d50 --- /dev/null +++ b/modules/base/cirbuf/test/.config @@ -0,0 +1,212 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +CONFIG_MODULE_CIRBUF_LARGE=y +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/base/cirbuf/test/CVS/Entries b/modules/base/cirbuf/test/CVS/Entries new file mode 100644 index 0000000..c145fa5 --- /dev/null +++ b/modules/base/cirbuf/test/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.1.2.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/Makefile/1.1.2.1/Sun Aug 19 10:33:55 2007//Tb_zer0 +/error_config.h/1.1.2.1/Sun Aug 19 10:33:55 2007//Tb_zer0 +/main.c/1.1.2.1/Sun Aug 19 10:33:55 2007//Tb_zer0 +D diff --git a/modules/base/cirbuf/test/CVS/Repository b/modules/base/cirbuf/test/CVS/Repository new file mode 100644 index 0000000..622cc43 --- /dev/null +++ b/modules/base/cirbuf/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/cirbuf/test diff --git a/modules/base/cirbuf/test/CVS/Root b/modules/base/cirbuf/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/cirbuf/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/cirbuf/test/CVS/Tag b/modules/base/cirbuf/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/cirbuf/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/cirbuf/test/CVS/Template b/modules/base/cirbuf/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/cirbuf/test/Makefile b/modules/base/cirbuf/test/Makefile new file mode 100644 index 0000000..639fab0 --- /dev/null +++ b/modules/base/cirbuf/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/base/cirbuf/test/error_config.h b/modules/base/cirbuf/test/error_config.h new file mode 100644 index 0000000..447b9be --- /dev/null +++ b/modules/base/cirbuf/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-08-19 10:33:55 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/base/cirbuf/test/main.c b/modules/base/cirbuf/test/main.c new file mode 100644 index 0000000..98bc579 --- /dev/null +++ b/modules/base/cirbuf/test/main.c @@ -0,0 +1,225 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.1 2007-08-19 10:33:55 zer0 Exp $ + * + */ + +#include <aversive.h> + +#include <cirbuf.h> + +#include <stdio.h> +#include <string.h> + +#ifdef HOST_VERSION +#include <assert.h> +#else +#define assert(cond) do { if (!cond) { printf("%s:%d - %s", __FILE__, __LINE__, #cond); while(1); } } while(0) +#endif + +void dump_it(struct cirbuf * cbuf) +{ + int i; + char e; + + printf("sta=%2.2d end=%2.2d len=%2.2d/%2.2d { ", + cbuf->start, cbuf->end, + CIRBUF_GET_LEN(cbuf), + CIRBUF_GET_MAXLEN(cbuf)); + + for (i=0; i<CIRBUF_GET_MAXLEN(cbuf) ; i++) { + if (cbuf->start <= cbuf->end) { + if (i >= cbuf->start && + i <= cbuf->end && + CIRBUF_GET_LEN(cbuf) != 0) + printf("%2.2x, ", cbuf->buf[i]&0xFF); + else + printf("XX, "); + } + else { + if (i < cbuf->start && + i > cbuf->end) + printf("XX, "); + else + printf("%2.2x, ", cbuf->buf[i]&0xFF); + } + } + printf("} -> "); + + printf("[ "); + CIRBUF_FOREACH(cbuf, i, e) { + printf("%2.2x, ", e&0xFF); + } + printf("]\n"); + + if(CIRBUF_GET_LEN(cbuf) == 0) { + assert(cbuf->start == cbuf->end); + } + else { + assert( ((cbuf->end - cbuf->start + 1) + cbuf->maxlen) % cbuf->maxlen == + CIRBUF_GET_LEN(cbuf) % cbuf->maxlen ); + } + +} + +int main(void) +{ + uint8_t i; + struct cirbuf my_fifo; + char fifo_buf[16]; + + char buf1[] = { 0x10, 0x11, 0x12 }; + char buf2[] = { 0x20, 0x21, 0x22, 0x23 }; + + char tmp_buf[16]; + char ref_buf[] = { 0x20, 0x21, 0x22, 0x23, 0x01, 0x10, 0x11, 0x12 }; + + /* Test 1 */ + + printf("Test 1\n"); + + cirbuf_init(&my_fifo, fifo_buf, 0, 4); + assert(CIRBUF_IS_EMPTY(&my_fifo)); + assert(!CIRBUF_IS_FULL(&my_fifo)); + dump_it(&my_fifo); + + cirbuf_add_tail(&my_fifo, 1); + assert(cirbuf_get_head(&my_fifo) == 1); + assert(cirbuf_get_tail(&my_fifo) == 1); + dump_it(&my_fifo); + + + cirbuf_add_tail(&my_fifo, 2); + assert(!CIRBUF_IS_EMPTY(&my_fifo)); + assert(!CIRBUF_IS_FULL(&my_fifo)); + dump_it(&my_fifo); + + cirbuf_add_tail(&my_fifo, 3); + assert(cirbuf_get_head(&my_fifo) == 1); + assert(cirbuf_get_tail(&my_fifo) == 3); + dump_it(&my_fifo); + + cirbuf_add_tail(&my_fifo, 4); + assert(!CIRBUF_IS_EMPTY(&my_fifo)); + assert(CIRBUF_IS_FULL(&my_fifo)); + dump_it(&my_fifo); + + cirbuf_del_tail(&my_fifo); + dump_it(&my_fifo); + assert(cirbuf_get_tail(&my_fifo) == 3); + assert(cirbuf_get_head(&my_fifo) == 1); + + cirbuf_del_head(&my_fifo); + assert(cirbuf_get_tail(&my_fifo) == 3); + assert(cirbuf_get_head(&my_fifo) == 2); + dump_it(&my_fifo); + + cirbuf_del_head(&my_fifo); + assert(cirbuf_get_tail(&my_fifo) == 3); + assert(cirbuf_get_head(&my_fifo) == 3); + dump_it(&my_fifo); + + cirbuf_del_head(&my_fifo); + assert(CIRBUF_IS_EMPTY(&my_fifo)); + dump_it(&my_fifo); + + + /* Test 2 */ + + printf("Test 2\n"); + + cirbuf_init(&my_fifo, fifo_buf, 2, 4); + dump_it(&my_fifo); + + cirbuf_add_head(&my_fifo, 4); + assert(cirbuf_get_head(&my_fifo) == 4); + assert(cirbuf_get_tail(&my_fifo) == 4); + dump_it(&my_fifo); + + + cirbuf_add_head(&my_fifo, 3); + assert(!CIRBUF_IS_EMPTY(&my_fifo)); + assert(!CIRBUF_IS_FULL(&my_fifo)); + dump_it(&my_fifo); + + cirbuf_add_head(&my_fifo, 2); + assert(cirbuf_get_head(&my_fifo) == 2); + assert(cirbuf_get_tail(&my_fifo) == 4); + dump_it(&my_fifo); + + cirbuf_add_head(&my_fifo, 1); + assert(!CIRBUF_IS_EMPTY(&my_fifo)); + assert(CIRBUF_IS_FULL(&my_fifo)); + dump_it(&my_fifo); + + + /* Test 3 */ + + printf("Test 3\n"); + + for (i=0 ; i<16; i++) { + cirbuf_init(&my_fifo, fifo_buf, i, 16); + dump_it(&my_fifo); + cirbuf_add_buf_head(&my_fifo, buf1, sizeof(buf1)); + dump_it(&my_fifo); + cirbuf_add_head(&my_fifo, 1); + dump_it(&my_fifo); + cirbuf_add_buf_head(&my_fifo, buf2, sizeof(buf2)); + dump_it(&my_fifo); + cirbuf_get_buf_head(&my_fifo, tmp_buf, sizeof(tmp_buf)); + assert(memcmp(tmp_buf, ref_buf, sizeof(ref_buf)) == 0); + } + + /* Test 4 */ + + printf("Test 4\n"); + + for (i=0 ; i<16; i++) { + cirbuf_init(&my_fifo, fifo_buf, i, 16); + dump_it(&my_fifo); + cirbuf_add_buf_tail(&my_fifo, buf2, sizeof(buf2)); + dump_it(&my_fifo); + cirbuf_add_tail(&my_fifo, 1); + dump_it(&my_fifo); + cirbuf_add_buf_tail(&my_fifo, buf1, sizeof(buf1)); + dump_it(&my_fifo); + cirbuf_get_buf_tail(&my_fifo, tmp_buf, sizeof(tmp_buf)); + assert(memcmp(tmp_buf, ref_buf, sizeof(ref_buf)) == 0); + } + + /* Test 5 */ + + printf("Test 5\n"); + + cirbuf_init(&my_fifo, fifo_buf, 10, 16); + dump_it(&my_fifo); + i=0; + while (cirbuf_add_tail_safe(&my_fifo, i) == 0) + i++; + dump_it(&my_fifo); + cirbuf_del_buf_tail(&my_fifo, 10); + dump_it(&my_fifo); + assert(CIRBUF_GET_LEN(&my_fifo)==6); + assert(cirbuf_del_buf_tail(&my_fifo, 10) != 0); + assert(cirbuf_get_tail(&my_fifo) == 5); + assert(cirbuf_get_head(&my_fifo) == 0); + + + + return 0; +} diff --git a/modules/base/list/CVS/Entries b/modules/base/list/CVS/Entries new file mode 100644 index 0000000..e2bd02c --- /dev/null +++ b/modules/base/list/CVS/Entries @@ -0,0 +1,2 @@ +/list.h/1.14.4.4/Wed May 23 17:18:10 2007//Tb_zer0 +D diff --git a/modules/base/list/CVS/Repository b/modules/base/list/CVS/Repository new file mode 100644 index 0000000..882230f --- /dev/null +++ b/modules/base/list/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/list diff --git a/modules/base/list/CVS/Root b/modules/base/list/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/list/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/list/CVS/Tag b/modules/base/list/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/list/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/list/CVS/Template b/modules/base/list/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/list/list.h b/modules/base/list/list.h new file mode 100644 index 0000000..efb20a4 --- /dev/null +++ b/modules/base/list/list.h @@ -0,0 +1,24 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: list.h,v 1.14.4.4 2007-05-23 17:18:10 zer0 Exp $ + * + */ + +#warning "This include file is deprecated, please use <aversive/list.h>" + +#include <aversive/list.h> diff --git a/modules/base/math/CVS/Entries b/modules/base/math/CVS/Entries new file mode 100644 index 0000000..7013952 --- /dev/null +++ b/modules/base/math/CVS/Entries @@ -0,0 +1,3 @@ +D/fixed_point//// +D/geometry//// +D/vect2//// diff --git a/modules/base/math/CVS/Repository b/modules/base/math/CVS/Repository new file mode 100644 index 0000000..1f067b4 --- /dev/null +++ b/modules/base/math/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math diff --git a/modules/base/math/CVS/Root b/modules/base/math/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/CVS/Tag b/modules/base/math/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/CVS/Template b/modules/base/math/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/fixed_point/CVS/Entries b/modules/base/math/fixed_point/CVS/Entries new file mode 100644 index 0000000..0bc6ae3 --- /dev/null +++ b/modules/base/math/fixed_point/CVS/Entries @@ -0,0 +1,44 @@ +/Makefile/1.3.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/f16.h/1.6.4.3/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_add.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_div.c/1.3.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_double.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_int.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_inv.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_msb_mul.c/1.5.4.1/Sun Nov 26 21:06:00 2006//Tb_zer0 +/f16_mul.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_neg.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_print.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_sqrt.c/1.5.4.4/Mon Feb 2 22:21:20 2009//Tb_zer0 +/f16_sub.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f16_to_s16.h/1.3.6.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32.h/1.6.4.3/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_add.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_div.c/1.3.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_double.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_int.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_inv.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_msb_mul.c/1.5.4.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/f32_mul.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_neg.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_print.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_sqrt.c/1.5.4.4/Mon Feb 2 22:21:20 2009//Tb_zer0 +/f32_sub.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f32_to_s32.h/1.3.6.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64.h/1.6.4.3/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_add.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_div.c/1.3.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_double.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_int.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_inv.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_msb_mul.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_mul.c/1.5.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_neg.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_print.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_sqrt.c/1.5.4.4/Mon Feb 2 22:21:20 2009//Tb_zer0 +/f64_sub.c/1.4.4.2/Sat May 10 15:06:26 2008//Tb_zer0 +/f64_to_s64.h/1.3.6.3/Sat May 10 15:06:27 2008//Tb_zer0 +/s16_to_f16.h/1.3.6.2/Sat May 10 15:06:27 2008//Tb_zer0 +/s32_to_f32.h/1.3.6.2/Sat May 10 15:06:27 2008//Tb_zer0 +/s64_to_f64.h/1.3.6.3/Sat May 10 15:06:27 2008//Tb_zer0 +D/test//// diff --git a/modules/base/math/fixed_point/CVS/Repository b/modules/base/math/fixed_point/CVS/Repository new file mode 100644 index 0000000..b1f1005 --- /dev/null +++ b/modules/base/math/fixed_point/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math/fixed_point diff --git a/modules/base/math/fixed_point/CVS/Root b/modules/base/math/fixed_point/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/fixed_point/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/fixed_point/CVS/Tag b/modules/base/math/fixed_point/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/fixed_point/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/fixed_point/CVS/Template b/modules/base/math/fixed_point/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/fixed_point/Makefile b/modules/base/math/fixed_point/Makefile new file mode 100644 index 0000000..7d6183b --- /dev/null +++ b/modules/base/math/fixed_point/Makefile @@ -0,0 +1,18 @@ +TARGET = fixed_point + +# List C source files here. (C dependencies are automatically generated.) + +SRC = \ +f16_add.c f16_div.c f16_double.c f16_int.c \ +f16_inv.c f16_mul.c f16_msb_mul.c \ +f16_neg.c f16_print.c f16_sqrt.c f16_sub.c \ +f32_add.c f32_div.c f32_double.c f32_int.c \ +f32_inv.c f32_mul.c f32_msb_mul.c \ +f32_neg.c f32_print.c f32_sqrt.c f32_sub.c \ +f64_add.c f64_div.c f64_double.c f64_int.c \ +f64_inv.c f64_mul.c f64_msb_mul.c \ +f64_neg.c f64_print.c f64_sqrt.c f64_sub.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/math/fixed_point/f16.h b/modules/base/math/fixed_point/f16.h new file mode 100644 index 0000000..9f6289c --- /dev/null +++ b/modules/base/math/fixed_point/f16.h @@ -0,0 +1,123 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16.h,v 1.6.4.3 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +/* Here is an example of what is fixed point. This is the f16 type : + * + * int dec 1/256 = 0.00390625 + * + * 07 01 : 7 + 0x01*0.00390625 = 7.0039625 + * 07 80 : 7 + 0x80*0.00390625 = 7.5 + * 07 FF : 7 + 0xFF*0.00390625 = 7.99609375 + * 00 00 : 0 + * FF 00 : -1 + * FF FF : -1 + 0xFF*0.00390625 = -0.0039625 + * 7F 00 : +127 + * 7F FF : +127 + 0xFF*0.00390625 = 127.99609375 + * 80 00 : -128 + * + * For f16 the structure is composed by 2 integer of 8 bits. */ + +#ifndef _F16_H_ +#define _F16_H_ + +#include <aversive.h> + +typedef struct fixed_16 { + union { + struct { + uint8_t decimal; + int8_t integer; + } s; + int16_t s16; + } u; +} f16; +#define f16_decimal u.s.decimal +#define f16_integer u.s.integer + +#define F16_ZERO ( \ +{ \ + f16 __f; \ + __f.u.s16 = 0; \ + __f; \ +}) + +#define F16_NAN ( \ +{ \ + f16 __f; \ + __f.u.s16 = 0xFFFF; \ + __f; \ +}) + +#define F16_IS_GT(x,y) (f16_to_s16(x) > f16_to_s16(y)) +#define F16_IS_LT(x,y) (f16_to_s16(x) < f16_to_s16(y)) +#define F16_IS_GE(x,y) (f16_to_s16(x) >= f16_to_s16(y)) +#define F16_IS_LE(x,y) (f16_to_s16(x) <= f16_to_s16(y)) +#define F16_IS_EQ(x,y) (f16_to_s16(x) == f16_to_s16(y)) +#define F16_IS_NE(x,y) (f16_to_s16(x) != f16_to_s16(y)) +#define F16_IS_NEG(x) ((x).f16_integer < 0) +#define F16_IS_ZERO(x) ((x).f16_integer == 0 && (x).f16_decimal == 0) + + +/** convert a double to a f16 */ +f16 f16_from_double(double f); + +/** convert a f16 to a double */ +double f16_to_double(f16 fix); + +/** convert 2 integer (int8_t and uint8_t) to a f16 */ +f16 f16_from_integer(int8_t i, uint8_t d); + +/** convert msb integer (int8_t) to a f16 */ +f16 f16_from_msb(int8_t i); + +/** convert lsb integer (int8_t) to a f16 + * ( -0.5 < ret < 0.5 ) + */ +f16 f16_from_lsb(int8_t i); + +/** return opposite of the number (=-f) */ +f16 f16_neg(f16 f); + +/** add a with b (=a+b) */ +f16 f16_add(f16 a, f16 b); + +/** add a with b (=a-b) */ +f16 f16_sub(f16 a, f16 b); + +/** return opposite of the number (=1/f) */ +f16 f16_inv(f16 f); + +/** mul a with b (=a*b) */ +f16 f16_mul(f16 a, f16 b); + +/** mul a with b (=a*b), but return only the msb */ +f16 f16_mul_msb(f16 a, f16 b); + +/** div a with b (=a/b) */ +f16 f16_div(f16 a, f16 b); + +/** sqrt of f */ +f16 f16_sqrt(f16 f); + +/** function that display a f16 to the standard output */ +void f16_print(f16 fix); + +#endif diff --git a/modules/base/math/fixed_point/f16_add.c b/modules/base/math/fixed_point/f16_add.c new file mode 100644 index 0000000..c87980e --- /dev/null +++ b/modules/base/math/fixed_point/f16_add.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_add.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <f16_to_s16.h> +#include <s16_to_f16.h> + + +f16 f16_add(f16 a, f16 b) +{ + return s16_to_f16( f16_to_s16(a) + f16_to_s16(b) ); +} + diff --git a/modules/base/math/fixed_point/f16_div.c b/modules/base/math/fixed_point/f16_div.c new file mode 100644 index 0000000..c44c928 --- /dev/null +++ b/modules/base/math/fixed_point/f16_div.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_div.c,v 1.3.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> + + +f16 f16_div(f16 a, f16 b) +{ + if (F16_IS_ZERO(b)) + return F16_NAN; + return f16_mul(a,f16_inv(b)); +} + diff --git a/modules/base/math/fixed_point/f16_double.c b/modules/base/math/fixed_point/f16_double.c new file mode 100644 index 0000000..6122aa0 --- /dev/null +++ b/modules/base/math/fixed_point/f16_double.c @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_double.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> + +/* value of 2^^8 in float */ +#define POW2_8F (256.0) + + +/**************** double <-> f16 */ + +f16 f16_from_double(double d) +{ + f16 f; + f.f16_decimal = (uint8_t) ((d - (int8_t)d) * POW2_8F); + f.f16_integer = (d < 0 && f.f16_decimal != 0 ? (int8_t)d-1 : (int8_t)d) ; + + return f; +} + +double f16_to_double(f16 f) +{ + double d; + + d = f.f16_integer; + d += ((double)f.f16_decimal / POW2_8F); + + return d; +} diff --git a/modules/base/math/fixed_point/f16_int.c b/modules/base/math/fixed_point/f16_int.c new file mode 100644 index 0000000..1065326 --- /dev/null +++ b/modules/base/math/fixed_point/f16_int.c @@ -0,0 +1,63 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_int.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> + + +/**************** int8_t,uint8_t <-> f16 */ + +f16 f16_from_integer(int8_t i, uint8_t d) +{ + f16 f; + f.f16_integer = i; + f.f16_decimal = d; + + return f; +} + +/**************** int8_t <-> f16 */ + +f16 f16_from_msb(int8_t i) +{ + f16 f; + f.f16_integer = i; + f.f16_decimal = 0; + + return f; +} + + +/**************** int8_t <-> f16 */ + +f16 f16_from_lsb(int8_t i) +{ + f16 f; + if ( i >= 0 ) { + f.f16_integer = 0; + f.f16_decimal = i; + } + else { + f.f16_integer = -1; + f.f16_decimal = i; + } + return f; +} diff --git a/modules/base/math/fixed_point/f16_inv.c b/modules/base/math/fixed_point/f16_inv.c new file mode 100644 index 0000000..ee87259 --- /dev/null +++ b/modules/base/math/fixed_point/f16_inv.c @@ -0,0 +1,35 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_inv.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <f16_to_s16.h> +#include <s16_to_f16.h> + + +f16 f16_inv(f16 f) +{ + if (F16_IS_ZERO(f)) + return F16_NAN; + + return s16_to_f16( ((int16_t)0x7fff) / (f16_to_s16(f)/2) ); +} + diff --git a/modules/base/math/fixed_point/f16_msb_mul.c b/modules/base/math/fixed_point/f16_msb_mul.c new file mode 100644 index 0000000..97bcf8b --- /dev/null +++ b/modules/base/math/fixed_point/f16_msb_mul.c @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_msb_mul.c,v 1.5.4.1 2006-11-26 21:06:00 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <f16_to_s16.h> + + +int16_t f16_msb_mul(f16 a, f16 b) +{ + return (int8_t)(( f16_to_s16(a) * f16_to_s16(b)) >> 8); +} + diff --git a/modules/base/math/fixed_point/f16_mul.c b/modules/base/math/fixed_point/f16_mul.c new file mode 100644 index 0000000..008cf1e --- /dev/null +++ b/modules/base/math/fixed_point/f16_mul.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_mul.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <s16_to_f16.h> + + +f16 f16_mul(f16 a, f16 b) +{ + return s16_to_f16( ( ((int16_t)(a.f16_integer) * (int16_t)(b.f16_integer)) << 8 ) + + (int16_t)(a.f16_integer) * (int16_t)(b.f16_decimal) + + (int16_t)(a.f16_decimal) * (int16_t)(b.f16_integer) + + ( ((int16_t)(a.f16_decimal) * (int16_t)(b.f16_decimal)) >> 8 ) ); +} diff --git a/modules/base/math/fixed_point/f16_neg.c b/modules/base/math/fixed_point/f16_neg.c new file mode 100644 index 0000000..3114d2f --- /dev/null +++ b/modules/base/math/fixed_point/f16_neg.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_neg.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <f16_to_s16.h> +#include <s16_to_f16.h> + +f16 f16_neg(f16 f) +{ + return s16_to_f16( -f16_to_s16(f) ); +} diff --git a/modules/base/math/fixed_point/f16_print.c b/modules/base/math/fixed_point/f16_print.c new file mode 100644 index 0000000..b45b8c2 --- /dev/null +++ b/modules/base/math/fixed_point/f16_print.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_print.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <f16_to_s16.h> + +void f16_print(f16 f) +{ + if(F16_IS_EQ(f, F16_NAN)) + printf("nan"); + else + printf("%f",f16_to_double(f)); +} + diff --git a/modules/base/math/fixed_point/f16_sqrt.c b/modules/base/math/fixed_point/f16_sqrt.c new file mode 100644 index 0000000..39eb65a --- /dev/null +++ b/modules/base/math/fixed_point/f16_sqrt.c @@ -0,0 +1,66 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_sqrt.c,v 1.5.4.4 2009-02-02 22:21:20 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <s16_to_f16.h> + + +#define NEXT(n, i) (((n) + (i)/(n)) >> 1) + +static uint16_t u16_sqrt(uint16_t number) { + uint16_t n = 1; + uint16_t n1 = NEXT(n, number); + + if (number == 0) + return 0; + + while(ABS(n1 - n) > 1) { + n = n1; + n1 = NEXT(n, number); + } + while((n1*n1) > number) { + n1 -= 1; + } + return n1; +} + + +f16 f16_sqrt(f16 f) +{ + uint16_t a,b,c,d; + + if (F16_IS_NEG(f)) + return F16_NAN; + + if(f.f16_integer) { + /* sqrt(a+b) = sqrt(a)*sqrt(1+b/a) */ + a=(uint16_t)(f.f16_integer) << 8 ; + b=(uint16_t)(f.f16_decimal) << 8 ; + c=u16_sqrt(a); + d=u16_sqrt(0x100 + (b/a)); + return f16_mul(s16_to_f16( c<<4 ), s16_to_f16( d<<4 )); + } + else { + b=(uint16_t)(f.f16_decimal) << 8 ; + return s16_to_f16(u16_sqrt(b)); + } +} diff --git a/modules/base/math/fixed_point/f16_sub.c b/modules/base/math/fixed_point/f16_sub.c new file mode 100644 index 0000000..c292fc9 --- /dev/null +++ b/modules/base/math/fixed_point/f16_sub.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_sub.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f16.h> +#include <f16_to_s16.h> +#include <s16_to_f16.h> + + +f16 f16_sub(f16 a, f16 b) +{ + return s16_to_f16( f16_to_s16(a) - f16_to_s16(b) ); +} + diff --git a/modules/base/math/fixed_point/f16_to_s16.h b/modules/base/math/fixed_point/f16_to_s16.h new file mode 100644 index 0000000..b9a263e --- /dev/null +++ b/modules/base/math/fixed_point/f16_to_s16.h @@ -0,0 +1,42 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f16_to_s16.h,v 1.3.6.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#ifndef _F16_TO_S16_H_ +#define _F16_TO_S16_H_ + +#ifdef HOST_VERSION +/* not optimized, but will work with any endianness */ +static inline int16_t f16_to_s16(f16 f) +{ + return ( ((int16_t)(f.f16_integer))<<8 ) | ((int16_t)(f.f16_decimal)); +} + +#else +/* only for AVR, faster */ +static inline int16_t f16_to_s16(f16 f) +{ + return f.u.s16; +} + +#endif + + +#endif diff --git a/modules/base/math/fixed_point/f32.h b/modules/base/math/fixed_point/f32.h new file mode 100644 index 0000000..034cfad --- /dev/null +++ b/modules/base/math/fixed_point/f32.h @@ -0,0 +1,122 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32.h,v 1.6.4.3 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +/* Here is an example of what is fixed point. This is the f16 type : + * + * int dec 1/256 = 0.00390625 + * + * 07 01 : 7 + 0x01*0.00390625 = 7.0039625 + * 07 80 : 7 + 0x80*0.00390625 = 7.5 + * 07 FF : 7 + 0xFF*0.00390625 = 7.99609375 + * 00 00 : 0 + * FF 00 : -1 + * FF FF : -1 + 0xFF*0.00390625 = -0.0039625 + * 7F 00 : +127 + * 7F FF : +127 + 0xFF*0.00390625 = 127.99609375 + * 80 00 : -128 + * + * For f32 the structure is composed by 2 integer of 16 bits. */ + +#ifndef _F32_H_ +#define _F32_H_ + +#include <aversive.h> + +typedef struct fixed_32 { + union { + struct { + uint16_t decimal; + int16_t integer; + } s; + int32_t s32; + } u; +} f32; +#define f32_decimal u.s.decimal +#define f32_integer u.s.integer + +#define F32_ZERO ( \ +{ \ + f32 __f; \ + __f.u.s32 = 0; \ + __f; \ +}) + +#define F32_NAN ( \ +{ \ + f32 __f; \ + __f.u.s32 = 0xFFFFFFFF; \ + __f; \ +}) + +#define F32_IS_GT(x,y) (f32_to_s32(x) > f32_to_s32(y)) +#define F32_IS_LT(x,y) (f32_to_s32(x) < f32_to_s32(y)) +#define F32_IS_GE(x,y) (f32_to_s32(x) >= f32_to_s32(y)) +#define F32_IS_LE(x,y) (f32_to_s32(x) <= f32_to_s32(y)) +#define F32_IS_EQ(x,y) (f32_to_s32(x) == f32_to_s32(y)) +#define F32_IS_NE(x,y) (f32_to_s32(x) != f32_to_s32(y)) +#define F32_IS_NEG(x) ((x).f32_integer < 0) +#define F32_IS_ZERO(x) ((x).f32_integer == 0 && (x).f32_decimal == 0) + +/** convert a double to a f32 */ +f32 f32_from_double(double f); + +/** convert a f32 to a double */ +double f32_to_double(f32 fix); + +/** convert 2 integer (int16_t and uint16_t) to a f32 */ +f32 f32_from_integer(int16_t i, uint16_t d); + +/** convert msb integer (int16_t) to a f32 */ +f32 f32_from_msb(int16_t i); + +/** convert lsb integer (int16_t) to a f32 + * ( -0.5 < ret < 0.5 ) + */ +f32 f32_from_lsb(int16_t i); + +/** return opposite of the number (=-f) */ +f32 f32_neg(f32 f); + +/** add a with b (=a+b) */ +f32 f32_add(f32 a, f32 b); + +/** add a with b (=a-b) */ +f32 f32_sub(f32 a, f32 b); + +/** return opposite of the number (=1/f) */ +f32 f32_inv(f32 f); + +/** mul a with b (=a*b) */ +f32 f32_mul(f32 a, f32 b); + +/** mul a with b (=a*b), but return only the msb */ +f32 f32_mul_msb(f32 a, f32 b); + +/** div a with b (=a/b) */ +f32 f32_div(f32 a, f32 b); + +/** sqrt of f */ +f32 f32_sqrt(f32 f); + +/** function that display a f32 to the standard output */ +void f32_print(f32 fix); + +#endif diff --git a/modules/base/math/fixed_point/f32_add.c b/modules/base/math/fixed_point/f32_add.c new file mode 100644 index 0000000..9d6501b --- /dev/null +++ b/modules/base/math/fixed_point/f32_add.c @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_add.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <f32_to_s32.h> +#include <s32_to_f32.h> + +f32 f32_add(f32 a, f32 b) +{ + return s32_to_f32( f32_to_s32(a) + f32_to_s32(b) ); +} + diff --git a/modules/base/math/fixed_point/f32_div.c b/modules/base/math/fixed_point/f32_div.c new file mode 100644 index 0000000..3325d3d --- /dev/null +++ b/modules/base/math/fixed_point/f32_div.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_div.c,v 1.3.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> + +f32 f32_div(f32 a, f32 b) +{ + if (F32_IS_ZERO(b)) + return F32_NAN; + return f32_mul(a,f32_inv(b)); +} diff --git a/modules/base/math/fixed_point/f32_double.c b/modules/base/math/fixed_point/f32_double.c new file mode 100644 index 0000000..63f274f --- /dev/null +++ b/modules/base/math/fixed_point/f32_double.c @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_double.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> + +/* value of 2^^16 in float */ +#define POW2_16F (65536.0) + + +/**************** double <-> f32 */ + +f32 f32_from_double(double d) +{ + f32 f; + f.f32_decimal = (uint16_t) ((d - (int16_t)d) * POW2_16F); + f.f32_integer = (d < 0 && f.f32_decimal != 0 ? (int16_t)d-1 : (int16_t)d) ; + + return f; +} + +double f32_to_double(f32 f) +{ + double d; + + d = f.f32_integer; + d += ((double)f.f32_decimal / POW2_16F); + + return d; +} diff --git a/modules/base/math/fixed_point/f32_int.c b/modules/base/math/fixed_point/f32_int.c new file mode 100644 index 0000000..7637a0d --- /dev/null +++ b/modules/base/math/fixed_point/f32_int.c @@ -0,0 +1,63 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_int.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> + + +/**************** int16_t,uint16_t <-> f32 */ + +f32 f32_from_integer(int16_t i, uint16_t d) +{ + f32 f; + f.f32_integer = i; + f.f32_decimal = d; + + return f; +} + +/**************** int16_t <-> f32 */ + +f32 f32_from_msb(int16_t i) +{ + f32 f; + f.f32_integer = i; + f.f32_decimal = 0; + + return f; +} + + +/**************** int16_t <-> f32 */ + +f32 f32_from_lsb(int16_t i) +{ + f32 f; + if ( i >= 0 ) { + f.f32_integer = 0; + f.f32_decimal = i; + } + else { + f.f32_integer = -1; + f.f32_decimal = i; + } + return f; +} diff --git a/modules/base/math/fixed_point/f32_inv.c b/modules/base/math/fixed_point/f32_inv.c new file mode 100644 index 0000000..087a7f1 --- /dev/null +++ b/modules/base/math/fixed_point/f32_inv.c @@ -0,0 +1,34 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_inv.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <f32_to_s32.h> +#include <s32_to_f32.h> + + +f32 f32_inv(f32 f) +{ + if (F32_IS_ZERO(f)) + return F32_NAN; + + return s32_to_f32( ((int32_t)0x7fffffff) / (f32_to_s32(f)/2) ); +} diff --git a/modules/base/math/fixed_point/f32_msb_mul.c b/modules/base/math/fixed_point/f32_msb_mul.c new file mode 100644 index 0000000..78b76f8 --- /dev/null +++ b/modules/base/math/fixed_point/f32_msb_mul.c @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_msb_mul.c,v 1.5.4.1 2006-11-26 21:06:01 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <f32_to_s32.h> + + +int32_t f32_msb_mul(f32 a, f32 b) +{ + return (int16_t)(( f32_to_s32(a) * f32_to_s32(b)) >> 16); +} + diff --git a/modules/base/math/fixed_point/f32_mul.c b/modules/base/math/fixed_point/f32_mul.c new file mode 100644 index 0000000..5d4680d --- /dev/null +++ b/modules/base/math/fixed_point/f32_mul.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_mul.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <s32_to_f32.h> + + +f32 f32_mul(f32 a, f32 b) +{ + return s32_to_f32( ( ((int32_t)(a.f32_integer) * (int32_t)(b.f32_integer)) << 16 ) + + (int32_t)(a.f32_integer) * (int32_t)(b.f32_decimal) + + (int32_t)(a.f32_decimal) * (int32_t)(b.f32_integer) + + ( ((int32_t)(a.f32_decimal) * (int32_t)(b.f32_decimal)) >> 16 ) ); +} diff --git a/modules/base/math/fixed_point/f32_neg.c b/modules/base/math/fixed_point/f32_neg.c new file mode 100644 index 0000000..c1d9784 --- /dev/null +++ b/modules/base/math/fixed_point/f32_neg.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_neg.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <f32_to_s32.h> +#include <s32_to_f32.h> + +f32 f32_neg(f32 f) +{ + return s32_to_f32( -f32_to_s32(f) ); +} diff --git a/modules/base/math/fixed_point/f32_print.c b/modules/base/math/fixed_point/f32_print.c new file mode 100644 index 0000000..a61880a --- /dev/null +++ b/modules/base/math/fixed_point/f32_print.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_print.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <f32_to_s32.h> + + +void f32_print(f32 f) +{ + if(F32_IS_EQ(f, F32_NAN)) + printf("nan"); + else + printf("%f",f32_to_double(f)); +} diff --git a/modules/base/math/fixed_point/f32_sqrt.c b/modules/base/math/fixed_point/f32_sqrt.c new file mode 100644 index 0000000..97810cb --- /dev/null +++ b/modules/base/math/fixed_point/f32_sqrt.c @@ -0,0 +1,69 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_sqrt.c,v 1.5.4.4 2009-02-02 22:21:20 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <s32_to_f32.h> + +#define NEXT(n, i) (((n) + (i)/(n)) >> 1) + +static uint32_t u32_sqrt(uint32_t number) +{ + uint32_t n = 1; + uint32_t n1 = NEXT(n, number); + + if (number == 0) + return 0; + + while(ABS(n1 - n) > 1) { + n = n1; + n1 = NEXT(n, number); + } + while((n1*n1) > number) { + n1 -= 1; + } + return n1; +} + +f32 f32_sqrt(f32 f) +{ + uint32_t a,b,c,d; + + if (F32_IS_ZERO(f)) + return F32_ZERO; + + if (F32_IS_NEG(f)) + return F32_NAN; + + if(f.f32_integer) { + /* sqrt(a+b) = sqrt(a)*sqrt(1+b/a) */ + a=(uint32_t)(f.f32_integer) << 16 ; + b=(uint32_t)(f.f32_decimal) << 16 ; + c=u32_sqrt(a); + d=u32_sqrt(0x10000 + (b/a)); + return f32_mul(s32_to_f32( c<<8 ), s32_to_f32( d<<8 )); + } + else { + b=(uint32_t)(f.f32_decimal) << 16 ; + return s32_to_f32(u32_sqrt(b)); + } +} + diff --git a/modules/base/math/fixed_point/f32_sub.c b/modules/base/math/fixed_point/f32_sub.c new file mode 100644 index 0000000..274c61c --- /dev/null +++ b/modules/base/math/fixed_point/f32_sub.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_sub.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f32.h> +#include <f32_to_s32.h> +#include <s32_to_f32.h> + +f32 f32_sub(f32 a, f32 b) +{ + return s32_to_f32( f32_to_s32(a) - f32_to_s32(b) ); +} diff --git a/modules/base/math/fixed_point/f32_to_s32.h b/modules/base/math/fixed_point/f32_to_s32.h new file mode 100644 index 0000000..ffd20ca --- /dev/null +++ b/modules/base/math/fixed_point/f32_to_s32.h @@ -0,0 +1,42 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f32_to_s32.h,v 1.3.6.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#ifndef _F32_TO_S32_H_ +#define _F32_TO_S32_H_ + +#ifdef HOST_VERSION +/* not optimized, but will work with any endianness */ +static inline int32_t f32_to_s32(f32 f) +{ + return ( ((int32_t)(f.f32_integer))<<16 ) | ((int32_t)(f.f32_decimal)); +} + +#else +/* only for AVR, faster */ +static inline int32_t f32_to_s32(f32 f) +{ + return f.u.s32; +} + +#endif + + +#endif diff --git a/modules/base/math/fixed_point/f64.h b/modules/base/math/fixed_point/f64.h new file mode 100644 index 0000000..a5fce74 --- /dev/null +++ b/modules/base/math/fixed_point/f64.h @@ -0,0 +1,123 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64.h,v 1.6.4.3 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +/* Here is an example of what is fixed point. This is the f16 type : + * + * int dec 1/256 = 0.00390625 + * + * 07 01 : 7 + 0x01*0.00390625 = 7.0039625 + * 07 80 : 7 + 0x80*0.00390625 = 7.5 + * 07 FF : 7 + 0xFF*0.00390625 = 7.99609375 + * 00 00 : 0 + * FF 00 : -1 + * FF FF : -1 + 0xFF*0.00390625 = -0.0039625 + * 7F 00 : +127 + * 7F FF : +127 + 0xFF*0.00390625 = 127.99609375 + * 80 00 : -128 + * + * For f64 the structure is composed by 2 integer of 32 bits. */ + +#include <aversive.h> + +#ifndef _F64_H_ +#define _F64_H_ + +typedef struct fixed_64 { + union { + struct { + uint32_t decimal; + int32_t integer; + } s; + int64_t s64; + } u; +} f64; +#define f64_integer u.s.integer +#define f64_decimal u.s.decimal + +#define F64_ZERO ( \ +{ \ + f64 __f; \ + __f.u.s64 = 0; \ + __f; \ +}) + +#define F64_NAN ( \ +{ \ + f64 __f; \ + __f.u.s64 = 0xFFFFFFFFFFFFFFFF; \ + __f; \ +}) + +#define F64_IS_GT(x,y) (f64_to_s64(x) > f64_to_s64(y)) +#define F64_IS_LT(x,y) (f64_to_s64(x) < f64_to_s64(y)) +#define F64_IS_GE(x,y) (f64_to_s64(x) >= f64_to_s64(y)) +#define F64_IS_LE(x,y) (f64_to_s64(x) <= f64_to_s64(y)) +#define F64_IS_EQ(x,y) (f64_to_s64(x) == f64_to_s64(y)) +#define F64_IS_NE(x,y) (f64_to_s64(x) != f64_to_s64(y)) +#define F64_IS_NEG(x) ((x).f64_integer < 0) +#define F64_IS_ZERO(x) ((x).f64_integer == 0 && (x).f64_decimal == 0) + + +/** convert a double to a f64 */ +f64 f64_from_double(double f); + +/** convert a f64 to a double */ +double f64_to_double(f64 fix); + +/** convert 2 integer (int32_t and uint32_t) to a f64 */ +f64 f64_from_integer(int32_t i, uint32_t d); + +/** convert msb integer (int32_t) to a f64 */ +f64 f64_from_msb(int32_t i); + +/** convert lsb integer (int32_t) to a f64 + * ( -0.5 < ret < 0.5 ) + */ +f64 f64_from_lsb(int32_t i); + +/** return opposite of the number (=-f) */ +f64 f64_neg(f64 f); + +/** add a with b (=a+b) */ +f64 f64_add(f64 a, f64 b); + +/** add a with b (=a-b) */ +f64 f64_sub(f64 a, f64 b); + +/** return opposite of the number (=1/f) */ +f64 f64_inv(f64 f); + +/** mul a with b (=a*b) */ +f64 f64_mul(f64 a, f64 b); + +/** mul a with b (=a*b), but return only the msb */ +int32_t f64_msb_mul(f64 a, f64 b); + +/** div a with b (=a/b) */ +f64 f64_div(f64 a, f64 b); + +/** sqrt of f */ +f64 f64_sqrt(f64 f); + +/** function that display a f64 to the standard output */ +void f64_print(f64 fix); + +#endif diff --git a/modules/base/math/fixed_point/f64_add.c b/modules/base/math/fixed_point/f64_add.c new file mode 100644 index 0000000..898b711 --- /dev/null +++ b/modules/base/math/fixed_point/f64_add.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_add.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <f64_to_s64.h> +#include <s64_to_f64.h> + +f64 f64_add(f64 a, f64 b) +{ + return s64_to_f64( f64_to_s64(a) + f64_to_s64(b) ); +} diff --git a/modules/base/math/fixed_point/f64_div.c b/modules/base/math/fixed_point/f64_div.c new file mode 100644 index 0000000..810cbc9 --- /dev/null +++ b/modules/base/math/fixed_point/f64_div.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_div.c,v 1.3.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> + +f64 f64_div(f64 a, f64 b) +{ + if (F64_IS_ZERO(b)) + return F64_NAN; + return f64_mul(a,f64_inv(b)); +} diff --git a/modules/base/math/fixed_point/f64_double.c b/modules/base/math/fixed_point/f64_double.c new file mode 100644 index 0000000..f13e1d6 --- /dev/null +++ b/modules/base/math/fixed_point/f64_double.c @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_double.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> + +/* value of 2^^32 in float */ +#define POW2_32F (4294967296.0) + + +/**************** double <-> f64 */ + +f64 f64_from_double(double d) +{ + f64 f; + f.f64_decimal = (uint32_t) ((d - (int32_t)d) * POW2_32F); + f.f64_integer = (d < 0 && f.f64_decimal != 0 ? (int32_t)d-1 : (int32_t)d) ; + + return f; +} + +double f64_to_double(f64 f) +{ + double d; + + d = f.f64_integer; + d += ((double)f.f64_decimal / POW2_32F); + + return d; +} diff --git a/modules/base/math/fixed_point/f64_int.c b/modules/base/math/fixed_point/f64_int.c new file mode 100644 index 0000000..e6d7e39 --- /dev/null +++ b/modules/base/math/fixed_point/f64_int.c @@ -0,0 +1,62 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_int.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> + +/**************** int32_t,uint32_t <-> f64 */ + +f64 f64_from_integer(int32_t i, uint32_t d) +{ + f64 f; + f.f64_integer = i; + f.f64_decimal = d; + + return f; +} + +/**************** int32_t <-> f64 */ + +f64 f64_from_msb(int32_t i) +{ + f64 f; + f.f64_integer = i; + f.f64_decimal = 0; + + return f; +} + + +/**************** int32_t <-> f64 */ + +f64 f64_from_lsb(int32_t i) +{ + f64 f; + if ( i >= 0 ) { + f.f64_integer = 0; + f.f64_decimal = i; + } + else { + f.f64_integer = -1; + f.f64_decimal = i; + } + return f; +} diff --git a/modules/base/math/fixed_point/f64_inv.c b/modules/base/math/fixed_point/f64_inv.c new file mode 100644 index 0000000..1e50e06 --- /dev/null +++ b/modules/base/math/fixed_point/f64_inv.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_inv.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <f64_to_s64.h> +#include <s64_to_f64.h> + +f64 f64_inv(f64 f) +{ + if (F64_IS_ZERO(f)) + return F64_NAN; + + return s64_to_f64( ((int64_t)0x7fffffffffffffff) / (f64_to_s64(f)/2) ); +} diff --git a/modules/base/math/fixed_point/f64_msb_mul.c b/modules/base/math/fixed_point/f64_msb_mul.c new file mode 100644 index 0000000..d0a18df --- /dev/null +++ b/modules/base/math/fixed_point/f64_msb_mul.c @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_msb_mul.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <f64_to_s64.h> + + +/* about 80 us with a 16 Mhz quartz on an atm128 */ +int32_t f64_msb_mul(f64 a, f64 b) +{ + return (int32_t)(( f64_to_s64(a) * f64_to_s64(b)) >> 32); +} diff --git a/modules/base/math/fixed_point/f64_mul.c b/modules/base/math/fixed_point/f64_mul.c new file mode 100644 index 0000000..a38a6f6 --- /dev/null +++ b/modules/base/math/fixed_point/f64_mul.c @@ -0,0 +1,34 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_mul.c,v 1.5.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <s64_to_f64.h> + + +/* about 300 us with a 16 Mhz quartz on an atm128 */ +f64 f64_mul(f64 a, f64 b) +{ + return s64_to_f64( ( ((int64_t)(a.f64_integer) * (int64_t)(b.f64_integer)) << 32 ) + + (int64_t)(a.f64_integer) * (int64_t)(b.f64_decimal) + + (int64_t)(a.f64_decimal) * (int64_t)(b.f64_integer) + + ( ((int64_t)(a.f64_decimal) * (int64_t)(b.f64_decimal)) >> 32 ) ); +} diff --git a/modules/base/math/fixed_point/f64_neg.c b/modules/base/math/fixed_point/f64_neg.c new file mode 100644 index 0000000..87ee893 --- /dev/null +++ b/modules/base/math/fixed_point/f64_neg.c @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_neg.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <f64_to_s64.h> +#include <s64_to_f64.h> + + +f64 f64_neg(f64 f) +{ + return s64_to_f64( -f64_to_s64(f) ); +} diff --git a/modules/base/math/fixed_point/f64_print.c b/modules/base/math/fixed_point/f64_print.c new file mode 100644 index 0000000..5ef0550 --- /dev/null +++ b/modules/base/math/fixed_point/f64_print.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_print.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <f64_to_s64.h> + +void f64_print(f64 f) +{ + if(F64_IS_EQ(f, F64_NAN)) + printf("nan"); + else + printf("%f",f64_to_double(f)); +} diff --git a/modules/base/math/fixed_point/f64_sqrt.c b/modules/base/math/fixed_point/f64_sqrt.c new file mode 100644 index 0000000..4aa4eca --- /dev/null +++ b/modules/base/math/fixed_point/f64_sqrt.c @@ -0,0 +1,67 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_sqrt.c,v 1.5.4.4 2009-02-02 22:21:20 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <s64_to_f64.h> + +#define NEXT(n, i) (((n) + (i)/(n)) >> 1) + +static uint64_t u64_sqrt(uint64_t number) { + uint64_t n = 1; + uint64_t n1 = NEXT(n, number); + + if (number == 0) + return 0; + + while(ABS(n1 - n) > 1) { + n = n1; + n1 = NEXT(n, number); + } + while((n1*n1) > number) { + n1 -= 1; + } + return n1; +} + +f64 f64_sqrt(f64 f) +{ + uint64_t a,b,c,d; + + if (F64_IS_ZERO(f)) + return F64_ZERO; + + if (F64_IS_NEG(f)) + return F64_NAN; + + if(f.f64_integer) { + /* sqrt(a+b) = sqrt(a)*sqrt(1+b/a) */ + a=(uint64_t)(f.f64_integer) << 32 ; + b=(uint64_t)(f.f64_decimal) << 32 ; + c=u64_sqrt(a); + d=u64_sqrt(0x100000000 + (b/a)); + return f64_mul(s64_to_f64( c<<16 ), s64_to_f64( d<<16 )); + } + else { + b=(uint64_t)(f.f64_decimal) << 32 ; + return s64_to_f64(u64_sqrt(b)); + } +} diff --git a/modules/base/math/fixed_point/f64_sub.c b/modules/base/math/fixed_point/f64_sub.c new file mode 100644 index 0000000..96244f5 --- /dev/null +++ b/modules/base/math/fixed_point/f64_sub.c @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_sub.c,v 1.4.4.2 2008-05-10 15:06:26 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <f64.h> +#include <f64_to_s64.h> +#include <s64_to_f64.h> + +f64 f64_sub(f64 a, f64 b) +{ + return s64_to_f64( f64_to_s64(a) - f64_to_s64(b) ); +} diff --git a/modules/base/math/fixed_point/f64_to_s64.h b/modules/base/math/fixed_point/f64_to_s64.h new file mode 100644 index 0000000..6b25f9a --- /dev/null +++ b/modules/base/math/fixed_point/f64_to_s64.h @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: f64_to_s64.h,v 1.3.6.3 2008-05-10 15:06:27 zer0 Exp $ + * + */ + +#include <aversive.h> + +#ifndef _F64_TO_S64_H_ +#define _F64_TO_S64_H_ + +#if HOST_VERSION +/* not optimized, but will work with any endianness */ +static inline int64_t f64_to_s64(f64 f) +{ + return ( ((int64_t)(f.f64_integer))<<32 ) | ((int64_t)(f.f64_decimal)); +} + +#else +/* only for AVR, faster */ +static inline int64_t f64_to_s64(f64 f) +{ + return f.u.s64; +} + +#endif + +#endif diff --git a/modules/base/math/fixed_point/s16_to_f16.h b/modules/base/math/fixed_point/s16_to_f16.h new file mode 100644 index 0000000..5644e39 --- /dev/null +++ b/modules/base/math/fixed_point/s16_to_f16.h @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: s16_to_f16.h,v 1.3.6.2 2008-05-10 15:06:27 zer0 Exp $ + * + */ + +#ifndef _S16_TO_F16_H_ +#define _S16_TO_F16_H_ + +#ifdef HOST_VERSION +/* not optimized, but will work with any endianness */ +static inline f16 s16_to_f16(int16_t i) +{ + f16 f; + f.f16_integer = ((i) >> 8); + f.f16_decimal = (i); + return f; +} +#else +/* only for AVR, faster */ +static inline f16 s16_to_f16(int16_t i) +{ + f16 f; + f.u.s16 = i; + return f; +} +#endif + +#endif diff --git a/modules/base/math/fixed_point/s32_to_f32.h b/modules/base/math/fixed_point/s32_to_f32.h new file mode 100644 index 0000000..7765664 --- /dev/null +++ b/modules/base/math/fixed_point/s32_to_f32.h @@ -0,0 +1,46 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: s32_to_f32.h,v 1.3.6.2 2008-05-10 15:06:27 zer0 Exp $ + * + */ + +#ifndef _S32_TO_F32_H_ +#define _S32_TO_F32_H_ + +#ifdef HOST_VERSION +/* not optimized, but will work with any endianness */ + +static inline f32 s32_to_f32(int32_t i) +{ + f32 f; + f.f32_integer = ((i) >> 16); + f.f32_decimal = (i); + return f; +} +#else +/* only for AVR, faster */ + +static inline f32 s32_to_f32(int32_t i) +{ + f32 f; + f.u.s32 = i; + return f; +} +#endif + +#endif diff --git a/modules/base/math/fixed_point/s64_to_f64.h b/modules/base/math/fixed_point/s64_to_f64.h new file mode 100644 index 0000000..0a36717 --- /dev/null +++ b/modules/base/math/fixed_point/s64_to_f64.h @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: s64_to_f64.h,v 1.3.6.3 2008-05-10 15:06:27 zer0 Exp $ + * + */ + +#include <aversive.h> + +#ifndef _S64_TO_F64_H_ +#define _S64_TO_F64_H_ + +#if HOST_VERSION +/* not optimized, but will work with any endianness */ + +static inline f64 s64_to_f64(int64_t i) +{ + f64 f; + f.f64_integer = ((i) >> 32); + f.f64_decimal = (i); + return f; +} +#else +/* only for AVR, faster */ + +static inline f64 s64_to_f64(int64_t i) +{ + f64 f; + f.u.s64 = i; + return f; +} +#endif + +#endif diff --git a/modules/base/math/fixed_point/test/.config b/modules/base/math/fixed_point/test/.config new file mode 100644 index 0000000..296da2c --- /dev/null +++ b/modules/base/math/fixed_point/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_ADVANCED_PRINTF=y +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +CONFIG_MODULE_FIXED_POINT=y +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/base/math/fixed_point/test/CVS/Entries b/modules/base/math/fixed_point/test/CVS/Entries new file mode 100644 index 0000000..d323972 --- /dev/null +++ b/modules/base/math/fixed_point/test/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.7.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/main.c/1.5.4.2/Tue Jun 12 16:18:43 2007//Tb_zer0 +/uart_config.h/1.4.4.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +D diff --git a/modules/base/math/fixed_point/test/CVS/Repository b/modules/base/math/fixed_point/test/CVS/Repository new file mode 100644 index 0000000..a2c7bd7 --- /dev/null +++ b/modules/base/math/fixed_point/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math/fixed_point/test diff --git a/modules/base/math/fixed_point/test/CVS/Root b/modules/base/math/fixed_point/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/fixed_point/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/fixed_point/test/CVS/Tag b/modules/base/math/fixed_point/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/fixed_point/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/fixed_point/test/CVS/Template b/modules/base/math/fixed_point/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/fixed_point/test/Makefile b/modules/base/math/fixed_point/test/Makefile new file mode 100644 index 0000000..8e56dbc --- /dev/null +++ b/modules/base/math/fixed_point/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/base/math/fixed_point/test/main.c b/modules/base/math/fixed_point/test/main.c new file mode 100644 index 0000000..8b65b64 --- /dev/null +++ b/modules/base/math/fixed_point/test/main.c @@ -0,0 +1,289 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.5.4.2 2007-06-12 16:18:43 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <math.h> + +#include <uart.h> +#include <f64.h> +#include <f32.h> +#include <f16.h> + +#define A 6.25 +#define B -4.684 +#define C 0.0566 + +int f64_test(void) +{ + f64 a,b,c; + + a = f64_from_double(A); + b = f64_from_double(B); + c = f64_from_double(C); + + printf("************ F64\n\n"); + + printf("*** ADD\n\n"); + printf("Result is "); + f64_print(f64_add(a,b)); + printf("\nResult should be %f\n\n", A+B); + printf("Result is "); + f64_print(f64_add(b,c)); + printf("\nResult should be %f\n\n", B+C); + printf("Result is "); + f64_print(f64_add(c,a)); + printf("\nResult should be %f\n\n", C+A); + + printf("*** SUB\n\n"); + printf("Result is "); + f64_print(f64_sub(a,b)); + printf("\nResult should be %f\n\n", A-B); + printf("Result is "); + f64_print(f64_sub(b,c)); + printf("\nResult should be %f\n\n", B-C); + printf("Result is "); + f64_print(f64_sub(c,a)); + printf("\nResult should be %f\n\n", C-A); + + printf("*** INV\n\n"); + printf("Result is "); + f64_print(f64_inv(a)); + printf("\nResult should be %f\n\n", 1.0/A); + printf("Result is "); + f64_print(f64_inv(b)); + printf("\nResult should be %f\n\n", 1.0/B); + printf("Result is "); + f64_print(f64_inv(c)); + printf("\nResult should be %f\n\n", 1.0/C); + + printf("*** MUL\n\n"); + printf("Result is "); + f64_print(f64_mul(a,b)); + printf("\nResult should be %f\n\n", A*B); + printf("Result is "); + f64_print(f64_mul(b,c)); + printf("\nResult should be %f\n\n", B*C); + printf("Result is "); + f64_print(f64_mul(c,a)); + printf("\nResult should be %f\n\n", C*A); + + printf("*** DIV\n\n"); + printf("Result is "); + f64_print(f64_div(a,b)); + printf("\nResult should be %f\n\n", A/B); + printf("Result is "); + f64_print(f64_div(b,c)); + printf("\nResult should be %f\n\n", B/C); + printf("Result is "); + f64_print(f64_div(c,a)); + printf("\nResult should be %f\n\n", C/A); + + printf("*** SQRT\n\n"); + printf("Result is "); + f64_print(f64_sqrt(a)); + f64_sqrt(a); + printf("\nResult should be %f\n\n", sqrt(A)); + printf("Result is "); + f64_print(f64_sqrt(b)); + printf("\nResult should be %f\n\n", sqrt(B)); + printf("Result is "); + f64_print(f64_sqrt(c)); + printf("\nResult should be %f\n\n", sqrt(C)); + + + return 0; +} + + +int f32_test(void) +{ + f32 a,b,c; + + a = f32_from_double(A); + b = f32_from_double(B); + c = f32_from_double(C); + + printf("************ F32\n\n"); + + printf("*** ADD\n\n"); + printf("Result is "); + f32_print(f32_add(a,b)); + printf("\nResult should be %f\n\n", A+B); + printf("Result is "); + f32_print(f32_add(b,c)); + printf("\nResult should be %f\n\n", B+C); + printf("Result is "); + f32_print(f32_add(c,a)); + printf("\nResult should be %f\n\n", C+A); + + printf("*** SUB\n\n"); + printf("Result is "); + f32_print(f32_sub(a,b)); + printf("\nResult should be %f\n\n", A-B); + printf("Result is "); + f32_print(f32_sub(b,c)); + printf("\nResult should be %f\n\n", B-C); + printf("Result is "); + f32_print(f32_sub(c,a)); + printf("\nResult should be %f\n\n", C-A); + + printf("*** INV\n\n"); + printf("Result is "); + f32_print(f32_inv(a)); + printf("\nResult should be %f\n\n", 1.0/A); + printf("Result is "); + f32_print(f32_inv(b)); + printf("\nResult should be %f\n\n", 1.0/B); + printf("Result is "); + f32_print(f32_inv(c)); + printf("\nResult should be %f\n\n", 1.0/C); + + printf("*** MUL\n\n"); + printf("Result is "); + f32_print(f32_mul(a,b)); + printf("\nResult should be %f\n\n", A*B); + printf("Result is "); + f32_print(f32_mul(b,c)); + printf("\nResult should be %f\n\n", B*C); + printf("Result is "); + f32_print(f32_mul(c,a)); + printf("\nResult should be %f\n\n", C*A); + + printf("*** DIV\n\n"); + printf("Result is "); + f32_print(f32_div(a,b)); + printf("\nResult should be %f\n\n", A/B); + printf("Result is "); + f32_print(f32_div(b,c)); + printf("\nResult should be %f\n\n", B/C); + printf("Result is "); + f32_print(f32_div(c,a)); + printf("\nResult should be %f\n\n", C/A); + + printf("*** SQRT\n\n"); + printf("Result is "); + f32_print(f32_sqrt(a)); + printf("\nResult should be %f\n\n", sqrt(A)); + printf("Result is "); + f32_print(f32_sqrt(b)); + printf("\nResult should be %f\n\n", sqrt(B)); + printf("Result is "); + f32_print(f32_sqrt(c)); + printf("\nResult should be %f\n\n", sqrt(C)); + + + return 0; +} + +int f16_test(void) +{ + f16 a,b,c; + + a = f16_from_double(A); + b = f16_from_double(B); + c = f16_from_double(C); + + printf("************ F16\n\n"); + + printf("*** ADD\n\n"); + printf("Result is "); + f16_print(f16_add(a,b)); + printf("\nResult should be %f\n\n", A+B); + printf("Result is "); + f16_print(f16_add(b,c)); + printf("\nResult should be %f\n\n", B+C); + printf("Result is "); + f16_print(f16_add(c,a)); + printf("\nResult should be %f\n\n", C+A); + + printf("*** SUB\n\n"); + printf("Result is "); + f16_print(f16_sub(a,b)); + printf("\nResult should be %f\n\n", A-B); + printf("Result is "); + f16_print(f16_sub(b,c)); + printf("\nResult should be %f\n\n", B-C); + printf("Result is "); + f16_print(f16_sub(c,a)); + printf("\nResult should be %f\n\n", C-A); + + printf("*** INV\n\n"); + printf("Result is "); + f16_print(f16_inv(a)); + printf("\nResult should be %f\n\n", 1.0/A); + printf("Result is "); + f16_print(f16_inv(b)); + printf("\nResult should be %f\n\n", 1.0/B); + printf("Result is "); + f16_print(f16_inv(c)); + printf("\nResult should be %f\n\n", 1.0/C); + + printf("*** MUL\n\n"); + printf("Result is "); + f16_print(f16_mul(a,b)); + printf("\nResult should be %f\n\n", A*B); + printf("Result is "); + f16_print(f16_mul(b,c)); + printf("\nResult should be %f\n\n", B*C); + printf("Result is "); + f16_print(f16_mul(c,a)); + printf("\nResult should be %f\n\n", C*A); + + printf("*** DIV\n\n"); + printf("Result is "); + f16_print(f16_div(a,b)); + printf("\nResult should be %f\n\n", A/B); + printf("Result is "); + f16_print(f16_div(b,c)); + printf("\nResult should be %f\n\n", B/C); + printf("Result is "); + f16_print(f16_div(c,a)); + printf("\nResult should be %f\n\n", C/A); + + printf("*** SQRT\n\n"); + printf("Result is "); + f16_print(f16_sqrt(a)); + printf("\nResult should be %f\n\n", sqrt(A)); + printf("Result is "); + f16_print(f16_sqrt(b)); + printf("\nResult should be %f\n\n", sqrt(B)); + printf("Result is "); + f16_print(f16_sqrt(c)); + printf("\nResult should be %f\n\n", sqrt(C)); + + + return 0; +} + +int main(void) +{ +#ifndef HOST_VERSION + uart_init(); + fdevopen((void*)uart0_dev_send, (void*)uart0_dev_recv); + + sei(); +#endif + + f64_test(); + f32_test(); + f16_test(); + return 0; +} diff --git a/modules/base/math/fixed_point/test/uart_config.h b/modules/base/math/fixed_point/test/uart_config.h new file mode 100644 index 0000000..8bd18fe --- /dev/null +++ b/modules/base/math/fixed_point/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.4.4.1 2006-11-26 21:06:01 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/base/math/geometry/CVS/Entries b/modules/base/math/geometry/CVS/Entries new file mode 100644 index 0000000..8d4939d --- /dev/null +++ b/modules/base/math/geometry/CVS/Entries @@ -0,0 +1,8 @@ +/Makefile/1.1.2.1/Sat May 2 10:00:36 2009//Tb_zer0 +/lines.c/1.1.2.2/Mon May 18 12:26:49 2009//Tb_zer0 +/lines.h/1.1.2.2/Mon May 18 12:26:49 2009//Tb_zer0 +/polygon.c/1.1.2.2/Mon May 18 12:26:49 2009//Tb_zer0 +/polygon.h/1.1.2.2/Mon May 18 12:26:49 2009//Tb_zer0 +/vect_base.c/1.1.2.1/Sat May 2 10:00:35 2009//Tb_zer0 +/vect_base.h/1.1.2.1/Sat May 2 10:00:35 2009//Tb_zer0 +D/test//// diff --git a/modules/base/math/geometry/CVS/Repository b/modules/base/math/geometry/CVS/Repository new file mode 100644 index 0000000..973e31e --- /dev/null +++ b/modules/base/math/geometry/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math/geometry diff --git a/modules/base/math/geometry/CVS/Root b/modules/base/math/geometry/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/geometry/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/geometry/CVS/Tag b/modules/base/math/geometry/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/geometry/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/geometry/CVS/Template b/modules/base/math/geometry/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/geometry/Makefile b/modules/base/math/geometry/Makefile new file mode 100644 index 0000000..aa808b6 --- /dev/null +++ b/modules/base/math/geometry/Makefile @@ -0,0 +1,9 @@ +TARGET = geometry + +# List C source files here. (C dependencies are automatically generated.) +SRC = vect_base.c lines.c polygon.c + + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/math/geometry/lines.c b/modules/base/math/geometry/lines.c new file mode 100755 index 0000000..a31834f --- /dev/null +++ b/modules/base/math/geometry/lines.c @@ -0,0 +1,223 @@ +#include <aversive.h> + +#include <stdint.h> +#include <inttypes.h> +#include <stdlib.h> +#include <stdio.h> +#include <math.h> + +#include <vect_base.h> +#include <lines.h> + +#define DEBUG 0 + +#if DEBUG == 1 +#define debug_printf(args...) printf(args) +#else +#define debug_printf(args...) +#endif + +/* return values : + * 0 dont cross + * 1 cross + * 2 parallel crossing + * + * p argument is the crossing point coordinates (dummy for 0 or 2 + * result) + */ +uint8_t +intersect_line(const line_t *l1, const line_t *l2, point_t *p) +{ + double tmp1, tmp2; + + debug_printf("l1:%2.2f,%2.2f,%2.2f l2:%2.2f,%2.2f,%2.2f\n", + l1->a, l1->b, l1->c, l2->a, l2->b, l2->c); + /* if dummy lines */ + if ((l1->a == 0 && l1->b == 0) || (l2->a == 0 && l2->b == 0)) + return 0; + + if (l1->a == 0) { + if (l2->a == 0) { + if (l1->b*l2->c == l2->b*l1->c) + return 2; + return 0; + } + + /* by + c = 0 + * a'x + b'y + c' = 0 */ + /* + p->y = -l1->c/l1->b; + p->x = -(l2->b*p->y + l2->c)/l2->a; + */ + p->y = -l1->c/l1->b; + p->x = -(l2->b*(-l1->c) + l2->c*l1->b)/(l2->a*l1->b); + return 1; + } + + if (l1->b == 0) { + if (l2->b == 0) { + if (l1->a*l2->c == l2->a*l1->c) + return 2; + return 0; + } + /* ax + c = 0 + * a'x + b'y + c' = 0 */ + + /* + p->x = -l1->c/l1->a; + p->y = -(l2->a*p->x + l2->c)/l2->b; + */ + p->x = -l1->c/l1->a; + p->y = -(l2->a*(-l1->c) + l2->c*(l1->a))/(l2->b*l1->a); + return 1; + } + + /* parallel lines */ + if (l2->a*l1->b-l1->a*l2->b == 0) { + if (l1->a*l2->c == l2->a*l1->c) + return 2; + return 0; + } + /* + p->y = (l1->a*l2->c - l1->c*l2->a)/(l2->a*l1->b - l1->a*l2->b); + p->x = -(l1->b*p->y+l1->c)/l1->a; + */ + tmp1 = (l1->a*l2->c - l1->c*l2->a); + tmp2 = (l2->a*l1->b - l1->a*l2->b); + p->y = tmp1 / tmp2; + p->x = -(l1->b*tmp1 + l1->c*tmp2) / (l1->a*tmp2); + return 1; +} + +void pts2line(const point_t *p1, const point_t *p2, line_t *l) +{ + double p1x, p1y, p2x, p2y; + + p1x = p1->x; + p1y = p1->y; + p2x = p2->x; + p2y = p2->y; + + + l->a = -(p2y - p1y); + l->b = (p2x - p1x); + l->c = -(l->a * p1x + l->b * p1y); + + debug_printf("%s: %2.2f, %2.2f, %2.2f\r\n", + __FUNCTION__, l->a, l->b, l->c); +} + +void proj_pt_line(const point_t * p, const line_t * l, point_t * p_out) +{ + line_t l_tmp; + + l_tmp.a = l->b; + l_tmp.b = -l->a; + l_tmp.c = -l_tmp.a*p->x - l_tmp.b*p->y; + + p_out->y = (l_tmp.a*l->c - l->a*l_tmp.c) / (l->a*l_tmp.b - l_tmp.a*l->b); + p_out->x = (l->b*l_tmp.c - l_tmp.b*l->c) / (l->a*l_tmp.b - l_tmp.a*l->b); + +} + + + +/* return values: + * 0 dont cross + * 1 cross + * 2 cross on point + * 3 parallel and one point in + * + * p argument is the crossing point coordinates (dummy for 0 1 or 3 + * result) + */ +uint8_t +intersect_segment(const point_t *s1, const point_t *s2, + const point_t *t1, const point_t *t2, + point_t *p) +{ + line_t l1, l2; + uint8_t ret; + int8_t u1, u2; + vect_t v, w; + + debug_printf("s1:%"PRIi32",%"PRIi32" s2:%"PRIi32",%"PRIi32" " + "t1:%"PRIi32",%"PRIi32" t2:%"PRIi32",%"PRIi32"\r\n", + s1->x, s1->y, s2->x, s2->y, + t1->x, t1->y, t2->x, t2->y); + + pts2line(s1, s2, &l1); + pts2line(t1, t2, &l2); + + ret = intersect_line(&l1, &l2, p); + if (!ret) + return 0; + if (ret == 2) { + v.x = t1->x - s1->x; + v.y = t1->y - s1->y; + w.x = t1->x - s2->x; + w.y = t1->y - s2->y; + *p = *t1; + if (vect_pscal_sign(&v, &w)<=0) + return 3; + + v.x = t2->x - s1->x; + v.y = t2->y - s1->y; + w.x = t2->x - s2->x; + w.y = t2->y - s2->y; + *p = *t2; + if (vect_pscal_sign(&v, &w)<=0) + return 3; + return 0; + } + + + /* if points equal */ + if (s1->x == t1->x && s1->y == t1->y) { + *p = *s1; + return 2; + } + if (s1->x == t2->x && s1->y == t2->y) { + *p = *s1; + return 2; + } + if (s2->x == t1->x && s2->y == t1->y) { + *p = *s2; + return 2; + } + if (s2->x == t2->x && s2->y == t2->y) { + *p = *s2; + return 2; + } + + debug_printf("px=%" PRIi32 " py=%" PRIi32 "\n", p->x, p->y); + + /* Consider as parallel if intersection is too far */ + if (ABS(p->x) > (1L << 15) || ABS(p->y) > (1L << 15)) + return 0; + + /* if prod scal neg: cut in middle of segment */ + /* todo for both segment */ + v.x = p->x-s1->x; + v.y = p->y-s1->y; + w.x = p->x-s2->x; + w.y = p->y-s2->y; + u1 = vect_pscal_sign(&v, &w ); + + v.x = p->x-t1->x; + v.y = p->y-t1->y; + w.x = p->x-t2->x; + w.y = p->y-t2->y; + u2 = vect_pscal_sign(&v, &w); + + debug_printf("u1=%d u2=%d\n", u1, u2); + + if (u1>0 || u2>0) + return 0; + + if (u1==0 || u2==0) + return 2; + + return 1; + +} diff --git a/modules/base/math/geometry/lines.h b/modules/base/math/geometry/lines.h new file mode 100755 index 0000000..a6cf421 --- /dev/null +++ b/modules/base/math/geometry/lines.h @@ -0,0 +1,20 @@ +typedef struct _line { + double a; + double b; + double c; +} line_t; + + +void +pts2line(const point_t *p1, const point_t *p2, line_t *l); + +void +proj_pt_line(const point_t * p, const line_t * l, point_t * p_out); + +uint8_t +intersect_line(const line_t *l1, const line_t *l2, point_t *p); + +uint8_t +intersect_segment(const point_t *s1, const point_t *s2, + const point_t *t1, const point_t *t2, + point_t *p); diff --git a/modules/base/math/geometry/polygon.c b/modules/base/math/geometry/polygon.c new file mode 100755 index 0000000..d62179c --- /dev/null +++ b/modules/base/math/geometry/polygon.c @@ -0,0 +1,310 @@ +#include <stdint.h> +#include <inttypes.h> +#include <stdlib.h> +#include <stdio.h> +#include <math.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> + +#define DEBUG 0 + +#if DEBUG == 1 +#define debug_printf(args...) printf(args) +#else +#define debug_printf(args...) +#endif + +/* default bounding box is (0,0) (100,100) */ +static int32_t bbox_x1 = 0; +static int32_t bbox_y1 = 0; +static int32_t bbox_x2 = 100; +static int32_t bbox_y2 = 100; + +void polygon_set_boundingbox(int32_t x1, int32_t y1, int32_t x2, int32_t y2) +{ + bbox_x1 = x1; + bbox_y1 = y1; + bbox_x2 = x2; + bbox_y2 = y2; +} + +uint8_t is_in_boundingbox(const point_t *p) +{ + if (p->x >= bbox_x1 && + p->x <= bbox_x2 && + p->y >= bbox_y1 && + p->y <= bbox_y2) + return 1; + return 0; +} + +/* Test if a point is in a polygon (including edges) + * 0 not inside + * 1 inside + * 2 on edge + */ +uint8_t +is_in_poly(const point_t *p, poly_t *pol) +{ + uint8_t i; + uint8_t ii; + int8_t z; + uint8_t ret=1; + vect_t v, w; + + for (i=0;i<pol->l;i++) { + /* is a polygon point */ + if (p->x == pol->pts[i].x && p->y == pol->pts[i].y) + return 2; + } + + for (i=0;i<pol->l;i++) { + + ii = (i+1)%pol->l; + v.x = pol->pts[ii].x-p->x; + v.y = pol->pts[ii].y-p->y; + w.x = pol->pts[i].x-p->x; + w.y = pol->pts[i].y-p->y; + z = vect_pvect_sign(&v, &w ); + if (z>0) + return 0; + if (z==0) + ret=2; + } + + return ret; +} + +/* public wrapper for is_in_poly() */ +uint8_t is_point_in_poly(poly_t *pol, int16_t x, int16_t y) +{ + point_t p; + p.x = x; + p.y = y; + return is_in_poly(&p, pol); +} + +/* Is segment crossing polygon? (including edges) + * 0 don't cross + * 1 cross + * 2 on a side + * 3 touch out (a segment boundary is on a polygon edge, + * and the second segment boundary is out of the polygon) + */ +uint8_t +is_crossing_poly(point_t p1, point_t p2, point_t *intersect_pt, + poly_t *pol) +{ + uint8_t i; + uint8_t ret; + point_t p; + uint8_t ret1, ret2; + uint8_t cpt=0; + + debug_printf("%" PRIi32 " %" PRIi32 " -> %" PRIi32 " %" PRIi32 " crossing poly %p ?\n", + p1.x, p1.y, p2.x, p2.y, pol); + debug_printf("poly is : "); + for (i=0; i<pol->l; i++) { + debug_printf("%" PRIi32 ",%" PRIi32 " ", pol->pts[i].x, pol->pts[i].y); + } + debug_printf("\n"); + + for (i=0;i<pol->l;i++) { + ret = intersect_segment(&p1, &p2, &pol->pts[i], &pol->pts[(i+1)%pol->l], &p); + debug_printf("%" PRIi32 ",%" PRIi32 " -> %" PRIi32 ",%" PRIi32 + " return %d\n", pol->pts[i].x, pol->pts[i].y, + pol->pts[(i+1)%pol->l].x, pol->pts[(i+1)%pol->l].y, ret); + + + switch(ret) { + case 0: + break; + case 1: + if (intersect_pt) + *intersect_pt = p; + return 1; + break; + case 2: + cpt++; + if (intersect_pt) + *intersect_pt = p; + + break; + case 3: + if (intersect_pt) + *intersect_pt = p; + return 2; + break; + } + } + + if (cpt==3 ||cpt==4) + return 1; + + ret1 = is_in_poly(&p1, pol); + /* XXX opt */ + ret2 = is_in_poly(&p2, pol); + + debug_printf("is in poly: p1 %d p2: %d cpt %d\r\n", ret1, ret2, cpt); + + debug_printf("p intersect: %"PRIi32" %"PRIi32"\r\n", p.x, p.y); + + + if (cpt==0) { + if (ret1==1 || ret2==1) + return 1; + return 0; + } + + + if (cpt==1) { + if (ret1==1 || ret2==1) + return 1; + return 3; + } + if (cpt==2) { + if (ret1==1 || ret2==1) + return 1; + if (ret1==0 || ret2==0) + return 3; + return 1; + } + + return 1; +} + +/* Giving the list of poygons, compute the graph of "visibility rays". + * This rays array is composed of indexes representing 2 polygon + * vertices that can "see" each others: + * + * i : the first polygon number in the input polygon list + * i+1: the vertex index of this polygon (vertex 1) + * i+2: the second polygon number in the input polygon list + * i+3: the vertex index of this polygon (vertex 2) + * + * Here, vertex 1 can "see" vertex 2 in our visibility graph + * + * As the first polygon is not a real polygon but the start/stop + * point, the polygon is NOT an ocluding polygon (but its vertices + * are used to compute visibility to start/stop points) + */ + +uint8_t +calc_rays(poly_t *polys, uint8_t npolys, uint8_t *rays) +{ + uint8_t i, ii, index; + uint8_t ray_n=0; + uint8_t is_ok; + uint8_t n; + uint8_t pt1, pt2; + + /* !\\first poly is the start stop point */ + + /* 1: calc inner polygon rays + * compute for each polygon edges, if the vertices can see each others + * (usefull if interlaced polygons) + */ + + for (i=0; i<npolys; i++) { + debug_printf("%s(): poly num %d/%d\n", __FUNCTION__, i, npolys); + for (ii=0; ii<polys[i].l; ii++) { + debug_printf("%s() line num %d/%d\n", __FUNCTION__, ii, polys[i].l); + if (! is_in_boundingbox(&polys[i].pts[ii])) + continue; + is_ok = 1; + n = (ii+1)%polys[i].l; + + if (!(is_in_boundingbox(&polys[i].pts[n]))) + continue; + + + /* check if a polygon cross our ray */ + for (index=1; index<npolys; index++) { + + /* don't check polygon against itself */ + if (index == i) continue; + + if (is_crossing_poly(polys[i].pts[ii], polys[i].pts[n], NULL, + &polys[index]) == 1) { + is_ok = 0; + debug_printf("is_crossing_poly() returned 1\n"); + break; + } + } + /* if ray is not crossed, add it */ + if (is_ok) { + rays[ray_n++] = i; + rays[ray_n++] = ii; + rays[ray_n++] = i; + rays[ray_n++] = n; + } + } + } + + + /* 2: calc inter polygon rays. + * Visibility of inter-polygon vertices.*/ + + /* For all poly */ + for (i=0; i<npolys-1; i++) { + for (pt1=0;pt1<polys[i].l;pt1++) { + + if (!(is_in_boundingbox(&polys[i].pts[pt1]))) + continue; + + /* for next poly */ + for (ii=i+1; ii<npolys; ii++) { + for (pt2=0;pt2<polys[ii].l;pt2++) { + + if (!(is_in_boundingbox(&polys[ii].pts[pt2]))) + continue; + + is_ok=1; + /* test if a poly cross */ + for (index=1;index<npolys;index++) { + if (is_crossing_poly(polys[i].pts[pt1], + polys[ii].pts[pt2], NULL, + &polys[index]) == 1) { + is_ok=0; + break; + } + } + /* if not crossed, we found a vilisity ray */ + if (is_ok) { + rays[ray_n++] = i; + rays[ray_n++] = pt1; + rays[ray_n++] = ii; + rays[ray_n++] = pt2; + } + } + } + } + } + + + return ray_n; +} + +/* Compute the weight of every rays: the length of the rays is used + * here. + * + * Note the +1 is a little hack to introduce a preference between to + * possiblity path: If we have 3 checpoint aligned in a path (say A, + * B, C) the algorithm will prefer (A, C) instead of (A, B, C) */ +void +calc_rays_weight(poly_t *polys, uint8_t npolys, uint8_t *rays, + uint8_t ray_n, uint16_t *weight) +{ + uint8_t i; + vect_t v; + + for (i=0;i<ray_n;i+=4) { + v.x = polys[rays[i]].pts[rays[i+1]].x - polys[rays[i+2]].pts[rays[i+3]].x; + v.y = polys[rays[i]].pts[rays[i+1]].y - polys[rays[i+2]].pts[rays[i+3]].y; + weight[i/4] = vect_norm(&v) + 1; + } +} + + + diff --git a/modules/base/math/geometry/polygon.h b/modules/base/math/geometry/polygon.h new file mode 100755 index 0000000..83468d8 --- /dev/null +++ b/modules/base/math/geometry/polygon.h @@ -0,0 +1,78 @@ +#ifndef _POLYGON_H_ +#define _POLYGON_H_ + +typedef struct _poly { + point_t * pts; + uint8_t l; +} poly_t; + +/* XXX add const, fix arg order */ + +/* + * return: + * 0 not inside + * 1 inside + * 2 on edge + */ +uint8_t is_in_poly(const point_t *p, poly_t *pol); + +/* + * public wrapper for is_in_poly() + * 0 not inside + * 1 inside + * 2 on edge + */ +uint8_t is_point_in_poly(poly_t *pol, int16_t x, int16_t y); + +/* Is segment crossing polygon? (including edges) + * 0 don't cross + * 1 cross + * 2 on a side + * 3 touch out (a segment boundary is on a polygon edge, + * and the second segment boundary is out of the polygon) + * Fill the intersect_pt if not NULL. + */ +uint8_t +is_crossing_poly(point_t p1, point_t p2, point_t *intersect_pt, + poly_t *pol); + +/* + * set coords of bounding box. + */ +void polygon_set_boundingbox(int32_t x1, int32_t y1, int32_t x2, int32_t y2); + +/* + * return 1 if a point is in the bounding box. + */ +uint8_t is_in_boundingbox(const point_t *p); + +/* Giving the list of poygons, compute the graph of "visibility rays". + * This rays array is composed of indexes representing 2 polygon + * vertices that can "see" each others: + * + * i : the first polygon number in the input polygon list + * i+1: the vertex index of this polygon (vertex 1) + * i+2: the second polygon number in the input polygon list + * i+3: the vertex index of this polygon (vertex 2) + * + * Here, vertex 1 can "see" vertex 2 in our visibility graph + * + * As the first polygon is not a real polygon but the start/stop + * point, the polygon is NOT an ocluding polygon (but its vertices + * are used to compute visibility to start/stop points) + */ + +uint8_t +calc_rays(poly_t *polys, uint8_t npolys, uint8_t *rays); + +/* Compute the weight of every rays: the length of the rays is used + * here. + * + * Note the +1 is a little hack to introduce a preference between to + * possiblity path: If we have 3 checpoint aligned in a path (say A, + * B, C) the algorithm will prefer (A, C) instead of (A, B, C) */ +void +calc_rays_weight(poly_t *polys, uint8_t npolys, uint8_t *rays, + uint8_t ray_n, uint16_t *weight); + +#endif diff --git a/modules/base/math/geometry/test/.config b/modules/base/math/geometry/test/.config new file mode 100644 index 0000000..ef5935c --- /dev/null +++ b/modules/base/math/geometry/test/.config @@ -0,0 +1,279 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +CONFIG_MODULE_VECT2=y +CONFIG_MODULE_GEOMETRY=y +CONFIG_MODULE_GEOMETRY_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_9BITS is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/modules/base/math/geometry/test/CVS/Entries b/modules/base/math/geometry/test/CVS/Entries new file mode 100644 index 0000000..e3e1209 --- /dev/null +++ b/modules/base/math/geometry/test/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.1.2.2/Mon May 18 12:26:49 2009//Tb_zer0 +/Makefile/1.1.2.1/Sat May 2 10:00:35 2009//Tb_zer0 +/error_config.h/1.1.2.1/Sat May 2 10:00:35 2009//Tb_zer0 +/main.c/1.1.2.2/Mon May 18 12:26:49 2009//Tb_zer0 +D diff --git a/modules/base/math/geometry/test/CVS/Repository b/modules/base/math/geometry/test/CVS/Repository new file mode 100644 index 0000000..23e6c41 --- /dev/null +++ b/modules/base/math/geometry/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math/geometry/test diff --git a/modules/base/math/geometry/test/CVS/Root b/modules/base/math/geometry/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/geometry/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/geometry/test/CVS/Tag b/modules/base/math/geometry/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/geometry/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/geometry/test/CVS/Template b/modules/base/math/geometry/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/geometry/test/Makefile b/modules/base/math/geometry/test/Makefile new file mode 100644 index 0000000..8e56dbc --- /dev/null +++ b/modules/base/math/geometry/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/base/math/geometry/test/error_config.h b/modules/base/math/geometry/test/error_config.h new file mode 100644 index 0000000..c1fae80 --- /dev/null +++ b/modules/base/math/geometry/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2009-05-02 10:00:35 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/base/math/geometry/test/main.c b/modules/base/math/geometry/test/main.c new file mode 100755 index 0000000..ad5977e --- /dev/null +++ b/modules/base/math/geometry/test/main.c @@ -0,0 +1,285 @@ +#include <inttypes.h> +#include <stdint.h> +#include <math.h> + +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> + +#include <stdio.h> + +#define EPSILON 0.000001 + +int main(void) +{ + vect_t v, w; + int32_t ps; + float n1, n2; + float a; + + point_t p1, p2, p3, p4, p5, p6, p7, p; + point_t p8, p9, p10, p11; + line_t l1, l2, l3, l4; + uint8_t ret; + + poly_t poly1, poly2; + + point_t poly_pts1[4]; + point_t poly_pts2[5]; + + polygon_set_boundingbox(25, 25, 275, 185); + + /* basic vect test */ + v.x = 1; + v.y = 0; + + vect_rot_trigo(&v); + if (v.x != 0 || v.y != 1) + printf("error rot rigo ok1\r\n"); + + vect_rot_trigo(&v); + vect_rot_trigo(&v); + vect_rot_trigo(&v); + + if (v.x != 1 || v.y != 0) + printf("error rot trigo ok2\r\n"); + + vect_rot_retro(&v); + if (v.x != 0 || v.y != -1) + printf("error rot rigo ok1\r\n"); + + vect_rot_retro(&v); + vect_rot_retro(&v); + vect_rot_retro(&v); + + if (v.x != 1 || v.y != 0) + printf("error rot retro ok2\r\n"); + + + + w.x = 2; + w.y = 2; + ps = vect_pscal(&v, &w); + + n1 = vect_norm(&v); + n2 = vect_norm(&w); + if (fabs(n1-1.)>EPSILON || fabs(n2-2.828427)>EPSILON) + printf("error in norm\r\n"); + + a = acos((float)ps/(n1*n2))*180./M_PI; + + if (fabs(a-45.)>EPSILON) + printf("error in norm/pscal\r\n"); + + a = vect_get_angle(&v, &w)*180./M_PI; + if (fabs(a-45.)>EPSILON) + printf("error in get angle\r\n"); + + /* basic lines tests */ + p1.x = 0; + p1.y = 0; + + p2.x = 0; + p2.y = 10; + + pts2line(&p1, &p2, &l1); + printf("%2.2f %2.2f %2.2f\r\n", l1.a, l1.b, l1.c); + + + p3.x = 10; + p3.y = 0; + + pts2line(&p1, &p3, &l2); + printf("%2.2f %2.2f %2.2f\r\n", l2.a, l2.b, l2.c); + + + p4.x = 10; + p4.y = 10; + + p5.x = 20; + p5.y = 20; + + pts2line(&p4, &p5, &l3); + printf("%2.2f %2.2f %2.2f\r\n", l3.a, l3.b, l3.c); + + p6.x = 30; + p6.y = 0; + + p7.x = 0; + p7.y = 30; + + pts2line(&p6, &p7, &l4); + printf("%2.2f %2.2f %2.2f\r\n", l4.a, l4.b, l4.c); + + + intersect_line(&l1, &l2, &p); + printf("* %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + + intersect_line(&l1, &l4, &p); + printf("* %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + + intersect_line(&l2, &l4, &p); + printf("* %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + + intersect_line(&l3, &l4, &p); + printf("* %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + + ret = intersect_segment(&p1, &p2, &p4, &p5, &p); + printf("%d (%" PRIi32 " %" PRIi32 ")\r\n", ret, p.x, p.y); + if (ret != 0) + printf("error in segment cros\r\n"); + + ret = intersect_segment(&p4, &p5, &p6, &p7, &p); + printf("%d (%" PRIi32 " %" PRIi32 ")\r\n", ret, p.x, p.y); + if (ret != 1) + printf("error in segment cros\r\n"); + + ret = intersect_segment(&p1, &p2, &p1, &p3, &p); + printf("%d (%" PRIi32 " %" PRIi32 ")\r\n", ret, p.x, p.y); + if (ret != 2) + printf("error in segment cros\r\n"); + + p8.x = 105; + p8.y = 60; + p9.x = 200; + p9.y = 150; + p10.x = 195; + p10.y = 150; + p11.x = 195; + p11.y = 60; + ret = intersect_segment(&p8, &p9, &p10, &p11, &p); + printf("%d (%" PRIi32 " %" PRIi32 ")\r\n", ret, p.x, p.y); + if (ret != 1) + printf("error in segment cros\r\n"); + + + + + p6.x = 30; + p6.y = 0; + + p7.x = 0; + p7.y = 30; + + p8.x = 10; + p8.y = 10; + + pts2line(&p6, &p7, &l3); + proj_pt_line(&p8, &l3, &p); + printf("proj: %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + if (p.x != 15 || p.y != 15) + printf("error in proj 1\r\n"); + + + p6.x = 0; + p6.y = 0; + + p7.x = 0; + p7.y = 30; + + p8.x = 10; + p8.y = 10; + + pts2line(&p6, &p7, &l3); + proj_pt_line(&p8, &l3, &p); + printf("proj: %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + if (p.x != 0 || p.y != 10) + printf("error in proj 2\r\n"); + + + p6.x = 30; + p6.y = 0; + + p7.x = 0; + p7.y = 0; + + p8.x = 10; + p8.y = 10; + + pts2line(&p6, &p7, &l3); + proj_pt_line(&p8, &l3, &p); + printf("proj: %" PRIi32 " %" PRIi32 "\r\n", p.x, p.y); + if (p.x != 10 || p.y != 0) + printf("error in proj 3\r\n"); + + + p1.x = 0; + p1.y = 10; + + p2.x = 20; + p2.y = 20; + + pts2line(&p1, &p2, &l1); + printf("%2.2f %2.2f %2.2f\r\n", l1.a, l1.b, l1.c); + + p2.x = 0; + p2.y = 10; + + p1.x = 10; + p1.y = -10; + + pts2line(&p1, &p2, &l1); + printf("%2.2f %2.2f %2.2f\r\n", l1.a, l1.b, l1.c); + + + /* basic poly tests */ + + poly1.pts = poly_pts1; + poly1.l = 4; + + poly2.pts = poly_pts2; + poly2.l = 5; + + + poly1.pts[0].x = 0; + poly1.pts[0].y = 0; + + poly1.pts[0].x = 1; + poly1.pts[0].y = 0; + + poly1.pts[0].x = 1; + poly1.pts[0].y = 1; + + poly1.pts[0].x = 0; + poly1.pts[0].y = 1; + + + + poly1.pts[0].x = 0; + poly1.pts[0].y = 0; + + poly1.pts[1].x = 10; + poly1.pts[1].y = 0; + + poly1.pts[2].x = 20; + poly1.pts[2].y = 20; + + poly1.pts[3].x = 0; + poly1.pts[3].y = 10; + + + ret = is_in_poly(&p6, &poly1); + printf("%d\r\n", ret); + if (ret!=0) + printf("error in is in poly\r\n"); + + + + ret = is_in_poly(&p4, &poly1); + printf("%d\r\n", ret); + if (ret!=1) + printf("error in is in poly\r\n"); + + + ret = is_in_poly(&p1, &poly1); + printf("%d\r\n", ret); + if (ret!=2) + printf("error in is in poly\r\n"); + + + + + return 0; + + +} diff --git a/modules/base/math/geometry/vect_base.c b/modules/base/math/geometry/vect_base.c new file mode 100755 index 0000000..f36724c --- /dev/null +++ b/modules/base/math/geometry/vect_base.c @@ -0,0 +1,78 @@ +#include <stdint.h> +#include <math.h> +#include <vect_base.h> + +/* Return scalar product */ +int32_t +vect_pscal(vect_t *v, vect_t *w) +{ + return v->x * w->x + v->y * w->y; +} + +/* Return Z of vectorial product */ +int32_t +vect_pvect(vect_t *v, vect_t *w) +{ + return v->x*w->y - v->y*w->x; +} + +/* Return scalar product */ +int8_t +vect_pscal_sign(vect_t *v, vect_t *w) +{ + int32_t z; + z = vect_pscal(v, w); + if (z==0) + return 0; + return z>0?1:-1; +} + +/* Return Z of vectorial product */ +int8_t +vect_pvect_sign(vect_t *v, vect_t *w) +{ + int32_t z; + z = vect_pvect(v, w); + if (z==0) + return 0; + return z>0?1:-1; +} + +/* norm of a vector */ +float +vect_norm(vect_t *v) +{ + return sqrt(v->x*v->x+v->y*v->y); +} + + + +void vect_rot_trigo(vect_t *v) +{ + int32_t s; + + s = v->x; + v->x= -v->y; + v->y = s; +} + +void vect_rot_retro(vect_t *v) +{ + int32_t s; + + s = v->x; + v->x= v->y; + v->y = -s; +} + + +float vect_get_angle(vect_t *v, vect_t *w) +{ + int32_t ps; + float n; + + ps = vect_pscal(v, w); + n = vect_norm(v) * vect_norm(w); + + return acos((float)ps/n); +} diff --git a/modules/base/math/geometry/vect_base.h b/modules/base/math/geometry/vect_base.h new file mode 100755 index 0000000..b9dda3f --- /dev/null +++ b/modules/base/math/geometry/vect_base.h @@ -0,0 +1,34 @@ +typedef struct _vect_t { + int32_t x; + int32_t y; +}vect_t; + +typedef struct _point_t { + int32_t x; + int32_t y; +}point_t; + + + +/* Return scalar product */ +int32_t +vect_pscal(vect_t *v, vect_t *w); + +/* Return Z of vectorial product */ +int32_t +vect_pvect(vect_t *v, vect_t *w); + +/* Return scalar product */ +int8_t +vect_pscal_sign(vect_t *v, vect_t *w); + +/* Return Z of vectorial product */ +int8_t +vect_pvect_sign(vect_t *v, vect_t *w); + +/* norm of a vector */ +float vect_norm(vect_t *v); +void vect_rot_trigo(vect_t *v); +void vect_rot_retro(vect_t *v); +float vect_get_angle(vect_t *v, vect_t *w); + diff --git a/modules/base/math/vect2/CVS/Entries b/modules/base/math/vect2/CVS/Entries new file mode 100644 index 0000000..aaa77f5 --- /dev/null +++ b/modules/base/math/vect2/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/vect2.c/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/vect2.h/1.3.4.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +D/test//// diff --git a/modules/base/math/vect2/CVS/Repository b/modules/base/math/vect2/CVS/Repository new file mode 100644 index 0000000..7aa5cac --- /dev/null +++ b/modules/base/math/vect2/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math/vect2 diff --git a/modules/base/math/vect2/CVS/Root b/modules/base/math/vect2/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/vect2/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/vect2/CVS/Tag b/modules/base/math/vect2/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/vect2/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/vect2/CVS/Template b/modules/base/math/vect2/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/vect2/Makefile b/modules/base/math/vect2/Makefile new file mode 100644 index 0000000..df4ea61 --- /dev/null +++ b/modules/base/math/vect2/Makefile @@ -0,0 +1,8 @@ +TARGET = vect2 + +# List C source files here. (C dependencies are automatically generated.) +SRC = vect2.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/math/vect2/test/.config b/modules/base/math/vect2/test/.config new file mode 100644 index 0000000..247b95d --- /dev/null +++ b/modules/base/math/vect2/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +CONFIG_MODULE_VECT2=y +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/base/math/vect2/test/CVS/Entries b/modules/base/math/vect2/test/CVS/Entries new file mode 100644 index 0000000..94fc322 --- /dev/null +++ b/modules/base/math/vect2/test/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.6.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/error_config.h/1.3.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/main.c/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +D diff --git a/modules/base/math/vect2/test/CVS/Repository b/modules/base/math/vect2/test/CVS/Repository new file mode 100644 index 0000000..7a56245 --- /dev/null +++ b/modules/base/math/vect2/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/math/vect2/test diff --git a/modules/base/math/vect2/test/CVS/Root b/modules/base/math/vect2/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/math/vect2/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/math/vect2/test/CVS/Tag b/modules/base/math/vect2/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/math/vect2/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/math/vect2/test/CVS/Template b/modules/base/math/vect2/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/math/vect2/test/Makefile b/modules/base/math/vect2/test/Makefile new file mode 100644 index 0000000..8e56dbc --- /dev/null +++ b/modules/base/math/vect2/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/base/math/vect2/test/error_config.h b/modules/base/math/vect2/test/error_config.h new file mode 100644 index 0000000..d54bb34 --- /dev/null +++ b/modules/base/math/vect2/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.3.6.1 2006-11-26 21:06:01 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/base/math/vect2/test/main.c b/modules/base/math/vect2/test/main.c new file mode 100755 index 0000000..ed1a851 --- /dev/null +++ b/modules/base/math/vect2/test/main.c @@ -0,0 +1,129 @@ +#include <vect2.h> + +#include <stdio.h> + +int main(void) +{ + vect2_pol vP; + + vect2_pol vP2; + vect2_pol vP3; + + vect2_cart vC; + + vect2_cart vC2; + vect2_cart vC3; + + + Real R = 1.45064930529587234; + /* theta must be [0,2*Pi] or fake errors will appears ( because of modulo ) */ + Real theta = 0.6734390282904231341; + + Real R2 = 120398490.45064930529587234; + /* theta2 must be [0,2*Pi] or fake errors will appears ( because of modulo ) */ + Real theta2 = 0.00001293892147; + + Real X = 2.5693042; + Real Y = 957802.203419598832952903; + + Real X2 = 984.1204192049021; + Real Y2 = 0.000034248975923; + + Real alpha = 93.1240812795; + + + /* */ + + vP.r = R; + vP.theta = theta; + + /* */ + + printf("\nTesting polar->cartesian->polar convertions...\n"); + + vect2_pol2cart(&vP,&vC); + + vect2_cart2pol(&vC,&vP); + + printf("Error on r = %f%%\nError on theta = %f%%\n",100 - 100*(vP.r)/R,100 - 100*(vP.theta)/theta); + + /* */ + + vC.x = X; + vC.y = Y; + + /* */ + + printf("\nTesting cartesian->polar->cartesian convertions...\n"); + + vect2_cart2pol(&vC,&vP); + vect2_pol2cart(&vP,&vC); + + printf("Error on x = %f%%\nError on y = %f%%\n",100 - 100*(vC.x)/X,100 - 100*(vC.y)/Y); + + + vC2.x = X2; + vC2.y = Y2; + + + /* Realise C = A + B puis C - B == A et C - A == B */ + + printf("\nTesting cartesian addition and sub...\nV3 <- V1 + V2\nV3 - V2 == V1\nV3 - V1 == V2\n"); + + vect2_add_cart(&vC,&vC2,&vC3); + vect2_sub_cart(&vC3,&vC2,&vC); + vect2_sub_cart(&vC3,&vC,&vC2); + + printf("Error on x1 = %f%%\nError on y1 = %f%%\n",100 - 100*(vC.x)/X,100 - 100*(vC.y)/Y); + printf("Error on x2 = %f%%\nError on y2 = %f%%\n",100 - 100*(vC2.x)/X2,100 - 100*(vC2.y)/Y2); + /* */ + + vP.r = R; + vP.theta = theta; + + vP2.r = R2; + vP2.theta = theta2; + + /* */ + + printf("\nTesting polar addition and sub...\nV3 <- V1 + V2\nV3 - V2 == V1\nV3 - V1 == V2\n"); + + vect2_add_pol(&vP,&vP2,&vP3); + vect2_sub_pol(&vP3,&vP2,&vP); + vect2_sub_pol(&vP3,&vP,&vP2); + + printf("Error on r1 = %f%%\nError on theta1 = %f%%\n",100 - 100*(vP.r)/R,100 - 100*(vP.theta)/theta); + printf("Error on r2 = %f%%\nError on theta2 = %f%%\n",100 - 100*(vP2.r)/R2,100 - 100*(vP2.theta)/theta2); + + /* */ + + vC.x = X; + vC.y = Y; + + /* */ + + printf("\nTesting cartesian scaling...\nV1 = alpha*V2\n(1/alpha)*V1 == V2\n"); + + vect2_scale_cart(&vC,alpha,&vC2); + vect2_scale_cart(&vC2,1/alpha,&vC); + + printf("Error on x = %f%%\nError on y = %f%%\n",100 - 100*(vC.x)/X,100 - 100*(vC.y)/Y); + + + /* */ + + vP.r = R; + vP.theta = theta; + + /* */ + + printf("\nTesting polar scaling...\nV1 = alpha*V2\n(1/alpha)*V1 == V2\n"); + + vect2_scale_pol(&vP,alpha,&vP2); + vect2_scale_pol(&vP2,1/alpha,&vP); + + printf("Error on r = %f%%\nError on theta = %f%%\n",100 - 100*(vP.r)/R,100 - 100*(vP.theta)/theta); + + + return 0; +} diff --git a/modules/base/math/vect2/vect2.c b/modules/base/math/vect2/vect2.c new file mode 100755 index 0000000..0bb7c3c --- /dev/null +++ b/modules/base/math/vect2/vect2.c @@ -0,0 +1,102 @@ +#include "vect2.h" + +#include <stdlib.h> +#include <math.h> + +/* Convert a polar vector to a cartesian one */ +void vect2_pol2cart(vect2_pol* vp, vect2_cart* vc) +{ + if(vp == NULL) return; + if(vc == NULL) return; + + vc->x = (Real)( (vp->r)*cos(vp->theta) ); + vc->y = (Real)( (vp->r)*sin(vp->theta) ); + + return; +} + +/* Convert a cartesian vector to a polar one */ +void vect2_cart2pol(vect2_cart* vc, vect2_pol* vp) +{ + if(vc == NULL) return; + if(vp == NULL) return; + + vp->r = (Real)( sqrt((vc->x)*(vc->x)+(vc->y)*(vc->y)) ); + vp->theta = (Real)atan2(vc->y,vc->x); + + return; +} + + +/* Add 2 polar vectors and return the result */ +void vect2_add_pol(vect2_pol* vp1, vect2_pol* vp2, vect2_pol* vresult) +{ + vect2_cart vc1; + vect2_cart vc2; + + vect2_cart vc; + + vect2_pol2cart(vp1,&vc1); + vect2_pol2cart(vp2,&vc2); + + vect2_add_cart(&vc1,&vc2,&vc); + + vect2_cart2pol(&vc,vresult); + + return; +} + +/* Add 2 cartesian vectors and return the result */ +void vect2_add_cart(vect2_cart* vc1, vect2_cart* vc2, vect2_cart* vresult) +{ + vresult->x = vc1->x + vc2->x; + vresult->y = vc1->y + vc2->y; + + return; +} + + +/* Substract 2 polar vectors and return the result */ +void vect2_sub_pol(vect2_pol* vp1, vect2_pol* vp2, vect2_pol* vresult) +{ + vect2_cart vc1; + vect2_cart vc2; + + vect2_cart vc; + + vect2_pol2cart(vp1,&vc1); + vect2_pol2cart(vp2,&vc2); + + vect2_sub_cart(&vc1,&vc2,&vc); + + vect2_cart2pol(&vc,vresult); + + return; +} + +/* Substract 2 cartesian vectors and return the result */ +void vect2_sub_cart(vect2_cart* vc1, vect2_cart* vc2, vect2_cart* vresult) +{ + vresult->x = vc1->x - vc2->x; + vresult->y = vc1->y - vc2->y; + + return; +} + + +/* Multiply a cartesian vector by a scalar and return the result */ +void vect2_scale_cart(vect2_cart* vc1, Real alpha, vect2_cart* vresult) +{ + vresult->x = alpha*(vc1->x); + vresult->y = alpha*(vc1->y); + + return; +} + +/* Multiply a polar vector by a scalar and return the result */ +void vect2_scale_pol(vect2_pol* vp1, Real alpha, vect2_pol* vresult) +{ + vresult->r = alpha*vp1->r; + + return; +} diff --git a/modules/base/math/vect2/vect2.h b/modules/base/math/vect2/vect2.h new file mode 100755 index 0000000..8a1ac5d --- /dev/null +++ b/modules/base/math/vect2/vect2.h @@ -0,0 +1,168 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: vect2.h,v 1.3.4.1 2006-11-26 21:06:01 zer0 Exp $ + * + */ + +/** \file vect2.h +* \brief Interface for the 2 dimensional vector module. +* \author JD & Vincent +* \version 2.0 +* \date 21.12.2005 @ 23:09 +* \todo Complex operations on vectors and implementation of the <french> reperes </french> +* \test polar -> cartesian & cartesian -> polar seems to be ok. +* +* This module provides functions to handle 2d vectors and basic geometry fucntions. +*/ + +/** \dontinclude main.c */ + +#ifndef _VECT2_H_ +#define _VECT2_H_ + +/** \brief Definition of reals used in vector 2d */ +typedef double Real; + +#define TO_RAD(x) (((double)x)*(M_PI/180.0)) +#define TO_DEG(x) (((double)x)*(180.0/M_PI)) + +/** \brief Cartesian vector structure +**/ +typedef struct _vect2_cart +{ + Real x; + Real y; + +}vect2_cart; + + +/** \brief Polar vector structure +**/ +typedef struct _vect2_pol +{ + Real r; + Real theta; + +}vect2_pol; + +/************************ Begin prototyping ************************/ + +/** \addtogroup Convertions + * This functions allow to convert between the 2 vector types. + * @{ + */ + +/** \brief Convert a polar vector to a cartesian one +* \param vp reference to target polar vector to convert from. +* \param vc reference to target cartesian vector where the function write. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* +**/ +void vect2_pol2cart(vect2_pol* vp, vect2_cart* vc); + + +/** \brief Convert a cartesian vector to a polar one +* \param vc reference to target cartesian vector to convert from. +* \param vp reference to target polar vector where the function write the result. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* +**/ +void vect2_cart2pol(vect2_cart* vc, vect2_pol* vp); + +/** @} */ + + +/** \addtogroup Basics + * This functions allow basic vector operations. + * @{ + */ + + +/** \brief Add 2 polar vectors and return the result +* \param v1 Reference to a polar vector to sum. +* \param v2 Reference to a polar vector to sum. +* \param vresult Reference to a polar vector to store the result. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* \note This function convert the 2 entry vectors to cartesian, sum them and then convert the result to polar. +* So please think before using it. +* +* \f[ \vec V_{result} = \vec V_1 + \vec V_2 \f] +**/ +void vect2_add_pol(vect2_pol* v1, vect2_pol* v2, vect2_pol* vresult); + + +/** \brief Add 2 cartesian vectors and return the result +* \param v1 Reference to a cartesian vector to sum. +* \param v2 Reference to a cartesian vector to sum. +* \param vresult Reference to a polar vector to store the result. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* +* \f[ \vec V_{result} = \vec V_1 + \vec V_2 \f] +**/ +void vect2_add_cart(vect2_cart* v1, vect2_cart* v2, vect2_cart* vresult); + + +/** \brief Substract 2 polar vectors and return the result +* \param v1 Reference to a polar vector to substract. +* \param v2 Reference to a polar vector to substract. +* \param vresult Reference to a polar vector to store the result. +* \warning This function doesn't do any + Real R = 1.45064930529587234; + Real theta = 0.6734390282904231341;malloc ! You have to allocate structures before calling this function. +* \note This function convert the 2 entry vectors to cartesian, substract them and then convert the result to polar. +* So please think before using it. +* +* \f[ \vec V_{result} = \vec V_1 - \vec V_2 \f] +**/ +void vect2_sub_pol(vect2_pol* v1, vect2_pol* v2, vect2_pol* vresult); + +/** \brief Substract 2 cartesian vectors and return the result +* \param v1 Reference to a cartesian vector to substract. +* \param v2 Reference to a cartesian vector to substract. +* \param vresult Reference to a cartesian vector to store the result. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* +* \f[ \vec V_{result} = \vec V_1 - \vec V_2 \f] +**/ +void vect2_sub_cart(vect2_cart* v1, vect2_cart* v2, vect2_cart* vresult); + + +/** \brief Multiply a cartesian vector by a scalar and return the result +* \param v1 Reference to a cartesian vector. +* \param alpha The multiplying scalar. +* \param vresult Reference to a cartesian vector to store the result. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* +* \f[ \vec V_{result} = \alpha\vec V_1 \f] +**/ +void vect2_scale_cart(vect2_cart* v1, Real alpha, vect2_cart* vresult); + +/** \brief Multiply a polar vector by a scalar and return the result +* \param v1 Reference to a polar vector. +* \param alpha The multiplying scalar. +* \param vresult Reference to a cartesian vector to store the result. +* \warning This function doesn't do any malloc ! You have to allocate structures before calling this function. +* +* \f[ \vec V_{result} = \alpha\vec V_1 \f] +**/ +void vect2_scale_pol(vect2_pol* v1, Real alpha, vect2_pol* vresult); + +/** @} */ + + +#endif /*_VECT2_H_*/ diff --git a/modules/base/scheduler/CVS/Entries b/modules/base/scheduler/CVS/Entries new file mode 100644 index 0000000..56b99aa --- /dev/null +++ b/modules/base/scheduler/CVS/Entries @@ -0,0 +1,12 @@ +/Makefile/1.4.10.3/Mon Mar 5 14:41:06 2007//Tb_zer0 +/scheduler.c/1.9.4.6/Sun Nov 8 17:33:14 2009//Tb_zer0 +/scheduler.h/1.8.4.11/Mon May 18 12:30:36 2009//Tb_zer0 +/scheduler_add.c/1.1.2.4/Sun Nov 8 17:33:14 2009//Tb_zer0 +/scheduler_del.c/1.1.2.3/Sun Nov 8 17:33:14 2009//Tb_zer0 +/scheduler_dump.c/1.1.2.3/Mon May 18 12:30:36 2009//Tb_zer0 +/scheduler_host.c/1.5.10.2/Mon Mar 5 14:41:07 2007//Tb_zer0 +/scheduler_interrupt.c/1.1.2.9/Sun Nov 8 17:33:14 2009//Tb_zer0 +/scheduler_private.h/1.1.2.8/Mon May 18 12:30:36 2009//Tb_zer0 +/scheduler_stats.h/1.1.2.1/Sun Nov 8 17:33:14 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/base/scheduler/CVS/Repository b/modules/base/scheduler/CVS/Repository new file mode 100644 index 0000000..d2b6cc0 --- /dev/null +++ b/modules/base/scheduler/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/scheduler diff --git a/modules/base/scheduler/CVS/Root b/modules/base/scheduler/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/scheduler/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/scheduler/CVS/Tag b/modules/base/scheduler/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/scheduler/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/scheduler/CVS/Template b/modules/base/scheduler/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/scheduler/Makefile b/modules/base/scheduler/Makefile new file mode 100644 index 0000000..1da307b --- /dev/null +++ b/modules/base/scheduler/Makefile @@ -0,0 +1,11 @@ +TARGET = scheduler + +# List C source files here. (C dependencies are automatically generated.) +SRC = scheduler_add.c scheduler_del.c scheduler_interrupt.c scheduler_dump.c +ifeq ($(H),1) +SRC += scheduler_host.c +else +SRC += scheduler.c +endif + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/scheduler/config/CVS/Entries b/modules/base/scheduler/config/CVS/Entries new file mode 100644 index 0000000..930154b --- /dev/null +++ b/modules/base/scheduler/config/CVS/Entries @@ -0,0 +1,2 @@ +/scheduler_config.h/1.1.10.8/Tue Nov 27 23:16:15 2007//Tb_zer0 +D diff --git a/modules/base/scheduler/config/CVS/Repository b/modules/base/scheduler/config/CVS/Repository new file mode 100644 index 0000000..97084d9 --- /dev/null +++ b/modules/base/scheduler/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/scheduler/config diff --git a/modules/base/scheduler/config/CVS/Root b/modules/base/scheduler/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/scheduler/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/scheduler/config/CVS/Tag b/modules/base/scheduler/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/scheduler/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/scheduler/config/CVS/Template b/modules/base/scheduler/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/scheduler/config/scheduler_config.h b/modules/base/scheduler/config/scheduler_config.h new file mode 100644 index 0000000..ba35429 --- /dev/null +++ b/modules/base/scheduler/config/scheduler_config.h @@ -0,0 +1,77 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1.10.8 2007-11-27 23:16:15 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 5 + + +/* define it only if CONFIG_MODULE_SCHEDULER_USE_TIMERS is enabled. In + this case, precaler is defined in timers_config.h in your project + directory. */ +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS +/** the num of the timer to use for the scheduler */ +#define SCHEDULER_TIMER_NUM 0 + +/* or set the prescaler manually (in this case, you use must TIMER0, + and the prescaler must be a correct value regarding the AVR device + you are using (look in include/aversive/parts.h). Obviously, the + values of SCHEDULER_CK and SCHEDULER_CLOCK_PRESCALER must also be + coherent (TIMER0_PRESCALER_DIV_VALUE and VALUE) */ +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + + +#ifdef CONFIG_MODULE_SCHEDULER_TIMER0 +/* The 2 values below MUST be coherent: + * if SCHEDULER_CK = TIMER0_PRESCALER_DIV_x, then + * you must have SCHEDULER_CLOCK_PRESCALER = x too !!! */ +#define SCHEDULER_CK TIMER0_PRESCALER_DIV_8 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif /* CONFIG_MODULE_SCHEDULER_TIMER0 */ + +/* last case, the scheduler is called manually. The user has to + define the period here */ +#ifdef CONFIG_MODULE_SCHEDULER_MANUAL + +#define SCHEDULER_UNIT_FLOAT 1000.0 +#define SCHEDULER_UNIT 1000UL + +#endif /* CONFIG_MODULE_SCHEDULER_MANUAL */ + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/base/scheduler/scheduler.c b/modules/base/scheduler/scheduler.c new file mode 100644 index 0000000..8d0f730 --- /dev/null +++ b/modules/base/scheduler/scheduler.c @@ -0,0 +1,85 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler.c,v 1.9.4.6 2009-11-08 17:33:14 zer0 Exp $ + * + */ + +#include <string.h> +#include <stdio.h> +#include <inttypes.h> + +#include <aversive/parts.h> +#include <aversive/pgmspace.h> +#include <aversive.h> + +#include <scheduler.h> +#include <scheduler_private.h> +#include <scheduler_stats.h> +#include <scheduler_config.h> + + +/* this file is compiled for AVR version only */ + +/** declared in scheduler_host.c in case of host version */ +struct event_t g_tab_event[SCHEDULER_NB_MAX_EVENT]; + +#ifdef CONFIG_MODULE_SCHEDULER_STATS +struct scheduler_stats sched_stats; +#endif + +void scheduler_init(void) +{ + memset(g_tab_event, 0, sizeof(g_tab_event)); + +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS + SCHEDULER_TIMER_REGISTER(); +#endif + +#ifdef CONFIG_MODULE_SCHEDULER_TIMER0 + /* activation of corresponding interrupt */ + TOIE0_REG |= (1<<TOIE0); /* TIMSK */ + + TCNT0 = 0; + CS00_REG = SCHEDULER_CK; /* TCCR0 */ +#endif +} + + +#ifdef CONFIG_MODULE_SCHEDULER_TIMER0 +SIGNAL(SIG_OVERFLOW0) +{ + scheduler_interrupt(); +} +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + + +void scheduler_stats_dump(void) +{ +#ifdef CONFIG_MODULE_SCHEDULER_STATS + uint8_t i; + + printf_P(PSTR("alloc_fails: %"PRIu32"\r\n"), sched_stats.alloc_fails); + printf_P(PSTR("add_event: %"PRIu32"\r\n"), sched_stats.add_event); + printf_P(PSTR("del_event: %"PRIu32"\r\n"), sched_stats.del_event); + printf_P(PSTR("max_stacking: %"PRIu32"\r\n"), sched_stats.max_stacking); + for (i=0; i<SCHEDULER_NB_MAX_EVENT; i++) { + printf_P(PSTR("task_delayed[%d]: %"PRIu32"\r\n"), i, + sched_stats.task_delayed[i]); + } +#endif /* CONFIG_MODULE_SCHEDULER_STATS */ +} diff --git a/modules/base/scheduler/scheduler.h b/modules/base/scheduler/scheduler.h new file mode 100644 index 0000000..d49fc37 --- /dev/null +++ b/modules/base/scheduler/scheduler.h @@ -0,0 +1,198 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler.h,v 1.8.4.11 2009-05-18 12:30:36 zer0 Exp $ + * + */ + +/* Olivier MATZ <zer0@droids-corp.org> + * Interface of the SCHEDULER Module + */ + +/** \file scheduler.h + * + * This module provides a function scheduler. You can call + * scheduler_add_event for adding a function to the scheduler, and + * specifying what interval between each call. During the execution of + * the function, interrupts are masked !! So use this module with + * caution (small functions) for avoiding problems. + * + * Functions with a high priority value will be call before others + * (default is 128). + * + * This module uses Timer 0 + */ + + +#ifndef _SCHEDULER_H_ +#define _SCHEDULER_H_ + +#include <aversive.h> + +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS +#include <timer.h> +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + +#include <scheduler_config.h> + +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS +#if SCHEDULER_TIMER_NUM == 0 +#define SCHEDULER_TIMER_REGISTER() timer0_register_OV_intr(scheduler_interrupt) +#define SCHEDULER_CLOCK_PRESCALER timer0_get_prescaler_div() +#ifdef TCNT0H +#define SCHEDULER_TIMER_BITS 16 +#else +#define SCHEDULER_TIMER_BITS 8 +#endif + +#elif SCHEDULER_TIMER_NUM == 1 +#define SCHEDULER_TIMER_REGISTER() timer1_register_OV_intr(scheduler_interrupt) +#define SCHEDULER_CLOCK_PRESCALER timer1_get_prescaler_div() +#ifdef TCNT1H +#define SCHEDULER_TIMER_BITS 16 +#else +#define SCHEDULER_TIMER_BITS 8 +#endif + +#elif SCHEDULER_TIMER_NUM == 2 +#define SCHEDULER_TIMER_REGISTER() timer2_register_OV_intr(scheduler_interrupt) +#define SCHEDULER_CLOCK_PRESCALER timer2_get_prescaler_div() +#ifdef TCNT2H +#define SCHEDULER_TIMER_BITS 16 +#else +#define SCHEDULER_TIMER_BITS 8 +#endif + +#elif SCHEDULER_TIMER_NUM == 3 +#define SCHEDULER_TIMER_REGISTER() timer3_register_OV_intr(scheduler_interrupt) +#define SCHEDULER_CLOCK_PRESCALER timer3_get_prescaler_div() +#ifdef TCNT3H +#define SCHEDULER_TIMER_BITS 16 +#else +#define SCHEDULER_TIMER_BITS 8 +#endif + +#else +#error "Bad SCHEDULER_TIMER_NUM value in config file" +#endif + +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + +#ifdef CONFIG_MODULE_SCHEDULER_TIMER0 +#define SCHEDULER_TIMER_BITS 8 +#endif /* CONFIG_MODULE_SCHEDULER_TIMER0 */ + +#ifndef CONFIG_MODULE_SCHEDULER_MANUAL + +/** TIME_UNIT is the number of microseconds between each interruption + * if the prescaler equals 1 */ +#if SCHEDULER_TIMER_BITS == 8 +#define TIMER_UNIT_FLOAT ( 256000000.0 / (double)(CONFIG_QUARTZ) ) +#else +#define TIMER_UNIT_FLOAT ( 65536000000.0 / (double)(CONFIG_QUARTZ) ) +#endif + +/** SCHEDULER_UNIT is the number of microseconds between each + * scheduler interruption. We can use it like this : + * scheduler_add_periodical_event(f, 1000L/SCHEDULER_UNIT); + * The function f will be called every ms. + */ +#define SCHEDULER_UNIT_FLOAT ( TIMER_UNIT_FLOAT * (double)SCHEDULER_CLOCK_PRESCALER ) +#define SCHEDULER_UNIT ( (unsigned long) SCHEDULER_UNIT_FLOAT ) + +#endif /* ! CONFIG_MODULE_SCHEDULER_MANUAL */ + + + +#define SCHEDULER_PERIODICAL 0 +#define SCHEDULER_SINGLE 1 + +#define SCHEDULER_DEFAULT_PRIORITY 128 + + +/** Initialisation of the module */ +void scheduler_init(void); + +/** dump all loaded events */ +void scheduler_dump_events(void); + +/** + * Add an event to the event table. + * Return the id of the event on succes and -1 on error + * You can use static inline funcs below for simpler use. + */ +int8_t scheduler_add_event(uint8_t unicity, void (*f)(void *), void * data, uint16_t period, uint8_t priority); + + +/** + * Add a single event to the event table, specifying the priority + */ +static inline int8_t scheduler_add_single_event_priority(void (*f)(void *), void * data, uint16_t period, uint8_t priority) +{ + return scheduler_add_event(SCHEDULER_SINGLE, f, data, period, priority); +} + +/** + * Add a periodical event to the event table, specifying the priority + */ +static inline int8_t scheduler_add_periodical_event_priority(void (*f)(void *), void * data, uint16_t period, uint8_t priority) +{ + return scheduler_add_event(SCHEDULER_PERIODICAL, f, data, period, priority); +} + +/** + * Add a single event to the event table, with the default priority + */ +static inline int8_t scheduler_add_single_event(void (*f)(void *), void * data, uint16_t period) +{ + return scheduler_add_event(SCHEDULER_SINGLE, f, data, period, SCHEDULER_DEFAULT_PRIORITY); +} + +/** + * Add a periodical event to the event table, with the default priority + */ +static inline int8_t scheduler_add_periodical_event(void (*f)(void *), void * data, uint16_t period) +{ + return scheduler_add_event(SCHEDULER_PERIODICAL, f, data, period, SCHEDULER_DEFAULT_PRIORITY); +} + +/** + * Dels an event from the table by its ID. If there is no event, + * nothing is done. + */ +int8_t scheduler_del_event(int8_t num); + +/** Function called by the interruption. It is public in case of host + * version, because you have to call it by hand. In AVR version, you + * don't have to do anything with this function, it is called + * automatilcally by the timer interruption, except if + * CONFIG_MODULE_SCHEDULER_MANUAL is defined. In this case you have + * to call it manually too. */ +void scheduler_interrupt(void); + +/** + * Temporarily disable scheduler events. You may loose precision in + * events schedule. It returns the current priority of the scheduler. + */ +uint8_t scheduler_disable_save(void); + +/** + * Re-enable scheduler after a call to scheduler_disable_save(). + */ +void scheduler_enable_restore(uint8_t old_prio); + +#endif diff --git a/modules/base/scheduler/scheduler_add.c b/modules/base/scheduler/scheduler_add.c new file mode 100644 index 0000000..5ce78b3 --- /dev/null +++ b/modules/base/scheduler/scheduler_add.c @@ -0,0 +1,81 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_add.c,v 1.1.2.4 2009-11-08 17:33:14 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <scheduler_config.h> +#include <scheduler_private.h> +#include <scheduler_stats.h> + +/** get a free event, mark it as allocated and return its index, or -1 + * if not found. */ +static inline int8_t +scheduler_alloc_event(void) +{ + uint8_t i; + uint8_t flags; + + for (i=0 ; i<SCHEDULER_NB_MAX_EVENT ; i++) { + IRQ_LOCK(flags); + if( g_tab_event[i].state == SCHEDULER_EVENT_FREE ) { + g_tab_event[i].state = SCHEDULER_EVENT_ALLOCATED; + IRQ_UNLOCK(flags); + return i; + } + IRQ_UNLOCK(flags); + } + SCHED_INC_STAT(alloc_fails); + return -1; +} + + +/** Alloc an event, and fill its field, then mark it as active. + * return its index in the table, or -1 if no evt is available */ +int8_t +scheduler_add_event(uint8_t unicity, void (*f)(void *), + void *data, uint16_t period, + uint8_t priority) { + int8_t i; + uint8_t flags; + + if (period == 0) + return -1; + + i = scheduler_alloc_event(); + if ( i == -1 ) + return -1; + + SCHED_INC_STAT(add_event); + + if (!unicity) + g_tab_event[i].period = period ; + else + g_tab_event[i].period = 0 ; + g_tab_event[i].current_time = period ; + g_tab_event[i].priority = priority ; + g_tab_event[i].f = f; + g_tab_event[i].data = data; + + IRQ_LOCK(flags); + g_tab_event[i].state = SCHEDULER_EVENT_ACTIVE; + IRQ_UNLOCK(flags); + + return i; +} diff --git a/modules/base/scheduler/scheduler_del.c b/modules/base/scheduler/scheduler_del.c new file mode 100644 index 0000000..6a60818 --- /dev/null +++ b/modules/base/scheduler/scheduler_del.c @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_del.c,v 1.1.2.3 2009-11-08 17:33:14 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <scheduler_config.h> +#include <scheduler_private.h> +#include <scheduler_stats.h> + +void scheduler_del_event(int8_t i) +{ + uint8_t flags; + + /* if scheduled, it will be deleted after execution. + * if active, free it. + * else do nothing. */ + IRQ_LOCK(flags); + if (g_tab_event[i].state == SCHEDULER_EVENT_SCHEDULED) { + g_tab_event[i].state = SCHEDULER_EVENT_DELETING; + } + else if (g_tab_event[i].state == SCHEDULER_EVENT_ACTIVE) { + g_tab_event[i].state = SCHEDULER_EVENT_FREE; + } + IRQ_UNLOCK(flags); + SCHED_INC_STAT(del_event); +} diff --git a/modules/base/scheduler/scheduler_dump.c b/modules/base/scheduler/scheduler_dump.c new file mode 100644 index 0000000..49eddcb --- /dev/null +++ b/modules/base/scheduler/scheduler_dump.c @@ -0,0 +1,53 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_dump.c,v 1.1.2.3 2009-05-18 12:30:36 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> + +#include <scheduler_config.h> +#include <scheduler_private.h> + +/** Dump the event structure table */ +void scheduler_dump_events(void) +{ + int i; + + printf_P(PSTR("== Dump events ==\r\n")); + for (i=0 ; i<SCHEDULER_NB_MAX_EVENT ; i++) { + printf_P(PSTR(" [%d]@%p : "), i, &g_tab_event[i]); + printf_P(PSTR(" state=%d"), g_tab_event[i].state); + if (g_tab_event[i].state >= SCHEDULER_EVENT_ACTIVE ) { + printf_P(PSTR(", f=%p, "), g_tab_event[i].f); + printf_P(PSTR("data=%p, "), g_tab_event[i].data); + printf_P(PSTR("period=%d, "), g_tab_event[i].period); + printf_P(PSTR("current_time=%d, "), g_tab_event[i].current_time); + printf_P(PSTR("priority=%d, "), g_tab_event[i].priority); + printf_P(PSTR("list_next=%p\r\n"), SLIST_NEXT(&g_tab_event[i], next)); + } + else { + printf_P(PSTR("\r\n")); + } + } +} + + diff --git a/modules/base/scheduler/scheduler_host.c b/modules/base/scheduler/scheduler_host.c new file mode 100644 index 0000000..05f6593 --- /dev/null +++ b/modules/base/scheduler/scheduler_host.c @@ -0,0 +1,41 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_host.c,v 1.5.10.2 2007-03-05 14:41:07 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <scheduler_config.h> +#include <scheduler_private.h> + +/* this file is compiled for host version only */ + +/** declared in scheduler.c in case of AVR version */ +struct event_t g_tab_event[SCHEDULER_NB_MAX_EVENT]; + +/** init all global data */ +void scheduler_init(void) +{ + memset(g_tab_event, 0, sizeof(g_tab_event)); + printf("Scheduler init (host). Warning, you have to call\n" + "scheduler_interrupt() by yourself on host version\n"); + DUMP_EVENTS(); +} + diff --git a/modules/base/scheduler/scheduler_interrupt.c b/modules/base/scheduler/scheduler_interrupt.c new file mode 100644 index 0000000..15b9409 --- /dev/null +++ b/modules/base/scheduler/scheduler_interrupt.c @@ -0,0 +1,202 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_interrupt.c,v 1.1.2.9 2009-11-08 17:33:14 zer0 Exp $ + * + */ + +#include <stdlib.h> + +#include <aversive.h> +#include <scheduler_config.h> +#include <scheduler_private.h> +#include <scheduler_stats.h> + +/** priority of the running event */ +static volatile uint8_t priority_running=0; + +/** number of imbricated scheduler interruptions */ +static volatile uint8_t nb_stacking=0; + +uint8_t scheduler_disable_save(void) +{ + uint8_t ret; + ret = priority_running; + priority_running = 255; + return ret; +} + +void scheduler_enable_restore(uint8_t old_prio) +{ + priority_running = old_prio; +} + +/** + * this function is called from a timer interruption. If an event has + * to be scheduled, it will execute the fonction (IRQ are allowed + * during the execution of the function). This interruption can be + * interrupted by itself too, in this case only events with a higher + * priority can be scheduled. + * + * We assume that this function is called from a SIGNAL(), with + * global interrupt flag disabled --> that's why we can use cli() and + * sei() instead of IRQ_LOCK(flags). + */ +void +scheduler_interrupt(void) +{ + uint8_t i; + uint8_t priority_tmp; + SLIST_HEAD(event_list_t, event_t) event_list; + struct event_t *e, *next_e, *prev_e=NULL; + + /* maximize the number of imbrications */ + if (nb_stacking >= SCHEDULER_NB_STACKING_MAX) { + SCHED_INC_STAT(max_stacking); + return; + } + + nb_stacking ++; + sei(); + + SLIST_INIT(&event_list); + + /* browse events table to determine which events should be + * scheduled */ + for (i=0 ; i<SCHEDULER_NB_MAX_EVENT ; i++) { + cli(); + + /* the event is already present in a schedule list, + * only update its current time until it reaches 1 */ + if (g_tab_event[i].state == SCHEDULER_EVENT_SCHEDULED) { + if (g_tab_event[i].current_time > 1) { + g_tab_event[i].current_time --; + sei(); + continue; + } + else { + SCHED_INC_STAT2(task_delayed, i); + sei(); + continue; + } + } + + /* nothing to do with other unactive events */ + if (g_tab_event[i].state != SCHEDULER_EVENT_ACTIVE) { + sei(); + continue; + } + + /* decrement current time (we know it is >0 if it is + * in SCHEDULER_EVENT_ACTIVE state */ + g_tab_event[i].current_time --; + + /* don't need to schedule now */ + if ( g_tab_event[i].current_time != 0 ) { + sei(); + continue; + } + + /* time to schedule, but priority is too low, + * delay it */ + if (g_tab_event[i].priority <= priority_running) { + g_tab_event[i].current_time = 1; + SCHED_INC_STAT2(task_delayed, i); + sei(); + continue; + } + + /* reload event (it is 0 if it is non-periodical) */ + g_tab_event[i].current_time = g_tab_event[i].period; + + /* schedule it */ + g_tab_event[i].state = SCHEDULER_EVENT_SCHEDULED; + sei(); + + /* insert it in the list (list is ordered). + this should be quite fast since the list is + expected to be small. */ + + e = SLIST_FIRST(&event_list); + /* easy case : list is empty */ + if (e == NULL) { + SLIST_INSERT_HEAD(&event_list, &g_tab_event[i], next); + continue; + } + + /* insert at head if it's the event with highest prio */ + if (g_tab_event[i].priority >= e->priority) { + SLIST_INSERT_HEAD(&event_list, &g_tab_event[i], next); + continue; + } + + /* harder : find the good place in list */ + SLIST_FOREACH(e, &event_list, next) { + next_e = SLIST_NEXT(e, next); + if (next_e == NULL || + g_tab_event[i].priority >= next_e->priority) { + SLIST_INSERT_AFTER(e, &g_tab_event[i], next); + break; + } + } + } + + /* only called if SCHEDULER_DEBUG is defined */ + DUMP_EVENTS(); + + cli(); + priority_tmp = priority_running; + + SLIST_FOREACH(e, &event_list, next) { + /* remove previous elt from list */ + if (prev_e) + SLIST_NEXT(prev_e, next) = NULL; + + /* set running priority */ + priority_running = e->priority; + sei(); + + /* the following fields (f and data) can't be modified + * while an event is in state SCHEDULED */ + e->f(e->data); + + cli(); + /* free it if it is single (non-periodical) */ + if (!e->period) { + e->state = SCHEDULER_EVENT_FREE; + } + + /* free event if someone asked for deletion during + * schedule */ + if (e->state == SCHEDULER_EVENT_DELETING) { + e->state = SCHEDULER_EVENT_FREE; + } + + /* end of schedule, mark it as active */ + if (e->state == SCHEDULER_EVENT_SCHEDULED) { + e->state = SCHEDULER_EVENT_ACTIVE; + } + + prev_e = e; + } + /* remove previous elt from list */ + if (prev_e) + SLIST_NEXT(prev_e, next) = NULL; + + priority_running = priority_tmp; + nb_stacking--; +} diff --git a/modules/base/scheduler/scheduler_private.h b/modules/base/scheduler/scheduler_private.h new file mode 100644 index 0000000..5d1ff38 --- /dev/null +++ b/modules/base/scheduler/scheduler_private.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_private.h,v 1.1.2.8 2009-05-18 12:30:36 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_PRIVATE_H_ +#define _SCHEDULER_PRIVATE_H_ + +/* sanity checks */ +#if _SCHEDULER_CONFIG_VERSION_ != 4 +#warning "You are using an old version of scheduler_config.h file" +#warning "_SCHEDULER_CONFIG_VERSION_ is != 4" +#warning "Look in modules/base/scheduler/config directory to import changes" +#warning "You should define SCHEDULER_NB_STACKING_MAX and SCHEDULER_CK" +#endif + +#include <stdint.h> + +#include <aversive/queue.h> + +/** state of events */ +enum event_state_t { + SCHEDULER_EVENT_FREE, /**< event is free */ + SCHEDULER_EVENT_ALLOCATED, /**< a place is reserved in the tab */ + SCHEDULER_EVENT_ACTIVE, /**< fields are filled correctly, event can be scheduled */ + SCHEDULER_EVENT_SCHEDULED, /**< event is inserted in a list to be running soon, or is running */ + SCHEDULER_EVENT_DELETING, /**< event is scheduled but we asked to delete it */ +}; + +/** The event structure */ +struct event_t +{ + void (*f)(void *); /**< a pointer to the scheduled function */ + void * data; /**< a pointer to the data parameters */ + uint16_t period; /**< interval between each call */ + uint16_t current_time; /**< time remaining before next call */ + uint8_t priority; /**< if many events occur at the + same time, the first to be executed + will be the one with the highest + value of priority */ + enum event_state_t state; /**< (scheduled, active, allocated, free, deleting) */ + + SLIST_ENTRY(event_t) next; +}; + +extern struct event_t g_tab_event[SCHEDULER_NB_MAX_EVENT]; + + +/* define dump_events() if we are in debug mode */ +#ifdef SCHEDULER_DEBUG +#define DUMP_EVENTS() scheduler_dump_events() + +#else /* SCHEDULER_DEBUG */ +#define DUMP_EVENTS() do {} while(0) + +#endif /* SCHEDULER_DEBUG */ + +#endif /* _SCHEDULER_PRIVATE_H_ */ diff --git a/modules/base/scheduler/scheduler_stats.h b/modules/base/scheduler/scheduler_stats.h new file mode 100644 index 0000000..f3286b9 --- /dev/null +++ b/modules/base/scheduler/scheduler_stats.h @@ -0,0 +1,61 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_stats.h,v 1.1.2.1 2009-11-08 17:33:14 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#ifndef _SCHEDULER_STATS_H_ +#define _SCHEDULER_STATS_H_ + +#ifdef CONFIG_MODULE_SCHEDULER_STATS +struct scheduler_stats { + uint32_t alloc_fails; + uint32_t add_event; + uint32_t del_event; + uint32_t max_stacking; + uint32_t task_delayed[SCHEDULER_NB_MAX_EVENT]; +}; + +extern struct scheduler_stats sched_stats; + +#define SCHED_INC_STAT(x) do { \ + uint8_t flags; \ + IRQ_LOCK(flags); \ + sched_stats.x++; \ + IRQ_UNLOCK(flags); \ + } while(0) + +#define SCHED_INC_STAT2(x, i) do { \ + uint8_t flags; \ + IRQ_LOCK(flags); \ + sched_stats.x[i]++; \ + IRQ_UNLOCK(flags); \ + } while(0) + + +#else /* CONFIG_MODULE_SCHEDULER_STATS */ + +#define SCHED_INC_STAT(x) do { } while(0) +#define SCHED_INC_STAT2(x, i) do { } while(0) + +#endif /* CONFIG_MODULE_SCHEDULER_STATS */ + +void scheduler_stats_dump(void); + +#endif /* _SCHEDULER_STATS_H_ */ diff --git a/modules/base/scheduler/test/.config b/modules/base/scheduler/test/.config new file mode 100644 index 0000000..73a8d18 --- /dev/null +++ b/modules/base/scheduler/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/base/scheduler/test/CVS/Entries b/modules/base/scheduler/test/CVS/Entries new file mode 100644 index 0000000..2392b42 --- /dev/null +++ b/modules/base/scheduler/test/CVS/Entries @@ -0,0 +1,9 @@ +/.config/1.5.4.14/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.5.10.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/Makefile_host/1.1.10.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/error_config.h/1.1.2.1/Mon Mar 5 14:41:07 2007//Tb_zer0 +/main.c/1.9.4.5/Fri Jun 1 09:37:22 2007//Tb_zer0 +/scheduler_config.h/1.4.10.7/Tue Nov 27 23:16:15 2007//Tb_zer0 +/timer_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/uart_config.h/1.1.2.1/Sat Dec 2 18:17:42 2006//Tb_zer0 +D diff --git a/modules/base/scheduler/test/CVS/Repository b/modules/base/scheduler/test/CVS/Repository new file mode 100644 index 0000000..3b58d8d --- /dev/null +++ b/modules/base/scheduler/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/scheduler/test diff --git a/modules/base/scheduler/test/CVS/Root b/modules/base/scheduler/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/scheduler/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/scheduler/test/CVS/Tag b/modules/base/scheduler/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/scheduler/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/scheduler/test/CVS/Template b/modules/base/scheduler/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/scheduler/test/Makefile b/modules/base/scheduler/test/Makefile new file mode 100644 index 0000000..7f0072b --- /dev/null +++ b/modules/base/scheduler/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + diff --git a/modules/base/scheduler/test/Makefile_host b/modules/base/scheduler/test/Makefile_host new file mode 100644 index 0000000..ec825dc --- /dev/null +++ b/modules/base/scheduler/test/Makefile_host @@ -0,0 +1,21 @@ +# Target file name (without extension). +TARGET = main + +# Optimization level, can be [0, 1, 2, 3, s]. 0 turns off optimization. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = 0 + +# repertoire des modules +MODULE_DIR = ../../.. + +# Makefile principal +MAIN_MAKEFILE = ../../../../Makefile_hostproject + +# nom des modules utilis{\'e}s, du plus haut niveau vers le plus bas (pb +# de r{\'e}f{\'e}rences non r{\'e}solues sinon) +MODULES = time/scheduler utils + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +include $(MAIN_MAKEFILE) \ No newline at end of file diff --git a/modules/base/scheduler/test/error_config.h b/modules/base/scheduler/test/error_config.h new file mode 100644 index 0000000..530acd3 --- /dev/null +++ b/modules/base/scheduler/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-03-05 14:41:07 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/base/scheduler/test/main.c b/modules/base/scheduler/test/main.c new file mode 100644 index 0000000..43aff0f --- /dev/null +++ b/modules/base/scheduler/test/main.c @@ -0,0 +1,84 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.9.4.5 2007-06-01 09:37:22 zer0 Exp $ + * + */ + +#include <scheduler.h> +#include <aversive/wait.h> +#include <stdio.h> +#include <uart.h> + +uint8_t event_id; + +void f1(void * nothing) +{ + printf("%s\n", __FUNCTION__); +} + +void f2(void * nothing) +{ + printf("%s\n", __FUNCTION__); +} + +void f3(void * nothing) +{ + printf("%s START\n", __FUNCTION__); + wait_ms(1000); + printf("%s END\n", __FUNCTION__); +} + +void supp(void * nothing) +{ + scheduler_del_event(event_id); +} + +int main(void) +{ +#ifndef HOST_VERSION + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + sei(); +#else + int i; +#endif + printf("init\n"); + +#ifdef CONFIG_MODULE_TIMER + timer_init(); +#endif + scheduler_init(); + printf("init2\n"); + wait_ms(2000); + printf("init3\n"); + + event_id = scheduler_add_periodical_event_priority(f1, NULL, 500000l/SCHEDULER_UNIT, 200); + scheduler_add_periodical_event_priority(f2, NULL, 500000l/SCHEDULER_UNIT, 100); + scheduler_add_periodical_event(f3, NULL, 1000000l/SCHEDULER_UNIT); + + // scheduler_add_single_event(supp,65); + + +#ifdef HOST_VERSION + for (i=0 ; i<50000 ; i++) + scheduler_interrupt(); +#endif + return 0; +} + + diff --git a/modules/base/scheduler/test/scheduler_config.h b/modules/base/scheduler/test/scheduler_config.h new file mode 100644 index 0000000..8042648 --- /dev/null +++ b/modules/base/scheduler/test/scheduler_config.h @@ -0,0 +1,77 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.4.10.7 2007-11-27 23:16:15 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 5 + + +/* define it only if CONFIG_MODULE_SCHEDULER_USE_TIMERS is enabled. In + this case, precaler is defined in timers_config.h in your project + directory. */ +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS +/** the num of the timer to use for the scheduler */ +#define SCHEDULER_TIMER_NUM 0 + +/* or set the prescaler manually (in this case, you use must TIMER0, + and the prescaler must be a correct value regarding the AVR device + you are using (look in include/aversive/parts.h). Obviously, the + values of SCHEDULER_CK and SCHEDULER_CLOCK_PRESCALER must also be + coherent (TIMER0_PRESCALER_DIV_VALUE and VALUE) */ +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + + +#ifdef CONFIG_MODULE_SCHEDULER_TIMER0 +/* The 2 values below MUST be coherent: + * if SCHEDULER_CK = TIMER0_PRESCALER_DIV_x, then + * you must have SCHEDULER_CLOCK_PRESCALER = x too !!! */ +#define SCHEDULER_CK TIMER0_PRESCALER_DIV_8 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif /* CONFIG_MODULE_SCHEDULER_TIMER0 */ + +/* last case, the scheduler is called manually. The user has to + define the period here */ +#ifdef CONFIG_MODULE_SCHEDULER_MANUAL + +#define SCHEDULER_UNIT_FLOAT 1000.0 +#define SCHEDULER_UNIT 1000UL + +#endif /* CONFIG_MODULE_SCHEDULER_MANUAL */ + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/base/scheduler/test/timer_config.h b/modules/base/scheduler/test/timer_config.h new file mode 100644 index 0000000..724e689 --- /dev/null +++ b/modules/base/scheduler/test/timer_config.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.1 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 +/* #define TIMER1_PRESCALER_DIV 1 */ +/* #define TIMER2_PRESCALER_DIV 1 */ +/* #define TIMER3_PRESCALER_DIV 1 */ diff --git a/modules/base/scheduler/test/uart_config.h b/modules/base/scheduler/test/uart_config.h new file mode 100644 index 0000000..ba61726 --- /dev/null +++ b/modules/base/scheduler/test/uart_config.h @@ -0,0 +1,114 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2006-12-02 18:17:42 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + + + + +/* + * UART1 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 0 +//#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 4 +#define UART1_TX_FIFO_SIZE 16 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + + + +#endif + diff --git a/modules/base/time/CVS/Entries b/modules/base/time/CVS/Entries new file mode 100644 index 0000000..e37c00a --- /dev/null +++ b/modules/base/time/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/time.c/1.4.4.5/Fri Apr 24 19:26:37 2009//Tb_zer0 +/time.h/1.3.4.2/Wed May 23 17:18:11 2007//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/base/time/CVS/Repository b/modules/base/time/CVS/Repository new file mode 100644 index 0000000..3709e20 --- /dev/null +++ b/modules/base/time/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/time diff --git a/modules/base/time/CVS/Root b/modules/base/time/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/time/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/time/CVS/Tag b/modules/base/time/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/time/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/time/CVS/Template b/modules/base/time/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/time/Makefile b/modules/base/time/Makefile new file mode 100644 index 0000000..e1b547d --- /dev/null +++ b/modules/base/time/Makefile @@ -0,0 +1,8 @@ +TARGET = time + +# List C source files here. (C dependencies are automatically generated.) +SRC = time.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/time/config/CVS/Entries b/modules/base/time/config/CVS/Entries new file mode 100644 index 0000000..56687b7 --- /dev/null +++ b/modules/base/time/config/CVS/Entries @@ -0,0 +1,2 @@ +/time_config.h/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +D diff --git a/modules/base/time/config/CVS/Repository b/modules/base/time/config/CVS/Repository new file mode 100644 index 0000000..49bdc42 --- /dev/null +++ b/modules/base/time/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/time/config diff --git a/modules/base/time/config/CVS/Root b/modules/base/time/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/time/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/time/config/CVS/Tag b/modules/base/time/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/time/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/time/config/CVS/Template b/modules/base/time/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/time/config/time_config.h b/modules/base/time/config/time_config.h new file mode 100644 index 0000000..5f8a9c0 --- /dev/null +++ b/modules/base/time/config/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.2.6.1 2006-11-26 21:06:01 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000l diff --git a/modules/base/time/test/.config b/modules/base/time/test/.config new file mode 100644 index 0000000..d653dd2 --- /dev/null +++ b/modules/base/time/test/.config @@ -0,0 +1,176 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# To see all modules here, you must enable utils and wait modules, and math library +# +CONFIG_MODULE_UTILS=y +CONFIG_MODULE_UTILS_CREATE_CONFIG=y +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_WAIT=y +CONFIG_MODULE_LIST=y +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +CONFIG_MODULE_TIME=y +CONFIG_MODULE_TIME_CREATE_CONFIG=y + +# +# Communication modules +# + +# +# Some communications modules depend on utils and list modules +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set + +# +# Hardware modules +# + +# +# Hardware modules depend on utils module +# +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Encoders (you should enable utils and fixed_point modules to see all available encoders) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters (you should enable utils modules to see all available filters) +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" diff --git a/modules/base/time/test/CVS/Entries b/modules/base/time/test/CVS/Entries new file mode 100644 index 0000000..e198aa2 --- /dev/null +++ b/modules/base/time/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.4.4.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:01 2006//Tb_zer0 +/error_config.h/1.2.6.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/main.c/1.3.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/scheduler_config.h/1.2.6.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/time_config.h/1.2.6.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +D diff --git a/modules/base/time/test/CVS/Repository b/modules/base/time/test/CVS/Repository new file mode 100644 index 0000000..687f016 --- /dev/null +++ b/modules/base/time/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/time/test diff --git a/modules/base/time/test/CVS/Root b/modules/base/time/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/time/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/time/test/CVS/Tag b/modules/base/time/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/time/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/time/test/CVS/Template b/modules/base/time/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/time/test/Makefile b/modules/base/time/test/Makefile new file mode 100644 index 0000000..639fab0 --- /dev/null +++ b/modules/base/time/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/base/time/test/error_config.h b/modules/base/time/test/error_config.h new file mode 100644 index 0000000..2c634b1 --- /dev/null +++ b/modules/base/time/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.6.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/base/time/test/main.c b/modules/base/time/test/main.c new file mode 100644 index 0000000..2ba8379 --- /dev/null +++ b/modules/base/time/test/main.c @@ -0,0 +1,38 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.3.4.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +#include <avr/io.h> + +#include <time.h> + +int main(void) +{ + time_init(128); + + DDRB=0xFF; + + while(1) + { + PORTB=(uint8_t)time_get_s(); + } + + return 0; +} diff --git a/modules/base/time/test/scheduler_config.h b/modules/base/time/test/scheduler_config.h new file mode 100644 index 0000000..2774ac6 --- /dev/null +++ b/modules/base/time/test/scheduler_config.h @@ -0,0 +1,29 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.2.6.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + + +#define SCHEDULER_NB_MAX_EVENT 5 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/base/time/test/time_config.h b/modules/base/time/test/time_config.h new file mode 100644 index 0000000..f08d6f6 --- /dev/null +++ b/modules/base/time/test/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.2.6.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000l diff --git a/modules/base/time/time.c b/modules/base/time/time.c new file mode 100644 index 0000000..c44bcd4 --- /dev/null +++ b/modules/base/time/time.c @@ -0,0 +1,161 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time.c,v 1.4.4.5 2009-04-24 19:26:37 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Implementation of the time module + */ + +/** \file time.c + * \brief Implementation of the TIME module. + * + * + * This module can be used to get a human readable time. It uses the + * scheduler module. Its goal is not to be very precise, but just + * simple to use. + */ + + +/**********************************************************/ + +#include <stdlib.h> +#include <scheduler.h> + +#include <time.h> +#include <time_config.h> + +/**********************************************************/ + +#define NB_SCHEDULER_UNIT ( ((float)(TIME_PRECISION)) / SCHEDULER_UNIT_FLOAT ) +#define NB_SCHEDULER_UNIT_NOT_NULL (NB_SCHEDULER_UNIT == 0 ? 1.0 : NB_SCHEDULER_UNIT) + +static volatile time_h t; + +static volatile microseconds us2; // this one overflows naturally + + +void time_increment(void * dummy); + +/**********************************************************/ + +void time_init(uint8_t priority) +{ + time_reset(); + scheduler_add_periodical_event_priority(time_increment,NULL, + (int)NB_SCHEDULER_UNIT_NOT_NULL, priority); +} + +/**********************************************************/ + +seconds time_get_s(void) +{ + uint16_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = t.s; + IRQ_UNLOCK(flags); + return tmp; +} + +/**********************************************************/ + +microseconds time_get_us(void) +{ + microseconds tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = t.us; + IRQ_UNLOCK(flags); + return tmp; +} + +/**********************************************************/ + +microseconds time_get_us2(void) +{ + microseconds tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = us2; + IRQ_UNLOCK(flags); + return tmp; +} + +/**********************************************************/ + +time_h time_get_time(void) +{ + time_h tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = t; + IRQ_UNLOCK(flags); + return tmp; +} + +/**********************************************************/ + +void time_reset(void) +{ + uint8_t flags; + IRQ_LOCK(flags); + t.us = 0; + t.s = 0; + IRQ_UNLOCK(flags); +} + +/**********************************************************/ + +void time_set(seconds s, microseconds us) +{ + uint8_t flags; + IRQ_LOCK(flags); + t.us = us; + t.s = s; + IRQ_UNLOCK(flags); +} + +/**********************************************************/ + +void time_wait_ms(uint16_t ms) +{ + microseconds old = time_get_us2(); + while (time_get_us2() - old < ms*1000L); +} + +/**********************************************************/ +/* private */ +/**********************************************************/ + +void time_increment(__attribute__((unused)) void * dummy) +{ + uint8_t flags; + /* XXX we should lock only when writing */ + IRQ_LOCK(flags); // for reading correct time inside an interrupt + + us2 += ((int)NB_SCHEDULER_UNIT_NOT_NULL * SCHEDULER_UNIT); + t.us += ((int)NB_SCHEDULER_UNIT_NOT_NULL * SCHEDULER_UNIT); + while (t.us > 1000000) { + t.s ++; + t.us -= 1000000; + } + + IRQ_UNLOCK(flags); +} diff --git a/modules/base/time/time.h b/modules/base/time/time.h new file mode 100644 index 0000000..4e1fcec --- /dev/null +++ b/modules/base/time/time.h @@ -0,0 +1,96 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time.h,v 1.3.4.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Interface of the time module + */ + +/** + * This module can be used to get a human readable time. It uses the + * scheduler module. Its goal is not to be very precise, but just + * simple to use. provides two timers: one in s and us, and one in + * us which doesn't overflow on seconds (better to substract two + * times) + */ + +#ifndef _TIME_H_ +#define _TIME_H_ + +#include <aversive.h> + +/* a 16 bit variable cannot cover one day */ +typedef int32_t seconds; +typedef int32_t microseconds; + + +/** the time structure */ +typedef struct +{ + microseconds us; + seconds s; +} time_h; + + + +/**********************************************************/ + +/** init time module : schedule the event with the givent priority */ +void time_init(uint8_t priority); + +/**********************************************************/ + +/** get time in second since last init/reset */ +seconds time_get_s(void); + +/**********************************************************/ + +/** get time in microsecond since last init/reset */ +microseconds time_get_us(void); + +/**********************************************************/ + +/** get the complete time struct since last init/reset */ +time_h time_get_time(void); + +/**********************************************************/ + +/** reset time counter */ +void time_reset(void); + +/**********************************************************/ + +/** set time */ +void time_set(seconds s, microseconds us); + +/**********************************************************/ + +/** This is an equivalent of 'wait_ms(x)', but uses time value, so it + * is independant of CPU load. Warning, you should not use this + * function in a irq locked context, or in a scheduled function with + * higher priority than time module */ +void time_wait_ms(uint16_t ms); + +/**********************************************************/ + +/** get a microsecond timer that overflows naturally */ +microseconds time_get_us2(void); + +#endif diff --git a/modules/base/time_ext/CVS/Entries b/modules/base/time_ext/CVS/Entries new file mode 100644 index 0000000..3367de6 --- /dev/null +++ b/modules/base/time_ext/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +/time_ext.c/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +/time_ext.h/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +D/config//// diff --git a/modules/base/time_ext/CVS/Repository b/modules/base/time_ext/CVS/Repository new file mode 100644 index 0000000..f623adb --- /dev/null +++ b/modules/base/time_ext/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/time_ext diff --git a/modules/base/time_ext/CVS/Root b/modules/base/time_ext/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/time_ext/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/time_ext/CVS/Tag b/modules/base/time_ext/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/time_ext/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/time_ext/CVS/Template b/modules/base/time_ext/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/time_ext/Makefile b/modules/base/time_ext/Makefile new file mode 100644 index 0000000..e496830 --- /dev/null +++ b/modules/base/time_ext/Makefile @@ -0,0 +1,8 @@ +TARGET = time_ext + +# List C source files here. (C dependencies are automatically generated.) +SRC = time_ext.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/base/time_ext/config/CVS/Entries b/modules/base/time_ext/config/CVS/Entries new file mode 100644 index 0000000..348e1ca --- /dev/null +++ b/modules/base/time_ext/config/CVS/Entries @@ -0,0 +1,2 @@ +/time_ext_config.h/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +D diff --git a/modules/base/time_ext/config/CVS/Repository b/modules/base/time_ext/config/CVS/Repository new file mode 100644 index 0000000..74c4c47 --- /dev/null +++ b/modules/base/time_ext/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/time_ext/config diff --git a/modules/base/time_ext/config/CVS/Root b/modules/base/time_ext/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/time_ext/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/time_ext/config/CVS/Tag b/modules/base/time_ext/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/time_ext/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/time_ext/config/CVS/Template b/modules/base/time_ext/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/time_ext/config/time_ext_config.h b/modules/base/time_ext/config/time_ext_config.h new file mode 100644 index 0000000..1fec4e8 --- /dev/null +++ b/modules/base/time_ext/config/time_ext_config.h @@ -0,0 +1,53 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ +#ifndef _TIME_EXT_CONFIG_H_ +#define _TIME_EXT_CONFIG_H_ + + +/* + * Speed of your external Quartz (in Hertz) + * Typically you want it to be a 32.768kHz watch-like quartz + */ +#define TIME_EXT_QUARTZ_FREQ 32768000UL + + +/* + * Quartz period (1/freq) in NANO-SECONDS + * The rounding error here, for a 32768kHz quartz, + * is of 36450 ns per 24 hours. + */ +#define TIME_EXT_QUARTZ_PERIOD 30518UL + + +/* + * If the resolution of 30us (with a 32kHz quartz) is + * not enough for your application, you can define + * TIME_EXT_FINE_GRAIN + * The timer will then use TIMER1 driven by the CPU clock, + * in addition to TIMER2 in asynchronous mode driven by + * the external quartz, to achieve the best resolution possible. + */ +#define TIME_EXT_FINE_GRAIN + + +#endif /* _TIME_EXT_CONFIG_H_ */ diff --git a/modules/base/time_ext/time_ext.c b/modules/base/time_ext/time_ext.c new file mode 100644 index 0000000..ed24190 --- /dev/null +++ b/modules/base/time_ext/time_ext.c @@ -0,0 +1,327 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#include <aversive.h> +#include <aversive/error.h> +#include <aversive/wait.h> + +#include <time_ext.h> +#include <time_ext_config.h> + +/* Global time variable */ +static volatile time_ext_t g_time; + + +/* Global counters */ +static volatile uint32_t g_timer1_cnt; +static volatile uint16_t g_timer1_val; +static volatile uint32_t g_inst_number; +static volatile uint32_t g_frequency; +static volatile uint16_t g_nano_per_inst; + +#if 0 +/* Function pointer (points to the current interrupt) */ +static volatile void (*g_timer1_ovf_interrupt)(void); +static volatile void (*g_timer2_ovf_interrupt)(void); + + +/* + * Interrupt vector: Timer1 OVerFlow + */ +void SIG_OVERFLOW1(void) __attribute__ ((signal)); +void SIG_OVERFLOW1(void) +{ + g_timer1_cnt++; +} +#endif + + +/* + * Interrupt vector: Timer2 OVerFlow + */ +void SIG_OVERFLOW2(void) __attribute__ ((signal)); +void SIG_OVERFLOW2(void) +{ +#if 0 + TCNT1 = 0; + g_timer1_cnt = 0; +#endif + /* 256 times NANO_PER_QUARTZ_TICK / prescaler since last overflow */ + g_time.nano += (NANO_PER_QUARTZ_TICK << 8) / time_ext_get_prescaler(); + + if(g_time.nano >= NANO_PER_S) + { + g_time.nano -= NANO_PER_S; + g_time.sec++; + } +} + + +#if 0 +/* + * Timer1 overflow interrupt + * Basic one, used in production + */ +void timer1_ovf_basic(void) +{ + g_timer1_cnt++; +} + +/* + * Timer1 overflow interrupt + * Calibration + */ +void timer1_ovf_calib(void) +{ + /* Remember how many times we were here */ + g_timer1_cnt++; +} + +/* + * Timer2 overflow interrupt + * Basic one, used in production + */ +void timer2_ovf_basic(void) +{ + TCNT1 = 0; + g_timer1_cnt = 0; + /* 256 times NANO_PER_QUARTZ_TICK / prescaler since last overflow */ + g_time.nano += (NANO_PER_QUARTZ_TICK << 8) / time_ext_get_prescaler(); + + if(g_time.nano >= NANO_PER_S) + { + g_time.nano -= NANO_PER_S; + g_time.sec++; + } +} + +/* + * Timer2 overflow interrupt + * Used for crystal calibration + */ +void timer2_ovf_calib(void) +{ + /* XXX nothing for now */ + + /* + * When calibrating the main crystal, this + * interrupt is triggered exactly one second + * after the start of the calibration. + * This then reads the number of instructions + * executed during this second, and deduces the + * main crystal frequency. + * It then configures the module back to its normal + * function (that is, couting time). + */ + + /* STOP timers */ + TCCR1B = 0x00; + TIFR1 = 0xFF; + TCCR2B = 0x00; + TIFR2 = 0xFF; + + /* Fetch the value of TCNT1 */ + g_timer1_val = TCNT1; //(((uint16_t)TCNT1H) << 8) + TCNT1L; + + /* Total number of instructions */ + g_inst_number = (((uint32_t)g_timer1_cnt) << 16) + g_timer1_val; + + /* Print that */ + NOTICE(E_TIME_EXT, "%ld instructions in 8 second !", g_inst_number); + NOTICE(E_TIME_EXT, "timer_val = %d, timer_cnt = %ld", g_timer1_val, g_timer1_cnt); + g_frequency = g_inst_number >> 3; + NOTICE(E_TIME_EXT, "Main crystal frequency = %ld Hz", g_frequency); + g_nano_per_inst = (1000000000UL / g_frequency); + NOTICE(E_TIME_EXT, "Instruction every %d nanosecond", g_nano_per_inst); + + /* Come back to normal state */ + g_timer1_ovf_interrupt = timer1_ovf_basic; + g_timer2_ovf_interrupt = timer2_ovf_basic; + + g_timer1_cnt = 0; + TCNT2 = 0; + + TCCR1B = 0x01; + TCCR2B = 0x01; +} +#endif + + + + +/* + * Initialize TIMER2 + */ +void time_ext_init(void) +{ + /* + * Asynchronous operation of Timer2 + * Some considerations must be taken. + * See DataSheet for additional information. + */ + + NOTICE(E_TIME_EXT, "Initialization"); + +#if 0 + /* Set interrupt */ + g_timer1_ovf_interrupt = timer1_ovf_basic; + g_timer2_ovf_interrupt = timer2_ovf_basic; + + /* Deactivate TIMER1 */ + TIMSK1 = 0x00; + TCCR1A = 0x00; + TCCR1B = 0x00; + TCNT1 = 0x00; + g_timer1_val = 0; + g_timer1_cnt = 0; +#endif + + /* Asynchronous mode: + * EXCLK = 0 (we have an oscillator) + * AS2 = 1 + * other bits are read only + */ + ASSR = _BV(AS2); + /* We want a 'normal' operation mode */ + TCCR2A = 0x00; + /* Clock Select: no prescaling */ + TCCR2B = 0x01; + /* Reset the counter */ + TCNT2 = 0x00; + /* We want an interrupt when TCNT2 overflows */ + TIMSK2 = _BV(TOIE2); + + + g_time.sec = 0; + g_time.nano = 0; +} + + +/* + * Change the prescaler + */ +inline void time_ext_set_prescaler(uint8_t p) +{ + /* Prevent fools to pass an incorrect value */ + TCCR2B = p & 0x07; +} + +/* + * Get the prescaler value + */ +inline uint8_t time_ext_get_prescaler(void) +{ + return TCCR2B & 0x07; +} + +#if 0 +/* + * Calibration of main crystal + */ +void time_ext_calib(void) +{ + /* + * Configure TIMER1 and all the stuff + * No prescaler, normal mode, interrupt on OVF + */ + TCCR1A = 0x00; + TCCR1B = 0x00; + TIMSK1 = _BV(TOIE1); + TIFR1 = 0xFF; /* clear flags */ + + /* Configure TIMER2 */ + time_ext_set_prescaler(TIMER2_PRESCALER_OFF); + + /* Change the interrupt handlers */ + g_timer1_ovf_interrupt = timer1_ovf_calib; + g_timer2_ovf_interrupt = timer2_ovf_calib; + + g_frequency = 0; + g_nano_per_inst = 0; + g_inst_number = 0; + + g_timer1_cnt = 0; + g_timer1_val = 0; + TCNT1 = 0; + TCNT2 = 0; + + /* Launch the prescalers -> timers ON */ + TCCR2B = TIMER2_PRESCALER_1024; + TCCR1B = 0x01; +} +#endif + + +/* + * Get time. + * Since we only update g_time when TCNT2 overflows, + * we add the value of TCNT2 to the nano field. + */ +inline uint32_t time_ext_get_s(void) +{ + return g_time.sec; +} + +inline uint32_t time_ext_get_ns(void) +{ + uint32_t tmp, tmp1; + /* Fetch timer1 value */ + //tmp1 = TCNT1; + + tmp = ((uint32_t)TCNT2) * NANO_PER_QUARTZ_TICK / time_ext_get_prescaler(); + //tmp += tmp1 * g_nano_per_inst; + + return g_time.nano + tmp; +} + +time_ext_t time_ext_get(void) +{ + time_ext_t t; + t.nano = time_ext_get_ns(); + t.sec = time_ext_get_s(); + if(t.nano >= NANO_PER_S) { + t.sec++; + t.nano -= NANO_PER_S; + } + return t; +} + + +/* + * Set the time + * Resets TCNT2 as well + */ +inline void time_ext_set(uint32_t sec, uint32_t nano) +{ + TCNT2 = 0; + g_time.nano = nano; + g_time.sec = sec; + NOTICE(E_TIME_EXT, "Time set to %ld %ld", sec, nano); +} + + + + + + + diff --git a/modules/base/time_ext/time_ext.h b/modules/base/time_ext/time_ext.h new file mode 100644 index 0000000..c293478 --- /dev/null +++ b/modules/base/time_ext/time_ext.h @@ -0,0 +1,95 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ +#ifndef _TIME_EXT_H_ +#define _TIME_EXT_H + + +#include <time_ext_config.h> + +/* + * Since we want the maximum resolution available, + * the prescaler of timer2 is set to 1. + * Thus counter2 is incremented every positive edge of the external quartz. + * You can define the frequency of your quartz in time_ext_config.h + */ + + +/* Number of NANOSECONDS */ +#define NANO_PER_US 1000UL +#define NANO_PER_MS 1000000UL +#define NANO_PER_S 1000000000UL + + +/* Prescaler */ +#define TIMER2_PRESCALER_OFF 0 +#define TIMER2_PRESCALER_1 1 +#define TIMER2_PRESCALER_8 2 +#define TIMER2_PRESCALER_32 3 +#define TIMER2_PRESCALER_64 4 +#define TIMER2_PRESCALER_128 5 +#define TIMER2_PRESCALER_256 6 +#define TIMER2_PRESCALER_1024 7 + + +/* Useful defines */ +#define NANO_PER_QUARTZ_TICK TIME_EXT_QUARTZ_PERIOD + + + + +/* + * Time structure. + * We want to have the best resolution possible. + * Thus, we store nano-seconds and seconds. + */ +typedef struct _time_ext +{ + uint32_t sec; + uint32_t nano; +} time_ext_t; + + +/* Initialize the module */ +void time_ext_init(void); + +/* + * Setter and getter for the prescaler + * By default, it is set to 1 + */ +inline void time_ext_set_prescaler(uint8_t p); +inline uint8_t time_ext_get_prescaler(void); + +/* + * Get time (seconds only, nanos only, or both) + */ +inline uint32_t time_ext_get_s(void); +inline uint32_t time_ext_get_ns(void); +time_ext_t time_ext_get(void); + +/* + * Sets the global time. + * This resets TCNT2 as well + */ +inline void time_ext_set(uint32_t sec, uint32_t nano); + +#endif /* _TIME_EXT_H_ */ diff --git a/modules/base/utils/CVS/Entries b/modules/base/utils/CVS/Entries new file mode 100644 index 0000000..e4687c0 --- /dev/null +++ b/modules/base/utils/CVS/Entries @@ -0,0 +1,6 @@ +/hertz.h/1.2.10.2/Wed May 23 17:18:11 2007//Tb_zer0 +/irq_lock_macros.h/1.9.4.2/Wed May 23 17:18:11 2007//Tb_zer0 +/utils.h/1.36.4.3/Wed May 23 17:18:11 2007//Tb_zer0 +/utils_errno.h/1.3.4.3/Wed May 23 17:18:11 2007//Tb_zer0 +/utils_types.h/1.5.4.2/Wed May 23 17:18:11 2007//Tb_zer0 +D diff --git a/modules/base/utils/CVS/Repository b/modules/base/utils/CVS/Repository new file mode 100644 index 0000000..d890d4d --- /dev/null +++ b/modules/base/utils/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/utils diff --git a/modules/base/utils/CVS/Root b/modules/base/utils/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/utils/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/utils/CVS/Tag b/modules/base/utils/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/utils/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/utils/CVS/Template b/modules/base/utils/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/utils/hertz.h b/modules/base/utils/hertz.h new file mode 100644 index 0000000..dc4d5f9 --- /dev/null +++ b/modules/base/utils/hertz.h @@ -0,0 +1,26 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: hertz.h,v 1.2.10.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +/** these defs are used mainly to define frequency of quartz, and interrupts ... */ + +#warning "This file is deprecated, include <aversive.h> instead" + +#include <aversive.h> diff --git a/modules/base/utils/irq_lock_macros.h b/modules/base/utils/irq_lock_macros.h new file mode 100644 index 0000000..f800d3b --- /dev/null +++ b/modules/base/utils/irq_lock_macros.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: irq_lock_macros.h,v 1.9.4.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#warning "This file is deprecated, use <aversive/irq_lock.h> instead" + +#include <aversive/irq_lock.h> + diff --git a/modules/base/utils/utils.h b/modules/base/utils/utils.h new file mode 100644 index 0000000..2eeb612 --- /dev/null +++ b/modules/base/utils/utils.h @@ -0,0 +1,24 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: utils.h,v 1.36.4.3 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#warning "This file is deprecated, use <aversive.h> instead" + +#include <aversive.h> diff --git a/modules/base/utils/utils_errno.h b/modules/base/utils/utils_errno.h new file mode 100644 index 0000000..9498ea2 --- /dev/null +++ b/modules/base/utils/utils_errno.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: utils_errno.h,v 1.3.4.3 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#warning "This file is deprecated, include <aversive/errno.h> instead" +#include <aversive/errno.h> diff --git a/modules/base/utils/utils_types.h b/modules/base/utils/utils_types.h new file mode 100644 index 0000000..09a147c --- /dev/null +++ b/modules/base/utils/utils_types.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: utils_types.h,v 1.5.4.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#warning "This file is deprecated, include <aversive/types.h> instead" +#include <aversive/types.h> diff --git a/modules/base/wait/CVS/Entries b/modules/base/wait/CVS/Entries new file mode 100644 index 0000000..21beedb --- /dev/null +++ b/modules/base/wait/CVS/Entries @@ -0,0 +1,2 @@ +/wait.h/1.13.4.2/Wed May 23 17:18:11 2007//Tb_zer0 +D diff --git a/modules/base/wait/CVS/Repository b/modules/base/wait/CVS/Repository new file mode 100644 index 0000000..e72d570 --- /dev/null +++ b/modules/base/wait/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/base/wait diff --git a/modules/base/wait/CVS/Root b/modules/base/wait/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/base/wait/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/base/wait/CVS/Tag b/modules/base/wait/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/base/wait/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/base/wait/CVS/Template b/modules/base/wait/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/base/wait/wait.h b/modules/base/wait/wait.h new file mode 100644 index 0000000..ffd1287 --- /dev/null +++ b/modules/base/wait/wait.h @@ -0,0 +1,24 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: wait.h,v 1.13.4.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#warning "This include file is deprecated, please use <aversive/wait.h>" + +#include <aversive/wait.h> diff --git a/modules/comm/CVS/Entries b/modules/comm/CVS/Entries new file mode 100644 index 0000000..b29178a --- /dev/null +++ b/modules/comm/CVS/Entries @@ -0,0 +1,5 @@ +D/i2c//// +D/mf2_client//// +D/mf2_server//// +D/spi//// +D/uart//// diff --git a/modules/comm/CVS/Repository b/modules/comm/CVS/Repository new file mode 100644 index 0000000..b2eb325 --- /dev/null +++ b/modules/comm/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm diff --git a/modules/comm/CVS/Root b/modules/comm/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/CVS/Tag b/modules/comm/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/CVS/Template b/modules/comm/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/i2c/CVS/Entries b/modules/comm/i2c/CVS/Entries new file mode 100644 index 0000000..aa25e52 --- /dev/null +++ b/modules/comm/i2c/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.1.2.1/Mon Jan 15 20:14:56 2007//Tb_zer0 +/i2c.c/1.1.2.12/Fri Apr 24 19:26:54 2009//Tb_zer0 +/i2c.h/1.1.2.9/Fri Jan 23 22:57:17 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/comm/i2c/CVS/Repository b/modules/comm/i2c/CVS/Repository new file mode 100644 index 0000000..efa9afc --- /dev/null +++ b/modules/comm/i2c/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/i2c diff --git a/modules/comm/i2c/CVS/Root b/modules/comm/i2c/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/i2c/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/i2c/CVS/Tag b/modules/comm/i2c/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/i2c/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/i2c/CVS/Template b/modules/comm/i2c/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/i2c/Makefile b/modules/comm/i2c/Makefile new file mode 100644 index 0000000..5cab808 --- /dev/null +++ b/modules/comm/i2c/Makefile @@ -0,0 +1,6 @@ +TARGET = i2c + +# List C source files here. (C dependencies are automatically generated.) +SRC = i2c.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/comm/i2c/config/CVS/Entries b/modules/comm/i2c/config/CVS/Entries new file mode 100644 index 0000000..a949406 --- /dev/null +++ b/modules/comm/i2c/config/CVS/Entries @@ -0,0 +1,2 @@ +/i2c_config.h/1.1.2.1/Sun Jun 24 19:55:54 2007//Tb_zer0 +D diff --git a/modules/comm/i2c/config/CVS/Repository b/modules/comm/i2c/config/CVS/Repository new file mode 100644 index 0000000..d53c93e --- /dev/null +++ b/modules/comm/i2c/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/i2c/config diff --git a/modules/comm/i2c/config/CVS/Root b/modules/comm/i2c/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/i2c/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/i2c/config/CVS/Tag b/modules/comm/i2c/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/i2c/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/i2c/config/CVS/Template b/modules/comm/i2c/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/i2c/config/i2c_config.h b/modules/comm/i2c/config/i2c_config.h new file mode 100644 index 0000000..1075e85 --- /dev/null +++ b/modules/comm/i2c/config/i2c_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.1.2.1 2007-06-24 19:55:54 zer0 Exp $ + * + */ + + +#define I2C_BITRATE 1 // divider dor i2c baudrate, see TWBR in doc +#define I2C_PRESCALER 3 // prescaler config, rate = 2^(n*2) + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 16 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 16 diff --git a/modules/comm/i2c/i2c.c b/modules/comm/i2c/i2c.c new file mode 100644 index 0000000..d1832a3 --- /dev/null +++ b/modules/comm/i2c/i2c.c @@ -0,0 +1,827 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c.c,v 1.1.2.12 2009-04-24 19:26:54 zer0 Exp $ + * + */ + +/* + * Author : Olivier MATZ zer0@droids-corp.org + * + * Thanks to Tof for the old i2c module and to Serpilliere for + * testing. + */ + +#include <stdlib.h> +#include <string.h> +#include <util/twi.h> + +#include <autoconf.h> +#include <aversive/errno.h> +#include <i2c.h> + +#if I2C_SEND_BUFFER_SIZE < 1 +#error "I2C_SEND_BUFFER_SIZE must be at least 1" +#endif + +#if I2C_RECV_BUFFER_SIZE < 1 +#error "I2C_RECV_BUFFER_SIZE must be at least 1" +#endif + +/** recv event, called when we receive a frame + * params are : data buffer and size */ +static void (*g_recv_event)(uint8_t *, int8_t) = NULL; + +/** recv event, called when we receive a byte + * params are : hwstatus, index of byte in frame, byte value */ +static void (*g_recv_byte_event)(uint8_t, uint8_t, uint8_t) = NULL; + +/** send event, called when transmit is complete + * param is error code : 0 if success */ +static void (*g_send_event)(int8_t) = NULL; + +static volatile i2c_mode_t g_mode = I2C_MODE_UNINIT; +static volatile uint8_t g_status = I2C_STATUS_READY; + +static volatile uint8_t g_ctrl = 0; /* ctrl flags */ +static volatile uint8_t g_sync_res = 0; /* result of sync send */ +static uint8_t g_send_buf[I2C_SEND_BUFFER_SIZE]; +static uint8_t g_recv_buf[I2C_RECV_BUFFER_SIZE]; +static volatile uint8_t g_dest = 0; /* destination slave in master mode */ + + +static volatile uint8_t g_send_nbytes = 0; /* number of transmitted bytes */ +static volatile uint8_t g_send_size = 0; /* size of buffer to be transmitted */ +static volatile uint8_t g_recv_nbytes = 0; /* number of received bytes */ +static volatile uint8_t g_recv_size = 0; /* size of buffer to be received */ + +#if I2C_DEBUG == 1 +#include <stdio.h> +#include <aversive/pgmspace.h> +static volatile uint8_t g_prev_twstatus = 0; +static volatile uint8_t g_intr_cpt = 0; +static volatile uint8_t g_prev_status = 0; +static volatile uint8_t g_command = 0; +#endif + +/** + * mode is I2C_MODE_UNINIT, I2C_MODE_MASTER, I2C_MODE_MULTIMASTER or + * I2C_MODE_SLAVE. Parameter add is the address in slave mode, it is + * composed from: + * b7 : true if the uC can be addressed with GENCALL + * b0-6: slave address + */ +void +i2c_init(i2c_mode_t mode, uint8_t add) +{ + uint8_t flags; + + IRQ_LOCK(flags); + + if (mode == I2C_MODE_UNINIT) { + /* disable all */ + TWCR = 0; + IRQ_UNLOCK(flags); + return; + } +#ifdef CONFIG_MODULE_I2C_MASTER + else if (mode == I2C_MODE_MASTER) { + /* enable, enable int */ + TWCR = (1<<TWEN) | (1<<TWIE) ; + } +#endif + else { + /* enable, enable int, answer to own adress */ + TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWEA) ; + } + + TWBR = I2C_BITRATE; + + /* prescaler */ + if (I2C_PRESCALER & 1) + sbi(TWSR, TWPS0); + if (I2C_PRESCALER & 2) + sbi(TWSR, TWPS1); + + /* change for TWAR format */ + TWAR = add << 1 ; + + /* general call */ + if (add & 0x80) + sbi(TWAR, TWGCE); + + /* init vars */ + g_mode = mode; + g_status = I2C_STATUS_READY; + g_dest = 0; + g_ctrl = 0; + g_recv_nbytes = 0; + g_recv_size = 0; + g_send_nbytes = 0; + g_send_size = 0; + + IRQ_UNLOCK(flags); +} + + +/** + * Register a function that is called when a buffer is received. The + * user application is always notified when data frame is received. + * Arguments of the callback are: + * - (recv_buf, n>0) if transmission succedded. The first parameter + * contains the address of the reception buffer and + * the second contains the number of received bytes. + * - (NULL, err<0) if the transmission failed (slave not answering + * or arbiteration lost). The first parameter is + * NULL and the second contains the error code. + */ +void +i2c_register_recv_event(void (*event)(uint8_t *, int8_t)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_recv_event = event ; + IRQ_UNLOCK(flags); +} + +/** + * Register a function that is called when a byte is received. + * Arguments of the callback are: (hwstatus, numbyte, byte). The user + * app can modify the g_recv_size value, which is the number of bytes + * to be received in the frame: this can be done by calling + * i2c_set_recv_size(). + */ +void +i2c_register_recv_byte_event(void (*event)(uint8_t, uint8_t, uint8_t)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_recv_byte_event = event ; + IRQ_UNLOCK(flags); +} + +/** + * register a function that is called when a buffer is sent (or an + * error occured while sending) on the i2c bus. The event function is + * always called by software if the i2c_send() function returned 0. + * The parameter of the event function is the error code: + * - <0 if 0 byte has been transmitted (arbiteration lost) + * - Else, the number of transmitted bytes is given, including the + * one that was not acked. + */ +void +i2c_register_send_event(void (*event)(int8_t)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_send_event = event ; + IRQ_UNLOCK(flags); +} + +/** + * Send a buffer. Return 0 if xmit starts correctly. + * On error, return < 0. + * - If mode is slave, dest_add should be I2C_ADD_MASTER, and transmission + * starts when the master transmits a clk. + * - If mode is master and if dest_add != I2C_ADD_MASTER, it will transmit + * a START condition if bus is available (the uc will act as a + * master) + * - If mode is master and if dest_add == I2C_ADD_MASTER, the uC will + * act as a slave, and data will be sent when the uC will be + * addressed. + * The transmission will be processed with these params until a + * i2c_flush() is called. + * The 'ctrl' parameter is composed by the flags I2C_CTRL_SYNC and + * I2C_CTRL_DONT_RELEASE_BUS + */ +int8_t +i2c_send(uint8_t dest_add, uint8_t *buf, uint8_t size, uint8_t ctrl) +{ + uint8_t flags; + + IRQ_LOCK(flags); + if (g_mode == I2C_MODE_UNINIT) { + IRQ_UNLOCK(flags); + return -ENXIO; + } + + if (g_status & (I2C_STATUS_MASTER_XMIT | + I2C_STATUS_MASTER_RECV | + I2C_STATUS_SLAVE_XMIT_WAIT | + I2C_STATUS_SLAVE_XMIT)) { + IRQ_UNLOCK(flags); + return -EBUSY; + } + + if (size > I2C_SEND_BUFFER_SIZE) { /* XXX is size==0 ok ? */ + IRQ_UNLOCK(flags); + return -EINVAL; + } + + /* bad dest_address */ + if (g_mode == I2C_MODE_SLAVE) { + if (dest_add != I2C_ADD_MASTER) { + IRQ_UNLOCK(flags); + return -EINVAL; + } + } + else { + if (dest_add >= I2C_ADD_MASTER) { + IRQ_UNLOCK(flags); + return -EINVAL; + } + } + + /* if g_send_buf == buf, it is a resend, so don't update + * parameters */ + if ( g_send_buf != buf ) { + g_dest = dest_add; + g_send_size = size; + g_ctrl = ctrl; + memcpy(g_send_buf, buf, size); + } + + /* if destination is not the master, IT MEANS THAT WE ARE THE + * MASTER, so we should initiate the transmission */ + if (dest_add != I2C_ADD_MASTER) { + g_status |= I2C_STATUS_MASTER_XMIT; + TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE) | (1<<TWSTA); + } + else { + /* else we are a slave */ + g_status |= I2C_STATUS_SLAVE_XMIT_WAIT; + } + + IRQ_UNLOCK(flags); + + /* If it is sync mode, wait op_finished. Here we will reset + * the status flag to ready */ + if (ctrl & I2C_CTRL_SYNC) { + while ( 1 ) { + IRQ_LOCK(flags); + if (g_status & I2C_STATUS_OP_FINISHED) { + g_status &= ~(I2C_STATUS_MASTER_XMIT | + I2C_STATUS_MASTER_RECV | + I2C_STATUS_SLAVE_XMIT | + I2C_STATUS_SLAVE_RECV | + I2C_STATUS_OP_FINISHED); + break; + } + IRQ_UNLOCK(flags); + } + IRQ_UNLOCK(flags); + if (g_sync_res == size) + return 0; + return g_sync_res; + } + + return -ESUCCESS; +} + + +/** + * Resend the same buffer. This call is equivalent to i2c_send() with + * the same parameters as the last call. It safe to call it from the + * send_event, but else the send buffer may have been overwritten. + */ +int8_t +i2c_resend(void) +{ + return i2c_send(g_dest, g_send_buf, g_send_size, g_ctrl); +} + +/** + * same but for recv + */ +int8_t +i2c_rerecv(void) +{ + return i2c_recv(g_dest, g_recv_size, g_ctrl); +} + +/** + * release the bus + */ +void +i2c_release_bus(void) +{ + TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE) | (1<<TWSTO); +} + +/** + * recover from error state + */ +void +i2c_reset(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + TWCR = 0; + g_status = I2C_STATUS_READY; +#ifdef CONFIG_MODULE_I2C_MASTER + if (g_mode == I2C_MODE_MASTER) + TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE); + else +#endif + TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE) | + (1<<TWSTO) | (1<<TWEA); + IRQ_UNLOCK(flags); +} + +/** + * In slave mode, it returns error and is useless (all data is + * received trough the callback). In master mode, if dest_add is + * between 0 and 127, it will start to read the addressed slave. The + * size of the buffer to read must be specified. Return 0 on success. + */ +int8_t i2c_recv(uint8_t dest_add, uint8_t size, uint8_t ctrl) +{ +#ifndef CONFIG_MODULE_I2C_MASTER + return -EINVAL; +#else + uint8_t flags; + + IRQ_LOCK(flags); + if (g_mode == I2C_MODE_UNINIT) { + IRQ_UNLOCK(flags); + return -ENXIO; + } + + if (g_status != I2C_STATUS_READY) { + IRQ_UNLOCK(flags); + return -EBUSY; + } + + if (size > I2C_SEND_BUFFER_SIZE) { /* XXX is size=0 ok ? */ + IRQ_UNLOCK(flags); + return -EINVAL; + } + + if (g_mode == I2C_MODE_SLAVE || dest_add >= I2C_ADD_MASTER) { + IRQ_UNLOCK(flags); + return -EINVAL; + } + + g_ctrl = ctrl; + g_recv_size = size; + g_status |= I2C_STATUS_MASTER_RECV; + g_dest = dest_add ; + TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE) | (1<<TWSTA); + + IRQ_UNLOCK(flags); + + /* If it is sync mode, wait op_finished. Here we will reset + * the status flag to ready */ + if (ctrl & I2C_CTRL_SYNC) { + while ( 1 ) { + IRQ_LOCK(flags); + if (g_status & I2C_STATUS_OP_FINISHED) { + g_status &= ~(I2C_STATUS_MASTER_XMIT | + I2C_STATUS_MASTER_RECV | + I2C_STATUS_SLAVE_XMIT | + I2C_STATUS_SLAVE_RECV | + I2C_STATUS_OP_FINISHED); + break; + } + IRQ_UNLOCK(flags); + } + IRQ_UNLOCK(flags); + if (g_sync_res == size) + return 0; + return g_sync_res; + } + + return -ESUCCESS; +#endif +} + + +/** + * Try to flush the current operation, before it is started. The + * i2c module is then tagged as ready. If it returns 0, the flush was + * a success, and i2c_send() can be called. Else, it means that + * a transmission was running. + */ +int8_t i2c_flush(void) +{ + uint8_t flags; + IRQ_LOCK(flags); + if ( ! (g_status & I2C_STATUS_SLAVE_XMIT_WAIT) ) { + IRQ_UNLOCK(flags); + return -EBUSY; + } + + g_status &= ~(I2C_STATUS_SLAVE_XMIT_WAIT); + IRQ_UNLOCK(flags); + + return -ESUCCESS; +} + + +/** + * In MASTER RECEIVER mode, it is possible that the user application + * does not know the size of the buffer. You can adjust this size + * during transmission (generally the size can be specified at the + * beginning of received data, so the user app can be notified thanks + * to recv_byte_event(). Note that i2c_set_recv_size() function has to + * be used with careful, making sure you understand i2c protocol and + * this code. Return 0 on success. Note than in SLAVE RECEIVER mode, + * you don't have to use this function, because the master can end the + * transmission by sending a stop condition on the bus. + */ +uint8_t i2c_set_recv_size(uint8_t size) +{ + uint8_t flags; + + IRQ_LOCK(flags); + + /* check that we are in reveiver mode */ + if (! (g_status & I2C_STATUS_MASTER_RECV)) { + IRQ_UNLOCK(flags); + return -EBUSY; + } + + /* check that specified size is not greater than + * I2C_SEND_BUFFER_SIZE. But it must be greater than current + * number of received bytes. */ + /* XXX ? +1 ? */ + if (size > I2C_SEND_BUFFER_SIZE || size <= g_recv_nbytes) { + IRQ_UNLOCK(flags); + return -EINVAL; + } + + g_recv_size = size; + + IRQ_UNLOCK(flags); + return -ESUCCESS; +} + + +/** + * return the current mode of the i2c module. + */ +i2c_mode_t i2c_mode(void) +{ + return g_mode; +} + +/** + * return the status of the i2c module. + */ +uint8_t i2c_status(void) +{ + return g_status; +} + +/** + * Copy the received buffer in the buffer given as parameter. Return + * number of copied bytes or < 0 on error. + */ +uint8_t i2c_get_recv_buffer(uint8_t *buf, uint8_t size) +{ + uint8_t flags; + + IRQ_LOCK(flags); + /* check that reception is finished */ + if ( g_status & (I2C_STATUS_MASTER_RECV | + I2C_STATUS_SLAVE_RECV) ) { + IRQ_UNLOCK(flags); + return -EBUSY; + } + + if (size > g_recv_nbytes) + size = g_recv_nbytes; + memcpy(buf, g_recv_buf, size); + + IRQ_UNLOCK(flags); + + return size; +} + +#if I2C_DEBUG == 1 +void i2c_debug(void) +{ + printf_P(PSTR("mode=0x%x\r\n"), g_mode); + printf_P(PSTR("status=0x%x\r\n"), g_status); + printf_P(PSTR("ctrl=0x%x\r\n"), g_ctrl); + printf_P(PSTR("dst=%d\r\n"), g_dest); + printf_P(PSTR("send_nbytes=%d, send_size=%d\r\n"), g_send_nbytes, g_send_size); + printf_P(PSTR("recv_nbytes=%d, recv_size=%d\r\n"), g_recv_nbytes, g_recv_size); + printf_P(PSTR("prev_twstatus=0x%x\r\n"), g_prev_twstatus); + printf_P(PSTR("intr_cpt=%d\r\n"), g_intr_cpt); + printf_P(PSTR("prev_status=0x%x\r\n"), g_prev_status); + printf_P(PSTR("prev_command=0x%x\r\n"), g_command); +} +#endif + +/** interrupt ********************************************************/ + +/** + * Interrupt routing for I2C. Refer to datasheets for more + * informations. + */ +SIGNAL(SIG_2WIRE_SERIAL) +{ + uint8_t hard_status; + uint8_t command = (1<<TWINT) | (1<<TWEN) | (1<<TWIE); + + hard_status = TW_STATUS; + +#if I2C_DEBUG == 1 + g_prev_twstatus = hard_status; + g_intr_cpt++; +#endif + switch(hard_status) { + +#ifdef CONFIG_MODULE_I2C_MASTER + case TW_START: + case TW_REP_START: + /* a start has been transmitted, transmit SLA+W which is : + * b7-1: slave address + * b0 : 0 (write operation) or 1 (read) */ + if (g_status & I2C_STATUS_MASTER_RECV) { + TWDR = (g_dest << 1) | (0x01); + g_recv_nbytes = 0; + } + else { + TWDR = (g_dest << 1); + g_send_nbytes = 0; + } + break; + + + /* MASTER TRANSMITTER */ + + case TW_MT_SLA_ACK: + /* the slave is there. start sending data */ + TWDR = g_send_buf[g_send_nbytes++]; + break; + + case TW_MT_SLA_NACK: + /* the slave does not answer, send a stop condition */ + g_send_nbytes = -ENOENT; + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_XMIT_EVT); + break; + + case TW_MT_DATA_ACK: /* 0x28 */ + /* we transmitted data with success, send next one or + * stop condition if there is no more data */ + if (g_send_nbytes >= g_send_size) { + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_XMIT_EVT); + } + else { + TWDR = g_send_buf[g_send_nbytes++]; + } + break; + + case TW_MT_DATA_NACK: + /* we transmitted data but slave sent us a NACK. + * Notify the number of bytes sent, including the one + * that were not acked, and send a stop condition */ + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_XMIT_EVT); + break; + + + /* MASTER RECEIVER */ + + case TW_MR_SLA_ACK: + /* the slave is there, we know that we have enough + * room in buffer because it is the 1st byte. If + * there's only 1 byte to receive, don't set TWEA */ + if (g_recv_size > 1) + command |= (1<<TWEA); + break; + + case TW_MR_SLA_NACK: + /* the slave does not answer, send a stop condition */ + g_recv_nbytes = -ENOENT; + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_RECV_EVT); + break; + + case TW_MR_DATA_ACK: + /* receive data */ + if (g_recv_nbytes < g_recv_size) { + g_recv_buf[g_recv_nbytes] = TWDR; + + if(g_recv_byte_event) + g_recv_byte_event(hard_status, g_recv_nbytes, g_recv_buf[g_recv_nbytes]); + + g_recv_nbytes++; + } + /* More than one byte remaining -> set TWEA */ + if (g_recv_nbytes < g_recv_size) { + command |= (1<<TWEA); + } + break; + + case TW_MR_DATA_NACK: + /* we received the last byte */ + if (g_recv_nbytes < g_recv_size) { + g_recv_buf[g_recv_nbytes] = TWDR; + + if(g_recv_byte_event) + g_recv_byte_event(hard_status, g_recv_nbytes, g_recv_buf[g_recv_nbytes]); + g_recv_nbytes ++; + } + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_RECV_EVT); + break; + + + /* MASTER TRANSMITTER or MASTER RECEIVER */ + + case TW_MT_ARB_LOST: + /* arbitration lost, notify application */ + /* XXX here we may have to change status flags ? */ + if (g_status & I2C_STATUS_MASTER_XMIT) { + g_recv_nbytes = -EAGAIN; + g_status |= I2C_STATUS_NEED_RECV_EVT; + } + else if (g_status & I2C_STATUS_MASTER_RECV) { + g_send_nbytes = -EAGAIN; + g_status |= I2C_STATUS_NEED_XMIT_EVT; + } + /* g_status |= I2C_STATUS_OP_FINISHED; */ /* ?? or not ? */ + break; + +#endif + + + /* SLAVE RECEIVER */ + + case TW_SR_ARB_LOST_SLA_ACK: + case TW_SR_ARB_LOST_GCALL_ACK: + case TW_SR_GCALL_ACK: + case TW_SR_SLA_ACK: + /* slave is addressed (in general call or not, and + * after arbiteration lost or not) */ + g_recv_nbytes = 0; + g_recv_size = I2C_RECV_BUFFER_SIZE; + g_status |= I2C_STATUS_SLAVE_RECV; + command |= (1<<TWEA); + break; + + case TW_SR_DATA_ACK: + case TW_SR_GCALL_DATA_ACK: + /* receive data, the following test should always be + * true */ + if (g_recv_nbytes < g_recv_size) { + g_recv_buf[g_recv_nbytes] = TWDR; + if(g_recv_byte_event) + g_recv_byte_event(hard_status, g_recv_nbytes, g_recv_buf[g_recv_nbytes]); + g_recv_nbytes++; + } + /* if there's more than one byte left in buffer, send + * TWEA */ + if (g_recv_nbytes < g_recv_size) { + command |= (1<<TWEA); + } + break; + + case TW_SR_GCALL_DATA_NACK: + case TW_SR_DATA_NACK: + /* receive last data byte (our buffer is full) */ + if (g_recv_nbytes < g_recv_size) { + g_recv_buf[g_recv_nbytes] = TWDR; + + if(g_recv_byte_event) + g_recv_byte_event(hard_status, g_recv_nbytes, g_recv_buf[g_recv_nbytes]); + g_recv_nbytes++; + } + break; + + case TW_SR_STOP: + /* the master sent a stop condition, notify app */ + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_RECV_EVT); + break; + + + /* SLAVE TRANSMITTER */ + + case TW_ST_ARB_LOST_SLA_ACK: + case TW_ST_SLA_ACK: + /* slave is addressed. If it is not ready, send a 0 as + * last byte. */ + g_send_nbytes = 0; + if (! (g_status & I2C_STATUS_SLAVE_XMIT_WAIT)) { + TWDR = 0; + g_send_size=0; + } + /* else: + * if there is only 1 byte to transmit, we don't + * need to send ack, else set TWEA. */ + else { + if (g_send_size > 1) { + command |= (1<<TWEA); + } + TWDR = g_send_buf[g_send_nbytes++]; + } + g_status &= ~(I2C_STATUS_SLAVE_XMIT_WAIT); + g_status |= I2C_STATUS_SLAVE_XMIT; + break; + + case TW_ST_DATA_ACK: + /* transmitting data, if there is more than one byte + * to send, send ack */ + if (g_send_size > g_send_nbytes + 1) + command |= (1<<TWEA); + TWDR = g_send_buf[g_send_nbytes++]; + break; + + case TW_ST_DATA_NACK: + /* notify app that we send the frame */ + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_XMIT_EVT); + break; + + + case TW_ST_LAST_DATA: + /* last data transmitted, notify app XXX (not very sure) */ + g_status |= (I2C_STATUS_OP_FINISHED | I2C_STATUS_NEED_XMIT_EVT); + break; + + + /* COMMON */ + + case TW_BUS_ERROR: + command |= (1<<TWSTO); + g_status |= I2C_STATUS_OP_FINISHED; + break; + + default : + /* default ... what can we do ? */ + g_status |= I2C_STATUS_OP_FINISHED; + break; + + } + +#if I2C_DEBUG == 1 + g_prev_status = g_status; +#endif + + /* transmission finished */ + if (g_status & I2C_STATUS_OP_FINISHED) { + /* if it is not a synchronous op, we should be aware + * of next SLA+RW if we are a slave or multimaster */ +#ifdef CONFIG_MODULE_I2C_MASTER + if (g_mode != I2C_MODE_MASTER) { + command |= (1<<TWEA); + } + else if ( ! (g_ctrl & I2C_CTRL_DONT_RELEASE_BUS) ) { + /* do it only if we want to release bus */ + command |= (1<<TWSTO); + } +#else /* CONFIG_MODULE_I2C_MASTER */ + command |= (1<<TWEA); +#endif + /* Remove current op if !sync, else it is done in the + * i2c_send/recv func */ + if ( ! (g_ctrl & I2C_CTRL_SYNC) ) { + g_status &= ~(I2C_STATUS_MASTER_XMIT | + I2C_STATUS_MASTER_RECV | + I2C_STATUS_SLAVE_XMIT | + I2C_STATUS_SLAVE_RECV | + I2C_STATUS_OP_FINISHED); + } + } + + /* Callback events if necessary (if not sync) */ + if ( ! (g_ctrl & I2C_CTRL_SYNC) ) { + if ( (g_status & I2C_STATUS_NEED_XMIT_EVT) && g_send_event) { + g_send_event(g_send_nbytes); + } + if ( (g_status & I2C_STATUS_NEED_RECV_EVT) && g_recv_event) { + g_recv_event(g_recv_buf, g_recv_nbytes); + } + } + else { + if ( g_status & (I2C_STATUS_MASTER_XMIT | I2C_STATUS_SLAVE_XMIT) ) + g_sync_res = g_send_nbytes; + else + g_sync_res = g_recv_nbytes; + } + g_status &= ~(I2C_STATUS_NEED_XMIT_EVT | I2C_STATUS_NEED_RECV_EVT); + +#if I2C_DEBUG == 1 + g_command = command; +#endif + + /* if a command (repeated start) has been sent in the callback + * (by calling i2c_send() or i2c_recv(), we don't need to + * send it (we are back in MASTER_SEND or MASTER_RECV mode) */ + if (TWCR & (1<<TWINT)) + TWCR = command; +} diff --git a/modules/comm/i2c/i2c.h b/modules/comm/i2c/i2c.h new file mode 100644 index 0000000..6f241c6 --- /dev/null +++ b/modules/comm/i2c/i2c.h @@ -0,0 +1,248 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c.h,v 1.1.2.9 2009-01-23 22:57:17 zer0 Exp $ + * + */ + +/* Author Zer0, based on Tof old i2c module */ + +/** please read carefully ! + * + * + * this implementation of the i2c interface is very specific this is a + * multi bus implementation. The multi bus operation is done by + * implementing software i2c modules (slave only) + * + * HARDWARE I2C : + * -------------- + * + * This module implements i2c using the hardware twi interface of AVR + * devices. It can operates in slave and/or master mode, depending on + * the initialisation parameter. This module is interrupt driven only. + * + * In master mode, buffer can be transmitted/received on demand (with + * start and stop conditions). In slave mode, operations are done + * asynchronously. Like some other modules in aversive, callback + * functions can be registered and are called on transmission or + * reception events. + * + * This module should support multimaster mode, send() or recv() depends + * on the address parameter. + */ +#ifndef _I2C_H_ +#define _I2C_H_ + +#include <aversive.h> +#include <i2c_config.h> + +#define I2C_DEBUG 1 + +#define I2C_ADD_GENCALL 0x00 + +/* this is not a valid address regarding the I2C protocol, but is used + * as a magic for addressing the master from the slave */ +#define I2C_ADD_MASTER 0x80 + + + + +/* I2C modes */ +typedef enum { I2C_MODE_UNINIT, /**< not initialized */ + I2C_MODE_SLAVE, /**< Slave */ +#ifdef CONFIG_MODULE_I2C_MASTER + I2C_MODE_MASTER, /**< Master */ +#endif +#ifdef CONFIG_MODULE_I2C_MULTIMASTER + I2C_MODE_MULTIMASTER, /**< Master, but allow multimaster mode */ +#endif +} i2c_mode_t ; + +/* control flags */ +#define I2C_CTRL_GENERIC 0x00 +/** Error code is returned instead of beeing sent as a callback. Note + * that the send_event callback is _not_ called if it is + * registered. This functions waits and only returns when the + * transmission is finished or if it failed. Note that there is no + * timeout, so it can loop forever... WARNING : irq MUST be + * allowed */ +#define I2C_CTRL_SYNC 0x01 +/** when the operation is finished as a master, don't release the bus + * (don't send any stop condition). You can send several commands + * without beeing interrupted by another master. To release it, send + * another command without this flag or just call + * i2c_release_bus(). This has no effect on a slave. */ +#define I2C_CTRL_DONT_RELEASE_BUS 0x02 + + +/* status flags */ +#define I2C_STATUS_READY 0x00 +#define I2C_STATUS_MASTER_XMIT 0x01 +#define I2C_STATUS_MASTER_RECV 0x02 +#define I2C_STATUS_SLAVE_XMIT_WAIT 0x04 +#define I2C_STATUS_SLAVE_XMIT 0x08 +#define I2C_STATUS_SLAVE_RECV 0x10 +#define I2C_STATUS_OP_FINISHED 0x20 +#define I2C_STATUS_NEED_XMIT_EVT 0x40 +#define I2C_STATUS_NEED_RECV_EVT 0x80 + + +/** + * mode is I2C_MODE_UNINIT, I2C_MODE_MASTER, I2C_MODE_MULTIMASTER or + * I2C_MODE_SLAVE. Parameter add is the address in slave mode, it is + * composed from: + * b7 : true if the uC can be addressed with GENCALL + * b0-6: slave address + */ +void i2c_init(i2c_mode_t mode, uint8_t add); + + +/** + * Register a function that is called when a buffer is received. The + * user application is always notified when data frame is received. + * Arguments of the callback are: + * - (recv_buf, n>0) if transmission succedded. The first parameter + * contains the address of the reception buffer and + * the second contains the number of received bytes. + * - (NULL, err<0) if the transmission failed (slave not answering + * or arbiteration lost). The first parameter is + * NULL and the second contains the error code. + */ +void i2c_register_recv_event(void (*event)(uint8_t *, int8_t)); + +/** + * Register a function that is called when a byte is received. + * Arguments of the callback are: (hwstatus, numbyte, byte). The user + * app can modify the g_size value, which is the number of bytes to be + * received in the frame: this can be done by calling + * i2c_set_recv_size(). + */ +void i2c_register_recv_byte_event(void (*event)(uint8_t, uint8_t, uint8_t)); + + +/** + * register a function that is called when a buffer is sent (or an + * error occured while sending) on the i2c bus. The event function is + * always called by software if the i2c_send() function returned 0. + * The parameter of the event function is the error code: + * - 0 if the number of transmitted bytes is equal to the size + * of the original send buffer, without NACK. + * - <0 if 0 byte has been transmitted (slave not answering or + * arbiteration lost) + * - Else, the number of transmitted bytes is given, including the + * one that was not acked. + */ +void i2c_register_send_event(void (*event)(int8_t)); + + +/** + * Send a buffer. Return 0 if xmit starts correctly. + * On error, return < 0. + * - If mode is slave, dest_add should be I2C_ADD_MASTER, and transmission + * starts when the master transmits a clk. + * - If mode is master and if dest_add != I2C_ADD_MASTER, it will transmit + * a START condition if bus is available (the uc will act as a + * master) + * - If mode is master and if dest_add == I2C_ADD_MASTER, the uC will + * act as a slave, and data will be sent when the uC will be + * addressed. + * The transmission will be processed with these params until a + * i2c_flush() is called. + * The 'ctrl' parameter is composed by the flags I2C_CTRL_SYNC and + * I2C_CTRL_DONT_RELEASE_BUS + */ +int8_t i2c_send(uint8_t dest_add, uint8_t *buf, uint8_t size, uint8_t ctrl); + +/** + * Resend the same buffer. This call is equivalent to i2c_send() with + * the same parameters as the last call. It safe to call it from the + * send_event, but else the send buffer may have been overwritten. + */ +int8_t i2c_resend(void); + +/** + * same but for recv + */ +int8_t i2c_rerecv(void); + +/** + * release the bus + */ +void i2c_release_bus(void); + +/** + * In slave mode, it returns error and is useless (all data is + * received trough the callback). In master mode, if dest_add is + * between 0 and 127, it will start to read the addressed slave. The + * size of the buffer to read must be specified. Return 0 on success. + * The 'ctrl' parameter is composed by the flags I2C_CTRL_SYNC and + * I2C_CTRL_DONT_RELEASE_BUS + */ +int8_t i2c_recv(uint8_t dest_add, uint8_t size, uint8_t ctrl); + + +/** + * Try to flush the current operation, before it is started. The + * i2c module is then tagged as ready. If it returns 0, the flush was + * a success, and i2c_send() can be called. Else, it means that + * a transmission was running. + */ +int8_t i2c_flush(void); + +/** + * In MASTER RECEIVER mode, it is possible that the user application + * does not know the size of the buffer. You can adjust this size + * during transmission (generally the size can be specified at the + * beginning of received data, so the user app can be notified thanks + * to recv_byte_event(). Note that i2c_set_recv_size() function has to + * be used with careful, making sure you understand i2c protocol and + * this code. Return 0 on success. Note than in SLAVE RECEIVER mode, + * you don't have to use this function, because the master can end the + * transmission by sending a stop condition on the bus. + */ +uint8_t i2c_set_recv_size(uint8_t size); + +/** + * return the current mode of the i2c module. + */ +i2c_mode_t i2c_mode(void); + +/** + * return the status of the i2c module. + */ +uint8_t i2c_status(void); + +/** + * Copy the received buffer in the buffer given as parameter. Return + * number of copied bytes or < 0 on error. + */ +uint8_t i2c_get_recv_buffer(uint8_t *buf, uint8_t size); + +/** + * recover from error states + */ +void i2c_reset(void); + +#if I2C_DEBUG == 1 +/** + * display debug infos + */ +void i2c_debug(void); +#endif + + +#endif diff --git a/modules/comm/i2c/test/.config b/modules/comm/i2c/test/.config new file mode 100644 index 0000000..aac71a3 --- /dev/null +++ b/modules/comm/i2c/test/.config @@ -0,0 +1,204 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_UTILS=y +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_WAIT=y +CONFIG_MODULE_LIST=y +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +CONFIG_MODULE_I2C=y +CONFIG_MODULE_I2C_MASTER=y +CONFIG_MODULE_I2C_MULTIMASTER=y +CONFIG_MODULE_I2C_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable utils and pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set + +# +# Encoders (you should enable utils and fixed_point modules to see all available encoders) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/comm/i2c/test/CVS/Entries b/modules/comm/i2c/test/CVS/Entries new file mode 100644 index 0000000..657e088 --- /dev/null +++ b/modules/comm/i2c/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.1.2.1/Mon Jan 15 20:14:56 2007//Tb_zer0 +/Makefile/1.1.2.1/Mon Jan 15 20:14:56 2007//Tb_zer0 +/error_config.h/1.1.2.1/Mon Jan 15 20:14:56 2007//Tb_zer0 +/i2c_config.h/1.1.2.1/Mon Jan 15 20:14:56 2007//Tb_zer0 +/main.c/1.1.2.2/Wed May 23 17:18:11 2007//Tb_zer0 +D diff --git a/modules/comm/i2c/test/CVS/Repository b/modules/comm/i2c/test/CVS/Repository new file mode 100644 index 0000000..93c2c90 --- /dev/null +++ b/modules/comm/i2c/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/i2c/test diff --git a/modules/comm/i2c/test/CVS/Root b/modules/comm/i2c/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/i2c/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/i2c/test/CVS/Tag b/modules/comm/i2c/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/i2c/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/i2c/test/CVS/Template b/modules/comm/i2c/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/i2c/test/Makefile b/modules/comm/i2c/test/Makefile new file mode 100644 index 0000000..ed79efe --- /dev/null +++ b/modules/comm/i2c/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/comm/i2c/test/error_config.h b/modules/comm/i2c/test/error_config.h new file mode 100644 index 0000000..7abc7c5 --- /dev/null +++ b/modules/comm/i2c/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-01-15 20:14:56 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/comm/i2c/test/i2c_config.h b/modules/comm/i2c/test/i2c_config.h new file mode 100644 index 0000000..1452e9f --- /dev/null +++ b/modules/comm/i2c/test/i2c_config.h @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.1.2.1 2007-01-15 20:14:56 zer0 Exp $ + * + */ + +/* divider dor i2c baudrate, see TWBR in doc */ +#define I2C_BITRATE 1 + +/* prescaler config, rate = 2^(n*2) */ +#define I2C_PRESCALER 3 + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 16 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 16 diff --git a/modules/comm/i2c/test/main.c b/modules/comm/i2c/test/main.c new file mode 100644 index 0000000..0d11a08 --- /dev/null +++ b/modules/comm/i2c/test/main.c @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#include <aversive.h> + + +int main(void) +{ +#ifndef HOST_VERSION + uint8_t flags, flags2; + + IRQ_LOCK(flags); + IRQ_UNLOCK(flags); + + IRQ_LOCK(flags); + IRQ_LOCK(flags2); + IRQ_UNLOCK(flags2); + IRQ_UNLOCK(flags); +#endif + return 0; +} diff --git a/modules/comm/mf2_client/CVS/Entries b/modules/comm/mf2_client/CVS/Entries new file mode 100644 index 0000000..4c82877 --- /dev/null +++ b/modules/comm/mf2_client/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +/mf2_client.c/1.1.2.5/Wed May 23 17:18:11 2007//Tb_zer0 +/mf2_client.h/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/comm/mf2_client/CVS/Repository b/modules/comm/mf2_client/CVS/Repository new file mode 100644 index 0000000..6e3b3c0 --- /dev/null +++ b/modules/comm/mf2_client/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/mf2_client diff --git a/modules/comm/mf2_client/CVS/Root b/modules/comm/mf2_client/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/mf2_client/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/mf2_client/CVS/Tag b/modules/comm/mf2_client/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/mf2_client/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/mf2_client/CVS/Template b/modules/comm/mf2_client/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/mf2_client/Makefile b/modules/comm/mf2_client/Makefile new file mode 100644 index 0000000..1c5bb22 --- /dev/null +++ b/modules/comm/mf2_client/Makefile @@ -0,0 +1,6 @@ +TARGET = mf2_client + +# List C source files here. (C dependencies are automatically generated.) +SRC = mf2_client.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/comm/mf2_client/config/CVS/Entries b/modules/comm/mf2_client/config/CVS/Entries new file mode 100644 index 0000000..6bcf0d1 --- /dev/null +++ b/modules/comm/mf2_client/config/CVS/Entries @@ -0,0 +1,3 @@ +/mf2_client_config.h/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +/mf2_server_config.h/1.1.2.1/Sat Mar 10 21:14:52 2007//Tb_zer0 +D diff --git a/modules/comm/mf2_client/config/CVS/Repository b/modules/comm/mf2_client/config/CVS/Repository new file mode 100644 index 0000000..ffe2266 --- /dev/null +++ b/modules/comm/mf2_client/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/mf2_client/config diff --git a/modules/comm/mf2_client/config/CVS/Root b/modules/comm/mf2_client/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/mf2_client/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/mf2_client/config/CVS/Tag b/modules/comm/mf2_client/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/mf2_client/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/mf2_client/config/CVS/Template b/modules/comm/mf2_client/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/mf2_client/config/mf2_client_config.h b/modules/comm/mf2_client/config/mf2_client_config.h new file mode 100644 index 0000000..3cba2c8 --- /dev/null +++ b/modules/comm/mf2_client/config/mf2_client_config.h @@ -0,0 +1,41 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_client_config.h,v 1.1.2.1 2006-11-30 21:59:07 zer0 Exp $ + * + */ + +#ifndef MF2_CLIENT_CONFIG_H +#define MF2_CLIENT_CONFIG_H + +#define MF2_CLIENT_DATA_PORT PORTB +#define MF2_CLIENT_DATA_BIT 0 + +/* MF2 clk should be an external interrupt pin */ +#define MF2_CLIENT_CLK_PORT PORTE +#define MF2_CLIENT_CLK_BIT 4 + +#define MF2_CLIENT_INTERRUPT SIG_INTERRUPT4 +#define MF2_CLIENT_INT_REG EICRB +#define MF2_CLIENT_INT_BIT0 ISC40 +#define MF2_CLIENT_INT_BIT1 ISC41 +#define MF2_CLIENT_IMASK EIMSK +#define MF2_CLIENT_IFLAG EIFR +#define MF2_CLIENT_IMASK_BIT 4 + +#endif + diff --git a/modules/comm/mf2_client/config/mf2_server_config.h b/modules/comm/mf2_client/config/mf2_server_config.h new file mode 100644 index 0000000..3c64879 --- /dev/null +++ b/modules/comm/mf2_client/config/mf2_server_config.h @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_server_config.h,v 1.1.2.1 2007-03-10 21:14:52 zer0 Exp $ + * + */ + +#ifndef MF2_SERVER_CONFIG_H +#define MF2_SERVER_CONFIG_H + +#define MF2_SERVER_DATA_PORT PORTB +#define MF2_SERVER_DATA_BIT 0 + +#define MF2_SERVER_CLK_PORT PORTE +#define MF2_SERVER_CLK_BIT 4 + +#endif + diff --git a/modules/comm/mf2_client/mf2_client.c b/modules/comm/mf2_client/mf2_client.c new file mode 100644 index 0000000..92803b1 --- /dev/null +++ b/modules/comm/mf2_client/mf2_client.c @@ -0,0 +1,321 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_client.c,v 1.1.2.5 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2006 */ + +#include <stdio.h> + +#include <aversive.h> +#include <mf2_client.h> +#include <mf2_client_config.h> + +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER +#include <scheduler.h> +#else +#include <aversive/wait.h> +#endif + +#define WATCHDOG_TIMEOUT 10000 + +#define MF2_CLIENT_STATE_IDLE 0 +#define MF2_CLIENT_STATE_RECV 1 +#define MF2_CLIENT_STATE_XMIT 2 +#define MF2_CLIENT_STATE_ACK 3 + +#define data_Z() cbi(DDR(MF2_CLIENT_DATA_PORT), MF2_CLIENT_DATA_BIT) +#define data_0() sbi(DDR(MF2_CLIENT_DATA_PORT), MF2_CLIENT_DATA_BIT) +#define clk_Z() cbi(DDR(MF2_CLIENT_CLK_PORT), MF2_CLIENT_CLK_BIT) +#define clk_0() sbi(DDR(MF2_CLIENT_CLK_PORT), MF2_CLIENT_CLK_BIT) + +/* XXX s08 -> int8_t */ + +static volatile u08 state=MF2_CLIENT_STATE_IDLE; +static volatile u08 current_bitnum; +static volatile u16 rx_buf; +static volatile u16 tx_buf; +static volatile u08 tx_c; +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER +static volatile s08 sched_event = -1; +#endif + +typedef void (event)(char); + +static event * tx_event = NULL; +static event * rx_event = NULL; + +static s16 check_rx_buf(u16 buf); + +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER +static void watchdog_timeout(void * dummy); +#endif + +static void disable_intr(void); +static void set_falling_edge(void); + +#define START_BIT 0x0001 +#define PARITY_BIT 0x0200 +#define STOP_BIT 0x0400 + +SIGNAL(MF2_CLIENT_INTERRUPT) +{ + s16 c; + + + switch(state) { + case MF2_CLIENT_STATE_IDLE: + rx_buf=0; + state=MF2_CLIENT_STATE_RECV; + current_bitnum=1; +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER + sched_event = scheduler_add_single_event(watchdog_timeout, + NULL, WATCHDOG_TIMEOUT/SCHEDULER_UNIT); +#endif + break; + + case MF2_CLIENT_STATE_RECV: + if(PIN(MF2_CLIENT_DATA_PORT) & (1<<MF2_CLIENT_DATA_BIT)) + rx_buf |= (1 << current_bitnum); + + if (current_bitnum==10) { + disable_intr(); + clk_0(); + if (rx_event) { + c=check_rx_buf(rx_buf); + if( c >= 0 ) { + rx_event((char)(c)); + } + } + current_bitnum=0; +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER + if (sched_event != -1) { + scheduler_del_event(sched_event); + sched_event = -1; + } +#endif + data_Z(); + clk_Z(); + set_falling_edge(); + state=MF2_CLIENT_STATE_IDLE; + } + else { + current_bitnum++; + } + break; + + case MF2_CLIENT_STATE_XMIT: + if (current_bitnum < 10) { + if (tx_buf & (1<<current_bitnum)) + data_Z(); + else + data_0(); + current_bitnum ++; + } + else { + data_Z(); + current_bitnum=0; + state=MF2_CLIENT_STATE_ACK; + } + break; + + case MF2_CLIENT_STATE_ACK: + /* if(PIN(MF2_CLIENT_DATA_PORT) & (1<<MF2_CLIENT_DATA_BIT)) */ + /* XXX error; */ + /* else */ + if (tx_event) { + tx_event((char)(tx_c)); + } + state=MF2_CLIENT_STATE_IDLE; +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER + if (sched_event != -1) { + scheduler_del_event(sched_event); + sched_event = -1; + } +#endif + break; + + default: + break; + } +} + +static void set_falling_edge(void) +{ + /* disable intr */ + cbi(MF2_CLIENT_IMASK, MF2_CLIENT_IMASK_BIT); + + /* intr on falling edge */ + cbi(MF2_CLIENT_INT_REG, MF2_CLIENT_INT_BIT0); + sbi(MF2_CLIENT_INT_REG, MF2_CLIENT_INT_BIT1); + + /* reset flag */ + sbi(MF2_CLIENT_IFLAG, MF2_CLIENT_IMASK_BIT); + + /* enable intr */ + sbi(MF2_CLIENT_IMASK, MF2_CLIENT_IMASK_BIT); + +} + +static void disable_intr(void) +{ + /* disable intr */ + cbi(MF2_CLIENT_IMASK, MF2_CLIENT_IMASK_BIT); +} + + +void mf2_client_init(void) +{ + u08 flags; + + IRQ_LOCK(flags); + /* ports are inputs, and values are 0 */ + data_Z(); + clk_Z(); + cbi(MF2_CLIENT_DATA_PORT, MF2_CLIENT_DATA_BIT); + cbi(MF2_CLIENT_CLK_PORT, MF2_CLIENT_CLK_BIT); + + set_falling_edge(); + + state = MF2_CLIENT_STATE_IDLE; + current_bitnum = 0; + IRQ_UNLOCK(flags); +} + +static s16 check_rx_buf(u16 buf) +{ + u16 mask, cpt=0; + + /* start bit should be 0 */ + if(buf & START_BIT) + return -1; + + /* stop bit should be 1 */ + if(! (buf & STOP_BIT)) + return -2; + + for (mask = START_BIT ; mask != STOP_BIT; mask<<=1 ) { + if (buf & mask) + cpt++; + } + + /* bad parity */ + if (!(cpt % 2)) + return -3; + + return (buf>>1) & 0xFF; +} + + +s08 mf2_client_ready(void) +{ + return state==MF2_CLIENT_STATE_IDLE; +} + +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER +static void watchdog_timeout(void * dummy) +{ + printf("TIMEOUT\n"); + current_bitnum=0; + state=MF2_CLIENT_STATE_IDLE; + data_Z(); + clk_Z(); + set_falling_edge(); +} +#endif + +static void start_sending(void * dummy) +{ + /* set clk to Z and data to 0 */ + clk_Z(); + data_0(); + set_falling_edge(); +#ifdef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER + sched_event = scheduler_add_single_event(watchdog_timeout, + NULL, WATCHDOG_TIMEOUT/SCHEDULER_UNIT); +#endif +} + +s08 mf2_client_send(char c) +{ + u16 mask, cpt=0; + u08 flags; + + IRQ_LOCK(flags); + + /* we don't preempt the remote device, even if the + protocol allow it */ + if (!mf2_client_ready()) { + IRQ_UNLOCK(flags); + return -1; + } + + state=MF2_CLIENT_STATE_XMIT; + current_bitnum = 1; + + disable_intr(); + + /* set clk to 0 */ + clk_0(); + + IRQ_UNLOCK(flags); + + tx_buf = c; + tx_c = c; + tx_buf <<= 1; + tx_buf |= STOP_BIT; + + for (mask = START_BIT ; mask != STOP_BIT; mask<<=1 ) { + if (tx_buf & mask) + cpt++; + } + + if (!(cpt % 2)) + tx_buf |= PARITY_BIT; + +#if CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER + scheduler_add_single_event(start_sending, NULL, 1000L/SCHEDULER_UNIT); +#else + wait_ms(1); + start_sending(NULL); +#endif + + return 0; +} + +/* This function is used to register another function which will be */ +/* executed at each byte transmission. */ +void mf2_client_register_tx_event(void (*f)(char)) +{ + u08 flags; + IRQ_LOCK(flags); + tx_event = f; + IRQ_UNLOCK(flags); +} + +/* This function is used to register another function which will be */ +/* executed at each byte reception. */ +void mf2_client_register_rx_event(void (*f)(char)) +{ + u08 flags; + IRQ_LOCK(flags); + rx_event = f; + IRQ_UNLOCK(flags); +} + diff --git a/modules/comm/mf2_client/mf2_client.h b/modules/comm/mf2_client/mf2_client.h new file mode 100644 index 0000000..38301d9 --- /dev/null +++ b/modules/comm/mf2_client/mf2_client.h @@ -0,0 +1,28 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_client.h,v 1.1.2.1 2006-11-30 21:59:07 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2006 */ + +void mf2_client_init(void); +s08 mf2_client_ready(void); +s08 mf2_client_send(char c); +void mf2_client_register_tx_event(void (*f)(char)); +void mf2_client_register_rx_event(void (*f)(char)); diff --git a/modules/comm/mf2_client/test/.config b/modules/comm/mf2_client/test/.config new file mode 100644 index 0000000..3c357c4 --- /dev/null +++ b/modules/comm/mf2_client/test/.config @@ -0,0 +1,230 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +# CONFIG_STRIP_UNUSED_FUNCTIONS is not set +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# To see all modules here, you must enable utils and wait modules, and math library +# +CONFIG_MODULE_UTILS=y +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_WAIT=y +CONFIG_MODULE_LIST=y +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# Some communications modules depend on utils and list modules +# + +# +# mf2 client need scheduler or wait +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_MF2_CLIENT=y +CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER=y +CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# + +# +# Hardware modules depend on utils module +# +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable utils and pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set + +# +# Encoders (you should enable utils and fixed_point modules to see all available encoders) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters (you should enable utils modules to see all available filters) +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/comm/mf2_client/test/CVS/Entries b/modules/comm/mf2_client/test/CVS/Entries new file mode 100644 index 0000000..63194e2 --- /dev/null +++ b/modules/comm/mf2_client/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +/Makefile/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +/main.c/1.1.2.2/Wed May 23 17:18:11 2007//Tb_zer0 +/mf2_client_config.h/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +/scheduler_config.h/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +/uart_config.h/1.1.2.1/Thu Nov 30 21:59:07 2006//Tb_zer0 +D diff --git a/modules/comm/mf2_client/test/CVS/Repository b/modules/comm/mf2_client/test/CVS/Repository new file mode 100644 index 0000000..d6e43a6 --- /dev/null +++ b/modules/comm/mf2_client/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/mf2_client/test diff --git a/modules/comm/mf2_client/test/CVS/Root b/modules/comm/mf2_client/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/mf2_client/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/mf2_client/test/CVS/Tag b/modules/comm/mf2_client/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/mf2_client/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/mf2_client/test/CVS/Template b/modules/comm/mf2_client/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/mf2_client/test/Makefile b/modules/comm/mf2_client/test/Makefile new file mode 100644 index 0000000..73ab23b --- /dev/null +++ b/modules/comm/mf2_client/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/comm/mf2_client/test/main.c b/modules/comm/mf2_client/test/main.c new file mode 100644 index 0000000..db8a954 --- /dev/null +++ b/modules/comm/mf2_client/test/main.c @@ -0,0 +1,70 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.2 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <uart.h> +#include <aversive.h> +#include <aversive/wait.h> +#include <scheduler.h> +#include <mf2_client.h> + +void mf2_print(char c) +{ + printf(">> %x\n", c); +} + +int main(void) +{ + scheduler_init(); + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + mf2_client_init(); + sei(); + + printf("Test MF2 protocol\n"); + + mf2_client_register_rx_event(mf2_print); + + while(1) { + + wait_ms(100); + while (!mf2_client_ready()); + mf2_client_send(0xED); + while (!mf2_client_ready()); + mf2_client_send(0x01); + + wait_ms(100); + while (!mf2_client_ready()); + mf2_client_send(0xED); + while (!mf2_client_ready()); + mf2_client_send(0x04); + + wait_ms(100); + while (!mf2_client_ready()); + mf2_client_send(0xED); + while (!mf2_client_ready()); + mf2_client_send(0x02); + } + while(1); + + return 0; +} diff --git a/modules/comm/mf2_client/test/mf2_client_config.h b/modules/comm/mf2_client/test/mf2_client_config.h new file mode 100644 index 0000000..3cba2c8 --- /dev/null +++ b/modules/comm/mf2_client/test/mf2_client_config.h @@ -0,0 +1,41 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_client_config.h,v 1.1.2.1 2006-11-30 21:59:07 zer0 Exp $ + * + */ + +#ifndef MF2_CLIENT_CONFIG_H +#define MF2_CLIENT_CONFIG_H + +#define MF2_CLIENT_DATA_PORT PORTB +#define MF2_CLIENT_DATA_BIT 0 + +/* MF2 clk should be an external interrupt pin */ +#define MF2_CLIENT_CLK_PORT PORTE +#define MF2_CLIENT_CLK_BIT 4 + +#define MF2_CLIENT_INTERRUPT SIG_INTERRUPT4 +#define MF2_CLIENT_INT_REG EICRB +#define MF2_CLIENT_INT_BIT0 ISC40 +#define MF2_CLIENT_INT_BIT1 ISC41 +#define MF2_CLIENT_IMASK EIMSK +#define MF2_CLIENT_IFLAG EIFR +#define MF2_CLIENT_IMASK_BIT 4 + +#endif + diff --git a/modules/comm/mf2_client/test/scheduler_config.h b/modules/comm/mf2_client/test/scheduler_config.h new file mode 100644 index 0000000..9d6d2cd --- /dev/null +++ b/modules/comm/mf2_client/test/scheduler_config.h @@ -0,0 +1,29 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1.2.1 2006-11-30 21:59:07 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + + +#define SCHEDULER_NB_MAX_EVENT 5 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/comm/mf2_client/test/uart_config.h b/modules/comm/mf2_client/test/uart_config.h new file mode 100644 index 0000000..773bd29 --- /dev/null +++ b/modules/comm/mf2_client/test/uart_config.h @@ -0,0 +1,114 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2006-11-30 21:59:07 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + + + + +/* + * UART1 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 0 +//#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 4 +#define UART1_TX_FIFO_SIZE 16 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + + + +#endif + diff --git a/modules/comm/mf2_server/CVS/Entries b/modules/comm/mf2_server/CVS/Entries new file mode 100644 index 0000000..b7388ce --- /dev/null +++ b/modules/comm/mf2_server/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Sat Mar 10 21:07:58 2007//Tb_zer0 +/mf2_server.c/1.1.2.5/Wed May 23 17:18:11 2007//Tb_zer0 +/mf2_server.h/1.1.2.2/Mon Mar 12 22:34:31 2007//Tb_zer0 +D diff --git a/modules/comm/mf2_server/CVS/Repository b/modules/comm/mf2_server/CVS/Repository new file mode 100644 index 0000000..0550be1 --- /dev/null +++ b/modules/comm/mf2_server/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/mf2_server diff --git a/modules/comm/mf2_server/CVS/Root b/modules/comm/mf2_server/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/mf2_server/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/mf2_server/CVS/Tag b/modules/comm/mf2_server/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/mf2_server/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/mf2_server/CVS/Template b/modules/comm/mf2_server/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/mf2_server/Makefile b/modules/comm/mf2_server/Makefile new file mode 100644 index 0000000..2429c4b --- /dev/null +++ b/modules/comm/mf2_server/Makefile @@ -0,0 +1,6 @@ +TARGET = mf2_server + +# List C source files here. (C dependencies are automatically generated.) +SRC = mf2_server.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/comm/mf2_server/mf2_server.c b/modules/comm/mf2_server/mf2_server.c new file mode 100644 index 0000000..cdc56a9 --- /dev/null +++ b/modules/comm/mf2_server/mf2_server.c @@ -0,0 +1,394 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_server.c,v 1.1.2.5 2007-05-23 17:18:11 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2007 */ + +#include <stdio.h> + +#include <aversive.h> +#include <aversive/wait.h> +#include <timer.h> +#include <mf2_server.h> +#include <mf2_server_config.h> + + +#define data_Z() do { cbi(DDR(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT); } while(0) +#define data_0() do { sbi(DDR(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT); } while(0) +#define read_data() (bit_is_set(PIN(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT)) +#define data_is_Z() (!bit_is_set(DDR(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT)) + +#define clk_Z() do { cbi(DDR(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT); } while(0) +#define clk_0() do { sbi(DDR(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT); } while(0) +#define read_clk() (bit_is_set(PIN(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT)) +#define clk_is_Z() (!bit_is_set(DDR(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT)) + +#define MF2_SERVER_STATE_READY 0 +#define MF2_SERVER_STATE_SEND 1 +#define MF2_SERVER_STATE_RECV 2 + +static volatile uint8_t mf2_state=0; + +typedef void (event)(char); +static event * tx_event = NULL; +static event * rx_event = NULL; +static volatile uint8_t mf2_step=0; +static volatile uint8_t mf2_parity_cpt=0; +static volatile char mf2_data_send=0; +static volatile char mf2_data_recv=0; + + +#define WAIT_KBD_CYCLE 600 +#define WAIT_KBD_CYCLE4 WAIT_KBD_CYCLE/4 + + +void recv(void) +{ + uint8_t i; + uint16_t c=0; + uint16_t d=0; + data_Z(); + clk_Z(); + if (read_data()) + printf("burp\r\n"); +/* wait_4cyc(WAIT_KBD_CYCLE4); */ +/* wait_4cyc(WAIT_KBD_CYCLE4); */ +/* wait_4cyc(WAIT_KBD_CYCLE4); */ + clk_0(); + wait_4cyc(WAIT_KBD_CYCLE4); + + + for (i=0; i<8 ; i++) { + if (read_data()) + c |= 1 << i; + clk_Z(); + wait_4cyc(WAIT_KBD_CYCLE4); + if (read_data()) + d |= 1 << i; + clk_0(); + wait_4cyc(WAIT_KBD_CYCLE4); + } + + // parite + clk_Z(); + wait_4cyc(WAIT_KBD_CYCLE4); + clk_0(); + wait_4cyc(WAIT_KBD_CYCLE4); + + // ack + clk_Z(); + data_0(); + wait_4cyc(WAIT_KBD_CYCLE4); + clk_0(); + wait_4cyc(WAIT_KBD_CYCLE4); + + // stop + clk_Z(); + data_Z(); + wait_4cyc(WAIT_KBD_CYCLE4); + clk_0(); + wait_4cyc(WAIT_KBD_CYCLE4); + clk_Z(); + + printf("%x\r\n", c); + printf("%x\r\n", d); + wait_4cyc(2*WAIT_KBD_CYCLE4); + while(1); +} + +static inline int8_t mf2_server_bus_free(void) +{ + return read_clk() && read_data(); +} + + +int8_t mf2_server_ready(void) +{ + return (mf2_state==MF2_SERVER_STATE_READY && mf2_server_bus_free()); +} + +/* a virer XXX */ +void disp(char c); + +#if 0 +static inline void dump(void) +{ + char c=0; + if(read_data()) + c|=1; + if(read_clk()) + c|=0x10; + + if(data_is_Z()) + c|=2; + if(clk_is_Z()) + c|=0x20; + + disp((char)(c)); +} +#else +#define dump() do {} while(0) +#endif + +void mf2_server_timer_cb(void) +{ +/* static uint16_t i=0; */ + static uint16_t t; + + /* if it is just polling */ + if (mf2_state == MF2_SERVER_STATE_READY) { + clk_Z(); + data_Z(); + + /* the central server has something to say */ + if (read_clk() && !read_data()) { + mf2_state = MF2_SERVER_STATE_RECV; + mf2_step = 1; + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_CLK_HALF_PERIOD); + // recv(); + dump(); + return; + } + /* nothing to do if the central server has nothing to say */ + else { + /* reload timer */ + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_READ_POLL_PERIOD); + return; + } + } + + /* an operation is running */ + + /* reload timer */ + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_CLK_HALF_PERIOD); + + /* XXX we should check if clk is 0 when clk_Z() */ + if (mf2_state == MF2_SERVER_STATE_RECV) { + switch(mf2_step) { + case 1: + mf2_data_recv=0; + dump(); + clk_0(); + break; + case 2: + dump(); + clk_Z(); + break; + + case 3: + case 5: + case 7: + case 9: + case 11: + case 13: + case 15: + case 17: + // t = timer1_get(); + dump(); + clk_0(); + if(read_data()) + mf2_data_recv |= (1 << ( (mf2_step-3)/2 ) ); + break; + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + case 18: +/* printf("%d\n", timer1_get() - t); */ +/* while(1); */ + dump(); + clk_Z(); + break; + + case 19: + /* parity */ + dump(); + clk_0(); + break; + case 20: + dump(); + clk_Z(); + data_0(); + break; + case 21: + dump(); + clk_0(); + break; + case 22: + dump(); + clk_Z(); + data_Z(); + break; + + default: + if (rx_event) { +/* c=check_rx_buf(rx_buf); */ + rx_event((char)(mf2_data_recv)); +/* rx_event((char)(0xED)); */ + } + mf2_state = MF2_SERVER_STATE_READY; + mf2_step = 0; + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_READ_POLL_PERIOD); + return; + } + mf2_step++; + } + else { + switch(mf2_step) { + case 1: + data_0(); + break; + case 2: + clk_0(); + break; + case 3: + case 5: + case 7: + case 9: + case 11: + case 13: + case 15: + case 17: + if(mf2_data_send & (1<<((mf2_step-3)/2))) { + data_Z(); + mf2_parity_cpt ++; + } + else { + data_0(); + } + clk_Z(); + break; + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + case 18: + /* XXX */ + if(!(read_clk())) { +/* /\* recv(); *\/ */ +/* printf("Ceci est un test\n"); */ +/* printf("%d\n", mf2_step); */ +/* printf("%2.2x\n", mf2_data_send); */ +/* while(1); */ + mf2_step=0; + mf2_state = MF2_SERVER_STATE_RECV; + + } + clk_0(); + break; + + case 19: + if(!(mf2_parity_cpt%2)) + data_Z(); + else + data_0(); + clk_Z(); + break; + case 20: + clk_0(); + break; + case 21: + clk_Z(); + data_Z(); + break; + case 22: + clk_0(); + break; + case 23: + clk_Z(); + break; + case 24: + case 25: + break; + default: + mf2_state = MF2_SERVER_STATE_READY; + mf2_step = 0; + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_READ_POLL_PERIOD); + return; + } + mf2_step++; + } +} + + + +int8_t mf2_server_send(char c) +{ + uint8_t flags; + + IRQ_LOCK(flags); + + if (!mf2_server_ready()) { + IRQ_UNLOCK(flags); + // recv(); + return -1; + } + + mf2_state = MF2_SERVER_STATE_SEND; + mf2_step = 1; + mf2_data_send = c; + mf2_parity_cpt = 0; + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, + timer1_get()+MF2_SERVER_CLK_HALF_PERIOD); + clk_Z(); + data_Z(); + IRQ_UNLOCK(flags); + return 0; +} + +void mf2_server_init(void) +{ + cbi(MF2_SERVER_DATA_PORT, MF2_SERVER_DATA_BIT); + cbi(MF2_SERVER_CLK_PORT, MF2_SERVER_CLK_BIT); + + timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, + timer1_get()+MF2_SERVER_READ_POLL_PERIOD); + + /* XXX choose timer */ + clk_Z(); + data_Z(); +} + +/* This function is used to register another function which will be */ +/* executed at each byte transmission. */ +void mf2_server_register_tx_event(void (*f)(char)) +{ + u08 flags; + IRQ_LOCK(flags); + tx_event = f; + IRQ_UNLOCK(flags); +} + +/* This function is used to register another function which will be */ +/* executed at each byte reception. */ +void mf2_server_register_rx_event(void (*f)(char)) +{ + u08 flags; + IRQ_LOCK(flags); + rx_event = f; + IRQ_UNLOCK(flags); +} + diff --git a/modules/comm/mf2_server/mf2_server.h b/modules/comm/mf2_server/mf2_server.h new file mode 100644 index 0000000..f3c648a --- /dev/null +++ b/modules/comm/mf2_server/mf2_server.h @@ -0,0 +1,28 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: mf2_server.h,v 1.1.2.2 2007-03-12 22:34:31 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2006 */ + +void mf2_server_init(void); +int8_t mf2_server_ready(void); +int8_t mf2_server_send(char c); +void mf2_server_register_tx_event(void (*f)(char)); +void mf2_server_register_rx_event(void (*f)(char)); diff --git a/modules/comm/spi/CVS/Entries b/modules/comm/spi/CVS/Entries new file mode 100644 index 0000000..cd03839 --- /dev/null +++ b/modules/comm/spi/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +/spi.c/1.1.2.3/Fri Feb 20 20:21:35 2009//Tb_zer0 +/spi.h/1.1.2.3/Fri Feb 20 20:21:35 2009//Tb_zer0 +D/config//// diff --git a/modules/comm/spi/CVS/Repository b/modules/comm/spi/CVS/Repository new file mode 100644 index 0000000..2297ff2 --- /dev/null +++ b/modules/comm/spi/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/spi diff --git a/modules/comm/spi/CVS/Root b/modules/comm/spi/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/spi/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/spi/CVS/Tag b/modules/comm/spi/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/spi/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/spi/CVS/Template b/modules/comm/spi/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/spi/Makefile b/modules/comm/spi/Makefile new file mode 100644 index 0000000..8f06ed2 --- /dev/null +++ b/modules/comm/spi/Makefile @@ -0,0 +1,9 @@ + +TARGET = spi + +# List C source files here. (C dependencies are automatically generated.) +SRC = spi.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/comm/spi/config/CVS/Entries b/modules/comm/spi/config/CVS/Entries new file mode 100644 index 0000000..6997b98 --- /dev/null +++ b/modules/comm/spi/config/CVS/Entries @@ -0,0 +1,2 @@ +/spi_config.h/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +D diff --git a/modules/comm/spi/config/CVS/Repository b/modules/comm/spi/config/CVS/Repository new file mode 100644 index 0000000..bbe324b --- /dev/null +++ b/modules/comm/spi/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/spi/config diff --git a/modules/comm/spi/config/CVS/Root b/modules/comm/spi/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/spi/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/spi/config/CVS/Tag b/modules/comm/spi/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/spi/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/spi/config/CVS/Template b/modules/comm/spi/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/spi/config/spi_config.h b/modules/comm/spi/config/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/modules/comm/spi/config/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/modules/comm/spi/spi.c b/modules/comm/spi/spi.c new file mode 100644 index 0000000..cdb7b12 --- /dev/null +++ b/modules/comm/spi/spi.c @@ -0,0 +1,223 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#include <aversive.h> +#include <aversive/parts.h> +#include <aversive/error.h> + +#include <stdlib.h> +#include <string.h> + +#include <spi.h> +#include <spi_config.h> + +/* internal structure to store SS pins */ +typedef struct _ss_pin { + volatile uint8_t *port; + uint8_t bitnum; +} ss_pin_t; + + +/* global vars */ +static volatile ss_pin_t g_ss_lines[SPI_MAX_SLAVES+1]; +static volatile uint8_t g_ss_number; +static volatile spi_mode_t g_spi_mode; +static volatile uint8_t g_slave_selected; + + + + +/* + * Register a pin as SS line + * Returns a unique identifier, or -1 on error + * There is always the physical SS line registered as 0 + */ +int8_t spi_register_ss_line(volatile uint8_t *port, uint8_t bitnum) +{ + DEBUG(E_SPI, "Trying to register new SS line: port 0x%x, bitnum %d", port, bitnum); + /* too much SS lines (try to change SPI_MAX_SLAVES) */ + if (g_ss_number >= SPI_MAX_SLAVES+1) + return -1; + + g_ss_lines[g_ss_number].port = port; + g_ss_lines[g_ss_number].bitnum = bitnum; + *(port-1) |= _BV(bitnum); // was DDR(port) |= _BV(bitnum); + /* Unselected at first */ + *port |= (_BV(bitnum)); + + NOTICE(E_SPI, "New Slave Line registered: %d", g_ss_number); + + return g_ss_number++; +} + + +/* + * Set data order (default: MSB first) + */ +inline void spi_set_data_order(uint8_t order) +{ + if (order == SPI_LSB_FIRST) + SPCR |= _BV(DORD); + else + SPCR &= ~(_BV(DORD)); +} + +/* + * Get data order + */ +inline uint8_t spi_get_data_order(void) +{ + if (SPCR & _BV(DORD)) + return SPI_LSB_FIRST; + return SPI_MSB_FIRST; +} + + +/* + * Initialize SPI + */ +void spi_init(spi_mode_t mode, spi_format_t format, spi_clk_rate_t clk_rate) +{ + NOTICE(E_SPI, "Init SPI: mode %d, format %d, clk_rate %d", + mode, format, clk_rate); + + /* Configure SPI pins */ + DDR(SCK_PORT) |= _BV(SCK_BIT); + DDR(MOSI_PORT) |= _BV(MOSI_BIT); + DDR(MISO_PORT) &= ~(_BV(MISO_BIT)); + /* SS pin is not driven by SPI hardware + * This is taken care of by spi_register_ss_line() + * EVEN for the "default" SS line */ + g_ss_number = 0; + g_slave_selected = FALSE; + + /* Registers init */ +#ifdef PRR0 + PRR0 &= ~(_BV(PRSPI)); /* Clear power reduction bit */ +#endif + SPCR = 0; + SPSR = 0; + + SPCR |= _BV(MSTR); /* XXX Master only for now ! */ + SPCR |= (uint8_t)format; /* Clock polarity and phase */ + + /* clockrate: SPR0, SPR1, SPI2X */ + if (clk_rate & 0x01) + SPR0_REG |= _BV(SPR0); + else + SPR0_REG &= ~(_BV(SPR0)); + if (clk_rate & 0x02) + SPR1_REG |= _BV(SPR1); + else + SPR1_REG &= ~(_BV(SPR1)); + if (clk_rate & 0x10) + SPI2X_REG |= _BV(SPI2X); + else + SPI2X_REG &= ~(_BV(SPI2X)); + + SPCR |= _BV(SPE); /* Enable SPI */ + + g_spi_mode = SPI_MODE_MASTER; + NOTICE(E_SPI, "Init done"); +} + +/* + * Returns the state of SPI + */ +inline spi_mode_t spi_get_mode(void) +{ + return g_spi_mode; +} + +/* + * Send a byte (and receive one) + * Returns the received byte + */ +uint8_t spi_send_and_receive_byte(uint8_t byte) +{ + //DEBUG(E_SPI, "Sending 0x%x", byte); + /* Start transmission */ + SPDR = byte; + + /* Wait for transmission complete + * Timings are VERY important, do not bypass this ! */ + while(!(SPSR & (1<<SPIF))) + ; + /* Return received byte */ + return SPDR; +} + +/* + * Send a byte, discard the result + */ +inline void spi_send_byte(uint8_t byte) +{ + spi_send_and_receive_byte(byte); +} + +/* + * Receives a byte (sends a NULL) + */ +uint8_t spi_receive_byte(void) +{ + return spi_send_and_receive_byte(0x00); +} + +/* + * Activates the selected SS line + */ +uint8_t spi_slave_select(uint8_t slave) +{ + if (g_slave_selected) { + ERROR(E_SPI, "A slave is already selected !"); + return EBUSY; + } + + *(g_ss_lines[slave].port) &= ~(_BV(g_ss_lines[slave].bitnum)); + g_slave_selected = TRUE; + return ESUCCESS; +} + +/* + * Desactivates the selected SS line + */ +void spi_slave_deselect(uint8_t slave) +{ + *(g_ss_lines[slave].port) |= (_BV(g_ss_lines[slave].bitnum)); + g_slave_selected = FALSE; +} + +/* + * Display SS lines + */ +void spi_display_ss_lines(void) +{ + uint8_t i; + for (i = 0; i < g_ss_number; i++) { + DEBUG(E_SPI, "SS%d: adr 0x%x bitnum %d value 0x%x", + i, + g_ss_lines[i].port, + g_ss_lines[i].bitnum, + *(g_ss_lines[i].port)); + } +} diff --git a/modules/comm/spi/spi.h b/modules/comm/spi/spi.h new file mode 100644 index 0000000..e370809 --- /dev/null +++ b/modules/comm/spi/spi.h @@ -0,0 +1,178 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +/* + * -- INFO -- + * This module enable the use of the SPI hardware + * on some AVRs. For now, only MASTER mode is available. + * You can have as many slaves as you want, as long as you + * don't confuse them by trying to speak to several at the same time. + * + * BIG WARNING: If you use /SS as a slave selector, always + * register it using spi_register_ss_line() *before* calling + * spi_init(). Read carrefully the datasheet, especially the + * paragraph "SS Pin Functionnality" in SPI section. In master + * mode, the SS pin must be configured as an output OR driven + * high by an external circuitry. + * + * -- USAGE -- + * So you have one (or several) device(s) that want to speak to your + * shiny AVR over SPI ? + * This is fairly easy. First, summon this module with spi_init(). + * You can configure + * - the FORMAT of the link (sample on rising or falling edge, ...) + * - the RATE of the connection (you set the prescaler dividing the CPU clock) + * You can also set the data order (MSB or LSB first on the link) + * + * After that you can register your devices using spi_register_ss_line(); + * This returns you a device identifier you can use with spi_slave_[de]select(); + * + * Remember to ALWAYS select your slave before talking to it, and deselect if + * once your are done. + */ + + + +#ifndef _SPI_H_ +#define _SPI_H_ + +#include <stdint.h> + +/* SPI modes */ +typedef enum { + SPI_MODE_UNINIT, /* not initialized */ + SPI_MODE_MASTER /* for now, only master mode as + * slave mode cannot be tested */ +} spi_mode_t; + + +/* SPI transfert format + * This defines the SCK phase and polarity. + * For instance in FORMAT_0, data lines are set on the falling edge + * of SCK, and sampled on its rising edge. This determines the order + * in which sampling and setting occurs. + * For more information on SPI formats, please see your CPU datasheet. + */ +typedef enum { + SPI_FORMAT_0 = 0x00, /* Sample rising Setup falling */ + SPI_FORMAT_1 = _BV(CPHA), /* Setup rising Sample falling */ + SPI_FORMAT_2 = _BV(CPOL), /* Sample falling Setup rising */ + SPI_FORMAT_3 = _BV(CPHA) | _BV(CPOL), /* Setup falling Sample rising*/ +} spi_format_t; + + +/* SPI Clock Rate + * This code the values for SPI2X (high nibble), SPR1 and SPR0 (low nibble) + * f_sck = f_osc / SPI_CLK_RATE_xx + */ +typedef enum { + SPI_CLK_RATE_2 = 0x10, + SPI_CLK_RATE_4 = 0x00, + SPI_CLK_RATE_8 = 0x11, + SPI_CLK_RATE_16 = 0x01, + SPI_CLK_RATE_32 = 0x12, + SPI_CLK_RATE_64 = 0x02, + SPI_CLK_RATE_128 = 0x03 +} spi_clk_rate_t; + + +/* + * Data order (bits order) + * order is either SPI_LSB_FIRST or SPI_MSB_FIRST + * Default is MSB first + */ +#define SPI_MSB_FIRST 0 +#define SPI_LSB_FIRST 1 +void spi_set_data_order(uint8_t order); + + + + +/* Initialize the SPI + * mode is SPI_MODE_MASTER (slave is not implemented) + * format defines the transfert format (see above) + * clk_rate defines the frequency of SCK line (f_sck = f_osc / clk_rate) + */ +void spi_init(spi_mode_t mode, spi_format_t format, spi_clk_rate_t clk_rate); + + +/* + * Returns the state of the SPI + */ +spi_mode_t spi_get_mode(void); + + +/* + * Register a pin as SS line + * Returns a unique identifier, or -1 on error + * There is always the physical SS line registered as 0 + */ +int8_t spi_register_ss_line(volatile uint8_t *port, uint8_t bitnum); + + +/* + * Sends a byte (and receive one at the same time) + * Returns the received byte + * Wait for the end of transmission + */ +uint8_t spi_send_and_receive_byte(uint8_t byte); + + +/* + * Sends a byte, discards the received one. + * Do NOT wait for the end of transmission + */ +void spi_send_byte(uint8_t byte); + +/* + * Receives a byte (sends a NULL) + */ +uint8_t spi_receive_byte(void); + +/* + * Select or Deselect the SS line + * The SPI standard defines that only ONE slave can + * be selected at any time. An internal mecanism prevents + * the selection of several slaves at the same time, but + * this is not completely foolproof. + * + * /!\ Behavior is NOT ASSURED if you mess with SS lines + * outside of this module, so PLEASE use these setters. /!\ + * + * This function returns EBUSY if there is already a selected slave + */ +uint8_t spi_slave_select(uint8_t slave); + +/* + * Inconditionnaly releases the line. + */ +void spi_slave_deselect(uint8_t slave); + +/* + * Display SS lines + */ +void spi_display_ss_lines(void); + + +#endif /* _SPI_H_ */ + diff --git a/modules/comm/uart/CVS/Entries b/modules/comm/uart/CVS/Entries new file mode 100644 index 0000000..cd4af1c --- /dev/null +++ b/modules/comm/uart/CVS/Entries @@ -0,0 +1,22 @@ +/Makefile/1.5.6.4/Sat Dec 27 16:50:01 2008//Tb_zer0 +/uart.c/1.33.4.7/Fri Jan 23 23:08:42 2009//Tb_zer0 +/uart.h/1.22.4.4/Sat Dec 27 16:29:07 2008//Tb_zer0 +/uart_defs.h/1.2.4.13/Mon Jun 29 20:28:27 2009//Tb_zer0 +/uart_dev_io.c/1.1.2.2/Tue Apr 7 20:00:47 2009//Tb_zer0 +/uart_errors.h/1.5.6.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/uart_events.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_getconf.c/1.1.2.3/Fri Feb 20 20:16:09 2009//Tb_zer0 +/uart_host.c/1.3.4.3/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_private.h/1.1.2.5/Sat Jan 3 16:24:50 2009//Tb_zer0 +/uart_recv.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_recv9.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_recv9_nowait.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_recv_nowait.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_send.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_send9.c/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_send9_nowait.c/1.1.2.2/Sat Dec 27 16:50:01 2008//Tb_zer0 +/uart_send_nowait.c/1.1.2.2/Sat Dec 27 16:50:01 2008//Tb_zer0 +/uart_setconf.c/1.1.2.3/Sat Jan 3 16:24:50 2009//Tb_zer0 +D/config//// +D/doc//// +D/test//// diff --git a/modules/comm/uart/CVS/Repository b/modules/comm/uart/CVS/Repository new file mode 100644 index 0000000..6616cb3 --- /dev/null +++ b/modules/comm/uart/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/uart diff --git a/modules/comm/uart/CVS/Root b/modules/comm/uart/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/uart/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/uart/CVS/Tag b/modules/comm/uart/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/uart/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/uart/CVS/Template b/modules/comm/uart/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/uart/Makefile b/modules/comm/uart/Makefile new file mode 100644 index 0000000..483f156 --- /dev/null +++ b/modules/comm/uart/Makefile @@ -0,0 +1,21 @@ +TARGET = uart + +# List C source files here. (C dependencies are automatically generated.) +ifeq ($(HOST),avr) +SRC = uart_setconf.c uart_dev_io.c +SRC += uart_getconf.c uart_events.c +SRC += uart.c + +SRC += uart_send.c uart_send_nowait.c +SRC += uart_recv.c uart_recv_nowait.c + +ifeq ($(CONFIG_MODULE_UART_9BITS),y) +SRC += uart_send9.c uart_send9_nowait.c +SRC += uart_recv9.c uart_recv9_nowait.c +endif + +else # is it ok ?? +SRC = uart_host.c +endif + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/comm/uart/config/CVS/Entries b/modules/comm/uart/config/CVS/Entries new file mode 100644 index 0000000..b49bfee --- /dev/null +++ b/modules/comm/uart/config/CVS/Entries @@ -0,0 +1,2 @@ +/uart_config.h/1.3.10.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +D diff --git a/modules/comm/uart/config/CVS/Repository b/modules/comm/uart/config/CVS/Repository new file mode 100644 index 0000000..6e7da3e --- /dev/null +++ b/modules/comm/uart/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/uart/config diff --git a/modules/comm/uart/config/CVS/Root b/modules/comm/uart/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/uart/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/uart/config/CVS/Tag b/modules/comm/uart/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/uart/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/uart/config/CVS/Template b/modules/comm/uart/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/uart/config/uart_config.h b/modules/comm/uart/config/uart_config.h new file mode 100644 index 0000000..67cb785 --- /dev/null +++ b/modules/comm/uart/config/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.3.10.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/comm/uart/doc/CVS/Entries b/modules/comm/uart/doc/CVS/Entries new file mode 100644 index 0000000..7d219dd --- /dev/null +++ b/modules/comm/uart/doc/CVS/Entries @@ -0,0 +1,3 @@ +/interface.txt/1.3.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/uart_v2.txt/1.2.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +D diff --git a/modules/comm/uart/doc/CVS/Repository b/modules/comm/uart/doc/CVS/Repository new file mode 100644 index 0000000..a91ef90 --- /dev/null +++ b/modules/comm/uart/doc/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/uart/doc diff --git a/modules/comm/uart/doc/CVS/Root b/modules/comm/uart/doc/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/uart/doc/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/uart/doc/CVS/Tag b/modules/comm/uart/doc/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/uart/doc/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/uart/doc/CVS/Template b/modules/comm/uart/doc/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/uart/doc/interface.txt b/modules/comm/uart/doc/interface.txt new file mode 100644 index 0000000..8a8d50d --- /dev/null +++ b/modules/comm/uart/doc/interface.txt @@ -0,0 +1,172 @@ +Configuration statique : + +UART_MCU_QUARTZ + +UARTx_TX_ENABLED +UARTx_RX_ENABLED + +UARTx_DONT_LOOSE_DATA + +UARTx_TX_FIFO_SIZE uint8_t +UARTx_RX_FIFO_SIZE uint8_t + + +UARTx_DEFAULT_BAUDRATE uint32_t + +UARTx_DEFAULT_9BITS/UARTx_DEFAULT_8BITS/UARTx_DEFAULT_7BITS/UARTx_DEFAULT_6BITS/UARTx_DEFAULT_5BITS + +UARTx_DEFAULT_NO_PARITY/UARTx_DEFAULT_PARITY_ODD/UARTx_DEFAULT_PARITY_EVEN + +UARTx_DEFAULT_1_STOP_BIT/UARTx_DEFAULT_2_STOP_BIT + + + +------------------------------------------------------ + +Configuration dynamique : + + + +Modification et lecture de la vitesse de transmission. Le set retourne +0 en cas de succès, ou un code d'erreur si la vitesse ne peut être +atteinte. + +uint8_t uart_set_baudrate(uint32_t) +uint32_t uart_get_baudrate() + + + +Modification de la parité. Elle est exécutée en hard sur les USART +mais elle devra être effectuée en soft sur les uart (9e +bit). set_parity retourne 0 en cas de succès. + +uint8_t uart_set_parity(NO_PARITY/PARITY_ODD/PARITY_EVEN) +uint8_t uart_get_parity() + + + +Modification du nombre de bits de stop. Executé en hard sur les USART, +il doit être effectué en soft sinon. Il est à savoir qu'il n'est pas +possible avec un uart d'avoir plus d'une de ces options :9bits, +2bits_stop, parité, car tout est géré avec le 9e bit. Il est par +contre envisageable d'avoir une combinaison : 7bits + parité + 2 bits +stop. En même temps, les AVR avec uart sont de plus en plus rare, il +n'est peut-etre pas nécessaire de s'embeter avec ça. + +uint8_t uart_set_1_stop_bit() +uint8_t uart_set_2_stop_bit() +uint8_t uart_get_stop_bit() + + +Ajoute une fonction appelée sur un évènement tx ou rx. Si on l'appelle +avec un pointeur nul, aucune fonction n'est appelée. data_size est un +uint8_t ou un uint16_t, selon la taille des données. + +uint8_t uart_register_tx_event(void (*f)(data_size)) +uint8_t uart_register_rx_event(void (*f)(data_size)) + +------------------------------------------------------------------ + +Initialisation : + +Voici un apperçu des caractéristiques de quelques AVR: + +at90s2313 et at90s8515 : +uart +8 bits +9bits ou parité ou stop supplémentaire +UCR (uart control register) et USR (status) + +pareil + +at90int16_t3 : +pareil, mais avec en plus double speed +et comm multiprocesseur +UCSRA et UCSRB + + +atm32 et atm8515 : +usart +URSEL pour acceder à UBRRH ou UCSRC +5 6 7 8 9 bits +parité et bits stop natifs +opérations synchrones + + +atm128 : +pareil, mais en double, et sans le URSEL + + + + +Résultat des courses, pour la fonction d'init, il faut séparer +intelligemment. + +D'abord, définissons des caractéristiques pour chaque processeur : + +AT90s2313: +UART_SIMPLE +UART_UCR_USR + + +ATmega163: +UART_SIMPLE +UART_UCSR (implique U2X ?) +UART_U2X + + +ATM32: +UART_USART (a priori, implique 56789 bits,parité et stop natifs + u2x) +UART_URSEL + + +ATM128: +UART_USART +UART_DOUBLE + + +Dans l'init, on a donc : + +init générique : ports, fifos + +#if defined(UART_SIMPLE) && defined(UART_UCR_USR) +uart_init_simple_ucr_usr() +#elif defined(UART_SIMPLE) && defined(UART_UCSR) +uart_init_simple_ucsr() +#elif !defined(UART_DOUBLE) +uart_init_usart() +#else +uart_init_double_usart() +#endif + + + + +puis dans chaque fonction d'init, on a : + +#if defined(UART_TX_ENABLED) && defined(UART_RX_ENABLED) + config interruptions + + config selon 5/6/7/8/9 bits + parité + stop + + U2X si nécessaire + + init baudrate + + + + +Concernant la parité, et les bits de stop : +- Il faudra implémenter des fonctions sur les uC ne disposant pas de +ces options en natif. Pour l'instant, il me semble que ce n'est pas +hyper important : d'une part c'est peu utilisé, d'autre part, il faut +pouvoir être averti (en réception) qu'il y a eu une erreur (que ce +soit une erreur de parité, overrun ou frame error d'ailleurs). Je +pense qu'il serait bien de fournir des fonctions du genre : + +uint8_t uart_udr_get() // lit le registre udr, bêtement <=> toto=UDR +uint8_t uart_udr_get_check_errors(&errors) // lit le registre udr, et + place un indicateur d'erreurs + dans error. + +Voilà, il ne reste plus qu'à coder, le gros du boulot est fait. diff --git a/modules/comm/uart/doc/uart_v2.txt b/modules/comm/uart/doc/uart_v2.txt new file mode 100644 index 0000000..f9d6b53 --- /dev/null +++ b/modules/comm/uart/doc/uart_v2.txt @@ -0,0 +1,91 @@ +function for configuring uart : + + +int8_t uartX_init( ) + equivalent to uartX_set(NULL) + + +int8_t uartX_get (struct uart_params * conf ) + return values : + 0 if ok + < 0 if error + +this func fills the value of the structure with current values. + + +int8_t uartX_set( struct uart_params conf ); + return values : + 0 if ok + < 0 if error + +apply the conf. If conf==NULL, apply the default conf (static) + + +int8_t uart_enable(struct uart_param) +int8_t uart_disable(struct uart_param) + +int8_t uart_tx_enable(struct uart_param) +int8_t uart_tx_disable(struct uart_param) + +int8_t uart_rx_enable(struct uart_param) +int8_t uart_rx_disable(struct uart_param) + +int8_t uart_dont_loose_data(struct uart_param) +int8_t uart_can_loose_data(struct uart_param) + +int8_t uart_use_double_speed(struct uart_param) +int8_t uart_use_simple_speed(struct uart_param) + +int8_t uart_parity_none(struct uart_param) +int8_t uart_parity_odd(struct uart_param) +int8_t uart_parity_even(struct uart_param) + +int8_t uart_stop_bits(struct uart_param, uint8_t nbits) + +int8_t uart_baudrate(struct uart_param, uint32_t baudrate) + + +struct uart_param { + unsigned char enabled : 1, + tx_enabled : 1, + rx_enabled : 1, + dont_loose_data : 1, + use_double_speed : 1, + partity : 2, + stop_bit : 1; + uint8_t nbits; + uint32_t baudrate; +} + + + +Configuration example : + +** change one parameter only : + +uart1_set_baudrate(uint32_t baudrate) +{ + struct uart_param u; + + if (uart1_get(&u) < 0) { + printf ("error"); + goto error; + } + + if (uart1_baudrate(u, baudrate) < 0) { + printf ("error"); + goto error; + } + + if (uart1_set(u) < 0) { + printf ("error"); + goto error; + } + + return 0; + +error: + return 1; +} + + diff --git a/modules/comm/uart/test/.config b/modules/comm/uart/test/.config new file mode 100644 index 0000000..f397aae --- /dev/null +++ b/modules/comm/uart/test/.config @@ -0,0 +1,251 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +CONFIG_MCU_ATMEGA168=y +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +CONFIG_OPTM_3=y +# CONFIG_OPTM_S is not set +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_GEOMETRY is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/modules/comm/uart/test/CVS/Entries b/modules/comm/uart/test/CVS/Entries new file mode 100644 index 0000000..87f74b0 --- /dev/null +++ b/modules/comm/uart/test/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.13.4.11/Mon Jun 29 20:28:27 2009//Tb_zer0 +/Makefile/1.10.10.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/main.c/1.15.10.5/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_config.h/1.10.10.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +D diff --git a/modules/comm/uart/test/CVS/Repository b/modules/comm/uart/test/CVS/Repository new file mode 100644 index 0000000..5accfd6 --- /dev/null +++ b/modules/comm/uart/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/comm/uart/test diff --git a/modules/comm/uart/test/CVS/Root b/modules/comm/uart/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/comm/uart/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/comm/uart/test/CVS/Tag b/modules/comm/uart/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/comm/uart/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/comm/uart/test/CVS/Template b/modules/comm/uart/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/comm/uart/test/Makefile b/modules/comm/uart/test/Makefile new file mode 100644 index 0000000..73ab23b --- /dev/null +++ b/modules/comm/uart/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/comm/uart/test/main.c b/modules/comm/uart/test/main.c new file mode 100644 index 0000000..b5ef729 --- /dev/null +++ b/modules/comm/uart/test/main.c @@ -0,0 +1,70 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.15.10.5 2008-12-27 16:29:08 zer0 Exp $ + * + */ +#include <uart.h> +#include <aversive/wait.h> + +#include <stdio.h> + +#include <avr/io.h> +#include <avr/pgmspace.h> + +/* + * This code sends a counter value to uart. + */ +int main(void) +{ + int i; + + /* initialize uart with the default parameters ( see + * uart_config.h ) */ + uart_init(); + + /* enable interrupts */ + sei(); + + /* send some single characters */ + for (i=0; i<10; i++) { + uart_send(0, 'x'); + uart_send(0, '0' + i); + wait_ms(100); + } + uart_send(0, '\n'); + + /* now we want to do a printf : we must register the + * uart0_send as stdout. Here no receive function is + * specified. */ + fdevopen(uart0_dev_send, NULL); + + /** ready to do a nice printf on the uart */ + printf("Uart is cool !!\n"); + + /* one drawback of the previous printf is that the format + * chain is srored in RAM and this can take a huge size if + * there are many printf. To avoid this problem, please use + * printf_P together with PSTR, like in the next example. */ + while (1) { + printf_P(PSTR("This format string takes no RAM " + "space. %i\n"), i++); + wait_ms(1000); + } + + return 0; +} diff --git a/modules/comm/uart/test/uart_config.h b/modules/comm/uart/test/uart_config.h new file mode 100644 index 0000000..842c93e --- /dev/null +++ b/modules/comm/uart/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.10.10.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/comm/uart/uart.c b/modules/comm/uart/uart.c new file mode 100644 index 0000000..25aa9e8 --- /dev/null +++ b/modules/comm/uart/uart.c @@ -0,0 +1,256 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart.c,v 1.33.4.7 2009-01-23 23:08:42 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <aversive.h> +#include <aversive/list.h> + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +struct cirbuf g_tx_fifo[UART_HW_NUM]; +struct cirbuf g_rx_fifo[UART_HW_NUM]; + +/* global vars are initialized to 0 (NULL) */ +event *rx_event[UART_HW_NUM]; +event *tx_event[UART_HW_NUM]; + +const struct regs uart_regs[UART_HW_NUM] = { +#ifdef UDR0 + { + .udr = &UDR0, + .ucsra = &UCSR0A, + .ucsrb = &UCSR0B, + .ucsrc = &UCSR0C, + .ubrrl = &UBRR0L, + .ubrrh = &UBRR0H, + }, +#endif +#ifdef UDR1 + { + .udr = &UDR1, + .ucsra = &UCSR1A, + .ucsrb = &UCSR1B, + .ucsrc = &UCSR1C, + .ubrrl = &UBRR1L, + .ubrrh = &UBRR1H, + }, +#endif +#ifdef UDR2 + { + .udr = &UDR2, + .ucsra = &UCSR2A, + .ucsrb = &UCSR2B, + .ucsrc = &UCSR2C, + .ubrrl = &UBRR2L, + .ubrrh = &UBRR2H, + }, +#endif +#ifdef UDR3 + { + .udr = &UDR3, + .ucsra = &UCSR3A, + .ucsrb = &UCSR3B, + .ucsrc = &UCSR3C, + .ubrrl = &UBRR3L, + .ubrrh = &UBRR3H, + }, +#endif +}; + +/** + * This is the interruption function which occurs when the entire + * frame in the transmit shift register has been shifted out and + * there is no new data in the transmit buffer. + */ +#ifdef UART0_COMPILE +#ifndef SIG_UART0_DATA +#define SIG_UART0_DATA SIG_USART0_DATA +#endif +SIGNAL(SIG_UART0_DATA) +{ + uart_send_next_char(0); +} +#endif +#ifdef UART1_COMPILE +#ifndef SIG_UART1_DATA +#define SIG_UART1_DATA SIG_USART1_DATA +#endif +SIGNAL(SIG_UART1_DATA) +{ + uart_send_next_char(1); +} +#endif +#ifdef UART2_COMPILE +#ifndef SIG_UART2_DATA +#define SIG_UART2_DATA SIG_USART2_DATA +#endif +SIGNAL(SIG_UART2_DATA) +{ + uart_send_next_char(2); +} +#endif +#ifdef UART3_COMPILE +#ifndef SIG_UART3_DATA +#define SIG_UART3_DATA SIG_USART3_DATA +#endif +SIGNAL(SIG_UART3_DATA) +{ + uart_send_next_char(3); +} +#endif + +static void uart_recv_next_char(uint8_t num); + +/** + * This is the interruption function which occurs when there is + * a new unread data in the reception buffer. + */ +#ifdef UART0_COMPILE +#ifndef SIG_UART0_RECV +#define SIG_UART0_RECV SIG_USART0_RECV +#endif +SIGNAL(SIG_UART0_RECV) +{ + uart_recv_next_char(0); +} +#endif +#ifdef UART1_COMPILE +#ifndef SIG_UART1_RECV +#define SIG_UART1_RECV SIG_USART1_RECV +#endif +SIGNAL(SIG_UART1_RECV) +{ + uart_recv_next_char(1); +} +#endif +#ifdef UART2_COMPILE +#ifndef SIG_UART2_RECV +#define SIG_UART2_RECV SIG_USART2_RECV +#endif +SIGNAL(SIG_UART2_RECV) +{ + uart_recv_next_char(2); +} +#endif +#ifdef UART3_COMPILE +#ifndef SIG_UART3_RECV +#define SIG_UART3_RECV SIG_USART3_RECV +#endif +SIGNAL(SIG_UART3_RECV) +{ + uart_recv_next_char(3); +} +#endif + + +/** + * transmit next character of fifo if any, and call the event function. + * This function is executed with intr locked. + */ +void uart_send_next_char(uint8_t num) +{ +#ifdef CONFIG_MODULE_UART_9BITS + if (uart_getconf_nbits(num) == 9) { + int elt = 0; + + /* for 9 bits, it uses 2 places in the fifo */ + if (CIRBUF_GET_LEN(&g_tx_fifo[num]) < 2) { + cbi(*uart_regs[num].ucsrb, UDRIE); + return; + } + + cirbuf_get_buf_tail(&g_tx_fifo[num], (char *)&elt, 2); + cirbuf_del_buf_tail(&g_tx_fifo[num], 2); + + uart_set_udr_9bits(num, elt); + sbi(*uart_regs[num].ucsrb, UDRIE); + } + else /* 5, 6, 7 or 8 bits */ +#endif /* CONFIG_MODULE_UART_9BITS */ + { + char elt = 0; + + if (CIRBUF_IS_EMPTY(&g_tx_fifo[num])) { + cbi(*uart_regs[num].ucsrb, UDRIE); + return; + } + + elt = cirbuf_get_tail(&g_tx_fifo[num]); + cirbuf_del_tail(&g_tx_fifo[num]); + uart_set_udr(num, elt); + sbi(*uart_regs[num].ucsrb, UDRIE); + } +} + +/** + * UART RX Interrupt + */ +static void uart_recv_next_char(uint8_t num) +{ +#ifdef CONFIG_MODULE_UART_9BITS + if (uart_getconf_nbits() == 9) { + int elt = 0; + + elt = uart_get_udr_9bits(num); + if (CIRBUF_GET_FREELEN(&g_rx_fifo[num]) >= 2) { + cirbuf_add_buf_head(&g_rx_fifo[num], (char *)&elt, 2); + } + + if (rx_event[num]) + ((event_9bits *)rx_event[num])(elt); + } + else +#endif /* CONFIG_MODULE_UART_9BITS */ + { + char elt = 0; + + elt = uart_get_udr(num); + if (!CIRBUF_IS_FULL(&g_rx_fifo[num])) { + cirbuf_add_head(&g_rx_fifo[num], elt); + } + + if (rx_event[num]) + rx_event[num](elt); + } +} + +/* init all uarts */ +void uart_init(void) +{ +#if (defined UDR0) && (defined UART0_COMPILE) + uart_setconf(0, NULL); +#endif + +#if (defined UDR1) && (defined UART1_COMPILE) + uart_setconf(1, NULL); +#endif + +#if (defined UDR2) && (defined UART2_COMPILE) + uart_setconf(2, NULL); +#endif + +#if (defined UDR3) && (defined UART3_COMPILE) + uart_setconf(3, NULL); +#endif +} diff --git a/modules/comm/uart/uart.h b/modules/comm/uart/uart.h new file mode 100644 index 0000000..6e4bd51 --- /dev/null +++ b/modules/comm/uart/uart.h @@ -0,0 +1,188 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart.h,v 1.22.4.4 2008-12-27 16:29:07 zer0 Exp $ + * + */ + +/* Olivier MATZ, 2004 - 2006 + * Interface of the uart module + */ + +/** \file uart.h + * \brief Interface of the UART module. + * + * This module provides : + * - Tx and Rx with fifo + * - Speed selection + * - Parity selection (if the uC support it) + * - 5 to 8 data bits (if the uC support it). + * - 1 or 2 stop bits (if the uC support it). + * - up to 4 UARTs (if the uC support it). + * + * Number of bits in frame, parity, stop bits are the same for tx and + * rx. TX fifo is useless if interrupts are disabled because the uart + * wait that all bytes are transmitted before returning. + * + * It doesn't support some USART capabilities : + * - Synchronous mode + * - Multiprocessor communication + */ + +#ifndef _UART_H_ +#define _UART_H_ + +#include <stdio.h> +#include <aversive.h> +#include <uart_config.h> + +#include <cirbuf.h> + +/** this structure stores the configuration of the uart */ +struct uart_config { + uint8_t enabled : 1, /**< enable or disable the uart */ + intr_enabled : 1, /**< use interruptions or not */ + use_double_speed : 1, /**< less acurate, but can reach faster baudrate */ + parity : 2, /**< none, odd or even */ + stop_bits : 1, /**< 1 or 2 bits at the end of the frame */ + reserved : 1; /**< nothing for now */ + uint8_t nbits; /**< number of bits in frame, 5,6,7,8 or 9 */ + uint32_t baudrate; /**< speed of uart */ +}; + + +/** + * Initialisation function. This function puts the registers of the + * microcontroler in a correct state in order to use the uart. It + * uses the configuration file <uart_config.h> ; this function is + * equivalent to call uartX_setconf(NULL) for each uart. + */ +void uart_init(void); + +/** + * Configure the uart 'num' with the given configuration. Returns 0 on + * success. + */ +int8_t uart_setconf(uint8_t num, struct uart_config *u); + +/** Get the current configuration of the uart 'num' */ +void uart_getconf(uint8_t num, struct uart_config *u); + +/** + * uart_recv returns the next character, taken from the fifo (if + * any). If there is nothing to read, the function waits until + * something come on the uart. + */ +int uart_recv(uint8_t num); + +/** + * uart_recv returns the next character, taken from the fifo (if + * any). If there is nothing to read, the function returns -1. + */ +int uart_recv_nowait(uint8_t num); + +/** + * same than uart_recv with 9 bits. + */ +int uart_9bits_recv(uint8_t num); + +/** + * same than uart_recv_nowait() with 9 bits. + */ +int uart_9bits_recv_nowait(uint8_t num); + +/** + * uart_send_nowait is used to send data to the uart 'num'. The data + * is first stored in the FIFO before beeing sent. If the FIFO is + * full, data is dropped and the function returns -1, else it returns + * the character c. + */ +int uart_send_nowait(uint8_t num, char c); + +/** + * uart_send is used to send data to the uart 'num'. The data is first + * stored in the FIFO before beeing sent. If the FIFO is full, the + * function wait until the uart is ready. The function returns c. + */ +int uart_send(uint8_t num, char c); + +/** + * uart_send_9bits is the same that uart_send but arg is 16 bits so + * data can be 9 bits wide. + */ +int uart_send_9bits_nowait(uint8_t num, int c); + +/* uart_send_9bits_wait is the same that uart_send_wait but arg is + * 16 bits so data can be 9 bits wide. + */ +int uart_send_9bits(uint8_t num, int c); + + + +/** + * This function is used to register another function which will be + * executed at each byte transmission (5, 6 ,7 ,8 bits) + */ +void uart_register_tx_event(uint8_t num, void (*f)(char)); + +/** + * This function is used to register another function which will be + * executed at each byte reception (5, 6 ,7 ,8 bits) + */ +void uart_register_rx_event(uint8_t num, void (*f)(char)); + + +/** + * This function is used to register another function which will be + * executed at each 9 bits frame transmission. WARNING : it uses the + * same internal pointer that the 8 bits event, so be carreful to + * unregister 8 bits events when doing 9 bits and vice versa. + */ +void uart_register_tx_9bits_event(uint8_t num, void (*f)(int)); + +/** + * This function is used to register another function which will be + * executed at each 9 bits reception. WARNING : it uses the + * same internal pointer that the 8 bits event, so be carreful to + * unregister 8 bits events when doing 9 bits and vice versa. + */ +void uart_register_rx_9bits_event(uint8_t num, void (*f)(int)); + +/* funcs for use with fdevopen (avrlibc > 1.4.0) */ +int uart0_dev_send_nowait(char c, FILE* f); +int uart0_dev_send(char c, FILE* f); +int uart0_dev_recv_nowait(FILE* f); +int uart0_dev_recv(FILE* f); + +int uart1_dev_send_nowait(char c, FILE* f); +int uart1_dev_send(char c, FILE* f); +int uart1_dev_recv_nowait(FILE* f); +int uart1_dev_recv(FILE* f); + +int uart2_dev_send_nowait(char c, FILE* f); +int uart2_dev_send(char c, FILE* f); +int uart2_dev_recv_nowait(FILE* f); +int uart2_dev_recv(FILE* f); + +int uart3_dev_send_nowait(char c, FILE* f); +int uart3_dev_send(char c, FILE* f); +int uart3_dev_recv_nowait(FILE* f); +int uart3_dev_recv(FILE* f); + + +#endif /* _UART_H_ */ + diff --git a/modules/comm/uart/uart_defs.h b/modules/comm/uart/uart_defs.h new file mode 100644 index 0000000..e37de8c --- /dev/null +++ b/modules/comm/uart/uart_defs.h @@ -0,0 +1,178 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_defs.h,v 1.2.4.13 2009-06-29 20:28:27 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2006 + * Uart specific definitions + */ + +#ifndef _UART_DEFS_H_ +#define _UART_DEFS_H_ + +#define UART_PARTITY_NONE 0 +#define UART_PARTITY_ODD 1 +#define UART_PARTITY_EVEN 2 + +#define UART_STOP_BITS_1 0 +#define UART_STOP_BITS_2 1 + +#if (defined UDR3) +#define UART_HW_NUM 4 +#elif (defined UDR2) +#define UART_HW_NUM 3 +#elif (defined UDR1) +#define UART_HW_NUM 2 +#else /* assume 1 uart */ +#define UART_HW_NUM 1 +#endif + + +/* For arch with only one UART, we consider that UART0 = UART */ +#if !defined(SIG_UART0_DATA) && !defined(SIG_USART0_DATA) +#if defined SIG_UART_DATA +#define SIG_UART0_DATA SIG_UART_DATA +#elif defined SIG_USART_DATA +#define SIG_UART0_DATA SIG_USART_DATA +#endif +#endif + +#if !defined(SIG_UART0_RECV) && !defined(SIG_USART0_RECV) +#if defined SIG_UART_RECV +#define SIG_UART0_RECV SIG_UART_RECV +#elif defined SIG_USART_RECV +#define SIG_UART0_RECV SIG_USART_RECV +#endif +#endif + +#ifndef UDR0 +#define UDR0 UDR +#endif +#ifndef UCSR0A +#define UCSR0A UCSRA +#endif +#ifndef UCSR0B +#define UCSR0B UCSRB +#endif +#ifndef UCSR0C +#define UCSR0C UCSRC +#endif +#ifndef UBRR0L +#define UBRR0L UBRRL +#endif +#ifndef UBRR0H +#define UBRR0H UBRRH +#endif +#ifndef U2X +#define U2X U2X0 +#endif +#ifndef UCSZ0 +#define UCSZ0 UCSZ00 +#endif +#ifndef UCSZ1 +#define UCSZ1 UCSZ01 +#endif +#ifndef UCSZ2 +#define UCSZ2 UCSZ02 +#endif +#ifndef UPM0 +#define UPM0 UPM00 +#endif +#ifndef UPM1 +#define UPM1 UPM01 +#endif +#ifndef USBS +#define USBS USBS0 +#endif +#ifndef TXEN +#define TXEN TXEN0 +#endif +#ifndef TXCIE +#define TXCIE TXCIE0 +#endif +#ifndef RXEN +#define RXEN RXEN0 +#endif +#ifndef RXCIE +#define RXCIE RXCIE0 +#endif +#ifndef TXC +#define TXC TXC0 +#endif +#ifndef RXB8 +#define RXB8 RXB80 +#endif +#ifndef UDRIE +#define UDRIE UDRIE0 +#endif +#ifndef UDRE +#define UDRE UDRE0 +#endif + +/* makes functions more generic, we associate USR and UCR with UCSRA + * and UCSRB, respectively */ +#if ( ! defined UCSRA ) && ( defined USR ) +#define UCSRA USR +#endif + +#if ( ! defined UCSRB ) && ( defined UCR ) +#define UCSRB UCR +#endif + +/* UBRR is UBRRL */ +#ifndef UBRRL +#define UBRRL UBRR +#endif + + +/* workaround for libc incomplete headers when using CAN AVR + * (avr/iocanxx.h): USART is valid. + * see http://savannah.nongnu.org/bugs/?18964 + */ +#if defined (__AVR_AT90CAN128__) || defined (__AVR_AT90CAN64__) || defined (__AVR_AT90CAN32__) + +#ifndef SIG_USART0_RECV +#define SIG_USART0_RECV SIG_UART0_RECV +#define SIG_USART1_RECV SIG_UART1_RECV +#define SIG_USART0_DATA SIG_UART0_DATA +#define SIG_USART1_DATA SIG_UART1_DATA +#define SIG_USART0_TRANS SIG_UART0_TRANS +#define SIG_USART1_TRANS SIG_UART1_TRANS +#endif + +#endif + + +/* if the signal USART is defined, the uC has a USART. */ +#if ( defined SIG_USART0_RECV ) || ( defined SIG_USART_RECV ) +#define UART_IS_USART 1 +#elif (defined USART_UDRE_vect) || (defined USART_TXC_vect) || (defined USART_RXC_vect) +#define UART_IS_USART 1 +#else +#define UART_IS_USART 0 +#endif + +/* if the U2X macro is defined, the uC has the U2X option. */ +#ifdef U2X +#define UART_HAS_U2X 1 +#else +#define UART_HAS_U2X 0 +#endif + +#endif //_UART_DEFS_H_ diff --git a/modules/comm/uart/uart_dev_io.c b/modules/comm/uart/uart_dev_io.c new file mode 100644 index 0000000..8ffb89e --- /dev/null +++ b/modules/comm/uart/uart_dev_io.c @@ -0,0 +1,114 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_dev_io.c,v 1.1.2.2 2009-04-07 20:00:47 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +#ifdef UART0_COMPILE +int uart0_dev_send_nowait(char c, __attribute__((unused)) FILE *f) +{ + return uart_send_nowait(0, c); +} + +int uart0_dev_send(char c, __attribute__((unused)) FILE *f) +{ + return uart_send(0, c); +} + +int uart0_dev_recv_nowait(__attribute__((unused)) FILE *f) +{ + return uart_recv_nowait(0); +} + +int uart0_dev_recv(__attribute__((unused)) FILE *f) +{ + return uart_recv(0); +} +#endif + +#ifdef UART1_COMPILE +int uart1_dev_send_nowait(char c, __attribute__((unused)) FILE *f) +{ + return uart_send_nowait(1, c); +} + +int uart1_dev_send(char c, __attribute__((unused)) FILE *f) +{ + return uart_send(1, c); +} + +int uart1_dev_recv_nowait(__attribute__((unused)) FILE *f) +{ + return uart_recv_nowait(1); +} + +int uart1_dev_recv(__attribute__((unused)) FILE *f) +{ + return uart_recv(1); +} +#endif + +#ifdef UART2_COMPILE +int uart2_dev_send_nowait(char c, __attribute__((unused)) FILE *f) +{ + return uart_send_nowait(2, c); +} + +int uart2_dev_send(char c, __attribute__((unused)) FILE *f) +{ + return uart_send(2, c); +} + +int uart2_dev_recv_nowait(__attribute__((unused)) FILE *f) +{ + return uart_recv_nowait(2); +} + +int uart2_dev_recv(__attribute__((unused)) FILE *f) +{ + return uart_recv(2); +} +#endif + +#ifdef UART3_COMPILE +int uart3_dev_send_nowait(char c, __attribute__((unused)) FILE *f) +{ + return uart_send_nowait(3, c); +} + +int uart3_dev_send(char c, __attribute__((unused)) FILE *f) +{ + return uart_send(3, c); +} + +int uart3_dev_recv_nowait(__attribute__((unused)) FILE *f) +{ + return uart_recv_nowait(3); +} + +int uart3_dev_recv(__attribute__((unused)) FILE *f) +{ + return uart_recv(3); +} +#endif diff --git a/modules/comm/uart/uart_errors.h b/modules/comm/uart/uart_errors.h new file mode 100644 index 0000000..32ee436 --- /dev/null +++ b/modules/comm/uart/uart_errors.h @@ -0,0 +1,67 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_errors.h,v 1.5.6.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * Errors of the uart module + */ + +/** \file uart.c + * \brief Errors of the UART module. + * + * \todo None + * + * \test None + */ + + +/* check if uart configuration is correct at compilation time */ +#ifndef UART_IS_USART +#if (UART0_PARITY == UART_PARTITY_ODD) || (UART0_PARITY == UART_PARTITY_EVEN) +#error Currently this module does not support parity if your uC has no USART +#endif + +#if (UART0_STOP_BIT == 2) +#error Currently this module does not support another stop bit if your uC has no USART +#endif + +#if (UART0_NBITS < 8) +#error Currently this module does not support 5/6/7 bits frames if your uC has no USART +#endif +#endif // !UART_USART + + +/* check if uart configuration is correct */ +#if !defined(UART_USART) && defined(UART_DOUBLE) // is this possible ?? +#if (UART1_PARITY == UART_PARTITY_ODD) || (UART1_PARITY == UART_PARTITY_EVEN) +#error Currently this module does not support parity if your uC has no USART +#endif + +#if (UART1_STOP_BIT == 2) +#error Currently this module does not support another stop bit if your uC has no USART +#endif + +#if (UART1_NBITS < 8) +#error Currently this module does not support 5/6/7 bits frames if your uC has no USART +#endif +#endif // !UART_USART && UART_DOUBLE + + + diff --git a/modules/comm/uart/uart_events.c b/modules/comm/uart/uart_events.c new file mode 100644 index 0000000..42b2c2a --- /dev/null +++ b/modules/comm/uart/uart_events.c @@ -0,0 +1,51 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_events.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +/* This function is used to register another function which will be */ +/* executed at each byte transmission. */ +void uart_register_tx_event(uint8_t num, void (*f)(char)) +{ + uint8_t flags; + if (num >= UART_HW_NUM) + return; + IRQ_LOCK(flags); + tx_event[num] = f; + IRQ_UNLOCK(flags); +} + +/* This function is used to register another function which will be */ +/* executed at each byte reception */ +void uart_register_rx_event(uint8_t num, void (*f)(char)) +{ + uint8_t flags; + if (num >= UART_HW_NUM) + return; + IRQ_LOCK(flags); + rx_event[num] = f; + IRQ_UNLOCK(flags); +} + diff --git a/modules/comm/uart/uart_getconf.c b/modules/comm/uart/uart_getconf.c new file mode 100644 index 0000000..dafa500 --- /dev/null +++ b/modules/comm/uart/uart_getconf.c @@ -0,0 +1,177 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_getconf.c,v 1.1.2.3 2009-02-20 20:16:09 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2007 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +#if UART_IS_USART + +static inline uint8_t get_ucsrc(uint8_t num) +{ +#ifdef URSEL + uint8_t tmp; + /* on some uC, reading UCSRxC is a bit tricky */ + switch(num) { +#ifdef UART0_COMPILE + case 0: + tmp = UBRR0H; + tmp = UCSR0C; + break; +#endif +#ifdef UART1_COMPILE + case 1: + tmp = UBRR1H; + tmp = UCSR1C; + break; +#endif +#ifdef UART2_COMPILE + case 2: + tmp = UBRR2H; + tmp = UCSR2C; + break; +#endif +#ifdef UART3_COMPILE + case 3: + tmp = UBRR3H; + tmp = UCSR3C; + break; +#endif + default: + tmp = 0; + break; + } + return tmp; +#else + return *uart_regs[num].ucsrc; +#endif /* URSEL */ +} + +/* return number of bits in current conf. Intr must be disabled. */ +uint8_t uart_getconf_nbits(uint8_t num) +{ + uint8_t nbits; + + nbits = (get_ucsrc(num) >> UCSZ0) & 0x03; +#ifdef CONFIG_MODULE_UART_9BITS + if (*uart_regs[num].ucsrb & (1 << UCSZ2)) + nbits += 4; +#endif + nbits += 5; + return nbits; +} + +#else /* UART_IS_USART */ + +/* return number of bits in current conf */ +uint8_t uart_getconf_nbits(uint8_t num) +{ +#ifdef CONFIG_MODULE_UART_9BITS + if (*uart_regs[num].ucsrb & (uint8_t)(1 << CHR9)) + return 8; + else + return 9; +#else + return 8; +#endif +} + +#endif /* UART_IS_USART */ + + +#if UART_IS_USART + +/* return number of bits in current conf */ +static inline uint16_t uart_get_baudreg(uint8_t num) +{ + return ((uint16_t)*uart_regs[num].ubrrh << 8) | + (uint16_t)*uart_regs[num].ubrrl; +} + +#else /* UART_IS_USART */ + +/* return number of bits in current conf */ +static inline uint16_t uart_get_baudreg(uint8_t num) +{ + return (uint16_t)*uart_regs[num].ubrrl; +} + +#endif /* UART_IS_USART */ + + +/* get the running uart configurtion */ +void uart_getconf(uint8_t num, struct uart_config *u) +{ + uint8_t tmp; + uint8_t flags; + + IRQ_LOCK(flags); + + /* XXX */ + /* enabled if RXEN is set */ + if (*uart_regs[num].ucsrb & (1 << RXEN)) + u->enabled = 1; + else + u->enabled = 0; + + /* intrp enabled if RXCIE is set */ + if (*uart_regs[num].ucsrb & (1 << RXCIE)) + u->intr_enabled = 1; + else + u->intr_enabled = 0; + + /* use double speed */ + if (UART_HAS_U2X && (*uart_regs[num].ucsra & (1 << U2X))) + u->use_double_speed = 1; + else + u->use_double_speed = 0; + + + /* parity */ + if (UART_IS_USART) { + tmp = get_ucsrc(num) & ((1 << UPM1) | (1 << UPM0)); + if (tmp == ((1 << UPM1) | (1 << UPM0))) + u->parity = UART_PARTITY_ODD; + else if (tmp == (1 << UPM1)) + u->parity = UART_PARTITY_EVEN; + else + u->parity = UART_PARTITY_NONE; + } + else { + u->parity = UART_PARTITY_NONE; + } + + /* stop_bits */ + if (UART_IS_USART && (get_ucsrc(num) & (1 << USBS))) { + u->stop_bits = UART_STOP_BITS_2; + } + else { + u->stop_bits = UART_STOP_BITS_1; + } + + /* nbits */ + u->nbits = uart_getconf_nbits(num); + u->baudrate = (F_CPU / ((uart_get_baudreg(num)+1) * 16)) ; + + IRQ_UNLOCK(flags); +} diff --git a/modules/comm/uart/uart_host.c b/modules/comm/uart/uart_host.c new file mode 100644 index 0000000..8c58c44 --- /dev/null +++ b/modules/comm/uart/uart_host.c @@ -0,0 +1,70 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_host.c,v 1.3.4.3 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_private.h> + + +/* this file os a stub for host */ + +void uart_init(void) +{ +} + +/* global vars are initialized to 0 (NULL) */ +event *rx_event[UART_HW_NUM]; +event *tx_event[UART_HW_NUM]; + +int8_t uart_setconf(uint8_t num, struct uart_config *u) +{ + return 0; +} + +void uart_getconf(uint8_t num, struct uart_config *u) +{ +} + +int uart_recv(uint8_t num) +{ + return getchar(); +} + +int uart_send_nowait(uint8_t num, char c) +{ + return putchar(c); +} + +int uart_send(uint8_t num, char c) +{ + return put_char(c); +} + +void uart_register_tx_event(uint8_t num, void (*f)(char)) +{ + tx_event = f; +} + +void uart_register_rx_event(uint8_t num, void (*f)(char)) +{ + rx_event = f; +} diff --git a/modules/comm/uart/uart_private.h b/modules/comm/uart/uart_private.h new file mode 100644 index 0000000..f09e2a7 --- /dev/null +++ b/modules/comm/uart/uart_private.h @@ -0,0 +1,99 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_private.h,v 1.1.2.5 2009-01-03 16:24:50 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#ifndef _UART_PRIVATE_H_ +#define _UART_PRIVATE_H_ + +#include <aversive.h> +#include <aversive/list.h> + +#include <uart.h> +#include <uart_defs.h> +#include <uart_config.h> + +typedef volatile uint8_t *uart_reg_t; + +struct regs { + uart_reg_t udr; + uart_reg_t ucsra; + uart_reg_t ucsrb; + uart_reg_t ucsrc; + uart_reg_t ubrrl; + uart_reg_t ubrrh; +}; + +const struct regs uart_regs[UART_HW_NUM]; + +typedef void (event)(char); +typedef void (event_9bits)(int); + +/** The emission fifo of uart */ +extern struct cirbuf g_tx_fifo[UART_HW_NUM]; + +/** The reception fifo of uart */ +extern struct cirbuf g_rx_fifo[UART_HW_NUM]; + +extern event *rx_event[UART_HW_NUM]; +extern event *tx_event[UART_HW_NUM]; + +void uart_send_next_char(uint8_t num); +int8_t uart_setconf(uint8_t num, struct uart_config *u); + +static inline char uart_get_udr(uint8_t num) +{ + return *uart_regs[num].udr; +} + +static inline void uart_set_udr(uint8_t num, char c) +{ + *uart_regs[num].udr = c; + /* tx event function. We suppose interrupts are already + * locked, so no pb with tx_event pointer */ + if (tx_event[num]) + tx_event[num](c); +} + +#ifdef CONFIG_MODULE_UART_9BITS +static inline int uart_get_udr_9bits(uint8_t num) +{ + int val = *uart_regs[num].udr; + val |= (*uart_regs[num].ucsrb & ((1 << RXB8) ? 0x100 : 0)); + return val; +} + +static inline void uart_set_udr_9bits(uint8_t num, int c) +{ + if (c & 0x100 ) + *uart_regs[num].ucsrb |= (1 << RXB8); + else + *uart_regs[num].ucsrb &= ~(1 << RXB8); + *uart_regs[num].udr = c; + + /* tx event function. We suppose interrupts are already + * locked, so no pb with tx_event pointer */ + if (tx_event[num]) + ((event_9bits *)tx_event[num])(c); +} +#endif /* CONFIG_MODULE_UART_9BITS */ + +#endif /* _UART_PRIVATE_H_ */ diff --git a/modules/comm/uart/uart_recv.c b/modules/comm/uart/uart_recv.c new file mode 100644 index 0000000..8e1bd36 --- /dev/null +++ b/modules/comm/uart/uart_recv.c @@ -0,0 +1,34 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_recv.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +/* get a char from the receive fifo */ +int uart_recv(uint8_t num) +{ + int elt = 0; + while ( (elt = uart_recv_nowait(num)) == -1 ); + return elt; +} diff --git a/modules/comm/uart/uart_recv9.c b/modules/comm/uart/uart_recv9.c new file mode 100644 index 0000000..d0522d4 --- /dev/null +++ b/modules/comm/uart/uart_recv9.c @@ -0,0 +1,34 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_recv9.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +/* get a char from the receive fifo */ +int uart_9bits_recv(uint8_t num) +{ + int elt = 0; + while ( (elt = uart_9bits_recv_nowait(num)) == -1 ); + return elt; +} diff --git a/modules/comm/uart/uart_recv9_nowait.c b/modules/comm/uart/uart_recv9_nowait.c new file mode 100644 index 0000000..8c626a2 --- /dev/null +++ b/modules/comm/uart/uart_recv9_nowait.c @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_recv9_nowait.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +/* get a char from the receive fifo */ +int uart_9bits_recv_nowait(uint8_t num) +{ + char elt = 0; + uint8_t flags; + + IRQ_LOCK(flags); + if( CIRBUF_GET_LEN(&g_rx_fifo[num]) >= 2) { + cirbuf_get_buf_tail(&g_rx_fifo[num], (char *)&elt, 2); + cirbuf_del_buf_tail(&g_rx_fifo[num], 2); + IRQ_UNLOCK(flags); + return (int)elt; + } + IRQ_UNLOCK(flags); + return (-1); +} diff --git a/modules/comm/uart/uart_recv_nowait.c b/modules/comm/uart/uart_recv_nowait.c new file mode 100644 index 0000000..c4c1a04 --- /dev/null +++ b/modules/comm/uart/uart_recv_nowait.c @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_recv_nowait.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +/* get a char from the receive fifo */ +int uart_recv_nowait(uint8_t num) +{ + char elt = 0; + uint8_t flags; + + IRQ_LOCK(flags); + if( !CIRBUF_IS_EMPTY(&g_rx_fifo[num]) ) { + elt = cirbuf_get_tail(&g_rx_fifo[num]); + cirbuf_del_tail(&g_rx_fifo[num]); + IRQ_UNLOCK(flags); + return (int)elt; + } + IRQ_UNLOCK(flags); + return (-1); +} diff --git a/modules/comm/uart/uart_send.c b/modules/comm/uart/uart_send.c new file mode 100644 index 0000000..26bb2a3 --- /dev/null +++ b/modules/comm/uart/uart_send.c @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_send.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +int uart_send(uint8_t num, char c) +{ + /* if cannot send the char */ + if (uart_send_nowait(num, c) == -1) { + + /* if irq lock are masked and interrupt mode is on, we + * have to poll the status register */ + if (GLOBAL_IRQ_ARE_MASKED() && (*uart_regs[num].ucsrb & (1 << RXCIE)) ) { + while( !(*uart_regs[num].ucsra & (1 << UDRE)) ); + /* send the next char in the fifo to free a + * place */ + uart_send_next_char(num); + cirbuf_add_head(&g_tx_fifo[num], c); + } + else { + /* if irq are not locked, we can loop to emit */ + while(uart_send_nowait(num, c) == -1); + } + } + return c; +} diff --git a/modules/comm/uart/uart_send9.c b/modules/comm/uart/uart_send9.c new file mode 100644 index 0000000..ba5b898 --- /dev/null +++ b/modules/comm/uart/uart_send9.c @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_send9.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +int uart_send_9bits(uint8_t num, int c) +{ + /* if cannot send the char */ + if (uart_send_9bits_nowait(num, c) == -1) { + + /* if irq lock are masked and interrupt mode is on, we + * have to poll the status register */ + if (GLOBAL_IRQ_ARE_MASKED() && (*uart_regs[num].ucsrb & (1 << RXCIE)) ) { + while( !(*uart_regs[num].ucsra & (1 << UDRE)) ); + /* send the next char in the fifo to free two + * places */ + uart_send_next_char(num); + cirbuf_add_buf_head(&g_tx_fifo[num], (char *)&c, 2); + } + else { + /* if irq are not locked, we can loop to emit */ + while(uart_send_9bits_nowait(num, c) == -1); + } + } + return c; +} diff --git a/modules/comm/uart/uart_send9_nowait.c b/modules/comm/uart/uart_send9_nowait.c new file mode 100644 index 0000000..d22ef7b --- /dev/null +++ b/modules/comm/uart/uart_send9_nowait.c @@ -0,0 +1,65 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_send9_nowait.c,v 1.1.2.2 2008-12-27 16:50:01 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +int uart_send_9bits_nowait(int c) +{ + uint8_t flags; + IRQ_LOCK(flags); + + /* if tx intrp are disabled (RXCIE is 0) */ + if ( !(*uart_regs[num].ucsrb & (1 << RXCIE )) ) { + /* we have to poll the status register before xmit */ + if (*uart_regs[num].ucsra & (1<<UDRE)) { + uart_set_udr_9bits(c); + IRQ_UNLOCK(flags); + return c; + } + else { + IRQ_UNLOCK(flags); + return -1; + } + } + + /* the fifo must have 2 free places */ + if( CIRBUF_GET_FREELEN(&g_tx_fifo) < 2) { + IRQ_UNLOCK(flags); + return -1; + } + + /* uart is ready to send */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[num]) && + *uart_regs[num].ucsra & (1<<UDRE)) { + uart_set_udr_9bits(c); + sbi(*uart_regs[num].ucsrb, UDRIE); /* XXX */ + } + else { /* not ready, put char in fifo */ + cirbuf_add_buf_head(&g_tx_fifo, (char *)&c, 2); + } + + IRQ_UNLOCK(flags); + return (int)c; +} diff --git a/modules/comm/uart/uart_send_nowait.c b/modules/comm/uart/uart_send_nowait.c new file mode 100644 index 0000000..6a0a008 --- /dev/null +++ b/modules/comm/uart/uart_send_nowait.c @@ -0,0 +1,69 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_send_nowait.c,v 1.1.2.2 2008-12-27 16:50:01 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + + +/* send a char, or put it in the fifo if uart is not ready. Return -1 + * if fifo is full */ +int uart_send_nowait(uint8_t num, char c) +{ + uint8_t flags; + + IRQ_LOCK(flags); + + /* if uart intrp mode is disabled (note that we look rx */ + /* intrp -- RXCIE is 0) */ + if ( !(*uart_regs[num].ucsrb & (1 << RXCIE )) ) { + /* we have to poll the status register before xmit */ + if (*uart_regs[num].ucsra & (1<<UDRE)) { + uart_set_udr(num, c); + IRQ_UNLOCK(flags); + return (int)c; + } + else { + IRQ_UNLOCK(flags); + return -1; + } + } + + if (CIRBUF_IS_FULL(&g_tx_fifo[num])) { + IRQ_UNLOCK(flags); + return -1; + } + + /* uart is ready to send */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[num]) && + *uart_regs[num].ucsra & (1<<UDRE)) { + uart_set_udr(num, c); + sbi(*uart_regs[num].ucsrb, UDRIE); /* XXX */ + } + else { /* not ready, put char in fifo */ + cirbuf_add_head(&g_tx_fifo[num], c); + } + + IRQ_UNLOCK(flags); + return (int)c; +} diff --git a/modules/comm/uart/uart_setconf.c b/modules/comm/uart/uart_setconf.c new file mode 100644 index 0000000..7088887 --- /dev/null +++ b/modules/comm/uart/uart_setconf.c @@ -0,0 +1,272 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_setconf.c,v 1.1.2.3 2009-01-03 16:24:50 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2009 */ + +#include <uart.h> +#include <uart_defs.h> +#include <uart_private.h> + +/** The emission fifo of uart */ +#ifdef UART0_COMPILE +char g_tx0_buf[UART0_TX_FIFO_SIZE]; +char g_rx0_buf[UART0_RX_FIFO_SIZE]; +#endif +#ifdef UART1_COMPILE +char g_tx1_buf[UART1_TX_FIFO_SIZE]; +char g_rx1_buf[UART1_RX_FIFO_SIZE]; +#endif +#ifdef UART2_COMPILE +char g_tx2_buf[UART2_TX_FIFO_SIZE]; +char g_rx2_buf[UART2_RX_FIFO_SIZE]; +#endif +#ifdef UART3_COMPILE +char g_tx3_buf[UART3_TX_FIFO_SIZE]; +char g_rx3_buf[UART3_RX_FIFO_SIZE]; +#endif + +#if UART_IS_USART + +static int8_t uart_set_nbits_parity(uint8_t num, struct uart_config * u) +{ + uint8_t ucsrc = 0; + + /* number of bit in the frame */ +#ifdef CONFIG_MODULE_UART_9BITS + if (u->nbits < 5 || u->nbits > 9) { + return ENOTSUP; + } +#else + if (u->nbits < 5 || u->nbits > 8) { + return ENOTSUP; + } +#endif + + ucsrc |= ( ((u->nbits - 5) & 0x03) << UCSZ0 ); +#ifdef CONFIG_MODULE_UART_9BITS + if (u->nbits == 9) + *uart_regs[num].ucsrb |= (1 << UCSZ2); + else +#endif + *uart_regs[num].ucsrb &= ~(1 << UCSZ2); + + /* parity */ + if (u->parity == UART_PARTITY_ODD) + ucsrc |= ((1 << UPM0) | (1 << UPM1)); + else if (u->parity == UART_PARTITY_EVEN) + ucsrc |= (1 << UPM1); + else if (u->parity != UART_PARTITY_NONE) { + return EINVAL; + } + + /* nb of stop bits */ + if (u->stop_bits == UART_STOP_BITS_2) + ucsrc |= (1 << USBS); + else if (u->stop_bits != UART_STOP_BITS_1) + return EINVAL; + +#ifdef URSEL + /* some uC use a special bit URSEL to access to UCSRC */ + ucsrc |= (1<<URSEL); +#endif + *uart_regs[num].ucsrc = ucsrc; + + return ESUCCESS; +} + +#else /* UART_IS_USART */ + +static int8_t uart_set_nbits_parity(int8_t num, struct uart_config * u) +{ + /* number of bit in the frame */ + if (u->nbits == 8) + *uart_regs[num].ucsrb &= ~(1 << CHR9); +#ifdef CONFIG_MODULE_UART_9BITS + else if (u->nbits == 9) + *uart_regs[num].ucsrb |= (1 << CHR9); +#endif + else + return ENOTSUP; + + /* parity and stop */ + if (u->parity != UART_PARTITY_NONE || + u->stop_bits != UART_STOP_BITS_1) { + return ENOTSUP; + } + + return ESUCCESS; +} +#endif /* UART_IS_USART */ + + +#if UART_IS_USART + +static int8_t uart_set_baudreg(uint8_t num, uint16_t baudreg) +{ + uint8_t lo, hi; + + /* set msb bit of hi to 0 (useful fot uC with URSEL, and not + * important for the others because the baudreg will never be + * as big */ + lo = (uint8_t)baudreg; + hi = (uint8_t)(baudreg>>8) & 0x7F; + + *uart_regs[num].ubrrl = lo; + *uart_regs[num].ubrrh = hi; + + return ESUCCESS; +} + +#else /* UART_IS_USART */ + +static int8_t uart_set_baudreg(uint8_t num, uint16_t baudreg) +{ + uint8_t lo, hi; + + lo=(uint8_t)baudreg; + hi=(uint8_t)(baudreg>>8); + + if (hi != 0) + return EINVAL; + *uart_regs[num].ubrrl = lo; + + return ESUCCESS; +} +#endif /* UART_IS_USART */ + +/* configuration from uart_config.h */ +#define UART_SET_STATICCONF(x) \ + u->enabled = UART##x##_ENABLED; \ + u->intr_enabled = UART##x##_INTERRUPT_ENABLED; \ + u->use_double_speed = UART##x##_USE_DOUBLE_SPEED; \ + u->parity = UART##x##_PARITY; \ + u->stop_bits = UART##x##_STOP_BIT; \ + u->nbits = UART##x##_NBITS; \ + u->baudrate = UART##x##_BAUDRATE; \ + break + +int8_t uart_setconf(uint8_t num, struct uart_config *u) +{ + uint8_t ret = ESUCCESS; + uint16_t baudrate_reg; + struct uart_config static_conf; + uint8_t flags; + + IRQ_LOCK(flags); + + /* static configuration */ + if (!u) { + u = &static_conf; + switch (num) { +#ifdef UART0_COMPILE + case 0: + UART_SET_STATICCONF(0); +#endif +#ifdef UART1_COMPILE + case 1: + UART_SET_STATICCONF(1); +#endif +#ifdef UART2_COMPILE + case 2: + UART_SET_STATICCONF(2); +#endif +#ifdef UART3_COMPILE + case 3: + UART_SET_STATICCONF(3); +#endif + default: + ret = EINVAL; + goto out; + } + } + + /* wait xmit finished (UDRE = 1) */ + while( !(*uart_regs[num].ucsra & (1<<UDRE)) ); + + switch (num) { +#ifdef UART0_COMPILE + case 0: + cirbuf_init(&g_tx_fifo[0], g_tx0_buf, 0, UART0_TX_FIFO_SIZE); + cirbuf_init(&g_rx_fifo[0], g_rx0_buf, 0, UART0_RX_FIFO_SIZE); + break; +#endif +#ifdef UART1_COMPILE + case 1: + cirbuf_init(&g_tx_fifo[1], g_tx1_buf, 0, UART1_TX_FIFO_SIZE); + cirbuf_init(&g_rx_fifo[1], g_rx1_buf, 0, UART1_RX_FIFO_SIZE); + break; +#endif +#ifdef UART2_COMPILE + case 2: + cirbuf_init(&g_tx_fifo[2], g_tx2_buf, 0, UART2_TX_FIFO_SIZE); + cirbuf_init(&g_rx_fifo[2], g_rx2_buf, 0, UART2_RX_FIFO_SIZE); + break; +#endif +#ifdef UART3_COMPILE + case 3: + cirbuf_init(&g_tx_fifo[3], g_tx3_buf, 0, UART3_TX_FIFO_SIZE); + cirbuf_init(&g_rx_fifo[3], g_rx3_buf, 0, UART3_RX_FIFO_SIZE); + break; +#endif + default: + ret = EINVAL; + goto out; + } + *uart_regs[num].ucsra = 0; + + if (u->enabled) + *uart_regs[num].ucsrb = ((1 << TXEN) | (1 << RXEN)); + else { + *uart_regs[num].ucsrb = 0; + goto out; /* no more conf */ + } + + /* we only enable recv interrupt, the xmit intrpt will be + * enabled in the xmit function */ + if (u->intr_enabled) + *uart_regs[num].ucsrb |= (1 << RXCIE); + + if (UART_HAS_U2X) { /* if u2x is supported */ + if (u->use_double_speed) /* u2x is enabled */ + *uart_regs[num].ucsra |= (1 << U2X); + else + *uart_regs[num].ucsra &= ~(1 << U2X); + } + else if (u->use_double_speed) { + ret = ENOTSUP; + goto out; + } + + uart_set_nbits_parity(num, u); + + /* baudrate */ + if(u->use_double_speed) + baudrate_reg = (F_CPU / (u->baudrate*8l)) - 1; + else + baudrate_reg = (F_CPU / (u->baudrate*16l)) - 1; + + uart_set_baudreg(num, baudrate_reg); + + /* exit */ + out: + IRQ_UNLOCK(flags); + return ret; +} diff --git a/modules/crypto/CVS/Entries b/modules/crypto/CVS/Entries new file mode 100644 index 0000000..ebcd5e0 --- /dev/null +++ b/modules/crypto/CVS/Entries @@ -0,0 +1,4 @@ +D/aes//// +D/md5//// +D/rc4//// +D/test//// diff --git a/modules/crypto/CVS/Repository b/modules/crypto/CVS/Repository new file mode 100644 index 0000000..2d4f256 --- /dev/null +++ b/modules/crypto/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/crypto diff --git a/modules/crypto/CVS/Root b/modules/crypto/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/crypto/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/crypto/CVS/Tag b/modules/crypto/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/crypto/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/crypto/CVS/Template b/modules/crypto/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/crypto/aes/CVS/Entries b/modules/crypto/aes/CVS/Entries new file mode 100644 index 0000000..519749d --- /dev/null +++ b/modules/crypto/aes/CVS/Entries @@ -0,0 +1,7 @@ +/Makefile/1.1.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/aes.h/1.3.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/aes_core.c/1.2.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/aes_ctr.c/1.2.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/aes_ctr.h/1.1.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/aes_locl.h/1.3.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +D diff --git a/modules/crypto/aes/CVS/Repository b/modules/crypto/aes/CVS/Repository new file mode 100644 index 0000000..b7d0188 --- /dev/null +++ b/modules/crypto/aes/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/crypto/aes diff --git a/modules/crypto/aes/CVS/Root b/modules/crypto/aes/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/crypto/aes/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/crypto/aes/CVS/Tag b/modules/crypto/aes/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/crypto/aes/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/crypto/aes/CVS/Template b/modules/crypto/aes/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/crypto/aes/Makefile b/modules/crypto/aes/Makefile new file mode 100644 index 0000000..aa1f3d8 --- /dev/null +++ b/modules/crypto/aes/Makefile @@ -0,0 +1,11 @@ +TARGET = aes + +-include .config + +# List C source files here. (C dependencies are automatically generated.) +SRC = aes_core.c +ifeq ($(CONFIG_MODULE_AES_CTR),y) +SRC += aes_ctr.c +endif + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/crypto/aes/aes.h b/modules/crypto/aes/aes.h new file mode 100644 index 0000000..2a628ed --- /dev/null +++ b/modules/crypto/aes/aes.h @@ -0,0 +1,115 @@ +/* crypto/aes/aes.h -*- mode:C; c-file-style: "eay" -*- */ +/* ==================================================================== + * Copyright (c) 1998-2002 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== + * + */ + +#ifndef HEADER_AES_H +#define HEADER_AES_H + +#include <aversive.h> + +#ifdef OPENSSL_NO_AES +#error AES is disabled. +#endif + +#define AES_ENCRYPT 1 +#define AES_DECRYPT 0 + +/* Because array size can't be a const in C, the following two are macros. + Both sizes are in bytes. */ +#define AES_MAXNR 14 +#define AES_BLOCK_SIZE 16 + +#ifdef __cplusplus +extern "C" { +#endif + +/* This should be a hidden type, but EVP requires that the size be known */ +struct aes_key_st { + //unsigned long rd_key[4 *(AES_MAXNR + 1)]; + uint32_t rd_key[4 *(AES_MAXNR + 1)]; + int rounds; +}; +typedef struct aes_key_st AES_KEY; + +const char *AES_options(void); + +int AES_set_encrypt_key(const unsigned char *userKey, const int bits, + AES_KEY *key); +int AES_set_decrypt_key(const unsigned char *userKey, const int bits, + AES_KEY *key); + +void AES_encrypt(const unsigned char *in, unsigned char *out, + const AES_KEY *key); +void AES_decrypt(const unsigned char *in, unsigned char *out, + const AES_KEY *key); + +void AES_ecb_encrypt(const unsigned char *in, unsigned char *out, + const AES_KEY *key, const int enc); +void AES_cbc_encrypt(const unsigned char *in, unsigned char *out, + const unsigned long length, const AES_KEY *key, + unsigned char *ivec, const int enc); +void AES_cfb128_encrypt(const unsigned char *in, unsigned char *out, + const unsigned long length, const AES_KEY *key, + unsigned char *ivec, int *num, const int enc); +void AES_ofb128_encrypt(const unsigned char *in, unsigned char *out, + const unsigned long length, const AES_KEY *key, + unsigned char *ivec, int *num); +void AES_ctr128_encrypt(const unsigned char *in, unsigned char *out, + const unsigned long length, const AES_KEY *key, + unsigned char counter[AES_BLOCK_SIZE], + unsigned char ecount_buf[AES_BLOCK_SIZE], + unsigned int *num); + + +#ifdef __cplusplus +} +#endif + +#endif /* !HEADER_AES_H */ diff --git a/modules/crypto/aes/aes_core.c b/modules/crypto/aes/aes_core.c new file mode 100644 index 0000000..d121814 --- /dev/null +++ b/modules/crypto/aes/aes_core.c @@ -0,0 +1,790 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * This code is mainly from rijndael-alg-fst.c + * + * @version 3.0 (December 2000) + * + * Optimised ANSI C code for the Rijndael cipher (now AES) + * + * @author Vincent Rijmen <vincent.rijmen@esat.kuleuven.ac.be> + * @author Antoon Bosselaers <antoon.bosselaers@esat.kuleuven.ac.be> + * @author Paulo Barreto <paulo.barreto@terra.com.br> + * + */ + +/* Optimized to use AVR flash to store big tables */ + +#ifndef HOST_VERSION +#define USE_PGMMEM +#endif + +#ifndef AES_DEBUG +# ifndef NDEBUG +# define NDEBUG +# endif +#endif +#include <assert.h> + +#include <aversive.h> +#include "aes_locl.h" +#include "aes.h" +#include "aes_locl.h" +#include <aversive/pgmspace.h> + +/* +Te0[x] = S [x].[02, 01, 01, 03]; +Te1[x] = S [x].[03, 02, 01, 01]; +Te2[x] = S [x].[01, 03, 02, 01]; +Te3[x] = S [x].[01, 01, 03, 02]; +Te4[x] = S [x].[01, 01, 01, 01]; + +Td0[x] = Si[x].[0e, 09, 0d, 0b]; +Td1[x] = Si[x].[0b, 0e, 09, 0d]; +Td2[x] = Si[x].[0d, 0b, 0e, 09]; +Td3[x] = Si[x].[09, 0d, 0b, 0e]; +Td4[x] = Si[x].[01, 01, 01, 01]; +*/ + + +#define ROR_U32_1(a) ( (((a)&0xff)<<24) ^ ((((a)>>8)&0xff)<<0) ^ ((((a)>>16)&0xff)<<8) ^ (((a)>>24)<<16) ) +#define ROR_U32_2(a) ( (((a)&0xff)<<16) ^ ((((a)>>8)&0xff)<<24) ^ ((((a)>>16)&0xff)<<0) ^ (((a)>>24)<<8) ) +#define ROR_U32_3(a) ( (((a)&0xff)<<8) ^ ((((a)>>8)&0xff)<<16) ^ ((((a)>>16)&0xff)<<24)^ (((a)>>24)<<0) ) + + +#ifdef USE_PGMMEM +prog_uint32_t Te0_[256] = { +#else +static const uint32_t Te0_[256] = { +#endif + 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, + 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, + 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, + 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU, + 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, + 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, + 0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, + 0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU, + 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU, + 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, + 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, + 0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU, + 0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU, + 0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U, + 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, + 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, + 0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, + 0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU, + 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU, + 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, + 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, + 0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, + 0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU, + 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU, + 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, + 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, + 0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, + 0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U, + 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU, + 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, + 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, + 0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, + 0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU, + 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U, + 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, + 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, + 0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, + 0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U, + 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU, + 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, + 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, + 0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, + 0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U, + 0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU, + 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, + 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, + 0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, + 0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U, + 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U, + 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, + 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, + 0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, + 0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU, + 0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U, + 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, + 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, + 0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U, + 0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U, + 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U, + 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, + 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, + 0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, + 0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U, + 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU, +}; + +#ifdef USE_PGMMEM +static inline uint32_t Te0(int i) +{ + uint32_t tmp; + memcpy_P(&tmp, Te0_+i, sizeof(uint32_t)); + return tmp; +} +#else +#define Te0(x) Te0_[x] +#endif + +#ifdef USE_PGMMEM +prog_uint8_t Te4_[256] = { +#else +static const u8 Te4_[256] = { +#endif + 0x63U, 0x7cU, 0x77U, 0x7bU, + 0xf2U, 0x6bU, 0x6fU, 0xc5U, + 0x30U, 0x01U, 0x67U, 0x2bU, + 0xfeU, 0xd7U, 0xabU, 0x76U, + 0xcaU, 0x82U, 0xc9U, 0x7dU, + 0xfaU, 0x59U, 0x47U, 0xf0U, + 0xadU, 0xd4U, 0xa2U, 0xafU, + 0x9cU, 0xa4U, 0x72U, 0xc0U, + 0xb7U, 0xfdU, 0x93U, 0x26U, + 0x36U, 0x3fU, 0xf7U, 0xccU, + 0x34U, 0xa5U, 0xe5U, 0xf1U, + 0x71U, 0xd8U, 0x31U, 0x15U, + 0x04U, 0xc7U, 0x23U, 0xc3U, + 0x18U, 0x96U, 0x05U, 0x9aU, + 0x07U, 0x12U, 0x80U, 0xe2U, + 0xebU, 0x27U, 0xb2U, 0x75U, + 0x09U, 0x83U, 0x2cU, 0x1aU, + 0x1bU, 0x6eU, 0x5aU, 0xa0U, + 0x52U, 0x3bU, 0xd6U, 0xb3U, + 0x29U, 0xe3U, 0x2fU, 0x84U, + 0x53U, 0xd1U, 0x00U, 0xedU, + 0x20U, 0xfcU, 0xb1U, 0x5bU, + 0x6aU, 0xcbU, 0xbeU, 0x39U, + 0x4aU, 0x4cU, 0x58U, 0xcfU, + 0xd0U, 0xefU, 0xaaU, 0xfbU, + 0x43U, 0x4dU, 0x33U, 0x85U, + 0x45U, 0xf9U, 0x02U, 0x7fU, + 0x50U, 0x3cU, 0x9fU, 0xa8U, + 0x51U, 0xa3U, 0x40U, 0x8fU, + 0x92U, 0x9dU, 0x38U, 0xf5U, + 0xbcU, 0xb6U, 0xdaU, 0x21U, + 0x10U, 0xffU, 0xf3U, 0xd2U, + 0xcdU, 0x0cU, 0x13U, 0xecU, + 0x5fU, 0x97U, 0x44U, 0x17U, + 0xc4U, 0xa7U, 0x7eU, 0x3dU, + 0x64U, 0x5dU, 0x19U, 0x73U, + 0x60U, 0x81U, 0x4fU, 0xdcU, + 0x22U, 0x2aU, 0x90U, 0x88U, + 0x46U, 0xeeU, 0xb8U, 0x14U, + 0xdeU, 0x5eU, 0x0bU, 0xdbU, + 0xe0U, 0x32U, 0x3aU, 0x0aU, + 0x49U, 0x06U, 0x24U, 0x5cU, + 0xc2U, 0xd3U, 0xacU, 0x62U, + 0x91U, 0x95U, 0xe4U, 0x79U, + 0xe7U, 0xc8U, 0x37U, 0x6dU, + 0x8dU, 0xd5U, 0x4eU, 0xa9U, + 0x6cU, 0x56U, 0xf4U, 0xeaU, + 0x65U, 0x7aU, 0xaeU, 0x08U, + 0xbaU, 0x78U, 0x25U, 0x2eU, + 0x1cU, 0xa6U, 0xb4U, 0xc6U, + 0xe8U, 0xddU, 0x74U, 0x1fU, + 0x4bU, 0xbdU, 0x8bU, 0x8aU, + 0x70U, 0x3eU, 0xb5U, 0x66U, + 0x48U, 0x03U, 0xf6U, 0x0eU, + 0x61U, 0x35U, 0x57U, 0xb9U, + 0x86U, 0xc1U, 0x1dU, 0x9eU, + 0xe1U, 0xf8U, 0x98U, 0x11U, + 0x69U, 0xd9U, 0x8eU, 0x94U, + 0x9bU, 0x1eU, 0x87U, 0xe9U, + 0xceU, 0x55U, 0x28U, 0xdfU, + 0x8cU, 0xa1U, 0x89U, 0x0dU, + 0xbfU, 0xe6U, 0x42U, 0x68U, + 0x41U, 0x99U, 0x2dU, 0x0fU, + 0xb0U, 0x54U, 0xbbU, 0x16U, +}; +#ifdef USE_PGMMEM +static inline u8 Te4(int i) +{ + u8 tmp; + memcpy_P(&tmp, Te4_+i, sizeof(u8)); + return tmp; +} +#else +#define Te4(x) Te4_[x] +#endif + + +#ifdef USE_PGMMEM +prog_uint32_t Td0_[256] = { +#else +static const uint32_t Td0_[256] = { +#endif + 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, + 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, + 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, + 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU, + 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, + 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, + 0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU, + 0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U, + 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU, + 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, + 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, + 0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, + 0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U, + 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU, + 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, + 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, + 0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, + 0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU, + 0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U, + 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, + 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, + 0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU, + 0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U, + 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU, + 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, + 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, + 0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U, + 0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU, + 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU, + 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, + 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, + 0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, + 0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU, + 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U, + 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, + 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, + 0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, + 0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U, + 0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U, + 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, + 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, + 0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, + 0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U, + 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U, + 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, + 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, + 0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, + 0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U, + 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U, + 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, + 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, + 0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, + 0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU, + 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU, + 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, + 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, + 0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, + 0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU, + 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU, + 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, + 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, + 0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U, + 0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U, + 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U, +}; +#ifdef USE_PGMMEM +static inline uint32_t Td0(int i) +{ + uint32_t tmp; + memcpy_P(&tmp, Td0_+i, sizeof(uint32_t)); + return tmp; +} +#else +#define Td0(x) Td0_[x] +#endif + +#ifdef USE_PGMMEM +prog_uint8_t Td4_[256] = { +#else +static const u8 Td4_[256] = { +#endif + 0x52U, 0x09U, 0x6aU, 0xd5U, + 0x30U, 0x36U, 0xa5U, 0x38U, + 0xbfU, 0x40U, 0xa3U, 0x9eU, + 0x81U, 0xf3U, 0xd7U, 0xfbU, + 0x7cU, 0xe3U, 0x39U, 0x82U, + 0x9bU, 0x2fU, 0xffU, 0x87U, + 0x34U, 0x8eU, 0x43U, 0x44U, + 0xc4U, 0xdeU, 0xe9U, 0xcbU, + 0x54U, 0x7bU, 0x94U, 0x32U, + 0xa6U, 0xc2U, 0x23U, 0x3dU, + 0xeeU, 0x4cU, 0x95U, 0x0bU, + 0x42U, 0xfaU, 0xc3U, 0x4eU, + 0x08U, 0x2eU, 0xa1U, 0x66U, + 0x28U, 0xd9U, 0x24U, 0xb2U, + 0x76U, 0x5bU, 0xa2U, 0x49U, + 0x6dU, 0x8bU, 0xd1U, 0x25U, + 0x72U, 0xf8U, 0xf6U, 0x64U, + 0x86U, 0x68U, 0x98U, 0x16U, + 0xd4U, 0xa4U, 0x5cU, 0xccU, + 0x5dU, 0x65U, 0xb6U, 0x92U, + 0x6cU, 0x70U, 0x48U, 0x50U, + 0xfdU, 0xedU, 0xb9U, 0xdaU, + 0x5eU, 0x15U, 0x46U, 0x57U, + 0xa7U, 0x8dU, 0x9dU, 0x84U, + 0x90U, 0xd8U, 0xabU, 0x00U, + 0x8cU, 0xbcU, 0xd3U, 0x0aU, + 0xf7U, 0xe4U, 0x58U, 0x05U, + 0xb8U, 0xb3U, 0x45U, 0x06U, + 0xd0U, 0x2cU, 0x1eU, 0x8fU, + 0xcaU, 0x3fU, 0x0fU, 0x02U, + 0xc1U, 0xafU, 0xbdU, 0x03U, + 0x01U, 0x13U, 0x8aU, 0x6bU, + 0x3aU, 0x91U, 0x11U, 0x41U, + 0x4fU, 0x67U, 0xdcU, 0xeaU, + 0x97U, 0xf2U, 0xcfU, 0xceU, + 0xf0U, 0xb4U, 0xe6U, 0x73U, + 0x96U, 0xacU, 0x74U, 0x22U, + 0xe7U, 0xadU, 0x35U, 0x85U, + 0xe2U, 0xf9U, 0x37U, 0xe8U, + 0x1cU, 0x75U, 0xdfU, 0x6eU, + 0x47U, 0xf1U, 0x1aU, 0x71U, + 0x1dU, 0x29U, 0xc5U, 0x89U, + 0x6fU, 0xb7U, 0x62U, 0x0eU, + 0xaaU, 0x18U, 0xbeU, 0x1bU, + 0xfcU, 0x56U, 0x3eU, 0x4bU, + 0xc6U, 0xd2U, 0x79U, 0x20U, + 0x9aU, 0xdbU, 0xc0U, 0xfeU, + 0x78U, 0xcdU, 0x5aU, 0xf4U, + 0x1fU, 0xddU, 0xa8U, 0x33U, + 0x88U, 0x07U, 0xc7U, 0x31U, + 0xb1U, 0x12U, 0x10U, 0x59U, + 0x27U, 0x80U, 0xecU, 0x5fU, + 0x60U, 0x51U, 0x7fU, 0xa9U, + 0x19U, 0xb5U, 0x4aU, 0x0dU, + 0x2dU, 0xe5U, 0x7aU, 0x9fU, + 0x93U, 0xc9U, 0x9cU, 0xefU, + 0xa0U, 0xe0U, 0x3bU, 0x4dU, + 0xaeU, 0x2aU, 0xf5U, 0xb0U, + 0xc8U, 0xebU, 0xbbU, 0x3cU, + 0x83U, 0x53U, 0x99U, 0x61U, + 0x17U, 0x2bU, 0x04U, 0x7eU, + 0xbaU, 0x77U, 0xd6U, 0x26U, + 0xe1U, 0x69U, 0x14U, 0x63U, + 0x55U, 0x21U, 0x0cU, 0x7dU, +}; +#ifdef USE_PGMMEM +static inline u8 Td4(int i) +{ + u8 tmp; + memcpy_P(&tmp, Td4_+i, sizeof(u8)); + return tmp; +} +#else +#define Td4(x) Td4_[x] +#endif + +static const uint32_t rcon[] = { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, + 0x10000000, 0x20000000, 0x40000000, 0x80000000, + 0x1B000000, 0x36000000, /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ +}; + +/** + * Expand the cipher key into the encryption key schedule. + */ +int AES_set_encrypt_key(const unsigned char *userKey, const int bits, + AES_KEY *key) { + + uint32_t *rk; + int i = 0; + uint32_t temp; + + if (!userKey || !key) + return -1; + if (bits != 128 && bits != 192 && bits != 256) + return -2; + + rk = key->rd_key; + + if (bits==128) + key->rounds = 10; + else if (bits==192) + key->rounds = 12; + else + key->rounds = 14; + + rk[0] = GETU32(userKey ); + rk[1] = GETU32(userKey + 4); + rk[2] = GETU32(userKey + 8); + rk[3] = GETU32(userKey + 12); + if (bits == 128) { + for (;;) { + temp = rk[3]; + rk[4] = rk[0] ^ + ((uint32_t)Te4((temp >> 16) & 0xff) <<24) ^ + ((uint32_t)Te4((temp >> 8) & 0xff) <<16) ^ + ((uint32_t)Te4((temp ) & 0xff) <<8) ^ + ((uint32_t)Te4((temp >> 24) ) ) ^ + rcon[i]; + rk[5] = rk[1] ^ rk[4]; + rk[6] = rk[2] ^ rk[5]; + rk[7] = rk[3] ^ rk[6]; + if (++i == 10) { + return 0; + } + rk += 4; + } + } + rk[4] = GETU32(userKey + 16); + rk[5] = GETU32(userKey + 20); + if (bits == 192) { + for (;;) { + temp = rk[ 5]; + rk[ 6] = rk[ 0] ^ + ((uint32_t)Te4((temp >> 16) & 0xff) <<24) ^ + ((uint32_t)Te4((temp >> 8) & 0xff) <<16) ^ + ((uint32_t)Te4((temp ) & 0xff) <<8) ^ + ((uint32_t)Te4((temp >> 24) ) ) ^ + rcon[i]; + rk[ 7] = rk[ 1] ^ rk[ 6]; + rk[ 8] = rk[ 2] ^ rk[ 7]; + rk[ 9] = rk[ 3] ^ rk[ 8]; + if (++i == 8) { + return 0; + } + rk[10] = rk[ 4] ^ rk[ 9]; + rk[11] = rk[ 5] ^ rk[10]; + rk += 6; + } + } + rk[6] = GETU32(userKey + 24); + rk[7] = GETU32(userKey + 28); + if (bits == 256) { + for (;;) { + temp = rk[ 7]; + rk[ 8] = rk[ 0] ^ + ((uint32_t)Te4((temp >> 16) & 0xff) <<24) ^ + ((uint32_t)Te4((temp >> 8) & 0xff) <<16) ^ + ((uint32_t)Te4((temp ) & 0xff) <<8) ^ + ((uint32_t)Te4((temp >> 24) ) ) ^ + rcon[i]; + rk[ 9] = rk[ 1] ^ rk[ 8]; + rk[10] = rk[ 2] ^ rk[ 9]; + rk[11] = rk[ 3] ^ rk[10]; + if (++i == 7) { + return 0; + } + temp = rk[11]; + rk[12] = rk[ 4] ^ + ((uint32_t)Te4((temp >> 24) ) <<24) ^ + ((uint32_t)Te4((temp >> 16) & 0xff) <<16) ^ + ((uint32_t)Te4((temp >> 8) & 0xff) <<8) ^ + ((uint32_t)Te4((temp ) & 0xff) ); + rk[13] = rk[ 5] ^ rk[12]; + rk[14] = rk[ 6] ^ rk[13]; + rk[15] = rk[ 7] ^ rk[14]; + + rk += 8; + } + } + return 0; +} + +/** + * Expand the cipher key into the decryption key schedule. + */ +int AES_set_decrypt_key(const unsigned char *userKey, const int bits, + AES_KEY *key) { + + uint32_t *rk; + int i, j, status; + uint32_t temp; + + /* first, start with an encryption schedule */ + status = AES_set_encrypt_key(userKey, bits, key); + if (status < 0) + return status; + + rk = key->rd_key; + + /* invert the order of the round keys: */ + for (i = 0, j = 4*(key->rounds); i < j; i += 4, j -= 4) { + temp = rk[i ]; rk[i ] = rk[j ]; rk[j ] = temp; + temp = rk[i + 1]; rk[i + 1] = rk[j + 1]; rk[j + 1] = temp; + temp = rk[i + 2]; rk[i + 2] = rk[j + 2]; rk[j + 2] = temp; + temp = rk[i + 3]; rk[i + 3] = rk[j + 3]; rk[j + 3] = temp; + } + /* apply the inverse MixColumn transform to all round keys but the first and the last: */ + for (i = 1; i < (key->rounds); i++) { + rk += 4; + rk[0] = + Td0(Te4((rk[0] >> 24) ) ) ^ + ROR_U32_1(Td0(Te4((rk[0] >> 16) & 0xff) )) ^ + ROR_U32_2(Td0(Te4((rk[0] >> 8) & 0xff) )) ^ + ROR_U32_3(Td0(Te4((rk[0] ) & 0xff) )); + rk[1] = + Td0(Te4((rk[1] >> 24) ) ) ^ + ROR_U32_1(Td0(Te4((rk[1] >> 16) & 0xff) )) ^ + ROR_U32_2(Td0(Te4((rk[1] >> 8) & 0xff) )) ^ + ROR_U32_3(Td0(Te4((rk[1] ) & 0xff) )); + rk[2] = + Td0(Te4((rk[2] >> 24) ) ) ^ + ROR_U32_1(Td0(Te4((rk[2] >> 16) & 0xff) )) ^ + ROR_U32_2(Td0(Te4((rk[2] >> 8) & 0xff) )) ^ + ROR_U32_3(Td0(Te4((rk[2] ) & 0xff) )); + rk[3] = + Td0(Te4((rk[3] >> 24) ) ) ^ + ROR_U32_1(Td0(Te4((rk[3] >> 16) & 0xff) )) ^ + ROR_U32_2(Td0(Te4((rk[3] >> 8) & 0xff) )) ^ + ROR_U32_3(Td0(Te4((rk[3] ) & 0xff) )); + } + return 0; +} + +/* + * Encrypt a single block + * in and out can overlap + */ +void AES_encrypt(const unsigned char *in, unsigned char *out, + const AES_KEY *key) { + const uint32_t *rk; + uint32_t s0, s1, s2, s3, t0, t1, t2, t3; +#ifndef FULL_UNROLL + int r; +#endif /* ?FULL_UNROLL */ + + assert(in && out && key); + rk = key->rd_key; + + /* + * map byte array block to cipher state + * and add initial round key: + */ + s0 = GETU32(in ) ^ rk[0]; + s1 = GETU32(in + 4) ^ rk[1]; + s2 = GETU32(in + 8) ^ rk[2]; + s3 = GETU32(in + 12) ^ rk[3]; + /* + * Nr - 1 full rounds: + */ + r = key->rounds >> 1; + for (;;) { + t0 = + Te0((s0 >> 24) ) ^ + ROR_U32_1(Te0((s1 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((s2 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((s3 ) & 0xff)) ^ + rk[4]; + t1 = + Te0((s1 >> 24) ) ^ + ROR_U32_1(Te0((s2 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((s3 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((s0 ) & 0xff)) ^ + rk[5]; + t2 = + Te0((s2 >> 24) ) ^ + ROR_U32_1(Te0((s3 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((s0 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((s1 ) & 0xff)) ^ + rk[6]; + t3 = + Te0((s3 >> 24) ) ^ + ROR_U32_1(Te0((s0 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((s1 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((s2 ) & 0xff)) ^ + rk[7]; + + rk += 8; + if (--r == 0) { + break; + } + + s0 = + Te0((t0 >> 24) ) ^ + ROR_U32_1(Te0((t1 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((t2 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((t3 ) & 0xff)) ^ + rk[0]; + s1 = + Te0((t1 >> 24) ) ^ + ROR_U32_1(Te0((t2 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((t3 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((t0 ) & 0xff)) ^ + rk[1]; + s2 = + Te0((t2 >> 24) ) ^ + ROR_U32_1(Te0((t3 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((t0 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((t1 ) & 0xff)) ^ + rk[2]; + s3 = + Te0((t3 >> 24) ) ^ + ROR_U32_1(Te0((t0 >> 16) & 0xff)) ^ + ROR_U32_2(Te0((t1 >> 8) & 0xff)) ^ + ROR_U32_3(Te0((t2 ) & 0xff)) ^ + rk[3]; + } + /* + * apply last round and + * map cipher state to byte array block: + */ + s0 = + ((uint32_t)Te4((t0 >> 24) ) <<24) ^ + ((uint32_t)Te4((t1 >> 16) & 0xff) <<16) ^ + ((uint32_t)Te4((t2 >> 8) & 0xff) <<8) ^ + ((uint32_t)Te4((t3 ) & 0xff) ) ^ + rk[0]; + PUTU32(out , s0); + s1 = + ((uint32_t)Te4((t1 >> 24) ) <<24) ^ + ((uint32_t)Te4((t2 >> 16) & 0xff) <<16) ^ + ((uint32_t)Te4((t3 >> 8) & 0xff) <<8) ^ + ((uint32_t)Te4((t0 ) & 0xff) ) ^ + rk[1]; + PUTU32(out + 4, s1); + s2 = + ((uint32_t)Te4((t2 >> 24) ) <<24) ^ + ((uint32_t)Te4((t3 >> 16) & 0xff) <<16) ^ + ((uint32_t)Te4((t0 >> 8) & 0xff) <<8) ^ + ((uint32_t)Te4((t1 ) & 0xff) ) ^ + rk[2]; + PUTU32(out + 8, s2); + s3 = + ((uint32_t)Te4((t3 >> 24) ) <<24) ^ + ((uint32_t)Te4((t0 >> 16) & 0xff) <<16) ^ + ((uint32_t)Te4((t1 >> 8) & 0xff) <<8) ^ + ((uint32_t)Te4((t2 ) & 0xff) ) ^ + rk[3]; + PUTU32(out + 12, s3); +} + +/* + * Decrypt a single block + * in and out can overlap + */ +void AES_decrypt(const unsigned char *in, unsigned char *out, + const AES_KEY *key) { + + const uint32_t *rk; + uint32_t s0, s1, s2, s3, t0, t1, t2, t3; +#ifndef FULL_UNROLL + int r; +#endif /* ?FULL_UNROLL */ + + assert(in && out && key); + rk = key->rd_key; + + /* + * map byte array block to cipher state + * and add initial round key: + */ + s0 = GETU32(in ) ^ rk[0]; + s1 = GETU32(in + 4) ^ rk[1]; + s2 = GETU32(in + 8) ^ rk[2]; + s3 = GETU32(in + 12) ^ rk[3]; + /* + * Nr - 1 full rounds: + */ + r = key->rounds >> 1; + for (;;) { + t0 = + Td0((s0 >> 24) ) ^ + ROR_U32_1(Td0((s3 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((s2 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((s1 ) & 0xff)) ^ + rk[4]; + t1 = + Td0((s1 >> 24) ) ^ + ROR_U32_1(Td0((s0 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((s3 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((s2 ) & 0xff)) ^ + rk[5]; + t2 = + Td0((s2 >> 24) ) ^ + ROR_U32_1(Td0((s1 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((s0 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((s3 ) & 0xff)) ^ + rk[6]; + t3 = + Td0((s3 >> 24) ) ^ + ROR_U32_1(Td0((s2 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((s1 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((s0 ) & 0xff)) ^ + rk[7]; + + rk += 8; + if (--r == 0) { + break; + } + + s0 = + Td0((t0 >> 24) ) ^ + ROR_U32_1(Td0((t3 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((t2 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((t1 ) & 0xff)) ^ + rk[0]; + s1 = + Td0((t1 >> 24) ) ^ + ROR_U32_1(Td0((t0 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((t3 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((t2 ) & 0xff)) ^ + rk[1]; + s2 = + Td0((t2 >> 24) ) ^ + ROR_U32_1(Td0((t1 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((t0 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((t3 ) & 0xff)) ^ + rk[2]; + s3 = + Td0((t3 >> 24) ) ^ + ROR_U32_1(Td0((t2 >> 16) & 0xff)) ^ + ROR_U32_2(Td0((t1 >> 8) & 0xff)) ^ + ROR_U32_3(Td0((t0 ) & 0xff)) ^ + rk[3]; + } + /* + * apply last round and + * map cipher state to byte array block: + */ + s0 = + ((uint32_t)Td4((t0 >> 24) ) <<24) ^ + ((uint32_t)Td4((t3 >> 16) & 0xff) <<16) ^ + ((uint32_t)Td4((t2 >> 8) & 0xff) <<8) ^ + ((uint32_t)Td4((t1 ) & 0xff) ) ^ + rk[0]; + PUTU32(out , s0); + s1 = + ((uint32_t)Td4((t1 >> 24) ) <<24) ^ + ((uint32_t)Td4((t0 >> 16) & 0xff) <<16) ^ + ((uint32_t)Td4((t3 >> 8) & 0xff) <<8) ^ + ((uint32_t)Td4((t2 ) & 0xff) ) ^ + rk[1]; + PUTU32(out + 4, s1); + s2 = + ((uint32_t)Td4((t2 >> 24) ) <<24) ^ + ((uint32_t)Td4((t1 >> 16) & 0xff) <<16) ^ + ((uint32_t)Td4((t0 >> 8) & 0xff) <<8) ^ + ((uint32_t)Td4((t3 ) & 0xff) ) ^ + rk[2]; + PUTU32(out + 8, s2); + s3 = + ((uint32_t)Td4((t3 >> 24) ) <<24) ^ + ((uint32_t)Td4((t2 >> 16) & 0xff) <<16) ^ + ((uint32_t)Td4((t1 >> 8) & 0xff) <<8) ^ + ((uint32_t)Td4((t0 ) & 0xff) ) ^ + rk[3]; + PUTU32(out + 12, s3); +} + diff --git a/modules/crypto/aes/aes_ctr.c b/modules/crypto/aes/aes_ctr.c new file mode 100644 index 0000000..cf36d01 --- /dev/null +++ b/modules/crypto/aes/aes_ctr.c @@ -0,0 +1,129 @@ +/* crypto/aes/aes_ctr.c -*- mode:C; c-file-style: "eay" -*- */ +/* ==================================================================== + * Copyright (c) 1998-2002 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== + * + */ + +#ifndef AES_DEBUG +# ifndef NDEBUG +# define NDEBUG +# endif +#endif +#include <aversive.h> +#include <assert.h> +#include "aes_locl.h" +#include "aes.h" +#include "aes_locl.h" + +/* NOTE: CTR mode is big-endian. The rest of the AES code + * is endian-neutral. */ + +/* increment counter (128-bit int) by 2^64 */ +void AES_ctr128_inc(unsigned char *counter) { + unsigned long c; + + /* Grab 3rd dword of counter and increment */ +#ifdef L_ENDIAN + c = GETU32(counter + 8); + c++; + PUTU32(counter + 8, c); +#else + c = GETU32(counter + 4); + c++; + PUTU32(counter + 4, c); +#endif + + /* if no overflow, we're done */ + if (c) + return; + + /* Grab top dword of counter and increment */ +#ifdef L_ENDIAN + c = GETU32(counter + 12); + c++; + PUTU32(counter + 12, c); +#else + c = GETU32(counter + 0); + c++; + PUTU32(counter + 0, c); +#endif + +} + +/* The input encrypted as though 128bit counter mode is being + * used. The extra state information to record how much of the + * 128bit block we have used is contained in *num, and the + * encrypted counter is kept in ecount_buf. Both *num and + * ecount_buf must be initialised with zeros before the first + * call to AES_ctr128_encrypt(). + */ +void AES_ctr128_encrypt(const unsigned char *in, unsigned char *out, + const unsigned long length, const AES_KEY *key, + unsigned char counter[AES_BLOCK_SIZE], + unsigned char ecount_buf[AES_BLOCK_SIZE], + unsigned int *num) { + + unsigned int n; + unsigned long l=length; + + assert(in && out && key && counter && num); + assert(*num < AES_BLOCK_SIZE); + + n = *num; + + while (l--) { + if (n == 0) { + AES_encrypt(counter, ecount_buf, key); + AES_ctr128_inc(counter); + } + *(out++) = *(in++) ^ ecount_buf[n]; + n = (n+1) % AES_BLOCK_SIZE; + } + + *num=n; +} diff --git a/modules/crypto/aes/aes_ctr.h b/modules/crypto/aes/aes_ctr.h new file mode 100644 index 0000000..55f3229 --- /dev/null +++ b/modules/crypto/aes/aes_ctr.h @@ -0,0 +1,22 @@ +#ifndef AES_CTR_H +#define AES_CTR_H + + +typedef struct _aes_ctr_ctx +{ + AES_KEY key; + unsigned char counter[AES_BLOCK_SIZE]; + unsigned char ecount_buf[AES_BLOCK_SIZE]; + unsigned int num; +} aes_ctr_ctx; + +void AES_ctr128_inc(unsigned char *counter); + +void AES_ctr128_encrypt(const unsigned char *in, unsigned char *out, + const unsigned long length, const AES_KEY *key, + unsigned char counter[AES_BLOCK_SIZE], + unsigned char ecount_buf[AES_BLOCK_SIZE], + unsigned int *num) ; + + +#endif diff --git a/modules/crypto/aes/aes_locl.h b/modules/crypto/aes/aes_locl.h new file mode 100644 index 0000000..11554fb --- /dev/null +++ b/modules/crypto/aes/aes_locl.h @@ -0,0 +1,100 @@ +/* crypto/aes/aes.h -*- mode:C; c-file-style: "eay" -*- */ +/* ==================================================================== + * Copyright (c) 1998-2002 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== + * + */ + +#ifndef HEADER_AES_LOCL_H +#define HEADER_AES_LOCL_H + +//#include <openssl/e_os2.h> +#include <stdint.h> + +#ifdef OPENSSL_NO_AES +#error AES is disabled. +#endif + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +//#define L_ENDIAN +/* +#if defined(LITTLE_ENDIAN) +# define SWAP(x) (_lrotl(x, 8) & 0x00ff00ff | _lrotr(x, 8) & 0xff00ff00) +# define GETU32(p) SWAP(*((uint32_t *)(p))) +# define PUTU32(ct, st) { *((uint32_t *)(ct)) = SWAP((st)); } +#else +# define GETU32(pt) (((uint32_t)(pt)[0] << 24) ^ ((uint32_t)(pt)[1] << 16) ^ ((uint32_t)(pt)[2] << 8) ^ ((uint32_t)(pt)[3])) +# define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } +#endif +*/ + +#define GETU32(pt) (((uint32_t)(pt)[0] << 24) ^ ((uint32_t)(pt)[1] << 16) ^ ((uint32_t)(pt)[2] << 8) ^ ((uint32_t)(pt)[3])) +#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } + +/* +#define GETU32(pt) (((uint32_t)(pt)[0] << 0) ^ ((uint32_t)(pt)[1] << 8) ^ ((uint32_t)(pt)[2] << 16) ^ ((uint32_t)(pt)[3]<< 24)) +#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 0); (ct)[1] = (u8)((st) >> 8); (ct)[2] = (u8)((st) >> 16); (ct)[3] = (u8)((st) >> 24); } +*/ +/* +typedef unsigned long uint32_t; +typedef unsigned short uint16_t; +typedef unsigned char u8; +*/ + +typedef uint8_t u8; + +#define MAXKC (256/32) +#define MAXKB (256/8) +#define MAXNR 14 + +/* This controls loop-unrolling in aes_core.c */ +#undef FULL_UNROLL + +#endif /* !HEADER_AES_LOCL_H */ diff --git a/modules/crypto/md5/CVS/Entries b/modules/crypto/md5/CVS/Entries new file mode 100644 index 0000000..1496bb1 --- /dev/null +++ b/modules/crypto/md5/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.1.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/hmac_md5.c/1.2.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/hmac_md5.h/1.2.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/md5.h/1.3.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/md5c.c/1.3.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +D diff --git a/modules/crypto/md5/CVS/Repository b/modules/crypto/md5/CVS/Repository new file mode 100644 index 0000000..11f2e05 --- /dev/null +++ b/modules/crypto/md5/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/crypto/md5 diff --git a/modules/crypto/md5/CVS/Root b/modules/crypto/md5/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/crypto/md5/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/crypto/md5/CVS/Tag b/modules/crypto/md5/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/crypto/md5/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/crypto/md5/CVS/Template b/modules/crypto/md5/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/crypto/md5/Makefile b/modules/crypto/md5/Makefile new file mode 100644 index 0000000..5fbf856 --- /dev/null +++ b/modules/crypto/md5/Makefile @@ -0,0 +1,11 @@ +TARGET = md5 + +-include .config + +# List C source files here. (C dependencies are automatically generated.) +SRC = md5c.c +ifeq ($(CONFIG_MODULE_MD5_HMAC),y) +SRC += hmac_md5.c +endif + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/crypto/md5/hmac_md5.c b/modules/crypto/md5/hmac_md5.c new file mode 100644 index 0000000..7aa0423 --- /dev/null +++ b/modules/crypto/md5/hmac_md5.c @@ -0,0 +1,49 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: hmac_md5.c,v 1.2.4.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +#include <string.h> +#include "md5.h" + +void HMAC_MD5 (unsigned char *output, const unsigned char *input, + unsigned char *key, unsigned int inputLen, unsigned int keyLen) +{ + unsigned int i; + MD5_CTX context; + unsigned char key_tmp[64]; + + for (i=0;i<64;i++) + key_tmp[i] = (i<keyLen)?key[i]^0x36:0x36; + + MD5Init(&context); + MD5Update(&context, key_tmp, 64); + MD5Update(&context, input, inputLen); + MD5Final(output, &context); + + for (i=0;i<64;i++) + key_tmp[i] = (i<keyLen)?key[i]^0x5c:0x5c; + + + MD5Init(&context); + MD5Update(&context, key_tmp, 64); + MD5Update(&context, output, 16); + MD5Final(output, &context); +} + diff --git a/modules/crypto/md5/hmac_md5.h b/modules/crypto/md5/hmac_md5.h new file mode 100644 index 0000000..c6a39b4 --- /dev/null +++ b/modules/crypto/md5/hmac_md5.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: hmac_md5.h,v 1.2.4.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +void HMAC_MD5 (unsigned char *output, const unsigned char *input, + unsigned char *key, unsigned int inputLen, unsigned int keyLen); diff --git a/modules/crypto/md5/md5.h b/modules/crypto/md5/md5.h new file mode 100644 index 0000000..c7b2361 --- /dev/null +++ b/modules/crypto/md5/md5.h @@ -0,0 +1,48 @@ +/* MD5.H - header file for MD5C.C + * $OpenBSD: md5.h,v 1.3 1996/09/30 03:55:48 millert Exp $ + */ + +/* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All +rights reserved. + +License to copy and use this software is granted provided that it +is identified as the "RSA Data Security, Inc. MD5 Message-Digest +Algorithm" in all material mentioning or referencing this software +or this function. + +License is also granted to make and use derivative works provided +that such works are identified as "derived from the RSA Data +Security, Inc. MD5 Message-Digest Algorithm" in all material +mentioning or referencing the derived work. + +RSA Data Security, Inc. makes no representations concerning either +the merchantability of this software or the suitability of this +software for any particular purpose. It is provided "as is" +without express or implied warranty of any kind. + +These notices must be retained in any copies of any part of this +documentation and/or software. + */ + +#ifndef _MD5_H_ +#define _MD5_H_ + +#include <aversive.h> + +/* MD5 context. */ +typedef struct MD5Context { + uint32_t state[4]; /* state (ABCD) */ + uint32_t count[2]; /* number of bits, modulo 2^64 (lsb first) */ + unsigned char buffer[64]; /* input buffer */ +} MD5_CTX; + +#define MD5_SIZE 16 + +void MD5Init (MD5_CTX *); +void MD5Update (MD5_CTX *, const unsigned char *, unsigned int); +void MD5Final (unsigned char [MD5_SIZE], MD5_CTX *); +char * MD5End (MD5_CTX *, char *); +char * MD5File (char *, char *); +char * MD5Data (const unsigned char *, unsigned int, char *); + +#endif /* _MD5_H_ */ diff --git a/modules/crypto/md5/md5c.c b/modules/crypto/md5/md5c.c new file mode 100644 index 0000000..2aa44d7 --- /dev/null +++ b/modules/crypto/md5/md5c.c @@ -0,0 +1,327 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: md5c.c,v 1.3.4.1 2006-11-26 21:06:02 zer0 Exp $ + * + */ + +/* From MD5C.C - RSA Data Security, Inc., MD5 message-digest algorithm */ + +/* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All +rights reserved. + +License to copy and use this software is granted provided that it +is identified as the "RSA Data Security, Inc. MD5 Message-Digest +Algorithm" in all material mentioning or referencing this software +or this function. + +License is also granted to make and use derivative works provided +that such works are identified as "derived from the RSA Data +Security, Inc. MD5 Message-Digest Algorithm" in all material +mentioning or referencing the derived work. + +RSA Data Security, Inc. makes no representations concerning either +the merchantability of this software or the suitability of this +software for any particular purpose. It is provided "as is" +without express or implied warranty of any kind. + +These notices must be retained in any copies of any part of this +documentation and/or software. +*/ + +#include <string.h> +#include "md5.h" + +/* POINTER defines a generic pointer type */ +typedef unsigned char *POINTER; + +/* Constants for MD5Transform routine. + */ +#define S11 7 +#define S12 12 +#define S13 17 +#define S14 22 +#define S21 5 +#define S22 9 +#define S23 14 +#define S24 20 +#define S31 4 +#define S32 11 +#define S33 16 +#define S34 23 +#define S41 6 +#define S42 10 +#define S43 15 +#define S44 21 + +static void MD5Transform (uint32_t [4], const unsigned char [64]); + +#if BYTE_ORDER == LITTLE_ENDIAN +#define Encode memcpy +#define Decode memcpy +#else /* BIG_ENDIAN */ +static void Encode (unsigned char *, uint32_t *, unsigned int); +static void Decode (uint32_t *, const unsigned char *, unsigned int); +#endif /* LITTLE_ENDIAN */ + +static unsigned char PADDING[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* F, G, H and I are basic MD5 functions. + */ +#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) +#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) +#define H(x, y, z) ((x) ^ (y) ^ (z)) +#define I(x, y, z) ((y) ^ ((x) | (~z))) + +/* ROTATE_LEFT rotates x left n bits. + */ +#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) + +/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4. + Rotation is separate from addition to prevent recomputation. +*/ +#define FF(a, b, c, d, x, s, ac) { \ + (a) += F ((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define GG(a, b, c, d, x, s, ac) { \ + (a) += G ((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define HH(a, b, c, d, x, s, ac) { \ + (a) += H ((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define II(a, b, c, d, x, s, ac) { \ + (a) += I ((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } + +#if BYTE_ORDER != LITTLE_ENDIAN +/* Encodes input (uint32_t) into output (unsigned char). Assumes len is + a multiple of 4. +*/ +static void Encode (output, input, len) + unsigned char *output; + uint32_t *input; + unsigned int len; +{ + unsigned int i, j; + + for (i = 0, j = 0; j < len; i++, j += 4) { + output[j] = (unsigned char)(input[i] & 0xff); + output[j+1] = (unsigned char)((input[i] >> 8) & 0xff); + output[j+2] = (unsigned char)((input[i] >> 16) & 0xff); + output[j+3] = (unsigned char)((input[i] >> 24) & 0xff); + } +} + +/* Decodes input (unsigned char) into output (uint32_t). Assumes len is + a multiple of 4. +*/ +static void Decode (output, input, len) + uint32_t *output; + const unsigned char *input; + unsigned int len; +{ + unsigned int i, j; + + for (i = 0, j = 0; j < len; i++, j += 4) + output[i] = ((uint32_t)input[j]) | (((uint32_t)input[j+1]) << 8) | + (((uint32_t)input[j+2]) << 16) | (((uint32_t)input[j+3]) << 24); +} +#endif /* !LITTLE_ENDIAN */ + +/* MD5 initialization. Begins an MD5 operation, writing a new context. + */ +void MD5Init (context) + MD5_CTX *context; /* context */ +{ + context->count[0] = context->count[1] = 0; + /* Load magic initialization constants. */ + context->state[0] = 0x67452301; + context->state[1] = 0xefcdab89; + context->state[2] = 0x98badcfe; + context->state[3] = 0x10325476; +} + +/* MD5 block update operation. Continues an MD5 message-digest + operation, processing another message block, and updating the + context. +*/ +void MD5Update (context, input, inputLen) + MD5_CTX *context; /* context */ + const unsigned char *input; /* input block */ + unsigned int inputLen; /* length of input block */ +{ + unsigned int i, index, partLen; + + /* Compute number of bytes mod 64 */ + index = (unsigned int)((context->count[0] >> 3) & 0x3F); + + /* Update number of bits */ + if ((context->count[0] += ((uint32_t)inputLen << 3)) + < ((uint32_t)inputLen << 3)) + context->count[1]++; + context->count[1] += ((uint32_t)inputLen >> 29); + + partLen = 64 - index; + + /* Transform as many times as possible. */ + if (inputLen >= partLen) { + memcpy ((POINTER)&context->buffer[index], (POINTER)input, partLen); + MD5Transform (context->state, context->buffer); + + for (i = partLen; i + 63 < inputLen; i += 64) + MD5Transform (context->state, &input[i]); + + index = 0; + } + else + i = 0; + + /* Buffer remaining input */ + memcpy((POINTER)&context->buffer[index], (POINTER)&input[i], + inputLen-i); +} + +/* MD5 finalization. Ends an MD5 message-digest operation, writing the + the message digest and zeroizing the context. +*/ +void MD5Final (digest, context) + unsigned char digest[16]; /* message digest */ + MD5_CTX *context; /* context */ +{ + unsigned char bits[8]; + unsigned int index, padLen; + + /* Save number of bits */ + Encode (bits, context->count, 8); + + /* Pad out to 56 mod 64. */ + index = (unsigned int)((context->count[0] >> 3) & 0x3f); + padLen = (index < 56) ? (56 - index) : (120 - index); + MD5Update (context, PADDING, padLen); + + /* Append length (before padding) */ + MD5Update (context, bits, 8); + /* Store state in digest */ + Encode (digest, context->state, 16); + + /* Zeroize sensitive information. */ + memset ((POINTER)context, 0, sizeof (*context)); +} + +/* MD5 basic transformation. Transforms state based on block. + */ +static void MD5Transform (state, block) + uint32_t state[4]; + const unsigned char block[64]; +{ + uint32_t a = state[0], b = state[1], c = state[2], d = state[3], x[16]; + + Decode (x, block, 64); + + /* Round 1 */ + FF (a, b, c, d, x[ 0], S11, 0xd76aa478); /* 1 */ + FF (d, a, b, c, x[ 1], S12, 0xe8c7b756); /* 2 */ + FF (c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */ + FF (b, c, d, a, x[ 3], S14, 0xc1bdceee); /* 4 */ + FF (a, b, c, d, x[ 4], S11, 0xf57c0faf); /* 5 */ + FF (d, a, b, c, x[ 5], S12, 0x4787c62a); /* 6 */ + FF (c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */ + FF (b, c, d, a, x[ 7], S14, 0xfd469501); /* 8 */ + FF (a, b, c, d, x[ 8], S11, 0x698098d8); /* 9 */ + FF (d, a, b, c, x[ 9], S12, 0x8b44f7af); /* 10 */ + FF (c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */ + FF (b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */ + FF (a, b, c, d, x[12], S11, 0x6b901122); /* 13 */ + FF (d, a, b, c, x[13], S12, 0xfd987193); /* 14 */ + FF (c, d, a, b, x[14], S13, 0xa679438e); /* 15 */ + FF (b, c, d, a, x[15], S14, 0x49b40821); /* 16 */ + + /* Round 2 */ + GG (a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */ + GG (d, a, b, c, x[ 6], S22, 0xc040b340); /* 18 */ + GG (c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */ + GG (b, c, d, a, x[ 0], S24, 0xe9b6c7aa); /* 20 */ + GG (a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */ + GG (d, a, b, c, x[10], S22, 0x2441453); /* 22 */ + GG (c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */ + GG (b, c, d, a, x[ 4], S24, 0xe7d3fbc8); /* 24 */ + GG (a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */ + GG (d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */ + GG (c, d, a, b, x[ 3], S23, 0xf4d50d87); /* 27 */ + GG (b, c, d, a, x[ 8], S24, 0x455a14ed); /* 28 */ + GG (a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */ + GG (d, a, b, c, x[ 2], S22, 0xfcefa3f8); /* 30 */ + GG (c, d, a, b, x[ 7], S23, 0x676f02d9); /* 31 */ + GG (b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */ + + /* Round 3 */ + HH (a, b, c, d, x[ 5], S31, 0xfffa3942); /* 33 */ + HH (d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */ + HH (c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */ + HH (b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */ + HH (a, b, c, d, x[ 1], S31, 0xa4beea44); /* 37 */ + HH (d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */ + HH (c, d, a, b, x[ 7], S33, 0xf6bb4b60); /* 39 */ + HH (b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */ + HH (a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */ + HH (d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */ + HH (c, d, a, b, x[ 3], S33, 0xd4ef3085); /* 43 */ + HH (b, c, d, a, x[ 6], S34, 0x4881d05); /* 44 */ + HH (a, b, c, d, x[ 9], S31, 0xd9d4d039); /* 45 */ + HH (d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */ + HH (c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */ + HH (b, c, d, a, x[ 2], S34, 0xc4ac5665); /* 48 */ + + /* Round 4 */ + II (a, b, c, d, x[ 0], S41, 0xf4292244); /* 49 */ + II (d, a, b, c, x[ 7], S42, 0x432aff97); /* 50 */ + II (c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */ + II (b, c, d, a, x[ 5], S44, 0xfc93a039); /* 52 */ + II (a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */ + II (d, a, b, c, x[ 3], S42, 0x8f0ccc92); /* 54 */ + II (c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */ + II (b, c, d, a, x[ 1], S44, 0x85845dd1); /* 56 */ + II (a, b, c, d, x[ 8], S41, 0x6fa87e4f); /* 57 */ + II (d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */ + II (c, d, a, b, x[ 6], S43, 0xa3014314); /* 59 */ + II (b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */ + II (a, b, c, d, x[ 4], S41, 0xf7537e82); /* 61 */ + II (d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */ + II (c, d, a, b, x[ 2], S43, 0x2ad7d2bb); /* 63 */ + II (b, c, d, a, x[ 9], S44, 0xeb86d391); /* 64 */ + + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + + /* Zeroize sensitive information. */ + memset ((POINTER)x, 0, sizeof (x)); +} + diff --git a/modules/crypto/rc4/CVS/Entries b/modules/crypto/rc4/CVS/Entries new file mode 100644 index 0000000..de9b704 --- /dev/null +++ b/modules/crypto/rc4/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.4.1/Sun Nov 26 21:06:02 2006//Tb_zer0 +/rc4.c/1.2.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/rc4.h/1.2.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +D diff --git a/modules/crypto/rc4/CVS/Repository b/modules/crypto/rc4/CVS/Repository new file mode 100644 index 0000000..dd1e0e3 --- /dev/null +++ b/modules/crypto/rc4/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/crypto/rc4 diff --git a/modules/crypto/rc4/CVS/Root b/modules/crypto/rc4/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/crypto/rc4/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/crypto/rc4/CVS/Tag b/modules/crypto/rc4/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/crypto/rc4/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/crypto/rc4/CVS/Template b/modules/crypto/rc4/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/crypto/rc4/Makefile b/modules/crypto/rc4/Makefile new file mode 100644 index 0000000..c7eacd7 --- /dev/null +++ b/modules/crypto/rc4/Makefile @@ -0,0 +1,6 @@ +TARGET = rc4 + +# List C source files here. (C dependencies are automatically generated.) +SRC = rc4.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/crypto/rc4/rc4.c b/modules/crypto/rc4/rc4.c new file mode 100644 index 0000000..38b82f0 --- /dev/null +++ b/modules/crypto/rc4/rc4.c @@ -0,0 +1,93 @@ +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Inspired by the ARC4 implementation by Christophe Devine + * The original licence is below + * Implementation for RC4 + */ + +/** \file rc4.c + * \brief Implementation for the RC4 module. + * + * \todo Test the module. + * + * \test No tests for the moment. + * + * This module provides RC4 cryptographic functions. + */ + +/* + * An implementation of the ARC4 algorithm + * + * Copyright (C) 2001-2003 Christophe Devine + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <aversive.h> +#include "rc4.h" + +struct rc4_state s; + + + +void rc4_init(uint8_t *key, uint8_t length ) +{ + uint8_t i, j, k, a; + uint8_t * m; + + s.x = 0; + s.y = 0; + m = s.m; + + i=0; + m[i] = i; + for( i = 1; i !=0 ; i++ ) + { + m[i] = i; + } + + j = k = 0; + + + i=0; + a = m[i]; + j = (uint8_t) ( j + a + key[k] ); + m[i] = m[j]; m[j] = a; + if( ++k >= length ) k = 0; + + for( i = 1; i != 0 ; i++ ) + { + a = m[i]; + j = (uint8_t) ( j + a + key[k] ); + m[i] = m[j]; m[j] = a; + if( ++k >= length ) k = 0; + } +} + + + +uint8_t rc4_crypt_char(uint8_t data) +{ + uint8_t a, b; + + s.x = (uint8_t) ( s.x + 1 ); + a = s.m[s.x]; + s.y = (uint8_t) ( s.y + a ); + s.m[s.x] = b = s.m[s.y]; + s.m[s.y] = a; + data ^= s.m[(uint8_t) ( a + b )]; + + return data; +} + diff --git a/modules/crypto/rc4/rc4.h b/modules/crypto/rc4/rc4.h new file mode 100644 index 0000000..35330c2 --- /dev/null +++ b/modules/crypto/rc4/rc4.h @@ -0,0 +1,51 @@ +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Inspired by the ARC4 interface by Christophe Devine + * The original licence is below + * Interface for RC4 + */ + +/** \file rc4.c + * \brief Interface for the RC4 module. + * + * \todo Test the module. + * + * \test No tests for the moment. + * + * This module provides RC4 cryptographic functions. + */ + +/* + * An implementation of the ARC4 algorithm + * + * Copyright (C) 2001-2003 Christophe Devine + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _RC4_H +#define _RC4_H + +#include <aversive.h> + +struct rc4_state +{ + uint8_t x, y; + uint8_t m[256]; +}; + +void rc4_init( uint8_t *key, uint8_t length ); +uint8_t rc4_crypt_char(uint8_t data); + +#endif /* rc4.h */ diff --git a/modules/crypto/test/.config b/modules/crypto/test/.config new file mode 100644 index 0000000..8c5684c --- /dev/null +++ b/modules/crypto/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +CONFIG_MODULE_AES=y +CONFIG_MODULE_AES_CTR=y +CONFIG_MODULE_MD5=y +CONFIG_MODULE_MD5_HMAC=y +CONFIG_MODULE_RC4=y + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/crypto/test/CVS/Entries b/modules/crypto/test/CVS/Entries new file mode 100644 index 0000000..f7c4d60 --- /dev/null +++ b/modules/crypto/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.2.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.4.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/error_config.h/1.1.4.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/main.c/1.3.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/uart_config.h/1.1.4.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D diff --git a/modules/crypto/test/CVS/Repository b/modules/crypto/test/CVS/Repository new file mode 100644 index 0000000..d179ee3 --- /dev/null +++ b/modules/crypto/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/crypto/test diff --git a/modules/crypto/test/CVS/Root b/modules/crypto/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/crypto/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/crypto/test/CVS/Tag b/modules/crypto/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/crypto/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/crypto/test/CVS/Template b/modules/crypto/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/crypto/test/Makefile b/modules/crypto/test/Makefile new file mode 100644 index 0000000..c52ca9c --- /dev/null +++ b/modules/crypto/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/crypto/test/error_config.h b/modules/crypto/test/error_config.h new file mode 100644 index 0000000..e317b48 --- /dev/null +++ b/modules/crypto/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.4.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/crypto/test/main.c b/modules/crypto/test/main.c new file mode 100644 index 0000000..4262d79 --- /dev/null +++ b/modules/crypto/test/main.c @@ -0,0 +1,253 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.3.4.2 2007-05-23 17:18:12 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <uart.h> +#include <aversive.h> +#include <aversive/wait.h> + +#include "md5.h" +#include "aes_locl.h" +#include "aes.h" +#include "hmac_md5.h" + +#include <rc4.h> +#include <stdio.h> +#include <string.h> + +#define SKEY_BINKEY_SIZE 8 + + + + +/*test crypto*/ +unsigned char text_in[] = "666Doyourecognizethisnumber?Thisisthenumberofthebeast4567890abcd"; +unsigned char text_im[64]; +unsigned char text_out[64]; +unsigned char my_key[] = "ThisIsMySecret!!AndTheRestOfdata"; + + +unsigned char test_hmac_md5_key[] = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"; +unsigned char test_hmac_md5_data[] = "Hi There"; + +unsigned char test_aes_ctr_key[] = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"; +unsigned char test_aes_counterblock[] = "\x00\x00\x00\x00\x00\x00\x00\x00"; +unsigned char test_aes_text[] = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789aa"; +unsigned long test_aes_Nonce = 0x30; + + + + +/* + * ARC4 tests vectors from OpenSSL (crypto/rc4/rc4test.c) + */ + +void rc4_crypt(unsigned char *data, int length ) +{ + int i; + + for (i=0 ; i<length ; i++) + data[i] = rc4_crypt_char(data[i]); +} + + +static unsigned char rc4_keys[7][30]={ + {8,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef}, + {8,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef}, + {8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, + {4,0xef,0x01,0x23,0x45}, + {8,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef}, + {4,0xef,0x01,0x23,0x45}, + }; + +static unsigned char rc4_data_len[7]={8,8,8,20,28,10}; +static unsigned char rc4_data[7][30]={ + {0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef,0xff}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xff}, + {0x12,0x34,0x56,0x78,0x9A,0xBC,0xDE,0xF0, + 0x12,0x34,0x56,0x78,0x9A,0xBC,0xDE,0xF0, + 0x12,0x34,0x56,0x78,0x9A,0xBC,0xDE,0xF0, + 0x12,0x34,0x56,0x78,0xff}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff}, + {0}, + }; + +static unsigned char rc4_output[7][30]={ + {0x75,0xb7,0x87,0x80,0x99,0xe0,0xc5,0x96,0x00}, + {0x74,0x94,0xc2,0xe7,0x10,0x4b,0x08,0x79,0x00}, + {0xde,0x18,0x89,0x41,0xa3,0x37,0x5d,0x3a,0x00}, + {0xd6,0xa1,0x41,0xa7,0xec,0x3c,0x38,0xdf, + 0xbd,0x61,0x5a,0x11,0x62,0xe1,0xc7,0xba, + 0x36,0xb6,0x78,0x58,0x00}, + {0x66,0xa0,0x94,0x9f,0x8a,0xf7,0xd6,0x89, + 0x1f,0x7f,0x83,0x2b,0xa8,0x33,0xc0,0x0c, + 0x89,0x2e,0xbe,0x30,0x14,0x3c,0xe2,0x87, + 0x40,0x01,0x1e,0xcf,0x00}, + {0xd6,0xa1,0x41,0xa7,0xec,0x3c,0x38,0xdf,0xbd,0x61,0x00}, + {0}, + }; + +#if 0 +void dump_hex(unsigned char* in, unsigned int len) +{ + unsigned int i; + printf("[__\n"); + for (i=0;i<len;i++) { + if (i && !(i%16)) + printf("\n"); + printf("%.2X ", in[i]&0xFF); + } + printf("\n__]\n"); +} +#endif + +int key_len = 128; +int main(void) +{ + MD5_CTX h1; + unsigned char out[32]; + unsigned char text[16]; + AES_KEY key; + + unsigned char counter[AES_BLOCK_SIZE] = {0}; + unsigned char ecount_buf[AES_BLOCK_SIZE] = {0}; + unsigned int num = 0; + int i; + + uint8_t rc4_buffer[30]; + +#ifndef HOST_VERSION + /* UART */ + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + + sei(); +#endif + + /************ TEST RC4 */ + + for( i = 0; i < 6; i++ ) { + printf( " Test %d ", i + 1 ); + + memcpy( rc4_buffer, rc4_data[i], rc4_data_len[i] ); + + rc4_init( &rc4_keys[i][1], rc4_keys[i][0] ); + rc4_crypt( rc4_buffer, rc4_data_len[i] ); + + if( memcmp( rc4_buffer, rc4_output[i], rc4_data_len[i] ) ) { + printf( "RC4 failed!\n" ); + } + else { + printf( "RC4 test passed.\n" ); + } + } + + + memset(my_key, 0, 16); + strcpy((char*)my_key, "toto"); + + + + /*TEST HASH MD5*/ + MD5Init(&h1); + MD5Update(&h1, text_in, 64); + MD5Update(&h1, my_key, 32); + MD5Final(out, &h1); + + if (memcmp(out,"\xB8\x65\xA8\x46\xFC\x9F\x81\xFC\x4B\x98\x73\x4B\xAB\x1D\x4E\x65",16)) + printf( "Hash MD5 failed!\n" ); + else + printf( "Hash MD5 passed\n" ); + + + + + + /*TEST AES ENCRYPT*/ + AES_set_encrypt_key(my_key, key_len, &key); + AES_encrypt(text_in, out, &key); + if (memcmp(out,"\x7F\xA0\x88\xA5\xDB\x57\xE8\x63\x44\x35\xF6\xF5\x7F\xE6\x4A\xA1",16)) + printf( "AES encrypt failed!\n" ); + else + printf( "AES encrypt passed\n" ); + + + /*TEST AES DECRYPT*/ + AES_set_decrypt_key(my_key, key_len, &key); + AES_decrypt(out, text, &key); + if (memcmp(text,"\x36\x36\x36\x44\x6F\x79\x6F\x75\x72\x65\x63\x6F\x67\x6E\x69\x7A",16)) + printf( "AES decrypt failed!\n" ); + else + printf( "AES decrypt passed\n" ); + + + + /*TEST AES MODE CTR ENCRYPT*/ + memset(counter, 0, AES_BLOCK_SIZE); + memset(ecount_buf, 0, AES_BLOCK_SIZE); + num = 0; + AES_set_encrypt_key(test_aes_ctr_key, key_len, &key); + for (i=0;i<sizeof(test_aes_text)-1;i++) + AES_ctr128_encrypt(&test_aes_text[i], &text_im[i], 1, &key,counter,ecount_buf,&num); + if (memcmp(text_im, "\x07\x8B\x28\xB0\x8A\xEC\x4B\x53\xE1\x26\x91\x35\xA7\x5A\x44\x5E" + "\x09\xF9\xBE\x65\x6B\xB9\x04\xAC\x9E\xF7\x6F\x63\xFD\xB1\x11\x26" + "\xF2\xF8\x7D\x6B\x95\xC7\xF2\xB2\x01\xFD\xBD\x24\x20\x6D\xFC\xEB" + "\xCD\x38\xEC\x77\xBC\xCA\x84\xB5\x63\x4E\x4E\x82\x1E\x9E\x72\x77", 64)) + printf( "AES counter encrypt failed!\n" ); + else + printf( "AES counter encrypt passed\n" ); + + + /*TEST AES MODE CTR DECRYPT*/ + memset(counter, 0, AES_BLOCK_SIZE); + memset(ecount_buf, 0, AES_BLOCK_SIZE); + num=0; + AES_set_encrypt_key(test_aes_ctr_key, key_len, &key); + for (i=0;i<64;i++) + AES_ctr128_encrypt(&text_im[i], &text_out[i], 1, &key,counter,ecount_buf,&num); + if (memcmp(text_out, test_aes_text, 64)) + printf( "AES counter encrypt failed!\n" ); + else + printf( "AES counter encrypt passed\n" ); + + + /*TEST HASH MAC MD5 rfc2104*/ + /*RESULT 0x9294727a3638bb1c13f48ef8158bfc9d*/ + HMAC_MD5(out, test_hmac_md5_data, test_hmac_md5_key, 8, 16); + if (memcmp(out,"\x92\x94\x72\x7A\x36\x38\xBB\x1C\x13\xF4\x8E\xF8\x15\x8B\xFC\x9D", 16)) + printf( "AES counter encrypt failed!\n" ); + else + printf( "AES counter encrypt passed\n" ); + + printf( "End\n"); + while(1); + + return 0; +} + diff --git a/modules/crypto/test/uart_config.h b/modules/crypto/test/uart_config.h new file mode 100644 index 0000000..3c83c3c --- /dev/null +++ b/modules/crypto/test/uart_config.h @@ -0,0 +1,114 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.4.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + + + + +/* + * UART1 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 0 +//#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 4 +#define UART1_TX_FIFO_SIZE 16 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + + + +#endif + diff --git a/modules/debug/CVS/Entries b/modules/debug/CVS/Entries new file mode 100644 index 0000000..fc45682 --- /dev/null +++ b/modules/debug/CVS/Entries @@ -0,0 +1,2 @@ +D/diagnostic//// +D/error//// diff --git a/modules/debug/CVS/Repository b/modules/debug/CVS/Repository new file mode 100644 index 0000000..56759eb --- /dev/null +++ b/modules/debug/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug diff --git a/modules/debug/CVS/Root b/modules/debug/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/CVS/Tag b/modules/debug/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/CVS/Template b/modules/debug/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/diagnostic/CVS/Entries b/modules/debug/diagnostic/CVS/Entries new file mode 100644 index 0000000..05a1a65 --- /dev/null +++ b/modules/debug/diagnostic/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.2.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/diagnostic.h/1.6.4.2/Fri May 9 08:23:52 2008//Tb_zer0 +/int_show.c/1.6.10.3/Fri May 9 08:23:52 2008//Tb_zer0 +/stack_space.c/1.7.4.3/Fri May 9 08:23:52 2008//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/debug/diagnostic/CVS/Repository b/modules/debug/diagnostic/CVS/Repository new file mode 100644 index 0000000..31fa813 --- /dev/null +++ b/modules/debug/diagnostic/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug/diagnostic diff --git a/modules/debug/diagnostic/CVS/Root b/modules/debug/diagnostic/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/diagnostic/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/diagnostic/CVS/Tag b/modules/debug/diagnostic/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/diagnostic/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/diagnostic/CVS/Template b/modules/debug/diagnostic/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/diagnostic/Makefile b/modules/debug/diagnostic/Makefile new file mode 100644 index 0000000..c51d363 --- /dev/null +++ b/modules/debug/diagnostic/Makefile @@ -0,0 +1,7 @@ +TARGET = diagnostic + +# List C source files here. (C dependencies are automatically generated.) +SRC = stack_space.c int_show.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk + diff --git a/modules/debug/diagnostic/config/CVS/Entries b/modules/debug/diagnostic/config/CVS/Entries new file mode 100644 index 0000000..3e5ca7b --- /dev/null +++ b/modules/debug/diagnostic/config/CVS/Entries @@ -0,0 +1,2 @@ +/diagnostic_config.h/1.1.10.2/Fri May 9 08:23:52 2008//Tb_zer0 +D diff --git a/modules/debug/diagnostic/config/CVS/Repository b/modules/debug/diagnostic/config/CVS/Repository new file mode 100644 index 0000000..37dc2e6 --- /dev/null +++ b/modules/debug/diagnostic/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug/diagnostic/config diff --git a/modules/debug/diagnostic/config/CVS/Root b/modules/debug/diagnostic/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/diagnostic/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/diagnostic/config/CVS/Tag b/modules/debug/diagnostic/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/diagnostic/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/diagnostic/config/CVS/Template b/modules/debug/diagnostic/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/diagnostic/config/diagnostic_config.h b/modules/debug/diagnostic/config/diagnostic_config.h new file mode 100644 index 0000000..5dbd68f --- /dev/null +++ b/modules/debug/diagnostic/config/diagnostic_config.h @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.1.10.2 2008-05-09 08:23:52 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +/* undefine it to disable this functionnality */ +#define INTERRUPT_SHOW_PORT PORTA +#define INTERRUPT_SHOW_BIT 3 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#define DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/modules/debug/diagnostic/diagnostic.h b/modules/debug/diagnostic/diagnostic.h new file mode 100644 index 0000000..9d40f23 --- /dev/null +++ b/modules/debug/diagnostic/diagnostic.h @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic.h,v 1.6.4.2 2008-05-09 08:23:52 zer0 Exp $ + * + */ + +#include <diagnostic_config.h> + + + +/** shows the interrupt cycles on an oscilloscope or a multimeter you + * can then measure the interrupt busy time of your device. this + * function is an infinite loop which has to be the main program, and + * will be interrupted. a port bit is needed as diagnostic interface + * with scope or multimeter. if you use a scope : freezing of the + * oscillation shows interrupt if you use a multimeter : voltage is + * proportionnal to idle time + * 0V >> 0% idle (always busy) + * Vcc/2 >> 100% idle (not interupted) + * be careful, you perhaps need a low pass filter for your voltmeter */ +extern void show_int_loop(void); + +/** This functuion allows to monitor the maximal stack space that was + * used since the last reset (peak value) you can then monitor the + * available space in your ram returns the minimal value of the free + * space left */ +extern uint16_t min_stack_space_available(void); + diff --git a/modules/debug/diagnostic/int_show.c b/modules/debug/diagnostic/int_show.c new file mode 100644 index 0000000..2fa617d --- /dev/null +++ b/modules/debug/diagnostic/int_show.c @@ -0,0 +1,56 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: int_show.c,v 1.6.10.3 2008-05-09 08:23:52 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive.h> +#include <diagnostic.h> + + +#ifdef INTERRUPT_SHOW_PORT + +/** this loop is to be used as main program if you have interrupts + * running and want to see how much time is consumed by the + * interrupts. you must then observe the test pin with an + * oscilloscope, or eventually a multimeter. as long as there are no + * interrupts, the test port will toggle at 50% rate. when an + * interrupt occurs, the port stops to toggle, and remain low. the + * space before the next impulsion is the int time (always one toggle + * between ints!) if you look whith a multimeter, the processor free + * time is proportinnal to the observed voltage. 0V corresponds to + * an always busy processor, while if you read Vcc/2 the processor is + * almost always free. */ +void show_int_loop(void) +{ + sbi(DDR(INTERRUPT_SHOW_PORT), INTERRUPT_SHOW_BIT); + + while(1) { + cbi(INTERRUPT_SHOW_PORT, INTERRUPT_SHOW_BIT); // port to 0 + + sei(); + nop(); // ints can only arrive there (on low level of probe pin) + cli(); + + sbi(INTERRUPT_SHOW_PORT, INTERRUPT_SHOW_BIT); // port to 1 + + nop(); // is there to equalize the duty cycle + } +} +#endif diff --git a/modules/debug/diagnostic/stack_space.c b/modules/debug/diagnostic/stack_space.c new file mode 100644 index 0000000..01ed904 --- /dev/null +++ b/modules/debug/diagnostic/stack_space.c @@ -0,0 +1,99 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: stack_space.c,v 1.7.4.3 2008-05-09 08:23:52 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive.h> + + +#include <diagnostic.h> + + +/** This diagnostical software fills the RAM with a mark, and counts + * how many of these marks are unmodified, in order to avaluate the + * min stack space available after code execution. You can then know + * how much your stack your program needed in a peak, without looking + * espacially when this peak arises. you see the minmal stack space + * left since the reset of the microcontroller. */ + +// call this function at the beginning of program +void fill_mem_with_mark(void) __attribute__ ((naked)) \ +__attribute__ ((section (".init1"))); + + +/** this functions fills the ram with a predefined pattern after a + * reset and BEFORE any other operation */ +void fill_mem_with_mark(void) +{ + register int i asm("r16"); + register int end asm("r18"); + + + // where is the beginning of the RAM memory ? +#ifdef DIAG_FILL_ENTIRE_RAM // fill entire RAM + asm( "ldi r16,lo8(__data_start)" ); + asm( "ldi r17,hi8(__data_start)" ); +#else // fill only stack and heap spaces + asm( "ldi r16,lo8(__heap_start)" ); + asm( "ldi r17,hi8(__heap_start)" ); +#endif + + // end of RAM + asm( "ldi r18,lo8(__stack)" ); + asm( "ldi r19,hi8(__stack)" ); + + // fill ram with the spacified pattern + for(; i< end ; i++) + * ( (volatile unsigned char* )(i) ) = MARK; + +} + + +uint16_t min_stack_space_available(void) +{ + register int i asm("r16"); + register int end asm("r18"); + uint16_t count , max; + + // where is the beginning of the stack space ? + asm( "ldi r16,lo8(__heap_start)" ); + asm( "ldi r17,hi8(__heap_start)" ); + // end of RAM + asm( "ldi r18,lo8(__stack)" ); + asm( "ldi r19,hi8(__stack)" ); + + /* the algorithm finds the size of the biggest zone filled + * with the mark, which is normally the stack space left */ + count = 0; + max = 0; + for(; i<end; i++) { + // = mark? + if (MARK == * ( (volatile unsigned char* )(i) )) { + // count + count ++; + if (count > max) + max = count; + } + else + count = 0; // reset counter + } + + return max; +} diff --git a/modules/debug/diagnostic/test/.config b/modules/debug/diagnostic/test/.config new file mode 100644 index 0000000..bd9ea47 --- /dev/null +++ b/modules/debug/diagnostic/test/.config @@ -0,0 +1,247 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +CONFIG_MCU_ATMEGA32=y +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=8000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +CONFIG_OPTM_3=y +# CONFIG_OPTM_S is not set +# CONFIG_MATH_LIB is not set +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +CONFIG_MODULE_DIAGNOSTIC=y +CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG=y +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/debug/diagnostic/test/CVS/Entries b/modules/debug/diagnostic/test/CVS/Entries new file mode 100644 index 0000000..e019b47 --- /dev/null +++ b/modules/debug/diagnostic/test/CVS/Entries @@ -0,0 +1,8 @@ +/.config/1.11.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/diagnostic_config.h/1.3.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/main.c/1.8.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/test_int_show.c/1.3.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/test_stack_size.c/1.3.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/uart_config.h/1.3.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D diff --git a/modules/debug/diagnostic/test/CVS/Repository b/modules/debug/diagnostic/test/CVS/Repository new file mode 100644 index 0000000..8e0fec3 --- /dev/null +++ b/modules/debug/diagnostic/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug/diagnostic/test diff --git a/modules/debug/diagnostic/test/CVS/Root b/modules/debug/diagnostic/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/diagnostic/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/diagnostic/test/CVS/Tag b/modules/debug/diagnostic/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/diagnostic/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/diagnostic/test/CVS/Template b/modules/debug/diagnostic/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/diagnostic/test/Makefile b/modules/debug/diagnostic/test/Makefile new file mode 100644 index 0000000..f2f2d70 --- /dev/null +++ b/modules/debug/diagnostic/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c test_int_show.c test_stack_size.c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/debug/diagnostic/test/diagnostic_config.h b/modules/debug/diagnostic/test/diagnostic_config.h new file mode 100644 index 0000000..3642f2a --- /dev/null +++ b/modules/debug/diagnostic/test/diagnostic_config.h @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.3.10.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +#define INTERRUPT_SHOW_PORT PORTC +#define INTERRUPT_SHOW_BIT 6 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#ifdef DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/modules/debug/diagnostic/test/main.c b/modules/debug/diagnostic/test/main.c new file mode 100644 index 0000000..f3f4857 --- /dev/null +++ b/modules/debug/diagnostic/test/main.c @@ -0,0 +1,45 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.8.4.2 2007-05-23 17:18:12 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive.h> + +extern int test_stack_size(void); +extern int test_int_show(void); + + + + +// change this value to test either the stack size utility or the int show one +//volatile uint8_t test_ss = 1; // stack size demo +volatile uint8_t test_ss = 0; // int show demo + +int main(void) +{ + + if (test_ss) + test_stack_size(); + else + test_int_show(); + + + return 0; +} diff --git a/modules/debug/diagnostic/test/test_int_show.c b/modules/debug/diagnostic/test/test_int_show.c new file mode 100644 index 0000000..d5ef558 --- /dev/null +++ b/modules/debug/diagnostic/test/test_int_show.c @@ -0,0 +1,88 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: test_int_show.c,v 1.3.4.2 2007-05-23 17:18:12 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive.h> + + +#include <uart.h> +#include <aversive/wait.h> +#include <stdio.h> + +#include <diagnostic.h> + +int delay = 0; +int charcount = 0; + +char buf[20] = "toto"; +int buf_index = 0; + + +void interrupt(void) +{ + + // introduces a delay + wait_4cyc(delay *4); + + + // increments the delay, and prepares the string to print + if(charcount-- == 0) + { + charcount = 200; + sprintf(buf, "\n%i", delay++); + buf_index = 0; + } + + // prints the string + if (buf[buf_index] == 0) + uart0_send(' '); + else + uart0_send(buf[buf_index++]); + +} + + + +int test_int_show(void) +{ + + // uart stuff + uart_init(); + sei(); + fdevopen(uart0_dev_send,NULL); + + // bonjour + printf("\nhello, we will now test the int_show function\n"); + printf("the counter shoud increment while you see the voltage decreasing on the pin\n"); + printf("this is due to increasing processor charge\n"); + + wait_ms(500); + + // should be replaced by the scheduler + uart0_register_tx_event((void *) interrupt); + + // start characters + printf("\n"); + + show_int_loop(); + + return 0; +} diff --git a/modules/debug/diagnostic/test/test_stack_size.c b/modules/debug/diagnostic/test/test_stack_size.c new file mode 100644 index 0000000..4b749f4 --- /dev/null +++ b/modules/debug/diagnostic/test/test_stack_size.c @@ -0,0 +1,70 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: test_stack_size.c,v 1.3.4.2 2007-05-23 17:18:12 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive.h> + + +#include <uart.h> +#include <aversive/wait.h> +#include <stdio.h> + +#include <diagnostic.h> + + + +// this functions calls itself and consumes stack every time +// the stack space indication should decrement every time +// when the stack is all consumed, the processor can do crazy things. +// most time it will reset +void recursive_call(void) +{ + volatile int stack_size; // volatile necessary to put variable on stack + + // printing the stacck space + stack_size = min_stack_space_available(); + printf("stack size : %i\n", stack_size); + + + wait_ms(50); + + // consuming stack space + recursive_call(); +} + + + +int test_stack_size(void) +{ + + // uart stuff + uart_init(); + sei(); + fdevopen(uart0_dev_send,NULL); + + // bonjour + printf("\n\nhello, I just reset !\nperhaps a lack of stack space\n"); + + // the beginning of the loop + recursive_call(); + + return 0; +} diff --git a/modules/debug/diagnostic/test/uart_config.h b/modules/debug/diagnostic/test/uart_config.h new file mode 100644 index 0000000..3029287 --- /dev/null +++ b/modules/debug/diagnostic/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.3.10.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/debug/error/CVS/Entries b/modules/debug/error/CVS/Entries new file mode 100644 index 0000000..98f7e45 --- /dev/null +++ b/modules/debug/error/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.1.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/error.c/1.10.4.3/Mon Dec 31 16:25:00 2007//Tb_zer0 +/error.h/1.11.4.3/Mon Dec 31 16:25:00 2007//Tb_zer0 +/general_errors.h/1.5.4.3/Fri Jan 23 23:54:15 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/debug/error/CVS/Repository b/modules/debug/error/CVS/Repository new file mode 100644 index 0000000..c39aff9 --- /dev/null +++ b/modules/debug/error/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug/error diff --git a/modules/debug/error/CVS/Root b/modules/debug/error/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/error/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/error/CVS/Tag b/modules/debug/error/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/error/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/error/CVS/Template b/modules/debug/error/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/error/Makefile b/modules/debug/error/Makefile new file mode 100644 index 0000000..3ea89d9 --- /dev/null +++ b/modules/debug/error/Makefile @@ -0,0 +1,7 @@ +TARGET = error + +# List C source files here. (C dependencies are automatically generated.) +SRC = error.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk + diff --git a/modules/debug/error/config/CVS/Entries b/modules/debug/error/config/CVS/Entries new file mode 100644 index 0000000..1c33a95 --- /dev/null +++ b/modules/debug/error/config/CVS/Entries @@ -0,0 +1,2 @@ +/error_config.h/1.4.6.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D diff --git a/modules/debug/error/config/CVS/Repository b/modules/debug/error/config/CVS/Repository new file mode 100644 index 0000000..edaf83b --- /dev/null +++ b/modules/debug/error/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug/error/config diff --git a/modules/debug/error/config/CVS/Root b/modules/debug/error/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/error/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/error/config/CVS/Tag b/modules/debug/error/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/error/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/error/config/CVS/Template b/modules/debug/error/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/error/config/error_config.h b/modules/debug/error/config/error_config.h new file mode 100644 index 0000000..2e1288a --- /dev/null +++ b/modules/debug/error/config/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.4.6.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/debug/error/error.c b/modules/debug/error/error.c new file mode 100644 index 0000000..c2cf970 --- /dev/null +++ b/modules/debug/error/error.c @@ -0,0 +1,110 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error.c,v 1.10.4.3 2007-12-31 16:25:00 zer0 Exp $ + * + */ + + +#include <string.h> + +#ifndef HOST_VERSION +#include <avr/io.h> +#endif + +#include <aversive.h> +#include <aversive/error.h> + +struct error_fct g_error_fct; + +/** All fcts pointers to NULL */ +void error_init(void) +{ + uint8_t flags; + IRQ_LOCK(flags); + memset(&g_error_fct, 0, sizeof(g_error_fct)); + IRQ_UNLOCK(flags); +} + + +struct error error_generate(uint8_t num, uint8_t severity, PGM_P t, + PGM_P f, uint16_t l) { + struct error e; + + e.err_num = num; + e.severity = severity; +#ifdef ERROR_DUMP_TEXTLOG + e.text = t; +#else + e.text = PSTR(""); +#endif +#ifdef ERROR_DUMP_FILE_LINE + e.file = f; + e.line = l; +#else + e.file = PSTR(""); + e.line = 0; +#endif + return e; +} + + +/** Register log function for EMERG level */ +void error_register_emerg(void (*f)(struct error *, ...)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_error_fct.emerg = f; + IRQ_UNLOCK(flags); +} + +/** Register log function for ERROR level */ +void error_register_error(void (*f)(struct error *, ...)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_error_fct.error = f; + IRQ_UNLOCK(flags); +} + +/** Register log function for WARNING level */ +void error_register_warning(void (*f)(struct error *, ...)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_error_fct.warning = f; + IRQ_UNLOCK(flags); +} + +/** Register log function for NOTICE level */ +void error_register_notice(void (*f)(struct error *, ...)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_error_fct.notice = f; + IRQ_UNLOCK(flags); +} + +/** Register log function for DEBUG level */ +void error_register_debug(void (*f)(struct error *, ...)) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_error_fct.debug = f; + IRQ_UNLOCK(flags); +} + diff --git a/modules/debug/error/error.h b/modules/debug/error/error.h new file mode 100644 index 0000000..b5e9074 --- /dev/null +++ b/modules/debug/error/error.h @@ -0,0 +1,140 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error.h,v 1.11.4.3 2007-12-31 16:25:00 zer0 Exp $ + * + */ + +#ifndef _ERROR_H_ +#define _ERROR_H_ + +#ifndef _AVERSIVE_ERROR_H_ +#error "Don't include <error.h>, include <aversive/error.h> instead" +#endif + +#include <aversive/pgmspace.h> +#include <aversive.h> +#include <general_errors.h> + +#include "error_config.h" + +#define ERROR_SEVERITY_EMERG 0 +#define ERROR_SEVERITY_ERROR 1 +#define ERROR_SEVERITY_WARNING 2 +#define ERROR_SEVERITY_NOTICE 3 +#define ERROR_SEVERITY_DEBUG 4 + +/** The error structure, which is given as a parameter in log funcs */ +struct error { + uint8_t err_num; + uint8_t severity; + PGM_P text; + PGM_P file; + uint16_t line; +}; + + +struct error_fct { + void (*emerg)(struct error *, ...); + void (*error)(struct error *, ...); + void (*warning)(struct error *, ...); + void (*notice)(struct error *, ...); + void (*debug)(struct error *, ...); +} ; + +extern struct error_fct g_error_fct; + + +struct error error_generate(uint8_t num, uint8_t severity, PGM_P t, PGM_P f, uint16_t l); + +/** Register log function for EMERG level */ +void error_register_emerg(void (*f)(struct error *, ...)); + +/** Register log function for ERROR level */ +void error_register_error(void (*f)(struct error *, ...)); + +/** Register log function for WARNING level */ +void error_register_warning(void (*f)(struct error *, ...)); + +/** Register log function for NOTICE level */ +void error_register_notice(void (*f)(struct error *, ...)); + +/** Register log function for DEBUG level */ +void error_register_debug(void (*f)(struct error *, ...)); + + + + +/** Call this macro to log EMERG events */ +#define EMERG(num, text, ...) do { \ + if(g_error_fct.emerg) { \ + struct error e = error_generate(num, ERROR_SEVERITY_EMERG, \ + PSTR(text), \ + PSTR(__FILE__),\ + __LINE__); \ + g_error_fct.emerg(&e, ##__VA_ARGS__); \ + } \ +} while(0) + +/** Call this macro to log ERROR events */ +#define ERROR(num, text, ...) do { \ + if(g_error_fct.error) { \ + struct error e = error_generate(num, ERROR_SEVERITY_ERROR, \ + PSTR(text), \ + PSTR(__FILE__),\ + __LINE__); \ + g_error_fct.error(&e, ##__VA_ARGS__); \ + } \ +} while(0) + +/** Call this macro to log WARNING events */ +#define WARNING(num, text, ...) do { \ + if(g_error_fct.warning) { \ + struct error e = error_generate(num, ERROR_SEVERITY_WARNING, \ + PSTR(text), \ + PSTR(__FILE__),\ + __LINE__); \ + g_error_fct.warning(&e, ##__VA_ARGS__); \ + } \ +} while(0) + +/** Call this macro to log NOTICE events */ +#define NOTICE(num, text, ...) do { \ + if(g_error_fct.notice) { \ + struct error e = error_generate(num, ERROR_SEVERITY_NOTICE, \ + PSTR(text), \ + PSTR(__FILE__),\ + __LINE__); \ + g_error_fct.notice(&e, ##__VA_ARGS__); \ + } \ +} while(0) + +/** Call this macro to log DEBUG events */ +#define DEBUG(num, text, ...) do { \ + if(g_error_fct.debug) { \ + struct error e = error_generate(num, ERROR_SEVERITY_DEBUG, \ + PSTR(text), \ + PSTR(__FILE__),\ + __LINE__); \ + g_error_fct.debug(&e, ##__VA_ARGS__); \ + } \ +} while(0) + + + + +#endif /* _ERROR_H_ */ diff --git a/modules/debug/error/general_errors.h b/modules/debug/error/general_errors.h new file mode 100644 index 0000000..96e7173 --- /dev/null +++ b/modules/debug/error/general_errors.h @@ -0,0 +1,80 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: general_errors.h,v 1.5.4.3 2009-01-23 23:54:15 zer0 Exp $ + * + */ + + +/** + * these are general errors. + */ + +/* Not module specific */ + +/* Operation not permitted */ +#define EPERM_COMMENT "Operation not permitted" + +/* No such file or directory */ +#define ENOENT_COMMENT "No such file or directory" + +/* I/O error */ +#define EIO_COMMENT "I/O error" + +/* No such device or address */ +#define ENXIO_COMMENT "No such device or address" + +/* Argument list too long */ +#define E2BIG_COMMENT "Argument list too long" + +/* Try again */ +#define EAGAIN_COMMENT "Try again" + +/* Out of memory */ +#define ENOMEM_COMMENT "Out of memory" + +/* Bad address */ +#define EFAULT_COMMENT "Bad address" + +/* Device or resource busy */ +#define EBUSY_COMMENT "Device or resource busy" + +/* Invalid argument */ +#define EINVAL_COMMENT "Invalid argument" + +/* Unkwow error */ +#define EUNKNOW_COMMENT "Unkwow error" + + +/* Module specific, from 129 to 192 */ + +#define E_UART 129 +#define E_ROBOT_SYSTEM 130 +#define E_MULTISERVO 131 +#define E_TRAJECTORY 132 +#define E_I2C 133 +#define E_BLOCKING_DETECTION_MANAGER 134 +#define E_OA 135 +#define E_SPI 136 +#define E_CC2420 137 +#define E_TIME_EXT 138 + +/* ... etc TBD */ + +/* User specific, from > 192 */ + +/* defined in user app */ diff --git a/modules/debug/error/test/.config b/modules/debug/error/test/.config new file mode 100644 index 0000000..16dd42f --- /dev/null +++ b/modules/debug/error/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/debug/error/test/CVS/Entries b/modules/debug/error/test/CVS/Entries new file mode 100644 index 0000000..37a2b93 --- /dev/null +++ b/modules/debug/error/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.8.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/error_config.h/1.4.6.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/main.c/1.6.4.2/Wed May 23 17:18:12 2007//Tb_zer0 +/uart_config.h/1.4.6.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D diff --git a/modules/debug/error/test/CVS/Repository b/modules/debug/error/test/CVS/Repository new file mode 100644 index 0000000..46fb5c4 --- /dev/null +++ b/modules/debug/error/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/debug/error/test diff --git a/modules/debug/error/test/CVS/Root b/modules/debug/error/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/debug/error/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/debug/error/test/CVS/Tag b/modules/debug/error/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/debug/error/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/debug/error/test/CVS/Template b/modules/debug/error/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/debug/error/test/Makefile b/modules/debug/error/test/Makefile new file mode 100644 index 0000000..3f8134f --- /dev/null +++ b/modules/debug/error/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/debug/error/test/error_config.h b/modules/debug/error/test/error_config.h new file mode 100644 index 0000000..2e1288a --- /dev/null +++ b/modules/debug/error/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.4.6.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/debug/error/test/main.c b/modules/debug/error/test/main.c new file mode 100644 index 0000000..914f9dc --- /dev/null +++ b/modules/debug/error/test/main.c @@ -0,0 +1,76 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.6.4.2 2007-05-23 17:18:12 zer0 Exp $ + * + */ + +#include <aversive.h> + +#include <uart.h> +#include <aversive/wait.h> +#include <stdio.h> +#include <stdarg.h> + +#include <aversive/error.h> +#include <aversive/pgmspace.h> + + +void mylog(struct error * e, ...) +{ + va_list ap; + + va_start(ap, e); + printf_P(PSTR("[%d]: E%d "), e->severity, e->err_num); + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR(", ")); + printf_P(e->file); + printf_P(PSTR(", L%d\n"), e->line); + va_end(ap); +} + +int main(void) +{ +#ifndef HOST_VERSION + /* uart stuff */ + uart_init(); + sei(); + fdevopen(uart0_dev_send,NULL); +#endif + + /* hello */ + printf_P(PSTR("test error module\n")); + printf("%d\n",sizeof(va_list)); + + /* don't display anything */ + ERROR(54, "pouet"); + + error_register_emerg(mylog); + error_register_error(mylog); + + EMERG(3, "this is an emerg log"); + EMERG(3, "this is an emerg log with param %d", 453); + ERROR(54, "this is another log, level = error"); + + /* don't display it, fcts are not registered */ + WARNING(4, "not displayed"); + NOTICE(5, "not displayed"); + DEBUG(6, "not displayed"); + + while(1); + return 0; +} diff --git a/modules/debug/error/test/uart_config.h b/modules/debug/error/test/uart_config.h new file mode 100644 index 0000000..ed67beb --- /dev/null +++ b/modules/debug/error/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.4.6.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/CVS/Entries b/modules/devices/CVS/Entries new file mode 100644 index 0000000..e4e20d3 --- /dev/null +++ b/modules/devices/CVS/Entries @@ -0,0 +1,7 @@ +D/brushless_motors//// +D/control_system//// +D/encoders//// +D/ihm//// +D/radio//// +D/robot//// +D/servo//// diff --git a/modules/devices/CVS/Repository b/modules/devices/CVS/Repository new file mode 100644 index 0000000..dcc91d6 --- /dev/null +++ b/modules/devices/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices diff --git a/modules/devices/CVS/Root b/modules/devices/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/CVS/Tag b/modules/devices/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/CVS/Template b/modules/devices/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/CVS/Entries b/modules/devices/brushless_motors/CVS/Entries new file mode 100644 index 0000000..5da8fae --- /dev/null +++ b/modules/devices/brushless_motors/CVS/Entries @@ -0,0 +1,2 @@ +D/brushless_3phase_digital_hall//// +D/brushless_3phase_digital_hall_double//// diff --git a/modules/devices/brushless_motors/CVS/Repository b/modules/devices/brushless_motors/CVS/Repository new file mode 100644 index 0000000..57c82d7 --- /dev/null +++ b/modules/devices/brushless_motors/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors diff --git a/modules/devices/brushless_motors/CVS/Root b/modules/devices/brushless_motors/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/CVS/Tag b/modules/devices/brushless_motors/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/CVS/Template b/modules/devices/brushless_motors/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Entries b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Entries new file mode 100644 index 0000000..8864e4c --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/brushless.c/1.2.2.3/Wed May 23 17:18:12 2007//Tb_zer0 +/brushless.h/1.2.2.3/Wed May 23 17:18:12 2007//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Repository b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Repository new file mode 100644 index 0000000..76db920 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors/brushless_3phase_digital_hall diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Root b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Tag b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Template b/modules/devices/brushless_motors/brushless_3phase_digital_hall/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/Makefile b/modules/devices/brushless_motors/brushless_3phase_digital_hall/Makefile new file mode 100644 index 0000000..80100b9 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/Makefile @@ -0,0 +1,9 @@ +TARGET = brushless_3phase_digital_hall + + +# List C source files here. (C dependencies are automatically generated.) +SRC = brushless.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/brushless.c b/modules/devices/brushless_motors/brushless_3phase_digital_hall/brushless.c new file mode 100644 index 0000000..3a78aab --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/brushless.c @@ -0,0 +1,543 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless.c,v 1.2.2.3 2007-05-23 17:18:12 zer0 Exp $ + * + */ + + +/** This module handles a brushless motor with 3 phases, wired in triangle or star. + 3 hall sensors are used wih digital output. + 3 PWM are outputted, these MUST be synchronized !! + + The control value is a voltage. This can be assimiled to a torque at low speeds. + + There is a possibility of also of limiting the speed. This is accomplished by slowing down the sampling speed of the + sensors. Doing this,the motor effective torque is reduced when the speed is such that the sensor actuation + approaches the sampling frequency. + use this technique carefully, because the motor has already his full voltage applied, an can dissipate a lot of energy, especially at low speeds. + + + there is no external manage function, as the manage is done at the PWM speed (overflow of one PWM timer is used.) + This function is speed optimized. +*/ + + +/** ceci est une commande de moteur brushless triphase en etoile, + utilisant 3 capteurs a effet hall digitaux. + En sortie on a 3 PWM (il est necessaire de les synchroniser !) + + pour le commande en couple, on joue sur les pwm (pseudo-couple) + et pour la commande en vitesse, on joue sur la frequence de rafraichissement des phases + par rapport aux capteurs. + cette astuce simple permet de faire facilement une consigne de vitesse + (pas besoin d'asservissement) + mais des vitesses faibles sont saccadees.*/ + + +#include <avr/io.h> +#include <avr/signal.h> + + +#include <pwm.h> + +#include <aversive.h> + + +#include <avr/pgmspace.h> + +#include <brushless.h> + +#include "brushless_3phase_digital_hall_config.h" + +#if (BRUSHLESS_TYPE != BRUSHLESS_DIGITAL) +#error mauvais fichier de config "brushless_config.h" +#endif + + + + +/** calculating the event to use, based on PWM definition of the phase 1 + The two motors function on the same timer! */ + +#if (BRUSHLESS_TIMER == 0) +#define INIT_INT() sbi(TIMSK, TOIE0) +#define INT SIG_OVERFLOW0 + +#elif (BRUSHLESS_TIMER == 1) +#define INIT_INT() sbi(TIMSK, TOIE1) +#define INT SIG_OVERFLOW1 + +#elif (BRUSHLESS_TIMER == 2) +#define INIT_INT() sbi(TIMSK, TOIE2) +#define INT SIG_OVERFLOW2 + +#elif (BRUSHLESS_TIMER == 3) +#define INIT_INT() sbi(ETIMSK, TOIE3) /* extended timsk for this one ! */ +#define INT SIG_OVERFLOW3 + +#endif + + +/** 2 LUT tables: + sensors > relative electric angle + sensors > phase information + + + decimal value : 0 1 2 3 4 5 6 7 + sensors state : 000 001 010 011 100 101 110 111 + is this a valid state? : NO yes yes yes yes yes yes NO */ + +// conversion to electrical angle +// modulo 1 electrical turn. +// in RAM for faster acess +const int8_t g_brushless_angle[]= {0, 1, 5, 0, 3, 2, 4, 0}; + +// in progmem for ram optimization +const int8_t PROGMEM g_brushless_phase1[]= {0, 1, -1, 0, 0, 1, -1, 0}; +const int8_t PROGMEM g_brushless_phase2[]= {0, 0, 1, 1, -1, -1, 0, 0}; +const int8_t PROGMEM g_brushless_phase3[]= {0, -1, 0, -1, 1, 0, 1, 0}; + +// the zeroes in the phase give a 0 output if there are no sensors connected, or another problem like this. +// it could be a good idea to enable the pull up resistors ! + + +void brushless_speed_update_manage(void * dummy); + +// mem of previous position for speed calc. +brushless_position g_brushless_0_position_previous; + + +// memory for current measurements +brushless g_brushless_0; + + +// pseudo torque to use +brushless_torque g_brushless_0_torque; + + +// given with speed limit +uint16_t g_brushless_0_pwm_divider = 1; + + + +// function pointer definition for event +void (*periodic_event_0)(brushless) = 0; //NULL; + + + +/** This function is made of 5 parts : + - pwm divsion : gives a master frequency for the next parts, by dividing the PWM frequency (can also be set to 1) + - sensors acquisition : done every time + - angle update : done when there is a change in sensor state since last angle update + - PWM update : done only every x (every g_brushless_recurrence -1) and skipped if there is no change since last pwm update + - speed update : done only every y () this updates the speed + + + Typically, PWM update is slower than angle update, in order to not skip angle counting. + + + Typically, speed update is a lot slower than angle update in order to have a speed that is sampled at a correct rate. + This event can trigger an action, this is especially used if you have a servo control. + + + examples for a pretty fast motor : + - PWM at 30 kHz + - angle update at 10 kHz + - PWM update at 5 kHz or lower, depending on speed setting + - speed update at 100 Hz + +*/ + + +volatile uint8_t pwm_division_timer asm("pwm_div") = 1; +volatile uint8_t interrupt_pwm; +volatile uint8_t pwm_previous_sensors_0 = 0; // previous state of sensors for PWM update + + + +#ifdef ASMHEADER +/** Here the division is done in ASM before saving a lot of registers on the stack. + This gains a lot of time when using a 8 bit timer without prescale + (one interrupt every 256 clocks !!) + */ + +void INT (void) __attribute__ ((naked)); // no register save, and no exit !! +SIGNAL(INT) +{ +asm volatile( + +/* division, done very early, for optimization */ +"PUSH R1 \n\t" +"IN R1,0x3F \n\t" +"PUSH R1 \n\t" +"LDS R1,pwm_div \n\t" +"DEC R1 \n\t" +"BREQ continue \n\t" +"STS pwm_div,R1 \n\t" /*we store only if negative. if positive, it will be done in the C code*/ + + +/* early go out of int */ +"go_out: \n\t" +"POP R1 \n\t" +"OUT 0x3F,R1 \n\t" +"POP R1 \n\t" +"RETI \n\t" + +/* restoring context, double work with the following interrupt function, but no other way */ +"continue: \n\t" +"POP R1 \n\t" +"OUT 0x3F,R1 \n\t" +"POP R1 \n\t" + +::); + +} // no jump, we pass implicitely. +SIGNAL(DUMMY) // we hope that the two are after each other !! (it is always the case with GCC) +{ + +#else // the same code in C +SIGNAL(INT) +{ +/** PWM division part */ +if (--pwm_division_timer != 0) + return; + + +#endif //common code + + + pwm_division_timer = BRUSHLESS_PWM_TO_SAMPLE_DIVISOR; + // end of frequency division state machine + + + + /** various definitions */ + + // angle update variables + static int8_t angle_electrical_previous_0 = 0; // previous electrical angle + + static uint8_t angle_previous_sensors_0 = 0; // previous state of sensors for angle calc + + int8_t angle_electrical, diff; + uint8_t sensors_0 = 0; + + + // pwm update variables + static uint16_t pwm_update_timer_0 = 1; + + + + { + /*********** Motor 0 angle update **********/ + + + /** sensors acquisition part + extraction of the sensor signals, and built up of a 3 bit ordened byte + this is done every time */ + + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_1_PORT),BRUSHLESS_0_SENSOR_1_BIT)) + sensors_0 +=1; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_2_PORT),BRUSHLESS_0_SENSOR_2_BIT)) + sensors_0 +=2; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_3_PORT),BRUSHLESS_0_SENSOR_3_BIT)) + sensors_0 +=4; + + #ifdef BRUSHLESS_0_SENSORS_INVERT + sensors_0 = (~ sensors_0) & 0x7; // inversion of the sensors + #endif + + + + /** the angle update part */ + + #ifndef LOADTEST + // skipping if no change + if(sensors_0 != angle_previous_sensors_0) + #endif + { + angle_previous_sensors_0 = sensors_0; + + + angle_electrical = g_brushless_angle[sensors_0]; // calculate electrical angle + + diff = angle_electrical - angle_electrical_previous_0; // convert to angle delta + angle_electrical_previous_0 = angle_electrical; // store for next time + + // clipping + if (diff > 3) + diff -=6; + else if (diff < -3) + diff +=6; + + #ifndef BRUSHLESS_0_INVERT + diff *= -1; // inversion of the angle reading + #endif + + // update of the absolute angle with the delta + //IRQ_LOCK(); // not necessary coz we enable ints only after + g_brushless_0.position -= (brushless_position)diff * BRUSHLESS_POSITION_PRECISION; + //IRQ_UNLOCK(); + + } + + /*********** END Motor 0 angle update **********/ + } + + + if(interrupt_pwm ==0) + { + interrupt_pwm =1; + + sei(); + + /*********** Motor 0 PWM update **********/ + + // frequency division state machine + if (--pwm_update_timer_0 == 0) + { + uint8_t flags; + IRQ_LOCK(flags); + pwm_update_timer_0 = g_brushless_0_pwm_divider; // protected against glitches + IRQ_UNLOCK(flags); + // end of frequency division state machine + + #ifndef LOADTEST + // skipping if same as last time + if(sensors_0 != pwm_previous_sensors_0) + #endif + { + brushless_torque torque; + + pwm_previous_sensors_0 = sensors_0; + + + IRQ_LOCK(flags); + torque = g_brushless_0_torque; + IRQ_UNLOCK(flags); + + + + + BRUSHLESS_0_PWM_SET_1( + PWM_MAX/2 + // offset 50% + ((int8_t)pgm_read_byte(g_brushless_phase1 + sensors_0)) * // conversion from sensors + torque /*>> 1*/ ); // torque must be divided by 2. this is now done in the acess function + BRUSHLESS_0_PWM_SET_2( + PWM_MAX/2 + + ((int8_t)pgm_read_byte(g_brushless_phase2 + sensors_0)) * + torque /*>> 1*/ ); + BRUSHLESS_0_PWM_SET_3( + PWM_MAX/2 + + ((int8_t)pgm_read_byte(g_brushless_phase3 + sensors_0)) * + torque /*>> 1*/ ); + } + } + + + /*********** END Motor 0 PWM update **********/ + + interrupt_pwm =0; + } + + /** speed update part */ + +#ifndef BRUSHLESS_MANAGE_EXTERNAL + // speed update variables + static uint16_t speed_division_timer = 1; // only one needed + // frequency division state machine + if (--speed_division_timer == 0) + { + + speed_division_timer = BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR; + // end of frequency division state machine + + brushless_speed_update_manage((void *)0); + + } +#endif + +} + + +void brushless_speed_update_manage(void * dummy) +{ + + uint8_t flags; + + // speed calculation, protected against glitches + IRQ_LOCK(flags); + g_brushless_0.speed = g_brushless_0.position - g_brushless_0_position_previous; + g_brushless_0_position_previous = g_brushless_0.position; + IRQ_UNLOCK(flags); + + + // event call, with no imbrication autorized ! + { + void (*f)(brushless); + static volatile uint8_t in_progress = 0; + + if(in_progress ==0) + { + in_progress = 1; + + IRQ_LOCK(flags); + f = periodic_event_0; + IRQ_UNLOCK(flags); + + if(f) + f(g_brushless_0); + + + in_progress = 0; + } + } +} + + +brushless_speed speed_mem_0 = BRUSHLESS_MAX_SPEED; +brushless_torque torque_mem_0 = 0; + + +/** initialisation, also executes pwm_init */ +void brushless_init(void) +{ + + pwm_init(); + + // pull up resistors enable, if feature enabled +#ifdef BRUSHLESS_0_SENSORS_PULL_UP_RESISTORS + sbi(BRUSHLESS_0_SENSOR_1_PORT,BRUSHLESS_0_SENSOR_1_BIT); + sbi(BRUSHLESS_0_SENSOR_2_PORT,BRUSHLESS_0_SENSOR_2_BIT); + sbi(BRUSHLESS_0_SENSOR_3_PORT,BRUSHLESS_0_SENSOR_3_BIT); +#endif + + + INIT_INT(); + +} + + + + +/******** set parameters, two times *******************/ +void brushless_0_set_parameters(brushless_speed speed, brushless_torque torque) +{ + uint16_t pwm_divider = 0; + uint8_t flags; + + + // memory of settings + speed_mem_0 = speed; + torque_mem_0 = torque; + + + if(speed ==0) + torque = 0; + else + pwm_divider = BRUSHLESS_MAX_SPEED / speed ; + + if (pwm_divider ==0) + pwm_divider =1; + + torque /= 2; // division is made here instead of in int function + + // inversion +#ifdef BRUSHLESS_0_INVERT + torque *= -1; +#endif + + IRQ_LOCK(flags); + g_brushless_0_pwm_divider = pwm_divider; + g_brushless_0_torque = torque; + IRQ_UNLOCK(flags); + + pwm_previous_sensors_0 = 0; // force application of the torque +} + + + +/******** get current speed and position, two times *******************/ +brushless brushless_0_get_mesures(void) +{ + brushless ret; + uint8_t flags; + + IRQ_LOCK(flags); + ret = g_brushless_0; + IRQ_UNLOCK(flags); + + return ret; +} + + +/******** set the position counter, two times *******************/ +void brushless_0_set_position(brushless_position p) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_brushless_0_position_previous += (p - g_brushless_0.position); // avoids speed glitches on pos change + g_brushless_0.position = p; + IRQ_UNLOCK(flags); +} + + + +void brushless_0_register_periodic_event(void (*f)(brushless)) +{ + uint8_t flags; + IRQ_LOCK(flags); + periodic_event_0 = f; + IRQ_UNLOCK(flags); +} + + + +/** acess functions for the control system interface */ + + +/** get speed function, compatible with control_system. Argument not used. */ +int32_t brushless_get_speed(void * motor_num) +{ + brushless retour; + + retour = brushless_0_get_mesures(); + + return (int32_t)(retour.speed); +} + +/** get position function, compatible with control_system. Argument not used. */ +int32_t brushless_get_pos(void * motor_num) +{ + brushless retour; + + retour = brushless_0_get_mesures(); + + return (int32_t)(retour.position); +} + +/** set torque function, compatible with control_system. first argument not used. */ +void brushless_set_torque(void * motor_num, int32_t torque) +{ + brushless_0_set_parameters(speed_mem_0, (brushless_torque) torque); +} + +/** set speed function, compatible with control_system. first argument not used. */ +void brushless_set_speed(void * motor_num, int32_t speed) +{ + brushless_0_set_parameters((brushless_speed) speed, torque_mem_0); +} diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/brushless.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/brushless.h new file mode 100644 index 0000000..ca9c9cd --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/brushless.h @@ -0,0 +1,109 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless.h,v 1.2.2.3 2007-05-23 17:18:12 zer0 Exp $ + * + */ + + +#ifndef _BRUSHLESS_ +#define _BRUSHLESS_ + +#include <aversive.h> + +#include <brushless_3phase_digital_hall_config.h> + + + +/** This module handles a brushless motor with 3 phases, wired in triangle or star. + 3 hall sensors are used wih digital output. + 3 PWM are outputted, these MUST be synchronized !! + + The control value is a voltage. This can be assimiled to a torque at low speeds. + + There is a possibility of also of limiting the speed. This is accomplished by slowing down the sampling speed of the + sensors. Doing this,the motor effective torque is reduced when the speed is such that the sensor actuation + approaches the sampling frequency. + use this technique carefully, because the motor has already his full voltage applied, an can dissipate a lot of energy, especially at low speeds. + + + there is no external manage function, as the manage is done at the PWM speed (overflow of one PWM timer is used.) + This function is speed optimized. + */ + + +typedef struct +{ + brushless_speed speed; + brushless_position position; +} +brushless; + + + /** initialisation, also executes pwm_init */ +extern void brushless_init(void); + +/** sets a consign speed and torque + if you do not use the speed coarse limitation, please configure with BRUSHLESS_MAX_SPEED */ +extern void brushless_0_set_parameters(brushless_speed speed, brushless_torque torque); + + +/** calculates the speed update info. To be called externally only if not internally, ie + if the BRUSHLESS_MANAGE_EXTERNAL is set + */ +#ifdef BRUSHLESS_MANAGE_EXTERNAL +extern void brushless_speed_update_manage(void * dummy); +#endif + +/** get current speed and position + This function is very useful to get synchronous speed and torque info +*/ +extern brushless brushless_0_get_mesures(void); + + +/** sets the position counter */ +extern void brushless_0_set_position(brushless_position p); + + +/** registers an event function that triggers periodically, and synchronously with the speed measurement */ +extern void brushless_0_register_periodic_event(void (*f)(brushless)); + + + + +/** acess functions for the control system interface */ + + +/** get speed function, compatible with control_system. + argument is unused but should be 0 for compatibility */ +extern int32_t brushless_get_speed(void * ); + +/** get position function, compatible with control_system. + argument is unused but should be 0 for compatibility */ +extern int32_t brushless_get_pos(void * ); + +/** set torque function, compatible with control_system. + argument is unused but should be 0 for compatibility */ +extern void brushless_set_torque(void *, int32_t torque); + +/** set speed function, compatible with control_system. + argument is unused but should be 0 for compatibility */ +extern void brushless_set_speed(void *, int32_t speed); + + + +#endif diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Entries b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Entries new file mode 100644 index 0000000..26aea61 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Entries @@ -0,0 +1,3 @@ +/brushless_3phase_digital_hall_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/brushless_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +D diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Repository b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Repository new file mode 100644 index 0000000..138292f --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors/brushless_3phase_digital_hall/config diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Root b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Tag b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Template b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/brushless_3phase_digital_hall_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/brushless_3phase_digital_hall_config.h new file mode 100644 index 0000000..999a9c3 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/brushless_3phase_digital_hall_config.h @@ -0,0 +1,102 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_3phase_digital_hall_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef int16_t brushless_speed; +typedef int32_t brushless_position; + +typedef int16_t brushless_torque; // max value is that of the PWM + + +/** motor connection definition */ + +/** inversion of sensors*/ +#define BRUSHLESS_0_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_0_SENSOR_1_PORT PORTA +#define BRUSHLESS_0_SENSOR_1_BIT 0 +#define BRUSHLESS_0_SENSOR_2_PORT PORTA +#define BRUSHLESS_0_SENSOR_2_BIT 1 +#define BRUSHLESS_0_SENSOR_3_PORT PORTA +#define BRUSHLESS_0_SENSOR_3_BIT 2 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_0_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_0_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_0_PWM_SET_3(value) pwm_set_1C(value) + +/** this selects the timer overflow int to use + please enter the timer number of one of the 3 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +#define BRUSHLESS_0_INVERT + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 3 +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR 10000 // 1,041s with a 8 MHz quartz + + +// #define BRUSHLESS_MANAGE_EXTERNAL// manual manage call + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + + +#endif // BRUSHLESS_TYPE diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/brushless_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/brushless_config.h new file mode 100644 index 0000000..7a87c80 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/config/brushless_config.h @@ -0,0 +1,99 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef int16_t brushless_speed; +typedef int32_t brushless_position; + +typedef int16_t brushless_torque; // max value is that of the PWM + + +/** motor connection definition */ + +/** inversion of sensors*/ +#define BRUSHLESS_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_SENSOR_1_PORT PORTA +#define BRUSHLESS_SENSOR_1_BIT 0 +#define BRUSHLESS_SENSOR_2_PORT PORTA +#define BRUSHLESS_SENSOR_2_BIT 1 +#define BRUSHLESS_SENSOR_3_PORT PORTA +#define BRUSHLESS_SENSOR_3_BIT 2 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_PWM_SET_3(value) pwm_set_2(value) + +/** this selects the timer overflow int to use + please enter the timer number of one of the 3 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +#define BRUSHLESS_INVERT + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 3 +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR 10000 // 1,041s with a 8 MHz quartz + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + + +#endif // BRUSHLESS_TYPE diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Entries b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Entries new file mode 100644 index 0000000..6fc9fe4 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Entries @@ -0,0 +1,8 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/brushless_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/diagnostic_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/error_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/main.c/1.2.2.3/Wed May 23 17:18:12 2007//Tb_zer0 +/pwm_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +/uart_config.h/1.2.2.2/Sat May 12 16:42:38 2007//Tb_zer0 +D diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Repository b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Repository new file mode 100644 index 0000000..5567384 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors/brushless_3phase_digital_hall/test diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Root b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Tag b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Template b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/Makefile b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/Makefile new file mode 100644 index 0000000..8e56dbc --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/brushless_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/brushless_config.h new file mode 100644 index 0000000..7a87c80 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/brushless_config.h @@ -0,0 +1,99 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef int16_t brushless_speed; +typedef int32_t brushless_position; + +typedef int16_t brushless_torque; // max value is that of the PWM + + +/** motor connection definition */ + +/** inversion of sensors*/ +#define BRUSHLESS_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_SENSOR_1_PORT PORTA +#define BRUSHLESS_SENSOR_1_BIT 0 +#define BRUSHLESS_SENSOR_2_PORT PORTA +#define BRUSHLESS_SENSOR_2_BIT 1 +#define BRUSHLESS_SENSOR_3_PORT PORTA +#define BRUSHLESS_SENSOR_3_BIT 2 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_PWM_SET_3(value) pwm_set_2(value) + +/** this selects the timer overflow int to use + please enter the timer number of one of the 3 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +#define BRUSHLESS_INVERT + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 3 +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR 10000 // 1,041s with a 8 MHz quartz + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + + +#endif // BRUSHLESS_TYPE diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/diagnostic_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/diagnostic_config.h new file mode 100644 index 0000000..a4bd410 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/diagnostic_config.h @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +#define INTERRUPT_SHOW_PORT PORTF +#define INTERRUPT_SHOW_BIT 0 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#ifdef DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/error_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/error_config.h new file mode 100644 index 0000000..1287055 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/main.c b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/main.c new file mode 100644 index 0000000..5e5cc9a --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/main.c @@ -0,0 +1,137 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2.2.3 2007-05-23 17:18:12 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive/wait.h> +#include <aversive.h> + +#include <brushless.h> + +#include <pwm.h> + +#include <diagnostic.h> + +#include <uart.h> +#include <stdio.h> +#include <aversive/pgmspace.h> + + + + + +void event0(brushless mesures) +{ + static int8_t cpt; + static int8_t dir = 1; + + cpt +=dir; + + + if(cpt == 10) + dir = -1; + if (cpt == -10 ) + dir = 1; + + + + brushless_0_set_parameters(BRUSHLESS_MAX_SPEED, PWM_MAX/10*cpt /1 ); + + printf_P(PSTR("vitesse M0 : %5i t/s %5i t/min "), mesures.speed /48, (int16_t)((int32_t)mesures.speed *60/48)); + +} + +void test_capteurs(void) +{ + + uint8_t sensor1_0;uint8_t sensor2_0;uint8_t sensor3_0; + //uint8_t sensor1_1;uint8_t sensor2_1;uint8_t sensor3_1; + + while(1) + { + + sensor1_0 = 0;sensor2_0 = 0;sensor3_0 = 0; + //sensor1_1 = 0;sensor2_1 = 0;sensor3_1 = 0; + + + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_1_PORT),BRUSHLESS_0_SENSOR_1_BIT)) + sensor1_0 =1; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_2_PORT),BRUSHLESS_0_SENSOR_2_BIT)) + sensor2_0 =1; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_3_PORT),BRUSHLESS_0_SENSOR_3_BIT)) + sensor3_0 =1; + + + + /*if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_1_PORT),BRUSHLESS_1_SENSOR_1_BIT)) + sensor1_1 =1; + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_2_PORT),BRUSHLESS_1_SENSOR_2_BIT)) + sensor2_1 =1; + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_3_PORT),BRUSHLESS_1_SENSOR_3_BIT)) + sensor3_1 =1;*/ + + printf_P(PSTR("sensors M0 = %i%i%i "), sensor1_0,sensor2_0,sensor3_0); + wait_ms(100); + //printf_P(PSTR("sensors M1 = %i%i%i\n") , sensor1_1,sensor2_1,sensor3_1); + + wait_ms(250); + } + +} + + + + + +int main(void) +{ + + + + brushless_init(); + + wait_ms(500); + + + uart_init(); + fdevopen((void *)uart0_send,NULL,0); + + printf_P(PSTR("\nbonjour\n")); + sei(); + + + + //test_capteurs(); + + + + + // enable power bridges + sbi(DDRG, 1); + sbi(PORTG, 1); + + + + brushless_0_register_periodic_event(event0); + + show_int_loop(); + return 0; +} + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/pwm_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/pwm_config.h new file mode 100644 index 0000000..882fd54 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/pwm_config.h @@ -0,0 +1,147 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ +/** \file pwm_config.h + \brief Module to operate all PWM outputs + + \test not tested + +*/ + + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +/* Which PWM are enabled ? */ +//#define PWM0_ENABLED +#define PWM1A_ENABLED +#define PWM1B_ENABLED +#define PWM1C_ENABLED +//#define PWM2_ENABLED +#define PWM3A_ENABLED +#define PWM3B_ENABLED +#define PWM3C_ENABLED + + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +// timer configs + +//#define TIMER0_MODE TIMER_8_MODE_PWM +//#define TIMER0_PRESCALE TIMER_8_PRESCALE_1 + +// 31 kHz PWM +#define TIMER1_MODE TIMER_16_MODE_PWM_9 +#define TIMER1_PRESCALE TIMER_16_PRESCALE_1 + +//#define TIMER2_MODE TIMER_8_MODE_PWM +//#define TIMER2_PRESCALE TIMER_8_PRESCALE_1 + +// 31 kHz PWM +#define TIMER3_MODE TIMER_16_MODE_PWM_9 +#define TIMER3_PRESCALE TIMER_16_PRESCALE_1 + + + + +/** config for pwm and signs + +The pwm mode is defined as follows : +you can add flags like the ones who follow : + +PWM_NORMAL : normal pwm, just to put a value if nothing else is needed +PWM_REVERSE : invert pwm output, not sign + +PWM_SIGNED : activate the sign output on a port (see config) +PWM_SIGN_INVERTED : invert sign output +PWM_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for low values, + else negative low values are near 100% + + +the values of PWMxx_SIGN_PORT and PWMxx_SIGN_BIT are simply ignored if the PWM is not signed, but must be defined + + +if you need for example a PWM1A with special sign mode you configure like this : + +#define PWM1A_MODE (PWM_SIGNED | PWM_SPECIAL_SIGN_MODE) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + +*/ + + + +// PWM definitions +#define PWM1A_MODE (PWM_NORMAL) +#define PWM1A_SIGN_PORT PORTB // ignored +#define PWM1A_SIGN_BIT 2 // ignored + +#define PWM1B_MODE (PWM_NORMAL) +#define PWM1B_SIGN_PORT PORTB // ignored +#define PWM1B_SIGN_BIT 2 // ignored + +#define PWM1C_MODE (PWM_NORMAL) +#define PWM1C_SIGN_PORT PORTB // ignored +#define PWM1C_SIGN_BIT 2 // ignored + +#define PWM3A_MODE (PWM_NORMAL) +#define PWM3A_SIGN_PORT PORTB // ignored +#define PWM3A_SIGN_BIT 2 // ignored + +#define PWM3B_MODE (PWM_NORMAL) +#define PWM3B_SIGN_PORT PORTB // ignored +#define PWM3B_SIGN_BIT 2 // ignored + +#define PWM3C_MODE (PWM_NORMAL) +#define PWM3C_SIGN_PORT PORTB // ignored +#define PWM3C_SIGN_BIT 2 // ignored + + + +/** +PWM synchronization. + +this makes the PWMs synchronized. +just activate the timers you want to synchronize + +to synch PWMs you need to enshure that the timers have same prescales. This is verified. +you need also to enshure that the PWM mode is the same, this is NOT verified !! +especially, for syncing 8 and 16 bit timers, the PWM mode should be 8 bit. + + +side effect : on some controllers prescalers are shared, so unwanted prescalers can be reset. + +This feature is not 100% shure for the moment, but has been tested on M32 and M128 +*/ + +//#define TIMER0_SYNCH +#define TIMER1_SYNCH +//#define TIMER2_SYNCH +#define TIMER3_SYNCH + + + +#endif + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/uart_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/uart_config.h new file mode 100644 index 0000000..a554cdd --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.2.2 2007-05-12 16:42:38 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Entries b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Entries new file mode 100644 index 0000000..ffb0dc6 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/brushless.c/1.2.2.3/Wed May 23 17:18:12 2007//Tb_zer0 +/brushless.h/1.2.2.3/Wed May 23 17:18:12 2007//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Repository b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Repository new file mode 100644 index 0000000..2d08f01 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors/brushless_3phase_digital_hall_double diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Root b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Tag b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Template b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/Makefile b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/Makefile new file mode 100644 index 0000000..a0b36cf --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/Makefile @@ -0,0 +1,9 @@ +TARGET = brushless_3phase_digital_hall_double + + +# List C source files here. (C dependencies are automatically generated.) +SRC = brushless.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/brushless.c b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/brushless.c new file mode 100644 index 0000000..c8415ec --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/brushless.c @@ -0,0 +1,728 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless.c,v 1.2.2.3 2007-05-23 17:18:12 zer0 Exp $ + * + */ + + +/** This module handles a brushless motor with 3 phases, wired in triangle or star. + 3 hall sensors are used wih digital output. + 3 PWM are outputted, these MUST be synchronized !! + + The control value is a voltage. This can be assimiled to a torque at low speeds. + + There is a possibility of also of limiting the speed. This is accomplished by slowing down the sampling speed of the + sensors. Doing this,the motor effective torque is reduced when the speed is such that the sensor actuation + approaches the sampling frequency. + use this technique carefully, because the motor has already his full voltage applied, an can dissipate a lot of energy, especially at low speeds. + + + there is no external manage function, as the manage is done at the PWM speed (overflow of one PWM timer is used.) + This function is speed optimized. +*/ + + +/** ceci est une commande de moteur brushless triphase en etoile, + utilisant 3 capteurs a effet hall digitaux. + En sortie on a 3 PWM (il est necessaire de les synchroniser !) + + pour le commande en couple, on joue sur les pwm (pseudo-couple) + et pour la commande en vitesse, on joue sur la frequence de rafraichissement des phases + par rapport aux capteurs. + cette astuce simple permet de faire facilement une consigne de vitesse + (pas besoin d'asservissement) + mais des vitesses faibles sont saccadees.*/ + + +#include <avr/io.h> +#include <avr/signal.h> + + +#include <pwm.h> + +#include <aversive.h> + + +#include <avr/pgmspace.h> + +#include <brushless.h> + +#include "brushless_3phase_digital_hall_double_config.h" + +#if (BRUSHLESS_TYPE != BRUSHLESS_DIGITAL_DOUBLE) +#error mauvais fichier de config "brushless_double_config.h" +#endif + + + + +/** calculating the event to use, based on PWM definition of the phase 1 + The two motors function on the same timer! */ + +#if (BRUSHLESS_TIMER == 0) +#define INIT_INT() sbi(TIMSK, TOIE0) +#define INT SIG_OVERFLOW0 + +#elif (BRUSHLESS_TIMER == 1) +#define INIT_INT() sbi(TIMSK, TOIE1) +#define INT SIG_OVERFLOW1 + +#elif (BRUSHLESS_TIMER == 2) +#define INIT_INT() sbi(TIMSK, TOIE2) +#define INT SIG_OVERFLOW2 + +#elif (BRUSHLESS_TIMER == 3) +#define INIT_INT() sbi(ETIMSK, TOIE3) /* extended timsk for this one ! */ +#define INT SIG_OVERFLOW3 + +#endif + + +/** 2 LUT tables: + sensors > relative electric angle + sensors > phase information + + + decimal value : 0 1 2 3 4 5 6 7 + sensors state : 000 001 010 011 100 101 110 111 + is this a valid state? : NO yes yes yes yes yes yes NO */ + +// conversion to electrical angle +// modulo 1 electrical turn. +// in RAM for faster acess +const int8_t g_brushless_angle[]= {0, 1, 5, 0, 3, 2, 4, 0}; + +// in progmem for ram optimization +const int8_t PROGMEM g_brushless_phase1[]= {0, 1, -1, 0, 0, 1, -1, 0}; +const int8_t PROGMEM g_brushless_phase2[]= {0, 0, 1, 1, -1, -1, 0, 0}; +const int8_t PROGMEM g_brushless_phase3[]= {0, -1, 0, -1, 1, 0, 1, 0}; + +// the zeroes in the phase give a 0 output if there are no sensors connected, or another problem like this. +// it could be a good idea to enable the pull up resistors ! + +void brushless_speed_update_manage(void * dummy); + + +// mem of previous position for speed calc. +brushless_position g_brushless_0_position_previous; +brushless_position g_brushless_1_position_previous; + +// memory for current measurements +brushless g_brushless_0; +brushless g_brushless_1; + +// pseudo torque to use +brushless_torque g_brushless_0_torque; +brushless_torque g_brushless_1_torque; + +// given with speed limit +uint16_t g_brushless_0_pwm_divider = 1; +uint16_t g_brushless_1_pwm_divider = 1; + + +// function pointer definition for event +void (*periodic_event_0)(brushless) = 0; //NULL; +void (*periodic_event_1)(brushless) = 0; //NULL; + + +/** This function is made of 5 parts : + - pwm divsion : gives a master frequency for the next parts, by dividing the PWM frequency (can also be set to 1) + - sensors acquisition : done every time + - angle update : done when there is a change in sensor state since last angle update + - PWM update : done only every x (every g_brushless_recurrence -1) and skipped if there is no change since last pwm update + - speed update : done only every y () this updates the speed + + + Typically, PWM update is slower than angle update, in order to not skip angle counting. + + + Typically, speed update is a lot slower than angle update in order to have a speed that is sampled at a correct rate. + This event can trigger an action, this is especially used if you have a servo control. + + + examples for a pretty fast motor : + - PWM at 30 kHz + - angle update at 10 kHz + - PWM update at 5 kHz or lower, depending on speed setting + - speed update at 100 Hz + +*/ + + +volatile uint8_t pwm_division_timer asm("pwm_div") = 1; +volatile uint8_t interrupt_pwm; +volatile uint8_t pwm_previous_sensors_0 = 0; // previous state of sensors for PWM update +volatile uint8_t pwm_previous_sensors_1 = 0; // previous state of sensors for PWM update + + + +#ifdef ASMHEADER +/** Here the division is done in ASM before saving a lot of registers on the stack. + This gains a lot of time when using a 8 bit timer without prescale + (one interrupt every 256 clocks !!) + */ + +void INT (void) __attribute__ ((naked)); // no register save, and no exit !! +SIGNAL(INT) +{ +asm volatile( + +/* division, done very early, for optimization */ +"PUSH R1 \n\t" +"IN R1,0x3F \n\t" +"PUSH R1 \n\t" +"LDS R1,pwm_div \n\t" +"DEC R1 \n\t" +"BREQ continue \n\t" +"STS pwm_div,R1 \n\t" /*we store only if negative. if positive, it will be done in the C code*/ + + +/* early go out of int */ +"go_out: \n\t" +"POP R1 \n\t" +"OUT 0x3F,R1 \n\t" +"POP R1 \n\t" +"RETI \n\t" + +/* restoring context, double work with the following interrupt function, but no other way */ +"continue: \n\t" +"POP R1 \n\t" +"OUT 0x3F,R1 \n\t" +"POP R1 \n\t" + +::); + +} // no jump, we pass implicitely. +SIGNAL(DUMMY) // we hope that the two are after each other !! (it is always the case with GCC) +{ + +#else // the same code in C +SIGNAL(INT) +{ +/** PWM division part */ +if (--pwm_division_timer != 0) + return; + + +#endif //common code + + + pwm_division_timer = BRUSHLESS_PWM_TO_SAMPLE_DIVISOR; + // end of frequency division state machine + + + + /** various definitions */ + + // angle update variables + static int8_t angle_electrical_previous_0 = 0; // previous electrical angle + static int8_t angle_electrical_previous_1 = 0; // previous electrical angle + static uint8_t angle_previous_sensors_0 = 0; // previous state of sensors for angle calc + static uint8_t angle_previous_sensors_1 = 0; // previous state of sensors for angle calc + int8_t angle_electrical, diff; + uint8_t sensors_0 = 0; + uint8_t sensors_1 = 0; + + // pwm update variables + static uint16_t pwm_update_timer_0 = 1; + static uint16_t pwm_update_timer_1 = 1; + + + { + /*********** Motor 0 angle update **********/ + + + /** sensors acquisition part + extraction of the sensor signals, and built up of a 3 bit ordened byte + this is done every time */ + + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_1_PORT),BRUSHLESS_0_SENSOR_1_BIT)) + sensors_0 +=1; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_2_PORT),BRUSHLESS_0_SENSOR_2_BIT)) + sensors_0 +=2; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_3_PORT),BRUSHLESS_0_SENSOR_3_BIT)) + sensors_0 +=4; + + #ifdef BRUSHLESS_0_SENSORS_INVERT + sensors_0 = (~ sensors_0) & 0x7; // inversion of the sensors + #endif + + + + /** the angle update part */ + + #ifndef LOADTEST + // skipping if no change + if(sensors_0 != angle_previous_sensors_0) + #endif + { + angle_previous_sensors_0 = sensors_0; + + + angle_electrical = g_brushless_angle[sensors_0]; // calculate electrical angle + + diff = angle_electrical - angle_electrical_previous_0; // convert to angle delta + angle_electrical_previous_0 = angle_electrical; // store for next time + + // clipping + if (diff > 3) + diff -=6; + else if (diff < -3) + diff +=6; + + #ifndef BRUSHLESS_0_INVERT + diff *= -1; // inversion of the angle reading + #endif + + // update of the absolute angle with the delta + //IRQ_LOCK(); // not necessary coz we enable ints only after + g_brushless_0.position -= (brushless_position)diff * BRUSHLESS_POSITION_PRECISION; + //IRQ_UNLOCK(); + + } + + /*********** END Motor 0 angle update **********/ + + /*********** Motor 1 angle update **********/ + + + /** sensors acquisition part + extraction of the sensor signals, and built up of a 3 bit ordened byte + this is done every time */ + + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_1_PORT),BRUSHLESS_1_SENSOR_1_BIT)) + sensors_1 +=1; + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_2_PORT),BRUSHLESS_1_SENSOR_2_BIT)) + sensors_1 +=2; + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_3_PORT),BRUSHLESS_1_SENSOR_3_BIT)) + sensors_1 +=4; + + #ifdef BRUSHLESS_1_SENSORS_INVERT + sensors_1 = (~ sensors_1) & 0x7; // inversion of the sensors + #endif + + + + /** the angle update part */ + + #ifndef LOADTEST + // skipping if no change + if(sensors_1 != angle_previous_sensors_1) + #endif + { + angle_previous_sensors_1 = sensors_1; + + + angle_electrical = g_brushless_angle[sensors_1]; // calculate electrical angle + + diff = angle_electrical - angle_electrical_previous_1; // convert to angle delta + angle_electrical_previous_1 = angle_electrical; // store for next time + + // clipping + if (diff > 3) + diff -=6; + else if (diff < -3) + diff +=6; + + #ifndef BRUSHLESS_1_INVERT + diff *= -1; // inversion of the angle reading + #endif + + // update of the absolute angle with the delta + //IRQ_LOCK(); // not necessary coz we enable ints only after + g_brushless_1.position -= (brushless_position)diff * BRUSHLESS_POSITION_PRECISION; + //IRQ_UNLOCK(); + + } + +/*********** END Motor 1 angle update **********/ + } + + + if(interrupt_pwm ==0) + { + interrupt_pwm =1; + + sei(); + + /*********** Motor 0 PWM update **********/ + + // frequency division state machine + if (--pwm_update_timer_0 == 0) + { + uint8_t flags; + IRQ_LOCK(flags); + pwm_update_timer_0 = g_brushless_0_pwm_divider; // protected against glitches + IRQ_UNLOCK(flags); + // end of frequency division state machine + + #ifndef LOADTEST + // skipping if same as last time + if(sensors_0 != pwm_previous_sensors_0) + #endif + { + brushless_torque torque; + + pwm_previous_sensors_0 = sensors_0; + + + IRQ_LOCK(flags); + torque = g_brushless_0_torque; + IRQ_UNLOCK(flags); + + + + + BRUSHLESS_0_PWM_SET_1( + PWM_MAX/2 + // offset 50% + ((int8_t)pgm_read_byte(g_brushless_phase1 + sensors_0)) * // conversion from sensors + torque /*>> 1*/ ); // torque must be divided by 2. this is now done in the acess function + BRUSHLESS_0_PWM_SET_2( + PWM_MAX/2 + + ((int8_t)pgm_read_byte(g_brushless_phase2 + sensors_0)) * + torque /*>> 1*/ ); + BRUSHLESS_0_PWM_SET_3( + PWM_MAX/2 + + ((int8_t)pgm_read_byte(g_brushless_phase3 + sensors_0)) * + torque /*>> 1*/ ); + } + } + + + /*********** END Motor 0 PWM update **********/ + + + /*********** Motor 1 PWM update **********/ + + // frequency division state machine + if (--pwm_update_timer_1 == 0) + { + uint8_t flags; + IRQ_LOCK(flags); + pwm_update_timer_1 = g_brushless_1_pwm_divider; // protected against glitches + IRQ_UNLOCK(flags); + // end of frequency division state machine + + #ifndef LOADTEST + // skipping if same as last time + if(sensors_1 != pwm_previous_sensors_1) + #endif + { + brushless_torque torque; + + pwm_previous_sensors_1 = sensors_1; + + + IRQ_LOCK(flags); + torque = g_brushless_1_torque; + IRQ_UNLOCK(flags); + + + + + BRUSHLESS_1_PWM_SET_1( + PWM_MAX/2 + // offset 50% + ((int8_t)pgm_read_byte(g_brushless_phase1 + sensors_1)) * // conversion from sensors + torque /*>> 1*/ ); // torque must be divided by 2. this is now done in the acess function + BRUSHLESS_1_PWM_SET_2( + PWM_MAX/2 + + ((int8_t)pgm_read_byte(g_brushless_phase2 + sensors_1)) * + torque /*>> 1*/ ); + BRUSHLESS_1_PWM_SET_3( + PWM_MAX/2 + + ((int8_t)pgm_read_byte(g_brushless_phase3 + sensors_1)) * + torque /*>> 1*/ ); + } + } + /*********** END Motor 1 PWM update **********/ + interrupt_pwm =0; + } + + /** speed update part */ + +#ifndef BRUSHLESS_MANAGE_EXTERNAL + // speed update variables + static uint16_t speed_division_timer = 1; // only one needed + // frequency division state machine + if (--speed_division_timer == 0) + { + + speed_division_timer = BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR; + // end of frequency division state machine + + brushless_speed_update_manage((void *)0); + + } +#endif + +} + +void brushless_speed_update_manage(void * dummy) +{ + + uint8_t flags; + + // speed calculation, protected against glitches + IRQ_LOCK(flags); + g_brushless_0.speed = g_brushless_0.position - g_brushless_0_position_previous; + g_brushless_0_position_previous = g_brushless_0.position; + IRQ_UNLOCK(flags); + + IRQ_LOCK(flags); + g_brushless_1.speed = g_brushless_1.position - g_brushless_1_position_previous; + g_brushless_1_position_previous = g_brushless_1.position; + IRQ_UNLOCK(flags); + + // event call, with no imbrication autorized ! + { + void (*f)(brushless); + static volatile uint8_t in_progress = 0; + + if(in_progress ==0) { + in_progress = 1; + + IRQ_LOCK(flags); + f = periodic_event_0; + IRQ_UNLOCK(flags); + + if(f) + f(g_brushless_0); + + + IRQ_LOCK(flags); + f = periodic_event_1; + IRQ_UNLOCK(flags); + + if(f) + f(g_brushless_1); + + in_progress = 0; + } + } +} + + + +brushless_speed speed_mem_0 = BRUSHLESS_MAX_SPEED; +brushless_torque torque_mem_0 = 0; +brushless_speed speed_mem_1 = BRUSHLESS_MAX_SPEED; +brushless_torque torque_mem_1 = 0; + + +/** initialisation, also executes pwm_init */ +void brushless_init(void) +{ + + pwm_init(); + + // pull up resistors enable, if feature enabled +#ifdef BRUSHLESS_0_SENSORS_PULL_UP_RESISTORS + sbi(BRUSHLESS_0_SENSOR_1_PORT,BRUSHLESS_0_SENSOR_1_BIT); + sbi(BRUSHLESS_0_SENSOR_2_PORT,BRUSHLESS_0_SENSOR_2_BIT); + sbi(BRUSHLESS_0_SENSOR_3_PORT,BRUSHLESS_0_SENSOR_3_BIT); +#endif + +#ifdef BRUSHLESS_1_SENSORS_PULL_UP_RESISTORS + sbi(BRUSHLESS_1_SENSOR_1_PORT,BRUSHLESS_1_SENSOR_1_BIT); + sbi(BRUSHLESS_1_SENSOR_2_PORT,BRUSHLESS_1_SENSOR_2_BIT); + sbi(BRUSHLESS_1_SENSOR_3_PORT,BRUSHLESS_1_SENSOR_3_BIT); +#endif + + + INIT_INT(); + +} + + + + +/******** set parameters, two times *******************/ +void brushless_0_set_parameters(brushless_speed speed, brushless_torque torque) +{ + uint16_t pwm_divider = 0; + uint8_t flags; + + // memory of settings + speed_mem_0 = speed; + torque_mem_0 = torque; + + + if(speed ==0) + torque = 0; + else + pwm_divider = BRUSHLESS_MAX_SPEED / speed ; + + if (pwm_divider ==0) + pwm_divider =1; + + torque /= 2; // division is made here instead of in int function + + // inversion +#ifdef BRUSHLESS_0_INVERT + torque *= -1; +#endif + + IRQ_LOCK(flags); + g_brushless_0_pwm_divider = pwm_divider; + g_brushless_0_torque = torque; + IRQ_UNLOCK(flags); + + pwm_previous_sensors_0 = 0; // force application of the torque +} + +void brushless_1_set_parameters(brushless_speed speed, brushless_torque torque) +{ + uint16_t pwm_divider = 0; + uint8_t flags; + + // memory of settings + speed_mem_1 = speed; + torque_mem_1 = torque; + + + if(speed ==0) + torque = 0; + else + pwm_divider = BRUSHLESS_MAX_SPEED / speed ; + + if (pwm_divider ==0) + pwm_divider =1; + + torque /= 2; // division is made here instead of in int function + + // inversion +#ifdef BRUSHLESS_1_INVERT + torque *= -1; +#endif + + IRQ_LOCK(flags); + g_brushless_1_pwm_divider = pwm_divider; + g_brushless_1_torque = torque; + IRQ_UNLOCK(flags); + + pwm_previous_sensors_1 = 0; // force application of the torque +} + + +/******** get current speed and position, two times *******************/ +brushless brushless_0_get_mesures(void) +{ + brushless ret; + uint8_t flags; + + IRQ_LOCK(flags); + ret = g_brushless_0; + IRQ_UNLOCK(flags); + + return ret; +} +brushless brushless_1_get_mesures(void) +{ + brushless ret; + uint8_t flags; + + IRQ_LOCK(flags); + ret = g_brushless_1; + IRQ_UNLOCK(flags); + + return ret; +} + + +/******** set the position counter, two times *******************/ +void brushless_0_set_position(brushless_position p) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_brushless_0_position_previous += p - g_brushless_0.position; // avoids speed glitches on pos change + g_brushless_0.position = p; + IRQ_UNLOCK(flags); +} +void brushless_1_set_position(brushless_position p) +{ + uint8_t flags; + IRQ_LOCK(flags); + g_brushless_1_position_previous += p - g_brushless_1.position; // avoids speed glitches on pos change + g_brushless_1.position = p; + IRQ_UNLOCK(flags); +} + + +void brushless_0_register_periodic_event(void (*f)(brushless)) +{ + uint8_t flags; + IRQ_LOCK(flags); + periodic_event_0 = f; + IRQ_UNLOCK(flags); +} +void brushless_1_register_periodic_event(void (*f)(brushless)) +{ + uint8_t flags; + IRQ_LOCK(flags); + periodic_event_1 = f; + IRQ_UNLOCK(flags); +} + + + +/** acess functions for the control system interface */ + + +/** get speed function, compatible with control_system. Argument not used. */ +int32_t brushless_get_speed(void * motor_num) +{ + brushless retour; + + if(motor_num) + retour = brushless_1_get_mesures(); + else + retour = brushless_0_get_mesures(); + + return (int32_t)(retour.speed); +} + +/** get position function, compatible with control_system. Argument not used. */ +int32_t brushless_get_pos(void * motor_num) +{ + brushless retour; + + if(motor_num) + retour = brushless_1_get_mesures(); + else + retour = brushless_0_get_mesures(); + + return (int32_t)(retour.position); +} + +/** set torque function, compatible with control_system. first argument not used. */ +void brushless_set_torque(void * motor_num, int32_t torque) +{ + if(motor_num) + brushless_1_set_parameters(speed_mem_1, (brushless_torque) torque); + else + brushless_0_set_parameters(speed_mem_0, (brushless_torque) torque); +} + +/** set speed function, compatible with control_system. first argument not used. */ +void brushless_set_speed(void * motor_num, int32_t speed) +{ + if(motor_num) + brushless_1_set_parameters((brushless_speed) speed, torque_mem_1); + else + brushless_0_set_parameters((brushless_speed) speed, torque_mem_0); +} diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/brushless.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/brushless.h new file mode 100644 index 0000000..0b2bc95 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/brushless.h @@ -0,0 +1,108 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless.h,v 1.2.2.3 2007-05-23 17:18:12 zer0 Exp $ + * + */ + + +#ifndef _BRUSHLESS_ +#define _BRUSHLESS_ + +#include <aversive.h> + +#include <brushless_3phase_digital_hall_double_config.h> + + + +/** This module handles two brushless motors with 3 phases, wired in triangle or star. + 2x 3 hall sensors are used wih digital output. + 2x 3 PWM are outputted, these MUST be synchronized !! + + The control value is a voltage. This can be assimiled to a torque at low speeds. + + There is a possibility of also of limiting the speed. This is accomplished by slowing down the sampling speed of the + sensors. Doing this,the motor effective torque is reduced when the speed is such that the sensor actuation + approaches the sampling frequency. + use this technique carefully, because the motor has already his full voltage applied, an can dissipate a lot of energy, especially at low speeds. + + + there is no external manage function, as the manage is done at the PWM speed (overflow of one PWM timer is used.) + This function is speed optimized. + */ + +typedef struct +{ + brushless_speed speed; + brushless_position position; +} +brushless; + + + /** initialisation, also executes pwm_init */ +extern void brushless_init(void); + +/** sets a consign speed and torque + if you do not use the speed coarse limitation, please configure with BRUSHLESS_MAX_SPEED */ +extern void brushless_0_set_parameters(brushless_speed speed, brushless_torque torque); +extern void brushless_1_set_parameters(brushless_speed speed, brushless_torque torque); + +/** calculates the speed update info. To be called externally only if not internally, ie + if the BRUSHLESS_MANAGE_EXTERNAL is set + */ +#ifdef BRUSHLESS_MANAGE_EXTERNAL +extern void brushless_speed_update_manage(void * dummy); +#endif + +/** get current speed and position + This function is very useful to get synchronous speed and torque info +*/ +extern brushless brushless_0_get_mesures(void); +extern brushless brushless_1_get_mesures(void); + +/** sets the position counter */ +extern void brushless_0_set_position(brushless_position p); +extern void brushless_1_set_position(brushless_position p); + +/** registers an event function that triggers periodically, and synchronously with the speed measurement */ +extern void brushless_0_register_periodic_event(void (*f)(brushless)); +extern void brushless_1_register_periodic_event(void (*f)(brushless)); + + + +/** acess functions for the control system interface */ + + +/** get speed function, compatible with control_system. + Argument is the number of the adressed motor, which is casted to (void*) */ +extern int32_t brushless_get_speed(void * ); + +/** get position function, compatible with control_system. + Argument is the number of the adressed motor, which is casted to (void*) */ +extern int32_t brushless_get_pos(void * ); + +/** set torque function, compatible with control_system. + Argument is the number of the adressed motor, which is casted to (void*) */ +extern void brushless_set_torque(void *, int32_t torque); + +/** set speed function, compatible with control_system. + Argument is the number of the adressed motor, which is casted to (void*) */ +extern void brushless_set_speed(void *, int32_t speed); + + + +#endif diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Entries b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Entries new file mode 100644 index 0000000..52f197c --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Entries @@ -0,0 +1,2 @@ +/brushless_3phase_digital_hall_double_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +D diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Repository b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Repository new file mode 100644 index 0000000..6073739 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Root b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Tag b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Template b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/brushless_3phase_digital_hall_double_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/brushless_3phase_digital_hall_double_config.h new file mode 100644 index 0000000..9f75c79 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/config/brushless_3phase_digital_hall_double_config.h @@ -0,0 +1,136 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_3phase_digital_hall_double_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL_DOUBLE + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef int16_t brushless_speed; +typedef int32_t brushless_position; + +typedef int16_t brushless_torque; // max value is that of the PWM + + +/** motor 0 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_0_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_0_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_0_SENSOR_1_PORT PORTA +#define BRUSHLESS_0_SENSOR_1_BIT 4 +#define BRUSHLESS_0_SENSOR_2_PORT PORTA +#define BRUSHLESS_0_SENSOR_2_BIT 3 +#define BRUSHLESS_0_SENSOR_3_PORT PORTA +#define BRUSHLESS_0_SENSOR_3_BIT 5 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_0_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_0_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_0_PWM_SET_3(value) pwm_set_1C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +//#define BRUSHLESS_0_INVERT + + +/** motor 1 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_1_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_1_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_1_SENSOR_1_PORT PORTA +#define BRUSHLESS_1_SENSOR_1_BIT 1 +#define BRUSHLESS_1_SENSOR_2_PORT PORTA +#define BRUSHLESS_1_SENSOR_2_BIT 0 +#define BRUSHLESS_1_SENSOR_3_PORT PORTA +#define BRUSHLESS_1_SENSOR_3_BIT 2 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_1_PWM_SET_1(value) pwm_set_3A(value) +#define BRUSHLESS_1_PWM_SET_2(value) pwm_set_3B(value) +#define BRUSHLESS_1_PWM_SET_3(value) pwm_set_3C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +#define BRUSHLESS_1_INVERT + + + +/** this selects the timer overflow int to use + please enter the timer number of one of the 6 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 4 // PWM9 bits, quartz 16 MHz >> 7.8 kHz +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR 7812 // environ 1s + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + +//#define LOADTEST // define this to test the maximum processor load ! + +//#define ASMHEADER // optimized PWM division : particularly useful with 8 bit timers ! Using this can display one warning + + +#endif // BRUSHLESS_TYPE + + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Entries b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Entries new file mode 100644 index 0000000..8bd5b87 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Entries @@ -0,0 +1,9 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/brushless_3phase_digital_hall_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/brushless_3phase_digital_hall_double_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/diagnostic_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/error_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/main.c/1.2.2.3/Wed May 23 17:18:13 2007//Tb_zer0 +/pwm_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/uart_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +D diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Repository b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Repository new file mode 100644 index 0000000..e76ed05 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Root b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Tag b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Template b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/Makefile b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/Makefile new file mode 100644 index 0000000..8e56dbc --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/brushless_3phase_digital_hall_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/brushless_3phase_digital_hall_config.h new file mode 100644 index 0000000..7e2c0e6 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/brushless_3phase_digital_hall_config.h @@ -0,0 +1,108 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_3phase_digital_hall_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL_DOUBLE + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef int16_t brushless_speed; +typedef int32_t brushless_position; + +typedef int16_t brushless_torque; // max value is that of the PWM + + +/** motor 0 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_0_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_0_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_0_SENSOR_1_PORT PORTA +#define BRUSHLESS_0_SENSOR_1_BIT 4 +#define BRUSHLESS_0_SENSOR_2_PORT PORTA +#define BRUSHLESS_0_SENSOR_2_BIT 3 +#define BRUSHLESS_0_SENSOR_3_PORT PORTA +#define BRUSHLESS_0_SENSOR_3_BIT 5 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_0_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_0_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_0_PWM_SET_3(value) pwm_set_1C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +//#define BRUSHLESS_0_INVERT + + + + +/** this selects the timer overflow int to use + please enter the timer number of one of the 6 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 4 // PWM9 bits, quartz 16 MHz >> 7.8 kHz +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR 7812 // environ 1s + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + +//#define LOADTEST // define this to test the maximum processor load ! + +//#define ASMHEADER // optimized PWM division : particularly useful with 8 bit timers ! Using this can display one warning + + +#endif // BRUSHLESS_TYPE + + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/brushless_3phase_digital_hall_double_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/brushless_3phase_digital_hall_double_config.h new file mode 100644 index 0000000..9f75c79 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/brushless_3phase_digital_hall_double_config.h @@ -0,0 +1,136 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_3phase_digital_hall_double_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL_DOUBLE + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef int16_t brushless_speed; +typedef int32_t brushless_position; + +typedef int16_t brushless_torque; // max value is that of the PWM + + +/** motor 0 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_0_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_0_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_0_SENSOR_1_PORT PORTA +#define BRUSHLESS_0_SENSOR_1_BIT 4 +#define BRUSHLESS_0_SENSOR_2_PORT PORTA +#define BRUSHLESS_0_SENSOR_2_BIT 3 +#define BRUSHLESS_0_SENSOR_3_PORT PORTA +#define BRUSHLESS_0_SENSOR_3_BIT 5 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_0_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_0_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_0_PWM_SET_3(value) pwm_set_1C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +//#define BRUSHLESS_0_INVERT + + +/** motor 1 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_1_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_1_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_1_SENSOR_1_PORT PORTA +#define BRUSHLESS_1_SENSOR_1_BIT 1 +#define BRUSHLESS_1_SENSOR_2_PORT PORTA +#define BRUSHLESS_1_SENSOR_2_BIT 0 +#define BRUSHLESS_1_SENSOR_3_PORT PORTA +#define BRUSHLESS_1_SENSOR_3_BIT 2 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_1_PWM_SET_1(value) pwm_set_3A(value) +#define BRUSHLESS_1_PWM_SET_2(value) pwm_set_3B(value) +#define BRUSHLESS_1_PWM_SET_3(value) pwm_set_3C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +#define BRUSHLESS_1_INVERT + + + +/** this selects the timer overflow int to use + please enter the timer number of one of the 6 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 4 // PWM9 bits, quartz 16 MHz >> 7.8 kHz +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR 7812 // environ 1s + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + +//#define LOADTEST // define this to test the maximum processor load ! + +//#define ASMHEADER // optimized PWM division : particularly useful with 8 bit timers ! Using this can display one warning + + +#endif // BRUSHLESS_TYPE + + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/diagnostic_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/diagnostic_config.h new file mode 100644 index 0000000..23e6c18 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/diagnostic_config.h @@ -0,0 +1,43 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +#define INTERRUPT_SHOW_PORT PORTF +#define INTERRUPT_SHOW_BIT 0 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#ifdef DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/error_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/error_config.h new file mode 100644 index 0000000..851e7c3 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/main.c b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/main.c new file mode 100644 index 0000000..aaebd2e --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/main.c @@ -0,0 +1,162 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2.2.3 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive/wait.h> +#include <aversive.h> + +#include <brushless.h> + +#include <pwm.h> + +#include <diagnostic.h> + +#include <uart.h> +#include <stdio.h> +#include <aversive/pgmspace.h> + + + + + +void event0(brushless mesures) +{ + static int8_t cpt; + static int8_t dir = 1; + + cpt +=dir; + + if(cpt == 10) + dir = -1; + if (cpt == -10 ) + dir = 1; + + + + brushless_0_set_parameters(BRUSHLESS_MAX_SPEED, PWM_MAX/10*cpt /1 ); + + printf_P(PSTR("vitesse M0 : %5i t/s %5i t/min "), mesures.speed /48, (int16_t)((int32_t)mesures.speed *60/48)); + +} +void event1(brushless mesures) +{ + static int8_t cpt; + static int8_t dir = 1; + + cpt +=dir; + + if(cpt == 10) + dir = -1; + if (cpt == -10 ) + dir = 1; + + + + brushless_1_set_parameters(BRUSHLESS_MAX_SPEED, PWM_MAX/10*cpt /1 ); + + printf_P(PSTR("vitesse M1 : %5i t/s %5i t/min\n"), mesures.speed /48, (int16_t)((int32_t)mesures.speed *60/48)); + +} + +void test_capteurs(void) +{ + + uint8_t sensor1_0; + uint8_t sensor2_0; + uint8_t sensor3_0; + + uint8_t sensor1_1; + uint8_t sensor2_1; + uint8_t sensor3_1; + + while(1) { + + sensor1_0 = 0; + sensor2_0 = 0; + sensor3_0 = 0; + + sensor1_1 = 0; + sensor2_1 = 0; + sensor3_1 = 0; + + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_1_PORT),BRUSHLESS_0_SENSOR_1_BIT)) + sensor1_0 =1; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_2_PORT),BRUSHLESS_0_SENSOR_2_BIT)) + sensor2_0 =1; + if(bit_is_set(PIN(BRUSHLESS_0_SENSOR_3_PORT),BRUSHLESS_0_SENSOR_3_BIT)) + sensor3_0 =1; + + + + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_1_PORT),BRUSHLESS_1_SENSOR_1_BIT)) + sensor1_1 =1; + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_2_PORT),BRUSHLESS_1_SENSOR_2_BIT)) + sensor2_1 =1; + if(bit_is_set(PIN(BRUSHLESS_1_SENSOR_3_PORT),BRUSHLESS_1_SENSOR_3_BIT)) + sensor3_1 =1; + + printf_P(PSTR("sensors M0 = %i%i%i "), sensor1_0,sensor2_0,sensor3_0); + wait_ms(100); + printf_P(PSTR("sensors M1 = %i%i%i\n") , sensor1_1,sensor2_1,sensor3_1); + + wait_ms(250); + } + +} + + + + + +int main(void) +{ + + + + brushless_init(); + + //wait_ms(500); + + + uart_init(); + fdevopen((void *)uart0_send,NULL,0); + + printf_P(PSTR("\nbonjour\n")); + sei(); + + + + + //test_capteurs(); + + + // enable power bridges + sbi(DDRG, 1); + sbi(PORTG, 1); + + + + brushless_0_register_periodic_event(event0); + brushless_1_register_periodic_event(event1); + show_int_loop(); + return 0; +} + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/pwm_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/pwm_config.h new file mode 100644 index 0000000..2236353 --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/pwm_config.h @@ -0,0 +1,147 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ +/** \file pwm_config.h + \brief Module to operate all PWM outputs + + \test not tested + +*/ + + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +/* Which PWM are enabled ? */ +//#define PWM0_ENABLED +#define PWM1A_ENABLED +#define PWM1B_ENABLED +#define PWM1C_ENABLED +//#define PWM2_ENABLED +#define PWM3A_ENABLED +#define PWM3B_ENABLED +#define PWM3C_ENABLED + + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +// timer configs + +//#define TIMER0_MODE TIMER_8_MODE_PWM +//#define TIMER0_PRESCALE TIMER_8_PRESCALE_1 + +// 31 kHz PWM +#define TIMER1_MODE TIMER_16_MODE_PWM_9 +#define TIMER1_PRESCALE TIMER_16_PRESCALE_1 + +//#define TIMER2_MODE TIMER_8_MODE_PWM +//#define TIMER2_PRESCALE TIMER_8_PRESCALE_1 + +// 31 kHz PWM +#define TIMER3_MODE TIMER_16_MODE_PWM_9 +#define TIMER3_PRESCALE TIMER_16_PRESCALE_1 + + + + +/** config for pwm and signs + +The pwm mode is defined as follows : +you can add flags like the ones who follow : + +PWM_NORMAL : normal pwm, just to put a value if nothing else is needed +PWM_REVERSE : invert pwm output, not sign + +PWM_SIGNED : activate the sign output on a port (see config) +PWM_SIGN_INVERTED : invert sign output +PWM_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for low values, + else negative low values are near 100% + + +the values of PWMxx_SIGN_PORT and PWMxx_SIGN_BIT are simply ignored if the PWM is not signed, but must be defined + + +if you need for example a PWM1A with special sign mode you configure like this : + +#define PWM1A_MODE (PWM_SIGNED | PWM_SPECIAL_SIGN_MODE) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + +*/ + + + +// PWM definitions +#define PWM1A_MODE (PWM_NORMAL) +#define PWM1A_SIGN_PORT PORTB // ignored +#define PWM1A_SIGN_BIT 2 // ignored + +#define PWM1B_MODE (PWM_NORMAL) +#define PWM1B_SIGN_PORT PORTB // ignored +#define PWM1B_SIGN_BIT 2 // ignored + +#define PWM1C_MODE (PWM_NORMAL) +#define PWM1C_SIGN_PORT PORTB // ignored +#define PWM1C_SIGN_BIT 2 // ignored + +#define PWM3A_MODE (PWM_NORMAL) +#define PWM3A_SIGN_PORT PORTB // ignored +#define PWM3A_SIGN_BIT 2 // ignored + +#define PWM3B_MODE (PWM_NORMAL) +#define PWM3B_SIGN_PORT PORTB // ignored +#define PWM3B_SIGN_BIT 2 // ignored + +#define PWM3C_MODE (PWM_NORMAL) +#define PWM3C_SIGN_PORT PORTB // ignored +#define PWM3C_SIGN_BIT 2 // ignored + + + +/** +PWM synchronization. + +this makes the PWMs synchronized. +just activate the timers you want to synchronize + +to synch PWMs you need to enshure that the timers have same prescales. This is verified. +you need also to enshure that the PWM mode is the same, this is NOT verified !! +especially, for syncing 8 and 16 bit timers, the PWM mode should be 8 bit. + + +side effect : on some controllers prescalers are shared, so unwanted prescalers can be reset. + +This feature is not 100% shure for the moment, but has been tested on M32 and M128 +*/ + +//#define TIMER0_SYNCH +#define TIMER1_SYNCH +//#define TIMER2_SYNCH +#define TIMER3_SYNCH + + + +#endif + diff --git a/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/uart_config.h b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/uart_config.h new file mode 100644 index 0000000..19b7c9d --- /dev/null +++ b/modules/devices/brushless_motors/brushless_3phase_digital_hall_double/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/control_system/CVS/Entries b/modules/devices/control_system/CVS/Entries new file mode 100644 index 0000000..6beba31 --- /dev/null +++ b/modules/devices/control_system/CVS/Entries @@ -0,0 +1,2 @@ +D/control_system_manager//// +D/filters//// diff --git a/modules/devices/control_system/CVS/Repository b/modules/devices/control_system/CVS/Repository new file mode 100644 index 0000000..1baac74 --- /dev/null +++ b/modules/devices/control_system/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system diff --git a/modules/devices/control_system/CVS/Root b/modules/devices/control_system/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/CVS/Tag b/modules/devices/control_system/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/CVS/Template b/modules/devices/control_system/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/control_system_manager/CVS/Entries b/modules/devices/control_system/control_system_manager/CVS/Entries new file mode 100644 index 0000000..dee568a --- /dev/null +++ b/modules/devices/control_system/control_system_manager/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.3.6.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/control_system_manager.c/1.7.4.3/Mon Dec 31 16:25:00 2007//Tb_zer0 +/control_system_manager.h/1.7.4.5/Sun Mar 2 17:18:34 2008//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/control_system/control_system_manager/CVS/Repository b/modules/devices/control_system/control_system_manager/CVS/Repository new file mode 100644 index 0000000..57c6f0a --- /dev/null +++ b/modules/devices/control_system/control_system_manager/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/control_system_manager diff --git a/modules/devices/control_system/control_system_manager/CVS/Root b/modules/devices/control_system/control_system_manager/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/control_system_manager/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/control_system_manager/CVS/Tag b/modules/devices/control_system/control_system_manager/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/control_system_manager/CVS/Template b/modules/devices/control_system/control_system_manager/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/control_system_manager/Makefile b/modules/devices/control_system/control_system_manager/Makefile new file mode 100755 index 0000000..d1d9a84 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/Makefile @@ -0,0 +1,6 @@ +TARGET = control_system_manager + +# List C source files here. (C dependencies are automatically generated.) +SRC = control_system_manager.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/control_system/control_system_manager/config/CVS/Entries b/modules/devices/control_system/control_system_manager/config/CVS/Entries new file mode 100644 index 0000000..e699e37 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/config/CVS/Entries @@ -0,0 +1,2 @@ +/regulation_manager_config.h/1.1.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D diff --git a/modules/devices/control_system/control_system_manager/config/CVS/Repository b/modules/devices/control_system/control_system_manager/config/CVS/Repository new file mode 100644 index 0000000..0444b96 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/control_system_manager/config diff --git a/modules/devices/control_system/control_system_manager/config/CVS/Root b/modules/devices/control_system/control_system_manager/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/control_system_manager/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/control_system_manager/config/CVS/Tag b/modules/devices/control_system/control_system_manager/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/control_system_manager/config/CVS/Template b/modules/devices/control_system/control_system_manager/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/control_system_manager/config/regulation_manager_config.h b/modules/devices/control_system/control_system_manager/config/regulation_manager_config.h new file mode 100644 index 0000000..d250ece --- /dev/null +++ b/modules/devices/control_system/control_system_manager/config/regulation_manager_config.h @@ -0,0 +1,20 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ diff --git a/modules/devices/control_system/control_system_manager/control_system_manager.c b/modules/devices/control_system/control_system_manager/control_system_manager.c new file mode 100755 index 0000000..c1b2fa5 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/control_system_manager.c @@ -0,0 +1,306 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: control_system_manager.c,v 1.7.4.3 2007-12-31 16:25:00 zer0 Exp $ + * + */ +#include <stdio.h> +#include <control_system_manager.h> + +#define DEBUG 0 + +#if DEBUG == 1 +#define debug_printf(args...) do { printf(args); } while(0) +#else +#define debug_printf(args...) do { } while(0) +#endif + +/** Call a filter() pointer : + * - lock the interrupts + * - read the pointer to the filter function + * - unlock the interrupts + * - if pointer is null, return the IN value + * - else apply filter + */ +static inline uint32_t +safe_filter(int32_t (*f)(void *, int32_t), void * param, int32_t value) +{ + int32_t (*f_tmp)(void *, int32_t); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + return f_tmp(param_tmp, value); + } + return value; +} + +/** Call a processout() pointer : + * - lock the interrupts + * - read the pointer to the processout function + * - unlock the interrupts + * - if pointer is null, return 0 + * - else return the value processed by the function + */ +static inline uint32_t +safe_getprocessout(int32_t (*f)(void *), void * param) +{ + int32_t (*f_tmp)(void *); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + return f_tmp(param_tmp); + } + return 0; +} + +/** Call a processin() pointer : + * - lock the interrupts + * - read the pointer to the processin function + * - unlock the interrupts + * - if pointer is null, don't do anything + * - else call the processin with the parameters + */ +static inline void +safe_setprocessin(void (*f)(void *, int32_t), void * param, int32_t value) +{ + void (*f_tmp)(void *, int32_t); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + f_tmp(param_tmp, value); + } +} + +/**********************************************/ + +void cs_init(struct cs* cs) +{ + uint8_t flags; + IRQ_LOCK(flags); + cs->consign_filter = NULL; + cs->consign_filter_params = NULL; + + cs->correct_filter = NULL; + cs->correct_filter_params = NULL; + + cs->feedback_filter = NULL; + cs->feedback_filter_params = NULL; + + cs->process_out = NULL; + cs->process_out_params = NULL; + + cs->process_in = NULL; + cs->process_in_params = NULL; + + cs->consign_value = 0; + cs->error_value = 0; + cs->out_value = 0; + IRQ_UNLOCK(flags); + + return; +} + + +void cs_set_consign_filter(struct cs* cs, int32_t (*consign_filter)(void*, int32_t), void* consign_filter_params) +{ + uint8_t flags; + IRQ_LOCK(flags); + cs->consign_filter = consign_filter; + cs->consign_filter_params = consign_filter_params; + IRQ_UNLOCK(flags); +} + + + +void cs_set_correct_filter(struct cs* cs, int32_t (*correct_filter)(void*, int32_t), void* correct_filter_params) +{ + uint8_t flags; + IRQ_LOCK(flags); + cs->correct_filter = correct_filter; + cs->correct_filter_params = correct_filter_params; + IRQ_UNLOCK(flags); +} + + +void cs_set_feedback_filter(struct cs* cs, int32_t (*feedback_filter)(void*, int32_t), void* feedback_filter_params) +{ + uint8_t flags; + IRQ_LOCK(flags); + cs->feedback_filter = feedback_filter; + cs->feedback_filter_params = feedback_filter_params; + IRQ_UNLOCK(flags); +} + + +void cs_set_process_in(struct cs* cs, void (*process_in)(void*, int32_t), void* process_in_params) +{ + uint8_t flags; + IRQ_LOCK(flags); + cs->process_in = process_in; + cs->process_in_params = process_in_params; + IRQ_UNLOCK(flags); +} + + + +void cs_set_process_out(struct cs* cs, int32_t (*process_out)(void*), void* process_out_params) +{ + uint8_t flags; + IRQ_LOCK(flags); + cs->process_out = process_out; + cs->process_out_params = process_out_params; + IRQ_UNLOCK(flags); +} + + + +int32_t cs_do_process(struct cs* cs, int32_t consign) +{ +#if DEBUG == 1 + static int i=0; +#endif + int32_t process_out_value = 0; + + /* save the consign value into the structure */ + cs->consign_value = consign; + + debug_printf("%d %ld ", i++, consign); + + /* if the consign filter exist */ + cs->filtered_consign_value = consign = safe_filter(cs->consign_filter, cs->consign_filter_params, consign); + + debug_printf("%ld ", cs->filtered_consign_value); + + /* read the process out if defined */ + process_out_value = safe_getprocessout(cs->process_out, cs->process_out_params); + + debug_printf("%ld ", process_out_value); + + /* apply the feedback filter if defined */ + process_out_value = safe_filter(cs->feedback_filter, cs->feedback_filter_params, process_out_value); + cs->filtered_feedback_value = process_out_value; + + debug_printf("%ld ", process_out_value); + + /* substract consign and process out and put it into error */ + cs->error_value = cs->filtered_consign_value - process_out_value ; + + debug_printf("%ld ", cs->error_value); + + /* apply the correct filter to error_value and put it into out_value */ + cs->out_value = safe_filter(cs->correct_filter, cs->correct_filter_params, cs->error_value); + + debug_printf("%ld\n", cs->out_value); + + /* send out_value to process in*/ + safe_setprocessin (cs->process_in, cs->process_in_params, cs->out_value); + + /* return the out value */ + return (cs->out_value); +} + + + +void cs_manage(void * data) +{ + struct cs* cs = data; + cs_do_process(cs, cs->consign_value); +} + + + +int32_t cs_get_out(struct cs* cs) +{ + int32_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = cs->out_value; + IRQ_UNLOCK(flags); + + return tmp; +} + + + +int32_t cs_get_error(struct cs* cs) +{ + int32_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = cs->error_value; + IRQ_UNLOCK(flags); + + return tmp; +} + + + +int32_t cs_get_consign(struct cs* cs) +{ + int32_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = cs->consign_value; + IRQ_UNLOCK(flags); + + return tmp; +} + +int32_t cs_get_filtered_consign(struct cs* cs) +{ + int32_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = cs->filtered_consign_value; + IRQ_UNLOCK(flags); + + return tmp; +} + +int32_t cs_get_filtered_feedback(struct cs* cs) +{ + int32_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = cs->filtered_feedback_value; + IRQ_UNLOCK(flags); + + return tmp; +} + + + +void cs_set_consign(struct cs* cs, int32_t v) +{ + uint8_t flags; + /* set the consign */ + IRQ_LOCK(flags); + cs->consign_value = v; + IRQ_UNLOCK(flags); +} diff --git a/modules/devices/control_system/control_system_manager/control_system_manager.h b/modules/devices/control_system/control_system_manager/control_system_manager.h new file mode 100755 index 0000000..f19969b --- /dev/null +++ b/modules/devices/control_system/control_system_manager/control_system_manager.h @@ -0,0 +1,135 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: control_system_manager.h,v 1.7.4.5 2008-03-02 17:18:34 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Techology 2005 + * Implementation for the control_system manager + */ + +/** \file control_system_manager.h + * \brief Interface for the control_system manager module. + * + * \todo Test the module on a real system. + * + * \test No test for the moment, only correct compilation. + * + * This module provide functions to control and regulate a system. + */ + +#ifndef _CONTROL_SYSTEM_MANAGER_ +#define _CONTROL_SYSTEM_MANAGER_ + +#include <aversive.h> + +/** The data structure used by the control_system_manager module */ +struct cs { + + int32_t (*consign_filter)(void *, int32_t); + void* consign_filter_params; + + int32_t (*correct_filter)(void*, int32_t); + void* correct_filter_params; + + int32_t (*feedback_filter)(void*, int32_t); + void* feedback_filter_params; + + int32_t (*process_out)(void*); + void* process_out_params; + + void (*process_in)(void*, int32_t); + void* process_in_params; + + int32_t consign_value; + int32_t filtered_feedback_value; + int32_t filtered_consign_value; + int32_t error_value; + int32_t out_value; +}; + +/******* - Prototyping - *******/ + +/** Initiate the control_system structure by setting all fields to NULL */ +void cs_init(struct cs* cs); + +/** Set the cs consign_filter fields in the cs structure */ +void cs_set_consign_filter(struct cs* cs, + int32_t (*consign_filter)(void*, int32_t), + void* consign_filter_params); + +/** Set the cs correct_filter fields in the cs structure */ +void cs_set_correct_filter(struct cs* cs, + int32_t (*correct_filter)(void*, int32_t), + void* correct_filer_params); + +/** Set the cs feedback_filter fields in the cs structure */ +void cs_set_feedback_filter(struct cs* cs, + int32_t (*feedback_filter)(void*, int32_t), + void* feedback_filer_params); + +/** Set the cs process_in fields in the cs structure */ +void cs_set_process_in(struct cs* cs, + void (*process_in)(void*, int32_t), + void* process_in_params); + +/** Set the cs process_out fields in the cs structure */ +void cs_set_process_out(struct cs* cs, + int32_t (*process_out)(void*), + void* process_out_params); + + +/** \brief This function do the main loop of the control system process. + * + * - Save the consign in the structure. + * - Apply the consign filter to the consign. + * - Read the process out + * - Apply the feedback filter to the process out + * - Substract filtered consign to filtered process out. + * - Save the result in error_value and apply the correct filter. + * - Save the filtered result and send it to process_in(). + * - Return this result. + * + */ +int32_t cs_do_process(struct cs* cs, int32_t consign); + +/** Apply cs_do_process() to the structure cs + * \param cs should be a (struct cs*) + */ +void cs_manage(void * cs); + +/** Return the last output sent to process */ +int32_t cs_get_out(struct cs* cs); + +/** Return the last calculated error */ +int32_t cs_get_error(struct cs* cs); + +/** Return the current consign */ +int32_t cs_get_consign(struct cs* cs); + +/** Return the current consign, after filter */ +int32_t cs_get_filtered_consign(struct cs* cs); + +/** Return the last feedback value, after filter */ +int32_t cs_get_filtered_feedback(struct cs* cs); + +/** Change the consign without calculating control system */ +void cs_set_consign(struct cs* cs, int32_t v); + + +#endif /* #ifndef _CONTROL_SYSTEM_MANAGER_ */ diff --git a/modules/devices/control_system/control_system_manager/test/.config b/modules/devices/control_system/control_system_manager/test/.config new file mode 100644 index 0000000..e9bc046 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=8000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +CONFIG_MODULE_FIXED_POINT=y +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +CONFIG_MODULE_PID=y +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/control_system/control_system_manager/test/CVS/Entries b/modules/devices/control_system/control_system_manager/test/CVS/Entries new file mode 100644 index 0000000..0a2a898 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.7.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/list_config.h/1.1.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/main.c/1.4.4.2/Wed May 23 17:18:13 2007//Tb_zer0 +/pid_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/uart_config.h/1.1.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D diff --git a/modules/devices/control_system/control_system_manager/test/CVS/Repository b/modules/devices/control_system/control_system_manager/test/CVS/Repository new file mode 100644 index 0000000..2e4c15a --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/control_system_manager/test diff --git a/modules/devices/control_system/control_system_manager/test/CVS/Root b/modules/devices/control_system/control_system_manager/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/control_system_manager/test/CVS/Tag b/modules/devices/control_system/control_system_manager/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/control_system_manager/test/CVS/Template b/modules/devices/control_system/control_system_manager/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/control_system_manager/test/Makefile b/modules/devices/control_system/control_system_manager/test/Makefile new file mode 100755 index 0000000..d2c03d8 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/control_system/control_system_manager/test/list_config.h b/modules/devices/control_system/control_system_manager/test/list_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/control_system_manager/test/main.c b/modules/devices/control_system/control_system_manager/test/main.c new file mode 100755 index 0000000..2a02e32 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/main.c @@ -0,0 +1,87 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4.4.2 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <uart.h> +#include <aversive/wait.h> +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> + +#define MAX_SPEED 10000 +static int32_t motor_speed=0; +static int32_t motor_pos=0; + +/* try to simulate a motor (quick and dirty and wrong) */ +void motor_set(void * dummy, int32_t in) +{ + motor_speed = motor_speed - motor_speed/8 ; + motor_speed += in/8; +} + +int32_t motor_get_pos(void * dummy) +{ + motor_pos += motor_speed; + return motor_pos; +} + +int main(void) +{ + struct cs my_cs; + struct pid_filter my_pid; + struct quadramp_filter my_qr; + uint16_t i ; + + uart_init(); + + pid_init(&my_pid); + pid_set_gains(&my_pid, 40, 1, 3); + pid_set_maximums(&my_pid, 0, 5000, 4095); + pid_set_out_shift(&my_pid, 10); + + quadramp_init(&my_qr); + quadramp_set_1st_order_vars(&my_qr, 1000, 1000); /* set speed */ + quadramp_set_2nd_order_vars(&my_qr, 100, 100); /* set accel */ + + cs_init(&my_cs); + cs_set_consign_filter(&my_cs, quadramp_do_filter, &my_qr); + cs_set_correct_filter(&my_cs, pid_do_filter, &my_pid); + cs_set_process_in(&my_cs, motor_set, NULL); + cs_set_process_out(&my_cs, motor_get_pos, NULL); + cs_set_consign(&my_cs, 0); + + for ( i=0 ; i<10 ; i++) { + wait_ms(10); + cs_manage(&my_cs); + } + + cs_set_consign(&my_cs, 100000); + + while(1) { + wait_ms(10); + cs_manage(&my_cs); + } + + return 0; +} + + diff --git a/modules/devices/control_system/control_system_manager/test/pid_config.h b/modules/devices/control_system/control_system_manager/test/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/modules/devices/control_system/control_system_manager/test/uart_config.h b/modules/devices/control_system/control_system_manager/test/uart_config.h new file mode 100644 index 0000000..12e0f66 --- /dev/null +++ b/modules/devices/control_system/control_system_manager/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.10.1 2006-11-26 21:06:03 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/control_system/filters/CVS/Entries b/modules/devices/control_system/filters/CVS/Entries new file mode 100644 index 0000000..7bc12e9 --- /dev/null +++ b/modules/devices/control_system/filters/CVS/Entries @@ -0,0 +1,6 @@ +/filter.h/1.1.10.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +D/biquad//// +D/pid//// +D/quadramp//// +D/quadramp_derivate//// +D/ramp//// diff --git a/modules/devices/control_system/filters/CVS/Repository b/modules/devices/control_system/filters/CVS/Repository new file mode 100644 index 0000000..30b5c8c --- /dev/null +++ b/modules/devices/control_system/filters/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters diff --git a/modules/devices/control_system/filters/CVS/Root b/modules/devices/control_system/filters/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/CVS/Tag b/modules/devices/control_system/filters/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/CVS/Template b/modules/devices/control_system/filters/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/biquad/CVS/Entries b/modules/devices/control_system/filters/biquad/CVS/Entries new file mode 100644 index 0000000..d6d2f74 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/biquad.c/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/biquad.h/1.2.2.3/Wed May 23 17:18:13 2007//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/control_system/filters/biquad/CVS/Repository b/modules/devices/control_system/filters/biquad/CVS/Repository new file mode 100644 index 0000000..95aa5c1 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/biquad diff --git a/modules/devices/control_system/filters/biquad/CVS/Root b/modules/devices/control_system/filters/biquad/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/biquad/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/biquad/CVS/Tag b/modules/devices/control_system/filters/biquad/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/biquad/CVS/Template b/modules/devices/control_system/filters/biquad/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/biquad/Makefile b/modules/devices/control_system/filters/biquad/Makefile new file mode 100644 index 0000000..2e083a8 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/Makefile @@ -0,0 +1,6 @@ +TARGET = biquad + +# List C source files here. (C dependencies are automatically generated.) +SRC = biquad.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/control_system/filters/biquad/biquad.c b/modules/devices/control_system/filters/biquad/biquad.c new file mode 100644 index 0000000..11aaf10 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/biquad.c @@ -0,0 +1,144 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: biquad.c,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + + +#include <biquad.h> +#include <string.h> + +/** init sets an unity filter, as usual */ +void biquad_init (struct biquad_filter * p) +{ + uint8_t flags; + IRQ_LOCK(flags); + + /* set all structure to 0 */ + memset(p, 0, sizeof(struct biquad_filter)); + + /* unity filter */ + p-> b0=1; + + IRQ_UNLOCK(flags); +} + +/** this is useful for cleaning the filter memories before a new data + * set. With this you avoid having old data in the filter memories + * when beginning to filter a new stream. Can also be used after + * changing the coefficients, to avoid jumps of the output value. + */ +void biquad_flush_memories(struct biquad_filter *p) +{ + uint8_t flags; + IRQ_LOCK(flags); + + /* empty mem cells */ + p->mem_in_1 = 0; + p->mem_in_2 = 0; + p->mem_out_1 = 0; + p->mem_out_2 = 0; + + IRQ_UNLOCK(flags); +} + +/** accessors to coefficients */ +void biquad_set_numerator_coeffs(struct biquad_filter *p, int16_t b0, int16_t b1, int16_t b2) +{ + uint8_t flags; + IRQ_LOCK(flags); + + p->b0 = b0; + p->b1 = b1; + p->b2 = b2; + + IRQ_UNLOCK(flags); +} + +void biquad_set_deniminator_coeffs(struct biquad_filter *p, int16_t a1, int16_t a2) +{ + uint8_t flags; + IRQ_LOCK(flags); + + p->a1 = -a1; + p->a2 = -a2; + + IRQ_UNLOCK(flags); +} + +void biquad_set_divisor_shifts(struct biquad_filter *p, uint8_t recursive_shift, uint8_t out_shift) +{ + uint8_t flags; + IRQ_LOCK(flags); + + p-> out_shift = out_shift; + p-> recursive_shift = recursive_shift; + + IRQ_UNLOCK(flags); +} + +void biquad_set_series_son(struct biquad_filter *p, struct biquad_filter *son) +{ + uint8_t flags; + IRQ_LOCK(flags); + + p->son = son; + + IRQ_UNLOCK(flags); +} + +/** filter processing, 1 iteration. + This function is not protected against writing in the structure while execution is ongoing! */ +int32_t biquad_do_filter(void * data , int32_t in) +{ + + int32_t output; + + struct biquad_filter * p = data; + + /* filter computation */ + output = p->b0 * in; + + output += p->b1 * p->mem_in_1; + output += p->b2 * p->mem_in_2; + + output += p->a1 * p->mem_out_1; /* minus, placed on the accessor */ + output += p->a2 * p->mem_out_2; /* minus, placed on the accessor */ + + + + /* update of the memories for next iteration */ + p->mem_in_2 = p->mem_in_1; + p->mem_in_1 = in; + + p->mem_out_2 = p-> mem_out_1; + p->mem_out_1 = output >> p-> recursive_shift; // recursive shift, this corresponds to a division on the a1 and a2 terms. + + + /* output division with shifting */ + output >>= p-> out_shift; + + + /* execute series filter */ + if(p->son != NULL) + output = biquad_do_filter(p->son, output); + + /* finished */ + return output; + +} diff --git a/modules/devices/control_system/filters/biquad/biquad.h b/modules/devices/control_system/filters/biquad/biquad.h new file mode 100644 index 0000000..5a1deb6 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/biquad.h @@ -0,0 +1,97 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: biquad.h,v 1.2.2.3 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#ifndef _BIQUAD_H_ +#define _BIQUAD_H_ + +#include <aversive.h> +#include <stdlib.h> + +/** this is the biquad structure */ +struct biquad_filter +{ + + int16_t b0, b1, b2; + int16_t a1, a2; /* never access it directly, use accessors */ + + uint8_t out_shift; + uint8_t recursive_shift; + + int32_t mem_in_1; + int32_t mem_in_2; + int32_t mem_out_1; + int32_t mem_out_2; + + struct biquad_filter * son; + +}; + + + + +/** Prototyping */ + +/** + * init sets an unity filter, as usual initialization is absolutely + * necessary ! + */ +extern void biquad_init (struct biquad_filter * p); + + +extern void biquad_set_numerator_coeffs (struct biquad_filter *p, int16_t b0, int16_t b1, int16_t b2); +extern void biquad_set_deniminator_coeffs(struct biquad_filter *p, int16_t a1, int16_t a2); + +extern void biquad_set_divisor_shifts(struct biquad_filter *p, uint8_t recursive_shift, uint8_t out_shift); + +/** + * this sets a filter to put in series. + * use as following : + * + * biquad_set_series_son(& filter1, &filter2) + * + * then please use ONLY the filter1. The filter 2 will recursively + * be called into the filter 1 function : + * output = biquad_do_filter(& filter1, input); + * + * You can put in series as much biquad filters as you want. + */ +extern void biquad_set_series_son(struct biquad_filter *p, struct biquad_filter *son); + +/** + * this is useful for cleaning the filter memories before a new data + * set. + * + * With this you avoid having old data in the filter memories when + * beginning to filter a new stream. Can also be used after + * changing the coefficients, to avoid jumps of the output value. + */ +extern void biquad_flush_memories(struct biquad_filter *p); + + +/** + * filter processing, 1 iteration. + * This function is not protected against writing in the structure while + * execution is ongoing! + */ +extern int32_t biquad_do_filter(void * data , int32_t in); + + +#endif diff --git a/modules/devices/control_system/filters/biquad/config/CVS/Entries b/modules/devices/control_system/filters/biquad/config/CVS/Entries new file mode 100644 index 0000000..068e8f3 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/config/CVS/Entries @@ -0,0 +1,2 @@ +/biquad_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/biquad/config/CVS/Repository b/modules/devices/control_system/filters/biquad/config/CVS/Repository new file mode 100644 index 0000000..de97962 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/biquad/config diff --git a/modules/devices/control_system/filters/biquad/config/CVS/Root b/modules/devices/control_system/filters/biquad/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/biquad/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/biquad/config/CVS/Tag b/modules/devices/control_system/filters/biquad/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/biquad/config/CVS/Template b/modules/devices/control_system/filters/biquad/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/biquad/config/biquad_config.h b/modules/devices/control_system/filters/biquad/config/biquad_config.h new file mode 100644 index 0000000..fbedbb4 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/config/biquad_config.h @@ -0,0 +1,29 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef BIQUAD_CONFIG_H +#define BIQUAD_CONFIG_H 1 // version 1 + + + + + +#endif diff --git a/modules/devices/control_system/filters/biquad/test/CVS/Entries b/modules/devices/control_system/filters/biquad/test/CVS/Entries new file mode 100644 index 0000000..d917634 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/error_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/main.c/1.2.2.3/Wed May 23 17:18:13 2007//Tb_zer0 +/uart_config.h/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +D/results//// diff --git a/modules/devices/control_system/filters/biquad/test/CVS/Repository b/modules/devices/control_system/filters/biquad/test/CVS/Repository new file mode 100644 index 0000000..ecfc82b --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/biquad/test diff --git a/modules/devices/control_system/filters/biquad/test/CVS/Root b/modules/devices/control_system/filters/biquad/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/biquad/test/CVS/Tag b/modules/devices/control_system/filters/biquad/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/biquad/test/CVS/Template b/modules/devices/control_system/filters/biquad/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/biquad/test/Makefile b/modules/devices/control_system/filters/biquad/test/Makefile new file mode 100644 index 0000000..5b0709b --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/control_system/filters/biquad/test/error_config.h b/modules/devices/control_system/filters/biquad/test/error_config.h new file mode 100644 index 0000000..851e7c3 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/control_system/filters/biquad/test/main.c b/modules/devices/control_system/filters/biquad/test/main.c new file mode 100644 index 0000000..ba64fe7 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/main.c @@ -0,0 +1,64 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2.2.3 2007-05-23 17:18:13 zer0 Exp $ + * + */ +#include <uart.h> +#include <biquad.h> +#include <aversive/wait.h> + +#include <stdio.h> +#include <avr/pgmspace.h> + +int main(void) +{ + + + + struct biquad_filter filter; + + + // filter as in the wiki documentation + biquad_init(&filter); + biquad_set_numerator_coeffs (&filter, 5, 10, 5); + biquad_set_deniminator_coeffs(&filter,-400, 164); + biquad_set_divisor_shifts(&filter, 8, 8); + + // init uart + uart_init(); + fdevopen(uart0_send,NULL, 0); + + + + while(1) { + // variables + int32_t noise, filtered_noise; + + // generate white noise (is rand a white noise ??) + noise = rand() / (RAND_MAX /100); // from 0 to 100 + + // apply filter + filtered_noise = biquad_do_filter(& filter, noise); + + // output in a logging format : n10f30\n + printf_P(PSTR("n%lif%li\n"), noise, filtered_noise); + + } +} + + diff --git a/modules/devices/control_system/filters/biquad/test/results/CVS/Entries b/modules/devices/control_system/filters/biquad/test/results/CVS/Entries new file mode 100644 index 0000000..d438b9c --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/CVS/Entries @@ -0,0 +1,7 @@ +/affich_telemetry.m/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/amplitude.png/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/biquad_spectrum.png/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/get_telemetry.m/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/output.log/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/telemetry.m/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/biquad/test/results/CVS/Repository b/modules/devices/control_system/filters/biquad/test/results/CVS/Repository new file mode 100644 index 0000000..50e8304 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/biquad/test/results diff --git a/modules/devices/control_system/filters/biquad/test/results/CVS/Root b/modules/devices/control_system/filters/biquad/test/results/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/biquad/test/results/CVS/Tag b/modules/devices/control_system/filters/biquad/test/results/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/biquad/test/results/CVS/Template b/modules/devices/control_system/filters/biquad/test/results/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/biquad/test/results/affich_telemetry.m b/modules/devices/control_system/filters/biquad/test/results/affich_telemetry.m new file mode 100644 index 0000000..b7f51fa --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/affich_telemetry.m @@ -0,0 +1,54 @@ +function affich_telemetry(tableau) + +reunir_graphs = 0; + + + +% labels asserv +labels = { 't Couple moteur';'g Signal Gyro';'G Intégrale Gyro' ;'v Vitesse'; 'a Acceleration';'C position centre de gravité';'p position moteurs'}; + + +if length(tableau) ~=0 + + taille = size(tableau); + + figure; + + for graph = 1:taille(2) + if reunir_graphs == 0 + subplot(taille(2), 1, graph); + end + + hold on; + + data = tableau(2:end,graph); + + plot(data); + + %title + titre = char(tableau(1,graph)); + for i=1:length(labels) + if(max(strncmp(labels(i),char(tableau(1,graph)),1))) + titre = labels(i); + end + end + + title(strcat( ... + titre , ... + ' - max: ', num2str(max(data)) , ... + ' min: ', num2str(min(data)) , ... + ' avg: ', num2str(mean(data)) )); + end + + % histogramme sur la 4eme donnee + data = tableau(2:end,1); + + %figure; + %hist(data,length(data)); + + +end + +clear graph taille data i + + diff --git a/modules/devices/control_system/filters/biquad/test/results/amplitude.png b/modules/devices/control_system/filters/biquad/test/results/amplitude.png new file mode 100644 index 0000000..2196f33 Binary files /dev/null and b/modules/devices/control_system/filters/biquad/test/results/amplitude.png differ diff --git a/modules/devices/control_system/filters/biquad/test/results/biquad_spectrum.png b/modules/devices/control_system/filters/biquad/test/results/biquad_spectrum.png new file mode 100644 index 0000000..a412bd7 Binary files /dev/null and b/modules/devices/control_system/filters/biquad/test/results/biquad_spectrum.png differ diff --git a/modules/devices/control_system/filters/biquad/test/results/get_telemetry.m b/modules/devices/control_system/filters/biquad/test/results/get_telemetry.m new file mode 100644 index 0000000..80be1ef --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/get_telemetry.m @@ -0,0 +1,41 @@ + + + +filename = 'output.log'; + +display('Lecture telemetrie ...') +tableau = telemetry(filename); +display('Fin telemetrie') +clear filename; + +affich_telemetry(tableau); + +% titre +subplot(2, 1, 1); +title('input : pseudorandom noise'); + +subplot(2, 1, 2); +title('filtered output'); + + +tableau = tableau(2:end, :); + + +% display spectrums + + +figure; +Y1 = fft(tableau(:, 1),512); +Pyy1 = Y1.* conj(Y1) / 512; +f = 1000*(0:256)/512; +semilogy(f,Pyy1(1:257)) + +hold on; + +Y1 = fft(tableau(:, 2),512); +Pyy1 = Y1.* conj(Y1) / 512; +f = 1000*(0:256)/512; +semilogy(f,Pyy1(1:257), '-r') + +xlabel('frequency (Hz)') +legend('in', 'out'); \ No newline at end of file diff --git a/modules/devices/control_system/filters/biquad/test/results/output.log b/modules/devices/control_system/filters/biquad/test/results/output.log new file mode 100644 index 0000000..28bbbbd --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/results/output.log @@ -0,0 +1,1351 @@ +n51f0 +n46f2 +n35f6 +n9f10 +n43f13 +n71f17 +n11f22 +n7f25 +n37f26 +n3f26 +n19f25 +n47f24 +n14f23 +n71f23 +n66f25 +n43f29 +n44f33 +n50f36 +n52f38 +n57f40 +n36f42 +n33f43 +n17f42 +n8f39 +n39f35 +n80f32 +n1f31 +n23f29 +n93f28 +n22f29 +n78f31 +n41f34 +n11f36 +n63f36 +n86f37 +n15f39 +n60f40 +n11f40 +n62f39 +n83f39 +n94f42 +n41f46 +n27f48 +n92f49 +n92f51 +n54f54 +n81f57 +n16f59 +n32f58 +n65f55 +n0f51 +n63f46 +n78f43 +n29f42 +n79f42 +n21f42 +n40f41 +n80f40 +n86f41 +n14f43 +n34f43 +n41f42 +n71f41 +n14f41 +n57f40 +n25f39 +n4f37 +n27f34 +n67f31 +n21f30 +n34f29 +n14f28 +n83f28 +n94f31 +n52f36 +n92f42 +n6f47 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+% waiting for first input +while 1 + read = fgetl(SER_PORT_ID); + if ~ strcmp(read, '') + break; + end +end + +read = fgetl(SER_PORT_ID); % skip first entry, coz could be incomplete + +% main loop +while 1 + + %exit when finished + if strcmp(read, '') || ~isstr(read) + fclose(SER_PORT_ID); + break; + end + + % convertir + result = sscanf(read,'%c%i'); + + sortie(time, :) = NaN; + for no_param=1:length(result)/2 + % classement + a_classer = 1; + for i=1:length(labels) + if strcmp(labels{i}, char(result(no_param*2 -1))) + sortie(time, i) = result(no_param*2); + a_classer = 0; + break; + end + end + % ajout + if a_classer + labels{length(labels)+1} = char(result(no_param*2 -1)); + sortie(1, length(labels)) = result(no_param*2 -1); % label 2 + sortie(time, length(labels)) = result(no_param*2); + end + end + + % lecture suivant + read = fgetl(SER_PORT_ID); + time = time +1; +end + + + + + + diff --git a/modules/devices/control_system/filters/biquad/test/uart_config.h b/modules/devices/control_system/filters/biquad/test/uart_config.h new file mode 100644 index 0000000..19b7c9d --- /dev/null +++ b/modules/devices/control_system/filters/biquad/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.2.2 2007-05-12 16:42:39 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/control_system/filters/filter.h b/modules/devices/control_system/filters/filter.h new file mode 100755 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/pid/CVS/Entries b/modules/devices/control_system/filters/pid/CVS/Entries new file mode 100644 index 0000000..fab8d07 --- /dev/null +++ b/modules/devices/control_system/filters/pid/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:03 2006//Tb_zer0 +/pid.c/1.5.4.10/Thu Mar 5 22:02:55 2009//Tb_zer0 +/pid.h/1.4.4.7/Fri May 9 08:24:33 2008//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/control_system/filters/pid/CVS/Repository b/modules/devices/control_system/filters/pid/CVS/Repository new file mode 100644 index 0000000..4f88564 --- /dev/null +++ b/modules/devices/control_system/filters/pid/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/pid diff --git a/modules/devices/control_system/filters/pid/CVS/Root b/modules/devices/control_system/filters/pid/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/pid/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/pid/CVS/Tag b/modules/devices/control_system/filters/pid/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/pid/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/pid/CVS/Template b/modules/devices/control_system/filters/pid/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/pid/Makefile b/modules/devices/control_system/filters/pid/Makefile new file mode 100755 index 0000000..2ecee1a --- /dev/null +++ b/modules/devices/control_system/filters/pid/Makefile @@ -0,0 +1,6 @@ +TARGET = pid + +# List C source files here. (C dependencies are automatically generated.) +SRC = pid.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/control_system/filters/pid/config/CVS/Entries b/modules/devices/control_system/filters/pid/config/CVS/Entries new file mode 100644 index 0000000..8197dca --- /dev/null +++ b/modules/devices/control_system/filters/pid/config/CVS/Entries @@ -0,0 +1,2 @@ +/pid_config.h/1.1.10.2/Wed Dec 5 18:08:39 2007//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/pid/config/CVS/Repository b/modules/devices/control_system/filters/pid/config/CVS/Repository new file mode 100644 index 0000000..243d28a --- /dev/null +++ b/modules/devices/control_system/filters/pid/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/pid/config diff --git a/modules/devices/control_system/filters/pid/config/CVS/Root b/modules/devices/control_system/filters/pid/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/pid/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/pid/config/CVS/Tag b/modules/devices/control_system/filters/pid/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/pid/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/pid/config/CVS/Template b/modules/devices/control_system/filters/pid/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/pid/config/pid_config.h b/modules/devices/control_system/filters/pid/config/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/modules/devices/control_system/filters/pid/config/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/modules/devices/control_system/filters/pid/pid.c b/modules/devices/control_system/filters/pid/pid.c new file mode 100755 index 0000000..498d70a --- /dev/null +++ b/modules/devices/control_system/filters/pid/pid.c @@ -0,0 +1,235 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pid.c,v 1.5.4.10 2009-03-05 22:02:55 zer0 Exp $ + * + */ + +#include <string.h> +#include <pid.h> + + +/** this function will initialize all fieds of pid structure to 0 */ +void pid_init(struct pid_filter *p) +{ + uint8_t flags; + IRQ_LOCK(flags); + memset(p, 0, sizeof(*p)); + p->gain_P = 1 ; + p->derivate_nb_samples = 1; + IRQ_UNLOCK(flags); +} + +/** this function will initialize all fieds of pid structure to 0, + * except configuration */ +void pid_reset(struct pid_filter *p) +{ + uint8_t flags; + IRQ_LOCK(flags); + memset(p->prev_samples, 0, sizeof(p->prev_samples)); + p->integral = 0; + p->prev_D = 0; + p->prev_out = 0; + IRQ_UNLOCK(flags); +} + +void pid_set_gains(struct pid_filter *p, int16_t gp, int16_t gi, int16_t gd) +{ + uint8_t flags; + IRQ_LOCK(flags); + p->gain_P = gp; + p->gain_I = gi; + p->gain_D = gd; + IRQ_UNLOCK(flags); +} + +void pid_set_maximums(struct pid_filter *p, int32_t max_in, int32_t max_I, int32_t max_out) +{ + uint8_t flags; + IRQ_LOCK(flags); + p->max_in = max_in; + p->max_I = max_I; + p->max_out = max_out; + IRQ_UNLOCK(flags); +} + +void pid_set_out_shift(struct pid_filter *p, uint8_t out_shift) +{ + uint8_t flags; + IRQ_LOCK(flags); + p->out_shift=out_shift; + IRQ_UNLOCK(flags); +} + +int8_t pid_set_derivate_filter(struct pid_filter *p, uint8_t nb_samples) +{ + uint8_t flags; + int8_t ret; + IRQ_LOCK(flags); + if (nb_samples > PID_DERIVATE_FILTER_MAX_SIZE) { + ret = -1; + } + else { + p->derivate_nb_samples = nb_samples; + ret = 0; + } + IRQ_UNLOCK(flags); + return ret; +} + +int16_t pid_get_gain_P(struct pid_filter *p) +{ + return (p->gain_P); +} + +int16_t pid_get_gain_I(struct pid_filter *p) +{ + return (p->gain_I); +} + +int16_t pid_get_gain_D(struct pid_filter *p) +{ + return (p->gain_D); +} + + +int32_t pid_get_max_in(struct pid_filter *p) +{ + return (p->max_in); +} + +int32_t pid_get_max_I(struct pid_filter *p) +{ + return (p->max_I); +} + +int32_t pid_get_max_out(struct pid_filter *p) +{ + return (p->max_out); +} + + +uint8_t pid_get_out_shift(struct pid_filter *p) +{ + return (p->out_shift); +} + +uint8_t pid_get_derivate_filter(struct pid_filter *p) +{ + return (p->derivate_nb_samples); +} + +int32_t pid_get_value_I(struct pid_filter *p) +{ + uint8_t flags; + int32_t ret; + IRQ_LOCK(flags); + ret = (p->integral); + IRQ_UNLOCK(flags); + return ret; +} + +int32_t pid_get_value_in(struct pid_filter *p) +{ + uint8_t flags; + int32_t ret; + IRQ_LOCK(flags); + ret = p->prev_samples[p->index]; + IRQ_UNLOCK(flags); + return ret; +} + +int32_t pid_get_value_D(struct pid_filter *p) +{ + uint8_t flags; + int32_t ret; + IRQ_LOCK(flags); + ret = p->prev_D; + IRQ_UNLOCK(flags); + return ret; +} + +int32_t pid_get_value_out(struct pid_filter *p) +{ + uint8_t flags; + int32_t ret; + IRQ_LOCK(flags); + ret = (p->prev_out); + IRQ_UNLOCK(flags); + return ret; +} + +/* first parameter should be a (struct pid_filter *) */ +int32_t pid_do_filter(void * data, int32_t in) +{ + int32_t derivate ; + int32_t command ; + struct pid_filter * p = data; + uint8_t prev_index; + + /* + * Integral value : the integral become bigger with time .. (think + * to area of graph, we add one area to the previous) so, + * integral = previous integral + current value + */ + + /* derivate value + * f(t+h) - f(t) with f(t+h) = current value + * derivate = ------------- f(t) = previous value + * h + * so derivate = current error - previous error + * + * We can apply a filter to reduce noise on the derivate term, + * by using a bigger period. + */ + + prev_index = p->index + 1; + if (prev_index >= p->derivate_nb_samples) + prev_index = 0; + + /* saturate input... it influences integral an derivate */ + if (p->max_in) + S_MAX(in, p->max_in) ; + + derivate = in - p->prev_samples[prev_index]; + p->integral += in ; + + if (p->max_I) + S_MAX(p->integral, p->max_I) ; + + /* so, command = P.coef_P + I.coef_I + D.coef_D */ + command = in * p->gain_P + + p->integral * p->gain_I + + (derivate * p->gain_D) / p->derivate_nb_samples ; + + if ( command < 0 ) + command = -( -command >> p->out_shift ); + else + command = command >> p->out_shift ; + + if (p->max_out) + S_MAX (command, p->max_out) ; + + + /* backup of current error value (for the next calcul of derivate value) */ + p->prev_samples[p->index] = in ; + p->index = prev_index; /* next index is prev_index */ + p->prev_D = derivate ; + p->prev_out = command ; + + return command; +} diff --git a/modules/devices/control_system/filters/pid/pid.h b/modules/devices/control_system/filters/pid/pid.h new file mode 100755 index 0000000..5961c31 --- /dev/null +++ b/modules/devices/control_system/filters/pid/pid.h @@ -0,0 +1,91 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pid.h,v 1.4.4.7 2008-05-09 08:24:33 zer0 Exp $ + * + */ + +#ifndef _PID_H_ +#define _PID_H_ + +#include <aversive.h> +#include <stdlib.h> + +#include <pid_config.h> + + +/** this is the pid_filter structure*/ +struct pid_filter +{ + int16_t gain_P; /**< Gain of Proportionnal module */ + int16_t gain_I; /**< Gain of Integral module */ + int16_t gain_D; /**< Gain of Derivate module */ + + uint8_t out_shift; /**< big common divisor for output */ + + uint8_t derivate_nb_samples; /**< sample count for derivate filter */ + uint8_t index; /**< index in circular buffer below */ + int32_t prev_samples[PID_DERIVATE_FILTER_MAX_SIZE]; /**< previous in (circular buf) */ + + int32_t max_in; /**< In saturation levels */ + int32_t max_I; /**< Integral saturation levels */ + int32_t max_out; /**< Out saturation levels */ + + int32_t integral; /**< previous integral parameter */ + int32_t prev_D; /**< previous derivate parameter */ + int32_t prev_out; /**< previous out command (for debug only) */ +}; + +/** init pid */ +void pid_init(struct pid_filter *p); + +/** reset state (derivate and intergral state) */ +void pid_reset(struct pid_filter *p); + +/* Use these functions to change one parameter on pid_filter structure */ +void pid_set_gains(struct pid_filter *p, int16_t gp, int16_t gi, int16_t gd) ; +void pid_set_maximums(struct pid_filter *p, int32_t max_in, int32_t max_I, int32_t max_out); +void pid_set_out_shift(struct pid_filter *p, uint8_t out_shift); +int8_t pid_set_derivate_filter(struct pid_filter *p, uint8_t nb_samples); + +/* accessors of all parameter of pid structure*/ +int16_t pid_get_gain_P(struct pid_filter *p); +int16_t pid_get_gain_I(struct pid_filter *p); +int16_t pid_get_gain_D(struct pid_filter *p); +int32_t pid_get_max_in(struct pid_filter *p); +int32_t pid_get_max_I(struct pid_filter *p); +int32_t pid_get_max_out(struct pid_filter *p); +uint8_t pid_get_out_shift(struct pid_filter *p); +uint8_t pid_get_derivate_filter(struct pid_filter *p); + +/** get the sum of all nput samples since the filter initialisation */ +int32_t pid_get_value_I(struct pid_filter *p); + +/** get previous input value */ +int32_t pid_get_value_in(struct pid_filter *p); + +/** get previous derivate value (without gain) */ +int32_t pid_get_value_D(struct pid_filter *p); + +/** get previous output value */ +int32_t pid_get_value_out(struct pid_filter *p); + +/** PID process */ +int32_t pid_do_filter(void *p, int32_t in); + + +#endif diff --git a/modules/devices/control_system/filters/pid/test/.config b/modules/devices/control_system/filters/pid/test/.config new file mode 100644 index 0000000..3ceea30 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +CONFIG_MODULE_SCHEDULER_USE_TIMERS=y +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +CONFIG_MODULE_PID=y +CONFIG_MODULE_PID_CREATE_CONFIG=y +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/control_system/filters/pid/test/CVS/Entries b/modules/devices/control_system/filters/pid/test/CVS/Entries new file mode 100644 index 0000000..8d8f051 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.7.4.10/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/error_config.h/1.3.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/main.c/1.4.6.3/Wed Dec 5 18:08:40 2007//Tb_zer0 +/pid_config.h/1.1.10.2/Wed Dec 5 18:08:40 2007//Tb_zer0 +/uart_config.h/1.1.10.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/pid/test/CVS/Repository b/modules/devices/control_system/filters/pid/test/CVS/Repository new file mode 100644 index 0000000..352f858 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/pid/test diff --git a/modules/devices/control_system/filters/pid/test/CVS/Root b/modules/devices/control_system/filters/pid/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/pid/test/CVS/Tag b/modules/devices/control_system/filters/pid/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/pid/test/CVS/Template b/modules/devices/control_system/filters/pid/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/pid/test/Makefile b/modules/devices/control_system/filters/pid/test/Makefile new file mode 100755 index 0000000..5b0709b --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/control_system/filters/pid/test/error_config.h b/modules/devices/control_system/filters/pid/test/error_config.h new file mode 100644 index 0000000..f3f6236 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.3.6.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/control_system/filters/pid/test/main.c b/modules/devices/control_system/filters/pid/test/main.c new file mode 100755 index 0000000..3b38a00 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/main.c @@ -0,0 +1,51 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4.6.3 2007-12-05 18:08:40 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <pid.h> + +int32_t tab[] = { 0, 1, 2, 5, 6, 0, 0, 1, 0, 0, -10, -8, -5, -1 }; + +int main(void) +{ + struct pid_filter p; + int32_t val; + int i; + + pid_init(&p); + pid_set_gains(&p, 1000, 30, 5000); + pid_set_maximums(&p, 0, 50000, 4095); + pid_set_out_shift(&p, 10); + pid_set_derivate_filter(&p, 4); + + for (i=0; i < (sizeof(tab)/sizeof(int32_t)); i++) { + val = pid_do_filter(&p, tab[i]); + printf("in = %" PRId32 "\n", tab[i]); + printf("out = %" PRId32 "\n", val); + printf("I = %" PRId32 "\n", p.integral); + printf("D = %" PRId32 "\n\n", p.prev_D); + } + + return 0; +} + + diff --git a/modules/devices/control_system/filters/pid/test/pid_config.h b/modules/devices/control_system/filters/pid/test/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/modules/devices/control_system/filters/pid/test/uart_config.h b/modules/devices/control_system/filters/pid/test/uart_config.h new file mode 100755 index 0000000..0f24410 --- /dev/null +++ b/modules/devices/control_system/filters/pid/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.10.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/control_system/filters/quadramp/CVS/Entries b/modules/devices/control_system/filters/quadramp/CVS/Entries new file mode 100644 index 0000000..38d414f --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/quadramp.c/1.4.4.7/Mon May 18 12:29:51 2009//Tb_zer0 +/quadramp.h/1.3.4.4/Mon May 18 12:29:51 2009//Tb_zer0 +D/test//// diff --git a/modules/devices/control_system/filters/quadramp/CVS/Repository b/modules/devices/control_system/filters/quadramp/CVS/Repository new file mode 100644 index 0000000..c854213 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/quadramp diff --git a/modules/devices/control_system/filters/quadramp/CVS/Root b/modules/devices/control_system/filters/quadramp/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/quadramp/CVS/Tag b/modules/devices/control_system/filters/quadramp/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/quadramp/CVS/Template b/modules/devices/control_system/filters/quadramp/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/quadramp/Makefile b/modules/devices/control_system/filters/quadramp/Makefile new file mode 100644 index 0000000..1f812dc --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/Makefile @@ -0,0 +1,6 @@ +TARGET = quadramp + +# List C source files here. (C dependencies are automatically generated.) +SRC = quadramp.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/control_system/filters/quadramp/quadramp.c b/modules/devices/control_system/filters/quadramp/quadramp.c new file mode 100644 index 0000000..847d01a --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/quadramp.c @@ -0,0 +1,193 @@ + +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: quadramp.c,v 1.4.4.7 2009-05-18 12:29:51 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> +#include <math.h> + +#include <aversive.h> +#include <quadramp.h> + +#define NEXT(n, i) (((n) + (i)/(n)) >> 1) + +void quadramp_init(struct quadramp_filter * q) +{ + uint8_t flags; + IRQ_LOCK(flags); + memset(q, 0, sizeof(*q)); + IRQ_UNLOCK(flags); +} + + +void quadramp_reset(struct quadramp_filter * q) +{ + q->previous_var = 0; + q->previous_out = 0; + q->previous_in = 0; +} + +void quadramp_set_2nd_order_vars(struct quadramp_filter * q, + uint32_t var_2nd_ord_pos, + uint32_t var_2nd_ord_neg) +{ + uint8_t flags; + IRQ_LOCK(flags); + q->var_2nd_ord_pos = var_2nd_ord_pos; + q->var_2nd_ord_neg = var_2nd_ord_neg; + IRQ_UNLOCK(flags); +} + +void quadramp_set_1st_order_vars(struct quadramp_filter * q, + uint32_t var_1st_ord_pos, + uint32_t var_1st_ord_neg) +{ + uint8_t flags; + IRQ_LOCK(flags); + q->var_1st_ord_pos = var_1st_ord_pos; + q->var_1st_ord_neg = var_1st_ord_neg; + IRQ_UNLOCK(flags); +} + + +uint8_t quadramp_is_finished(struct quadramp_filter *q) +{ + return (q->previous_out == q->previous_in && + q->previous_var == 0); +} + +/** + * Process the ramp + * + * \param data should be a (struct quadramp_filter *) pointer + * \param in is the input of the filter + * + */ +int32_t quadramp_do_filter(void * data, int32_t in) +{ + struct quadramp_filter * q = data; + int32_t d ; + int32_t pos_target; + int32_t var_1st_ord_pos = 0; + int32_t var_1st_ord_neg = 0; + int32_t var_2nd_ord_pos = 0; + int32_t var_2nd_ord_neg = 0; + int32_t previous_var, previous_out ; + + if ( q->var_1st_ord_pos ) + var_1st_ord_pos = q->var_1st_ord_pos ; + + if ( q->var_1st_ord_neg ) + var_1st_ord_neg = -q->var_1st_ord_neg ; + + if ( q->var_2nd_ord_pos ) + var_2nd_ord_pos = q->var_2nd_ord_pos ; + + if ( q->var_2nd_ord_neg ) + var_2nd_ord_neg = -q->var_2nd_ord_neg ; + + previous_var = q->previous_var; + previous_out = q->previous_out; + + d = in - previous_out ; + + /* Deceleration ramp */ + if ( d > 0 && var_2nd_ord_neg) { + int32_t ramp_pos; + /* var_2nd_ord_neg < 0 */ + /* real EQ : sqrt( var_2nd_ord_neg^2/4 - 2.d.var_2nd_ord_neg ) + var_2nd_ord_neg/2 */ + ramp_pos = sqrt( (var_2nd_ord_neg*var_2nd_ord_neg)/4 - 2*d*var_2nd_ord_neg ) + var_2nd_ord_neg/2; + + if(ramp_pos < var_1st_ord_pos) + var_1st_ord_pos = ramp_pos ; + } + + else if (d < 0 && var_2nd_ord_pos) { + int32_t ramp_neg; + + /* var_2nd_ord_pos > 0 */ + /* real EQ : sqrt( var_2nd_ord_pos^2/4 - 2.d.var_2nd_ord_pos ) - var_2nd_ord_pos/2 */ + ramp_neg = -sqrt( (var_2nd_ord_pos*var_2nd_ord_pos)/4 - 2*d*var_2nd_ord_pos ) - var_2nd_ord_pos/2; + + /* ramp_neg < 0 */ + if(ramp_neg > var_1st_ord_neg) + var_1st_ord_neg = ramp_neg ; + } + + /* try to set the speed : can we reach the speed with our acceleration ? */ + /* si on va moins vite que la Vmax */ + if ( previous_var < var_1st_ord_pos ) { + /* acceleration would be to high, we reduce the speed */ + /* si rampe acceleration active ET qu'on ne peut pas atteindre Vmax, + * on sature Vmax a Vcourante + acceleration */ + if (var_2nd_ord_pos && ( var_1st_ord_pos - previous_var > var_2nd_ord_pos) ) + var_1st_ord_pos = previous_var + var_2nd_ord_pos ; + } + /* si on va plus vite que Vmax */ + else if ( previous_var > var_1st_ord_pos ) { + /* deceleration would be to high, we increase the speed */ + /* si rampe deceleration active ET qu'on ne peut pas atteindre Vmax, + * on sature Vmax a Vcourante + deceleration */ + if (var_2nd_ord_neg && ( var_1st_ord_pos - previous_var < var_2nd_ord_neg) ) + var_1st_ord_pos = previous_var + var_2nd_ord_neg; + } + + /* same for the neg */ + /* si on va plus vite que la Vmin (en negatif : en vrai la vitesse absolue est inferieure) */ + if ( previous_var > var_1st_ord_neg ) { + /* acceleration would be to high, we reduce the speed */ + /* si rampe deceleration active ET qu'on ne peut pas atteindre Vmin, + * on sature Vmax a Vcourante + deceleration */ + if (var_2nd_ord_neg && ( var_1st_ord_neg - previous_var < var_2nd_ord_neg) ) + var_1st_ord_neg = previous_var + var_2nd_ord_neg ; + } + /* si on va moins vite que Vmin (mais vitesse absolue superieure) */ + else if ( previous_var < var_1st_ord_neg ) { + /* deceleration would be to high, we increase the speed */ + /* si rampe acceleration active ET qu'on ne peut pas atteindre Vmin, + * on sature Vmax a Vcourante + deceleration */ + if (var_2nd_ord_pos && (var_1st_ord_neg - previous_var > var_2nd_ord_pos) ) + var_1st_ord_neg = previous_var + var_2nd_ord_pos; + } + + /* + * Position consign : can we reach the position with our speed ? + */ + if ( /* var_1st_ord_pos && */d > var_1st_ord_pos ) { + pos_target = previous_out + var_1st_ord_pos ; + previous_var = var_1st_ord_pos ; + } + else if ( /* var_1st_ord_neg && */d < var_1st_ord_neg ) { + pos_target = previous_out + var_1st_ord_neg ; + previous_var = var_1st_ord_neg ; + } + else { + pos_target = previous_out + d ; + previous_var = d ; + } + + // update previous_out and previous_var + q->previous_var = previous_var; + q->previous_out = pos_target; + q->previous_in = in; + + return pos_target ; +} diff --git a/modules/devices/control_system/filters/quadramp/quadramp.h b/modules/devices/control_system/filters/quadramp/quadramp.h new file mode 100644 index 0000000..69b95b3 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/quadramp.h @@ -0,0 +1,66 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: quadramp.h,v 1.3.4.4 2009-05-18 12:29:51 zer0 Exp $ + * + */ + +#ifndef _QUADRAMP_H_ +#define _QUADRAMP_H_ + +#include <aversive.h> + +struct quadramp_filter +{ + uint32_t var_2nd_ord_pos; + uint32_t var_2nd_ord_neg; + uint32_t var_1st_ord_pos; + uint32_t var_1st_ord_neg; + + int32_t previous_var; + int32_t previous_out; + int32_t previous_in; +}; + +/** Initialization of the filter */ +void quadramp_init(struct quadramp_filter *q); + +void quadramp_reset(struct quadramp_filter * q); + +void quadramp_set_2nd_order_vars(struct quadramp_filter *q, + uint32_t var_2nd_ord_pos, + uint32_t var_2nd_ord_neg); + +void quadramp_set_1st_order_vars(struct quadramp_filter *q, + uint32_t var_1st_ord_pos, + uint32_t var_1st_ord_neg); + +/** + * Return 1 when (filter_input == filter_output && 1st_ord variation + * is 0 --speed is 0-- ). + */ +uint8_t quadramp_is_finished(struct quadramp_filter *q); + +/** + * Process the ramp + * + * \param data should be a (struct quadramp_filter *) pointer + * \param in is the input of the filter + */ +int32_t quadramp_do_filter(void * data, int32_t in); + +#endif diff --git a/modules/devices/control_system/filters/quadramp/test/.config b/modules/devices/control_system/filters/quadramp/test/.config new file mode 100644 index 0000000..81400b6 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +CONFIG_OPTM_0=y +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +# CONFIG_OPTM_S is not set +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +CONFIG_MODULE_FIXED_POINT=y +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/control_system/filters/quadramp/test/CVS/Entries b/modules/devices/control_system/filters/quadramp/test/CVS/Entries new file mode 100644 index 0000000..fd82a20 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.7.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/main.c/1.3.4.2/Wed May 23 17:18:13 2007//Tb_zer0 +/plot/1.3.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/quadramp/test/CVS/Repository b/modules/devices/control_system/filters/quadramp/test/CVS/Repository new file mode 100644 index 0000000..5697f23 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/quadramp/test diff --git a/modules/devices/control_system/filters/quadramp/test/CVS/Root b/modules/devices/control_system/filters/quadramp/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/quadramp/test/CVS/Tag b/modules/devices/control_system/filters/quadramp/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/quadramp/test/CVS/Template b/modules/devices/control_system/filters/quadramp/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/quadramp/test/Makefile b/modules/devices/control_system/filters/quadramp/test/Makefile new file mode 100644 index 0000000..ba846b7 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/Makefile @@ -0,0 +1,26 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +.PHONY:plot +plot: all + ./main > data + ./plot \ No newline at end of file diff --git a/modules/devices/control_system/filters/quadramp/test/main.c b/modules/devices/control_system/filters/quadramp/test/main.c new file mode 100644 index 0000000..78a747f --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/main.c @@ -0,0 +1,83 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.3.4.2 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <quadramp.h> + +#include <stdio.h> + +int main(void) +{ + struct quadramp_filter q; + + int32_t in=0, out=0, prev_out=0; + int32_t i=0; + + quadramp_init(&q); + + for (i=0 ; i<4000 ; i++) { + switch(i) { + + case 0: + quadramp_set_1st_order_vars(&q, 50, 100); + quadramp_set_2nd_order_vars(&q, 1, 2); + in = 10000; + break; + + case 600: + in = 9000; + break; + + case 630: + in = 10000; + break; + + case 1000: + in = -5000; + break; + + case 1500: + in = -4000; + break; + + case 2000: + quadramp_set_1st_order_vars(&q, 10, 10); + quadramp_set_2nd_order_vars(&q, 2, 2); + in = 10000; + break; + + case 3000: + quadramp_set_1st_order_vars(&q, 100, 100); + break; + + + default: + break; + } + + out = quadramp_do_filter(&q, in); + printf("%" SCNu32 " %" SCNu32 " %" SCNu32 " %" SCNu32 "\n", i, in, out, out-prev_out); + + prev_out = out; + } + + return 0; +} diff --git a/modules/devices/control_system/filters/quadramp/test/plot b/modules/devices/control_system/filters/quadramp/test/plot new file mode 100755 index 0000000..e957650 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp/test/plot @@ -0,0 +1,20 @@ +#!/bin/bash + +(gnuplot <<EOF +set terminal postscript eps color "Times-Roman" 16 +set output 'in-out.eps' +set multiplot +set yrange [-6000:11000] +plot "data" using 1:2 with lines, "data" using 1:3 with lines +EOF +) & + +(gnuplot <<EOF +set terminal postscript eps color "Times-Roman" 16 +set output 'speed.eps' +set multiplot +set yrange [-110:110] +plot "data" using 1:4 with lines +EOF +)& + diff --git a/modules/devices/control_system/filters/quadramp_derivate/CVS/Entries b/modules/devices/control_system/filters/quadramp_derivate/CVS/Entries new file mode 100644 index 0000000..18f84b7 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/quadramp_derivate.c/1.2.2.4/Sat Nov 24 22:12:07 2007//Tb_zer0 +/quadramp_derivate.h/1.2.2.3/Wed May 23 17:18:13 2007//Tb_zer0 +D/test//// diff --git a/modules/devices/control_system/filters/quadramp_derivate/CVS/Repository b/modules/devices/control_system/filters/quadramp_derivate/CVS/Repository new file mode 100644 index 0000000..f3c6a56 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/quadramp_derivate diff --git a/modules/devices/control_system/filters/quadramp_derivate/CVS/Root b/modules/devices/control_system/filters/quadramp_derivate/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/quadramp_derivate/CVS/Tag b/modules/devices/control_system/filters/quadramp_derivate/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/quadramp_derivate/CVS/Template b/modules/devices/control_system/filters/quadramp_derivate/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/quadramp_derivate/Makefile b/modules/devices/control_system/filters/quadramp_derivate/Makefile new file mode 100644 index 0000000..97a5f51 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/Makefile @@ -0,0 +1,6 @@ +TARGET = quadramp_derivate + +# List C source files here. (C dependencies are automatically generated.) +SRC = quadramp_derivate.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/control_system/filters/quadramp_derivate/quadramp_derivate.c b/modules/devices/control_system/filters/quadramp_derivate/quadramp_derivate.c new file mode 100644 index 0000000..cc32e81 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/quadramp_derivate.c @@ -0,0 +1,220 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: quadramp_derivate.c,v 1.2.2.4 2007-11-24 22:12:07 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <aversive.h> +#include <quadramp_derivate.h> + + +void quadramp_derivate_init(struct quadramp_derivate_filter * q) +{ + uint8_t flags; + IRQ_LOCK(flags); + + q->var_2nd_ord_pos = 1; + q->var_2nd_ord_neg = 1; + q->var_1st_ord_pos = 0; + q->var_1st_ord_neg = 0; + + q->previous_in_position = 0; + q->previous_out_speed = 0; + + q-> gain_anticipation= 0; + q-> goal_window= 0; + + q-> divisor = 1; + + q-> pivot = 0; + + IRQ_UNLOCK(flags); +} + + +void quadramp_derivate_set_gain_anticipation(struct quadramp_derivate_filter * q, uint16_t gain_anticipation) +{ + uint8_t flags; + IRQ_LOCK(flags); + q->gain_anticipation = gain_anticipation; + IRQ_UNLOCK(flags); +} + +void quadramp_derivate_set_goal_window(struct quadramp_derivate_filter * q, uint32_t goal_window) +{ + uint8_t flags; + IRQ_LOCK(flags); + q->goal_window = goal_window; + IRQ_UNLOCK(flags); +} + +void quadramp_derivate_set_2nd_order_vars(struct quadramp_derivate_filter * q, uint32_t var_2nd_ord_pos, uint32_t var_2nd_ord_neg) +{ + uint8_t flags; + IRQ_LOCK(flags); + q->var_2nd_ord_pos = var_2nd_ord_pos; + q->var_2nd_ord_neg = var_2nd_ord_neg; + IRQ_UNLOCK(flags); +} + +void quadramp_derivate_set_1st_order_vars(struct quadramp_derivate_filter * q, uint32_t var_1st_ord_pos, uint32_t var_1st_ord_neg) +{ + uint8_t flags; + IRQ_LOCK(flags); + q->var_1st_ord_pos = var_1st_ord_pos; + q->var_1st_ord_neg = var_1st_ord_neg; + IRQ_UNLOCK(flags); +} + + +void quadramp_derivate_set_divisor(struct quadramp_derivate_filter * q, uint8_t divisor) +{ + uint8_t flags; + IRQ_LOCK(flags); + + q->divisor = divisor; + q->divisor_counter = 1; + + IRQ_UNLOCK(flags); +} + + +/** + * Process the ramp + * + * \param data should be a (struct quadramp_derivate_filter *) pointer + * \param in is the input of the filter + * + */ +int32_t quadramp_derivate_do_filter(void * data, int32_t in_position) +{ + struct quadramp_derivate_filter * q = data; + int32_t position_pivot, speed, var_2nd_ord, acceleration_consign, speed_consign; + + /** sampling divisor + this is a state machine who executes the algorithm only one time out of "divisor" */ + if( q->divisor != 1) { + if (-- (q->divisor_counter) !=0 ) { + // if it is not time to exec the algorithm, we just test the goal_window + if(ABS( in_position ) < q->goal_window) + q->previous_out_speed =0; + // and return the previous consign + return q->previous_out_speed; + } + + q->divisor_counter = q->divisor; + } + + + + /** compensation of the inversion before the input + (inversion of the control system where error = consign - feedback) + */ + in_position = -in_position; + + + // calculating the actual speed (derivate) + speed = in_position - q->previous_in_position; + + + + /** limitation of this speed, due to overflows, and calculations based on theoretical max value + and also the peak created when the position_consign changes */ + if (speed >=0) { + if(q->var_1st_ord_pos) + MAX(speed , (q->var_1st_ord_pos * q-> divisor) ); // divisor reequilibrates the value. + } + else { + if(q->var_1st_ord_neg) + MIN(speed , (-(q->var_1st_ord_neg* q-> divisor)) ); // divisor reequilibrates the value. + } + + + + + /** calculation of the pivot position. + when this position is atteined, it is just the right time to begin to deccelerate. + The length to this position is given by a linear decceleration to 0 : x = speed²/ (2 * acceleration) + + */ + + // taking the concerned acc. value + if (speed >=0) // why not position ? + var_2nd_ord = q->var_2nd_ord_pos; + else + var_2nd_ord = q->var_2nd_ord_neg; + + // anticipation, proportionnal to speed. Gain_anticipation is a fixed point value, with 8 bits shift + position_pivot = (ABS(speed) * q->gain_anticipation) >>8 ; + + // if necessary, compensation of the output units, when using a sampler divisor + if(q->divisor != 1) { + var_2nd_ord *= q-> divisor; + position_pivot /= q-> divisor; + } + + // pivot calculation itself + position_pivot += speed*speed /(2*var_2nd_ord); + + // taking the right sign + if(speed >=0) + position_pivot = - position_pivot; + + // mem only for debug + q-> pivot = position_pivot; + + /** this is the heart of the trajectory generation. + Pretty simple but indeed unstable, + because of this corresponds to an infinite gain, in the following equation : + acceleration_consign = ( position_pivot - in_position ) * gain + + In fact this unstability is erased by the fact that the acc value is nearly always limited + */ + if(position_pivot >= in_position) + acceleration_consign = q->var_2nd_ord_pos; + else + acceleration_consign = -q->var_2nd_ord_neg; + + + + /** integration and limitation of the acceleration to obtain a speed consign */ + speed_consign = q->previous_out_speed + acceleration_consign; + + if (speed_consign >=0) { + if(q->var_1st_ord_pos) + MAX(speed_consign , q->var_1st_ord_pos); + } + else { + if(q->var_1st_ord_neg) + MIN(speed_consign , -q->var_1st_ord_neg); + } + + + /** creation of an end arrival window. This is done to stop the oscillations when the goal is achieved. */ + if(ABS( in_position ) < q->goal_window) + speed_consign=0; + + /** refresh the memories */ + q->previous_in_position = in_position; + q->previous_out_speed = speed_consign; + + + return speed_consign ; +} diff --git a/modules/devices/control_system/filters/quadramp_derivate/quadramp_derivate.h b/modules/devices/control_system/filters/quadramp_derivate/quadramp_derivate.h new file mode 100644 index 0000000..2d29bc9 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/quadramp_derivate.h @@ -0,0 +1,91 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: quadramp_derivate.h,v 1.2.2.3 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#ifndef _QUADRAMP_DERIVATE_H_ +#define _QUADRAMP_DERIVATE_H_ + +#include <aversive.h> + +struct quadramp_derivate_filter +{ + uint32_t var_2nd_ord_pos; + uint32_t var_2nd_ord_neg; + uint32_t var_1st_ord_pos; + uint32_t var_1st_ord_neg; + + int32_t previous_in_position; + int32_t previous_out_speed; + + int32_t goal_window; + int32_t gain_anticipation; /* fixed point value, * 1/256 */ + + int32_t pivot; /* debug only */ + + uint8_t divisor; + uint8_t divisor_counter; +}; + +/** Initialization of the filter + as this filter has always an infinite gain, it is initilized with an integrative infinite gain limited by 1 */ +extern inline void quadramp_derivate_init(struct quadramp_derivate_filter * r); + +/** set the anticipation value. This gain is a fixed point value that will be divided by 256. + set this gain to have enough anticipation, so the goal is not atteined with too much speed. + too much, and the goal will be overlooked, and the system will oscillate. + Too less, and the goal will be atteined with speed, and the goal window will eventually cutoff brutally + */ +extern inline void quadramp_derivate_set_gain_anticipation(struct quadramp_derivate_filter * q, uint16_t gain_anticipation); + +/** goal window is a shutdown of the integration when the goal is atteined. + this aims to get rid of the very little oscillations when immobile */ +extern inline void quadramp_derivate_set_goal_window(struct quadramp_derivate_filter * q, uint32_t goal_window); + +/** as in the quadramp, we can set here the maximum speed (1st order) and maximum acceleration (2nd order) + and this in both directions, positive, and negative. */ +extern inline void quadramp_derivate_set_2nd_order_vars(struct quadramp_derivate_filter * q, uint32_t var_2nd_ord_pos, uint32_t var_2nd_ord_neg); +extern inline void quadramp_derivate_set_1st_order_vars(struct quadramp_derivate_filter * q, uint32_t var_1st_ord_pos, uint32_t var_1st_ord_neg); + +/** this sets a divisor. (executing only 1 time of n) + this permits to make a bigger resolution on the speed and acceleration consign. + + default is 1. + When using n>1, the new acceleration (2nd order) unit is divided by n (increasing precision) + The speed remains at the same unit. + + The drawback is that the speed will have the forma of a stair, so do not abuse of it ! + */ +extern inline void quadramp_derivate_set_divisor(struct quadramp_derivate_filter * q, uint8_t divisor); + + +/** + * Process the ramp + * + * \param data should be a (struct quadramp_filter *) pointer + * \param in is the input of the filter + * + * the input is a position (relative to goal) + * The output of the function is a speed, which is typically fed as consign to a speed PID. + * Beware !! the speed unit at the output must absolutely be the same that the derivate of the input, + * which means that the frequency of the quadramp_derivate_do_filter must be the same than that of the speed PID. + */ +extern int32_t quadramp_derivate_do_filter(void * data, int32_t in); + +#endif diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/.config b/modules/devices/control_system/filters/quadramp_derivate/test/.config new file mode 100644 index 0000000..508181e --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/.config @@ -0,0 +1,198 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_UTILS=y +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_WAIT=y +CONFIG_MODULE_LIST=y +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_PWM=y +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable utils and pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE=y +CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG=y + +# +# Encoders (you should enable utils and fixed_point modules to see all available encoders) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y +CONFIG_MODULE_PID=y +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +CONFIG_MODULE_QUADRAMP_DERIVATE=y +CONFIG_MODULE_BIQUAD=y + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Entries b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Entries new file mode 100644 index 0000000..1e2a0e4 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Entries @@ -0,0 +1,9 @@ +/.config/1.2.2.2/Sat May 12 16:42:39 2007//Tb_zer0 +/Makefile/1.2.2.2/Sat May 12 16:42:40 2007//Tb_zer0 +/brushless_3phase_digital_hall_double_config.h/1.2.2.2/Sat May 12 16:42:40 2007//Tb_zer0 +/error_config.h/1.2.2.2/Sat May 12 16:42:40 2007//Tb_zer0 +/main.c/1.2.2.3/Wed May 23 17:18:13 2007//Tb_zer0 +/pwm_config.h/1.2.2.2/Sat May 12 16:42:40 2007//Tb_zer0 +/time_config.h/1.2.2.2/Sat May 12 16:42:40 2007//Tb_zer0 +/uart_config.h/1.2.2.2/Sat May 12 16:42:40 2007//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Repository b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Repository new file mode 100644 index 0000000..64142a0 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/quadramp_derivate/test diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Root b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Tag b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Template b/modules/devices/control_system/filters/quadramp_derivate/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/Makefile b/modules/devices/control_system/filters/quadramp_derivate/test/Makefile new file mode 100644 index 0000000..ba846b7 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/Makefile @@ -0,0 +1,26 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +.PHONY:plot +plot: all + ./main > data + ./plot \ No newline at end of file diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/brushless_3phase_digital_hall_double_config.h b/modules/devices/control_system/filters/quadramp_derivate/test/brushless_3phase_digital_hall_double_config.h new file mode 100644 index 0000000..eb2007b --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/brushless_3phase_digital_hall_double_config.h @@ -0,0 +1,136 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: brushless_3phase_digital_hall_double_config.h,v 1.2.2.2 2007-05-12 16:42:40 zer0 Exp $ + * + */ + +#ifndef BRUSHLESS_TYPE +#define BRUSHLESS_TYPE BRUSHLESS_DIGITAL_DOUBLE + + +/** a setting of 1 gives 6 steps per electrical turn + the number of electrical poles per mechanical revolution depends on your motor. + Please consider that a value different from 1 rises the processor load ! so try to use 1 + */ +#define BRUSHLESS_POSITION_PRECISION 1 + + +typedef s16 brushless_speed; +typedef s32 brushless_position; + +typedef s16 brushless_torque; // max value is that of the PWM + + +/** motor 0 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_0_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_0_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_0_SENSOR_1_PORT PORTA +#define BRUSHLESS_0_SENSOR_1_BIT 4 +#define BRUSHLESS_0_SENSOR_2_PORT PORTA +#define BRUSHLESS_0_SENSOR_2_BIT 3 +#define BRUSHLESS_0_SENSOR_3_PORT PORTA +#define BRUSHLESS_0_SENSOR_3_BIT 5 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_0_PWM_SET_1(value) pwm_set_1A(value) +#define BRUSHLESS_0_PWM_SET_2(value) pwm_set_1B(value) +#define BRUSHLESS_0_PWM_SET_3(value) pwm_set_1C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +#define BRUSHLESS_0_INVERT + + +/** motor 1 connection definition */ + +/** inversion of sensors*/ +//#define BRUSHLESS_1_SENSORS_INVERT + +/** sensor pull ups. This is recommended for safety */ +//#define BRUSHLESS_1_SENSORS_PULL_UP_RESISTORS + +/** sensors port definitions */ +#define BRUSHLESS_1_SENSOR_1_PORT PORTA +#define BRUSHLESS_1_SENSOR_1_BIT 1 +#define BRUSHLESS_1_SENSOR_2_PORT PORTA +#define BRUSHLESS_1_SENSOR_2_BIT 0 +#define BRUSHLESS_1_SENSOR_3_PORT PORTA +#define BRUSHLESS_1_SENSOR_3_BIT 2 + +/** PWM definitions + Please activate the PWM synch in pwm.h if you use PWMs from separate timers + */ +#define BRUSHLESS_1_PWM_SET_1(value) pwm_set_3A(value) +#define BRUSHLESS_1_PWM_SET_2(value) pwm_set_3B(value) +#define BRUSHLESS_1_PWM_SET_3(value) pwm_set_3C(value) + + + +/** total inversion of the motor behaviour, other configuration remains the same */ +//#define BRUSHLESS_1_INVERT + + + +/** this selects the timer overflow int to use + please enter the timer number of one of the 6 PWMs + for example,if one of your pwm is the 2A, enter "2" here + */ +#define BRUSHLESS_TIMER 1 + +/** following parameters calculateas such : + + fsample = fpwm / PWM_TO_SAMPLE_DIVISOR + + fevent = fsample / SAMPLE_TO_EVENT_DIVISOR + + it is recommended to have fsample at approx 10 kHz max, less if you plan a slow motor + SAMPLE_TO_EVENT_DIVISOR should be at least 100, or more, so that the event is slow enough for your need + + these parameters should be carefully chosen to not overload the processor + + */ + +/** max 255 */ +#define BRUSHLESS_PWM_TO_SAMPLE_DIVISOR 4 // PWM9 bits, quartz 16 MHz >> 7.8 kHz +/** max 65535, min recommended 100 */ +#define BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR (78*1) // environ 10ms + + +/** max speed, is in general to BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + but can be adapted to your needs, if you need to go further down with the speed */ +#define BRUSHLESS_MAX_SPEED BRUSHLESS_SAMPLE_TO_EVENT_DIVISOR + + + +//#define LOADTEST // define this to test the maximum processor load ! + +//#define ASMHEADER // optimized PWM division : particularly useful with 8 bit timers ! Using this can display one warning + + +#endif // BRUSHLESS_TYPE + + diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/error_config.h b/modules/devices/control_system/filters/quadramp_derivate/test/error_config.h new file mode 100644 index 0000000..8e31973 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.2.2 2007-05-12 16:42:40 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/main.c b/modules/devices/control_system/filters/quadramp_derivate/test/main.c new file mode 100644 index 0000000..8850d4a --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/main.c @@ -0,0 +1,199 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2.2.3 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive/wait.h> +#include <aversive.h> + +#include <brushless.h> +#include <biquad.h> + +#include <pwm.h> + + + +#include <uart.h> +#include <stdio.h> +#include <aversive/pgmspace.h> + + + + +#include <pid.h> +#include <control_system_manager.h> +#include <quadramp_derivate.h> + + + +struct cs speed; +struct pid_filter speed_pid; +struct biquad_filter speed_derivation; + + +struct cs position; +struct quadramp_derivate_filter position_quadr_derv; + + + +// periodical 10ms execution +void asserv_rapide_manage(brushless data_moteur) +{ + + cs_manage(&position); + + cs_manage(&speed); + + + + // for debug graphs + printf_P(PSTR("C%lip%liP%liv%liV%li\n"), position.consign_value, brushless_get_pos((void*)0), position_quadr_derv.pivot + position.consign_value + , brushless_get_speed((void*)0), speed.consign_value); + + //printf_P(PSTR("i%lio%liv%li\n"), speed_pid.prev_in, speed_pid.prev_out, vitesse); +} + + +int main(void) +{ + + + + // init motors and PWMs + brushless_init(); + + + // enable power bridges + sbi(DDRG, 1); + sbi(PORTG, 1); + + + // init uart + uart_init(); + fdevopen((void *)uart0_send,NULL,0); + + + + //printf_P(PSTR("\nbonjour\n")); + + + + /** replaces the scheduler. This is directly derived from the interrupt which runs the brushless motors, for convenience */ + brushless_0_register_periodic_event(asserv_rapide_manage); // 10 ms + + + + /** speed PID stuff */ + + // PID + pid_init(&speed_pid); + + pid_set_gains(&speed_pid, 180, 70, 40); // sur alim + + pid_set_maximums(&speed_pid, 0, 80, PWM_MAX*4/5); + pid_set_out_shift(&speed_pid, 0); + + // derivation (This could alternatively be skipped if we use the brushless peed info directly) + biquad_init(&speed_derivation); + biquad_set_numerator_coeffs(&speed_derivation, 1,-1,0); // this is a discrete derivation : O(n) = I(n) - I(n-1) + // no need to initialize denominator coeffs to 0, init has done it + + // control system speed + cs_init(&speed); + + cs_set_correct_filter(&speed, pid_do_filter, &speed_pid); + cs_set_process_in(&speed, brushless_set_torque, (void *)0 ); + cs_set_process_out(&speed,brushless_get_pos , (void *)0 ); + cs_set_feedback_filter(&speed, biquad_do_filter, &speed_derivation); + cs_set_consign(&speed, 0); + + + + /** ramp generator parameters */ + + quadramp_derivate_init(&position_quadr_derv); + + quadramp_derivate_set_gain_anticipation(&position_quadr_derv, 256 *3);// some anticipation : 3.0 (this is a fixed point value *1/256) + + quadramp_derivate_set_goal_window(&position_quadr_derv, 5); // algorithm shut down window + + quadramp_derivate_set_2nd_order_vars(&position_quadr_derv, 1 , 1); // max acceleration : 1 + quadramp_derivate_set_1st_order_vars(&position_quadr_derv, 12, 12); // max speed is 12 + + quadramp_derivate_set_divisor(&position_quadr_derv, 2); // divisor, for precision + + + // control system position + cs_init(&position); + cs_set_correct_filter(&position, quadramp_derivate_do_filter, &position_quadr_derv); + cs_set_process_in(&position, (void *)cs_set_consign, &speed ); + cs_set_process_out(&position,brushless_get_pos , (void *)0 ); + cs_set_consign(&position, 0); + + + /** begin */ + + brushless_set_speed((void *)0 , BRUSHLESS_MAX_SPEED); // init speed + + sei(); + + + + + // some simple trajectories (enable one ) + + while(1) + { + wait_ms(3500); + cs_set_consign(&position, 400); + wait_ms(500); + cs_set_consign(&position, 0); + } + + + /* + while(1) + { + wait_ms(2500); + cs_set_consign(&position, 2000); + wait_ms(2500); + cs_set_consign(&position, 0); + } + + + + // test of speed pid only, deactivate the position. + while(1) + { + wait_ms(300); + cs_set_consign(&speed, 10); + wait_ms(300); + cs_set_consign(&speed, -10); + } */ + + + + + while(1); + + + return 0; +} + diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/pwm_config.h b/modules/devices/control_system/filters/quadramp_derivate/test/pwm_config.h new file mode 100644 index 0000000..2f4b159 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/pwm_config.h @@ -0,0 +1,147 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.2.2.2 2007-05-12 16:42:40 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ +/** \file pwm_config.h + \brief Module to operate all PWM outputs + + \test not tested + +*/ + + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +/* Which PWM are enabled ? */ +//#define PWM0_ENABLED +#define PWM1A_ENABLED +#define PWM1B_ENABLED +#define PWM1C_ENABLED +//#define PWM2_ENABLED +#define PWM3A_ENABLED +#define PWM3B_ENABLED +#define PWM3C_ENABLED + + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +// timer configs + +//#define TIMER0_MODE TIMER_8_MODE_PWM +//#define TIMER0_PRESCALE TIMER_8_PRESCALE_1 + +// 31 kHz PWM +#define TIMER1_MODE TIMER_16_MODE_PWM_9 +#define TIMER1_PRESCALE TIMER_16_PRESCALE_1 + +//#define TIMER2_MODE TIMER_8_MODE_PWM +//#define TIMER2_PRESCALE TIMER_8_PRESCALE_1 + +// 31 kHz PWM +#define TIMER3_MODE TIMER_16_MODE_PWM_9 +#define TIMER3_PRESCALE TIMER_16_PRESCALE_1 + + + + +/** config for pwm and signs + +The pwm mode is defined as follows : +you can add flags like the ones who follow : + +PWM_NORMAL : normal pwm, just to put a value if nothing else is needed +PWM_REVERSE : invert pwm output, not sign + +PWM_SIGNED : activate the sign output on a port (see config) +PWM_SIGN_INVERTED : invert sign output +PWM_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for low values, + else negative low values are near 100% + + +the values of PWMxx_SIGN_PORT and PWMxx_SIGN_BIT are simply ignored if the PWM is not signed, but must be defined + + +if you need for example a PWM1A with special sign mode you configure like this : + +#define PWM1A_MODE (PWM_SIGNED | PWM_SPECIAL_SIGN_MODE) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + +*/ + + + +// PWM definitions +#define PWM1A_MODE (PWM_NORMAL) +#define PWM1A_SIGN_PORT PORTB // ignored +#define PWM1A_SIGN_BIT 2 // ignored + +#define PWM1B_MODE (PWM_NORMAL) +#define PWM1B_SIGN_PORT PORTB // ignored +#define PWM1B_SIGN_BIT 2 // ignored + +#define PWM1C_MODE (PWM_NORMAL) +#define PWM1C_SIGN_PORT PORTB // ignored +#define PWM1C_SIGN_BIT 2 // ignored + +#define PWM3A_MODE (PWM_NORMAL) +#define PWM3A_SIGN_PORT PORTB // ignored +#define PWM3A_SIGN_BIT 2 // ignored + +#define PWM3B_MODE (PWM_NORMAL) +#define PWM3B_SIGN_PORT PORTB // ignored +#define PWM3B_SIGN_BIT 2 // ignored + +#define PWM3C_MODE (PWM_NORMAL) +#define PWM3C_SIGN_PORT PORTB // ignored +#define PWM3C_SIGN_BIT 2 // ignored + + + +/** +PWM synchronization. + +this makes the PWMs synchronized. +just activate the timers you want to synchronize + +to synch PWMs you need to enshure that the timers have same prescales. This is verified. +you need also to enshure that the PWM mode is the same, this is NOT verified !! +especially, for syncing 8 and 16 bit timers, the PWM mode should be 8 bit. + + +side effect : on some controllers prescalers are shared, so unwanted prescalers can be reset. + +This feature is not 100% shure for the moment, but has been tested on M32 and M128 +*/ + +//#define TIMER0_SYNCH +#define TIMER1_SYNCH +//#define TIMER2_SYNCH +#define TIMER3_SYNCH + + + +#endif + diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/time_config.h b/modules/devices/control_system/filters/quadramp_derivate/test/time_config.h new file mode 100644 index 0000000..b0f4823 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.2.2.2 2007-05-12 16:42:40 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000l diff --git a/modules/devices/control_system/filters/quadramp_derivate/test/uart_config.h b/modules/devices/control_system/filters/quadramp_derivate/test/uart_config.h new file mode 100644 index 0000000..109a510 --- /dev/null +++ b/modules/devices/control_system/filters/quadramp_derivate/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.2.2 2007-05-12 16:42:40 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/control_system/filters/ramp/CVS/Entries b/modules/devices/control_system/filters/ramp/CVS/Entries new file mode 100644 index 0000000..38daa5e --- /dev/null +++ b/modules/devices/control_system/filters/ramp/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/ramp.c/1.5.4.4/Sun Jun 24 17:31:05 2007//Tb_zer0 +/ramp.h/1.4.4.2/Wed Jan 9 22:27:01 2008//Tb_zer0 +D/config//// diff --git a/modules/devices/control_system/filters/ramp/CVS/Repository b/modules/devices/control_system/filters/ramp/CVS/Repository new file mode 100644 index 0000000..c84e7c1 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/ramp diff --git a/modules/devices/control_system/filters/ramp/CVS/Root b/modules/devices/control_system/filters/ramp/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/ramp/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/ramp/CVS/Tag b/modules/devices/control_system/filters/ramp/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/ramp/CVS/Template b/modules/devices/control_system/filters/ramp/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/ramp/Makefile b/modules/devices/control_system/filters/ramp/Makefile new file mode 100755 index 0000000..e9a2411 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/Makefile @@ -0,0 +1,6 @@ +TARGET = ramp + +# List C source files here. (C dependencies are automatically generated.) +SRC = ramp.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/control_system/filters/ramp/config/CVS/Entries b/modules/devices/control_system/filters/ramp/config/CVS/Entries new file mode 100644 index 0000000..52eeef1 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/config/CVS/Entries @@ -0,0 +1,2 @@ +/ramp_config.h/1.1.10.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/control_system/filters/ramp/config/CVS/Repository b/modules/devices/control_system/filters/ramp/config/CVS/Repository new file mode 100644 index 0000000..68fa4f6 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/control_system/filters/ramp/config diff --git a/modules/devices/control_system/filters/ramp/config/CVS/Root b/modules/devices/control_system/filters/ramp/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/control_system/filters/ramp/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/control_system/filters/ramp/config/CVS/Tag b/modules/devices/control_system/filters/ramp/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/control_system/filters/ramp/config/CVS/Template b/modules/devices/control_system/filters/ramp/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/control_system/filters/ramp/config/ramp_config.h b/modules/devices/control_system/filters/ramp/config/ramp_config.h new file mode 100755 index 0000000..d250ece --- /dev/null +++ b/modules/devices/control_system/filters/ramp/config/ramp_config.h @@ -0,0 +1,20 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ diff --git a/modules/devices/control_system/filters/ramp/ramp.c b/modules/devices/control_system/filters/ramp/ramp.c new file mode 100644 index 0000000..c45dd50 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/ramp.c @@ -0,0 +1,80 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + */ + + +#include <aversive.h> +#include "ramp.h" + + +/* Initialize the two first fields to the max possible value and previous out to 0*/ + +void ramp_init(struct ramp_filter * r) +{ + uint8_t flags; + IRQ_LOCK(flags); + + r->var_neg=0xFFFFFFFF; + r->var_pos=0xFFFFFFFF; + r->prev_out=0; + + IRQ_UNLOCK(flags); + return; +} + +/*Set the field var_neg to neg and var_pos to pos */ + +void ramp_set_vars(struct ramp_filter * r, uint32_t neg, uint32_t pos) +{ + uint8_t flags; + IRQ_LOCK(flags); + + r->var_neg=neg; + r->var_pos=pos; + + IRQ_UNLOCK(flags); + return; +} + +/*Filter the in value using the ramp_filter r*/ +int32_t ramp_do_filter(void * data, int32_t in) +{ + uint32_t variation; + struct ramp_filter * r = (struct ramp_filter *) data; + + if (in>r->prev_out) /*test if the variation is positive or negative */ + { + variation=in-r->prev_out; /* positive variation */ + if (variation<r->var_pos) /* test if the variation is too high */ + r->prev_out=in; /* variation ok return value will be in */ + else + r->prev_out=r->prev_out+r->var_pos; /* variation too high so return value is filtered */ + } + else + { + variation=r->prev_out-in; /* negative variation */ + if (variation<r->var_neg) /* test if the variation is too high */ + r->prev_out=in; /* variation ok return value will be in */ + else + r->prev_out=r->prev_out-r->var_neg; /* variation too high so return value is filtered */ + } + return(r->prev_out); +} + + diff --git a/modules/devices/control_system/filters/ramp/ramp.h b/modules/devices/control_system/filters/ramp/ramp.h new file mode 100644 index 0000000..3b12492 --- /dev/null +++ b/modules/devices/control_system/filters/ramp/ramp.h @@ -0,0 +1,74 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + */ + + +/** \file ramp.h +* \brief This module provides structure and functions to filter a ramp. +* \author Vincent +* \version 1.0 +* \date 6.01.2005 @ 12:00 +* \todo Verify the english language +* \test filter a constante value to generate a ramp on the hardware. Everything is all right +* +*/ + + + +#ifndef _RAMP_H +#define _RAMP_H + +/** \brief Definition of structur ramp_filter */ + +struct ramp_filter { + uint32_t var_neg; /**Authorized negative variation*/ + uint32_t var_pos; /**Authorized positive variation*/ + int32_t prev_out; /**Previous value calculated*/ +}; + + + +/* Begin prototyping ************************/ + +/**\brief Initialisation of the ramp_filter structur + *\param r ramp_filter structur to initiate + **/ + +void ramp_init(struct ramp_filter * r ); + + +/**\brief Set the fields of the ramp_filter structur + *\param r ramp_structure to modificate + *\param neg limit for the negative variation + *\param pos limit for the positive variation + */ + +void ramp_set_vars(struct ramp_filter * r, uint32_t neg, uint32_t pos); + + +/** \brief Apply ramp_filter to a ramp +* \param r ramp_filter used to filter the in +* \param in ramp to filter +* \return filtered in +*/ + + +int32_t ramp_do_filter(void * r, int32_t in); + +#endif /* ifndef _RAMP_H */ diff --git a/modules/devices/encoders/CVS/Entries b/modules/devices/encoders/CVS/Entries new file mode 100644 index 0000000..aebebe4 --- /dev/null +++ b/modules/devices/encoders/CVS/Entries @@ -0,0 +1,3 @@ +D/encoders_eirbot//// +D/encoders_microb//// +D/encoders_spi//// diff --git a/modules/devices/encoders/CVS/Repository b/modules/devices/encoders/CVS/Repository new file mode 100644 index 0000000..360ae67 --- /dev/null +++ b/modules/devices/encoders/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders diff --git a/modules/devices/encoders/CVS/Root b/modules/devices/encoders/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/CVS/Tag b/modules/devices/encoders/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/CVS/Template b/modules/devices/encoders/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_eirbot/CVS/Entries b/modules/devices/encoders/encoders_eirbot/CVS/Entries new file mode 100644 index 0000000..2ba3660 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/encoders_eirbot.c/1.4.4.3/Wed May 23 17:18:13 2007//Tb_zer0 +/encoders_eirbot.h/1.3.4.2/Wed May 23 17:18:13 2007//Tb_zer0 +D/config//// +D/xilinx_vhdl//// diff --git a/modules/devices/encoders/encoders_eirbot/CVS/Repository b/modules/devices/encoders/encoders_eirbot/CVS/Repository new file mode 100644 index 0000000..8696fc5 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_eirbot diff --git a/modules/devices/encoders/encoders_eirbot/CVS/Root b/modules/devices/encoders/encoders_eirbot/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_eirbot/CVS/Tag b/modules/devices/encoders/encoders_eirbot/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_eirbot/CVS/Template b/modules/devices/encoders/encoders_eirbot/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_eirbot/Makefile b/modules/devices/encoders/encoders_eirbot/Makefile new file mode 100644 index 0000000..90557f7 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/Makefile @@ -0,0 +1,6 @@ +TARGET = encoders_eirbot + +# List C source files here. (C dependencies are automatically generated.) +SRC = encoders_eirbot.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/encoders/encoders_eirbot/config/CVS/Entries b/modules/devices/encoders/encoders_eirbot/config/CVS/Entries new file mode 100644 index 0000000..ed0d9e1 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/config/CVS/Entries @@ -0,0 +1,2 @@ +/encoders_eirbot_config.h/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/encoders/encoders_eirbot/config/CVS/Repository b/modules/devices/encoders/encoders_eirbot/config/CVS/Repository new file mode 100644 index 0000000..ff44a83 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_eirbot/config diff --git a/modules/devices/encoders/encoders_eirbot/config/CVS/Root b/modules/devices/encoders/encoders_eirbot/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_eirbot/config/CVS/Tag b/modules/devices/encoders/encoders_eirbot/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_eirbot/config/CVS/Template b/modules/devices/encoders/encoders_eirbot/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_eirbot/config/encoders_eirbot_config.h b/modules/devices/encoders/encoders_eirbot/config/encoders_eirbot_config.h new file mode 100644 index 0000000..0d8a594 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/config/encoders_eirbot_config.h @@ -0,0 +1,48 @@ +// EIRBOT 2005 +// ToF +/** \file codeur_config.h + * \brief configuration du module codeur + * + * \todo il reste a implémanter la version sur irq + * + * \test a tester en version xil + * + * on peut configurer ici combien de codeurs seront utilisés + * et comment y accéder (interface bus xilinx ou ports en irq) + */ + +#ifndef _COUNTER_EIRBOT_CONFIG_ +#define _COUNTER_EIRBOT_CONFIG_ + + + +/** mode de fonctionnement, au choix */ +//#define CODEUR_MODE_IRQ +#define COUNTER_MODE_XILINX + + +/** port utilisé pour la séléction d'adresses dans le xilinx + * exemple, pour 4 codeurs, avec un port de séléction de 2 bits sur le portB, bits 5 et 6 : + * #define CODEUR_SELEC_NITS_NUM 2 + * #define CODEUR_SELEC_BIT0 5 + * #define CODEUR_SELEC_PORT PORTB + * #define CODEUR_SELEC_DDR DDRB +*/ + +#define COUNTER_NUMBER 4 +#define COUNTER_SELEC_NITS_NUM 3 +#define COUNTER_SELEC_BIT0 0 +#define COUNTER_SELEC_PORT PORTA +#define COUNTER_SELEC_DDR DDRA + +/** définition du bus 8 bits utilisé dans le mode xilinx */ +#define COUNTER_PIN PINB +#define COUNTER_DATA_NBBITS 8 +#define COUNTER_DATA_BIT0 0 +#define COUNTER_DATA_DDR DDRB + + + +#endif + + diff --git a/modules/devices/encoders/encoders_eirbot/encoders_eirbot.c b/modules/devices/encoders/encoders_eirbot/encoders_eirbot.c new file mode 100644 index 0000000..93ec9d7 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/encoders_eirbot.c @@ -0,0 +1,144 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_eirbot.c,v 1.4.4.3 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +/** \file encoders_eirbot.c + * \brief achieves acess to incremental encoderss through a xilinx interface + * + * \todo nothing ! + * + * \test + * + * this modules reads 8 bit encoders values on an external interface. + * there are two necessary busses with the interface logic: 8 bit data bus and a n bits selection bus. + * ( see the VDHL for the xilinx program) + * with n bits on the selection bus, you can acess to 2^n encoderss. + * + * modifié par lamygale le 10 octobre 2005. d'apres le code 2004 du codeur + * + */ + + + +#include <aversive.h> + + +#include "encoders_eirbot.h" + +#include "encoders_eirbot_config.h" + +#ifdef ENCODERS_MODE_XILINX +// mask for selection bits +#define ENCODERS_SELEC_MASK ((0xFF >> (8-ENCODERS_SELEC_NITS_NUM)) \ + << ENCODERS_SELEC_BIT0) +#define ENCODERS_DATA_MASK ((0xFF >> (8-ENCODERS_DATA_NBBITS)) \ + << ENCODERS_DATA_BIT0) +// bits qui ne sont pas des donnees sont a 1 (donnees sont alignees a droite) +#define DIFF_DATA_MASK ((0xFF >> ENCODERS_DATA_NBBITS) << ENCODERS_DATA_NBBITS) + +volatile encoders g_codeur_valeurs[ENCODERS_NUMBER]; + +volatile int8_t g_codeur_preced[ENCODERS_NUMBER]; + + + +/** + * fonction utilisée 2 fois seulement, acquiert un codeur +*/ +inline int8_t get_codeur(uint8_t num) +{ + int8_t val; + uint8_t flags; + + IRQ_LOCK(flags); + + ENCODERS_SELEC_PORT = ( ENCODERS_SELEC_PORT & (~ENCODERS_SELEC_MASK) ) | ( num << ENCODERS_SELEC_BIT0); + + nop(); // delay for IO & xilix delay time + nop(); + + val = (ENCODERS_PIN & ENCODERS_DATA_MASK) >> ENCODERS_DATA_BIT0; + + IRQ_UNLOCK(flags); + + return val; +} + +/** Initialisation des codeurs, variables, et ports */ +void encoders_init(void) +{ + uint8_t number; + uint8_t flags; + + IRQ_LOCK(flags); + + ENCODERS_SELEC_DDR |= ENCODERS_SELEC_MASK; // port de selection en sortie + ENCODERS_DATA_DDR &= (~ENCODERS_DATA_MASK); // port de donnees en entree + + for(number = 0 ; number < ENCODERS_NUMBER; number ++) + { + g_codeur_valeurs[number] = 0; + g_codeur_preced[number] = get_codeur(number); + } + + IRQ_UNLOCK(flags); +} + +/** mise a jour des valeurs des codeurs, a faire réguliereement minimum a la fréquence (Fmax_codeur/127) */ +void encoders_manage(void) +{ + uint8_t number; + int8_t res, lu; + uint8_t nombre_a_ajouter; // pour gerer les nombres négatifs + uint8_t flags; + + for(number = 0 ; number < ENCODERS_NUMBER; number ++) + { + + lu = get_codeur(number); // lecture + res = lu - g_codeur_preced[number]; // calcul diff + g_codeur_preced[number] = lu; // mise a jour ancienne valeur + + // on recopie l'etat du MSb dans les bits != donnees + nombre_a_ajouter = ((res >> (ENCODERS_DATA_NBBITS - 1))&1) ? DIFF_DATA_MASK : 0; // si MSb = 1, on prend mask + res = (res & ~DIFF_DATA_MASK) + nombre_a_ajouter; // bits de poids faibles = donnees, les autres = signe + + IRQ_LOCK(flags); + g_codeur_valeurs[number] += res; + IRQ_UNLOCK(flags); + } +} + +/** Extraction d'une valeur de codeur */ +encoders encoders_get_value(uint8_t number) +{ + encoders value; + uint8_t flags; + + IRQ_LOCK(flags); + value = g_codeur_valeurs[number]; + IRQ_UNLOCK(flags); + + return value; +} + +#else +#error the irq version of the codeur module is not implemented yet +#endif diff --git a/modules/devices/encoders/encoders_eirbot/encoders_eirbot.h b/modules/devices/encoders/encoders_eirbot/encoders_eirbot.h new file mode 100644 index 0000000..5a970f9 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/encoders_eirbot.h @@ -0,0 +1,49 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_eirbot.h,v 1.3.4.2 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +/** \file encoders_eirbot.h + * \brief universal Interface for incremental coders + */ + +#ifndef _ENCODERS_EIRBOT_H_ +#define _ENCODERS_EIRBOT_H_ + +#include <base/utils/aversive.h> +#include <encoders_eirbot_config.h> + +typedef int32_t encoders; + +/** + * Initialisation of counters, variables + */ +void encoders_init(void); + + +/** + * Update counter values, need to be done quite (depends on which counter) + */ +void encoders_manage(void); + + +/** Extract counter value */ +encoders encoders_get_value(uint8_t number); + +#endif diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Entries b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Entries new file mode 100644 index 0000000..69f0784 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Entries @@ -0,0 +1,4 @@ +/carte1.prj/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/compteur.vhd/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/test1.vhd/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Repository b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Repository new file mode 100644 index 0000000..a4f11ca --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_eirbot/xilinx_vhdl diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Root b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Tag b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Template b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/carte1.prj b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/carte1.prj new file mode 100644 index 0000000..51582de --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/carte1.prj @@ -0,0 +1,2 @@ +work compteur.vhd +work test1.vhd diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/compteur.vhd b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/compteur.vhd new file mode 100644 index 0000000..8ea17d2 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/compteur.vhd @@ -0,0 +1,59 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +--USE IEEE.STD_LOGIC_ARITH.ALL; +--USE IEEE.STD_LOGIC_UNSIGNED.ALL; +--USE IEEE.STD_LOGIC_SIGNED.ALL; + + +ENTITY compteur IS + GENERIC ( Nb_bascules : natural := 1 + ); + PORT ( AB : IN unsigned(1 DOWNTO 0); + cpt : OUT unsigned(7 DOWNTO 0); + clk : IN std_ulogic; + INV : IN std_ulogic + ); +END compteur; + +ARCHITECTURE Behavioral OF compteur IS +TYPE tableau IS ARRAY (Nb_bascules downto 0) OF unsigned(1 DOWNTO 0); +SIGNAL A_B : tableau; + +SIGNAL tmp : unsigned(7 DOWNTO 0); +BEGIN + + -- double latch des codeurs +copie : PROCESS + BEGIN + WAIT UNTIL rising_edge(clk) ; + + A_B(0)<= AB(1) & (AB(0) XOR INV); + + FOR i IN 1 TO Nb_bascules LOOP + A_B(i) <= A_B(i-1); + END LOOP; + + END PROCESS copie; + + + +-- decodage de la quadrature et comptage + comptage: PROCESS + BEGIN + WAIT UNTIL falling_edge(clk) ; + + + IF (A_B(Nb_bascules-1) = "00" and A_B(Nb_bascules) = "01") OR (A_B(Nb_bascules-1) = "01" AND A_B(Nb_bascules) = "11") OR (A_B(Nb_bascules-1) = "11" AND A_B(Nb_bascules) = "10") OR (A_B(Nb_bascules-1) = "10" AND A_B(Nb_bascules) = "00") THEN + tmp <= tmp - 1; + + ELSIF (A_B(Nb_bascules) = "00" and A_B(Nb_bascules-1) = "01") OR (A_B(Nb_bascules) = "01" AND A_B(Nb_bascules-1) = "11") OR (A_B(Nb_bascules) = "11" AND A_B(Nb_bascules-1) = "10") OR (A_B(Nb_bascules) = "10" AND A_B(Nb_bascules-1) = "00") THEN + tmp <= tmp + 1; + + END IF; + END PROCESS comptage; + + cpt <= tmp; + +END Behavioral; diff --git a/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/test1.vhd b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/test1.vhd new file mode 100644 index 0000000..c27a085 --- /dev/null +++ b/modules/devices/encoders/encoders_eirbot/xilinx_vhdl/test1.vhd @@ -0,0 +1,112 @@ +-- xilinx carte_prop + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +--USE IEEE.STD_LOGIC_ARITH.ALL; +--USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +ENTITY carte1 IS + PORT ( CLK : IN std_logic; + sortie : OUT unsigned(7 DOWNTO 0); + + SEL : IN unsigned(1 DOWNTO 0); + TX_bus : OUT std_logic; + RX_bus : IN std_logic; + TX_avr : IN std_logic; + RX_avr : OUT std_logic; + + AB0 : IN unsigned(1 DOWNTO 0); + AB1 : IN unsigned(1 DOWNTO 0); + + + + + +-- MASSE : std_logic + + ); + + +-- carte 1 + ATTRIBUTE pin_assign : string; + ATTRIBUTE pin_assign OF CLK : SIGNAL IS "7"; --clock + ATTRIBUTE pin_assign OF sortie : SIGNAL IS "11 12 9 8 6 5 4 3 "; --data 0 + -- a 7 + + + ATTRIBUTE pin_assign OF AB0 : SIGNAL IS "27 26"; --cod_d0 + ATTRIBUTE pin_assign OF AB1 : SIGNAL IS "25 29"; --cod_g0 + ATTRIBUTE pin_assign OF RX_bus : SIGNAL IS "19"; --rx_bus + ATTRIBUTE pin_assign OF TX_bus : SIGNAL IS "22"; --tx_bus + ATTRIBUTE pin_assign OF RX_avr : SIGNAL IS "14"; --rx_avr + ATTRIBUTE pin_assign OF TX_avr : SIGNAL IS "13"; --tx_avr + ATTRIBUTE pin_assign OF SEL : SIGNAL IS "1 44"; -- il reste data2 qui est inutilise + -- ATTRIBUTE pin_assign OF MASSE : SIGNAL IS " 43"; + + + + +END carte1; + + +ARCHITECTURE Behavioral OF carte1 IS + +-- 1 traitement de codeur +COMPONENT compteur + GENERIC (Nb_bascules : natural); + PORT ( AB : IN unsigned(1 DOWNTO 0); + cpt : OUT unsigned(7 DOWNTO 0); + clk : IN std_ulogic; + INV : IN std_ulogic + ); +END COMPONENT; + + + SIGNAL sortie0 : unsigned(7 DOWNTO 0); + SIGNAL sortie1 : unsigned(7 DOWNTO 0); + + + for cod0 : compteur + use entity work.compteur(Behavioral); + for cod1 : compteur + + + +BEGIN + + +-- compteur 0 + cod0 : compteur + GENERIC MAP (Nb_bascules => 1) + PORT MAP ( AB => AB0, cpt => sortie0, clk => CLK , INV => '0' ); + +-- compteur 1 + cod1 : compteur + GENERIC MAP (Nb_bascules => 1) + PORT MAP ( AB => AB1, cpt => sortie1, clk => CLK, INV => '1' ); + + + MUX: PROCESS (SEL, sortie0, sortie1, sortie2, sortie3) + BEGIN -- PROCESS MUX + CASE SEL IS + WHEN "00" => sortie <= sortie0; + WHEN "01" => sortie <= sortie1; + + + WHEN OTHERS => sortie <= (OTHERS => 'Z'); + END CASE; + + + END PROCESS MUX; + +UART : PROCESS (TX_avr,RX_bus) +BEGIN -- PROCESS UART + + TX_bus <= TX_avr; + RX_avr <= RX_bus; + +END PROCESS UART; + +END Behavioral; diff --git a/modules/devices/encoders/encoders_microb/CVS/Entries b/modules/devices/encoders/encoders_microb/CVS/Entries new file mode 100644 index 0000000..c875e79 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/encoders_microb.c/1.6.4.3/Wed Jan 9 22:27:19 2008//Tb_zer0 +/encoders_microb.h/1.4.4.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/encoders/encoders_microb/CVS/Repository b/modules/devices/encoders/encoders_microb/CVS/Repository new file mode 100644 index 0000000..c4355f7 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_microb diff --git a/modules/devices/encoders/encoders_microb/CVS/Root b/modules/devices/encoders/encoders_microb/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_microb/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_microb/CVS/Tag b/modules/devices/encoders/encoders_microb/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_microb/CVS/Template b/modules/devices/encoders/encoders_microb/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_microb/Makefile b/modules/devices/encoders/encoders_microb/Makefile new file mode 100644 index 0000000..53b3021 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/Makefile @@ -0,0 +1,6 @@ +TARGET = encoders_microb + +# List C source files here. (C dependencies are automatically generated.) +SRC = encoders_microb.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/encoders/encoders_microb/config/CVS/Entries b/modules/devices/encoders/encoders_microb/config/CVS/Entries new file mode 100644 index 0000000..095d646 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/config/CVS/Entries @@ -0,0 +1,2 @@ +/encoders_microb_config.h/1.3.4.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/encoders/encoders_microb/config/CVS/Repository b/modules/devices/encoders/encoders_microb/config/CVS/Repository new file mode 100644 index 0000000..daca17f --- /dev/null +++ b/modules/devices/encoders/encoders_microb/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_microb/config diff --git a/modules/devices/encoders/encoders_microb/config/CVS/Root b/modules/devices/encoders/encoders_microb/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_microb/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_microb/config/CVS/Tag b/modules/devices/encoders/encoders_microb/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_microb/config/CVS/Template b/modules/devices/encoders/encoders_microb/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_microb/config/encoders_microb_config.h b/modules/devices/encoders/encoders_microb/config/encoders_microb_config.h new file mode 100644 index 0000000..17f4d25 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/config/encoders_microb_config.h @@ -0,0 +1,45 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_microb_config.h,v 1.3.4.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ +#ifndef _ENCODERS_MICROB_CONFIG_H_ +#define _ENCODERS_MICROB_CONFIG_H_ + +/** number of the LAST encoders used + 1 */ +#define ENCODERS_MICROB_NUMBER 4 + +#define ENCODERS_MICROB_SEL_PORT PORTE +#define ENCODERS_MICROB_SEL_BIT 6 + +#define ENCODERS_MICROB0_ENABLED +#define ENCODERS_MICROB0_PIN PINA + +#define ENCODERS_MICROB1_ENABLED +#define ENCODERS_MICROB1_PIN PINA + +#define ENCODERS_MICROB2_ENABLED +#define ENCODERS_MICROB2_PIN PINC + +#define ENCODERS_MICROB3_ENABLED +#define ENCODERS_MICROB3_PIN PINC + + +// ... until 7 + +#endif diff --git a/modules/devices/encoders/encoders_microb/encoders_microb.c b/modules/devices/encoders/encoders_microb/encoders_microb.c new file mode 100644 index 0000000..24c283b --- /dev/null +++ b/modules/devices/encoders/encoders_microb/encoders_microb.c @@ -0,0 +1,255 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_microb.c,v 1.6.4.3 2008-01-09 22:27:19 zer0 Exp $ + * + */ + +/** \file encoders_microb.c + * \brief Implementation for getting motor position + * + * \todo test the module + * + * \test nothing done + * + * This module provides functions for getting position from + * coders. Its implementation depends on hardware, so that's why there + * is (or will be) multiple implementation of this module. + * + * The harware is quite simple here : + * + * \verbatim + * ---------- + * | | 8 + * | PINx|<-/--- value + * | | + * | | 8 + * | PINy|<-/--- value + * | | + * | | 8 + * | PINz|<-/--- value + * | | + * | ....| + * | | + * | SEL |----> (1 bit) + * | | + * | | + * | | + * ---------- + * \endverbatim + */ + +#include <stdlib.h> + +#include <aversive.h> +#include <aversive/wait.h> + +#include <encoders_microb.h> +#include <encoders_microb_config.h> + + +/******************************************/ +int32_t g_encoders_microb_values[ENCODERS_MICROB_NUMBER]; +int8_t g_encoders_microb_previous[ENCODERS_MICROB_NUMBER]; + +/******************************************/ + +#define SEL_A() cbi(ENCODERS_MICROB_SEL_PORT,ENCODERS_MICROB_SEL_BIT) +#define SEL_B() sbi(ENCODERS_MICROB_SEL_PORT,ENCODERS_MICROB_SEL_BIT) + +/******************************************/ + +#define READ(n) \ +do { \ +val = ENCODERS_MICROB##n##_PIN; \ +nop(); \ +if (val != ENCODERS_MICROB##n##_PIN) \ + val = ENCODERS_MICROB##n##_PIN; \ + \ +res = (val - g_encoders_microb_previous[n]); \ +g_encoders_microb_previous[n] = val; \ + \ +g_encoders_microb_values[n] += (int32_t)res ; \ +} while(0) + +/******************************************/ + +#define INIT(n) do { \ +g_encoders_microb_values[n] = 0; \ +} while(0) + +/******************************************/ + + + + + +/** + * Initialisation of encoders, variables + */ +void encoders_microb_init(void) +{ + uint8_t flags; + + sbi(DDR(ENCODERS_MICROB_SEL_PORT),ENCODERS_MICROB_SEL_BIT); + SEL_A(); + // wait at least 10us + wait_4cyc(50); + encoders_microb_manage(NULL); + wait_4cyc(50); + encoders_microb_manage(NULL); + + IRQ_LOCK(flags); +#ifdef ENCODERS_MICROB0_ENABLED + INIT(0); +#endif + +#ifdef ENCODERS_MICROB2_ENABLED + INIT(2); +#endif + +#ifdef ENCODERS_MICROB4_ENABLED + INIT(4); +#endif + +#ifdef ENCODERS_MICROB6_ENABLED + INIT(6); +#endif + + + SEL_B(); + // wait at least 10us + wait_4cyc(50); + +#ifdef ENCODERS_MICROB1_ENABLED + INIT(1); +#endif + +#ifdef ENCODERS_MICROB3_ENABLED + INIT(3); +#endif + +#ifdef ENCODERS_MICROB5_ENABLED + INIT(5); +#endif + +#ifdef ENCODERS_MICROB7_ENABLED + INIT(7); +#endif + IRQ_UNLOCK(flags); + +} + + +/** + * Update encoders values, need to be done quite often + * (Fmax_encoders/64). First, encoders 0 2 4 6 are read, and at next call + * encoders 1 3 5 7. + * + * \param dummy : a (void *) pointer that is not used. It is here according + * to the encoders interface. + */ +void encoders_microb_manage(void * dummy) +{ + static uint8_t sel=0; + uint8_t flags; + + + int8_t val, res; + + IRQ_LOCK(flags); + + if ( ! sel) /* here SEL_A() is set since last call */ + { +#ifdef ENCODERS_MICROB0_ENABLED + READ(0); +#endif + +#ifdef ENCODERS_MICROB2_ENABLED + READ(2); +#endif + +#ifdef ENCODERS_MICROB4_ENABLED + READ(4); +#endif + +#ifdef ENCODERS_MICROB6_ENABLED + READ(6); +#endif + + SEL_B(); + } + else /* here SEL_B() is set since last call */ + { +#ifdef ENCODERS_MICROB1_ENABLED + READ(1); +#endif + +#ifdef ENCODERS_MICROB3_ENABLED + READ(3); +#endif + +#ifdef ENCODERS_MICROB5_ENABLED + READ(5); +#endif + +#ifdef ENCODERS_MICROB7_ENABLED + READ(7); +#endif + + SEL_A(); + } + + sel = !sel; + + IRQ_UNLOCK(flags); + +} + + + +/** Extract encoder value. + * + * \param number : a (void *) that is casted in (int) containing the number + * of the encoder to be read. + */ +int32_t encoders_microb_get_value(void * number) +{ + int32_t value; + uint8_t flags; + + IRQ_LOCK(flags); + value = g_encoders_microb_values[(int)number]; + IRQ_UNLOCK(flags); + + return value; +} + +/** Set an encoder value + * + * \param number : a (void *) that is casted in (int) containing the number + * of the encoder to be read. + * \param v : the value + */ +void encoders_microb_set_value(void * number, int32_t v) +{ + uint8_t flags; + + IRQ_LOCK(flags); + g_encoders_microb_values[(int)number] = v; + IRQ_UNLOCK(flags); +} diff --git a/modules/devices/encoders/encoders_microb/encoders_microb.h b/modules/devices/encoders/encoders_microb/encoders_microb.h new file mode 100644 index 0000000..a9f8c25 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/encoders_microb.h @@ -0,0 +1,55 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_microb.h,v 1.4.4.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ + +#ifndef _ENCODERS_MICROB_H_ +#define _ENCODERS_MICROB_H_ + +/** + * Initialisation of encoders, variables + */ +void encoders_microb_init(void); + +/** + * Update encoders values, need to be done quite often + * (Fmax_encoders/64). First, encoders 0 2 4 6 are read, and at next call + * encoders 1 3 5 7. + * + * \param dummy : a (void *) pointer that is not used. It is here according + * to the encoders interface. + */ +void encoders_microb_manage(void * dummy); + +/** Extract encoder value. + * + * \param data : a (void *) that is casted in (uint8_t) containing the number + * of the encoder to be read. + */ +int32_t encoders_microb_get_value(void * data); + +/** Set an encoder value + * + * \param data : a (void *) that is casted in (uint8_t) containing the number + * of the encoder to be read. + * \param v : the value + */ +void encoders_microb_set_value(void * data, int32_t c); + +#endif diff --git a/modules/devices/encoders/encoders_microb/test/.config b/modules/devices/encoders/encoders_microb/test/.config new file mode 100644 index 0000000..1fcdd5d --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/.config @@ -0,0 +1,159 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# To see all modules here, you must enable utils and wait modules, and math library +# +CONFIG_MODULE_UTILS=y +CONFIG_MODULE_UTILS_CREATE_CONFIG=y +CONFIG_MODULE_FIXED_POINT=y +CONFIG_MODULE_WAIT=y +CONFIG_MODULE_WAIT_CREATE_CONFIG=y +CONFIG_MODULE_LIST=y +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y + +# +# Communication modules +# + +# +# Some communications modules depend on utils and list modules +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y + +# +# Hardware modules +# + +# +# Hardware modules depend on utils module +# +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set + +# +# Encoders (you should enable utils and fixed_point modules to see all available encoders) +# +CONFIG_MODULE_ENCODERS_MICROB=y +CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG=y + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters (you should enable utils and fixed_point modules to see all available filters) +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" diff --git a/modules/devices/encoders/encoders_microb/test/CVS/Entries b/modules/devices/encoders/encoders_microb/test/CVS/Entries new file mode 100644 index 0000000..7f34666 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.4.4.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/encoders_microb_config.h/1.3.4.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/main.c/1.4.4.2/Wed May 23 17:18:13 2007//Tb_zer0 +/scheduler_config.h/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/uart_config.h/1.2.6.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D diff --git a/modules/devices/encoders/encoders_microb/test/CVS/Repository b/modules/devices/encoders/encoders_microb/test/CVS/Repository new file mode 100644 index 0000000..cdbe594 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_microb/test diff --git a/modules/devices/encoders/encoders_microb/test/CVS/Root b/modules/devices/encoders/encoders_microb/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_microb/test/CVS/Tag b/modules/devices/encoders/encoders_microb/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_microb/test/CVS/Template b/modules/devices/encoders/encoders_microb/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_microb/test/Makefile b/modules/devices/encoders/encoders_microb/test/Makefile new file mode 100644 index 0000000..d2c03d8 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/encoders/encoders_microb/test/encoders_microb_config.h b/modules/devices/encoders/encoders_microb/test/encoders_microb_config.h new file mode 100644 index 0000000..17f4d25 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/encoders_microb_config.h @@ -0,0 +1,45 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_microb_config.h,v 1.3.4.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ +#ifndef _ENCODERS_MICROB_CONFIG_H_ +#define _ENCODERS_MICROB_CONFIG_H_ + +/** number of the LAST encoders used + 1 */ +#define ENCODERS_MICROB_NUMBER 4 + +#define ENCODERS_MICROB_SEL_PORT PORTE +#define ENCODERS_MICROB_SEL_BIT 6 + +#define ENCODERS_MICROB0_ENABLED +#define ENCODERS_MICROB0_PIN PINA + +#define ENCODERS_MICROB1_ENABLED +#define ENCODERS_MICROB1_PIN PINA + +#define ENCODERS_MICROB2_ENABLED +#define ENCODERS_MICROB2_PIN PINC + +#define ENCODERS_MICROB3_ENABLED +#define ENCODERS_MICROB3_PIN PINC + + +// ... until 7 + +#endif diff --git a/modules/devices/encoders/encoders_microb/test/main.c b/modules/devices/encoders/encoders_microb/test/main.c new file mode 100644 index 0000000..7c3a851 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/main.c @@ -0,0 +1,64 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4.4.2 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#include <stdlib.h> +#include <stdio.h> +#include <aversive.h> +#include <aversive/wait.h> +#include <uart.h> +#include <scheduler.h> +#include <encoders_microb.h> + +int main(void) +{ + uint8_t i=0; + int32_t e0, e1, e2, e3; + DDRE=0x0C; + + sbi(PORTE, 2); + uart_init(); + scheduler_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + encoders_microb_init(); + + sei(); + + /* add microb encoders management */ + scheduler_add_periodical_event(encoders_microb_manage, NULL, 1); + + while(1) { + e0 = encoders_microb_get_value_adjusted((void *)0); + e1 = encoders_microb_get_value_adjusted((void *)1); + e2 = encoders_microb_get_value_adjusted((void *)2); + e3 = encoders_microb_get_value_adjusted((void *)3); + + printf("%.8ld %.8ld %.8ld %.8ld\r\n", e0, e1, e2, e3); + + if (i++ % 2) + sbi(PORTE, 2); + else + cbi(PORTE, 2); + wait_ms(100); + } + + return 0; + +} diff --git a/modules/devices/encoders/encoders_microb/test/scheduler_config.h b/modules/devices/encoders/encoders_microb/test/scheduler_config.h new file mode 100644 index 0000000..0635998 --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/scheduler_config.h @@ -0,0 +1,29 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.2.6.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + + +#define SCHEDULER_NB_MAX_EVENT 2 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/devices/encoders/encoders_microb/test/uart_config.h b/modules/devices/encoders/encoders_microb/test/uart_config.h new file mode 100644 index 0000000..46ce84c --- /dev/null +++ b/modules/devices/encoders/encoders_microb/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.6.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/encoders/encoders_spi/CVS/Entries b/modules/devices/encoders/encoders_spi/CVS/Entries new file mode 100644 index 0000000..0f25b53 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Fri Feb 20 20:24:22 2009//Tb_zer0 +/encoders_spi.c/1.1.2.3/Tue Apr 7 20:00:46 2009//Tb_zer0 +/encoders_spi.h/1.1.2.1/Fri Feb 20 20:24:21 2009//Tb_zer0 +D/config//// diff --git a/modules/devices/encoders/encoders_spi/CVS/Repository b/modules/devices/encoders/encoders_spi/CVS/Repository new file mode 100644 index 0000000..8f129a6 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_spi diff --git a/modules/devices/encoders/encoders_spi/CVS/Root b/modules/devices/encoders/encoders_spi/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_spi/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_spi/CVS/Tag b/modules/devices/encoders/encoders_spi/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_spi/CVS/Template b/modules/devices/encoders/encoders_spi/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_spi/Makefile b/modules/devices/encoders/encoders_spi/Makefile new file mode 100644 index 0000000..29d4680 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/Makefile @@ -0,0 +1,6 @@ +TARGET = encoders_spi + +# List C source files here. (C dependencies are automatically generated.) +SRC = encoders_spi.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/encoders/encoders_spi/config/CVS/Entries b/modules/devices/encoders/encoders_spi/config/CVS/Entries new file mode 100644 index 0000000..8e06103 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/config/CVS/Entries @@ -0,0 +1,2 @@ +/encoders_spi_config.h/1.1.2.1/Fri Feb 20 20:24:21 2009//Tb_zer0 +D diff --git a/modules/devices/encoders/encoders_spi/config/CVS/Repository b/modules/devices/encoders/encoders_spi/config/CVS/Repository new file mode 100644 index 0000000..acd4e67 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/encoders/encoders_spi/config diff --git a/modules/devices/encoders/encoders_spi/config/CVS/Root b/modules/devices/encoders/encoders_spi/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/encoders/encoders_spi/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/encoders/encoders_spi/config/CVS/Tag b/modules/devices/encoders/encoders_spi/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/encoders/encoders_spi/config/CVS/Template b/modules/devices/encoders/encoders_spi/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/encoders/encoders_spi/config/encoders_spi_config.h b/modules/devices/encoders/encoders_spi/config/encoders_spi_config.h new file mode 100644 index 0000000..c67dfb0 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/config/encoders_spi_config.h @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_spi_config.h,v 1.1.2.1 2009-02-20 20:24:21 zer0 Exp $ + * + */ +#ifndef _ENCODERS_SPI_CONFIG_H_ +#define _ENCODERS_SPI_CONFIG_H_ + +#define ENCODERS_SPI_NUMBER 4 +#define ENCODERS_SPI_SS_PORT SS_PORT +#define ENCODERS_SPI_SS_BIT SS_BIT + +/* see spi configuration */ +#define ENCODERS_SPI_CLK_RATE SPI_CLK_RATE_16 +#define ENCODERS_SPI_FORMAT SPI_FORMAT_3 +#define ENCODERS_SPI_DATA_ORDER SPI_LSB_FIRST + +#endif diff --git a/modules/devices/encoders/encoders_spi/encoders_spi.c b/modules/devices/encoders/encoders_spi/encoders_spi.c new file mode 100644 index 0000000..a672803 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/encoders_spi.c @@ -0,0 +1,103 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_spi.c,v 1.1.2.3 2009-04-07 20:00:46 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +/* This modules handles encoders: values are read through a SPI + * interface. Basically, frames are formatted with 4 words of 16 bits, + * describing the values of the 4 encoders. */ + +#include <string.h> + +#include <aversive.h> +#include <aversive/parts.h> + +#include <spi.h> + +#include <encoders_spi.h> +#include <encoders_spi_config.h> + +static int32_t g_encoders_spi_values[ENCODERS_SPI_NUMBER]; +static int16_t g_encoders_spi_previous[ENCODERS_SPI_NUMBER]; + + +/* Initialisation of encoders, variables */ +void encoders_spi_init(void) +{ + memset(g_encoders_spi_previous, 0, sizeof(g_encoders_spi_previous)); + spi_register_ss_line(&ENCODERS_SPI_SS_PORT, ENCODERS_SPI_SS_BIT); + spi_init(SPI_MODE_MASTER, ENCODERS_SPI_FORMAT, ENCODERS_SPI_CLK_RATE); + spi_set_data_order(ENCODERS_SPI_DATA_ORDER); + encoders_spi_manage(NULL); + memset(g_encoders_spi_values, 0, sizeof(g_encoders_spi_values)); +} + + +/* Update encoders values */ +void encoders_spi_manage(__attribute__((unused)) void *dummy) +{ + union { + struct { + uint8_t u8_lsb; + uint8_t u8_msb; + } s; + int16_t s16; + } enc; + uint8_t i; + int16_t diff; + uint8_t flags; + + spi_slave_select(0); + for (i=0; i<ENCODERS_SPI_NUMBER; i++) { + enc.s.u8_lsb = spi_receive_byte(); + enc.s.u8_msb = spi_receive_byte(); + diff = enc.s16 - g_encoders_spi_previous[i]; + g_encoders_spi_previous[i] = enc.s16; + IRQ_LOCK(flags); + g_encoders_spi_values[i] += diff; + IRQ_UNLOCK(flags); + } + spi_slave_deselect(0); +} + + + +/* Extract encoder value */ +int32_t encoders_spi_get_value(void *encoder) +{ + int32_t value; + uint8_t flags; + + IRQ_LOCK(flags); + value = g_encoders_spi_values[(int)encoder]; + IRQ_UNLOCK(flags); + + return value; +} + +/* Set an encoder value */ +void encoders_spi_set_value(void *encoder, int32_t val) +{ + uint8_t flags; + + IRQ_LOCK(flags); + g_encoders_spi_values[(int)encoder] = val; + IRQ_UNLOCK(flags); +} diff --git a/modules/devices/encoders/encoders_spi/encoders_spi.h b/modules/devices/encoders/encoders_spi/encoders_spi.h new file mode 100644 index 0000000..9382748 --- /dev/null +++ b/modules/devices/encoders/encoders_spi/encoders_spi.h @@ -0,0 +1,46 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_spi.h,v 1.1.2.1 2009-02-20 20:24:21 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#ifndef _ENCODERS_SPI_H_ +#define _ENCODERS_SPI_H_ + +/** + * Initialisation of encoders, variables + */ +void encoders_spi_init(void); + +/** + * Update encoders values, need to be done quite often + */ +void encoders_spi_manage(void *dummy); + +/** + * Extract encoder value. + */ +int32_t encoders_spi_get_value(void *encoder); + +/** + * Set an encoder value + */ +void encoders_spi_set_value(void *encoder, int32_t val); + +#endif diff --git a/modules/devices/ihm/CVS/Entries b/modules/devices/ihm/CVS/Entries new file mode 100644 index 0000000..e4250da --- /dev/null +++ b/modules/devices/ihm/CVS/Entries @@ -0,0 +1 @@ +D/lcd//// diff --git a/modules/devices/ihm/CVS/Repository b/modules/devices/ihm/CVS/Repository new file mode 100644 index 0000000..c61f74b --- /dev/null +++ b/modules/devices/ihm/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/ihm diff --git a/modules/devices/ihm/CVS/Root b/modules/devices/ihm/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/ihm/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/ihm/CVS/Tag b/modules/devices/ihm/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/ihm/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/ihm/CVS/Template b/modules/devices/ihm/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/ihm/lcd/CVS/Entries b/modules/devices/ihm/lcd/CVS/Entries new file mode 100644 index 0000000..f5603a0 --- /dev/null +++ b/modules/devices/ihm/lcd/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.1.10.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +/lcd.c/1.5.4.3/Sun Aug 19 10:39:31 2007//Tb_zer0 +/lcd.h/1.3.4.3/Sun Aug 19 10:39:31 2007//Tb_zer0 +/lcd_protocol.h/1.1.10.1/Sun Nov 26 21:06:04 2006//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/ihm/lcd/CVS/Repository b/modules/devices/ihm/lcd/CVS/Repository new file mode 100644 index 0000000..ea83a3b --- /dev/null +++ b/modules/devices/ihm/lcd/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/ihm/lcd diff --git a/modules/devices/ihm/lcd/CVS/Root b/modules/devices/ihm/lcd/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/ihm/lcd/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/ihm/lcd/CVS/Tag b/modules/devices/ihm/lcd/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/ihm/lcd/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/ihm/lcd/CVS/Template b/modules/devices/ihm/lcd/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/ihm/lcd/Makefile b/modules/devices/ihm/lcd/Makefile new file mode 100644 index 0000000..f003f75 --- /dev/null +++ b/modules/devices/ihm/lcd/Makefile @@ -0,0 +1,7 @@ +TARGET = lcd + +# List C source files here. (C dependencies are automatically generated.) +SRC = lcd.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk + diff --git a/modules/devices/ihm/lcd/config/CVS/Entries b/modules/devices/ihm/lcd/config/CVS/Entries new file mode 100644 index 0000000..57e0e4c --- /dev/null +++ b/modules/devices/ihm/lcd/config/CVS/Entries @@ -0,0 +1,2 @@ +/lcd_config.h/1.1.10.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +D diff --git a/modules/devices/ihm/lcd/config/CVS/Repository b/modules/devices/ihm/lcd/config/CVS/Repository new file mode 100644 index 0000000..462c125 --- /dev/null +++ b/modules/devices/ihm/lcd/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/ihm/lcd/config diff --git a/modules/devices/ihm/lcd/config/CVS/Root b/modules/devices/ihm/lcd/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/ihm/lcd/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/ihm/lcd/config/CVS/Tag b/modules/devices/ihm/lcd/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/ihm/lcd/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/ihm/lcd/config/CVS/Template b/modules/devices/ihm/lcd/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/ihm/lcd/config/lcd_config.h b/modules/devices/ihm/lcd/config/lcd_config.h new file mode 100644 index 0000000..b36a315 --- /dev/null +++ b/modules/devices/ihm/lcd/config/lcd_config.h @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: lcd_config.h,v 1.1.10.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +/* change these definitions to adapt setting */ +// changed PIN in BIT to avoid confusion, don'use old version +#define LCD_PORT PORTC + +/* If the LCD module is a 1 line version with double addressing (8 + chars by segment), you need to define LCD_LINES to 2 and + LCD_DOUBLE_ADDRESSING to 1. This is the case with for example + SAMSUNG LTN 211 - N01. +*/ + +#define LCD_LINES 2 /* visible lines */ +#define LCD_LINE_LENGTH 0x40 /* internal line length */ +#define LCD_START_LINE1 0x00 /* DDRAM address of first char of line 1 */ +#define LCD_START_LINE2 0x40 /* DDRAM address of first char of line 2 */ +#define LCD_START_LINE3 0x14 /* DDRAM address of first char of line 3 */ +#define LCD_START_LINE4 0x54 /* DDRAM address of first char of line 4 */ + +#define LCD_DOUBLE_ADDRESSING 1 + +#define LCD_DATA_PORT LCD_PORT /* port for 4bit data */ +#define LCD_FIRST_DATA_BIT 3 +#define LCD_RS_PORT LCD_PORT /* port for RS line */ +#define LCD_RS_BIT 0 +#define LCD_RW_PORT LCD_PORT /* port for RW line */ +#define LCD_RW_BIT 1 +#define LCD_E_PORT LCD_PORT /* port for Enable line */ +#define LCD_E_BIT 2 diff --git a/modules/devices/ihm/lcd/lcd.c b/modules/devices/ihm/lcd/lcd.c new file mode 100755 index 0000000..9e0b2bd --- /dev/null +++ b/modules/devices/ihm/lcd/lcd.c @@ -0,0 +1,368 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: lcd.c,v 1.5.4.3 2007-08-19 10:39:31 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Implementation for LCD + */ + +/** \file lcd.c + * \brief Implementation for the LCD module. + * + * \todo Test the module with other wirings, verify the delay macro, stqtic inlines for the public functions ?? + * + * \test works on mega32 with all on the same port and old normal wiring, how about more speific connections ? + * + * This module provides functions for using a lcd device + */ + + + +#include <stdio.h> + +#include <aversive/pgmspace.h> +#include <aversive.h> +#include <aversive/wait.h> + +#include <lcd.h> +#include <lcd_protocol.h> + + +//#define lcd_e_delay() asm volatile("nop") /* delay 500ns with 4Mhz */ +#define e_delay() _delay_loop_1(1) // ok ca ? + + +/**********************************************************/ +/* +** port level functions +*/ + +// DDR en sortie +static inline void port_set_out(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); // if there is some other stuff on the same port + DDR(LCD_PORT) |= LCD_DATA_MASK; + IRQ_UNLOCK(flags); +} + +// DDR en entree +static inline void port_set_in(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + DDR(LCD_PORT) &= ~(LCD_DATA_MASK); + IRQ_UNLOCK(flags); +} + + +/* toggle Enable Pin */ +static inline void e_toggle(void) +{ + sbi(LCD_E_PORT, LCD_E_BIT); + e_delay(); + cbi(LCD_E_PORT, LCD_E_BIT); +} + +/**********************************************************/ +/* +** byte level functions +*/ +static inline void lcd_write(uint8_t data,uint8_t rs) +{ + register uint8_t port_save; + uint8_t flags; + + + port_set_out(); + + + cbi(LCD_RW_PORT, LCD_RW_BIT);//RW=0 + + if (rs) + sbi(LCD_RS_PORT, LCD_RS_BIT); //RS=1 + else + cbi(LCD_RS_PORT, LCD_RS_BIT); //RS=0 + + + // port state save + IRQ_LOCK(flags); + + port_save= LCD_DATA_PORT & ~(LCD_DATA_MASK); + + /* output high nibble first */ + LCD_DATA_PORT = ( ( ((data>>4) << LCD_FIRST_DATA_BIT) & LCD_DATA_MASK ) + | port_save ); + + e_toggle(); + + /* output low nibble */ + LCD_DATA_PORT = ( ((data<<LCD_FIRST_DATA_BIT) & LCD_DATA_MASK) + | port_save ); + + + IRQ_UNLOCK(flags); + + e_toggle(); +} + + + +static uint8_t lcd_read(uint8_t rs) +{ + register uint8_t dataH, dataL; + + + if (rs) sbi(LCD_RS_PORT, LCD_RS_BIT); /* RS=1: read data */ + else cbi(LCD_RS_PORT, LCD_RS_BIT); /* RS=0: read busy flag */ + sbi(LCD_RW_PORT, LCD_RW_BIT); /* RW=1 read mode */ + + /* configure data pins as input */ + port_set_in(); + + sbi(LCD_E_PORT, LCD_E_BIT); + e_delay(); + + + dataH = PIN(LCD_PORT) >> LCD_FIRST_DATA_BIT ;/* read high nibble first */ + + cbi(LCD_E_PORT, LCD_E_BIT); + e_delay(); /* Enable 500ns low */ + + + sbi(LCD_E_PORT, LCD_E_BIT); + e_delay(); + + dataL = PIN(LCD_PORT) >> LCD_FIRST_DATA_BIT ; /* read low nibble */ + + cbi(LCD_E_PORT, LCD_E_BIT); + + return ( (dataH<<4) | (dataL&0x0F) ); +} + + +// use for init, to set lcd mode to 4 bits +void initial_8_bit_write(uint8_t value) +{ + register uint8_t port_save; + uint8_t flags; + + + cbi(LCD_RW_PORT, LCD_RW_BIT); + + cbi(LCD_RS_PORT, LCD_RS_BIT); + + + IRQ_LOCK(flags); + + // port save + port_save = LCD_DATA_PORT & ~(LCD_DATA_MASK); + + + LCD_DATA_PORT = ( ((value <<LCD_FIRST_DATA_BIT) & LCD_DATA_MASK) + | port_save ); + + IRQ_UNLOCK(flags); + + e_toggle(); + wait_ms(1); // delay, busy flag can't be checked here +} + +/**********************************************************/ +/* +** commands and more +*/ + +static inline unsigned char lcd_waitbusy(void) +/* loops while lcd is busy, reads address counter */ +{ + register unsigned char c; + + while ( (c=lcd_read(0)) & (1<<LCD_BUSY)) ; + + return (c); // return address counter +} + + + +void lcd_command(uint8_t cmd) + /* send commando <cmd> to LCD */ +{ + lcd_waitbusy(); + lcd_write(cmd,0); +} + + + +static inline void lcd_newline(uint8_t pos) + /* goto start of next line */ +{ + register uint8_t addressCounter; + + +#if LCD_LINES==1 + addressCounter = 0; +#endif +#if LCD_LINES==2 + if ( pos < (LCD_START_LINE2) ) + addressCounter = LCD_START_LINE2; + else + addressCounter = LCD_START_LINE1; +#endif +#if LCD_LINES==4 + if ( pos < LCD_START_LINE3 ) + addressCounter = LCD_START_LINE2; + else if ( (pos >= LCD_START_LINE2) && (pos < LCD_START_LINE4) ) + addressCounter = LCD_START_LINE3; + else if ( (pos >= LCD_START_LINE3) && (pos < LCD_START_LINE2) ) + addressCounter = LCD_START_LINE4; + else + addressCounter = LCD_START_LINE1; +#endif + + + lcd_command((1<<LCD_DDRAM)+addressCounter); + +}/* lcd_newline */ + + + + + + +/**********************************************************/ + +/* +** PUBLIC FUNCTIONS +*/ + + + +void lcd_gotoxy(uint8_t x, uint8_t y) + /* goto position (x,y) */ +{ +#if (LCD_LINES==1) + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE1+x); +#endif +#if (LCD_LINES==2) + if ( y==0 ) + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE1+x); + else + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE2+x); +#endif +#if LCD_LINES==4 + if ( y==0 ) + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE1+x); + else if ( y==1) + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE2+x); + else if ( y==2) + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE3+x); + else /* y==3 */ + lcd_command((1<<LCD_DDRAM)+LCD_START_LINE4+x); +#endif + +}/* lcd_gotoxy */ + + + + +void lcd_clrscr(void) + /* clear lcd and set cursor to home position */ +{ + lcd_command(1<<LCD_CLR); +} + + + +void lcd_home(void) + /* set cursor to home position */ +{ + lcd_command(1<<LCD_HOME); +} + + + +void lcd_putc(char c) + /* print character at current cursor position */ +{ + register unsigned char pos; + + pos = lcd_waitbusy(); // read busy-flag and address counter + +#if LCD_DOUBLE_ADDRESSING == 1 + if(pos==8) + { + lcd_gotoxy(0,1); + lcd_waitbusy(); + } +#endif + + if (c=='\n') // new line + lcd_newline(pos); + else if (c== '\f') // form feed = clear screen + lcd_clrscr(); + else // normal car + lcd_write(c, 1); +} + +/* for use with fdevopen */ +int lcd_dev_putc(char c, FILE* f) +{ + lcd_putc(c); + return c; +} + +void lcd_init(uint8_t dispAttr) + /* initialize display and select type of cursor */ + /* dispAttr: LCD_DISP_OFF, LCD_DISP_ON, LCD_DISP_ON_CURSOR, LCD_DISP_CURSOR_BLINK */ +{ + + + // DDRs + port_set_out(); + + sbi(DDR(LCD_RW_PORT), LCD_RW_BIT); + sbi(DDR(LCD_RS_PORT), LCD_RS_BIT); + sbi(DDR(LCD_E_PORT), LCD_E_BIT); + + + wait_ms(16); /* wait 16ms or more after power-on */ + + /*------ Initialize lcd to 4 bit i/o mode -------*/ + /* initial write to lcd is 8bit */ + initial_8_bit_write(LCD_FUNCTION_8BIT_1LINE>>4); + initial_8_bit_write(LCD_FUNCTION_8BIT_1LINE>>4); + initial_8_bit_write(LCD_FUNCTION_8BIT_1LINE>>4); + initial_8_bit_write(LCD_FUNCTION_4BIT_1LINE>>4); + + + + lcd_command(LCD_FUNCTION_DEFAULT); /* function set: display lines */ + lcd_command(LCD_DISP_OFF); /* display off */ + lcd_clrscr(); /* display clear */ + lcd_command(LCD_MODE_DEFAULT); /* set entry mode */ + lcd_command(dispAttr); /* display/cursor control */ + + + + +}/* lcd_init */ diff --git a/modules/devices/ihm/lcd/lcd.h b/modules/devices/ihm/lcd/lcd.h new file mode 100755 index 0000000..5a12d04 --- /dev/null +++ b/modules/devices/ihm/lcd/lcd.h @@ -0,0 +1,81 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: lcd.h,v 1.3.4.3 2007-08-19 10:39:31 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Interface for LCD + */ + +/** \file lcd.c + * \brief Interface for the LCD module. + * + * \todo implement ANSI commands for cursor positionning ? + * + * \test works on mega32 with all on the same port and old normal wiring, how about more speific connections ? + * + * This module provides functions for using a standard lcd device + * the lcd s intended to be used in 4 bit mode, so don't wire the low nibble, only D4-D7 to 4 CONSECUTIVE port lines + * we need the RW, RS and E lines too. + * since the last version, you can scramble the wiring, except for D4-D7 who must remain consecutive (see lcd_config.h) + * + * in this new version you can use lcd_putc('\f'); to clear the screen. This maintains an easy compatibility + * when you want to use an uart instad (form feed). + */ + +/**********************************************************/ + +#ifndef _LCD_ +#define _LCD_ + +#include <stdio.h> + +#include <aversive.h> +#include "lcd_protocol.h" + +/** + * Init the LCD module + */ +extern void lcd_init(uint8_t dispAttr); + +/** + * Put a char on screen + * if c = \n cursor is positioned on the next line + * if c = \f the screen will be cleared + */ +extern void lcd_putc(char c); + +/** + * same than lcd_putc but with a prototype that is compliant with + * avrlibc > 1.4.0 fdevopen prototype + */ +extern int lcd_dev_putc(char c, FILE* f); + +/** + * move the cursor in the screen, x= line, y = char + */ +extern void lcd_gotoxy(uint8_t x, uint8_t y); + +/** + * clear all the screen + * avoid using this function, escpecially if you use printf + */ +extern void lcd_clrscr(void); + +#endif // _LCD_ diff --git a/modules/devices/ihm/lcd/lcd_protocol.h b/modules/devices/ihm/lcd/lcd_protocol.h new file mode 100644 index 0000000..68fea74 --- /dev/null +++ b/modules/devices/ihm/lcd/lcd_protocol.h @@ -0,0 +1,96 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: lcd_protocol.h,v 1.1.10.1 2006-11-26 21:06:04 zer0 Exp $ + * + */ + +#ifndef LCD_H +#define LCD_H + +#include "lcd_config.h" + + +// masque des broches concernees sur le port + +#define LCD_DATA_MASK (0x0F << LCD_FIRST_DATA_BIT) + +/* instruction register bit positions */ +#define LCD_CLR 0 /* DB0: clear display */ +#define LCD_HOME 1 /* DB1: return to home position */ +#define LCD_ENTRY_MODE 2 /* DB2: set entry mode */ +#define LCD_ENTRY_INC 1 /* DB1: 1=increment, 0=decrement */ +#define LCD_ENTRY_SHIFT 0 /* DB2: 1=display shift on */ +#define LCD_ON 3 /* DB3: turn lcd/cursor on */ +#define LCD_ON_DISPLAY 2 /* DB2: turn display on */ +#define LCD_ON_CURSOR 1 /* DB1: turn cursor on */ +#define LCD_ON_BLINK 0 /* DB0: blinking cursor ? */ +#define LCD_MOVE 4 /* DB4: move cursor/display */ +#define LCD_MOVE_DISP 3 /* DB3: move display (0-> cursor) ? */ +#define LCD_MOVE_RIGHT 2 /* DB2: move right (0-> left) ? */ +#define LCD_FUNCTION 5 /* DB5: function set */ +#define LCD_FUNCTION_8BIT 4 /* DB4: set 8BIT mode (0->4BIT mode) */ +#define LCD_FUNCTION_2LINES 3 /* DB3: two lines (0->one line) */ +#define LCD_FUNCTION_10DOTS 2 /* DB2: 5x10 font (0->5x7 font) */ +#define LCD_CGRAM 6 /* DB6: set CG RAM address */ +#define LCD_DDRAM 7 /* DB7: set DD RAM address */ +#define LCD_BUSY 7 /* DB7: LCD is busy */ + +/* set entry mode: display shift on/off, dec/inc cursor move direction */ +#define LCD_ENTRY_DEC 0x04 /* display shift off, dec cursor move dir */ +#define LCD_ENTRY_DEC_SHIFT 0x05 /* display shift on, dec cursor move dir */ +#define LCD_ENTRY_INC_ 0x06 /* display shift off, inc cursor move dir */ +#define LCD_ENTRY_INC_SHIFT 0x07 /* display shift on, inc cursor move dir */ + +/* display on/off, cursor on/off, blinking char at cursor position */ +#define LCD_DISP_OFF 0x08 /* display off */ +#define LCD_DISP_ON 0x0C /* display on, cursor off */ +#define LCD_DISP_ON_BLINK 0x0D /* display on, cursor off, blink char */ +#define LCD_DISP_ON_CURSOR 0x0E /* display on, cursor on */ +#define LCD_DISP_ON_CURSOR_BLINK 0x0F /* display on, cursor on, blink char */ + +/* move cursor/shift display */ +#define LCD_MOVE_CURSOR_LEFT 0x10 /* move cursor left (decrement) */ +#define LCD_MOVE_CURSOR_RIGHT 0x14 /* move cursor right (increment) */ +#define LCD_MOVE_DISP_LEFT 0x18 /* shift display left */ +#define LCD_MOVE_DISP_RIGHT 0x1C /* shift display right */ + +/* function set: set interface data length and number of display lines */ +#define LCD_FUNCTION_4BIT_1LINE 0x20 /* 4-bit interface, single line, 5x7 dots */ +#define LCD_FUNCTION_4BIT_2LINES 0x28 /* 4-bit interface, dual line, 5x7 dots */ +#define LCD_FUNCTION_8BIT_1LINE 0x30 /* 8-bit interface, single line, 5x7 dots */ +#define LCD_FUNCTION_8BIT_2LINES 0x38 /* 8-bit interface, dual line, 5x7 dots */ + +#if LCD_LINES==1 +#define LCD_FUNCTION_DEFAULT LCD_FUNCTION_4BIT_1LINE +#else +#define LCD_FUNCTION_DEFAULT LCD_FUNCTION_4BIT_2LINES +#endif + + +#define LCD_MODE_DEFAULT ((1<<LCD_ENTRY_MODE) | (1<<LCD_ENTRY_INC) ) + +/* +** macros for automatically storing string constant in program memory +*/ +#ifndef P +#define P(s) ({static const char c[] __attribute__ ((progmem)) = s;c;}) +#endif +#define lcd_puts_P(__s) lcd_puts_p(P(__s)) + + +#endif //LCD_PROTOCOLE_H diff --git a/modules/devices/ihm/lcd/test/.config b/modules/devices/ihm/lcd/test/.config new file mode 100644 index 0000000..90dc3fb --- /dev/null +++ b/modules/devices/ihm/lcd/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +CONFIG_MODULE_LCD=y +CONFIG_MODULE_LCD_CREATE_CONFIG=y +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/ihm/lcd/test/CVS/Entries b/modules/devices/ihm/lcd/test/CVS/Entries new file mode 100644 index 0000000..fcbfa37 --- /dev/null +++ b/modules/devices/ihm/lcd/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.7.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.10.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/error_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/lcd_config.h/1.1.10.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/list_config.h/1.1.10.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/main.c/1.4.4.2/Wed May 23 17:18:13 2007//Tb_zer0 +D diff --git a/modules/devices/ihm/lcd/test/CVS/Repository b/modules/devices/ihm/lcd/test/CVS/Repository new file mode 100644 index 0000000..4869b51 --- /dev/null +++ b/modules/devices/ihm/lcd/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/ihm/lcd/test diff --git a/modules/devices/ihm/lcd/test/CVS/Root b/modules/devices/ihm/lcd/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/ihm/lcd/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/ihm/lcd/test/CVS/Tag b/modules/devices/ihm/lcd/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/ihm/lcd/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/ihm/lcd/test/CVS/Template b/modules/devices/ihm/lcd/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/ihm/lcd/test/Makefile b/modules/devices/ihm/lcd/test/Makefile new file mode 100644 index 0000000..99d1787 --- /dev/null +++ b/modules/devices/ihm/lcd/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/ihm/lcd/test/error_config.h b/modules/devices/ihm/lcd/test/error_config.h new file mode 100644 index 0000000..1de36e9 --- /dev/null +++ b/modules/devices/ihm/lcd/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/ihm/lcd/test/lcd_config.h b/modules/devices/ihm/lcd/test/lcd_config.h new file mode 100644 index 0000000..b36a315 --- /dev/null +++ b/modules/devices/ihm/lcd/test/lcd_config.h @@ -0,0 +1,48 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: lcd_config.h,v 1.1.10.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +/* change these definitions to adapt setting */ +// changed PIN in BIT to avoid confusion, don'use old version +#define LCD_PORT PORTC + +/* If the LCD module is a 1 line version with double addressing (8 + chars by segment), you need to define LCD_LINES to 2 and + LCD_DOUBLE_ADDRESSING to 1. This is the case with for example + SAMSUNG LTN 211 - N01. +*/ + +#define LCD_LINES 2 /* visible lines */ +#define LCD_LINE_LENGTH 0x40 /* internal line length */ +#define LCD_START_LINE1 0x00 /* DDRAM address of first char of line 1 */ +#define LCD_START_LINE2 0x40 /* DDRAM address of first char of line 2 */ +#define LCD_START_LINE3 0x14 /* DDRAM address of first char of line 3 */ +#define LCD_START_LINE4 0x54 /* DDRAM address of first char of line 4 */ + +#define LCD_DOUBLE_ADDRESSING 1 + +#define LCD_DATA_PORT LCD_PORT /* port for 4bit data */ +#define LCD_FIRST_DATA_BIT 3 +#define LCD_RS_PORT LCD_PORT /* port for RS line */ +#define LCD_RS_BIT 0 +#define LCD_RW_PORT LCD_PORT /* port for RW line */ +#define LCD_RW_BIT 1 +#define LCD_E_PORT LCD_PORT /* port for Enable line */ +#define LCD_E_BIT 2 diff --git a/modules/devices/ihm/lcd/test/list_config.h b/modules/devices/ihm/lcd/test/list_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/ihm/lcd/test/main.c b/modules/devices/ihm/lcd/test/main.c new file mode 100644 index 0000000..89cc3df --- /dev/null +++ b/modules/devices/ihm/lcd/test/main.c @@ -0,0 +1,101 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4.4.2 2007-05-23 17:18:13 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <aversive/pgmspace.h> + +#include <aversive.h> +#include <aversive/wait.h> +#include <lcd.h> + + +#define DELAY 100 + +int lcd_dev_putc_delay(char c, FILE* f) +{ + lcd_putc(c); + wait_ms(DELAY); + return c; +} + + +int main(void) +{ + FILE * slow; + uint8_t i; + + + wait_ms(100); + + + lcd_init(LCD_DISP_ON); + + + lcd_putc('j'); // ne doit pas etre visible + + + lcd_putc('\f'); // effacement + + + + + lcd_gotoxy(5,0); + lcd_putc('h'); wait_ms(DELAY); + lcd_putc('e'); wait_ms(DELAY); + lcd_putc('l'); wait_ms(DELAY); + lcd_putc('l'); wait_ms(DELAY); + lcd_putc('o'); wait_ms(DELAY); + + lcd_putc('\n'); + + + for(i=0;i<5;i++) lcd_putc(' '); + + lcd_putc('w'); wait_ms(DELAY); + lcd_putc('o'); wait_ms(DELAY); + lcd_putc('r'); wait_ms(DELAY); + lcd_putc('l'); wait_ms(DELAY); + lcd_putc('d'); wait_ms(DELAY); + + + + + wait_ms(20*DELAY); + + // with printf :) + fdevopen(lcd_dev_putc,NULL); + + lcd_putc('\f'); // effacement + printf_P(PSTR("big brother")); + + wait_ms(20*DELAY); + + slow = fdevopen(lcd_dev_putc_delay,NULL); + + fprintf_P(slow, PSTR("\fl' AVR c'est top\nl' AVR c'est tof")); + + while(1); + return 0; +} + + + + diff --git a/modules/devices/radio/CVS/Entries b/modules/devices/radio/CVS/Entries new file mode 100644 index 0000000..af59c72 --- /dev/null +++ b/modules/devices/radio/CVS/Entries @@ -0,0 +1 @@ +D/cc2420//// diff --git a/modules/devices/radio/CVS/Repository b/modules/devices/radio/CVS/Repository new file mode 100644 index 0000000..eee740d --- /dev/null +++ b/modules/devices/radio/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/radio diff --git a/modules/devices/radio/CVS/Root b/modules/devices/radio/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/radio/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/radio/CVS/Tag b/modules/devices/radio/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/radio/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/radio/CVS/Template b/modules/devices/radio/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/radio/cc2420/CVS/Entries b/modules/devices/radio/cc2420/CVS/Entries new file mode 100644 index 0000000..a10b369 --- /dev/null +++ b/modules/devices/radio/cc2420/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +/cc2420.c/1.1.2.2/Fri Feb 27 21:36:06 2009//Tb_zer0 +/cc2420.h/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +/cc2420_arch.h/1.1.2.1/Fri Jan 23 23:54:15 2009//Tb_zer0 +D/config//// diff --git a/modules/devices/radio/cc2420/CVS/Repository b/modules/devices/radio/cc2420/CVS/Repository new file mode 100644 index 0000000..7c09dac --- /dev/null +++ b/modules/devices/radio/cc2420/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/radio/cc2420 diff --git a/modules/devices/radio/cc2420/CVS/Root b/modules/devices/radio/cc2420/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/radio/cc2420/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/radio/cc2420/CVS/Tag b/modules/devices/radio/cc2420/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/radio/cc2420/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/radio/cc2420/CVS/Template b/modules/devices/radio/cc2420/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/radio/cc2420/Makefile b/modules/devices/radio/cc2420/Makefile new file mode 100644 index 0000000..64ec49d --- /dev/null +++ b/modules/devices/radio/cc2420/Makefile @@ -0,0 +1,10 @@ +#-include .config + +TARGET = cc2420 + +# List C source files here. (C dependencies are automatically generated.) +SRC = cc2420.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/radio/cc2420/cc2420.c b/modules/devices/radio/cc2420/cc2420.c new file mode 100644 index 0000000..cc3deff --- /dev/null +++ b/modules/devices/radio/cc2420/cc2420.c @@ -0,0 +1,265 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <spi.h> + +#include <cc2420.h> +#include <cc2420_arch.h> +#include <cc2420_config.h> + + +#define SLAVE_SELECT() spi_slave_select(g_slave_adr) +#define SLAVE_DESELECT() spi_slave_deselect(g_slave_adr) + +/* +#define SLAVE_SELECT() PORTC &= 0xFE +#define SLAVE_DESELECT() PORTC |= 0x01 +*/ + +volatile static uint8_t g_slave_adr; + + +/* + * Read status byte + */ +uint8_t cc2420_get_status(void) +{ + uint8_t tmp; + SLAVE_SELECT(); + tmp = spi_send_and_receive_byte(SNOP); + SLAVE_DESELECT(); + return tmp; +} + +/* + * Write to a strobe register + * Returns Status byte + */ +uint8_t cc2420_strobe_register(uint8_t reg) +{ + uint8_t tmp; + SLAVE_SELECT(); + tmp = spi_send_and_receive_byte(reg); + SLAVE_DESELECT(); + return tmp; +} + +/* + * Read a two-bytes register + */ +uint16_t cc2420_read_register(uint8_t reg) +{ + uint16_t value; + SLAVE_SELECT(); + /* Send address and READ action */ + spi_send_byte(REG_BIT | READ_BIT | (reg & REG_MASK)); + /* Just send nothing (0x00) and read the value back (MSB first) */ + value = spi_receive_byte(); + value = (value<<8) | spi_receive_byte(); + SLAVE_DESELECT(); + return value; +} + +/* + * Write to a two-bytes register + */ +void cc2420_write_register(uint8_t reg, uint16_t value) +{ + SLAVE_SELECT(); + /* Send address and WRITE action */ + spi_send_byte(REG_BIT | WRITE_BIT | (reg & REG_MASK)); + /* Send the value, ignore the status byte in return */ + spi_send_byte((uint8_t)((value & 0xFF00)>>8)); + spi_send_byte((uint8_t)(value & 0x00FF)); + SLAVE_DESELECT(); +} + +/* + * Write the contents of a buffer to TXFIFO + * Returns last read status byte + */ +uint8_t cc2420_write_txfifo(uint8_t *buffer, uint8_t length) +{ + uint8_t status; + uint8_t i; + SLAVE_SELECT(); + /* Flush the FIFO - don't need the status byte */ + //spi_send_byte(SFLUSHTX); + /* TXFIFO Register address */ + NOTICE(E_CC2420, "Writing %d bytes to TXFIFO at address 0x%x", length, REG_BIT | WRITE_BIT | TXFIFO); + spi_send_byte(REG_BIT | WRITE_BIT | TXFIFO); + /* Send all bytes */ + for(i = 0; i < length; i++) + { + /* We may need the status byte at any time + * For instance, to detect TXFIFO underflow */ + status = spi_send_and_receive_byte(buffer[i]); + } + SLAVE_DESELECT(); + return status; +} + +/* + * Write the contents of a buffer to RXFIFO + * Returns last read status byte + */ +uint8_t cc2420_write_rxfifo(uint8_t *buffer, uint8_t length) +{ + uint8_t status; + uint8_t i; + SLAVE_SELECT(); + /* Flush the FIFO - don't need the status byte */ + spi_send_byte(SFLUSHRX); + /* RXFIFO Register address */ + spi_send_byte(REG_BIT | WRITE_BIT | RXFIFO); + /* Send all bytes */ + for(i = 0; i < length; i++) + { + /* We may need the status byte at any time + * For instance, to detect TXFIFO underflow */ + status = spi_send_and_receive_byte(buffer[i]); + } + SLAVE_DESELECT(); + return status; +} + +/* + * Read the contents of RXFIFO into a buffer + */ +void cc2420_read_rxfifo(uint8_t *buffer, uint8_t length) +{ + uint8_t i; + SLAVE_SELECT(); + /* RXFIFO Register address */ + spi_send_byte(REG_BIT | READ_BIT | RXFIFO); + /* Read all bytes */ + for(i = 0; i < length; i++) + { + buffer[i] = spi_receive_byte(); + } + SLAVE_DESELECT(); +} + +/* XXX Ca fait de la merde dans le coin la... */ + +/* + * Write to a RAM address one or several byte(s) + * /!\ This is NOT foolproof, you have to be sure of the + * address you write to, and the length of your buffer + */ +void cc2420_write_ram(uint16_t addr, uint8_t *buffer, uint16_t length) +{ + uint16_t i; + SLAVE_SELECT(); + /* Forge the address */ + spi_send_byte(RAM_BIT | (addr & RAM_MASK)); + spi_send_byte((((addr>>1) & BANK_MASK) | RAM_READ_WRITE)); + /* Send the data */ + for(i = 0; i < length; i++) + { + spi_send_byte((uint8_t)buffer[i]); + } + SLAVE_DESELECT(); +} + +/* + * Read from RAM. Same warning. + */ +void cc2420_read_ram(uint16_t addr, uint8_t *buffer, uint16_t length) +{ + uint16_t i; + SLAVE_SELECT(); + /* Forge the address */ + spi_send_byte((RAM_BIT | (addr & RAM_MASK))); + spi_send_byte((((addr>>1) & BANK_MASK) | RAM_READ)); + /* Receive the data */ + for(i = 0; i < length; i++) + { + buffer[i] = spi_receive_byte(); + } + SLAVE_DESELECT(); +} + + + +/* + * Initialize ports and starts-up the chip + */ +void cc2420_init(void) +{ + NOTICE(E_CC2420, "Initialization"); + /* Check and start SPI module */ + if (spi_get_mode() == SPI_MODE_UNINIT) + { + g_slave_adr = spi_register_ss_line(&CC2420_SS_PORT, CC2420_SS_PIN); + spi_init(SPI_MODE_MASTER, SPI_FORMAT_0, SPI_CLK_RATE_2); + } + + NOTICE(E_CC2420, "Registered slave line: %d", g_slave_adr); + + /* Configure all IO ports in input */ + DDR(CC2420_FIFO_PORT) &= ~(_BV(CC2420_FIFO_PIN)); + DDR(CC2420_FIFOP_PORT) &= ~(_BV(CC2420_FIFOP_PIN)); + DDR(CC2420_CCA_PORT) &= ~(_BV(CC2420_CCA_PIN)); + DDR(CC2420_SFD_PORT) &= ~(_BV(CC2420_SFD_PIN)); + + CC2420_SS_DDR = 0x01; + + /* Enable on-chip voltage regulator */ +#ifdef CC2420_VREG_ENABLE + NOTICE(E_CC2420, "Enable on-chip voltage regulator"); + DDR(CC2420_VREG_EN_PORT) |= _BV(CC2420_VREG_EN_PIN); + CC2420_VREG_EN_PORT |= _BV(CC2420_VREG_EN_PIN); + wait_ms(1); +#endif + + /* Reset the chip */ +#ifdef CC2420_RESET_ENABLE + NOTICE(E_CC2420, "Reset radio chip"); + DDR(CC2420_RESET_PORT) |= _BV(CC2420_RESET_PIN); + CC2420_RESET_PORT &= ~(_BV(CC2420_RESET_PIN)); + wait_ms(1); + CC2420_RESET_PORT |= _BV(CC2420_RESET_PIN); + wait_ms(1); +#endif + + + /* Start the oscillator */ + NOTICE(E_CC2420, "Start the oscillator"); + + /* Select the CC2420 SS line */ + SLAVE_SELECT(); + spi_send_byte(SXOSCON); + /* Release SS line */ + SLAVE_DESELECT(); + + /* Wait for stability */ + while(!CC2420_STATUS_CHECK(XOSC16M_STABLE)) + ; + + NOTICE(E_CC2420, "Init done"); +} diff --git a/modules/devices/radio/cc2420/cc2420.h b/modules/devices/radio/cc2420/cc2420.h new file mode 100644 index 0000000..6b2a1d5 --- /dev/null +++ b/modules/devices/radio/cc2420/cc2420.h @@ -0,0 +1,83 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#ifndef _CC2420_H_ +#define _CC2420_H_ + + +/* Convenient macro to ckeck status bits */ +#define CC2420_STATUS_CHECK(bit) ((cc2420_get_status() & _BV(bit)) >> (bit)) + + + +/* + * Initialize the CC2420 + */ +void cc2420_init(void); + +/* + * Get CC2420's status byte + */ +uint8_t cc2420_get_status(void); + +/* + * Write to a strobe register + * Returns Status byte + */ +inline uint8_t cc2420_strobe_register(uint8_t reg); + +/* Read and Write from/to a register */ +inline uint16_t cc2420_read_register(uint8_t reg); +inline void cc2420_write_register(uint8_t reg, uint16_t value); + +/* + * Write the contents of a buffer to TXFIFO + * Returns last read status byte + */ +uint8_t cc2420_write_txfifo(uint8_t *buffer, uint8_t length); + +/* + * Write the contents of a buffer to RXFIFO + * Returns last read status byte + */ +uint8_t cc2420_write_rxfifo(uint8_t *buffer, uint8_t length); + +/* + * Read the contents of RXFIFO into a buffer + */ +void cc2420_read_rxfifo(uint8_t *buffer, uint8_t length); + +/* + * Write to a RAM address one or several byte(s) + * /!\ This is NOT foolproof, you have to be sure of the + * address you write to, and the length of your buffer + */ +void cc2420_write_ram(uint16_t addr, uint8_t *buffer, uint16_t length); + +/* + * Read from RAM. Same warning. + */ +void cc2420_read_ram(uint16_t addr, uint8_t *buffer, uint16_t length); + + +#endif /* _CC2420_H_ */ diff --git a/modules/devices/radio/cc2420/cc2420_arch.h b/modules/devices/radio/cc2420/cc2420_arch.h new file mode 100644 index 0000000..bc5d84d --- /dev/null +++ b/modules/devices/radio/cc2420/cc2420_arch.h @@ -0,0 +1,435 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +/* + * This file defines the memory map of the CC2420 + * as well as all registers and bit names. + * Please refer to the DataSheet of your chip + * for more information. + */ + + +#ifndef _CC2420_ARCH_H_ +#define _CC2420_ARCH_H_ + + +/* + * Read/write and RAM/register bits + */ +#define WRITE_BIT (0<<6) +#define READ_BIT (1<<6) + +#define REG_BIT (0<<7) +#define RAM_BIT (1<<7) + +#define RAM_READ_WRITE (0<<5) +#define RAM_READ (1<<5) + +#define REG_MASK 0x3F +#define RAM_MASK 0x7F +#define BANK_MASK 0xC0 + + +/* + * RAM memory map + */ +#define RAM_NOT_USED 0x16C /* Not used */ +#define RAM_SHORTADR 0x16A /* 16-bits Short address */ +#define RAM_PANID 0x168 /* 16-bits PAN identifier */ +#define RAM_IEEEADR 0x160 /* 64-bits IEEE address */ +#define RAM_CBCSTATE 0x150 /* Temporary storage for CBC-MAC calculation*/ +#define RAM_TXNONCE 0x140 /* TX nonce (in-line auth) */ +#define RAM_TXCTR RAM_TXNONCE /* TX counter (in-line encrypt) */ +#define RAM_KEY1 0x130 /* Encryption key 1 */ +#define RAM_SABUF 0x120 /* Stand-alone encryption buffer */ +#define RAM_RXNONCE 0x110 /* RX nonce (in-line auth) */ +#define RAM_RXCTR RAM_RXNONCE /* RX counter (in-line encrypt) */ +#define RAM_KEY0 0x100 /* Encryption key 0 */ +#define RAM_RXFIFO 0x080 /* 128 bytes RX FIFO */ +#define RAM_TXFIFO 0x000 /* 128 bytes TX FIFO */ + +/* + * Configuration Registers + */ +/* STROBE registers */ +#define SNOP 0x00 /* No operation */ +#define SXOSCON 0x01 /* Turn ON the crystal oscillator */ +#define STXCAL 0x02 /* Enable & calibrate frequency synth for TX */ +#define SRXON 0x03 /* Enable RX */ +#define STXON 0x04 /* Enable TX after calibration */ +#define STXONCCA 0x05 /* if CCA clear, then enable calibration and TX */ +#define SRFOFF 0x06 /* Disable RX/TX and freq synth */ +#define SXOSCOFF 0x07 /* Turn OFF oscillator and RF */ +#define SFLUSHRX 0x08 /* Flush RX fifo */ +#define SFLUSHTX 0x09 /* Flush TX fifo */ +#define SACK 0x0A /* Send ACK frame */ +#define SACKPEND 0x0B /* Send ACK frame with pending bit */ +#define SRXDEC 0x0C /* Start RXFIFO decryption */ +#define STXENC 0x0D /* Start TXFIFO encryption */ +#define SAES 0x0E /* AES Stand alone encryption */ +/* 0x0F not used */ + +/* Read / Write registers */ +#define MAIN 0x10 /* Main control */ +#define MDMCTRL0 0x11 /* Modem control 0 */ +#define MDMCTRL1 0x12 /* Modem control 1 */ +#define RSSI 0x13 /* RSSI and CCA status and control */ +#define SYNCWORD 0x14 /* Synchronization word control */ +#define TXCTRL 0x15 /* Transmit control */ +#define RXCTRL0 0x16 /* Receive control 0 */ +#define RXCTRL1 0x17 /* Receive control 1 */ +#define FSCTRL 0x18 /* Frequency control and status */ +#define SECCTRL0 0x19 /* Security control 0 */ +#define SECCTRL1 0x1A /* Security control 1 */ +#define BATTMON 0x1B /* Battery monitor control and status */ +#define IOCFG0 0x1C /* IO control 0 */ +#define IOCFG1 0x1D /* IO control 1 */ +#define MANFIDL 0x1E /* Manufacturer ID low 16 bits */ +#define MANFIDH 0x1F /* Manufacturer ID high 16 bits */ +#define FSMTC 0x20 /* Finite State Machine Time Constants */ +#define MANAND 0x21 /* Manual AND override */ +#define MANOR 0x22 /* Manual OR override */ +#define AGCCTRL 0x23 /* Automatic Gain Control */ +#define AGCTST0 0x24 /* AGC test 0 */ +#define AGCTST1 0x25 /* AGC test 1 */ +#define AGCTST2 0x26 /* AGC test 2 */ +#define FSTST0 0x27 /* Frequency Synthetizer test 0 */ +#define FSTST1 0x28 /* FS test 1 */ +#define FSTST2 0x29 /* FS test 2 */ +#define FSTST3 0x2A /* FS test 3 */ +#define RXBPFTST 0x2B /* Receiver Bandpass Filter test */ +#define FSMSTATE 0x2C /* FSM status */ +#define ADCTST 0x2D /* ADC test */ +#define DACTST 0x2E /* DAC test */ +#define TOPTST 0x2F /* Top Level test */ + +#define RESERVED 0x30 +/* 0x31 - 0x3D not used */ + +#define TXFIFO 0x3E /* TX FIFO byte */ +#define RXFIFO 0x3F /* RX FIFO byte */ + + +/* + * Status byte bit names + */ +#define RESERVED_1 7 +#define XOSC16M_STABLE 6 +#define TX_UNDERFLOW 5 +#define ENC_BUSY 4 +#define TX_ACTIVE 3 +#define LOCK 2 +#define RSSI_VALID 1 +#define RESERVED_2 0 + +/* + * MAIN register bits + */ +#define RESETn 15 +#define ENC_RESETn 14 +#define DEMOD_RESETn 13 +#define MOD_RESETn 12 +#define FS_RESETn 11 +/* 10 - 1 reserved */ +#define XOSC16M_BYPASS 0 + +/* + * MDMCTRL0 + */ +/* 15 - 14 reserved */ +#define RESERVED_FRAME_MODE 13 +#define PAN_COORDINATOR 12 +#define ADR_DECODE 11 +#define CCA_HYST2 10 +#define CCA_HYST1 9 +#define CCA_HYST0 8 +#define CCA_MODE1 7 +#define CCA_MODE0 6 +#define AUTOCRC 5 +#define AUTOACK 4 +#define PREAMBLE_LENGTH3 3 +#define PREAMBLE_LENGTH2 2 +#define PREAMBLE_LENGTH1 1 +#define PREAMBLE_LENGTH0 0 + +/* + * MDMCTRL1 + */ +/* 15 - 11 reserved */ +#define CORR_THR4 10 +#define CORR_THR3 9 +#define CORR_THR2 8 +#define CORR_THR1 7 +#define CORR_THR0 6 +#define DEMOD_AVG_MODE 5 +#define MODULATION_MODE 4 +#define TX_MODE1 3 +#define TX_MODE0 2 +#define RX_MODE1 1 +#define RX_MODE0 0 + +/* + * RSSI + */ +#define CCA_THR 15 +#define RSSI_VAL 7 + +/* + * TXCTRL + */ +#define TXMIXBUF_CUR1 15 +#define TXMIXBUF_CUR0 14 +#define TX_TURNAROUND 13 +#define TXMIX_CAP_ARRAY1 12 +#define TXMIX_CAP_ARRAY0 11 +#define TXMIX_CURRENT1 10 +#define TXMIX_CURRENT0 9 +#define PA_CURRENT 8 +#define PA_LEVEL 4 + +/* + * RXCTRL0 + */ +#define RXMIXBUF_CUR 13 +#define HIGH_LNA_GAIN 11 +#define MED_LNA_GAIN 9 +#define LOW_LNA_GAIN 7 +#define HIGH_LNA_CURRENT 5 +#define MED_LNA_CURRENT 3 +#define LOW_LNA_CURRENT 1 + +/* + * RXCTRL1 + */ +#define RXBPF_LOCUR 13 +#define RXBPF_MIDCUR 12 +#define LOW_LOWGAIN 11 +#define MED_LOWGAIN 10 +#define HIGH_HGM 9 +#define MED_HGM 8 +#define LNA_CAP_ARRAY 7 +#define RXMIX_TAIL 5 +#define RXMIX_VCM 3 +#define RXMIX_CURRENT 1 + +/* + * FSCTRL + */ +#define LOCK_THR 15 +#define CAL_DONE 13 +#define CAL_RUNNING 12 +#define LOCK_LENGTH 11 +#define LOCK_STATUS 10 +#define FREQ 9 + +/* + * SECCTRL0 + */ +#define RXFIFO_PROTECTION 9 +#define SEC_CBC_HEAD 8 +#define SEC_SAKEYSEL 7 +#define SEC_TXKEYSEL 6 +#define SEC_RXKEYSEL 5 +#define SEC_M 4 +#define SEC_MODE 1 + +/* + * SECCTRL1 + */ +#define SEC_TXL 14 +#define SEC_RXL 6 + +/* + * BATTMON + */ +#define BATT_OK 6 +#define BATTMON_EN 5 +#define BATTMON_VOLTAGE 4 + +/* + * IOCFG0 + */ +#define BCN_ACCEPT 11 +#define FIFO_POLARITY 10 +#define FIFOP_POLARITY 9 +#define SFD_POLARITY 8 +#define CCA_POLARITY 7 +#define FIFOP_THR 6 + +/* + * IOCFG1 + */ +#define HSSD_SRC 12 +#define SFDMUX 9 +#define CCAMUX 4 + +/* + * MANFIDL + */ +#define PARTNUM_L 15 +#define MANFID 11 + +/* + * MANFIDH + */ +#define VERSION 15 +#define PARTNUM_H 11 + +/* + * FSMTC + */ +#define TC_RXCHAIN2RX 15 +#define TC_SWITCH2TX 12 +#define TC_PAON2TX 9 +#define TC_TXEND2SWITCH 5 +#define TC_TXEND2PAOFF 2 + +/* + * MANAND and MANOR + */ +#define VGA_RESET_N 15 +#define BIAS_PD 14 +#define BALUN_CTRL 13 +#define RXTX 12 +#define PRE_PD 11 +#define PA_N_PD 10 +#define PA_P_PD 9 +#define DAC_LPF_PD 8 +#define XOSC16M_PD 7 +#define RXBPF_CAL_PD 6 +#define CHP_PD 5 +#define FS_PD 4 +#define ADC_PD 3 +#define VGA_PD 2 +#define RXBPF_PD 1 +#define LNAMIX_PD 0 + +/* + * AGCCTRL + */ +#define VGA_GAIN_OE 11 +#define VGA_GAIN 10 +#define LNAMIX_GAINMODE_O 3 +#define LNAMIX_GAINMODE 1 + +/* + * AGCTST0 + */ +#define LNAMIX_HYST 15 +#define LNAMIX_THR_H 11 +#define LNAMIX_THR_L 5 + +/* + * AGCTST1 + */ +#define AGC_BLANK_MOD 14 +#define PEAKDET_CUR_BOOST 13 +#define AGC_SETTLE_WAIT 12 +#define AGC_PEAK_DET_MODE 10 +#define AGC_WIN_SIZE 7 +#define AGC_REF 5 + +/* + * AGCTST2 + */ +#define MED2HIGHGAIN 9 +#define LOW2MEDGAIN 4 + +/* + * FSTST0 + */ +#define VCO_ARRAY_SETTLE_LONG 11 +#define VCO_ARRAY_OE 10 +#define VCO_ARRAY_O 9 +#define VCO_ARRAY_RES 4 + +/* + * FSTST1 + */ +#define VCO_TX_NOCAL 15 +#define VCO_ARRAY_CAL_LONG 14 +#define VCO_CURRENT_REF 13 +#define VCO_CURRENT_K 9 +#define VC_DAC_EN 3 +#define VC_DAC_VAL 2 + +/* + * FSTST2 + */ +#define VCO_CURCAL_SPEED 14 +#define VCO_CURRENT_OE 12 +#define VCO_CURRENT_O 11 +#define VCO_CURRENT_RES 5 + +/* + * FSTST3 + */ +#define CHP_CAL_DISABLE 15 +#define CHP_CURRENT_OE 14 +#define CHP_TEST_UP 13 +#define CHP_TEST_DN 12 +#define CHP_DISABLE 11 +#define PD_DELAY 10 +#define CHP_STEP_PERIOD 9 +#define STOP_CHP_CURRENT 7 +#define START_CHP_CURRENT 3 + +/* + * RXBPFTST + */ +#define RXBPF_CAP_OE 14 +#define RXBPF_CAP_O 13 +#define RXBPF_CAP_RES 6 + +/* + * FSMSTATE + */ +#define FSM_CUR_STATE 5 + +/* + * ADCTST + */ +#define ADC_CLOCK_DISABLE 15 +#define ADC_I 14 +#define ADC_Q 6 + +/* + * DACTST + */ +#define DAC_SRC 14 +#define DAC_I_O 11 +#define DAC_Q_O 5 + +/* + * TOPTST + */ +#define RAM_BIST_RUN 7 +#define TEST_BATTMON_EN 6 +#define VC_IN_TEST_EN 5 +#define ATESTMOD_PD 4 +#define ATESTMOD_MODE 3 + + + +#endif /* _CC2420_ARCH_H_ */ + diff --git a/modules/devices/radio/cc2420/config/CVS/Entries b/modules/devices/radio/cc2420/config/CVS/Entries new file mode 100644 index 0000000..abd6452 --- /dev/null +++ b/modules/devices/radio/cc2420/config/CVS/Entries @@ -0,0 +1,2 @@ +/cc2420_config.h/1.1.2.1/Fri Jan 30 20:17:41 2009//Tb_zer0 +D diff --git a/modules/devices/radio/cc2420/config/CVS/Repository b/modules/devices/radio/cc2420/config/CVS/Repository new file mode 100644 index 0000000..621e730 --- /dev/null +++ b/modules/devices/radio/cc2420/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/radio/cc2420/config diff --git a/modules/devices/radio/cc2420/config/CVS/Root b/modules/devices/radio/cc2420/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/radio/cc2420/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/radio/cc2420/config/CVS/Tag b/modules/devices/radio/cc2420/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/radio/cc2420/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/radio/cc2420/config/CVS/Template b/modules/devices/radio/cc2420/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/radio/cc2420/config/cc2420_config.h b/modules/devices/radio/cc2420/config/cc2420_config.h new file mode 100644 index 0000000..eccf5d9 --- /dev/null +++ b/modules/devices/radio/cc2420/config/cc2420_config.h @@ -0,0 +1,93 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#ifndef _CC2420_CONFIG_H +#define _CC2420_CONFIG_H + +/* + * Configure HERE your hardware connections to the device + * Here is the list of connections between the CC2420 and the AVR: + * - VREG_EN Enable the onchip voltage regulator + * - RESET Drive the CC2420 reset line + * - FIFO RX FIFO status line + * - FIFOP RX FIFO status line + * - CCA Clear Channel Assessment + * - SFD Timing information + * + * In addition the chip communicates through a 4-wire SPI connection + * Thus you have to enable the SPI module in Aversive. The CC2420 is a slave + * on the SPI bus. + * + * For more information please see the CC2420 DataSheet. + */ + + +/* + * VREG_EN - Enable the CC2420 voltage regulator + */ + +/* Comment if you don't drive VREG_EN from the microcontroller */ +#define CC2420_VREG_ENABLE +#define CC2420_VREG_EN_PORT PORTA +#define CC2420_VREG_EN_PIN 5 + +/* + * RESET - Drive the CC2420 reset line + */ + +/* Comment if you don't drive RESET from the microcontroller */ +#define CC2420_RESET_ENABLE +#define CC2420_RESET_PORT PORTA +#define CC2420_RESET_PIN 6 + +/* + * FIFO status lines + */ +#define CC2420_FIFO_PORT PORTC +#define CC2420_FIFO_PIN 1 + +#define CC2420_FIFOP_PORT PORTE +#define CC2420_FIFOP_PIN 7 + +/* + * CCA status line + */ +#define CC2420_CCA_PORT PORTD +#define CC2420_CCA_PIN 4 + +/* + * SFD status line + */ +#define CC2420_SFD_PORT PORTD +#define CC2420_SFD_PIN 6 + +/* + * SPI Slave Select (SS pin) configuration + */ +#define CC2420_SS_DDR DDRC +#define CC2420_SS_PORT PORTC +#define CC2420_SS_PIN 0 + + + +#endif /* _CC2420_CONFIG_H */ diff --git a/modules/devices/robot/CVS/Entries b/modules/devices/robot/CVS/Entries new file mode 100644 index 0000000..27b59ae --- /dev/null +++ b/modules/devices/robot/CVS/Entries @@ -0,0 +1,5 @@ +D/blocking_detection_manager//// +D/obstacle_avoidance//// +D/position_manager//// +D/robot_system//// +D/trajectory_manager//// diff --git a/modules/devices/robot/CVS/Repository b/modules/devices/robot/CVS/Repository new file mode 100644 index 0000000..2c87726 --- /dev/null +++ b/modules/devices/robot/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot diff --git a/modules/devices/robot/CVS/Root b/modules/devices/robot/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/CVS/Tag b/modules/devices/robot/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/CVS/Template b/modules/devices/robot/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/blocking_detection_manager/CVS/Entries b/modules/devices/robot/blocking_detection_manager/CVS/Entries new file mode 100644 index 0000000..369bfd9 --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Mon Dec 31 16:25:00 2007//Tb_zer0 +/blocking_detection_manager.c/1.1.2.7/Mon May 18 12:29:10 2009//Tb_zer0 +/blocking_detection_manager.h/1.1.2.6/Fri May 9 08:25:10 2008//Tb_zer0 +D diff --git a/modules/devices/robot/blocking_detection_manager/CVS/Repository b/modules/devices/robot/blocking_detection_manager/CVS/Repository new file mode 100644 index 0000000..5e740d7 --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/blocking_detection_manager diff --git a/modules/devices/robot/blocking_detection_manager/CVS/Root b/modules/devices/robot/blocking_detection_manager/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/blocking_detection_manager/CVS/Tag b/modules/devices/robot/blocking_detection_manager/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/blocking_detection_manager/CVS/Template b/modules/devices/robot/blocking_detection_manager/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/blocking_detection_manager/Makefile b/modules/devices/robot/blocking_detection_manager/Makefile new file mode 100644 index 0000000..4236c4d --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/Makefile @@ -0,0 +1,8 @@ +TARGET = blocking_detection_manager + +# List C source files here. (C dependencies are automatically generated.) +SRC = blocking_detection_manager.c + +########################################## + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/robot/blocking_detection_manager/blocking_detection_manager.c b/modules/devices/robot/blocking_detection_manager/blocking_detection_manager.c new file mode 100644 index 0000000..cdb2b58 --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/blocking_detection_manager.c @@ -0,0 +1,130 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: blocking_detection_manager.c,v 1.1.2.7 2009-05-18 12:29:10 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +/* blocking detection manager */ + +#include <stdio.h> +#include <string.h> +#include <aversive/error.h> + +#include <blocking_detection_manager.h> + +/** init module, give the robot system to use as a parameter */ +void bd_init(struct blocking_detection * bd) +{ + uint8_t flags; + IRQ_LOCK(flags); + memset(bd, 0, sizeof(*bd)); + IRQ_UNLOCK(flags); +} + +/* thresholds */ +void bd_set_current_thresholds(struct blocking_detection * bd, + int32_t k1, int32_t k2, + uint32_t i_thres, uint16_t cpt_thres) +{ + uint8_t flags; + IRQ_LOCK(flags); + bd->k1 = k1; + bd->k2 = k2; + bd->i_thres = i_thres; + bd->cpt_thres = cpt_thres; + bd->cpt = 0; + IRQ_UNLOCK(flags); +} + +/* speed threshold */ +void bd_set_speed_threshold(struct blocking_detection * bd, + uint16_t speed) +{ + uint8_t flags; + IRQ_LOCK(flags); + bd->speed_thres = speed; + IRQ_UNLOCK(flags); +} + +/** reset current blocking */ +void bd_reset(struct blocking_detection * bd) +{ + uint8_t flags; + IRQ_LOCK(flags); + bd->cpt = 0; + IRQ_UNLOCK(flags); +} + + + +/** function to be called periodically */ +void bd_manage_from_speed_cmd(struct blocking_detection * bd, + int32_t speed, int32_t cmd) +{ + int32_t i=0; + + /* if current-based blocking_detection enabled */ + if ( bd->cpt_thres ) { + i = bd->k1 * cmd - bd->k2 * speed; + if ((uint32_t)ABS(i) > bd->i_thres && + (bd->speed_thres == 0 || ABS(speed) < bd->speed_thres)) { + if (bd->cpt == bd->cpt_thres - 1) + WARNING(E_BLOCKING_DETECTION_MANAGER, + "BLOCKING cmd=%ld, speed=%ld i=%ld", + cmd, speed, i); + if (bd->cpt < bd->cpt_thres) + bd->cpt++; + } + else { + bd->cpt=0; + } +#if BD_DEBUG + if (bd->debug_cpt++ == BD_DEBUG) { + DEBUG(E_BLOCKING_DETECTION_MANAGER, "cmd=%ld, speed=%ld i=%ld", + cmd, speed, i); + bd->debug_cpt = 0; + } + } +#endif +} + +/** function to be called periodically */ +void bd_manage_from_pos_cmd(struct blocking_detection * bd, + int32_t pos, int32_t cmd) +{ + int32_t speed = (pos - bd->prev_pos); + bd_manage_from_speed_cmd(bd, speed, cmd); + bd->prev_pos = pos; +} + +/** function to be called periodically */ +void bd_manage_from_cs(struct blocking_detection * bd, struct cs *cs) +{ + bd_manage_from_pos_cmd(bd, cs_get_filtered_feedback(cs), cs_get_out(cs)); +} + +/** get value of blocking detection */ +uint8_t bd_get(struct blocking_detection * bd) +{ + uint8_t ret, flags; + IRQ_LOCK(flags); + ret = (bd->cpt_thres && (bd->cpt == bd->cpt_thres)); + IRQ_UNLOCK(flags); + return ret; +} diff --git a/modules/devices/robot/blocking_detection_manager/blocking_detection_manager.h b/modules/devices/robot/blocking_detection_manager/blocking_detection_manager.h new file mode 100644 index 0000000..27b7897 --- /dev/null +++ b/modules/devices/robot/blocking_detection_manager/blocking_detection_manager.h @@ -0,0 +1,92 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: blocking_detection_manager.h,v 1.1.2.6 2008-05-09 08:25:10 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +/* blocking detection manager */ + +#ifndef BLOCKING_DETECTION_MANAGER_H_ +#define BLOCKING_DETECTION_MANAGER_H_ + +/* display debug every 128 calls of manage if defined */ +#define BD_DEBUG 128 + +#include <control_system_manager.h> + +/* detect blocking based on motor current. + * triggers the blocking if: + * - the current in the motor is a above a threshold + * during n tests + * - the speed is below the threshold (if specified) + * + * We suppose that i = k1.V - k2.w + * (V is the voltage applied on the motor, and w the current speed + * of the motor) + */ + +struct blocking_detection { + struct cs *cs; + + uint32_t i_thres; + int32_t k1; + int32_t k2; + uint16_t cpt_thres; + uint16_t cpt; + uint16_t speed_thres; +#ifdef BD_DEBUG + uint16_t debug_cpt; +#endif + + int32_t prev_pos; + int32_t speed; +}; + +/** init module, give the cs as parameter */ +void bd_init(struct blocking_detection * bd); + +/** thresholds for current-based blocking detection. If cpt_thres + * is 0, disable it. */ +void bd_set_current_thresholds(struct blocking_detection * bd, + int32_t k1, int32_t k2, + uint32_t i_thres, uint16_t cpt_thres); + +/** speed threshold: if speed is above it, disable + * blocking_detection. */ +void bd_set_speed_threshold(struct blocking_detection * bd, + uint16_t speed); + +/** reset the blocking */ +void bd_reset(struct blocking_detection * bd); + +/** function to be called periodicallyn, when we use cs structure */ +void bd_manage_from_cs(struct blocking_detection * bd, struct cs *cs); + +/** function to be called periodically, when we use values directly */ +void bd_manage_from_pos_cmd(struct blocking_detection * bd, + int32_t pos, int32_t cmd); + +/** function to be called periodically, when we use values directly */ +void bd_manage_from_speed_cmd(struct blocking_detection * bd, + int32_t speed, int32_t cmd); + +/** get value of blocking detection */ +uint8_t bd_get(struct blocking_detection * bd); + +#endif diff --git a/modules/devices/robot/obstacle_avoidance/CVS/Entries b/modules/devices/robot/obstacle_avoidance/CVS/Entries new file mode 100644 index 0000000..29ef8cb --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.1.2.1/Mon Dec 31 16:25:00 2007//Tb_zer0 +/obstacle_avoidance.c/1.1.2.8/Sat May 2 10:00:35 2009//Tb_zer0 +/obstacle_avoidance.h/1.1.2.7/Sat May 2 10:00:35 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/robot/obstacle_avoidance/CVS/Repository b/modules/devices/robot/obstacle_avoidance/CVS/Repository new file mode 100644 index 0000000..c7916c9 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/obstacle_avoidance diff --git a/modules/devices/robot/obstacle_avoidance/CVS/Root b/modules/devices/robot/obstacle_avoidance/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/obstacle_avoidance/CVS/Tag b/modules/devices/robot/obstacle_avoidance/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/obstacle_avoidance/CVS/Template b/modules/devices/robot/obstacle_avoidance/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/obstacle_avoidance/Makefile b/modules/devices/robot/obstacle_avoidance/Makefile new file mode 100644 index 0000000..bf0e931 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/Makefile @@ -0,0 +1,8 @@ +TARGET = obstacle_avoidance + +# List C source files here. (C dependencies are automatically generated.) +SRC = obstacle_avoidance.c + +########################################## + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/robot/obstacle_avoidance/config/CVS/Entries b/modules/devices/robot/obstacle_avoidance/config/CVS/Entries new file mode 100644 index 0000000..c6ef0d5 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/config/CVS/Entries @@ -0,0 +1,2 @@ +/obstacle_avoidance_config.h/1.1.2.1/Sat May 2 10:00:35 2009//Tb_zer0 +D diff --git a/modules/devices/robot/obstacle_avoidance/config/CVS/Repository b/modules/devices/robot/obstacle_avoidance/config/CVS/Repository new file mode 100644 index 0000000..4e8af63 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/obstacle_avoidance/config diff --git a/modules/devices/robot/obstacle_avoidance/config/CVS/Root b/modules/devices/robot/obstacle_avoidance/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/obstacle_avoidance/config/CVS/Tag b/modules/devices/robot/obstacle_avoidance/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/obstacle_avoidance/config/CVS/Template b/modules/devices/robot/obstacle_avoidance/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/obstacle_avoidance/config/obstacle_avoidance_config.h b/modules/devices/robot/obstacle_avoidance/config/obstacle_avoidance_config.h new file mode 100644 index 0000000..dbf2cab --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/config/obstacle_avoidance_config.h @@ -0,0 +1,26 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: obstacle_avoidance_config.h,v 1.1.2.1 2009-05-02 10:00:35 zer0 Exp $ + * + */ + +#define MAX_POLY 3 +#define MAX_PTS 10 +#define MAX_RAYS 100 +#define MAX_CHKPOINTS 5 +#define OA_COEF 30000 diff --git a/modules/devices/robot/obstacle_avoidance/obstacle_avoidance.c b/modules/devices/robot/obstacle_avoidance/obstacle_avoidance.c new file mode 100755 index 0000000..ee8a655 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/obstacle_avoidance.c @@ -0,0 +1,331 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: obstacle_avoidance.c,v 1.1.2.8 2009-05-02 10:00:35 zer0 Exp $ + * + * Main code and algorithm: Fabrice DESCLAUX <serpilliere@droids-corp.org> + * Integration in Aversive: Olivier MATZ <zer0@droids-corp.org> + */ + +#include <aversive.h> +#include <aversive/error.h> + +#include <math.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> + +#include <obstacle_avoidance.h> + +#define GET_PT(a) (&(a) - &(oa.points[0])) + +static struct obstacle_avoidance oa; + +static void __oa_start_end_points(int32_t st_x, int32_t st_y, + int32_t en_x, int32_t en_y); + +/* reset oa without reseting points coord */ +void oa_reset(void) +{ + DEBUG(E_OA, "%s()", __FUNCTION__); + + memset(oa.valid, 0, sizeof(oa.valid)); + memset(oa.pweight, 0, sizeof(oa.pweight)); + memset(oa.weight, 0, sizeof(oa.weight)); + memset(oa.p, 0, sizeof(oa.p)); + memset(oa.pt, 0, sizeof(oa.pt)); + + +} + +/** Init the oa structure. Note: In the algorithm, the first polygon + * is a dummy one, and is used to represent the START and END points + * (so it has 2 vertices) */ +void oa_init(void) +{ + DEBUG(E_OA, "%s()", __FUNCTION__); + memset(&oa, 0, sizeof(oa)); + + /* set a default start and point, reserve the first poly and + * the first 2 points for it */ + oa.polys[0].pts = oa.points; + oa.polys[0].l = 2; + __oa_start_end_points(0, 0, 100, 100); + oa.cur_pt_idx = 2; + oa.cur_poly_idx = 1; +} + +/** + * Set the start and destination point. Return 0 on sucess + */ +static void __oa_start_end_points(int32_t st_x, int32_t st_y, + int32_t en_x, int32_t en_y) +{ + /* we always use the first 2 points of the table for start and end */ + oa.points[0].x = en_x; + oa.points[0].y = en_y; + + /* Each point processed by Dijkstra is marked as valid. If we + * have unreachable points (out of playground or points inside + * polygons) Disjkstra won't mark them as valid. At the end of + * the algorithm, if the destination point is not marked as + * valid, there's no valid path to reach it. */ + + oa.valid[GET_PT(oa.points[0])] = 0; + /* the real dest is the start point for the algorithm */ + oa.pweight[GET_PT(oa.points[0])] = 1; + + oa.points[1].x = st_x; + oa.points[1].y = st_y; + oa.valid[GET_PT(oa.points[1])] = 0; + oa.pweight[GET_PT(oa.points[1])] = 0; +} + +/** + * Set the start and destination point. Return 0 on sucess + */ +void oa_start_end_points(int32_t st_x, int32_t st_y, + int32_t en_x, int32_t en_y) +{ + DEBUG(E_OA, "%s() (%ld,%ld) (%ld,%ld)", __FUNCTION__, + st_x, st_y, en_x, en_y); + + __oa_start_end_points(st_x, st_y, en_x, en_y); +} + + +/** + * Create a new obstacle polygon. Return NULL on error. + */ +poly_t *oa_new_poly(uint8_t size) +{ + DEBUG(E_OA, "%s(size=%d)", __FUNCTION__, size); + + if (oa.cur_pt_idx + size > MAX_PTS) + return NULL; + if (oa.cur_poly_idx + 1 > MAX_POLY) + return NULL; + + oa.polys[oa.cur_poly_idx].l = size; + oa.polys[oa.cur_poly_idx].pts = &oa.points[oa.cur_pt_idx]; + oa.cur_pt_idx += size; + + return &oa.polys[oa.cur_poly_idx++]; +} + +/** + * Add a point to the polygon. + */ +void oa_poly_set_point(poly_t *pol, + int32_t x, int32_t y, uint8_t i) +{ + DEBUG(E_OA, "%s() (%ld,%ld)", __FUNCTION__, x, y); + + pol->pts[i].x = x; + pol->pts[i].y = y; + oa.valid[GET_PT(pol->pts[i])] = 0; + oa.pweight[GET_PT(pol->pts[i])] = 0; +} + +point_t * oa_get_path(void) +{ + return oa.u.res; +} + +void oa_dump(void) +{ + uint8_t i,j; + poly_t *poly; + point_t *pt; + + printf_P(PSTR("-- OA dump --\r\n")); + printf_P(PSTR("nb_polys: %d\r\n"), oa.cur_poly_idx); + printf_P(PSTR("nb_pts: %d\r\n"), oa.cur_pt_idx); + for (i=0; i<oa.cur_poly_idx; i++) { + poly = &oa.polys[i]; + printf_P(PSTR("poly #%d\r\n"), i); + for (j=0; j<poly->l; j++) { + pt = &poly->pts[j]; + printf_P(PSTR(" pt #%d (%"PRIi32",%"PRIi32")\r\n"), j, pt->x, pt->y); + } + } +} + +/* Iterative Dijkstra algorithm: The valid filed is used to determine if: + * 1: this point has been visited, his weight is correct. + * 2: the point must be visited. + * + * The algorithm does: find a point that must be visited (2) update + * his weight, mark it as (1) and update all his neightbours has 2. + * + * The algorithm ends when no (2) points are found + * + * A point with weight 0 is a point that has not been visited (so + * weight is not affected yet); This explain why first point must have + * a start weight different than 0. + * + * When the algo finds a shorter path to reach a point B from point A, + * it will store in (p, pt) the parent point. This is important to + * remenber and extract the solution path. */ +void +dijkstra(uint8_t start_p, uint8_t start) +{ + uint8_t i; + int8_t add; + int8_t finish = 0; + /* weight == 0 means not visited */ + /* weight == 1 for start */ + + /* find all point linked to start */ + + oa.valid[GET_PT(oa.polys[start_p].pts[start])] = 2; + + while (!finish){ + finish = 1; + + for (start_p = 0;start_p<MAX_POLY;start_p++) { + for (start = 0;start<oa.polys[start_p].l;start++) { + if (oa.valid[GET_PT(oa.polys[start_p].pts[start])] != 2) + continue; + add = -2; + + /* For all points that must be + * visited, we look for rays that + * start or stop at this point. As + * ray array is (poly_num, point_num) + * we wtep 2 by 2. */ + for (i=0 ; i<oa.ray_n ; i+=2) { + + /* If index is even in the + * aray, we have a start point + * ray, so connected point is + * i+2; + * + * If index is odd, we are in stop + * point and ray start point is at + * i-2 pos */ + add = -add; + + if (start_p != oa.u.rays[i] || start != oa.u.rays[i+1]) + continue; + + if ((oa.pweight[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])] != 0) && + (oa.pweight[GET_PT(oa.polys[start_p].pts[start])]+oa.weight[i/4] >= + oa.pweight[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])])) + continue; + + oa.p[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])] = start_p; + oa.pt[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])] = start; + oa.valid[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])]=2; + oa.pweight[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])] = + oa.pweight[GET_PT(oa.polys[start_p].pts[start])]+oa.weight[i/4]; + + oa.valid[GET_PT(oa.polys[start_p].pts[start])] = 1; + finish = 0; + DEBUG(E_OA, "%s() (%ld,%ld p=%ld) %ld (%ld,%ld p=%ld)\r\n", __FUNCTION__, + oa.polys[start_p].pts[start].x, oa.polys[start_p].pts[start].y, + oa.pweight[GET_PT(oa.polys[start_p].pts[start])],oa.weight[i/4], + + oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]].x, + oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]].y, + oa.pweight[GET_PT(oa.polys[oa.u.rays[i+add]].pts[oa.u.rays[i+add+1]])] + ); + } + } + } + } +} + + +/* display the path */ +int8_t +get_path(poly_t *polys, uint8_t *rays) +{ + uint8_t p, pt, p1, pt1, i; + + p=0; + pt=1; + i=0; + + /* forget the first point */ + + while (!(p==0 && pt==0)) { + + if (i>=MAX_CHKPOINTS) + return -1; + + if (oa.valid[GET_PT(polys[p].pts[pt])]==0) { + DEBUG(E_OA, "invalid path!"); + return -1; + } + + p1 = oa.p[GET_PT(polys[p].pts[pt])]; + pt1 = oa.pt[GET_PT(polys[p].pts[pt])]; + p = p1; pt = pt1; + oa.u.res[i].x = polys[p].pts[pt].x; + oa.u.res[i].y = polys[p].pts[pt].y; + DEBUG(E_OA, "result[%d]: %d, %d", i, oa.u.res[i].x, oa.u.res[i].y); + i++; + } + + return i; +} + +int8_t +oa_process(void) +{ + uint8_t ret; + uint8_t i; + + /* First we compute the visibility graph */ + ret = calc_rays(oa.polys, oa.cur_poly_idx, oa.u.rays); + DEBUG(E_OA, "nb_rays = %d", ret); + + DEBUG(E_OA, "Ray list"); + for (i=0;i<ret;i+=4) { + DEBUG(E_OA, "%d,%d -> %d,%d", oa.u.rays[i], oa.u.rays[i+1], + oa.u.rays[i+2], oa.u.rays[i+3]); + } + + /* Then we affect the rays lengths to their weights */ + calc_rays_weight(oa.polys, oa.cur_poly_idx, + oa.u.rays, ret, oa.weight); + + DEBUG(E_OA, "Ray weights"); + for (i=0;i<ret;i+=4) { + DEBUG(E_OA, "%d,%d -> %d,%d (%d)", + (int)oa.polys[oa.u.rays[i]].pts[oa.u.rays[i+1]].x, + (int)oa.polys[oa.u.rays[i]].pts[oa.u.rays[i+1]].y, + (int)oa.polys[oa.u.rays[i+2]].pts[oa.u.rays[i+3]].x, + (int)oa.polys[oa.u.rays[i+2]].pts[oa.u.rays[i+3]].y, + oa.weight[i/4]); + } + + /* We aplly dijkstra on the visibility graph from the start + * point (point 0 of the polygon 0) */ + oa.ray_n = ret; + DEBUG(E_OA, "dijkstra ray_n = %d", ret); + dijkstra(0, 0); + + /* As dijkstra sets the parent points in the resulting graph, + * we can backtrack the solution path. */ + return get_path(oa.polys, oa.u.rays); +} diff --git a/modules/devices/robot/obstacle_avoidance/obstacle_avoidance.h b/modules/devices/robot/obstacle_avoidance/obstacle_avoidance.h new file mode 100644 index 0000000..f9bcf3b --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/obstacle_avoidance.h @@ -0,0 +1,138 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: obstacle_avoidance.h,v 1.1.2.7 2009-05-02 10:00:35 zer0 Exp $ + * + * Main code and algorithm: Fabrice DESCLAUX <serpilliere@droids-corp.org> + * Integration in Aversive: Olivier MATZ <zer0@droids-corp.org> + */ + +/* + * The algorithm is based on the "visible point" algorithm. + * There are 3 inputs: + * - the play ground (basically the table, here a rectangle) + * - the objects to avoid, represented by polygones + * - start/stop points (A, B) + * + * The algorithm will first find every ray formed by 2 points that can + * "see" each others. Basically, if a polygon is between two points, + * they cannot see each others. A side of a polygon is composed by 2 + * points that can se each others. + * + * From all these rays, we can create a graph. We affect for each ray + * a weight with its own length. + * + * The algorithm executes Dijkstra to find the shortest path to go + * from A to B. + */ + +/* + * As we run on 4Ko ram uC, we have static structures arrays to store: + * - MAX_POLY => represent the maximum polygons to avoid in the area. + * - MAX_PTS => maximize the sum of every polygons vertices. + * - MAX_RAYS => maximum number of rays. + * - MAX_CHKPOINTS => maximum accepted checkpoints in the resulting path. + * - PLAYGROUND XXX => dimensions of the playground. + */ + +#ifndef _OBSTACLE_AVOIDANCE_H_ +#define _OBSTACLE_AVOIDANCE_H_ + +#include <obstacle_avoidance_config.h> + +struct obstacle_avoidance { + poly_t polys[MAX_POLY]; /* tab of polygons (obstacles) */ + point_t points[MAX_PTS]; /* tab of points, referenced by polys */ + uint8_t valid[MAX_PTS]; + int32_t pweight[MAX_PTS]; + uint8_t p[MAX_PTS]; + uint8_t pt[MAX_PTS]; + + + + uint8_t ray_n; + uint8_t cur_poly_idx; + uint8_t cur_pt_idx; + + uint16_t weight[MAX_RAYS]; + union { + uint8_t rays[MAX_RAYS*2]; + point_t res[MAX_CHKPOINTS]; + } u; +}; + +/* To save memory space here is the moemory representation of + * polygons/points: + * + * We have an array of points (oa_ext_point_t points): + * _____ _____ _____ _____ _____ _____ _____ _____ _____ + * | | | | | | | | | | + * | p0 | p1 | p0 | p1 | p2 | p3 | p0 | p1 | p2 | + * |_____|_____|_____|_____|_____|_____|_____|_____|_____| + * + * + * ^ ^ ^ + * | | | + * -polygon 0 -polygon 1 -polygon 2 + * -2 vertices -4 vertices -3 vertices + * + * + * And each polygon is represented by the sub array starting with the + * point represented by oa_ext_point_t * pts and composed of uint8_t l; + * (in the oa_poly_t structure) + */ + +/* reset oa without cleaning points */ +void oa_reset(void); + + +/** Init the oa structure */ +void oa_init(void); + +/** + * Set the start and destination point. + */ +void oa_start_end_points(int32_t st_x, int32_t st_y, int32_t en_x, int32_t en_y); + +/** + * Create a new obstacle polygon. Return NULL on error. + */ +poly_t *oa_new_poly(uint8_t size); + + +/** + * Dump status + */ +void oa_dump(void); + +/** + * set a point of the polygon. + */ +void oa_poly_set_point(poly_t *pol, int32_t x, int32_t y, uint8_t i); + + +/** + * process the path from start to end. Return 0 on sucess. + */ +int8_t oa_process(void); + +/** + * get the result after a call to oa_process() + */ +point_t * oa_get_path(void); + +#endif /* _OBSTACLE_AVOIDANCE_H_ */ diff --git a/modules/devices/robot/obstacle_avoidance/test/.config b/modules/devices/robot/obstacle_avoidance/test/.config new file mode 100644 index 0000000..55e5303 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/.config @@ -0,0 +1,277 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +CONFIG_OPTM_0=y +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +# CONFIG_OPTM_S is not set +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_GEOMETRY=y +CONFIG_MODULE_GEOMETRY_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_9BITS is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +CONFIG_MODULE_OBSTACLE_AVOIDANCE=y +CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG=y + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/robot/obstacle_avoidance/test/CVS/Entries b/modules/devices/robot/obstacle_avoidance/test/CVS/Entries new file mode 100644 index 0000000..57e8562 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.1.2.2/Sat May 2 10:00:35 2009//Tb_zer0 +/Makefile/1.1.2.1/Mon Dec 31 16:25:01 2007//Tb_zer0 +/error_config.h/1.1.2.1/Mon Dec 31 16:25:01 2007//Tb_zer0 +/main.c/1.1.2.2/Sat May 2 10:00:35 2009//Tb_zer0 +/obstacle_avoidance_config.h/1.1.2.1/Sat May 2 10:00:35 2009//Tb_zer0 +D diff --git a/modules/devices/robot/obstacle_avoidance/test/CVS/Repository b/modules/devices/robot/obstacle_avoidance/test/CVS/Repository new file mode 100644 index 0000000..4cfc2a4 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/obstacle_avoidance/test diff --git a/modules/devices/robot/obstacle_avoidance/test/CVS/Root b/modules/devices/robot/obstacle_avoidance/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/obstacle_avoidance/test/CVS/Tag b/modules/devices/robot/obstacle_avoidance/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/obstacle_avoidance/test/CVS/Template b/modules/devices/robot/obstacle_avoidance/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/obstacle_avoidance/test/Makefile b/modules/devices/robot/obstacle_avoidance/test/Makefile new file mode 100755 index 0000000..d2c03d8 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/robot/obstacle_avoidance/test/error_config.h b/modules/devices/robot/obstacle_avoidance/test/error_config.h new file mode 100644 index 0000000..ce76f78 --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-12-31 16:25:01 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/robot/obstacle_avoidance/test/main.c b/modules/devices/robot/obstacle_avoidance/test/main.c new file mode 100644 index 0000000..86a199f --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/main.c @@ -0,0 +1,80 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.2 2009-05-02 10:00:35 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <stdarg.h> +#include <string.h> +#include <math.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> + +#include <obstacle_avoidance.h> + +#define PTX 150 +#define PTY 105 +#define SIZE 45 + +/* log function, add a command to configure + * it dynamically */ +void mylog(struct error * e, ...) +{ + va_list ap; + + va_start(ap, e); + printf_P(PSTR("[%d]: E%d "), e->severity, e->err_num); + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR("\r\n")); + va_end(ap); +} + + +int main(int argc, char** argv) +{ + poly_t *pol; + + /* LOGS */ + error_register_emerg(mylog); + error_register_error(mylog); + error_register_warning(mylog); + error_register_notice(mylog); + error_register_debug(mylog); + + oa_init(); + + oa_start_end_points(30, 30, 194, 149); + + pol = oa_new_poly(4); + + oa_poly_set_point(pol, PTX-SIZE, PTY-SIZE, 0); + oa_poly_set_point(pol, PTX+SIZE, PTY-SIZE, 1); + oa_poly_set_point(pol, PTX+SIZE, PTY+SIZE, 2); + oa_poly_set_point(pol, PTX-SIZE, PTY+SIZE, 3); + oa_process(); + + return 0; +} + + diff --git a/modules/devices/robot/obstacle_avoidance/test/obstacle_avoidance_config.h b/modules/devices/robot/obstacle_avoidance/test/obstacle_avoidance_config.h new file mode 100644 index 0000000..2f4da9e --- /dev/null +++ b/modules/devices/robot/obstacle_avoidance/test/obstacle_avoidance_config.h @@ -0,0 +1,27 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: obstacle_avoidance_config.h,v 1.1.2.1 2009-05-02 10:00:35 zer0 Exp $ + * + */ + +#define MAX_POLY 3 +#define MAX_PTS 12 +#define MAX_RAYS 150 +#define MAX_CHKPOINTS 5 + +#define OA_COEF 50000 diff --git a/modules/devices/robot/position_manager/CVS/Entries b/modules/devices/robot/position_manager/CVS/Entries new file mode 100644 index 0000000..a840829 --- /dev/null +++ b/modules/devices/robot/position_manager/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/position_manager.c/1.6.4.7/Mon May 18 12:27:26 2009//Tb_zer0 +/position_manager.h/1.5.4.4/Mon May 18 12:27:26 2009//Tb_zer0 +D diff --git a/modules/devices/robot/position_manager/CVS/Repository b/modules/devices/robot/position_manager/CVS/Repository new file mode 100644 index 0000000..cd2461a --- /dev/null +++ b/modules/devices/robot/position_manager/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/position_manager diff --git a/modules/devices/robot/position_manager/CVS/Root b/modules/devices/robot/position_manager/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/position_manager/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/position_manager/CVS/Tag b/modules/devices/robot/position_manager/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/position_manager/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/position_manager/CVS/Template b/modules/devices/robot/position_manager/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/position_manager/Makefile b/modules/devices/robot/position_manager/Makefile new file mode 100644 index 0000000..763c6ce --- /dev/null +++ b/modules/devices/robot/position_manager/Makefile @@ -0,0 +1,8 @@ +TARGET = position_manager + +# List C source files here. (C dependencies are automatically generated.) +SRC = position_manager.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/robot/position_manager/position_manager.c b/modules/devices/robot/position_manager/position_manager.c new file mode 100644 index 0000000..60ed260 --- /dev/null +++ b/modules/devices/robot/position_manager/position_manager.c @@ -0,0 +1,280 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: position_manager.c,v 1.6.4.7 2009-05-18 12:27:26 zer0 Exp $ + * + */ + +#include <string.h> +#include <math.h> + +#include <robot_system.h> +#include <position_manager.h> + +/** initialization of the robot_position pos, everthing is set to 0 */ +void position_init(struct robot_position *pos) +{ + uint8_t flags; + IRQ_LOCK(flags); + memset(pos, 0, sizeof(struct robot_position)); + IRQ_UNLOCK(flags); +} + +/** Set a new robot position */ +void position_set(struct robot_position *pos, int16_t x, int16_t y, int16_t a) +{ + uint8_t flags; + IRQ_LOCK(flags); + pos->pos_d.a = ((double)a * M_PI)/ 180.0; + pos->pos_d.x = x; + pos->pos_d.y = y; + pos->pos_s16.x = x; + pos->pos_s16.y = y; + pos->pos_s16.a = a; + IRQ_UNLOCK(flags); +} + +#ifdef CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE +void position_set_centrifugal_coef(struct robot_position *pos, double coef) +{ + pos->centrifugal_coef = coef; +} +#endif + +/** + * Save in pos structure the pointer to the associated robot_system. + * The robot_system structure is used to get values from virtual encoders + * that return angle and distance. + */ +void position_set_related_robot_system(struct robot_position *pos, struct robot_system *rs) +{ + uint8_t flags; + IRQ_LOCK(flags); + pos->rs = rs; + IRQ_UNLOCK(flags); +} + +/** + * Set the physical parameters of the robot : + * - number of impulsions for 1 mm (distance) + * - number of impulsions for 1 degree (angle) + */ +void position_set_physical_params(struct robot_position *pos, double track_mm, + double distance_imp_per_mm) +{ + uint8_t flags; + IRQ_LOCK(flags); + pos->phys.track_mm = track_mm; + pos->phys.distance_imp_per_mm = distance_imp_per_mm; + IRQ_UNLOCK(flags); +} + +void position_use_ext(struct robot_position *pos) +{ + struct rs_polar encoders; + uint8_t flags; + + IRQ_LOCK(flags); + encoders.distance = rs_get_ext_distance(pos->rs); + encoders.angle = rs_get_ext_angle(pos->rs); + pos->prev_encoders = encoders; + pos->use_ext = 1; + IRQ_UNLOCK(flags); +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +void position_use_mot(struct robot_position *pos) +{ + struct rs_polar encoders; + uint8_t flags; + + IRQ_LOCK(flags); + encoders.distance = rs_get_mot_distance(pos->rs); + encoders.angle = rs_get_mot_angle(pos->rs); + pos->prev_encoders = encoders; + pos->use_ext = 0; + IRQ_UNLOCK(flags); +} +#endif + +/** + * Process the absolute position (x,y,a) depending on the delta on + * virtual encoders since last read, and depending on physical + * parameters. The processed position is in mm. + */ +void position_manage(struct robot_position *pos) +{ + double x, y, a, r, arc_angle; + double dx, dy; + s16 x_s16, y_s16, a_s16; + struct rs_polar encoders; + struct rs_polar delta; + struct robot_system * rs; + uint8_t flags; + + IRQ_LOCK(flags); + rs = pos->rs; + IRQ_UNLOCK(flags); + /* here we could raise an error */ + if (rs == NULL) + return; + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + if (pos->use_ext) { + encoders.distance = rs_get_ext_distance(rs); + encoders.angle = rs_get_ext_angle(rs); + } + else { + encoders.distance = rs_get_mot_distance(rs); + encoders.angle = rs_get_mot_angle(rs); + } +#else + encoders.distance = rs_get_ext_distance(rs); + encoders.angle = rs_get_ext_angle(rs); +#endif + + /* process difference between 2 measures. + * No lock for prev_encoders since we are the only one to use + * this var XXX that's wrong now, perhaps we should lock */ + delta.distance = encoders.distance - pos->prev_encoders.distance; + delta.angle = encoders.angle - pos->prev_encoders.angle; + + pos->prev_encoders = encoders; + + /* update double position */ + IRQ_LOCK(flags); + a = pos->pos_d.a; + x = pos->pos_d.x; + y = pos->pos_d.y; + IRQ_UNLOCK(flags); + + if (delta.angle == 0) { + /* we go straight */ + dx = cos(a) * ((double) delta.distance / (pos->phys.distance_imp_per_mm)) ; + dy = sin(a) * ((double) delta.distance / (pos->phys.distance_imp_per_mm)) ; + x += dx; + y += dy; + } + else { + /* r the radius of the circle arc */ + r = (double)delta.distance * pos->phys.track_mm / ((double) delta.angle * 2); + arc_angle = 2 * (double) delta.angle / (pos->phys.track_mm * pos->phys.distance_imp_per_mm); + + dx = r * (-sin(a) + sin(a+arc_angle)); + dy = r * (cos(a) - cos(a+arc_angle)); + + x += dx; + y += dy; + a += arc_angle; + + if (a < -M_PI) + a += (M_PI*2); + else if (a > (M_PI)) + a -= (M_PI*2); + +#ifdef CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE + /* This part compensate the centrifugal force when we + * turn very quickly. Idea is from Gargamel (RCVA). */ + if (pos->centrifugal_coef && r != 0) { + double k; + + /* + * centrifugal force is F = (m.v^2 / R) + * with v: angular speed + * R: radius of the circle + */ + + k = ((double) delta.distance); + k = k * k; + k /= r; + k *= pos->centrifugal_coef; + + /* + * F acts perpendicularly to the vector + */ + x += k * sin(a); + y -= k * cos(a); + } +#endif + } + + /* update int position */ + x_s16 = (int16_t)x; + y_s16 = (int16_t)y; + a_s16 = (int16_t)(a * (360.0/(M_PI*2))); + + IRQ_LOCK(flags); + pos->pos_d.a = a; + pos->pos_d.x = x; + pos->pos_d.y = y; + pos->pos_s16.x = x_s16; + pos->pos_s16.y = y_s16; + pos->pos_s16.a = a_s16; + IRQ_UNLOCK(flags); +} + + +/** + * returns current x + */ +int16_t position_get_x_s16(struct robot_position *pos) +{ + return pos->pos_s16.x; +} + +/** + * returns current y + */ +int16_t position_get_y_s16(struct robot_position *pos) +{ + return pos->pos_s16.y; +} + +/** + * returns current alpha + */ +int16_t position_get_a_deg_s16(struct robot_position *pos) +{ + return pos->pos_s16.a; +} + +/********* double */ + +/** + * returns current x + */ +double position_get_x_double(struct robot_position *pos) +{ + return pos->pos_d.x; +} + +/** + * returns current y + */ +double position_get_y_double(struct robot_position *pos) +{ + return pos->pos_d.y; +} + +/** + * returns current alpha + */ +double position_get_a_rad_double(struct robot_position *pos) +{ + return pos->pos_d.a; +} + diff --git a/modules/devices/robot/position_manager/position_manager.h b/modules/devices/robot/position_manager/position_manager.h new file mode 100644 index 0000000..24c2447 --- /dev/null +++ b/modules/devices/robot/position_manager/position_manager.h @@ -0,0 +1,149 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: position_manager.h,v 1.5.4.4 2009-05-18 12:27:26 zer0 Exp $ + * + */ + + +#ifndef _ROBOT_POSITION_MANAGER_H_ +#define _ROBOT_POSITION_MANAGER_H_ + +#include <math.h> +#include <robot_system.h> + +/** + * structure that stores the number of impulsions that corresponds to + * a mm or a degre. We also need to specify the track of the + */ +struct robot_physical_params +{ + double track_mm; + double distance_imp_per_mm; +}; + + +/** + * stores a cartesian position on the area in double + * WARNING : a is stored in radian + */ +struct xya_position +{ + double x; + double y; + double a; +}; + +/** + * stores a cartesian position on the area in integers + * WARNING : a is stored in degree + */ +struct xya_position_s16 +{ + int16_t x; + int16_t y; + int16_t a; +}; + +/** + * Structure that stores everthing we need to get and stores the + * position of the robot + */ +struct robot_position +{ + uint8_t use_ext; + struct robot_physical_params phys; + struct xya_position pos_d; + struct xya_position_s16 pos_s16; + struct rs_polar prev_encoders; + struct robot_system *rs; +#ifdef CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE + double centrifugal_coef; +#endif +}; + + +/** initialization of the robot_position pos, everthing is set to 0 */ +void position_init(struct robot_position *pos); + +#ifdef CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE +/** set arbitrary coef to compensate the centrifugal force */ +void position_set_centrifugal_coef(struct robot_position *pos, double coef); +#endif + +/** Set a new robot position */ +void position_set(struct robot_position *pos, int16_t x, int16_t y, int16_t a); + +void position_use_ext(struct robot_position *pos); +void position_use_mot(struct robot_position *pos); + + +/** + * Set the physical parameters of the robot : + * - distance between wheels (track, in mm) + * - number of impulsions for 1 mm (distance) + */ +void position_set_physical_params(struct robot_position *pos, double track_mm, + double distance_imp_per_mm); + +/** + * Save in pos structure the pointer to the associated robot_system. + * The robot_system structure is used to get values from virtual encoders + * that return angle and distance. + */ +void position_set_related_robot_system(struct robot_position *pos, struct robot_system *rs); + +/** + * Process the absolute position (x,y,a) depending on the delta on + * virtual encoders since last read, and depending on physical + * parameters. + */ +void position_manage(struct robot_position *pos); + + +/** + * returns current x + */ +int16_t position_get_x_s16(struct robot_position *pos); + +/** + * returns current y + */ +int16_t position_get_y_s16(struct robot_position *pos); + +/** + * returns current alpha + */ +int16_t position_get_a_deg_s16(struct robot_position *pos); + +/** + * returns current x + */ +double position_get_x_double(struct robot_position *pos); + +/** + * returns current y + */ +double position_get_y_double(struct robot_position *pos); + +/** + * returns current alpha + */ +double position_get_a_rad_double(struct robot_position *pos); + + +#endif diff --git a/modules/devices/robot/robot_system/CVS/Entries b/modules/devices/robot/robot_system/CVS/Entries new file mode 100644 index 0000000..a6abb7f --- /dev/null +++ b/modules/devices/robot/robot_system/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/angle_distance.c/1.4.4.4/Thu Mar 5 22:02:55 2009//Tb_zer0 +/angle_distance.h/1.3.4.3/Sun Jun 17 21:23:41 2007//Tb_zer0 +/robot_system.c/1.6.4.7/Sun Mar 29 18:48:23 2009//Tb_zer0 +/robot_system.h/1.5.4.3/Sun Apr 6 17:33:57 2008//Tb_zer0 +D/test//// diff --git a/modules/devices/robot/robot_system/CVS/Repository b/modules/devices/robot/robot_system/CVS/Repository new file mode 100644 index 0000000..bf6cf92 --- /dev/null +++ b/modules/devices/robot/robot_system/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/robot_system diff --git a/modules/devices/robot/robot_system/CVS/Root b/modules/devices/robot/robot_system/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/robot_system/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/robot_system/CVS/Tag b/modules/devices/robot/robot_system/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/robot_system/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/robot_system/CVS/Template b/modules/devices/robot/robot_system/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/robot_system/Makefile b/modules/devices/robot/robot_system/Makefile new file mode 100755 index 0000000..6e3296e --- /dev/null +++ b/modules/devices/robot/robot_system/Makefile @@ -0,0 +1,6 @@ +TARGET = robot_system + +# List C source files here. (C dependencies are automatically generated.) +SRC = angle_distance.c robot_system.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/robot/robot_system/angle_distance.c b/modules/devices/robot/robot_system/angle_distance.c new file mode 100644 index 0000000..09309fb --- /dev/null +++ b/modules/devices/robot/robot_system/angle_distance.c @@ -0,0 +1,42 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: angle_distance.c,v 1.4.4.4 2009-03-05 22:02:55 zer0 Exp $ + * + */ + +#include "angle_distance.h" + +/** + * convert the values of wheels encoders (left, right) into (distance, + * angle) + */ +void rs_get_polar_from_wheels(struct rs_polar *p_dst, struct rs_wheels *w_src) +{ + p_dst->distance = (w_src->right + w_src->left) / 2; + p_dst->angle = (w_src->right - w_src->left) / 2; +} + +/** + * convert (distance, angle) into (left, right) + */ +void rs_get_wheels_from_polar(struct rs_wheels *w_dst, struct rs_polar *p_src) +{ + w_dst->left = p_src->distance - p_src->angle; + w_dst->right = p_src->distance + p_src->angle; +} + diff --git a/modules/devices/robot/robot_system/angle_distance.h b/modules/devices/robot/robot_system/angle_distance.h new file mode 100644 index 0000000..08764d8 --- /dev/null +++ b/modules/devices/robot/robot_system/angle_distance.h @@ -0,0 +1,49 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: angle_distance.h,v 1.3.4.3 2007-06-17 21:23:41 zer0 Exp $ + * + */ + +#ifndef _ANGLE_DISTANCE_H_ +#define _ANGLE_DISTANCE_H_ + +#include <aversive.h> + +struct rs_wheels { + int32_t left; + int32_t right; +}; + + +struct rs_polar { + int32_t distance; + int32_t angle; +}; + +/** + * convert the values of wheels encoders (left, right) into (distance, + * angle) + */ +void rs_get_polar_from_wheels(struct rs_polar * p_dst, struct rs_wheels * w_src); + +/** + * convert (distance, angle) into (left, right) + */ +void rs_get_wheels_from_polar(struct rs_wheels * w_dst, struct rs_polar * p_src); + +#endif diff --git a/modules/devices/robot/robot_system/robot_system.c b/modules/devices/robot/robot_system/robot_system.c new file mode 100755 index 0000000..be158e6 --- /dev/null +++ b/modules/devices/robot/robot_system/robot_system.c @@ -0,0 +1,458 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: robot_system.c,v 1.6.4.7 2009-03-29 18:48:23 zer0 Exp $ + * + */ + +/** + * The goal of this module is to provide an interface to motor and + * encoders of the robot. This module provide a function that returns + * the value of virtual encoders containing distance and angle. It + * also allow the user to command virtual angle and distance PWMs. + */ + +#include <string.h> +#include <stdio.h> + +#include <aversive/error.h> + +#include <aversive.h> +#include <f64.h> + +#include "angle_distance.h" +#include "robot_system.h" + + +/** Call a pwm() pointer : + * - lock the interrupts + * - read the pointer to the pwm function + * - unlock the interrupts + * - if pointer is null, don't do anything + * - else call the pwm with the parameters + */ +static inline void +safe_setpwm(void (*f)(void *, int32_t), void * param, int32_t value) +{ + void (*f_tmp)(void *, int32_t); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + f_tmp(param_tmp, value); + } +} + +/** Call a encoder() pointer : + * - lock the interrupts + * - read the pointer to the encoder function + * - unlock the interrupts + * - if pointer is null, return 0 + * - else return the value processed by the function + */ +static inline uint32_t +safe_getencoder(int32_t (*f)(void *), void * param) +{ + int32_t (*f_tmp)(void *); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + return f_tmp(param_tmp); + } + return 0; +} + +/** Set the structure to 0 */ +void rs_init( struct robot_system * rs) +{ + uint8_t flags; + + IRQ_LOCK(flags); + memset(rs, 0, sizeof(struct robot_system)); +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + rs_set_ratio(rs, 1.0); +#endif + IRQ_UNLOCK(flags); +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** define ratio between mot and ext track. (track_mot / track_ext) */ +void rs_set_ratio(struct robot_system * rs, double ratio) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->ratio_mot_ext = f64_from_double(ratio); + IRQ_UNLOCK(flags); +} +#endif + +/** define left PWM function and param */ +void rs_set_left_pwm(struct robot_system * rs, void (*left_pwm)(void *, int32_t), void *left_pwm_param) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->left_pwm = left_pwm; + rs->left_pwm_param = left_pwm_param; + IRQ_UNLOCK(flags); +} + +/** define right PWM function and param */ +void rs_set_right_pwm(struct robot_system * rs, void (*right_pwm)(void *, int32_t), void *right_pwm_param) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->right_pwm = right_pwm; + rs->right_pwm_param = right_pwm_param; + IRQ_UNLOCK(flags); +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** define left motor encoder function and param */ +void rs_set_left_mot_encoder(struct robot_system * rs, int32_t (*left_mot_encoder)(void *), + void *left_mot_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->left_mot_encoder = left_mot_encoder; + rs->left_mot_encoder_param = left_mot_encoder_param; + rs->left_mot_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} + +/** define right motor encoder function and param */ +void rs_set_right_mot_encoder(struct robot_system * rs, int32_t (*right_mot_encoder)(void *), + void *right_mot_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->right_mot_encoder = right_mot_encoder; + rs->right_mot_encoder_param = right_mot_encoder_param; + rs->right_mot_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} +#endif + +/** define left external encoder function and param */ +void rs_set_left_ext_encoder(struct robot_system * rs, int32_t (*left_ext_encoder)(void *), + void *left_ext_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->left_ext_encoder = left_ext_encoder; + rs->left_ext_encoder_param = left_ext_encoder_param; + rs->left_ext_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} + +/** define right external encoder function and param */ +void rs_set_right_ext_encoder(struct robot_system * rs, int32_t (*right_ext_encoder)(void *), + void *right_ext_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->right_ext_encoder = right_ext_encoder; + rs->right_ext_encoder_param = right_ext_encoder_param; + rs->right_ext_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} + +/**** Virtual encoders and PWM */ + +/** + * set the real pwms according to the specified angle (it also + * depends on the last distance command sent) + */ +void rs_set_angle(void * data, int32_t angle) +{ + struct rs_polar p; + struct rs_wheels w; + struct robot_system * rs = data; + uint8_t flags; + + IRQ_LOCK(flags); + p.distance = rs->virtual_pwm.distance ; + rs->virtual_pwm.angle = angle; + IRQ_UNLOCK(flags); + + p.angle = angle; + rs_get_wheels_from_polar(&w, &p); + + safe_setpwm(rs->left_pwm, rs->left_pwm_param, w.left); + safe_setpwm(rs->right_pwm, rs->right_pwm_param, w.right); +} + +/** + * set the real pwms according to the specified distance (it also + * depends on the last angle command sent) + */ +void rs_set_distance(void * data, int32_t distance) +{ + struct robot_system * rs = data; + struct rs_polar p; + struct rs_wheels w; + uint8_t flags; + + IRQ_LOCK(flags); + p.angle = rs->virtual_pwm.angle ; + rs->virtual_pwm.distance = distance; + IRQ_UNLOCK(flags); + + p.distance = distance; + rs_get_wheels_from_polar(&w, &p); + + safe_setpwm(rs->left_pwm, rs->left_pwm_param, w.left); + safe_setpwm(rs->right_pwm, rs->right_pwm_param, w.right); +} + +/** + * get the virtual angle according to real encoders value. + */ +int32_t rs_get_angle(void * data) +{ + struct robot_system * rs = data; + int32_t angle; + uint8_t flags; + + IRQ_LOCK(flags); + angle = rs->virtual_encoders.angle ; + IRQ_UNLOCK(flags); + return angle; +} + +/** + * get the virtual distance according to real encoders value. + */ +int32_t rs_get_distance(void * data) +{ + struct robot_system * rs = data; + int32_t distance; + uint8_t flags; + + IRQ_LOCK(flags); + distance = rs->virtual_encoders.distance ; + IRQ_UNLOCK(flags); + return distance; +} + +int32_t rs_get_ext_angle(void * data) +{ + struct robot_system * rs = data; + int32_t angle; + uint8_t flags; + + IRQ_LOCK(flags); + angle = rs->pext_prev.angle ; + IRQ_UNLOCK(flags); + return angle; +} + +int32_t rs_get_ext_distance(void * data) +{ + struct robot_system * rs = data; + int32_t distance; + uint8_t flags; + + IRQ_LOCK(flags); + distance = rs->pext_prev.distance ; + IRQ_UNLOCK(flags); + return distance; +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +int32_t rs_get_mot_angle(void * data) +{ + struct robot_system * rs = data; + int32_t angle; + uint8_t flags; + + IRQ_LOCK(flags); + angle = rs->pmot_prev.angle ; + IRQ_UNLOCK(flags); + return angle; +} + +int32_t rs_get_mot_distance(void * data) +{ + struct robot_system * rs = data; + int32_t distance; + uint8_t flags; + + IRQ_LOCK(flags); + distance = rs->pmot_prev.distance ; + IRQ_UNLOCK(flags); + return distance; +} +#endif + +int32_t rs_get_ext_left(void * data) +{ + struct robot_system * rs = data; + int32_t left; + uint8_t flags; + + IRQ_LOCK(flags); + left = rs->wext_prev.left ; + IRQ_UNLOCK(flags); + return left; +} + +int32_t rs_get_ext_right(void * data) +{ + struct robot_system * rs = data; + int32_t right; + uint8_t flags; + + IRQ_LOCK(flags); + right = rs->wext_prev.right ; + IRQ_UNLOCK(flags); + return right; +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +int32_t rs_get_mot_left(void * data) +{ + struct robot_system * rs = data; + int32_t left; + uint8_t flags; + + IRQ_LOCK(flags); + left = rs->wmot_prev.left ; + IRQ_UNLOCK(flags); + return left; +} + +int32_t rs_get_mot_right(void * data) +{ + struct robot_system * rs = data; + int32_t right; + uint8_t flags; + + IRQ_LOCK(flags); + right = rs->wmot_prev.right ; + IRQ_UNLOCK(flags); + return right; +} +#endif + +void rs_set_flags(struct robot_system * rs, uint8_t flags) +{ + uint8_t i_flags; + + IRQ_LOCK(i_flags); + rs->flags = flags; + IRQ_UNLOCK(i_flags); +} + +/** + * Read the encoders, and update internal virtual counters. Call this + * function is needed before reading the virtual encoders.The program + * will decide if it the external encoders or the motor encoders are + * taken in account (depending on flags, but not yet) + */ +void rs_update(void * data) +{ + struct robot_system * rs = data; + struct rs_wheels wext; + struct rs_polar pext; +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + struct rs_wheels wmot; + struct rs_polar pmot; +#endif + int32_t delta_angle, delta_distance; + uint8_t flags; + + /* read encoders */ + wext.left = safe_getencoder(rs->left_ext_encoder, rs->left_ext_encoder_param); + wext.right = safe_getencoder(rs->right_ext_encoder, rs->right_ext_encoder_param); + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + wmot.left = safe_getencoder(rs->left_mot_encoder, rs->left_mot_encoder_param); + wmot.right = safe_getencoder(rs->right_mot_encoder, rs->right_mot_encoder_param); +#endif + + /* apply gains to each wheel */ + if (! (rs->flags & RS_IGNORE_EXT_GAIN )) { + wext.left = f64_msb_mul(f64_from_lsb(wext.left), rs->left_ext_gain); + wext.right = f64_msb_mul(f64_from_lsb(wext.right), rs->right_ext_gain); + } + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + if (! (rs->flags & RS_IGNORE_MOT_GAIN )) { + wmot.left = f64_msb_mul(f64_from_lsb(wmot.left), rs->left_mot_gain); + wmot.right = f64_msb_mul(f64_from_lsb(wmot.right), rs->right_mot_gain); + } +#endif + + rs_get_polar_from_wheels(&pext, &wext); +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + rs_get_polar_from_wheels(&pmot, &wmot); + + /* apply ratio to polar and reupdate wheels for ext coders */ + pext.angle = f64_msb_mul(f64_from_lsb(pext.angle), rs->ratio_mot_ext); + rs_get_wheels_from_polar(&wext, &pext); +#endif + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + /* update from external encoders */ + if (rs->flags & RS_USE_EXT) { + delta_angle = pext.angle - rs->pext_prev.angle; + delta_distance = pext.distance - rs->pext_prev.distance; + } + + /* update from motor encoders */ + else { + delta_angle = pmot.angle - rs->pmot_prev.angle; + delta_distance = pmot.distance - rs->pmot_prev.distance; + } +#else + delta_angle = pext.angle - rs->pext_prev.angle; + delta_distance = pext.distance - rs->pext_prev.distance; +#endif + + IRQ_LOCK(flags); + rs->virtual_encoders.angle += delta_angle; + rs->virtual_encoders.distance += delta_distance; + IRQ_UNLOCK(flags); + + /* don't lock too much time */ + + IRQ_LOCK(flags); + rs->pext_prev = pext; + rs->wext_prev = wext; + IRQ_UNLOCK(flags); + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + IRQ_LOCK(flags); + rs->pmot_prev = pmot; + rs->wmot_prev = wmot; + IRQ_UNLOCK(flags); +#endif +} diff --git a/modules/devices/robot/robot_system/robot_system.c.~1.6.4.7.~ b/modules/devices/robot/robot_system/robot_system.c.~1.6.4.7.~ new file mode 100755 index 0000000..be158e6 --- /dev/null +++ b/modules/devices/robot/robot_system/robot_system.c.~1.6.4.7.~ @@ -0,0 +1,458 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: robot_system.c,v 1.6.4.7 2009-03-29 18:48:23 zer0 Exp $ + * + */ + +/** + * The goal of this module is to provide an interface to motor and + * encoders of the robot. This module provide a function that returns + * the value of virtual encoders containing distance and angle. It + * also allow the user to command virtual angle and distance PWMs. + */ + +#include <string.h> +#include <stdio.h> + +#include <aversive/error.h> + +#include <aversive.h> +#include <f64.h> + +#include "angle_distance.h" +#include "robot_system.h" + + +/** Call a pwm() pointer : + * - lock the interrupts + * - read the pointer to the pwm function + * - unlock the interrupts + * - if pointer is null, don't do anything + * - else call the pwm with the parameters + */ +static inline void +safe_setpwm(void (*f)(void *, int32_t), void * param, int32_t value) +{ + void (*f_tmp)(void *, int32_t); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + f_tmp(param_tmp, value); + } +} + +/** Call a encoder() pointer : + * - lock the interrupts + * - read the pointer to the encoder function + * - unlock the interrupts + * - if pointer is null, return 0 + * - else return the value processed by the function + */ +static inline uint32_t +safe_getencoder(int32_t (*f)(void *), void * param) +{ + int32_t (*f_tmp)(void *); + void * param_tmp; + uint8_t flags; + IRQ_LOCK(flags); + f_tmp = f; + param_tmp = param; + IRQ_UNLOCK(flags); + if (f_tmp) { + return f_tmp(param_tmp); + } + return 0; +} + +/** Set the structure to 0 */ +void rs_init( struct robot_system * rs) +{ + uint8_t flags; + + IRQ_LOCK(flags); + memset(rs, 0, sizeof(struct robot_system)); +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + rs_set_ratio(rs, 1.0); +#endif + IRQ_UNLOCK(flags); +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** define ratio between mot and ext track. (track_mot / track_ext) */ +void rs_set_ratio(struct robot_system * rs, double ratio) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->ratio_mot_ext = f64_from_double(ratio); + IRQ_UNLOCK(flags); +} +#endif + +/** define left PWM function and param */ +void rs_set_left_pwm(struct robot_system * rs, void (*left_pwm)(void *, int32_t), void *left_pwm_param) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->left_pwm = left_pwm; + rs->left_pwm_param = left_pwm_param; + IRQ_UNLOCK(flags); +} + +/** define right PWM function and param */ +void rs_set_right_pwm(struct robot_system * rs, void (*right_pwm)(void *, int32_t), void *right_pwm_param) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->right_pwm = right_pwm; + rs->right_pwm_param = right_pwm_param; + IRQ_UNLOCK(flags); +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** define left motor encoder function and param */ +void rs_set_left_mot_encoder(struct robot_system * rs, int32_t (*left_mot_encoder)(void *), + void *left_mot_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->left_mot_encoder = left_mot_encoder; + rs->left_mot_encoder_param = left_mot_encoder_param; + rs->left_mot_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} + +/** define right motor encoder function and param */ +void rs_set_right_mot_encoder(struct robot_system * rs, int32_t (*right_mot_encoder)(void *), + void *right_mot_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->right_mot_encoder = right_mot_encoder; + rs->right_mot_encoder_param = right_mot_encoder_param; + rs->right_mot_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} +#endif + +/** define left external encoder function and param */ +void rs_set_left_ext_encoder(struct robot_system * rs, int32_t (*left_ext_encoder)(void *), + void *left_ext_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->left_ext_encoder = left_ext_encoder; + rs->left_ext_encoder_param = left_ext_encoder_param; + rs->left_ext_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} + +/** define right external encoder function and param */ +void rs_set_right_ext_encoder(struct robot_system * rs, int32_t (*right_ext_encoder)(void *), + void *right_ext_encoder_param, double gain) +{ + uint8_t flags; + + IRQ_LOCK(flags); + rs->right_ext_encoder = right_ext_encoder; + rs->right_ext_encoder_param = right_ext_encoder_param; + rs->right_ext_gain = f64_from_double(gain); + IRQ_UNLOCK(flags); +} + +/**** Virtual encoders and PWM */ + +/** + * set the real pwms according to the specified angle (it also + * depends on the last distance command sent) + */ +void rs_set_angle(void * data, int32_t angle) +{ + struct rs_polar p; + struct rs_wheels w; + struct robot_system * rs = data; + uint8_t flags; + + IRQ_LOCK(flags); + p.distance = rs->virtual_pwm.distance ; + rs->virtual_pwm.angle = angle; + IRQ_UNLOCK(flags); + + p.angle = angle; + rs_get_wheels_from_polar(&w, &p); + + safe_setpwm(rs->left_pwm, rs->left_pwm_param, w.left); + safe_setpwm(rs->right_pwm, rs->right_pwm_param, w.right); +} + +/** + * set the real pwms according to the specified distance (it also + * depends on the last angle command sent) + */ +void rs_set_distance(void * data, int32_t distance) +{ + struct robot_system * rs = data; + struct rs_polar p; + struct rs_wheels w; + uint8_t flags; + + IRQ_LOCK(flags); + p.angle = rs->virtual_pwm.angle ; + rs->virtual_pwm.distance = distance; + IRQ_UNLOCK(flags); + + p.distance = distance; + rs_get_wheels_from_polar(&w, &p); + + safe_setpwm(rs->left_pwm, rs->left_pwm_param, w.left); + safe_setpwm(rs->right_pwm, rs->right_pwm_param, w.right); +} + +/** + * get the virtual angle according to real encoders value. + */ +int32_t rs_get_angle(void * data) +{ + struct robot_system * rs = data; + int32_t angle; + uint8_t flags; + + IRQ_LOCK(flags); + angle = rs->virtual_encoders.angle ; + IRQ_UNLOCK(flags); + return angle; +} + +/** + * get the virtual distance according to real encoders value. + */ +int32_t rs_get_distance(void * data) +{ + struct robot_system * rs = data; + int32_t distance; + uint8_t flags; + + IRQ_LOCK(flags); + distance = rs->virtual_encoders.distance ; + IRQ_UNLOCK(flags); + return distance; +} + +int32_t rs_get_ext_angle(void * data) +{ + struct robot_system * rs = data; + int32_t angle; + uint8_t flags; + + IRQ_LOCK(flags); + angle = rs->pext_prev.angle ; + IRQ_UNLOCK(flags); + return angle; +} + +int32_t rs_get_ext_distance(void * data) +{ + struct robot_system * rs = data; + int32_t distance; + uint8_t flags; + + IRQ_LOCK(flags); + distance = rs->pext_prev.distance ; + IRQ_UNLOCK(flags); + return distance; +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +int32_t rs_get_mot_angle(void * data) +{ + struct robot_system * rs = data; + int32_t angle; + uint8_t flags; + + IRQ_LOCK(flags); + angle = rs->pmot_prev.angle ; + IRQ_UNLOCK(flags); + return angle; +} + +int32_t rs_get_mot_distance(void * data) +{ + struct robot_system * rs = data; + int32_t distance; + uint8_t flags; + + IRQ_LOCK(flags); + distance = rs->pmot_prev.distance ; + IRQ_UNLOCK(flags); + return distance; +} +#endif + +int32_t rs_get_ext_left(void * data) +{ + struct robot_system * rs = data; + int32_t left; + uint8_t flags; + + IRQ_LOCK(flags); + left = rs->wext_prev.left ; + IRQ_UNLOCK(flags); + return left; +} + +int32_t rs_get_ext_right(void * data) +{ + struct robot_system * rs = data; + int32_t right; + uint8_t flags; + + IRQ_LOCK(flags); + right = rs->wext_prev.right ; + IRQ_UNLOCK(flags); + return right; +} + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +int32_t rs_get_mot_left(void * data) +{ + struct robot_system * rs = data; + int32_t left; + uint8_t flags; + + IRQ_LOCK(flags); + left = rs->wmot_prev.left ; + IRQ_UNLOCK(flags); + return left; +} + +int32_t rs_get_mot_right(void * data) +{ + struct robot_system * rs = data; + int32_t right; + uint8_t flags; + + IRQ_LOCK(flags); + right = rs->wmot_prev.right ; + IRQ_UNLOCK(flags); + return right; +} +#endif + +void rs_set_flags(struct robot_system * rs, uint8_t flags) +{ + uint8_t i_flags; + + IRQ_LOCK(i_flags); + rs->flags = flags; + IRQ_UNLOCK(i_flags); +} + +/** + * Read the encoders, and update internal virtual counters. Call this + * function is needed before reading the virtual encoders.The program + * will decide if it the external encoders or the motor encoders are + * taken in account (depending on flags, but not yet) + */ +void rs_update(void * data) +{ + struct robot_system * rs = data; + struct rs_wheels wext; + struct rs_polar pext; +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + struct rs_wheels wmot; + struct rs_polar pmot; +#endif + int32_t delta_angle, delta_distance; + uint8_t flags; + + /* read encoders */ + wext.left = safe_getencoder(rs->left_ext_encoder, rs->left_ext_encoder_param); + wext.right = safe_getencoder(rs->right_ext_encoder, rs->right_ext_encoder_param); + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + wmot.left = safe_getencoder(rs->left_mot_encoder, rs->left_mot_encoder_param); + wmot.right = safe_getencoder(rs->right_mot_encoder, rs->right_mot_encoder_param); +#endif + + /* apply gains to each wheel */ + if (! (rs->flags & RS_IGNORE_EXT_GAIN )) { + wext.left = f64_msb_mul(f64_from_lsb(wext.left), rs->left_ext_gain); + wext.right = f64_msb_mul(f64_from_lsb(wext.right), rs->right_ext_gain); + } + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + if (! (rs->flags & RS_IGNORE_MOT_GAIN )) { + wmot.left = f64_msb_mul(f64_from_lsb(wmot.left), rs->left_mot_gain); + wmot.right = f64_msb_mul(f64_from_lsb(wmot.right), rs->right_mot_gain); + } +#endif + + rs_get_polar_from_wheels(&pext, &wext); +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + rs_get_polar_from_wheels(&pmot, &wmot); + + /* apply ratio to polar and reupdate wheels for ext coders */ + pext.angle = f64_msb_mul(f64_from_lsb(pext.angle), rs->ratio_mot_ext); + rs_get_wheels_from_polar(&wext, &pext); +#endif + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + /* update from external encoders */ + if (rs->flags & RS_USE_EXT) { + delta_angle = pext.angle - rs->pext_prev.angle; + delta_distance = pext.distance - rs->pext_prev.distance; + } + + /* update from motor encoders */ + else { + delta_angle = pmot.angle - rs->pmot_prev.angle; + delta_distance = pmot.distance - rs->pmot_prev.distance; + } +#else + delta_angle = pext.angle - rs->pext_prev.angle; + delta_distance = pext.distance - rs->pext_prev.distance; +#endif + + IRQ_LOCK(flags); + rs->virtual_encoders.angle += delta_angle; + rs->virtual_encoders.distance += delta_distance; + IRQ_UNLOCK(flags); + + /* don't lock too much time */ + + IRQ_LOCK(flags); + rs->pext_prev = pext; + rs->wext_prev = wext; + IRQ_UNLOCK(flags); + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + IRQ_LOCK(flags); + rs->pmot_prev = pmot; + rs->wmot_prev = wmot; + IRQ_UNLOCK(flags); +#endif +} diff --git a/modules/devices/robot/robot_system/robot_system.h b/modules/devices/robot/robot_system/robot_system.h new file mode 100755 index 0000000..8f72dc5 --- /dev/null +++ b/modules/devices/robot/robot_system/robot_system.h @@ -0,0 +1,185 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: robot_system.h,v 1.5.4.3 2008-04-06 17:33:57 zer0 Exp $ + * + */ + +/** + * The goal of this module is to provide an interface to motor and + * encoders of the robot. This module provide a function that returns + * the value of virtual encoders containing distance and angle. It + * also allow the user to command virtual angle and distance PWMs. + */ + +#include <aversive.h> +#include <f64.h> + +#include "angle_distance.h" + +#ifndef _ROBOT_SYSTEM_H_ +#define _ROBOT_SYSTEM_H_ + +/* flags */ +#define RS_USE_EXT 1 +#define RS_IGNORE_EXT_GAIN 2 +#define RS_IGNORE_MOT_GAIN 4 + + +struct robot_system +{ + uint8_t flags; + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT + struct rs_polar pmot_prev; + struct rs_wheels wmot_prev; + + f64 ratio_mot_ext; + + /* Motor encoders */ + int32_t (*left_mot_encoder)(void *); + void* left_mot_encoder_param; + f64 left_mot_gain; + + int32_t (*right_mot_encoder)(void *); + void* right_mot_encoder_param; + f64 right_mot_gain; +#endif + + struct rs_polar virtual_pwm; + struct rs_polar virtual_encoders; + + struct rs_polar pext_prev; + struct rs_wheels wext_prev; + + /* External encoders */ + int32_t (*left_ext_encoder)(void *); + void* left_ext_encoder_param; + f64 left_ext_gain; + + int32_t (*right_ext_encoder)(void *); + void* right_ext_encoder_param; + f64 right_ext_gain; + + /* PWM */ + void (*left_pwm)(void *, int32_t); + void *left_pwm_param; + void (*right_pwm)(void *, int32_t); + void *right_pwm_param; +}; + +/** Set the structure to 0 */ +void rs_init( struct robot_system * ); + +/**** ACCESSORS */ + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** define ratio between mot and ext track. (track_mot / track_ext) */ +void rs_set_ratio(struct robot_system * rs, double ratio); +#endif + +/** define left PWM function and param */ +void rs_set_left_pwm(struct robot_system * rs, void (*left_pwm)(void *, int32_t), void *left_pwm_param); + +/** define right PWM function and param */ +void rs_set_right_pwm(struct robot_system * rs, void (*right_pwm)(void *, int32_t), void *right_pwm_param); + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** define left motor encoder function and param */ +void rs_set_left_mot_encoder(struct robot_system * rs, int32_t (*left_mot_encoder)(void *), + void *left_mot_encoder_param, double gain); + +/** define right motor encoder function and param */ +void rs_set_right_mot_encoder(struct robot_system * rs, int32_t (*right_mot_encoder)(void *), + void *right_mot_encoder_param, double gain); +#endif + +/** define left external encoder function and param */ +void rs_set_left_ext_encoder(struct robot_system * rs, int32_t (*left_ext_encoder)(void *), + void *left_ext_encoder_param, double gain); + +/** define right external encoder function and param */ +void rs_set_right_ext_encoder(struct robot_system * rs, int32_t (*right_ext_encoder)(void *), + void *right_ext_encoder_param, double gain); + +/**** Virtual encoders and PWM */ + +/** + * set the real pwms according to the specified angle (it also + * depends on the last distance command sent) + */ +void rs_set_angle(void * rs, int32_t angle); + +/** + * set the real pwms according to the specified distance (it also + * depends on the last angle command sent) + */ +void rs_set_distance(void * rs, int32_t distance); + +/** + * get the virtual angle according to real encoders value. + */ +int32_t rs_get_angle(void * rs); + +/** + * get the virtual distance according to real encoders value. + */ +int32_t rs_get_distance(void * rs); + +/** + * get the angle according to ext encoders value. + */ +int32_t rs_get_ext_angle(void * rs); + +/** + * get the distance according to ext encoders value. + */ +int32_t rs_get_ext_distance(void * rs); + +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +/** + * get the angle according to mot encoders value. + */ +int32_t rs_get_mot_angle(void * rs); + +/** + * get the distance according to mot encoders value. + */ +int32_t rs_get_mot_distance(void * rs); +#endif + +/* same for left/right */ +int32_t rs_get_ext_left(void * rs); +int32_t rs_get_ext_right(void * rs); +#ifdef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT +int32_t rs_get_mot_left(void * rs); +int32_t rs_get_mot_right(void * rs); +#endif + + +/** + * Read the encoders, and update internal virtual counters. Call this + * function is needed before reading the virtual encoders. The program + * will decide if it the external encoders or the motor encoders are + * taken in account (depending on flags, but not yet) + */ +void rs_update(void * rs); + +void rs_set_flags(struct robot_system * rs, uint8_t flags); + + +#endif /* #ifndef _ROBOT_SYSTEM */ diff --git a/modules/devices/robot/robot_system/test/.config b/modules/devices/robot/robot_system/test/.config new file mode 100644 index 0000000..b1f2f89 --- /dev/null +++ b/modules/devices/robot/robot_system/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +CONFIG_MODULE_FIXED_POINT=y +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +CONFIG_MODULE_ROBOT_SYSTEM=y +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/robot/robot_system/test/CVS/Entries b/modules/devices/robot/robot_system/test/CVS/Entries new file mode 100644 index 0000000..8cd4ddd --- /dev/null +++ b/modules/devices/robot/robot_system/test/CVS/Entries @@ -0,0 +1,10 @@ +/.config/1.6.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/encoders_eirbot_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/error_config.h/1.3.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/main.c/1.3.6.2/Wed May 23 17:18:14 2007//Tb_zer0 +/pwm_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/scheduler_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/uart_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/wait_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +D diff --git a/modules/devices/robot/robot_system/test/CVS/Repository b/modules/devices/robot/robot_system/test/CVS/Repository new file mode 100644 index 0000000..19710ac --- /dev/null +++ b/modules/devices/robot/robot_system/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/robot_system/test diff --git a/modules/devices/robot/robot_system/test/CVS/Root b/modules/devices/robot/robot_system/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/robot_system/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/robot_system/test/CVS/Tag b/modules/devices/robot/robot_system/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/robot_system/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/robot_system/test/CVS/Template b/modules/devices/robot/robot_system/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/robot_system/test/Makefile b/modules/devices/robot/robot_system/test/Makefile new file mode 100755 index 0000000..d2c03d8 --- /dev/null +++ b/modules/devices/robot/robot_system/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/robot/robot_system/test/encoders_eirbot_config.h b/modules/devices/robot/robot_system/test/encoders_eirbot_config.h new file mode 100644 index 0000000..9524b83 --- /dev/null +++ b/modules/devices/robot/robot_system/test/encoders_eirbot_config.h @@ -0,0 +1,48 @@ +// EIRBOT 2005 +// ToF +/** \file encoders_eirbot_config.h + * \brief configuration du module codeur + * + * \todo il reste a implémanter la version sur irq + * + * \test a tester en version xil + * + * on peut configurer ici combien de codeurs seront utilisés + * et comment y accéder (interface bus xilinx ou ports en irq) + */ + +#ifndef _ENCODERS_EIRBOT_CONFIG_ +#define _ENCODERS_EIRBOT_CONFIG_ + + + +/** mode de fonctionnement, au choix */ +//#define CODEUR_MODE_IRQ +#define ENCODERS_MODE_XILINX + + +/** port utilisé pour la séléction d'adresses dans le xilinx + * exemple, pour 4 codeurs, avec un port de séléction de 2 bits sur le portB, bits 5 et 6 : + * #define CODEUR_SELEC_NITS_NUM 2 + * #define CODEUR_SELEC_BIT0 5 + * #define CODEUR_SELEC_PORT PORTB + * #define CODEUR_SELEC_DDR DDRB +*/ + +#define ENCODERS_NUMBER 4 +#define ENCODERS_SELEC_NITS_NUM 3 +#define ENCODERS_SELEC_BIT0 0 +#define ENCODERS_SELEC_PORT PORTA +#define ENCODERS_SELEC_DDR DDRA + +/** définition du bus 8 bits utilisé dans le mode xilinx */ +#define ENCODERS_PIN PINB +#define ENCODERS_DATA_NBBITS 8 +#define ENCODERS_DATA_BIT0 0 +#define ENCODERS_DATA_DDR DDRB + + + +#endif + + diff --git a/modules/devices/robot/robot_system/test/error_config.h b/modules/devices/robot/robot_system/test/error_config.h new file mode 100644 index 0000000..5c2b6df --- /dev/null +++ b/modules/devices/robot/robot_system/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.3.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/robot/robot_system/test/main.c b/modules/devices/robot/robot_system/test/main.c new file mode 100755 index 0000000..62f2973 --- /dev/null +++ b/modules/devices/robot/robot_system/test/main.c @@ -0,0 +1,42 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.3.6.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <uart.h> +#include <aversive/wait.h> + + +#include <robot_system.h> + +int main(void) +{ + /* XXX todo */ + + struct robot_system mon_robot; + + rs_init(&mon_robot); + + + + return 0; +} + diff --git a/modules/devices/robot/robot_system/test/pwm_config.h b/modules/devices/robot/robot_system/test/pwm_config.h new file mode 100644 index 0000000..9a366a7 --- /dev/null +++ b/modules/devices/robot/robot_system/test/pwm_config.h @@ -0,0 +1,116 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ +/** \file pwm_config.h + \brief Module to operate all PWM outputs + + \test not tested + +*/ + + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +/* Which PWM are enabled ? */ +//#define PWM0_ENABLED +#define PWM1A_ENABLED +//#define PWM1B_ENABLED +//#define PWM1C_ENABLED +//#define PWM2_ENABLED +//#define PWM3A_ENABLED +//#define PWM3B_ENABLED +//#define PWM3C_ENABLED + + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +// timer configs (not all possibilities can be used at this time) +#define TIMER0_MODE TIMER_8_MODE_PWM +#define TIMER0_PRESCALE TIMER_8_PRESCALE_64 + +#define TIMER1_MODE TIMER_16_MODE_PWM_10 +#define TIMER1_PRESCALE TIMER_16_PRESCALE_8 + +#define TIMER2_MODE TIMER_8_MODE_PWM +#define TIMER2_PRESCALE TIMER_8_PRESCALE_64 + +#define TIMER3_MODE TIMER_16_MODE_PWM_10 +#define TIMER3_PRESCALE TIMER_16_PRESCALE_8 + + + + +/** config for pwm and signs + +The pwm mode is defined as follows : +you can add flags like the ones who follow : + +PWM_NORMAL : normal pwm, just to put a value if nothing else is needed +PWM_REVERSE : invert pwm output, not sign + +PWM_SIGNED : activate the sign output on a port (see config) +PWM_SIGN_INVERTED : invert sign output +PWM_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for low values, + else negative low values are near 100% + +if you need for example a PWM1A with special sign mode you configure like this : + +#define PWM1A_MODE (PWM_SIGNED | PWM_SPECIAL_SIGN_MODE) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + +*/ + + + +// example for signed pwm1A +#define PWM1A_MODE (PWM_SIGNED) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + + + + /** this tries to make the PWMs to synchronize. + experimental feature, could lead to problems. + to synch PWMs you need to enshure that the timers have same prescales, + and the same PWM mode */ + +//#define PWM_SYNCH + +/* choose one of these */ +//#define PWM_SYNCH_NO_PRESCALE +//#define PWM_SYNCH_PRESCALE_8 +#define PWM_SYNCH_PRESCALE_MORE + +#define TIMER_0_SYNCH +#define TIMER_1_SYNCH +#define TIMER_2_SYNCH +#define TIMER_3_SYNCH + + + +#endif + diff --git a/modules/devices/robot/robot_system/test/scheduler_config.h b/modules/devices/robot/robot_system/test/scheduler_config.h new file mode 100644 index 0000000..d91a05a --- /dev/null +++ b/modules/devices/robot/robot_system/test/scheduler_config.h @@ -0,0 +1,29 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + + +#define SCHEDULER_NB_MAX_EVENT 5 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/devices/robot/robot_system/test/uart_config.h b/modules/devices/robot/robot_system/test/uart_config.h new file mode 100644 index 0000000..6b4cec8 --- /dev/null +++ b/modules/devices/robot/robot_system/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/devices/robot/robot_system/test/wait_config.h b/modules/devices/robot/robot_system/test/wait_config.h new file mode 100755 index 0000000..bb87103 --- /dev/null +++ b/modules/devices/robot/robot_system/test/wait_config.h @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: wait_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +#ifndef _WAIT_CONFIG_ +#define _WAIT_CONFIG_ 1.0 // version + +// wait_config.h +// This file is the local config file to be used with the wait module. +// This is an example file +//can we perhaps delete this file? + + + +#endif diff --git a/modules/devices/robot/trajectory_manager/CVS/Entries b/modules/devices/robot/trajectory_manager/CVS/Entries new file mode 100644 index 0000000..f229895 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/doc.txt/1.1.2.1/Fri Jun 1 09:37:22 2007//Tb_zer0 +/trajectory_manager.c/1.4.4.17/Mon May 18 12:28:36 2009//Tb_zer0 +/trajectory_manager.h/1.4.4.10/Sat May 2 10:03:04 2009//Tb_zer0 +D/test//// diff --git a/modules/devices/robot/trajectory_manager/CVS/Repository b/modules/devices/robot/trajectory_manager/CVS/Repository new file mode 100644 index 0000000..a457c0e --- /dev/null +++ b/modules/devices/robot/trajectory_manager/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/trajectory_manager diff --git a/modules/devices/robot/trajectory_manager/CVS/Root b/modules/devices/robot/trajectory_manager/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/trajectory_manager/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/trajectory_manager/CVS/Tag b/modules/devices/robot/trajectory_manager/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/trajectory_manager/CVS/Template b/modules/devices/robot/trajectory_manager/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/trajectory_manager/Makefile b/modules/devices/robot/trajectory_manager/Makefile new file mode 100644 index 0000000..a4b4c77 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/Makefile @@ -0,0 +1,8 @@ +TARGET = trajectory_manager + +# List C source files here. (C dependencies are automatically generated.) +SRC = trajectory_manager.c + +########################################## + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/robot/trajectory_manager/doc.txt b/modules/devices/robot/trajectory_manager/doc.txt new file mode 100644 index 0000000..b5f3f83 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/doc.txt @@ -0,0 +1,148 @@ +Le module ne fonctionne qu'avec un asserv composes des modules +control_system_manager, position_manager, quadramp, robot_system. +Il utilise le module vect2. + + +QUESTIONS (et reponses) QUI RESTENT + +- cm ou mm ? +- quand on donne l'ordre d'aller a un point tres proche du robot, mais + different en angle, ca fait des gros pivots. Solution ? +- pour le trajectory_nearly_finished(), doit-on utiliser une fenetre, ou + etre en fonction de la rampe ? Pour la rampe, la distance en pas c'est + Vmax.Vmax / 2.Adec +- bien preciser les unites dans les noms des variables, ca rend le + code plus clair (par exemple les angles en deg ou rad, les distances + en cm ou mm...) +- l'angle target.angle de la structure est entre 0 et 2 pi ? +- pour le 'nearly finished' dans le cas d'une trajectoire sans evenement, + comment gerer ? +- quid du position manager, qui retourne un angle entre -pi et pi, et ca, + c'est chiant. +- dans position manager, il manque les unites dans les noms de var +- l'evenement trajectory est supprime lorsque l'on s'approche du point, du + coup on n'est plus asservi sur le point x,y a partir d'une certaine + distance +- la vitesse pourrait etre specifiee en cm/s et deg/s + +INIT DU MODULE + + void trajectory_init(struct trajectory * traj); + +Initialisation de la structure. Met tout a zero, et le scheduler_task +a -1. + + + void trajectory_set_cs(struct trajectory * traj, struct cs * cs_d, struct cs * cs_a); + +Associe les structures d'asservissement a la structure traj. + + void trajectory_set_robot_params(struct trajectory * traj, struct robot_system * rs, + struct robot_position * pos); + +Associe les structures robot_system et position a la structure traj. + + + void trajectory_set_windows(struct trajectory * traj, double d_win, double a_win) + +Definit la fenetre de fin de trajectoire, en angle comme en distance + + + void trajectory_set_speed( struct trajectory * traj, int16_t speed_d, int16_t speed_a); + +Definit la vitesse lineaire et angulaire max + + +STRUCTURE DE DONNEES + +struct trajectory { + enum trajectory_state state; /*<< describe the type of target, and if we reached the target */ + + union { + vect2_cart vect; /**<< target, if it is a vector */ + double angle; /**<< target, if it is an angle */ + } target; + + double d_win; /**<< distance window (for END_NEAR) */ + double a_win_rad; /**<< angle window (for END_NEAR) */ + + uint16_t d_speed; /**<< distance speed consign */ + uint16_t a_speed; /**<< angle speed consign */ + + struct robot_position * position; /**<< associated robot_position */ + struct robot_system * robot; /**<< associated robot_system */ + struct cs * csm_angle; /**<< associated control system (angle) */ + struct cs * csm_distance; /**<< associated control system (distance) */ + + int8_t scheduler_task; /**<< id of current task (-1 if no running task) */ +}; + + +FONCTIONS ET MACROS STATIQUES + +- modulo_pi(a) : retourne a entre -pi et pi +- modulo_2pi(a) : retourne a entre 0 et 2.pi +- modulo_180(a) : retourne a entre -180 et 180 +- modulo_360(a) : retourne a entre 0 et 360 +(on considere que le a d'origine n'est pas a plus d'un + tour [2.pi ou 360] de son intervalle) + +- is_in_dist_window(t) : vrai si on a dans la fenetre de dist +- is_in_angle_window(t) : vrai si on a dans la fenetre d'angle + +- schedule_traj_event(t) : ajoute l'evenement de gestion de traj +- delete_traj_event(t) : le supprime + + +GOTO XY + +Donnees d'entree, fournies par l'utilisateur du module +- vitesse lineaire max et vitesse angulaire max +- le point de destination du robot (relatif ou absolu) +- fenetre de fin de trajectoire (distance, precise a l'init) +- marche avant, arriere, ou le plus court des deux. + +Donnees d'entree +- la position du robot +- les parametres du quadramp + +Evenements retournes + Les fonctions ne re retournent rien, on sait lorsque l'on arrive en + appelant: + - trajectory_finished() : le robot est arrive a destination, la + consigne d'asservissement en position correspond alors a la + consigne de position filtree (apres quadramp). Le robot est sense + etre a l'arret, ou presque. + - trajectory_in_window() : le robot est entre dans la fenetre + d'arrivee, de distance ou d'angle. + - trajectory_in_deceleration() : le robot est arrive assez pres du + point, juste avant la rampe de deceleration. Permet d'enchainer + des trajectoires sans ralentir. Si ca ne va pas avec la rampe de + deceleration, alors il faut au moins quelque chose qui depende de + la vitesse + +Infos sur l'algo +- La consigne de vitesse passee a l'asservissement depend de l'angle + du robot pour aller vers le point suivant +- La consigne de position en distance est la distance vers le point +- La consigne de position en angle est l'angle vers le point + + void trajectory_goto_xy_abs( struct trajectory * traj, double x, double y ); + void trajectory_goto_xy_rel( struct trajectory * traj, double x, double y ); + void trajectory_goto_da_rel( struct trajectory * traj, double d, double a_deg ); + + + + +TRAJS SIMPLE (pas d'event) + void trajectory_d_a_rel ( struct trajectory * traj, double d, double a ); + void trajectory_d_rel( struct trajectory * traj, double d, double a ); + void trajectory_a_rel( struct trajectory * traj, double d, double a ); + void trajectory_a_abs( struct trajectory * traj, double a ); + void trajectory_turnto_xy_abs( struct trajectory* traj, double tx, double ty ); + void trajectory_only_d( struct trajectory * traj, double d ); + void trajectory_only_a( struct trajectory * traj, double a ); + void trajectory_stop( struct trajectory * traj ); + void trajectory_hardstop( struct trajectory * traj ); + + diff --git a/modules/devices/robot/trajectory_manager/test/.config b/modules/devices/robot/trajectory_manager/test/.config new file mode 100644 index 0000000..145956d --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/.config @@ -0,0 +1,234 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_FIXED_POINT=y +CONFIG_MODULE_VECT2=y +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +CONFIG_MODULE_ROBOT_SYSTEM=y +CONFIG_MODULE_POSITION_MANAGER=y +CONFIG_MODULE_TRAJECTORY_MANAGER=y + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/robot/trajectory_manager/test/CVS/Entries b/modules/devices/robot/trajectory_manager/test/CVS/Entries new file mode 100644 index 0000000..386d4be --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.1.2.2/Fri Jun 1 10:30:05 2007//Tb_zer0 +/Makefile/1.1.2.1/Fri Jun 1 09:37:22 2007//Tb_zer0 +/error_config.h/1.1.2.1/Fri Jun 1 09:37:22 2007//Tb_zer0 +/main.c/1.1.2.3/Mon Dec 31 16:25:01 2007//Tb_zer0 +/scheduler_config.h/1.1.2.1/Fri Jun 1 09:37:23 2007//Tb_zer0 +D diff --git a/modules/devices/robot/trajectory_manager/test/CVS/Repository b/modules/devices/robot/trajectory_manager/test/CVS/Repository new file mode 100644 index 0000000..f9984ee --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/robot/trajectory_manager/test diff --git a/modules/devices/robot/trajectory_manager/test/CVS/Root b/modules/devices/robot/trajectory_manager/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/robot/trajectory_manager/test/CVS/Tag b/modules/devices/robot/trajectory_manager/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/robot/trajectory_manager/test/CVS/Template b/modules/devices/robot/trajectory_manager/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/robot/trajectory_manager/test/Makefile b/modules/devices/robot/trajectory_manager/test/Makefile new file mode 100755 index 0000000..d2c03d8 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/robot/trajectory_manager/test/error_config.h b/modules/devices/robot/trajectory_manager/test/error_config.h new file mode 100644 index 0000000..1dd55c8 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-06-01 09:37:22 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/robot/trajectory_manager/test/main.c b/modules/devices/robot/trajectory_manager/test/main.c new file mode 100644 index 0000000..129c02d --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/main.c @@ -0,0 +1,146 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.3 2007-12-31 16:25:01 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> +#include <math.h> +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/error.h> +#include <aversive/wait.h> + +#include <scheduler.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <position_manager.h> +#include <trajectory_manager.h> + + + +/* XXX it is 90 don't forget it :) */ +#define MATCH_TIME 90 + +/* decrease track to decrease angle */ +#define MOT_TRACK_CM 23.906 +#define EXT_TRACK_CM 8.995 // 8.5 +#define VIRTUAL_TRACK_CM MOT_TRACK_CM + +#define DIST_IMP_CM 6160.0 + +#define LEFT_ENCODER_MOT ((void *)0) +#define RIGHT_ENCODER_MOT ((void *)1) +#define LEFT_ENCODER_EXT ((void *)2) +#define RIGHT_ENCODER_EXT ((void *)3) + + +#define LEFT_PWM ((void *)PWM3C) +#define RIGHT_PWM ((void *)PWM1A) +#define ROLL_PWM ((void *)PWM2) + +#define DO_CS 1 /* control system */ +#define DO_RS 2 /* robot system (angle/distance) */ +#define DO_POS 4 /* process position */ +#define DO_BD 8 /* process blocking detection */ +#define DO_TIMER 16 /* check time and stop after 90 secs */ + +/** ERROR NUMS */ +#define E_USER_NOTHING 193 + +#define BALL_IS_READY 1 +#define BALL_IS_WHITE 2 +#define BALL_COUNT (4+8) +#define BALL_SUCKED 16 +#define BALL_BUSY 32 + +#define BALL_COUNT_BIT 2 + +#define BALL_LAYDOWN 1 +#define BALL_EJECT 2 +#define BALL_RESUCK 3 +#define BALL_OFF 4 +#define BALL_ON 5 +#define BALL_LAYDOWN_FORCE 6 +#define BALL_EJECT_FORCE 7 + +struct robot { + s08 cs_events; + + struct robot_system rs; + struct robot_position pos; + + struct cs cs_a; + struct quadramp_filter qr_a; + + struct cs cs_d; + struct quadramp_filter qr_d; + + struct trajectory traj; +} robot; + +/* WARNING : this test is only a compilation test */ +/* it does not check that the module is working */ +int main(void) +{ + /* ROBOT_SYSTEM */ + rs_init(&robot.rs); + rs_set_ratio(&robot.rs, MOT_TRACK_CM / EXT_TRACK_CM); + rs_set_flags(&robot.rs, 0); /* rs use mot */ + + /* POSITION MANAGER */ + position_init(&robot.pos); + position_set_physical_params(&robot.pos, VIRTUAL_TRACK_CM, DIST_IMP_CM); + position_set_related_robot_system(&robot.pos, &robot.rs); + position_use_ext(&robot.pos); + + /* CS DISTANCE */ + quadramp_init(&robot.qr_d); + quadramp_set_1st_order_vars(&robot.qr_d, 1000, 1000); /* set speed */ + quadramp_set_2nd_order_vars(&robot.qr_d, 10, 10); /* set accel */ + + cs_init(&robot.cs_d); + cs_set_consign_filter(&robot.cs_d, quadramp_do_filter, &robot.qr_d); + cs_set_consign(&robot.cs_d, 0); + + /* CS ANGLE */ + quadramp_init(&robot.qr_a); + quadramp_set_1st_order_vars(&robot.qr_a, 500, 500); /* set speed */ + quadramp_set_2nd_order_vars(&robot.qr_a, 5, 5); /* set accel */ + + cs_init(&robot.cs_a); + cs_set_consign_filter(&robot.cs_a, quadramp_do_filter, &robot.qr_a); + cs_set_consign(&robot.cs_a, 0); + + /* TRAJECTORY MANAGER */ + trajectory_init(&robot.traj); + trajectory_set_cs(&robot.traj, &robot.cs_d, &robot.cs_a); + trajectory_set_robot_params(&robot.traj, &robot.rs, &robot.pos); + trajectory_set_windows(&robot.traj, 12.0, 15.0, 50.0); + +#ifdef HOST_VERSION + while(1) { + scheduler_interrupt(); + } +#endif + + return 0; +} + + diff --git a/modules/devices/robot/trajectory_manager/test/scheduler_config.h b/modules/devices/robot/trajectory_manager/test/scheduler_config.h new file mode 100644 index 0000000..e57ce35 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/test/scheduler_config.h @@ -0,0 +1,64 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1.2.1 2007-06-01 09:37:23 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 2 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 5 + + +/* define it only if CONFIG_MODULE_SCHEDULER_USE_TIMERS is enabled. In + this case, precaler is defined in timers_config.h in your project + directory. */ +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS +#define SCHEDULER_TIMER_REGISTER() timer0_register_OV_intr(scheduler_interrupt) +#define SCHEDULER_CLOCK_PRESCALER timer0_get_prescaler_div() + + +/* or set the prescaler manually (in this case, you use must TIMER0, + and the prescaler must be a correct value regarding the AVR device + you are using (look in include/aversive/parts.h). Obviously, the + values of SCHEDULER_CK and SCHEDULER_CLOCK_PRESCALER must also be + coherent (TIMER0_PRESCALER_DIV_VALUE and VALUE) */ +#else /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ +#define SCHEDULER_CK TIMER0_PRESCALER_DIV_8 +#define SCHEDULER_CLOCK_PRESCALER 8 /* must coherent with value above */ + +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/devices/robot/trajectory_manager/trajectory_manager.c b/modules/devices/robot/trajectory_manager/trajectory_manager.c new file mode 100644 index 0000000..d2960f4 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/trajectory_manager.c @@ -0,0 +1,642 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: trajectory_manager.c,v 1.4.4.17 2009-05-18 12:28:36 zer0 Exp $ + * + */ + +/* Trajectory Manager v2 - zer0 - for Eurobot 2008 */ + +#include <string.h> +#include <stdlib.h> +#include <math.h> + +#include <aversive.h> +#include <aversive/error.h> +#include <scheduler.h> +#include <vect2.h> + +#include <position_manager.h> +#include <robot_system.h> +#include <control_system_manager.h> +#include <quadramp.h> + +#include <trajectory_manager.h> + +#define M_2PI (2*M_PI) + +#define DEG(x) ((x) * (180.0 / M_PI)) +#define RAD(x) ((x) * (M_PI / 180.0)) + +static void trajectory_manager_event(void *param); + +/************ INIT FUNCS */ + +/** structure initialization */ +void trajectory_init(struct trajectory *traj) +{ + uint8_t flags; + + IRQ_LOCK(flags); + memset(traj, 0, sizeof(struct trajectory)); + traj->state = READY; + traj->scheduler_task = -1; + IRQ_UNLOCK(flags); +} + +/** structure initialization */ +void trajectory_set_cs(struct trajectory *traj, struct cs *cs_d, + struct cs *cs_a) +{ + uint8_t flags; + + IRQ_LOCK(flags); + traj->csm_distance = cs_d; + traj->csm_angle = cs_a; + IRQ_UNLOCK(flags); +} + +/** structure initialization */ +void trajectory_set_robot_params(struct trajectory *traj, + struct robot_system *rs, + struct robot_position *pos) +{ + uint8_t flags; + IRQ_LOCK(flags); + traj->robot = rs; + traj->position = pos; + IRQ_UNLOCK(flags); +} + +/** set speed consign */ +void trajectory_set_speed( struct trajectory *traj, int16_t d_speed, int16_t a_speed) +{ + uint8_t flags; + IRQ_LOCK(flags); + traj->d_speed = d_speed; + traj->a_speed = a_speed; + IRQ_UNLOCK(flags); +} + +/** set windows for trajectory */ +void trajectory_set_windows(struct trajectory *traj, double d_win, + double a_win_deg, double a_start_deg) +{ + uint8_t flags; + IRQ_LOCK(flags); + traj->d_win = d_win ; + traj->a_win_rad = RAD(a_win_deg); + traj->a_start_rad = RAD(a_start_deg); + IRQ_UNLOCK(flags); +} + +/************ STATIC [ AND USEFUL ] FUNCS */ + +/** set speed consign in quadramp filter */ +static void set_quadramp_speed(struct trajectory *traj, int16_t d_speed, int16_t a_speed) +{ + struct quadramp_filter * q_d, * q_a; + q_d = traj->csm_distance->consign_filter_params; + q_a = traj->csm_angle->consign_filter_params; + quadramp_set_1st_order_vars(q_d, ABS(d_speed), ABS(d_speed)); + quadramp_set_1st_order_vars(q_a, ABS(a_speed), ABS(a_speed)); +} + +/** get angle speed consign in quadramp filter */ +static uint32_t get_quadramp_angle_speed(struct trajectory *traj) +{ + struct quadramp_filter *q_a; + q_a = traj->csm_angle->consign_filter_params; + return q_a->var_1st_ord_pos; +} + +/** get distance speed consign in quadramp filter */ +static uint32_t get_quadramp_distance_speed(struct trajectory *traj) +{ + struct quadramp_filter *q_d; + q_d = traj->csm_distance->consign_filter_params; + return q_d->var_1st_ord_pos; +} + +/** remove event if any */ +static void delete_event(struct trajectory *traj) +{ + set_quadramp_speed(traj, traj->d_speed, traj->a_speed); + if ( traj->scheduler_task != -1) { + DEBUG(E_TRAJECTORY, "Delete event"); + scheduler_del_event(traj->scheduler_task); + traj->scheduler_task = -1; + } +} + +/** schedule the trajectory event */ +static void schedule_event(struct trajectory *traj) +{ + if ( traj->scheduler_task != -1) { + DEBUG(E_TRAJECTORY, "Schedule event, already scheduled"); + } + else { + traj->scheduler_task = + scheduler_add_periodical_event_priority(&trajectory_manager_event, + (void*)traj, + 100000L/SCHEDULER_UNIT, 30); + } +} + +/** do a modulo 2.pi -> [-Pi,+Pi], knowing that 'a' is in [-3Pi,+3Pi] */ +static double simple_modulo_2pi(double a) +{ + if (a < -M_PI) { + a += M_2PI; + } + else if (a > M_PI) { + a -= M_2PI; + } + return a; +} + +/** do a modulo 2.pi -> [-Pi,+Pi] */ +static double modulo_2pi(double a) +{ + double res = a - (((int32_t) (a/M_2PI)) * M_2PI); + return simple_modulo_2pi(res); +} + +/** near the target (dist) ? */ +static uint8_t is_robot_in_dist_window(struct trajectory *traj, double d_win) +{ + double d = traj->target.pol.distance - rs_get_distance(traj->robot); + d = ABS(d); + d = d / traj->position->phys.distance_imp_per_mm; + return (d < d_win); +} + +/** near the target (dist in x,y) ? */ +static uint8_t is_robot_in_xy_window(struct trajectory *traj, double d_win) +{ + double x1 = traj->target.cart.x; + double y1 = traj->target.cart.y; + double x2 = position_get_x_double(traj->position); + double y2 = position_get_y_double(traj->position); + return ( sqrt ((x2-x1) * (x2-x1) + (y2-y1) * (y2-y1)) < d_win ); +} + +/** near the angle target in radian ? Only valid if + * traj->target.pol.angle is set (i.e. an angle command, not an xy + * command) */ +static uint8_t is_robot_in_angle_window(struct trajectory *traj, double a_win_rad) +{ + double a; + + /* convert relative angle from imp to rad */ + a = traj->target.pol.angle - rs_get_angle(traj->robot); + a /= traj->position->phys.distance_imp_per_mm; + a /= traj->position->phys.track_mm; + a *= 2.; + return ABS(a) < a_win_rad; +} + + +/************ SIMPLE TRAJS, NO EVENT */ + +#define UPDATE_D 1 +#define UPDATE_A 2 +#define RESET_D 4 +#define RESET_A 8 + +/** + * update angle and/or distance + * this function is not called directly by the user + * traj : pointer to the trajectory structure + * d_mm : distance in mm + * a_rad : angle in radian + * flags : what to update (UPDATE_A, UPDATE_D) + */ +void __trajectory_goto_d_a_rel(struct trajectory *traj, double d_mm, + double a_rad, uint8_t state, uint8_t flags) +{ + int32_t a_consign, d_consign; + + DEBUG(E_TRAJECTORY, "Goto DA/RS rel to d=%f a_rad=%f", d_mm, a_rad); + delete_event(traj); + traj->state = state; + if (flags & UPDATE_A) { + if (flags & RESET_A) { + a_consign = 0; + } + else { + a_consign = (int32_t)(a_rad * (traj->position->phys.distance_imp_per_mm) * + (traj->position->phys.track_mm) / 2); + } + a_consign += rs_get_angle(traj->robot); + traj->target.pol.angle = a_consign; + cs_set_consign(traj->csm_angle, a_consign); + } + if (flags & UPDATE_D) { + if (flags & RESET_D) { + d_consign = 0; + } + else { + d_consign = (int32_t)((d_mm) * (traj->position->phys.distance_imp_per_mm)); + } + d_consign += rs_get_distance(traj->robot); + traj->target.pol.distance = d_consign; + cs_set_consign(traj->csm_distance, d_consign); + } +} + +/** go straight forward (d is in mm) */ +void trajectory_d_rel(struct trajectory *traj, double d_mm) +{ + __trajectory_goto_d_a_rel(traj, d_mm, 0, RUNNING_D, + UPDATE_D | UPDATE_A | RESET_A); +} + +/** update distance consign without changing angle consign */ +void trajectory_only_d_rel(struct trajectory *traj, double d_mm) +{ + __trajectory_goto_d_a_rel(traj, d_mm, 0, RUNNING_D, UPDATE_D); +} + +/** turn by 'a' degrees */ +void trajectory_a_rel(struct trajectory *traj, double a_deg_rel) +{ + __trajectory_goto_d_a_rel(traj, 0, RAD(a_deg_rel), RUNNING_A, + UPDATE_A | UPDATE_D | RESET_D); +} + +/** turn by 'a' degrees */ +void trajectory_a_abs(struct trajectory *traj, double a_deg_abs) +{ + double posa = position_get_a_rad_double(traj->position); + double a; + + a = RAD(a_deg_abs) - posa; + a = modulo_2pi(a); + __trajectory_goto_d_a_rel(traj, 0, a, RUNNING_A, + UPDATE_A | UPDATE_D | RESET_D); +} + +/** turn the robot until the point x,y is in front of us */ +void trajectory_turnto_xy(struct trajectory *traj, double x_abs_mm, double y_abs_mm) +{ + double posx = position_get_x_double(traj->position); + double posy = position_get_y_double(traj->position); + double posa = position_get_a_rad_double(traj->position); + + DEBUG(E_TRAJECTORY, "Goto Turn To xy %f %f", x_abs_mm, y_abs_mm); + __trajectory_goto_d_a_rel(traj, 0, + simple_modulo_2pi(atan2(y_abs_mm - posy, x_abs_mm - posx) - posa), + RUNNING_A, + UPDATE_A | UPDATE_D | RESET_D); +} + +/** turn the robot until the point x,y is behind us */ +void trajectory_turnto_xy_behind(struct trajectory *traj, double x_abs_mm, double y_abs_mm) +{ + double posx = position_get_x_double(traj->position); + double posy = position_get_y_double(traj->position); + double posa = position_get_a_rad_double(traj->position); + + DEBUG(E_TRAJECTORY, "Goto Turn To xy %f %f", x_abs_mm, y_abs_mm); + __trajectory_goto_d_a_rel(traj, 0, + modulo_2pi(atan2(y_abs_mm - posy, x_abs_mm - posx) - posa + M_PI), + RUNNING_A, + UPDATE_A | UPDATE_D | RESET_D); +} + +/** update angle consign without changing distance consign */ +void trajectory_only_a_rel(struct trajectory *traj, double a_deg) +{ + __trajectory_goto_d_a_rel(traj, 0, RAD(a_deg), RUNNING_A, + UPDATE_A); +} + +/** update angle consign without changing distance consign */ +void trajectory_only_a_abs(struct trajectory *traj, double a_deg_abs) +{ + double posa = position_get_a_rad_double(traj->position); + double a; + + a = RAD(a_deg_abs) - posa; + a = modulo_2pi(a); + __trajectory_goto_d_a_rel(traj, 0, a, RUNNING_A, UPDATE_A); +} + +/** turn by 'a' degrees */ +void trajectory_d_a_rel(struct trajectory *traj, double d_mm, double a_deg) +{ + __trajectory_goto_d_a_rel(traj, d_mm, RAD(a_deg), + RUNNING_AD, UPDATE_A | UPDATE_D); +} + +/** set relative angle and distance consign to 0 */ +void trajectory_stop(struct trajectory *traj) +{ + __trajectory_goto_d_a_rel(traj, 0, 0, READY, + UPDATE_A | UPDATE_D | RESET_D | RESET_A); +} + +/** set relative angle and distance consign to 0, and break any + * deceleration ramp in quadramp filter */ +void trajectory_hardstop(struct trajectory *traj) +{ + struct quadramp_filter *q_d, *q_a; + + q_d = traj->csm_distance->consign_filter_params; + q_a = traj->csm_angle->consign_filter_params; + __trajectory_goto_d_a_rel(traj, 0, 0, READY, + UPDATE_A | UPDATE_D | RESET_D | RESET_A); + + q_d->previous_var = 0; + q_d->previous_out = rs_get_distance(traj->robot); + q_a->previous_var = 0; + q_a->previous_out = rs_get_angle(traj->robot); +} + + +/************ GOTO XY, USE EVENTS */ + +/** goto a x,y point, using a trajectory event */ +void trajectory_goto_xy_abs(struct trajectory *traj, double x, double y) +{ + DEBUG(E_TRAJECTORY, "Goto XY"); + delete_event(traj); + traj->target.cart.x = x; + traj->target.cart.y = y; + traj->state = RUNNING_XY_START; + trajectory_manager_event(traj); + schedule_event(traj); +} + +/** go forward to a x,y point, using a trajectory event */ +void trajectory_goto_forward_xy_abs(struct trajectory *traj, double x, double y) +{ + DEBUG(E_TRAJECTORY, "Goto XY_F"); + delete_event(traj); + traj->target.cart.x = x; + traj->target.cart.y = y; + traj->state = RUNNING_XY_F_START; + trajectory_manager_event(traj); + schedule_event(traj); +} + +/** go backward to a x,y point, using a trajectory event */ +void trajectory_goto_backward_xy_abs(struct trajectory *traj, double x, double y) +{ + DEBUG(E_TRAJECTORY, "Goto XY_B"); + delete_event(traj); + traj->target.cart.x = x; + traj->target.cart.y = y; + traj->state = RUNNING_XY_B_START; + trajectory_manager_event(traj); + schedule_event(traj); +} + +/** go forward to a d,a point, using a trajectory event */ +void trajectory_goto_d_a_rel(struct trajectory *traj, double d, double a) +{ + vect2_pol p; + double x = position_get_x_double(traj->position); + double y = position_get_y_double(traj->position); + + DEBUG(E_TRAJECTORY, "Goto DA rel"); + + delete_event(traj); + p.r = d; + p.theta = RAD(a) + position_get_a_rad_double(traj->position); + vect2_pol2cart(&p, &traj->target.cart); + traj->target.cart.x += x; + traj->target.cart.y += y; + + traj->state = RUNNING_XY_START; + trajectory_manager_event(traj); + schedule_event(traj); +} + +/** go forward to a x,y relative point, using a trajectory event */ +void trajectory_goto_xy_rel(struct trajectory *traj, double x_rel_mm, double y_rel_mm) +{ + vect2_cart c; + vect2_pol p; + double x = position_get_x_double(traj->position); + double y = position_get_y_double(traj->position); + + DEBUG(E_TRAJECTORY, "Goto XY rel"); + + delete_event(traj); + c.x = x_rel_mm; + c.y = y_rel_mm; + + vect2_cart2pol(&c, &p); + p.theta += position_get_a_rad_double(traj->position);; + vect2_pol2cart(&p, &traj->target.cart); + + traj->target.cart.x += x; + traj->target.cart.y += y; + + traj->state = RUNNING_XY_START; + trajectory_manager_event(traj); + schedule_event(traj); +} + +/************ FUNCS FOR GETTING TRAJ STATE */ + +/** return true if the position consign is equal to the filtered + * position consign (after quadramp filter), for angle and + * distance. */ +uint8_t trajectory_finished(struct trajectory *traj) +{ + return cs_get_consign(traj->csm_angle) == cs_get_filtered_consign(traj->csm_angle) && + cs_get_consign(traj->csm_distance) == cs_get_filtered_consign(traj->csm_distance) ; +} + +/** return true if traj is nearly finished */ +uint8_t trajectory_in_window(struct trajectory *traj, double d_win, double a_win_rad) +{ + switch(traj->state) { + + case RUNNING_XY_ANGLE_OK: + case RUNNING_XY_F_ANGLE_OK: + case RUNNING_XY_B_ANGLE_OK: + /* if robot coordinates are near the x,y target */ + return is_robot_in_xy_window(traj, d_win); + + case RUNNING_A: + return is_robot_in_angle_window(traj, a_win_rad); + + case RUNNING_D: + return is_robot_in_dist_window(traj, d_win); + + case RUNNING_AD: + return is_robot_in_dist_window(traj, d_win) && + is_robot_in_angle_window(traj, a_win_rad); + + case RUNNING_XY_START: + case RUNNING_XY_F_START: + case RUNNING_XY_B_START: + case RUNNING_XY_ANGLE: + case RUNNING_XY_F_ANGLE: + case RUNNING_XY_B_ANGLE: + default: + return 0; + } +} + +/*********** *TRAJECTORY EVENT FUNC */ + +/** event called for xy trajectories */ +static void trajectory_manager_event(void * param) +{ + struct trajectory *traj = (struct trajectory *)param; + double coef=1.0; + double x = position_get_x_double(traj->position); + double y = position_get_y_double(traj->position); + double a = position_get_a_rad_double(traj->position); + int32_t d_consign=0, a_consign=0; + + /* These vectors contain target position of the robot in + * its own coordinates */ + vect2_cart v2cart_pos; + vect2_pol v2pol_target; + + /* step 1 : process new commands to quadramps */ + + switch (traj->state) { + case RUNNING_XY_START: + case RUNNING_XY_ANGLE: + case RUNNING_XY_ANGLE_OK: + case RUNNING_XY_F_START: + case RUNNING_XY_F_ANGLE: + case RUNNING_XY_F_ANGLE_OK: + case RUNNING_XY_B_START: + case RUNNING_XY_B_ANGLE: + case RUNNING_XY_B_ANGLE_OK: + + /* process the command vector from absolute target and + * current position */ + v2cart_pos.x = traj->target.cart.x - x; + v2cart_pos.y = traj->target.cart.y - y; + vect2_cart2pol(&v2cart_pos, &v2pol_target); + v2pol_target.theta = simple_modulo_2pi(v2pol_target.theta - a); + + /* asked to go backwards */ + if (traj->state >= RUNNING_XY_B_START && + traj->state <= RUNNING_XY_B_ANGLE_OK ) { + v2pol_target.r = -v2pol_target.r; + v2pol_target.theta = simple_modulo_2pi(v2pol_target.theta + M_PI); + } + + /* if we don't need to go forward */ + if (traj->state >= RUNNING_XY_START && + traj->state <= RUNNING_XY_ANGLE_OK ) { + /* If the target is behind the robot, we need to go + * backwards. 0.52 instead of 0.5 because we prefer to + * go forward */ + if ((v2pol_target.theta > 0.52*M_PI) || + (v2pol_target.theta < -0.52*M_PI ) ) { + v2pol_target.r = -v2pol_target.r; + v2pol_target.theta = simple_modulo_2pi(v2pol_target.theta + M_PI); + } + } + + /* If the robot is correctly oriented to start moving in distance */ + /* here limit dist speed depending on v2pol_target.theta */ + if (ABS(v2pol_target.theta) > traj->a_start_rad) // || ABS(v2pol_target.r) < traj->d_win) + set_quadramp_speed(traj, 0, traj->a_speed); + else { + coef = (traj->a_start_rad - ABS(v2pol_target.theta)) / traj->a_start_rad; + set_quadramp_speed(traj, traj->d_speed * coef, traj->a_speed); + } + + d_consign = (int32_t)(v2pol_target.r * (traj->position->phys.distance_imp_per_mm)); + d_consign += rs_get_distance(traj->robot); + + /* angle consign */ + /* XXX here we specify 2.2 instead of 2.0 to avoid oscillations */ + a_consign = (int32_t)(v2pol_target.theta * + (traj->position->phys.distance_imp_per_mm) * + (traj->position->phys.track_mm) / 2.2); + a_consign += rs_get_angle(traj->robot); + + break; + + default: + /* hmmm quite odd, delete the event */ + DEBUG(E_TRAJECTORY, "GNI ???"); + delete_event(traj); + traj->state = READY; + } + + + /* step 2 : update state, or delete event if we reached the + * destination */ + + /* XXX if target is our pos !! */ + + switch (traj->state) { + case RUNNING_XY_START: + case RUNNING_XY_F_START: + case RUNNING_XY_B_START: + /* START -> ANGLE */ + DEBUG(E_TRAJECTORY, "-> ANGLE"); + traj->state ++; + break; + + case RUNNING_XY_ANGLE: + case RUNNING_XY_F_ANGLE: + case RUNNING_XY_B_ANGLE: { + struct quadramp_filter *q_a; + q_a = traj->csm_angle->consign_filter_params; + /* if d_speed is not 0, we are in start_angle_win */ + if (get_quadramp_distance_speed(traj)) { + if(is_robot_in_xy_window(traj, traj->d_win)) { + delete_event(traj); + } + /* ANGLE -> ANGLE_OK */ + traj->state ++; + DEBUG(E_TRAJECTORY, "-> ANGLE_OK"); + } + break; + } + + case RUNNING_XY_ANGLE_OK: + case RUNNING_XY_F_ANGLE_OK: + case RUNNING_XY_B_ANGLE_OK: + /* If we reached the destination */ + if(is_robot_in_xy_window(traj, traj->d_win)) { + delete_event(traj); + } + break; + + default: + break; + } + + /* step 3 : send the processed commands to cs */ + + DEBUG(E_TRAJECTORY, "EVENT XY cur=(%f,%f,%f) cart=(%f,%f) pol=(%f,%f)", + x, y, a, v2cart_pos.x, v2cart_pos.y, v2pol_target.r, v2pol_target.theta); + + DEBUG(E_TRAJECTORY,"d_cur=%" PRIi32 ", d_consign=%" PRIi32 ", d_speed=%" PRIi32 ", " + "a_cur=%" PRIi32 ", a_consign=%" PRIi32 ", a_speed=%" PRIi32, + rs_get_distance(traj->robot), d_consign, get_quadramp_distance_speed(traj), + rs_get_angle(traj->robot), a_consign, get_quadramp_angle_speed(traj)); + + cs_set_consign(traj->csm_angle, a_consign); + cs_set_consign(traj->csm_distance, d_consign); +} diff --git a/modules/devices/robot/trajectory_manager/trajectory_manager.h b/modules/devices/robot/trajectory_manager/trajectory_manager.h new file mode 100644 index 0000000..e2f8034 --- /dev/null +++ b/modules/devices/robot/trajectory_manager/trajectory_manager.h @@ -0,0 +1,162 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: trajectory_manager.h,v 1.4.4.10 2009-05-02 10:03:04 zer0 Exp $ + * + */ + +#ifndef TRAJECTORY_MANAGER +#define TRAJECTORY_MANAGER + +#include <aversive.h> +#include <vect2.h> +#include <robot_system.h> + +enum trajectory_state { + READY, + + /* simple trajectories */ + RUNNING_A, + RUNNING_D, + RUNNING_AD, + + /* trajectories using events */ + RUNNING_XY_START, + RUNNING_XY_ANGLE, + RUNNING_XY_ANGLE_OK, + RUNNING_XY_F_START, + RUNNING_XY_F_ANGLE, + RUNNING_XY_F_ANGLE_OK, + RUNNING_XY_B_START, + RUNNING_XY_B_ANGLE, + RUNNING_XY_B_ANGLE_OK, +}; + + +struct trajectory { + enum trajectory_state state; /*<< describe the type of target, and if we reached the target */ + + union { + vect2_cart cart; /**<< target, if it is a x,y vector */ + struct rs_polar pol; /**<< target, if it is a d,a vector */ + } target; + + double d_win; /**<< distance window (for END_NEAR) */ + double a_win_rad; /**<< angle window (for END_NEAR) */ + double a_start_rad;/**<< in xy consigns, start to move in distance + * when a_target < a_start */ + + uint16_t d_speed; /**<< distance speed consign */ + uint16_t a_speed; /**<< angle speed consign */ + + struct robot_position *position; /**<< associated robot_position */ + struct robot_system *robot; /**<< associated robot_system */ + struct cs *csm_angle; /**<< associated control system (angle) */ + struct cs *csm_distance; /**<< associated control system (distance) */ + + int8_t scheduler_task; /**<< id of current task (-1 if no running task) */ +}; + +/** structure initialization */ +void trajectory_init(struct trajectory *traj); + +/** structure initialization */ +void trajectory_set_cs(struct trajectory *traj, struct cs *cs_d, + struct cs * cs_a); + +/** structure initialization */ +void trajectory_set_robot_params(struct trajectory *traj, + struct robot_system *rs, + struct robot_position *pos) ; + +/** set speed consign */ +void trajectory_set_speed(struct trajectory *traj, int16_t d_speed, int16_t a_speed); + +/** + * set windows for trajectory. + * params: distance window, angle window: we the robot enters this + * position window, we deletes the event and the last consign is + * used. + * a_start_deg used in xy consigns (start to move in distance when + * a_target < a_start) + */ +void trajectory_set_windows(struct trajectory *traj, double d_win, + double a_win_deg, double a_start_deg); + +/** return true if the position consign is equal to the filtered + * position consign (after quadramp filter), for angle and + * distance. */ +uint8_t trajectory_finished(struct trajectory *traj); + +/** return true if traj is nearly finished depending on specified + * parameters */ +uint8_t trajectory_in_window(struct trajectory *traj, double d_win, double a_win_rad); + +/* simple commands */ + +/** set relative angle and distance consign to 0 */ +void trajectory_stop(struct trajectory *traj); + +/** set relative angle and distance consign to 0, and break any + * deceleration ramp in quadramp filter */ +void trajectory_hardstop(struct trajectory *traj); + +/** go straight forward (d is in mm) */ +void trajectory_d_rel(struct trajectory *traj, double d_mm); + +/** update distance consign without changing angle consign */ +void trajectory_only_d_rel(struct trajectory *traj, double d_mm); + +/** turn by 'a' degrees */ +void trajectory_a_rel(struct trajectory *traj, double a_deg); + +/** go to angle 'a' in degrees */ +void trajectory_a_abs(struct trajectory *traj, double a_deg); + +/** turn the robot until the point x,y is in front of us */ +void trajectory_turnto_xy(struct trajectory*traj, double x_abs_mm, double y_abs_mm); + +/** turn the robot until the point x,y is behind us */ +void trajectory_turnto_xy_behind(struct trajectory*traj, double x_abs_mm, double y_abs_mm); + +/** update angle consign without changing distance consign */ +void trajectory_only_a_rel(struct trajectory *traj, double a_deg); + +/** update angle consign without changing distance consign */ +void trajectory_only_a_abs(struct trajectory *traj, double a_deg); + +/** turn by 'a' degrees and go by 'd' mm */ +void trajectory_d_a_rel(struct trajectory *traj, double d_mm, double a_deg); + +/* commands using events */ + +/** goto a x,y point, using a trajectory event */ +void trajectory_goto_xy_abs(struct trajectory *traj, double x_abs_mm, double y_abs_mm); + +/** go forward to a x,y point, using a trajectory event */ +void trajectory_goto_forward_xy_abs(struct trajectory *traj, double x_abs_mm, double y_abs_mm); + +/** go backward to a x,y point, using a trajectory event */ +void trajectory_goto_backward_xy_abs(struct trajectory *traj, double x_abs_mm, double y_abs_mm); + +/** go forward to a d,a point, using a trajectory event */ +void trajectory_goto_d_a_rel(struct trajectory *traj, double d, double a); + +/** go forward to a x,y relative point, using a trajectory event */ +void trajectory_goto_xy_rel(struct trajectory *traj, double x_rel_mm, double y_rel_mm); + +#endif //TRAJECTORY_MANAGER diff --git a/modules/devices/servo/CVS/Entries b/modules/devices/servo/CVS/Entries new file mode 100644 index 0000000..e730039 --- /dev/null +++ b/modules/devices/servo/CVS/Entries @@ -0,0 +1,2 @@ +D/ax12//// +D/multiservo//// diff --git a/modules/devices/servo/CVS/Repository b/modules/devices/servo/CVS/Repository new file mode 100644 index 0000000..140a217 --- /dev/null +++ b/modules/devices/servo/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo diff --git a/modules/devices/servo/CVS/Root b/modules/devices/servo/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/CVS/Tag b/modules/devices/servo/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/CVS/Template b/modules/devices/servo/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/ax12/CVS/Entries b/modules/devices/servo/ax12/CVS/Entries new file mode 100644 index 0000000..4462055 --- /dev/null +++ b/modules/devices/servo/ax12/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.1.4.2/Sun Oct 26 21:59:28 2008//Tb_zer0 +/ax12.c/1.1.4.3/Fri Dec 26 13:48:37 2008//Tb_zer0 +/ax12.h/1.1.4.4/Tue Apr 7 20:00:57 2009//Tb_zer0 +/ax12_address.h/1.1.4.2/Sun Oct 26 21:59:28 2008//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/servo/ax12/CVS/Repository b/modules/devices/servo/ax12/CVS/Repository new file mode 100644 index 0000000..6df8544 --- /dev/null +++ b/modules/devices/servo/ax12/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo/ax12 diff --git a/modules/devices/servo/ax12/CVS/Root b/modules/devices/servo/ax12/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/ax12/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/ax12/CVS/Tag b/modules/devices/servo/ax12/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/ax12/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/ax12/CVS/Template b/modules/devices/servo/ax12/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/ax12/Makefile b/modules/devices/servo/ax12/Makefile new file mode 100755 index 0000000..602ee49 --- /dev/null +++ b/modules/devices/servo/ax12/Makefile @@ -0,0 +1,6 @@ +TARGET = ax12 + +# List C source files here. (C dependencies are automatically generated.) +SRC = ax12.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/servo/ax12/ax12.c b/modules/devices/servo/ax12/ax12.c new file mode 100755 index 0000000..f4e1d4b --- /dev/null +++ b/modules/devices/servo/ax12/ax12.c @@ -0,0 +1,494 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2008) + * JD Brossillon <jean.damien.brossillon@gmail.com> (main job) + * Olivier Matz <zer0@droids-corp.org> (clean-up, fixes) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12.c,v 1.1.4.3 2008-12-26 13:48:37 zer0 Exp $ + * + */ + +/* See some help in ax12.h */ + +#include <stdio.h> +#include <string.h> +#include "ax12.h" +#ifdef CONFIG_MODULE_SCHEDULER +#include <scheduler.h> +#endif + +void AX12_init(AX12 *s) +{ + s->hardware_send = NULL; + s->hardware_recv = NULL; + s->hardware_switch = NULL; +} + +/*_________________________________________________________*/ +/*_________________________________________________________*/ + +void AX12_set_hardware_send(AX12 *s, int8_t(*pf)(uint8_t)) +{ + s->hardware_send = pf; +} + +void AX12_set_hardware_recv(AX12 *s, int16_t(*pf)(void)) +{ + s->hardware_recv = pf; +} + +void AX12_set_hardware_switch(AX12 *s, void(*pf)(uint8_t)) +{ + s->hardware_switch = pf; +} + +/*_________________________________________________________*/ +/*_________________________________________________________*/ + +/* process the cksum of a packet */ +uint8_t AX12_checksum(AX12_Packet *packet) +{ + uint8_t i; + uint8_t checksum=0; + + checksum += packet->id; + checksum += packet->instruction; + + /* Packet also contain length = number of params + 2 */ + checksum += packet->nparams + 2; + + for (i=0; i<packet->nparams; i++) + checksum += packet->params[i]; + + return ~checksum; +} + +/* Send a packet to ax12. Return 0 on sucess. */ +uint8_t AX12_send(AX12 *s, AX12_Packet *packet) +{ + uint8_t i; + uint8_t flags; + uint8_t err; + +#ifdef CONFIG_MODULE_SCHEDULER + uint8_t scheduler_prio; + + scheduler_prio = scheduler_disable_save(); +#endif + + if (packet->nparams > AX12_MAX_PARAMS) { + err = AX12_ERROR_TYPE_INVALID_PACKET; + goto fail; + } + + /* Switch line to write */ + s->hardware_switch(AX12_STATE_WRITE); + + /* Header */ + if (s->hardware_send(0xFF)) { + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + + if (s->hardware_send(0xFF)) { + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + + /* AX12 ID */ + if (s->hardware_send(packet->id)) { + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + + /* Packet length */ + if (s->hardware_send(packet->nparams + 2)) { + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + + /* Instruction */ + if (s->hardware_send(packet->instruction)) { + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + + /* Params */ + for (i=0; i<(packet->nparams); i++) { + if (s->hardware_send(packet->params[i])) { + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + } + + IRQ_LOCK(flags); /* needed if hardware_switch is + synchronous */ + + /* Checksum */ + if (s->hardware_send(AX12_checksum(packet))) { + IRQ_UNLOCK(flags); + err = AX12_ERROR_TYPE_XMIT_FAILED; + goto fail; + } + + /* Switch line back to read */ + s->hardware_switch(AX12_STATE_READ); + + IRQ_UNLOCK(flags); + +#ifdef CONFIG_MODULE_SCHEDULER + scheduler_enable_restore(scheduler_prio); +#endif + return 0; + + fail: + /* Switch line back to read */ + s->hardware_switch(AX12_STATE_READ); +#ifdef CONFIG_MODULE_SCHEDULER + scheduler_enable_restore(scheduler_prio); +#endif + return err; +} + +/* Receive a packet from ax12. Return 0 on sucess. */ +uint8_t AX12_recv(AX12 *s, AX12_Packet *packet) +{ + int16_t c; + uint8_t length; + uint8_t i; + + /* Switch line to read */ + s->hardware_switch(AX12_STATE_READ); + + c = s->hardware_recv(); + if (c == -1) + return AX12_ERROR_TYPE_NO_ANSWER; + if (c != 0xFF) + return AX12_ERROR_TYPE_INVALID_PACKET; + + c = s->hardware_recv(); + if (c == -1) + return AX12_ERROR_TYPE_TIMEOUT; + if (c != 0xFF) + return AX12_ERROR_TYPE_INVALID_PACKET; + + c = s->hardware_recv(); + if (c == -1) + return AX12_ERROR_TYPE_TIMEOUT; + packet->id = c; /* we should check id ? */ + + c = s->hardware_recv(); + if (c == -1) + return AX12_ERROR_TYPE_TIMEOUT; + length = c; + packet->nparams = length - 2; + if (packet->nparams > AX12_MAX_PARAMS) + return AX12_ERROR_TYPE_INVALID_PACKET; + + c = s->hardware_recv(); + if (c == -1) + return AX12_ERROR_TYPE_TIMEOUT; + packet->error = c; + if (packet->error) + return packet->error; + + for (i=0; i<(length-2); i++) { + c = s->hardware_recv(); + if (c == -1) + return AX12_ERROR_TYPE_TIMEOUT; + packet->params[i] = c; + } + + /* Checksum */ + c = s->hardware_recv(); + + if (c != AX12_checksum(packet)) + return AX12_ERROR_TYPE_BAD_CKSUM; + + return 0; +} + +/*_________________________________________________________*/ +/*_________________________________________________________*/ + +/* Write a byte to an adress. Return 0 on success. */ +uint8_t AX12_write_byte(AX12 *s, uint8_t id, AX12_ADDRESS address, + uint8_t data) +{ + AX12_Packet p, rp; + uint8_t ret; + + memset(&p, 0, sizeof(p)); + memset(&rp, 0, sizeof(rp)); + + p.id = id; + p.instruction = AX12_WRITE; + p.nparams = 2; + + /* memory address */ + p.params[0] = (uint8_t)address; + + /* value */ + p.params[1] = data; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + /* We talk broadcast, no reply */ + if (p.id == AX12_BROADCAST_ID) + return 0; + + /* recv packet */ + return AX12_recv(s, &rp); +} + +/* Write a word to an adress. Return 0 on success. */ +uint8_t AX12_write_int(AX12 *s, uint8_t id, AX12_ADDRESS address, + uint16_t data) +{ + AX12_Packet p, rp; + uint8_t ret; + + memset(&p, 0, sizeof(p)); + memset(&rp, 0, sizeof(rp)); + + p.id = id; + p.instruction = AX12_WRITE; + p.nparams = 3; + + /* memory address */ + p.params[0] = (uint8_t)address; + + /* value (low) */ + p.params[1] = 0xFF & data; + + /* value (high) */ + p.params[2] = data>>8; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + /* We talk broadcast, no reply */ + if (p.id == AX12_BROADCAST_ID) + return 0; + + /* recv packet */ + return AX12_recv(s, &rp); +} + +/* Read a byte at given adress. On success, fill val and return 0, + * else return error and keep val unmodified. */ +uint8_t AX12_read_byte(AX12 *s, uint8_t id, AX12_ADDRESS address, + uint8_t *val) +{ + AX12_Packet p, rp; + uint8_t ret; + + memset(&p, 0, sizeof(p)); + memset(&rp, 0, sizeof(rp)); + + p.id = id; + p.instruction = AX12_READ; + p.nparams = 2; + + /* memory address */ + p.params[0] = (uint8_t)address; + + /* data length */ + p.params[1] = 1; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + ret = AX12_recv(s, &rp); + if (ret) + return ret; + + *val = rp.params[0]; + return 0; +} + +uint8_t AX12_read_int(AX12 *s, uint8_t id, AX12_ADDRESS address, + uint16_t *val) +{ + AX12_Packet p, rp; + uint8_t ret; + + memset(&p, 0, sizeof(p)); + memset(&rp, 0, sizeof(rp)); + + p.id = id; + p.instruction = AX12_READ; + p.nparams = 2; + + /* memory address */ + p.params[0] = (uint8_t)address; + + /* data length */ + p.params[1] = 2; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + ret = AX12_recv(s, &rp); + if (ret) + return ret; + + *val = rp.params[0] + ((rp.params[1])<<8); + return 0; +} + +/*_________________________________________________________*/ +/*_________________________________________________________*/ + +uint8_t AX12_set_position(AX12 *s,uint8_t id, uint16_t position) +{ + return AX12_write_int(s, id, AA_GOAL_POSITION_L, position); +} + +uint8_t AX12_set_position2(AX12 *s, uint8_t id, uint16_t position, + uint16_t speed) +{ + AX12_Packet p, rp; + uint8_t ret; + + p.id = id; + p.instruction = AX12_WRITE; + p.nparams = 5; + + /* memory address */ + p.params[0] = AA_GOAL_POSITION_L; + /* position */ + p.params[1] = 0xFF & position; + p.params[2] = position>>8; + /* speed */ + p.params[3] = 0xFF & speed; + p.params[4] = speed>>8; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + /* We talk broadcast, no reply */ + if(p.id == AX12_BROADCAST_ID) + return 0; + + /* recv packet */ + return AX12_recv(s, &rp); +} + +uint8_t AX12_set_position3(AX12*s, uint8_t id, uint16_t position, + uint16_t speed, uint16_t torque) +{ + AX12_Packet p, rp; + uint8_t ret; + + p.id = id; + p.instruction = AX12_WRITE; + p.nparams = 7; + + /* memory address */ + p.params[0] = AA_GOAL_POSITION_L; + /* position */ + p.params[1] = 0xFF & position; + p.params[2] = position>>8; + /* speed */ + p.params[3] = 0xFF & speed; + p.params[4] = speed>>8; + /* torque */ + p.params[5] = 0xFF & torque; + p.params[6] = torque>>8; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + /* We talk broadcast, no reply */ + if(p.id == AX12_BROADCAST_ID) + return 0; + + /* recv packet */ + return AX12_recv(s, &rp); +} + +uint8_t AX12_get_position(AX12 *s, uint8_t id, uint16_t *pos) +{ + return AX12_read_int(s, id, AA_PRESENT_POSITION_L, pos); +} + +uint8_t AX12_get_speed(AX12 *s, uint8_t id, uint16_t *speed) +{ + return AX12_read_int(s, id, AA_PRESENT_SPEED_L, speed); +} + +uint8_t AX12_get_load(AX12 *s, uint8_t id, uint16_t *load) +{ + return AX12_read_int(s, id, AA_PRESENT_LOAD_L, load); +} + +uint8_t AX12_ping(AX12 *s, uint8_t id) +{ + AX12_Packet p, rp; + uint8_t ret; + + p.id = id; + p.instruction = AX12_PING; + p.nparams = 0; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + /* We talk broadcast, no reply */ + if(p.id == AX12_BROADCAST_ID) + return 0; + + /* recv packet */ + return AX12_recv(s, &rp); +} + +uint8_t AX12_reset(AX12 *s, uint8_t id) +{ + AX12_Packet p, rp; + uint8_t ret; + + p.id = id; + p.instruction = AX12_RESET; + p.nparams = 0; + + /* send packet */ + ret = AX12_send(s, &p); + if (ret) + return ret; + + /* We talk broadcast, no reply */ + if(p.id == AX12_BROADCAST_ID) + return 0; + + /* recv packet */ + return AX12_recv(s, &rp); +} diff --git a/modules/devices/servo/ax12/ax12.h b/modules/devices/servo/ax12/ax12.h new file mode 100755 index 0000000..7c05602 --- /dev/null +++ b/modules/devices/servo/ax12/ax12.h @@ -0,0 +1,211 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2008) + * JD Brossillon <jean.damien.brossillon@gmail.com> (main job) + * Olivier Matz <zer0@droids-corp.org> (clean-up, fixes) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12.h,v 1.1.4.4 2009-04-07 20:00:57 zer0 Exp $ + * + */ + +/** + * @file ax12.h + * + * @brief This module provides functions for using a Robotis Dynamixel + * AX-12 numeric actuator + * + * @todo + * - Manage the "Status Return Level" + * + * AX12 servos uses a half duplex uart. This means that there is only + * one line that is used for both transmitting and receiving. Refer to + * the AX12 documentation for more informations. + * + * This module doesn't need ATmega's uart, user have to provide + * 3 functions to control the half duplex uart: + * - send char. + * - write char. + * - switch direction + * + * These functions may use (or not) the AVR uart. Have a look to the + * test program in test/ directory for an example. + */ + +#ifndef _AX12_H_ +#define _AX12_H_ + +#include <aversive.h> +#include <stdlib.h> + +#include "ax12_address.h" +#include "ax12_config.h" + +/*__________________________________________*/ + +/* Half duplex uart switch */ +#define AX12_STATE_READ 0 +#define AX12_STATE_WRITE 1 + +/* Error bits */ +#define AX12_ERROR_BIT_VOLTAGE 0 +#define AX12_ERROR_BIT_ANGLE_LIMIT 1 +#define AX12_ERROR_BIT_OVERHEAT 2 +#define AX12_ERROR_BIT_RANGE 3 +#define AX12_ERROR_BIT_CHECKSUM 4 +#define AX12_ERROR_BIT_OVERLOAD 5 +#define AX12_ERROR_BIT_INSTRUCTION 6 + +/* Other error types when bit 7 id 1 */ +#define AX12_ERROR_TYPE_NO_ANSWER 0xff +#define AX12_ERROR_TYPE_TIMEOUT 0xfe +#define AX12_ERROR_TYPE_INVALID_PACKET 0xfd +#define AX12_ERROR_TYPE_XMIT_FAILED 0xfc +#define AX12_ERROR_TYPE_BAD_CKSUM 0xfb + +/* Address (see ax12_address.h) */ +#define AX12_BROADCAST_ID 0xFE + +/* AX-12 instruction set */ +#define AX12_PING 0x01 +#define AX12_READ 0x02 +#define AX12_WRITE 0x03 +#define AX12_REG_WRITE 0x04 +#define AX12_ACTION 0x05 +#define AX12_RESET 0x06 +#define AX12_SYNC_WRITE 0x83 + +/*__________________________________________*/ + +typedef struct AX12 +{ + /* function to send a byte to the serial line. Return 0 on + * success. */ + int8_t (*hardware_send)(uint8_t); + + /* synchronously receive a byte from ax12. Return -1 on + * timeout, or the received byte. */ + int16_t (*hardware_recv)(void); + + /* switch the line state (read or write) */ + void (*hardware_switch)(uint8_t); +} AX12; + +typedef struct AX12_Packet +{ + uint8_t id; + uint8_t instruction; + + /* Size of AX12_Packet.params */ + uint8_t nparams; + uint8_t params[AX12_MAX_PARAMS]; + + /* Used in status packet */ + uint8_t error; + +} AX12_Packet; + +/*___________ Interface ____________*/ + +void AX12_init(AX12 *ax12); + +/*___________ Hardware layer _____________*/ + +/** @brief Set the function called when writing a character. */ +void AX12_set_hardware_send(AX12 *ax12, int8_t(*)(uint8_t)); + +/** @brief Set the function called when reading a character. */ +void AX12_set_hardware_recv(AX12 *ax12, int16_t(*)(void)); + +/** @brief Set the function called when switching line direction */ +void AX12_set_hardware_switch(AX12 *ax12, void(*)(uint8_t)); + +/*___________ Low level layer ____________*/ + +/** @brief Compute AX12 packet checksum */ +uint8_t AX12_checksum(AX12_Packet *packet); + +/** @brief Send a formated AX12 instruction packet. Return 0 on + * on success. */ +uint8_t AX12_send(AX12 *ax12, AX12_Packet *packet); + +/* @brief Receive a formated AX12 status packet. Return 0 on + * on success. */ +uint8_t AX12_recv(AX12 *ax12, AX12_Packet *packet); + +/*___________ Medium level layer _________*/ + +/* + * ////////////////// WARNING ///////////////////////// + * The following functions assume that AX12 always + * answer with a status packet + * (Status Return Level = 0x02 in AX12 EEPROM area) + * ////////////////// WARNING ///////////////////////// + */ + +/** @brief Write byte in AX-12 memory + * @return Error code from AX-12 (0 means okay) */ +uint8_t AX12_write_byte(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint8_t data); + +/** @brief Write integer (2 bytes) in AX-12 memory + * @return Error code from AX-12 (0 means okay) + * + * address : data low + * address+1 : data high + */ +uint8_t AX12_write_int(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t data); + +/** @brief Read byte from AX-12 memory + * @return Error code from AX-12 (0 means okay) */ +uint8_t AX12_read_byte(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint8_t *val); + +/** @brief Write integer (2 bytes) from AX-12 memory + * @return Error code from AX-12 (0 means okay) */ +uint8_t AX12_read_int(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t *val); + +/*___________ High level layer _________*/ + +/** @brief Set AX12 position */ +uint8_t AX12_set_position(AX12 *ax12,uint8_t id, uint16_t position); + +/** @brief Set AX12 position and moving speed */ +uint8_t AX12_set_position2(AX12 *ax12, uint8_t id, uint16_t position, + uint16_t speed); + +/** @brief Set AX12 position, moving speed and torque */ +uint8_t AX12_set_position3(AX12 *ax12, uint8_t id, uint16_t position, + uint16_t speed, uint16_t torque); + +/** @brief Read AX12 position */ +uint8_t AX12_get_position(AX12 *ax12, uint8_t id, uint16_t *pos); + +/** @brief Read AX12 speed */ +uint8_t AX12_get_speed(AX12 *ax12, uint8_t id, uint16_t *speed); + +/** @brief Read AX12 load */ +uint8_t AX12_get_load(AX12 *ax12, uint8_t id, uint16_t *load); + + +/** @brief Ping an AX12 and return error register */ +uint8_t AX12_ping(AX12 *ax12, uint8_t id); + +/** @brief Reset AX12 back to factory settings */ +uint8_t AX12_reset(AX12 *ax12, uint8_t id); + +#endif/*_AX12_H */ diff --git a/modules/devices/servo/ax12/ax12_address.h b/modules/devices/servo/ax12/ax12_address.h new file mode 100755 index 0000000..e89097e --- /dev/null +++ b/modules/devices/servo/ax12/ax12_address.h @@ -0,0 +1,60 @@ +#ifndef _AX12_INSTRUCTIONS_H_ +#define _AX12_INSTRUCTIONS_H_ + +/** @brief AX-12 control table */ +typedef enum _AX12_ADDRESS +{ + AA_MODEL_NUMBER_L = 0x00, + AA_MODEL_NUMBER_H, + AA_FIRMWARE, + AA_ID, + AA_BAUD_RATE, + AA_DELAY_TIME, + AA_CW_ANGLE_LIMIT_L, + AA_CW_ANGLE_LIMIT_H, + AA_CCW_ANGLE_LIMIT_L, + AA_CCW_ANGLE_LIMIT_H, + AA_RESERVED_1, + AA_HIGHEST_LIMIT_TEMP, + AA_LOWEST_LIMIT_VOLTAGE, + AA_HIGHEST_LIMIT_VOLTAGE, + AA_MAX_TORQUE_L, + AA_MAX_TORQUE_H, + AA_STATUS_RETURN_LEVEL, + AA_ALARM_LED, + AA_ALARM_SHUTDOWN, + AA_RESERVED_2, + AA_DOWN_CALIBRATION_L, + AA_DOWN_CALIBRATION_H, + AA_UP_CALIBRATION_L, + AA_UP_CALIBRATION_H, + AA_TORQUE_ENABLE, + AA_LED, + AA_CW_COMPLIANCE_MARGIN, + AA_CCW_COMPLIANCE_MARGIN, + AA_CW_COMPLIANCE_SLOPE, + AA_CCW_COMPLIANCE_SLOPE, + AA_GOAL_POSITION_L, + AA_GOAL_POSITION_H, + AA_MOVING_SPEED_L, + AA_MOVING_SPEED_H, + AA_TORQUE_LIMIT_L, + AA_TORQUE_LIMIT_H, + AA_PRESENT_POSITION_L, + AA_PRESENT_POSITION_H, + AA_PRESENT_SPEED_L, + AA_PRESENT_SPEED_H, + AA_PRESENT_LOAD_L, + AA_PRESENT_LOAD_H, + AA_PRESENT_VOLTAGE, + AA_PRESENT_TEMP, + AA_PRESENT_REGINST, + AA_RESERVED_3, + AA_MOVING, + AA_LOCK, + AA_PUNCH_L, + AA_PUNCH_H + +}AX12_ADDRESS; + +#endif/*_AX12_INSTRUCTIONS_H_*/ diff --git a/modules/devices/servo/ax12/config/CVS/Entries b/modules/devices/servo/ax12/config/CVS/Entries new file mode 100644 index 0000000..dec1c4d --- /dev/null +++ b/modules/devices/servo/ax12/config/CVS/Entries @@ -0,0 +1,2 @@ +/ax12_config.h/1.1.4.3/Fri Dec 26 13:48:37 2008//Tb_zer0 +D diff --git a/modules/devices/servo/ax12/config/CVS/Repository b/modules/devices/servo/ax12/config/CVS/Repository new file mode 100644 index 0000000..1120324 --- /dev/null +++ b/modules/devices/servo/ax12/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo/ax12/config diff --git a/modules/devices/servo/ax12/config/CVS/Root b/modules/devices/servo/ax12/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/ax12/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/ax12/config/CVS/Tag b/modules/devices/servo/ax12/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/ax12/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/ax12/config/CVS/Template b/modules/devices/servo/ax12/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/ax12/config/ax12_config.h b/modules/devices/servo/ax12/config/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/modules/devices/servo/ax12/config/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/modules/devices/servo/ax12/test/.config b/modules/devices/servo/ax12/test/.config new file mode 100644 index 0000000..e72b09f --- /dev/null +++ b/modules/devices/servo/ax12/test/.config @@ -0,0 +1,250 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +CONFIG_MODULE_TIME=y +CONFIG_MODULE_TIME_CREATE_CONFIG=y + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +CONFIG_MODULE_AX12=y +CONFIG_MODULE_AX12_CREATE_CONFIG=y + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/.static/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/servo/ax12/test/CVS/Entries b/modules/devices/servo/ax12/test/CVS/Entries new file mode 100644 index 0000000..633a7e3 --- /dev/null +++ b/modules/devices/servo/ax12/test/CVS/Entries @@ -0,0 +1,12 @@ +/.config/1.1.4.3/Sat Dec 27 16:29:08 2008//Tb_zer0 +/Makefile/1.1.4.2/Sun Oct 26 21:59:28 2008//Tb_zer0 +/ax12_config.h/1.1.4.3/Fri Dec 26 13:48:37 2008//Tb_zer0 +/commands.c/1.1.2.3/Sat Dec 27 16:29:08 2008//Tb_zer0 +/error_config.h/1.1.4.2/Sun Oct 26 21:59:28 2008//Tb_zer0 +/main.c/1.1.4.4/Sat Dec 27 16:29:08 2008//Tb_zer0 +/rdline_config.h/1.1.2.1/Sun Oct 26 21:59:28 2008//Tb_zer0 +/scheduler_config.h/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/time_config.h/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/timer_config.h/1.1.2.1/Sat Dec 27 16:29:08 2008//Tb_zer0 +/uart_config.h/1.1.4.3/Fri Dec 26 14:01:10 2008//Tb_zer0 +D diff --git a/modules/devices/servo/ax12/test/CVS/Repository b/modules/devices/servo/ax12/test/CVS/Repository new file mode 100644 index 0000000..887fcf5 --- /dev/null +++ b/modules/devices/servo/ax12/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo/ax12/test diff --git a/modules/devices/servo/ax12/test/CVS/Root b/modules/devices/servo/ax12/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/ax12/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/ax12/test/CVS/Tag b/modules/devices/servo/ax12/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/ax12/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/ax12/test/CVS/Template b/modules/devices/servo/ax12/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/ax12/test/Makefile b/modules/devices/servo/ax12/test/Makefile new file mode 100755 index 0000000..e6e8f76 --- /dev/null +++ b/modules/devices/servo/ax12/test/Makefile @@ -0,0 +1,22 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../../.. +# VALUE, absolute or relative path : example ../.. # + +# List C source files here. (C dependencies are automatically generated.) +SRC = commands.c $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/servo/ax12/test/ax12_config.h b/modules/devices/servo/ax12/test/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/modules/devices/servo/ax12/test/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/modules/devices/servo/ax12/test/commands.c b/modules/devices/servo/ax12/test/commands.c new file mode 100644 index 0000000..77b6923 --- /dev/null +++ b/modules/devices/servo/ax12/test/commands.c @@ -0,0 +1,395 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.1.2.3 2008-12-27 16:29:08 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <ax12.h> +#include <parse.h> +#include <parse_num.h> +#include <parse_string.h> +#include <uart.h> + + +extern AX12 ax12; + +uint8_t addr_from_string(const char *s) +{ + /* 16 bits */ + if (!strcmp_P(s, PSTR("cw_angle_limit"))) + return AA_CW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("ccw_angle_limit"))) + return AA_CCW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("max_torque"))) + return AA_MAX_TORQUE_L; + if (!strcmp_P(s, PSTR("down_calibration"))) + return AA_DOWN_CALIBRATION_L; + if (!strcmp_P(s, PSTR("up_calibration"))) + return AA_UP_CALIBRATION_L; + if (!strcmp_P(s, PSTR("torque_limit"))) + return AA_TORQUE_LIMIT_L; + if (!strcmp_P(s, PSTR("position"))) + return AA_PRESENT_POSITION_L; + if (!strcmp_P(s, PSTR("speed"))) + return AA_PRESENT_SPEED_L; + if (!strcmp_P(s, PSTR("load"))) + return AA_PRESENT_LOAD_L; + if (!strcmp_P(s, PSTR("moving_speed"))) + return AA_MOVING_SPEED_L; + if (!strcmp_P(s, PSTR("model"))) + return AA_MODEL_NUMBER_L; + if (!strcmp_P(s, PSTR("goal_pos"))) + return AA_GOAL_POSITION_L; + if (!strcmp_P(s, PSTR("punch"))) + return AA_PUNCH_L; + + /* 8 bits */ + if (!strcmp_P(s, PSTR("firmware"))) + return AA_FIRMWARE; + if (!strcmp_P(s, PSTR("id"))) + return AA_ID; + if (!strcmp_P(s, PSTR("baudrate"))) + return AA_BAUD_RATE; + if (!strcmp_P(s, PSTR("delay"))) + return AA_DELAY_TIME; + if (!strcmp_P(s, PSTR("high_lim_temp"))) + return AA_HIGHEST_LIMIT_TEMP; + if (!strcmp_P(s, PSTR("low_lim_volt"))) + return AA_LOWEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("high_lim_volt"))) + return AA_HIGHEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("status_return"))) + return AA_STATUS_RETURN_LEVEL; + if (!strcmp_P(s, PSTR("alarm_led"))) + return AA_ALARM_LED; + if (!strcmp_P(s, PSTR("alarm_shutdown"))) + return AA_ALARM_SHUTDOWN; + if (!strcmp_P(s, PSTR("torque_enable"))) + return AA_TORQUE_ENABLE; + if (!strcmp_P(s, PSTR("led"))) + return AA_LED; + if (!strcmp_P(s, PSTR("cw_comp_margin"))) + return AA_CW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("ccw_comp_margin"))) + return AA_CCW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("cw_comp_slope"))) + return AA_CW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("ccw_comp_slope"))) + return AA_CCW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("voltage"))) + return AA_PRESENT_VOLTAGE; + if (!strcmp_P(s, PSTR("temp"))) + return AA_PRESENT_TEMP; + if (!strcmp_P(s, PSTR("reginst"))) + return AA_PRESENT_REGINST; + if (!strcmp_P(s, PSTR("moving"))) + return AA_MOVING; + if (!strcmp_P(s, PSTR("lock"))) + return AA_LOCK; + + return 0; +} + + + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(void * parsed_result, void * data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Test */ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_test is parsed successfully */ +static void cmd_test_parsed(void * parsed_result, void * data) +{ + /* Set some AX12 parameters */ + AX12_write_int(&ax12,0xFE,AA_PUNCH_L,0x20); + AX12_write_int(&ax12,0xFE,AA_TORQUE_LIMIT_L,0x3FF); + AX12_write_int(&ax12,0xFE,AA_MOVING_SPEED_L,0x2FF); + AX12_write_byte(&ax12,0xFE,AA_ALARM_LED,0xEF); + + AX12_set_position(&ax12,0xFE,0x1FF - 0x130); + wait_ms(800); + AX12_set_position(&ax12,0xFE,0x1FF + 0x130); + wait_ms(800); +} + +prog_char str_test_arg0[] = "test"; +parse_pgm_token_string_t cmd_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_test_result, arg0, str_test_arg0); + +prog_char help_test[] = "Test func"; +parse_pgm_inst_t cmd_test = { + .f = cmd_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_test_arg0, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_baudrate_result { + fixed_string_t arg0; + uint32_t arg1; +}; + +/* function called when cmd_baudrate is parsed successfully */ +static void cmd_baudrate_parsed(void * parsed_result, void * data) +{ + struct cmd_baudrate_result *res = parsed_result; + struct uart_config c; + + uart_getconf(1, &c); + c.baudrate = res->arg1; + uart_setconf(1, &c); + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); +} + +prog_char str_baudrate_arg0[] = "baudrate"; +parse_pgm_token_string_t cmd_baudrate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0, str_baudrate_arg0); +parse_pgm_token_num_t cmd_baudrate_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1, UINT32); + +prog_char help_baudrate[] = "Change ax12 baudrate"; +parse_pgm_inst_t cmd_baudrate = { + .f = cmd_baudrate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_baudrate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_baudrate_arg0, + (prog_void *)&cmd_baudrate_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Uint16 */ + + +/* this structure is filled when cmd_uint16_read is parsed successfully */ +struct cmd_uint16_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint16_t val; +}; + +/* function called when cmd_uint16_read is parsed successfully */ +static void cmd_uint16_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint16_t val; + uint8_t addr = addr_from_string(res->arg1); + ret = AX12_read_int(&ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.4x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint16_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint16_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0); +prog_char str_uint16_arg1[] = "moving_speed#model#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#down_calibration#up_calibration#torque_limit#" + "position#speed#load#punch"; +parse_pgm_token_string_t cmd_uint16_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1); +parse_pgm_token_num_t cmd_uint16_num = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, num, UINT8); + +prog_char help_uint16_read[] = "Read uint16 value (type, num)"; +parse_pgm_inst_t cmd_uint16_read = { + .f = cmd_uint16_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0, + (prog_void *)&cmd_uint16_arg1, + (prog_void *)&cmd_uint16_num, + NULL, + }, +}; + +/* function called when cmd_uint16_write is parsed successfully */ +static void cmd_uint16_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint8_t addr = addr_from_string(res->arg1); + printf_P(PSTR("writing %s: %d [0x%.4x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_int(&ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint16_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint16_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0_w); +prog_char str_uint16_arg1_w[] = "moving_speed#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#torque_limit#punch"; +parse_pgm_token_string_t cmd_uint16_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1_w); +parse_pgm_token_num_t cmd_uint16_val = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, val, UINT16); + +prog_char help_uint16_write[] = "Write uint16 value (write, num, val)"; +parse_pgm_inst_t cmd_uint16_write = { + .f = cmd_uint16_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0_w, + (prog_void *)&cmd_uint16_arg1_w, + (prog_void *)&cmd_uint16_num, + (prog_void *)&cmd_uint16_val, + NULL, + }, +}; + +/**********************************************************/ +/* Uint8 */ + + +/* this structure is filled when cmd_uint8_read is parsed successfully */ +struct cmd_uint8_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint8_t val; +}; + +/* function called when cmd_uint8_read is parsed successfully */ +static void cmd_uint8_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t ret; + uint8_t val; + uint8_t addr = addr_from_string(res->arg1); + + ret = AX12_read_byte(&ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.2x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint8_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint8_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0); +prog_char str_uint8_arg1[] = "id#firmware#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "voltage#temp#reginst#moving#lock"; +parse_pgm_token_string_t cmd_uint8_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1); +parse_pgm_token_num_t cmd_uint8_num = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, num, UINT8); + +prog_char help_uint8_read[] = "Read uint8 value (type, num)"; +parse_pgm_inst_t cmd_uint8_read = { + .f = cmd_uint8_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0, + (prog_void *)&cmd_uint8_arg1, + (prog_void *)&cmd_uint8_num, + NULL, + }, +}; + +/* function called when cmd_uint8_write is parsed successfully */ +static void cmd_uint8_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t addr = addr_from_string(res->arg1); + uint8_t ret; + printf_P(PSTR("writing %s: %d [0x%.2x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_byte(&ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint8_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint8_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0_w); +prog_char str_uint8_arg1_w[] = "id#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "reginst#lock"; +parse_pgm_token_string_t cmd_uint8_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1_w); +parse_pgm_token_num_t cmd_uint8_val = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, val, UINT8); + +prog_char help_uint8_write[] = "Write uint8 value (write, num, val)"; +parse_pgm_inst_t cmd_uint8_write = { + .f = cmd_uint8_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0_w, + (prog_void *)&cmd_uint8_arg1_w, + (prog_void *)&cmd_uint8_num, + (prog_void *)&cmd_uint8_val, + NULL, + }, +}; + + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_test, + (parse_pgm_inst_t *)&cmd_baudrate, + (parse_pgm_inst_t *)&cmd_uint16_read, + (parse_pgm_inst_t *)&cmd_uint16_write, + (parse_pgm_inst_t *)&cmd_uint8_read, + (parse_pgm_inst_t *)&cmd_uint8_write, + NULL, +}; diff --git a/modules/devices/servo/ax12/test/error_config.h b/modules/devices/servo/ax12/test/error_config.h new file mode 100644 index 0000000..8d1231f --- /dev/null +++ b/modules/devices/servo/ax12/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.4.2 2008-10-26 21:59:28 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/servo/ax12/test/main.c b/modules/devices/servo/ax12/test/main.c new file mode 100755 index 0000000..c58faeb --- /dev/null +++ b/modules/devices/servo/ax12/test/main.c @@ -0,0 +1,243 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.4.4 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/* + * Cmdline interface for AX12. Use the PC to command a daisy-chain of + * AX12 actuators with a nice command line interface. + * + * The circuit should be as following: + * + * |----------| + * | uart0|------->--- PC (baudrate=57600) + * | |-------<--- + * | atmega128| + * | | + * | uart1|---->---+-- AX12 (baudrate 1 000 000) + * | |----<---| + * |----------| + * + * Note that RX and TX pins of UART1 are connected together to provide + * a half-duplex UART emulation. + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <uart.h> +#include <ax12.h> +#include <parse.h> +#include <rdline.h> +#include <scheduler.h> +#include <time.h> +#include <timer.h> + +/* for cmdline interface */ +struct rdline rdl; +char prompt[RDLINE_PROMPT_SIZE]; +extern parse_pgm_ctx_t main_ctx[]; + +/* structure defining the AX12 servo */ +AX12 ax12; + +/******** For cmdline. See in commands.c for the list of commands. */ +static void write_char(char c) +{ + uart_send(0, c); +} + +static void +valid_buffer(const char * buf, uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char * buf, char * dstbuf, uint8_t dstsize, + int16_t * state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + +/********************************* AX12 commands */ + +/* + * --- use uart1 + * + * We use synchronous access (not interrupt driven) to the hardware + * UART, because we have to be sure that the transmission/reception is + * really finished when we return from the functions. + * + * We don't use the CM-5 circuit as described in the AX12 + * documentation, we simply connect TX and RX and use TXEN + RXEN + + * DDR to manage the port directions. + */ + +static volatile uint8_t ax12_state = AX12_STATE_READ; +extern volatile struct cirbuf g_tx_fifo[]; /* uart fifo */ +static volatile uint8_t ax12_nsent = 0; + +/* Called by ax12 module to send a character on serial line. Count the + * number of transmitted bytes. It will be used in ax12_recv_char() to + * drop the bytes that we transmitted. */ +static int8_t ax12_send_char(uint8_t c) +{ + uart_send(1, c); + ax12_nsent++; + return 0; +} + +/* called by uart module when the character has been written in + * UDR. It does not mean that the byte is physically transmitted. */ +static void ax12_send_callback(char c) +{ + if (ax12_state == AX12_STATE_READ) { + /* disable TX when last byte is pushed. */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[1])) + UCSR1B &= ~(1<<TXEN); + } +} + +/* Called by ax12 module when we want to receive a char. Note that we + * also receive the bytes we sent ! So we need to drop them. */ +static int16_t ax12_recv_char(void) +{ + microseconds t = time_get_us2(); + int c; + while (1) { + c = uart_recv_nowait(1); + if (c != -1) { + if (ax12_nsent == 0) + return c; + ax12_nsent --; + } + + /* 50 ms timeout */ + if ((time_get_us2() - t) > 50000) + return -1; + } + return c; +} + +/* called by ax12 module when we want to switch serial line. As we + * work in interruption mode, this function can be called to switch + * back in read mode even if the bytes are not really transmitted on + * the line. That's why in this case we do nothing, we will fall back + * in read mode in any case when xmit is finished -- see in + * ax12_send_callback() -- */ +static void ax12_switch_uart(uint8_t state) +{ + uint8_t flags; + + if (state == AX12_STATE_WRITE) { + IRQ_LOCK(flags); + ax12_nsent=0; + UCSR1B |= (1<<TXEN); + ax12_state = AX12_STATE_WRITE; + IRQ_UNLOCK(flags); + } + else { + IRQ_LOCK(flags); + if (CIRBUF_IS_EMPTY(&g_tx_fifo[1])) + UCSR1B &= ~(1<<TXEN); + ax12_state = AX12_STATE_READ; + IRQ_UNLOCK(flags); + } +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + + cpt++; + + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +/***********************/ + +int main(void) +{ + int c; + const char * history; + int8_t ret; + + wait_ms(1000); + + uart_init(); + + ax12_switch_uart(AX12_STATE_READ); + fdevopen(uart0_dev_send, uart0_dev_recv); + + /* AX12 */ + AX12_init(&ax12); + AX12_set_hardware_send(&ax12, ax12_send_char); + AX12_set_hardware_recv(&ax12, ax12_recv_char); + AX12_set_hardware_switch(&ax12, ax12_switch_uart); + uart_register_tx_event(1, ax12_send_callback); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* SCHEDULER */ + scheduler_init(); + + sei(); + + /* set status return level to 2 and torque to 0 */ + AX12_write_int(&ax12,0xFE, AA_TORQUE_ENABLE, 0x00); + AX12_write_byte(&ax12, 0xFE, AA_STATUS_RETURN_LEVEL, 2); + + rdline_init(&rdl, write_char, valid_buffer, complete_buffer); + snprintf(prompt, sizeof(prompt), "ax12 > "); + rdline_newline(&rdl, prompt); + + /* waiting for commands now... */ + + while (1) { + c = uart_recv_nowait(0); + if (c == -1) + continue; + ret = rdline_char_in(&rdl, c); + if (ret != 2 && ret != 0) { + history = rdline_get_buffer(&rdl); + if (strlen(history) > 1) + rdline_add_history(&rdl, history); + rdline_newline(&rdl, prompt); + } + } + + return 0; +} diff --git a/modules/devices/servo/ax12/test/rdline_config.h b/modules/devices/servo/ax12/test/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/ax12/test/scheduler_config.h b/modules/devices/servo/ax12/test/scheduler_config.h new file mode 100644 index 0000000..a884ee4 --- /dev/null +++ b/modules/devices/servo/ax12/test/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 7 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/modules/devices/servo/ax12/test/time_config.h b/modules/devices/servo/ax12/test/time_config.h new file mode 100644 index 0000000..37ff646 --- /dev/null +++ b/modules/devices/servo/ax12/test/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 25000l diff --git a/modules/devices/servo/ax12/test/timer_config.h b/modules/devices/servo/ax12/test/timer_config.h new file mode 100644 index 0000000..f1b7121 --- /dev/null +++ b/modules/devices/servo/ax12/test/timer_config.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +#define TIMER1_ENABLED +#define TIMER1A_ENABLED +#define TIMER1B_ENABLED +#define TIMER1C_ENABLED + +#define TIMER2_ENABLED + +#define TIMER3_ENABLED +#define TIMER3A_ENABLED +#define TIMER3B_ENABLED +#define TIMER3C_ENABLED + +#define TIMER0_PRESCALER_DIV 1 +#define TIMER1_PRESCALER_DIV 1 +#define TIMER2_PRESCALER_DIV 1 +#define TIMER3_PRESCALER_DIV 1 diff --git a/modules/devices/servo/ax12/test/uart_config.h b/modules/devices/servo/ax12/test/uart_config.h new file mode 100644 index 0000000..c42f3c2 --- /dev/null +++ b/modules/devices/servo/ax12/test/uart_config.h @@ -0,0 +1,104 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.4.3 2008-12-26 14:01:10 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 64 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + +/* + * UART1 definitions + */ + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 250000 +//#define UART1_BAUDRATE 1000000 + + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +//#define UART1_USE_DOUBLE_SPEED 0 +#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 32 +#define UART1_TX_FIFO_SIZE 32 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + + +#endif + diff --git a/modules/devices/servo/multiservo/CVS/Entries b/modules/devices/servo/multiservo/CVS/Entries new file mode 100644 index 0000000..46c98fc --- /dev/null +++ b/modules/devices/servo/multiservo/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/multiservo.c/1.5.4.5/Sun Mar 2 17:18:16 2008//Tb_zer0 +/multiservo.h/1.3.4.3/Wed May 23 17:18:14 2007//Tb_zer0 +/multiservo_archs.h/1.3.4.4/Sun Mar 2 17:18:16 2008//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/devices/servo/multiservo/CVS/Repository b/modules/devices/servo/multiservo/CVS/Repository new file mode 100644 index 0000000..299aabf --- /dev/null +++ b/modules/devices/servo/multiservo/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo/multiservo diff --git a/modules/devices/servo/multiservo/CVS/Root b/modules/devices/servo/multiservo/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/multiservo/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/multiservo/CVS/Tag b/modules/devices/servo/multiservo/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/multiservo/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/multiservo/CVS/Template b/modules/devices/servo/multiservo/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/multiservo/Makefile b/modules/devices/servo/multiservo/Makefile new file mode 100644 index 0000000..501d2a8 --- /dev/null +++ b/modules/devices/servo/multiservo/Makefile @@ -0,0 +1,8 @@ +TARGET = multiservo + +# List C source files here. (C dependencies are automatically generated.) +SRC = multiservo.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/devices/servo/multiservo/config/CVS/Entries b/modules/devices/servo/multiservo/config/CVS/Entries new file mode 100644 index 0000000..30e582c --- /dev/null +++ b/modules/devices/servo/multiservo/config/CVS/Entries @@ -0,0 +1,2 @@ +/multiservo_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +D diff --git a/modules/devices/servo/multiservo/config/CVS/Repository b/modules/devices/servo/multiservo/config/CVS/Repository new file mode 100644 index 0000000..f6e0e3e --- /dev/null +++ b/modules/devices/servo/multiservo/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo/multiservo/config diff --git a/modules/devices/servo/multiservo/config/CVS/Root b/modules/devices/servo/multiservo/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/multiservo/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/multiservo/config/CVS/Tag b/modules/devices/servo/multiservo/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/multiservo/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/multiservo/config/CVS/Template b/modules/devices/servo/multiservo/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/multiservo/config/multiservo_config.h b/modules/devices/servo/multiservo/config/multiservo_config.h new file mode 100644 index 0000000..11ae0e9 --- /dev/null +++ b/modules/devices/servo/multiservo/config/multiservo_config.h @@ -0,0 +1,59 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: multiservo_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + + +#ifndef _MULTISERVO_CONFIG_H_ +#define _MULTISERVO_CONFIG_H_ + +/** we need one timer, can be 0, 1, 2, 3 (depending on arch) */ +#define MULTISERVO_TIMER 1 + +/* You should specify the config for prescaler + * It is in TCCRnB for 16 bits timer or in TCCRn for + * 8 bits timer. See the doc of your AVR device. + * This is not automatic because it would be too complicated. + * + * Example (for timer 3, prescaler 1) : + * + * #define MULTISERVO_TIMER_PRESCALER 1 + * #define MULTISERVO_TIMER_PRESCALER_CONFIG (1 << CS30) + * + * Another example (for timer 2, prescaler 32) : + * + * #define MULTISERVO_TIMER_PRESCALER 128 + * #define MULTISERVO_TIMER_PRESCALER_CONFIG ((1 << CS22) | (1 << CS20)) + * + * XXX : currently, the user has to choose a good prescaler + * value. A good prescaler value is the more precise value + * (the highest) that can count during 2 ms. + */ +/* ok for atm 128 */ +/* #define MULTISERVO_TIMER_PRESCALER 256 */ +/* #define MULTISERVO_TIMER_PRESCALER_CONFIG (1 << CS22) */ + +#define MULTISERVO_TIMER_PRESCALER 256 +#define MULTISERVO_TIMER_PRESCALER_CONFIG (1 << CS22) +/* #define MULTISERVO_TIMER_PRESCALER 1 */ +/* #define MULTISERVO_TIMER_PRESCALER_CONFIG (1 << CS10) */ + +#define MULTISERVO_NB_MAX 4 + +#endif diff --git a/modules/devices/servo/multiservo/multiservo.c b/modules/devices/servo/multiservo/multiservo.c new file mode 100644 index 0000000..43015bb --- /dev/null +++ b/modules/devices/servo/multiservo/multiservo.c @@ -0,0 +1,181 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: multiservo.c,v 1.5.4.5 2008-03-02 17:18:16 zer0 Exp $ + * + */ + +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> +#include <multiservo.h> +#include <multiservo_archs.h> + +struct multiservo g_multiservo; + +//#define MULTISERVO_ENABLE_DEBUG + +#ifdef MULTISERVO_ENABLE_DEBUG +#define MULTISERVO_DEBUG(args...) DEBUG(args) +#else +#define MULTISERVO_DEBUG(args...) do { } while(0) +#endif + +/* value of timer for 1 ms */ +#define TIME_1MS (CONFIG_QUARTZ/((1000UL)*MULTISERVO_TIMER_PRESCALER)) +#define TIME_1_5MS ((TIME_1MS*3)/2) + +/* for timers 8 bits, check that 2ms value (max) is < 256 */ +#if (MULTISERVO_TIMER == 0 || MULTISERVO_TIMER == 2) && ((TIME_1MS*2) >= 256L) +#error "Bad PRESCALER, you should increase it in multiservo_config.h" +#endif + +/* for timers 16 bits, check that 2ms value (max) is < 65536 */ +#if (MULTISERVO_TIMER == 1 || MULTISERVO_TIMER == 3) && ((TIME_1MS*2) >= 65536L) +#error "Bad PRESCALER, you should increase it in multiservo_config.h" +#endif + + + +SIGNAL(MULTISERVO_SIG_OUTPUT_COMPARE) /* other ints NOT allowed */ +{ + volatile uint8_t * port ; + + if (g_multiservo.time_sum > TIME_1MS * 20) { + MULTISERVO_DEBUG(E_MULTISERVO, "end, restart"); + g_multiservo.time_sum = 0; + g_multiservo.current_multiservo = 0; + } + + /* reset pin */ + if (g_multiservo.id_prev != -1) { + port = g_multiservo.elts[g_multiservo.id_prev].port; + if(port) { + MULTISERVO_DEBUG(E_MULTISERVO, "reset %d",g_multiservo.id_prev); + cbi(*port, g_multiservo.elts[g_multiservo.id_prev].bitnum); + } + } + + /* set pin */ + while (g_multiservo.current_multiservo < MULTISERVO_NB_MAX) { + port = g_multiservo.elts[g_multiservo.current_multiservo].port; + if(port) { + MULTISERVO_DEBUG(E_MULTISERVO, "set %d %d", + g_multiservo.current_multiservo, + g_multiservo.elts[g_multiservo.current_multiservo].value); + sbi(*port, g_multiservo.elts[g_multiservo.current_multiservo].bitnum); + g_multiservo.id_prev = g_multiservo.current_multiservo; + MULTISERVO_OCR = g_multiservo.elts[g_multiservo.current_multiservo].value; + g_multiservo.time_sum += g_multiservo.elts[g_multiservo.current_multiservo].value; + break; + } + g_multiservo.current_multiservo ++; + } + + /* wait until 20ms is reached */ + if (g_multiservo.current_multiservo >= MULTISERVO_NB_MAX) { + g_multiservo.id_prev = -1; + MULTISERVO_DEBUG(E_MULTISERVO, "wait 1ms %d (%ld)", g_multiservo.current_multiservo, TIME_1MS); + MULTISERVO_OCR = TIME_1MS; + g_multiservo.time_sum += TIME_1MS; + } + else { + g_multiservo.current_multiservo ++; + } +} + + + +void multiservo_init(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + + cbi(MULTISERVO_TIMSK, MULTISERVO_OCIE); + + memset(&g_multiservo, 0, sizeof(g_multiservo)); + g_multiservo.id_prev = -1; + + /* Timer config (see in multiservo_archs.h) */ + MULTISERVO_TCCRnA = MULTISERVO_TCCRnA_VALUE; +#ifdef MULTISERVO_TCCRnB + MULTISERVO_TCCRnB = MULTISERVO_TCCRnB_VALUE; +#endif + + MULTISERVO_OCR = TIME_1MS; + sbi(MULTISERVO_TIMSK, MULTISERVO_OCIE); + IRQ_UNLOCK(flags); +} + + +int8_t multiservo_add(volatile uint8_t * port, uint8_t bitnum) +{ + uint8_t i; + uint8_t flags; + + IRQ_LOCK(flags); + /* find a place and add it */ + for ( i=0 ; i< MULTISERVO_NB_MAX ; i++ ) { + if(! g_multiservo.elts[i].port) { + g_multiservo.elts[i].port = port; + g_multiservo.elts[i].bitnum = bitnum; + g_multiservo.elts[i].value = TIME_1_5MS; /* dummy (center multiservo) */ + sbi(DDR(*port), bitnum); /* DDR */ + break; + } + } + IRQ_UNLOCK(flags); + + /* if found, return id, else -1 */ + if(i == MULTISERVO_NB_MAX) + return -1; + + return i; +} + + + + +void multiservo_del(int8_t id) +{ + uint8_t flags; + + IRQ_LOCK(flags); + cbi(DDR(*g_multiservo.elts[id].port), g_multiservo.elts[id].bitnum); /* DDR */ + memset(&g_multiservo.elts[id], 0, sizeof(struct multiservo_element)); + IRQ_UNLOCK(flags); +} + + +/** + * Set multiservo angle. Specify value in us. + * WARNING : should be (much) bigger than 0 + */ +void multiservo_set(int8_t id, uint16_t val_us) +{ + uint16_t val_timer; + uint8_t flags; + + val_timer = (((uint32_t)val_us)*TIME_1MS)/1000; + IRQ_LOCK(flags); + /* XXX convert us to counter unit */ + g_multiservo.elts[id].value = val_timer; + IRQ_UNLOCK(flags); +} + diff --git a/modules/devices/servo/multiservo/multiservo.h b/modules/devices/servo/multiservo/multiservo.h new file mode 100644 index 0000000..76783f2 --- /dev/null +++ b/modules/devices/servo/multiservo/multiservo.h @@ -0,0 +1,55 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: multiservo.h,v 1.3.4.3 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#ifndef _MULTISERVO__H_ +#define _MULTISERVO__H_ + +#include <aversive.h> +#include <multiservo_config.h> + + +struct multiservo_element { + volatile uint8_t * port; + uint8_t bitnum; + uint16_t value; +}; + +struct multiservo { + uint32_t time_sum; + uint16_t current_multiservo; + int8_t id_prev; + struct multiservo_element elts[MULTISERVO_NB_MAX]; +}; + +extern struct multiservo g_multiservo; + + + +void multiservo_init(void); + +int8_t multiservo_add(volatile uint8_t * port, uint8_t bitnum); + +void multiservo_del(int8_t id); + +void multiservo_set(int8_t id, uint16_t val); + + +#endif diff --git a/modules/devices/servo/multiservo/multiservo_archs.h b/modules/devices/servo/multiservo/multiservo_archs.h new file mode 100644 index 0000000..c7900bb --- /dev/null +++ b/modules/devices/servo/multiservo/multiservo_archs.h @@ -0,0 +1,147 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: multiservo_archs.h,v 1.3.4.4 2008-03-02 17:18:16 zer0 Exp $ + * + */ + +/* set in CTC mode */ + +#ifndef _MULTISERVO_ARCHS_H_ +#define _MULTISERVO_ARCHS_H_ + +#include <aversive.h> + +/* will be in aversive_timers */ +#if defined (__AVR_ATmega128__) + +#if MULTISERVO_TIMER == 0 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE0 +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE0 +#define MULTISERVO_TCCRnA TCCR0 +#define MULTISERVO_TCCRnA_VALUE ((1 << WGM01) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR0 + +#elif MULTISERVO_TIMER == 1 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE1A +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE1A +#define MULTISERVO_TCCRnA TCCR1A +#define MULTISERVO_TCCRnA_VALUE 0 +#define MULTISERVO_TCCRnB TCCR1B +#define MULTISERVO_TCCRnB_VALUE ((1 << WGM12) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR1A + +#elif MULTISERVO_TIMER == 2 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE2 +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE2 +#define MULTISERVO_TCCRnA TCCR2 +#define MULTISERVO_TCCRnA_VALUE ((1 << WGM21) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR2 + +#elif MULTISERVO_TIMER == 3 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE3A +#define MULTISERVO_TIMSK ETIMSK +#define MULTISERVO_OCIE OCIE3A +#define MULTISERVO_TCCRnA TCCR3A +#define MULTISERVO_TCCRnA_VALUE 0 +#define MULTISERVO_TCCRnB TCCR3B +#define MULTISERVO_TCCRnB_VALUE ((1 << WGM32) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR3A + +#else +#error "Bad timer number, check your multiservo_config.h" +#endif + + + + + +#elif defined (__AVR_ATmega32__) + +#if MULTISERVO_TIMER == 0 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE0 +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE0 +#define MULTISERVO_TCCRnA TCCR0 +#define MULTISERVO_TCCRnA_VALUE ((1 << WGM01) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR0 + +#elif MULTISERVO_TIMER == 1 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE1A +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE1A +#define MULTISERVO_TCCRnA TCCR1A +#define MULTISERVO_TCCRnA_VALUE 0 +#define MULTISERVO_TCCRnB TCCR1B +#define MULTISERVO_TCCRnB_VALUE ((1 << WGM12) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR1A + +#elif MULTISERVO_TIMER == 2 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE2 +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE2 +#define MULTISERVO_TCCRnA TCCR2 +#define MULTISERVO_TCCRnA_VALUE ((1 << WGM21) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR2 + +#else +#error "Bad timer number, check your multiservo_config.h" +#endif + +#elif defined (__AVR_ATtiny2313__) + +#if MULTISERVO_TIMER == 0 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE0 +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE0 +#define MULTISERVO_TCCRnA TCCR0A +#define MULTISERVO_TCCRnA_VALUE (1 << WGM01) +#define MULTISERVO_TCCRnA TCCR0B +#define MULTISERVO_TCCRnA_VALUE (MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR0 + +#elif MULTISERVO_TIMER == 1 +#define MULTISERVO_SIG_OUTPUT_COMPARE SIG_OUTPUT_COMPARE1A +#define MULTISERVO_TIMSK TIMSK +#define MULTISERVO_OCIE OCIE1A +#define MULTISERVO_TCCRnA TCCR1A +#define MULTISERVO_TCCRnA_VALUE 0 +#define MULTISERVO_TCCRnB TCCR1B +#define MULTISERVO_TCCRnB_VALUE ((1 << WGM12) | MULTISERVO_TIMER_PRESCALER_CONFIG) +#define MULTISERVO_OCR OCR1A + +#else +#error "Bad timer number, check your multiservo_config.h" +#endif + + + +/* #elif XYZ */ + +/* Add other archs here */ + +#else + +#error "This MCU is not supported, see in multiservo_archs.h" + +#endif /* MCU CHOICE */ + + +#endif /* _MULTISERVO_ARCHS_H_ */ diff --git a/modules/devices/servo/multiservo/test/.config b/modules/devices/servo/multiservo/test/.config new file mode 100644 index 0000000..6998ebe --- /dev/null +++ b/modules/devices/servo/multiservo/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +CONFIG_MCU_ATMEGA32=y +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +CONFIG_MODULE_MULTISERVO=y +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/devices/servo/multiservo/test/CVS/Entries b/modules/devices/servo/multiservo/test/CVS/Entries new file mode 100644 index 0000000..cec0fba --- /dev/null +++ b/modules/devices/servo/multiservo/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.6.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/error_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/main.c/1.4.4.2/Wed May 23 17:18:14 2007//Tb_zer0 +/multiservo_config.h/1.3.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/uart_config.h/1.2.6.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +D diff --git a/modules/devices/servo/multiservo/test/CVS/Repository b/modules/devices/servo/multiservo/test/CVS/Repository new file mode 100644 index 0000000..627e43c --- /dev/null +++ b/modules/devices/servo/multiservo/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/devices/servo/multiservo/test diff --git a/modules/devices/servo/multiservo/test/CVS/Root b/modules/devices/servo/multiservo/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/devices/servo/multiservo/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/devices/servo/multiservo/test/CVS/Tag b/modules/devices/servo/multiservo/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/devices/servo/multiservo/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/devices/servo/multiservo/test/CVS/Template b/modules/devices/servo/multiservo/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/devices/servo/multiservo/test/Makefile b/modules/devices/servo/multiservo/test/Makefile new file mode 100644 index 0000000..8e56dbc --- /dev/null +++ b/modules/devices/servo/multiservo/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/devices/servo/multiservo/test/error_config.h b/modules/devices/servo/multiservo/test/error_config.h new file mode 100644 index 0000000..1de36e9 --- /dev/null +++ b/modules/devices/servo/multiservo/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/devices/servo/multiservo/test/main.c b/modules/devices/servo/multiservo/test/main.c new file mode 100644 index 0000000..9264d6e --- /dev/null +++ b/modules/devices/servo/multiservo/test/main.c @@ -0,0 +1,64 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4.4.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdio.h> + +#include <aversive/error.h> +#include <uart.h> +#include <aversive/wait.h> +#include <multiservo.h> + + +void mylog(struct error * e, ...) +{ + va_list ap; + + va_start(ap, e); + printf_P(PSTR("[%d]: E%d "), e->severity, e->err_num); + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR("\n")); + va_end(ap); +} + +int main(void) +{ +#ifndef HOST_VERSION + /* uart stuff */ + uart_init(); + fdevopen(uart0_dev_send,NULL); +#endif + + error_register_debug(mylog); + printf_P("hello !!\n"); + + multiservo_init(); + multiservo_add(&PORTC, 7); /* return id 0 (atm32) */ + // multiservo_add(&PORTF, 0); /* return id 0 (atm 128) */ + sei(); + while(1) { + multiservo_set(0, 1200); + wait_ms(1000); + multiservo_set(0, 1800); + wait_ms(1000); + } + return 0; +} + diff --git a/modules/devices/servo/multiservo/test/multiservo_config.h b/modules/devices/servo/multiservo/test/multiservo_config.h new file mode 100644 index 0000000..2dab1d0 --- /dev/null +++ b/modules/devices/servo/multiservo/test/multiservo_config.h @@ -0,0 +1,55 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: multiservo_config.h,v 1.3.4.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + + +#ifndef _MULTISERVO_CONFIG_H_ +#define _MULTISERVO_CONFIG_H_ + +/** we need one timer, can be 0, 1, 2, 3 (depending on arch) */ +#define MULTISERVO_TIMER 2 + +/* You should specify the config for prescaler + * It is in TCCRnB for 16 bits timer or in TCCRn for + * 8 bits timer. See the doc of your AVR device. + * This is not automatic because it would be too complicated. + * + * Example (for timer 3, prescaler 1) : + * + * #define MULTISERVO_TIMER_PRESCALER 1 + * #define MULTISERVO_TIMER_PRESCALER_CONFIG (1 << CS30) + * + * Another example (for timer 2, prescaler 32) : + * + * #define MULTISERVO_TIMER_PRESCALER 128 + * #define MULTISERVO_TIMER_PRESCALER_CONFIG ((1 << CS22) | (1 << CS20)) + * + * XXX : currently, the user has to choose a good prescaler + * value. A good prescaler value is the more precise value + * (the highest) that can count during 2 ms. + */ + +/* this is ok for atm 32... */ +#define MULTISERVO_TIMER_PRESCALER 256 +#define MULTISERVO_TIMER_PRESCALER_CONFIG ((1 << CS22) | (1 << CS21)) + +#define MULTISERVO_NB_MAX 4 + +#endif diff --git a/modules/devices/servo/multiservo/test/uart_config.h b/modules/devices/servo/multiservo/test/uart_config.h new file mode 100644 index 0000000..df6c894 --- /dev/null +++ b/modules/devices/servo/multiservo/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.6.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/encoding/CVS/Entries b/modules/encoding/CVS/Entries new file mode 100644 index 0000000..02464c7 --- /dev/null +++ b/modules/encoding/CVS/Entries @@ -0,0 +1,2 @@ +D/base64//// +D/hamming//// diff --git a/modules/encoding/CVS/Repository b/modules/encoding/CVS/Repository new file mode 100644 index 0000000..4d456c1 --- /dev/null +++ b/modules/encoding/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/encoding diff --git a/modules/encoding/CVS/Root b/modules/encoding/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/encoding/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/encoding/CVS/Tag b/modules/encoding/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/encoding/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/encoding/CVS/Template b/modules/encoding/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/encoding/base64/CVS/Entries b/modules/encoding/base64/CVS/Entries new file mode 100644 index 0000000..791ec1f --- /dev/null +++ b/modules/encoding/base64/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/base64.c/1.2.4.3/Sun Mar 15 21:37:55 2009//Tb_zer0 +/base64.h/1.2.4.2/Wed May 23 17:18:14 2007//Tb_zer0 +D/test//// diff --git a/modules/encoding/base64/CVS/Repository b/modules/encoding/base64/CVS/Repository new file mode 100644 index 0000000..13dbac2 --- /dev/null +++ b/modules/encoding/base64/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/encoding/base64 diff --git a/modules/encoding/base64/CVS/Root b/modules/encoding/base64/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/encoding/base64/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/encoding/base64/CVS/Tag b/modules/encoding/base64/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/encoding/base64/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/encoding/base64/CVS/Template b/modules/encoding/base64/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/encoding/base64/Makefile b/modules/encoding/base64/Makefile new file mode 100644 index 0000000..278da54 --- /dev/null +++ b/modules/encoding/base64/Makefile @@ -0,0 +1,10 @@ +-include .config + +TARGET = base64 + +# List C source files here. (C dependencies are automatically generated.) +SRC = base64.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/encoding/base64/base64.c b/modules/encoding/base64/base64.c new file mode 100644 index 0000000..edb5aad --- /dev/null +++ b/modules/encoding/base64/base64.c @@ -0,0 +1,127 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: base64.c,v 1.2.4.3 2009-03-15 21:37:55 zer0 Exp $ + * + */ + +#include <string.h> + +char my_base64[]="ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + +/* return -1 if out buffer is too small */ +/* else return number of written bytes in out buffer */ +int base64_to_raw(char * in, int len_in, char * out, int len_out) +{ + int n_in; + int counter=0; + int n_out=0; + char* c; + unsigned int buf=0; + for (n_in=0 ; n_in<len_in && n_out<len_out ; n_in++) { + /* this is the end as it is padding */ + if (in[n_in] == '=') + break; + + c = strchr(my_base64, in[n_in]); + + /* ignore bad chars */ + if (c == NULL) + continue; + + buf <<= 6; + buf += (int)(c-my_base64); + counter+=6; + + if (counter < 8) + continue; + + if (n_out >= len_out) + return -1; + + out[n_out++] = (buf>>(counter-8)) & 0xFF; + counter -= 8; + } + + /* no padding at the end, ok */ + if (counter == 0 && (n_in+1 >= len_in || in[n_in] != '=')) { + return n_out; + } + + /* one '=' padding, ok */ + if (counter == 2 && (in[n_in] == '=') && + (n_in+1 >= len_in || in[n_in] != '=')) { + return n_out; + } + + /* two '=' padding, ok */ + if (counter == 4 && (in[n_in] == '=') && + n_in+1 < len_in && in[n_in+1] == '=') { + return n_out; + } + + /* bad padding */ + return -1; +} + + +/* return -1 if out buffer is too small */ +/* else return number of written bytes in out buffer */ +int raw_to_base64(char *in, int len_in, char * out, int len_out) +{ + int n_in; + int counter=0; + int n_out=0; + unsigned int buf=0; + + for (n_in=0 ; n_in<len_in && n_out<len_out ; n_in++) { + buf <<= 8; + buf += (unsigned char)(in[n_in]); + counter+=8; + + while(counter>=6) { + if (n_out>=len_out) + return -1; + out[n_out++] = my_base64[(buf>>(counter-6)) & 0x3F]; + counter-=6; + } + } + + /* should we add padding ? */ + if (counter) { + if (n_out >= len_out) + return -1; + + out[n_out++] = my_base64[(buf<<(6-counter)) & 0x3F]; + + if (n_out >= len_out) + return -1; + + /* one '=' if counter==4 (counter can be 4 or 2) */ + out[n_out++] = '='; + + if (n_out >= len_out) + return -1; + + /* two '=' if cpt==2 */ + if (counter==2) { + out[n_out++] = '='; + } + } + + return n_out; +} diff --git a/modules/encoding/base64/base64.h b/modules/encoding/base64/base64.h new file mode 100644 index 0000000..59fb1aa --- /dev/null +++ b/modules/encoding/base64/base64.h @@ -0,0 +1,28 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: base64.h,v 1.2.4.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#ifndef BASE64_H +#define BASE64_H + +int base64_to_raw(char * in, int len_in, char * out, int len_out); +int raw_to_base64(char *in, int len_in, char * out, int len_out); + +#endif diff --git a/modules/encoding/base64/test/.config b/modules/encoding/base64/test/.config new file mode 100644 index 0000000..e95d7c3 --- /dev/null +++ b/modules/encoding/base64/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +CONFIG_MODULE_BASE64=y +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/encoding/base64/test/CVS/Entries b/modules/encoding/base64/test/CVS/Entries new file mode 100644 index 0000000..7ab88b5 --- /dev/null +++ b/modules/encoding/base64/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.2.4.8/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/error_config.h/1.1.4.2/Wed May 23 17:18:14 2007//Tb_zer0 +/main.c/1.2.4.2/Wed May 23 17:18:14 2007//Tb_zer0 +/uart_config.h/1.1.4.2/Wed May 23 17:18:14 2007//Tb_zer0 +D diff --git a/modules/encoding/base64/test/CVS/Repository b/modules/encoding/base64/test/CVS/Repository new file mode 100644 index 0000000..7f7e2a0 --- /dev/null +++ b/modules/encoding/base64/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/encoding/base64/test diff --git a/modules/encoding/base64/test/CVS/Root b/modules/encoding/base64/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/encoding/base64/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/encoding/base64/test/CVS/Tag b/modules/encoding/base64/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/encoding/base64/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/encoding/base64/test/CVS/Template b/modules/encoding/base64/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/encoding/base64/test/Makefile b/modules/encoding/base64/test/Makefile new file mode 100644 index 0000000..ed79efe --- /dev/null +++ b/modules/encoding/base64/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/encoding/base64/test/error_config.h b/modules/encoding/base64/test/error_config.h new file mode 100644 index 0000000..d9fc446 --- /dev/null +++ b/modules/encoding/base64/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.4.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/encoding/base64/test/main.c b/modules/encoding/base64/test/main.c new file mode 100644 index 0000000..f2ac4f4 --- /dev/null +++ b/modules/encoding/base64/test/main.c @@ -0,0 +1,64 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2.4.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <uart.h> +#include <aversive.h> +#include <aversive/wait.h> + +#include <base64.h> + +int main(void) +{ + /* Text content "Man" */ + /* ASCII 77 97 110 */ + /* Bit pattern /8 01001101 01100001 01101110 */ + /* Bit pattern /6 010011 010110 000101 101110 */ + /* Index 19 22 5 46 */ + /* Base64-Encoded "TWFu" */ + char *toto = "Input ends with carnal pleasure."; + char test1[256], test2[256]; + int ret; + +#ifndef HOST_VERSION + /* UART */ + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + + sei(); +#endif + + ret = raw_to_base64(toto, strlen(toto), test1, 256); + printf("%d\n", ret); + test1[ret]=0; + printf("%s\n", test1); + memset(test2, 0, 256); + ret = base64_to_raw(test1, ret, test2, 255); + printf("%s\n", test2); + + while(1); + + return 0; +} diff --git a/modules/encoding/base64/test/uart_config.h b/modules/encoding/base64/test/uart_config.h new file mode 100644 index 0000000..3bffcf6 --- /dev/null +++ b/modules/encoding/base64/test/uart_config.h @@ -0,0 +1,114 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.4.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + + + + +/* + * UART1 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 0 +//#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 4 +#define UART1_TX_FIFO_SIZE 16 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + + + +#endif + diff --git a/modules/encoding/hamming/CVS/Entries b/modules/encoding/hamming/CVS/Entries new file mode 100644 index 0000000..92af2a9 --- /dev/null +++ b/modules/encoding/hamming/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/hamming.c/1.2.4.4/Sun May 11 15:04:53 2008//Tb_zer0 +/hamming.h/1.2.4.2/Sun Aug 19 10:39:31 2007//Tb_zer0 +D/test//// diff --git a/modules/encoding/hamming/CVS/Repository b/modules/encoding/hamming/CVS/Repository new file mode 100644 index 0000000..4dc0ea1 --- /dev/null +++ b/modules/encoding/hamming/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/encoding/hamming diff --git a/modules/encoding/hamming/CVS/Root b/modules/encoding/hamming/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/encoding/hamming/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/encoding/hamming/CVS/Tag b/modules/encoding/hamming/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/encoding/hamming/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/encoding/hamming/CVS/Template b/modules/encoding/hamming/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/encoding/hamming/Makefile b/modules/encoding/hamming/Makefile new file mode 100644 index 0000000..fbfefed --- /dev/null +++ b/modules/encoding/hamming/Makefile @@ -0,0 +1,8 @@ +TARGET = hamming + +# List C source files here. (C dependencies are automatically generated.) +SRC = hamming.c + +########################################### + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/encoding/hamming/hamming.c b/modules/encoding/hamming/hamming.c new file mode 100644 index 0000000..6670677 --- /dev/null +++ b/modules/encoding/hamming/hamming.c @@ -0,0 +1,322 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: hamming.c,v 1.2.4.4 2008-05-11 15:04:53 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Implementation for HAMMING + * + * Thanks and hello to Serpilliere + */ + +/** \file hamming.c + * \brief Implementation for the Hamiing module. + * + * \todo use progmem to store tables ! + * + * \test Seems to work + * + * This module provides functions for error detection/correction + */ + +/**********************************************************/ + +#include <aversive.h> + +#define P_MASK 0x0000808B + +#define P0_MASK 0x15555554 +#define P1_MASK 0x06666664 +#define P2_MASK 0x18787870 +#define P3_MASK 0x1F807F00 +#define P4_MASK 0x1FFF0000 + +#define P0_EMPL 0 +#define P1_EMPL 1 +#define P2_EMPL 3 +#define P3_EMPL 7 +#define P4_EMPL 15 + +uint8_t tab_abcd[16]= + { + 0, + 4, + 16, + 20, + 32, + 36, + 48, + 52, + 64, + 68, + 80, + 84, + 96, + 100, + 112, + 116 + }; + +uint8_t tab_dcba[32]= + { + 0, + 1, + 0, + 1, + 2, + 3, + 2, + 3, + 4, + 5, + 4, + 5, + 6, + 7, + 6, + 7, + 8, + 9, + 8, + 9, + 10, + 11, + 10, + 11, + 12, + 13, + 12, + 13, + 14, + 15, + 14, + 15 + }; + +uint8_t tab_parity[256] = + { + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 + }; + +/*******************************************************/ + +uint32_t hamming_expand(uint32_t frame) +{ + uint32_t tmp; + + uint16_t frame_middle; // octet 2 & 3 + uint8_t frame_last; // octet 3 + + tmp = tab_abcd[(uint8_t)frame&0x0F]; + + tmp |= (frame & 0x7F0) << 4; + + frame_middle = extr32_16_mid(frame); + tmp |= (uint32_t)(frame_middle & 0x7F8) << 13; + + + frame_last = extr32_08_2(frame); + tmp |= (uint32_t)(frame_last >> 3) << 24 ; + + return tmp; +} + +/*******************************************************/ + +uint32_t hamming_shrink(uint32_t frame) +{ + uint32_t ret; + uint8_t tmp; + + ret = tab_dcba[ (((uint8_t)frame) >> 2) & 0x1F ]; + + tmp = * ((uint8_t *)(&frame) + 1); + ret += (uint16_t)(tmp&0x7F) << 4; + + tmp = * ((uint8_t *)(&frame) + 2); + ret += (uint32_t)tmp << 11; + + tmp = * ((uint8_t *)(&frame) + 3); + ret += (uint32_t)(tmp&0x1F) << 19; + + return ret; +} + +/*******************************************************/ + +uint32_t hamming_process(uint32_t frame) +{ + uint32_t tmp; + uint8_t xor; + + tmp = frame&P0_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if(tab_parity[xor]) + frame |= (1l<<P0_EMPL); + + tmp = frame&P1_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if(tab_parity[xor]) + frame |= (1l<<P1_EMPL); + + tmp = frame&P2_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if(tab_parity[xor]) + frame |= (1l<<P2_EMPL); + + tmp = frame&P3_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if(tab_parity[xor]) + frame |= (1l<<P3_EMPL); + + tmp = frame&P4_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if(tab_parity[xor]) + frame |= (1l<<P4_EMPL); + + return frame; +} + +/*******************************************************/ + +uint8_t hamming_unprocess(uint32_t frame) +{ + uint32_t tmp; + uint8_t xor; + uint8_t indice=0; + + tmp = frame&P0_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if((1l<<P0_EMPL)&frame) + xor ^= 1; + + if(tab_parity[xor]) + indice |= 1; + + + tmp = frame&P1_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if((1l<<P1_EMPL)&frame) + xor ^= 1; + + if(tab_parity[xor]) + indice |= 2; + + tmp = frame&P2_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if((1l<<P2_EMPL)&frame) + xor ^= 1; + + if(tab_parity[xor]) + indice |=4; + + tmp = frame&P3_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if((1l<<P3_EMPL)&frame) + xor ^= 1; + + if(tab_parity[xor]) + indice |=8; + + tmp = frame&P4_MASK; + xor = ( (* (((uint8_t *)&tmp) + 0) ) ^ + (* (((uint8_t *)&tmp) + 1) ) ^ + (* (((uint8_t *)&tmp) + 2) ) ^ + (* (((uint8_t *)&tmp) + 3) ) ); + + if((1l<<P4_EMPL)&frame) + xor ^= 1; + + if(tab_parity[xor]) + indice |=16; + + return indice; +} + + +/*****************************/ + +uint32_t hamming_correct(uint32_t frame, uint8_t i) +{ + return frame ^ (1l<<(i-1)); +} + +/*****************************/ + + +void hamming_do(uint32_t *frame) +{ + *frame= hamming_process(hamming_expand(*frame)); +} + +/*******************************************************/ + +uint8_t hamming_undo(uint32_t *frame) +{ + uint8_t tmp; + + tmp=hamming_unprocess(*frame); + + if(tmp) + *frame= hamming_shrink(hamming_correct(*frame,tmp)); + else + *frame= hamming_shrink(*frame); + + + return tmp; +} + + + diff --git a/modules/encoding/hamming/hamming.h b/modules/encoding/hamming/hamming.h new file mode 100644 index 0000000..c0b3763 --- /dev/null +++ b/modules/encoding/hamming/hamming.h @@ -0,0 +1,51 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: hamming.h,v 1.2.4.2 2007-08-19 10:39:31 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Interface for HAMMING + * + * Thanks and hello to Serpilliere + */ + +/** \file hamming.c + * \brief Interface for the Hamming module. + * + * \todo nothing. + * + * \test Seems to work + * + * This module provides functions for error detection/correction + */ + +/**********************************************************/ + +/** + * Encode the frame (the 24 LSB bits) into a 29 bits frame with + * hamming error correction bits. The 3 MSB bits are not used. + */ +void hamming_do(uint32_t *frame); + +/** + * Decode the 29 bits frame into a 24 bits one. If an error occurs, + * the function tries to correct it and returns a positive value. If + * there is no error, the function returns 0. + */ +uint8_t hamming_undo(uint32_t *frame); diff --git a/modules/encoding/hamming/test/.config b/modules/encoding/hamming/test/.config new file mode 100644 index 0000000..dd92e5c --- /dev/null +++ b/modules/encoding/hamming/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +CONFIG_MODULE_HAMMING=y + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/encoding/hamming/test/CVS/Entries b/modules/encoding/hamming/test/CVS/Entries new file mode 100644 index 0000000..b34f779 --- /dev/null +++ b/modules/encoding/hamming/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.2.4.9/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/error_config.h/1.1.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +/main.c/1.2.4.2/Wed May 23 17:18:14 2007//Tb_zer0 +/uart_config.h/1.1.4.1/Sun Nov 26 21:06:05 2006//Tb_zer0 +D diff --git a/modules/encoding/hamming/test/CVS/Repository b/modules/encoding/hamming/test/CVS/Repository new file mode 100644 index 0000000..ba40dba --- /dev/null +++ b/modules/encoding/hamming/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/encoding/hamming/test diff --git a/modules/encoding/hamming/test/CVS/Root b/modules/encoding/hamming/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/encoding/hamming/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/encoding/hamming/test/CVS/Tag b/modules/encoding/hamming/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/encoding/hamming/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/encoding/hamming/test/CVS/Template b/modules/encoding/hamming/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/encoding/hamming/test/Makefile b/modules/encoding/hamming/test/Makefile new file mode 100644 index 0000000..ed79efe --- /dev/null +++ b/modules/encoding/hamming/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/encoding/hamming/test/error_config.h b/modules/encoding/hamming/test/error_config.h new file mode 100644 index 0000000..e2ca85f --- /dev/null +++ b/modules/encoding/hamming/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.4.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/encoding/hamming/test/main.c b/modules/encoding/hamming/test/main.c new file mode 100644 index 0000000..021d398 --- /dev/null +++ b/modules/encoding/hamming/test/main.c @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2.4.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <uart.h> +#include <hamming.h> + +/* in data is 24 bits */ +uint32_t tab[] = { + 0x00001200, + 0x00a843e1, + 0x00001560, + 0x001504e4, + 0x00d1d156, + 0x00000000, + 0x00123456, + 0x00d8de6a, +}; + +int main(void) +{ + uint32_t data; + uint32_t data_try; + uint8_t error; + int i; + +#ifndef HOST_VERSION + /* UART */ + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + + sei(); +#endif + + + for (i=0; i<(sizeof(tab)/sizeof(uint32_t)) ; i++) { + data=tab[i]; + for(error=0; error<29 ; error++) { + data_try = data; + + hamming_do(&data_try); + data_try ^= (1L << error); + + // block if pb + hamming_undo(&data_try); + if (data != data_try) { + printf("Hamming fail %d %d\n", i, error); + } + } + } + + printf("Hamming success\n"); + return 0; +} diff --git a/modules/encoding/hamming/test/uart_config.h b/modules/encoding/hamming/test/uart_config.h new file mode 100644 index 0000000..d5855d2 --- /dev/null +++ b/modules/encoding/hamming/test/uart_config.h @@ -0,0 +1,114 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.4.1 2006-11-26 21:06:05 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + + + + +/* + * UART1 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 0 +//#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 4 +#define UART1_TX_FIFO_SIZE 16 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + + + +#endif + diff --git a/modules/hardware/CVS/Entries b/modules/hardware/CVS/Entries new file mode 100644 index 0000000..c8b91a2 --- /dev/null +++ b/modules/hardware/CVS/Entries @@ -0,0 +1,4 @@ +D/adc//// +D/pwm//// +D/pwm_ng//// +D/timer//// diff --git a/modules/hardware/CVS/Repository b/modules/hardware/CVS/Repository new file mode 100644 index 0000000..2ce2315 --- /dev/null +++ b/modules/hardware/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware diff --git a/modules/hardware/CVS/Root b/modules/hardware/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/CVS/Tag b/modules/hardware/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/CVS/Template b/modules/hardware/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/adc/CVS/Entries b/modules/hardware/adc/CVS/Entries new file mode 100644 index 0000000..2af28dc --- /dev/null +++ b/modules/hardware/adc/CVS/Entries @@ -0,0 +1,6 @@ +/Makefile/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/adc.c/1.8.4.8/Fri Feb 27 21:37:49 2009//Tb_zer0 +/adc.h/1.7.4.3/Thu Sep 6 08:15:37 2007//Tb_zer0 +/adc_archs.h/1.4.4.4/Fri Feb 27 21:37:49 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/hardware/adc/CVS/Repository b/modules/hardware/adc/CVS/Repository new file mode 100644 index 0000000..fc4c6e1 --- /dev/null +++ b/modules/hardware/adc/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/adc diff --git a/modules/hardware/adc/CVS/Root b/modules/hardware/adc/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/adc/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/adc/CVS/Tag b/modules/hardware/adc/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/adc/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/adc/CVS/Template b/modules/hardware/adc/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/adc/Makefile b/modules/hardware/adc/Makefile new file mode 100644 index 0000000..dc5d349 --- /dev/null +++ b/modules/hardware/adc/Makefile @@ -0,0 +1,6 @@ +TARGET = adc + +# List C source files here. (C dependencies are automatically generated.) +SRC = adc.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/hardware/adc/adc.c b/modules/hardware/adc/adc.c new file mode 100644 index 0000000..a40d730 --- /dev/null +++ b/modules/hardware/adc/adc.c @@ -0,0 +1,233 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: adc.c,v 1.8.4.8 2009-02-27 21:37:49 zer0 Exp $ + * + */ + +#include <stdlib.h> + +#include <aversive.h> +#include <adc.h> + + /* keep the previous config */ +static uint16_t g_adc_previous_config = ADC_NO_CONFIG; + +/* function pointer definition for event */ +static void (*adc_event)(int16_t) = NULL; + + +/** + * Initialisation of ADC internal registers + * Can be called for a wake up after a shutdown command + */ +void adc_init(void) +{ +#if defined(PRADC) && defined(PRR) + cbi(PRR, PRADC); +#elif defined(PRADC) && defined(PRR0) + cbi(PRR0, PRADC); +#endif + + ADCSRA = (1<<ADEN) | (ADC_PRESCALE << ADPS0); + ADMUX = 0; +#ifdef ADCSRB + ADCSRB = 0; +#endif +} + +/** + * Shut down the ADC, for power consumption + */ +void adc_shutdown(void) +{ + ADCSRA = 0; // erases all the register + +#if defined(PRADC) && defined(PRR) + sbi(PRR, PRADC); +#elif defined(PRADC) && defined(PRR0) + sbi(PRR0, PRADC); +#endif +} + + +/** + * Register callback event. The parameter function is called when the + * conversion is finished. + */ +void adc_register_event(void (*f)(int16_t)) +{ + uint8_t flags; + + IRQ_LOCK(flags); + adc_event = f; + IRQ_UNLOCK(flags); +} + +/** + * Interrupt function, other interrupts are disabled during its + * execution. + */ +SIGNAL(SIG_ADC) +{ + int16_t result; + + if (!adc_event) + return; + + result = ADC; + + /* sign extension to fill the 16 bits when negative + * (for the 16 bits output format, the output is + * already right.) */ + if ( ( g_adc_previous_config & ADC_RESULT_SIGNED) + && !(g_adc_previous_config & ADC_MODE_16_BITS) + && (result & 0x0200) ) + result |= 0xFE00; + + adc_event(result); +} + + +/** + * Launch a conversion : this function launches a conversion with the + * specified configuration. The conversion_config is casted to an + * int. +*/ +void adc_launch(uint16_t conversion_config) +{ + /* configure multiplexer : done first, so the maximum time is + * left before the real conversion launch */ + ADMUX = conversion_config & 0xFF ; + /** + * This disables and reenables the ADC when a different + * channel is selected AND the new channel is a differential + * one. Using this trick, the ADC recalibrates, and the time + * for this allows the amplifier to settle. + * + * Datasheet says : + * When switching to a differential gain channel, the first + * conversion result may have a poor accuracy due to the + * required settling time for the automatic offset + * cancellation circuitry. The user should preferably + * disregard the first conversion result. + */ + if ( (conversion_config & ADC_RESULT_SIGNED) && + (g_adc_previous_config != conversion_config) ) { + cbi(ADCSRA,ADEN); + sbi(ADCSRA,ADEN); + } + + /* save config */ + g_adc_previous_config = conversion_config; + + /* for some devices, one additionnal MUX bit is in ADCSRB */ +#ifdef MUX5_IN_ADCSRB + if (conversion_config & MUX5_MASK_IN_CONFIG) + sbi(ADCSRB, MUX5); + else + cbi(ADCSRB, MUX5); +#endif // MUX5_IN_ADCSRB + + /* Enable free run or not (triggered mode) */ + if (conversion_config & ADC_MODE_TRIGGERED) + sbi(ADCSRA, ADFR); + else + cbi(ADCSRA, ADFR); + + /* Start conversion, with or without enabling interrupts */ + if (conversion_config & ADC_MODE_INT) { + /* Clear flag from previous intr (in case of previous + * conversion was not using intr), and enable + * interrupt */ + ADCSRA |= (1 << ADSC) | (1 << ADIF) | (1 << ADIE); + } + else { + /* clear flag from previous int, used as a 'conversion + finished' flag */ + cbi(ADCSRA, ADIE); + ADCSRA |= (1 << ADSC) | (1 << ADIF); + } +} + +/** + * This function gets an ADC value. If a conversion has been + * previously started, with EXACTLY the same config (or specifying + * ADC_NO_CONFIG) then it waits for it to finish. Else it launches a + * new one with the given config, and polls the result. + * + * This function should not be used if you use interrupts, but only + * can be used with triggered (or free run mode) +*/ +int16_t adc_get_value(uint16_t conversion_config) +{ + int16_t result; + + /* conversion has previously been launched, or no change */ + if ((conversion_config == ADC_NO_CONFIG) || + (conversion_config == g_adc_previous_config)) { + if (bit_is_clear(ADCSRA, ADSC) && + bit_is_clear(ADCSRA, ADIF)) { + /* no result is available now and no + conversion is pending -> launch it... */ + adc_launch(g_adc_previous_config); + } + } + /* The previous conversion had a different configuration : we + * must launch a new one */ + else { + /* Cancel previous triggered mode, if it was set and + * reset interrupt mask */ + cbi(ADCSRA, ADFR); + cbi(ADCSRA, ADIE); + + /* waiting for the previous conv to finish, result will + * be lost */ + while (bit_is_set(ADCSRA, ADSC)); + + /* launch new one */ + adc_launch(conversion_config); + } + + /* waiting for the result, works even in triggered mode, then + * clear the flag. */ + while (bit_is_clear(ADCSRA, ADIF)); + sbi(ADCSRA, ADIF); + + result = ADC; + + /* If we are in SIGNED_MODE + 10 bits format, and if the + * result is negative, set the 7 first MSB bits to 1 */ + if( ( g_adc_previous_config & ADC_RESULT_SIGNED ) && + !(g_adc_previous_config & ADC_MODE_16_BITS) && + (result & 0x0200) ) { + result |= 0xFE00; + } + + return result; +} + + +/** + * Just a int32_t version for compatibility with control_system + * function prototypes. + */ +int32_t adc_get_value32(void *conversion_config) +{ + return adc_get_value((uint16_t)conversion_config); +} + diff --git a/modules/hardware/adc/adc.h b/modules/hardware/adc/adc.h new file mode 100644 index 0000000..f177c8d --- /dev/null +++ b/modules/hardware/adc/adc.h @@ -0,0 +1,170 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: adc.h,v 1.7.4.3 2007-09-06 08:15:37 zer0 Exp $ + * + */ +/** \file adc.h + * \brief Interface of the ADC Module + * + * \todo some ATtiny support to add + * + * \test nothing done + * + * This module provides access to the built-in ADC unit of the AVR + * uCs. + */ + + +#ifndef _ADC_H_ +#define _ADC_H_ + +#include <aversive.h> + +#include <adc_archs.h> +#include <adc_config.h> + +/* + * You must always specify a MUX and a REF flag. + * MUX selection flags : + * + * A lot of them exist, for more, see the capabilities of your uC in + * the datasheet. Typical examples: + * + * MUX_ADC0 : selects input 0 + * MUX_ADC0_ADC1 : selects the electrical signal ADC0-ADC1 + * MUX_ADC0_ADC1_GAIN10 : selects the electrical signal (ADC0-ADC1) *10 + * ... + * MUX_VBG : selects the internal bandgap reference + * MUX_GND : selects the GND pin (0V) + * + * See your Datasheet, and adc_archs.h for more info. + * + * + * + * Reference flags : use one of these four : + * + * ADC_REF_AREF : a reference must be connected to the AREF pin : + * default + * ADC_REF_AVCC : using AVCC as reference : recommended for default !!! + * ADC_REF_VREF : using the internal reference + * ADC_REF_VREF2 : internal ref, with options. Beware, this does not + * work on all devices, see your Datasheet !! + * + * For some controllers (actually only ATtiny25-45-85) you can specify + * more options, just use (1<<REFS2)|(1<<REFS0) + * + * YOU NEED TO SPECIFY THIS VALUE FOR EACH CONVERSION CONFIGURATION !!!!! + */ + + +/** + * Set this flag for using interruptions instead of polling. + * If you use this, do not call the adc_get_value() function ! + */ +#define ADC_MODE_INT 0x0200 + +/** + * Flag for triggered mode. + */ +#define ADC_MODE_TRIGGERED 0x0400 + +/* + * Using one of this flags selects in which form the result is given + * + * These flags select the output format. The signed options are only + * for the differential measurement ! Don't use them for single ended + * measurements, or the results will be wrong. + * + * ADC_MODE_10_BITS : This format will give you a result between 0 and + * 1023 This format is default, you do not need to + * specify the flag. + + * ADC_MODE_16_BITS : This will use all the span of the uint16_t (or + * int16_t for a differential conversion) beware !! + * Cast your result in the correct type since the + * type depends of the type of channel you select. + */ +#define ADC_MODE_10_BITS 0 +#define ADC_MODE_16_BITS ADLAR_MASK_IN_CONFIG + +/** + * this flag is used internally of the module, use it only if you set + * manually a differential channel. + */ +#define ADC_RESULT_SIGNED 0x1000 + + +/** + * This specifies a conversion with no config (uses the previous + * parameters) always use this flag alone !! + */ +#define ADC_NO_CONFIG 0xFFFF + + +/**************/ + + +/** + * Initialisation of ADC internal registers + * Can be called for a wake up after a shutdown command + */ +void adc_init(void); + +/** + * Shut down the ADC, for power consumption + */ +void adc_shutdown(void); + + +/** + * Register callback event. The parameter function is called when the + * conversion is finished. + */ +void adc_register_event(void (*f)(int16_t)); + + + +/** + * Launch a conversion : this function launches a conversion with the + * specified configuration. The conversion_config is casted to an + * int. +*/ +void adc_launch(uint16_t conversion_config); + + +/** + * This function gets an ADC value. If a conversion has been + * previously started, with EXACTLY the same config (or specifying + * ADC_NO_CONFIG) then it waits for it to finish. Else it launches a + * new one with the given config, and polls the result. + * + * This function should not be used if you use interrupts, but only + * can be used with triggered (or free run mode) + */ +int16_t adc_get_value(uint16_t conversion_config); + + +/** + * Just a int32_t version for compatibility with control_system + * function prototypes. + */ +extern int32_t adc_get_value32(void * conversion_config); + + + +#endif // _ADC_H_ diff --git a/modules/hardware/adc/adc_archs.h b/modules/hardware/adc/adc_archs.h new file mode 100644 index 0000000..2207be1 --- /dev/null +++ b/modules/hardware/adc/adc_archs.h @@ -0,0 +1,412 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: adc_archs.h,v 1.4.4.4 2009-02-27 21:37:49 zer0 Exp $ + * + */ +#ifndef _ADC_ARCHS_ +#define _ADC_ARCHS_ + + +/** this file contains definitions for following configuration constants : + + ADC_REF_xxx : selection of a reference source + + MUX_xxx : selection options for the analog input multiplexerof the ADC + + prescaler : selected automatically with your clock setting. +*/ + + +/* ------------------------------------------------------------------------------------ + ---------------------------- REGISTER VARIATIONS ------------------------------- + ------------------------------------------------------------------------------------ */ + +/* + +Detailed register configurations, over the various AVR micros: + + ADMUX ADCSRA ADCSRB SFIOR + 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 +ATM64 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0 +also AT90CAN64 AT90CAN64 ATM164 ATM324 ATM644 ATM165 (ATM325 ATM3250 ATM645 ATM5450) + +ATM128 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 +also ATtiny26 + +AT90CAN128 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADHSM ADTS2 ADTS1 ADTS0 +also AT90USB1286 ATUSB1287 ATUSB646 ATUSB647 + +ATM16 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0 +also ATM32 ATM8535 + +ATM48 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0 +also ATM88 ATM168 ATM169 ATM329 ATM3290 ATM649 ATM6490 + +ATM8 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 + +AT90PWM2 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADHSM ADASCR ADTS2 ADTS1 ADTS0 +also AT90PWM3 (! AT90PWM2B and 3B do not have ADASCR !) + +ATM640 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 MUX5 ADTS2 ADTS1 ADTS0 +also ATM1280 ATM1281 ATM2560 ATM2561 + +ATtiny13 - REFS0 ADLAR - - - MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0 +ATtiny15 REFS1 REFS0 ADLAR - - MUX2 MUX1 MUX0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 +ATtiny24 REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 BIN ADLAR ADTS2 ADTS1 ADTS0 +also ATtiny44 ATtiny84 +ATtiny25 REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 BIN - IPR ADTS2 ADTS1 ADTS0 +also ATtiny45 ATtiny85 + + + +---------- +ATmega325_3250_645_6540 : preliminary incomplete DS, so not implemented now + +NO ADC : ATM162 ATM8515 ATtiny11 ATtiny12 ATtiny2313 ATtiny28 + +ATMEGA406 : completely different, 12bits, not implemented +*/ + + +/* some default defines */ +#define MUX5_MASK_IN_CONFIG (1<<MUX5) +#define ADLAR_MASK_IN_CONFIG (1<<ADLAR) + + + + +#if ( defined (__AVR_ATmega162__) \ + || defined (__AVR_ATmega8515__) \ + || defined (__AVR_ATtiny11__) || defined (__AVR_ATtiny12__) \ + || defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny28__) ) + +# error no ADC on your AVR device, please deactivate the ADC module +#endif // ... + +#if ( defined (__AVR_ATmega406__) ) +# error no The ADC of the ATmega406 is currently not supported by the ADC module +#endif // ... + +#if ( defined (__AVR_ATmega325__) || defined (__AVR_ATmega2350__) \ + || defined (__AVR_ATmega645__) || defined (__AVR_ATmega6540__) ) + +# error ADC module not implemented currently for your device (only incomplete preliminary Datasheet available) +#endif // ... + +/* this is not used for the moment */ +#if ( defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) \ + || defined (__AVR_ATmega8535__) ) + +# define ADTS_IN_SFIOR +#endif // ... + +/* this is a pity, on these devices, two bits are relocated */ +#if ( defined (__AVR_ATtiny24__) || defined (__AVR_ATtiny44__) \ + || defined (__AVR_ATtiny84__) ) + +# define ADLAR_IN_ADCSRB +# define MUX5_IN_ADMUX + +# undef ADLAR_MASK_IN_CONFIG +# define ADLAR_MASK_IN_CONFIG 0x0100 +#endif // ... + +/* additional mux5, this time at another location */ +#if ( defined (__AVR_ATmega640__) \ + || defined (__AVR_ATmega1280__) || defined (__AVR_ATmega1281__) \ + || defined (__AVR_ATmega2560__) || defined (__AVR_ATmega2561__) ) + +# define MUX5_IN_ADCSRB + +# undef MUX5_MASK_IN_CONFIG +# define MUX5_MASK_IN_CONFIG 0x0100 +#endif // ... + +// substitute +#ifndef ADFR +#define ADFR ADATE +#endif + + + +/* ------------------------------------------------------------------------------------ + ---------------------------- REF SELECTION ------------------------------------- + ------------------------------------------------------------------------------------ */ +/* +---------- +REFS1-0 bits : +0 : AREF is reference +1 : AVCC is reference +2 : internal reference2 (rarely available) +3 : internal reference1 (2.56 or 1.1 V, depends on AVR type, see DS) + +VREF2 is available on : ATM164 ATM324 ATM644 ATM640 ATM1280 ATM1281 ATM2561 +VREF2 is without external cap on : ATtiny24-44-84 +more options on ATtiny25-45-85, not implmented yet +---------- +*/ + +#define ADC_REF_AREF (0 << REFS0) +#define ADC_REF_AVCC (1 << REFS0) +#define ADC_REF_VREF2 (2 << REFS0) +#define ADC_REF_VREF (3 << REFS0) + + + +/* ------------------------------------------------------------------------------------ + ---------------------------- MUX ------------------------------------------------ + ------------------------------------------------------------------------------------ */ + + + +/** standard MUX table. if variations, please define MUX_NON_STD in your device specificity */ + +/* lacking configs on some devices : + + +no gain stages : ATM165 ATM169 aTM329 ATM3290 ATM649 ATM6490 +no gain and no differential stages : ATM48 ATM88 ATM168 ATM8 + +*/ +#if ( defined (__AVR_ATmega165__) \ + || defined (__AVR_ATmega169__) || defined (__AVR_ATmega329__) || defined (__AVR_ATmega3290__) \ + || defined (__AVR_ATmega649__) || defined (__AVR_ATmega6490__) ) + +# define MUX_NO_GAINS +#endif // ... + +/* we let a bit more in the config, not a problem, this will just set the reserved bit, with no effect */ +#if ( defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) \ + || defined (__AVR_ATmega8__) ) + +# define MUX_NO_GAINS +# define MUX_NO_DIFF + +#endif // ... + + + +/* 0x20 + 0x0-0x7 : individual channel 8 to 15 (ATM640 ATM1280 ATM1281 ATM2561 only !!) */ + +#if ( defined (__AVR_ATmega640__) || defined (__AVR_ATmega1280__) || defined (__AVR_ATmega1281__) \ + || defined (__AVR_ATmega2561__) || defined (__AVR_ATmega2560__) ) + + +# define MUX_ADC8 ((0 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC9 ((1 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC10 ((2 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC11 ((3 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC12 ((4 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC13 ((5 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC14 ((6 <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_ADC15 ((7 <<MUX0) | MUX5_MASK_IN_CONFIG) + +#endif // ... + +/* +AT30PWM2 &3 : only 4 MUX bits, as follow : +0x0 - 0xA : individual channel 0 to 10 +0xB : amplifier0 +0xC : amplifier1 +0xE : Vbg +0xF : GND + + we let a bit more in the config, not a problem, this will just set the reserved bit, with no effect +*/ +#if ( defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) \ + || defined (__AVR_ATmega8__) ) + +# define MUX_NO_GAINS +# define MUX_NO_DIFF + +# define MUX_AMP0 (0xB<<MUX0) +# define MUX_AMP1 (0xC<<MUX0) + +#endif // ... + +/** \todo : finish implmentation fully */ +/* +ATtiny13 : only 4 inputs, no gain, no diff, no ref voltage +ATtiny15 : + +0x0 - 0x3 : individual channel +0x4 : ADC2-ADC2 +0x5 : (ADC2 - ADC2) *20 +0x6 : ADC2-ADC3 +0x7 : (ADC2 - ADC3) *20 + +ATtiny24-44-84 : different table, not implemented yet +ATtiny25-45-85 : different table, not implemented yet +ATtiny26 : different table, not implemented yet +ATUSBxxx : different gains not implemanted yet, diffs available + +TO IMPLEMENT FULLY!! +yet these devices generate a warning, and select the default table, limited to 8 inputs + +*/ + +#if ( defined (__AVR_ATtiny13__) || defined (__AVR_ATtiny15__) \ + || defined (__AVR_ATtiny24__) || defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) \ + || defined (__AVR_ATtiny25__) || defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) \ + || defined (__AVR_ATtiny26__) \ + || defined (__AVR_AT90USB1286__) || defined (__AVR_AT90USB1287__) \ + || defined (__AVR_AT90USB646__) || defined (__AVR_AT90USB647__) ) + +# warning The ADC MUX table of your device is not fully defined, some inputs could not work correctly, see adc_archs.h + +# define MUX_NO_GAINS +# define MUX_NO_DIFF + +#endif // ... + + + +/* +currently implemented STD table is following : + +MUX4-0 bits : +0x0 - 0x7 : individual channel + +01000 : (ADC0 - ADC0) * 10 +01001 : (ADC1 - ADC0) * 10 +01010 : (ADC0 - ADC0) * 200 +01011 : (ADC1 - ADC0) * 200 + +01100 : (ADC2 - ADC2) * 10 +01101 : (ADC3 - ADC2) * 10 +01110 : (ADC2 - ADC2) * 200 +01111 : (ADC3 - ADC2) * 200 + +10000 + 0x0-0x7 : ADCx - ADC1 +11000 + 0x0-0x5 : ADCx - ADC2 + +0x1E : internal VBG reference (1.22V) +0x1F : GND + + +*/ + +#ifndef MUX_NON_STD + +# define MUX_ADC0 (0 <<MUX0) +# define MUX_ADC1 (1 <<MUX0) +# define MUX_ADC2 (2 <<MUX0) +# define MUX_ADC3 (3 <<MUX0) +# define MUX_ADC4 (4 <<MUX0) +# define MUX_ADC5 (5 <<MUX0) +# define MUX_ADC6 (6 <<MUX0) +# define MUX_ADC7 (7 <<MUX0) + +# ifndef MUX_NO_GAINS +# define MUX_ADC0_ADC0_GAIN10 ((0x8 <<MUX0) | ADC_RESULT_SIGNED ) /* specifies that the result is in signed mode */ +# define MUX_ADC1_ADC0_GAIN10 ((0x9 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC0_ADC0_GAIN200 ((0xA <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC1_ADC0_GAIN200 ((0xB <<MUX0) | ADC_RESULT_SIGNED ) + +# define MUX_ADC2_ADC2_GAIN10 ((0xC <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC3_ADC2_GAIN10 ((0xD <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC2_ADC2_GAIN200 ((0xE <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC3_ADC2_GAIN200 ((0xF <<MUX0) | ADC_RESULT_SIGNED ) +# endif // MUX_NO_GAINS + +# ifndef MUX_NO_DIFF +# define MUX_ADC0_ADC1 ((0x10 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC1_ADC1 ((0x11 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC2_ADC1 ((0x12 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC3_ADC1 ((0x13 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC4_ADC1 ((0x14 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC5_ADC1 ((0x15 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC6_ADC1 ((0x16 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC7_ADC1 ((0x17 <<MUX0) | ADC_RESULT_SIGNED ) + +# define MUX_ADC0_ADC2 ((0x18 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC1_ADC2 ((0x19 <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC2_ADC2 ((0x1A <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC3_ADC2 ((0x1B <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC4_ADC2 ((0x1C <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC5_ADC2 ((0x1D <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC6_ADC2 ((0x1E <<MUX0) | ADC_RESULT_SIGNED ) +# define MUX_ADC7_ADC2 ((0x1F <<MUX0) | ADC_RESULT_SIGNED ) +# endif // MUX_NO_DIFF + +# ifndef MUX5 +# define MUX_VBG (0x1E <<MUX0) +# define MUX_GND (0x1F <<MUX0) +# else +# define MUX_VBG ((0x1E <<MUX0) | MUX5_MASK_IN_CONFIG) +# define MUX_GND ((0x1F <<MUX0) | MUX5_MASK_IN_CONFIG) +# endif // MUX5 + +#endif // MUX_NON_STD + + + + +/* ------------------------------------------------------------------------------------ + ---------------------------- PRESCALER ----------------------------------------- + ------------------------------------------------------------------------------------ */ + +/* +---------- +ADPS bits : + +0 : prescaler = 2 +1 : prescaler = 2 +2 : prescaler = 4 +3 : prescaler = 8 +4 : prescaler = 16 +5 : prescaler = 32 +6 : prescaler = 64 +7 : prescaler = 128 + +This table is yet totally standard +the selection is based on the quartz frequency, given in autoconf.h + +*/ + +#include <autoconf.h> + +#if ( CONFIG_QUARTZ < 100000l) +# warning your clock is too slow, the ADC result is not guaranted +#endif + +#if (CONFIG_QUARTZ <= 400000l) // up to 400 kHz : PS = 2 +# define ADC_PRESCALE 0 +#elif (CONFIG_QUARTZ <= 800000l) // up to 800 kHz : PS = 4 +# define ADC_PRESCALE 2 +#elif (CONFIG_QUARTZ <= 1600000l) // up to 1.6 MHz : PS = 8 +# define ADC_PRESCALE 3 +#elif (CONFIG_QUARTZ <= 3200000l) // up to 3.2 MHz : PS = 16 +# define ADC_PRESCALE 4 +#elif (CONFIG_QUARTZ <= 6400000l) // up to 6.4 MHz : PS = 32 +# define ADC_PRESCALE 5 +#elif (CONFIG_QUARTZ <= 12800000l) // up to 12.8 MHz : PS = 64 +# define ADC_PRESCALE 6 +#elif ( CONFIG_QUARTZ <= 25600000l) // up to 25.6 MHz : PS = 128 +# define ADC_PRESCALE 7 +#else +# define ADC_PRESCALE 7 +# warning your clock is too fast, the ADC result is not guaranted +#endif + + + + + + +#endif // _ADC_ARCHS_ diff --git a/modules/hardware/adc/config/CVS/Entries b/modules/hardware/adc/config/CVS/Entries new file mode 100644 index 0000000..505e813 --- /dev/null +++ b/modules/hardware/adc/config/CVS/Entries @@ -0,0 +1,2 @@ +/adc_config.h/1.2.6.3/Fri Feb 20 20:17:31 2009//Tb_zer0 +D diff --git a/modules/hardware/adc/config/CVS/Repository b/modules/hardware/adc/config/CVS/Repository new file mode 100644 index 0000000..e7de666 --- /dev/null +++ b/modules/hardware/adc/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/adc/config diff --git a/modules/hardware/adc/config/CVS/Root b/modules/hardware/adc/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/adc/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/adc/config/CVS/Tag b/modules/hardware/adc/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/adc/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/adc/config/CVS/Template b/modules/hardware/adc/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/adc/config/adc_config.h b/modules/hardware/adc/config/adc_config.h new file mode 100644 index 0000000..5bce59c --- /dev/null +++ b/modules/hardware/adc/config/adc_config.h @@ -0,0 +1,7 @@ +#ifndef _ADC_CONFIG_H_ +#define _ADC_CONFIG_H_ + + + + +#endif // _ADC_CONFIG_H_ diff --git a/modules/hardware/adc/test/.config b/modules/hardware/adc/test/.config new file mode 100644 index 0000000..f2dc833 --- /dev/null +++ b/modules/hardware/adc/test/.config @@ -0,0 +1,272 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +CONFIG_MCU_ATMEGA32=y +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=8000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +CONFIG_MODULE_ADC=y +CONFIG_MODULE_ADC_CREATE_CONFIG=y + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/hardware/adc/test/CVS/Entries b/modules/hardware/adc/test/CVS/Entries new file mode 100644 index 0000000..7b97575 --- /dev/null +++ b/modules/hardware/adc/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.4.4.9/Fri Feb 20 20:17:31 2009//Tb_zer0 +/Makefile/1.2.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/adc_config.h/1.2.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/error_config.h/1.3.4.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/main.c/1.5.4.3/Thu Sep 6 08:15:37 2007//Tb_zer0 +/uart_config.h/1.3.4.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +D diff --git a/modules/hardware/adc/test/CVS/Repository b/modules/hardware/adc/test/CVS/Repository new file mode 100644 index 0000000..2e444a6 --- /dev/null +++ b/modules/hardware/adc/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/adc/test diff --git a/modules/hardware/adc/test/CVS/Root b/modules/hardware/adc/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/adc/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/adc/test/CVS/Tag b/modules/hardware/adc/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/adc/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/adc/test/CVS/Template b/modules/hardware/adc/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/adc/test/Makefile b/modules/hardware/adc/test/Makefile new file mode 100644 index 0000000..639fab0 --- /dev/null +++ b/modules/hardware/adc/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/hardware/adc/test/adc_config.h b/modules/hardware/adc/test/adc_config.h new file mode 100644 index 0000000..5bce59c --- /dev/null +++ b/modules/hardware/adc/test/adc_config.h @@ -0,0 +1,7 @@ +#ifndef _ADC_CONFIG_H_ +#define _ADC_CONFIG_H_ + + + + +#endif // _ADC_CONFIG_H_ diff --git a/modules/hardware/adc/test/error_config.h b/modules/hardware/adc/test/error_config.h new file mode 100644 index 0000000..3ea4032 --- /dev/null +++ b/modules/hardware/adc/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.3.4.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/hardware/adc/test/main.c b/modules/hardware/adc/test/main.c new file mode 100644 index 0000000..7860547 --- /dev/null +++ b/modules/hardware/adc/test/main.c @@ -0,0 +1,152 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.5.4.3 2007-09-06 08:15:37 zer0 Exp $ + * + */ + +#include <avr/io.h> +#include <aversive/wait.h> +#include <aversive.h> + +#include <adc.h> + +#include <uart.h> +#include <stdio.h> +#include <aversive/pgmspace.h> + +void event(int16_t); + + + +int main(void) +{ + int16_t a; int32_t b; + + uart_init(); + fdevopen(uart0_dev_send,NULL); + + sei(); + + adc_init(); + + while(1) { + + printf_P(PSTR("\n\nHello everybody\n This is the ADC test\n")); + + wait_ms(20); + + /* simple polling */ + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0 ); + + printf_P(PSTR("polling : ADC0 = %i\n"),a); + wait_ms(20); + + /* pre-launch */ + + adc_launch( ADC_REF_AVCC | MUX_ADC1 ); + wait_ms(1); + /* this function should take less time */ + a = adc_get_value( ADC_NO_CONFIG ); + + printf_P(PSTR("pre-launch : ADC1 = %i\n"),a); + wait_ms(20); + + /* test of free running mode */ + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC2 | ADC_MODE_TRIGGERED ); + printf_P(PSTR("free run mode : ADC2 = %i\n"),a); + wait_ms(1); + /* this function should take less time */ + a = adc_get_value( ADC_REF_AVCC | MUX_ADC3 | ADC_MODE_TRIGGERED ); + printf_P(PSTR("free run mode : ADC3 = %i\n\n"),a); + wait_ms(1); + + + /* test of different outputs formats */ + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0 | ADC_MODE_16_BITS ); + printf_P(PSTR("normal output 16: ADC0 = %u ( div = %u)\n"), + a, ((uint16_t)a)/(1<<6)); + + b = adc_get_value32( (void*)(ADC_REF_AVCC | MUX_ADC0 | + ADC_MODE_16_BITS) ); + printf_P(PSTR("normal output 16(32): ADC0 = %ld ( div = %lu)\n"), + b, b/(1l<<6)); + + /* ADC_MODE_10_BITS default */ + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0 ); + printf_P(PSTR("normal output 10: ADC0 = %u\n"),a); + + /* ADC_MODE_10_BITS default */ + b = adc_get_value32( (void*)(ADC_REF_AVCC | MUX_ADC0 ) ); + printf_P(PSTR("normal output 10(32): ADC0 = %lu\n"),b); + + printf_P(PSTR("now try a signed differential conversion\n")); + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0 | ADC_MODE_10_BITS ); + b = adc_get_value( ADC_REF_AVCC | MUX_ADC1 | ADC_MODE_10_BITS ); + printf_P(PSTR("computed : ADC0-ADC1 = %i\n"), + ((int16_t)a - (int16_t)b) /2); + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0_ADC1); + + printf_P(PSTR("signed output 10: ADC0-ADC1 = %i\n"),a); + + b = adc_get_value32( (void*)(ADC_REF_AVCC | MUX_ADC0_ADC1 ) ); + printf_P(PSTR("signed output 10(32): ADC0-ADC1 = %li\n"),b); + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0_ADC1 | + ADC_MODE_16_BITS ); + printf_P(PSTR("signed output 16: ADC0-ADC1 = %i ( div = %i)\n"), + a, a/(1<<6)); + + b = adc_get_value32( (void*)(ADC_REF_AVCC | MUX_ADC0_ADC1 | + ADC_MODE_16_BITS ) ); + printf_P(PSTR("signed output 16(32): ADC0-ADC1 = %li ( div = %li)\n\n"), + b, b/(1<<6)); + + /* test of interrupt mode : we scan once the 8 + inputs */ + + adc_register_event(event); + adc_launch( ADC_REF_AVCC | MUX_ADC0 | ADC_MODE_INT ); + wait_ms(20); + + wait_ms(2000); + } + + return 0; +} + + + +void event(int16_t result) +{ + static int i = 0; + + sei(); + + /* The printf in an interrupt is not a good idea, but ok for + * the test program */ + printf_P(PSTR("from interrupt : ADC%i = %i\n"),i,result); + + if(++i != 8) + adc_launch( ADC_REF_AVCC | ( MUX_ADC0 + i ) | ADC_MODE_INT ); + else + i = 0; /* end, reinitialisation for the next time */ +} diff --git a/modules/hardware/adc/test/uart_config.h b/modules/hardware/adc/test/uart_config.h new file mode 100644 index 0000000..d8db855 --- /dev/null +++ b/modules/hardware/adc/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.3.4.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/hardware/pwm/CVS/Entries b/modules/hardware/pwm/CVS/Entries new file mode 100644 index 0000000..70576d2 --- /dev/null +++ b/modules/hardware/pwm/CVS/Entries @@ -0,0 +1,8 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/pwm.c/1.8.4.8/Sun Apr 6 17:33:57 2008//Tb_zer0 +/pwm.h/1.7.4.7/Sun Apr 6 17:33:57 2008//Tb_zer0 +/pwm_archs.h/1.1.10.3/Wed May 23 17:18:14 2007//Tb_zer0 +/timers_synch.c/1.4.4.2/Thu Nov 30 22:00:31 2006//Tb_zer0 +/timers_synch.h/1.2.6.2/Thu Nov 30 22:00:31 2006//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/hardware/pwm/CVS/Repository b/modules/hardware/pwm/CVS/Repository new file mode 100644 index 0000000..eb46804 --- /dev/null +++ b/modules/hardware/pwm/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/pwm diff --git a/modules/hardware/pwm/CVS/Root b/modules/hardware/pwm/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/pwm/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/pwm/CVS/Tag b/modules/hardware/pwm/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/pwm/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/pwm/CVS/Template b/modules/hardware/pwm/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/pwm/Makefile b/modules/hardware/pwm/Makefile new file mode 100644 index 0000000..0d65a5a --- /dev/null +++ b/modules/hardware/pwm/Makefile @@ -0,0 +1,6 @@ +TARGET = pwm + +# List C source files here. (C dependencies are automatically generated.) +SRC = pwm.c timers_synch.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/hardware/pwm/config/CVS/Entries b/modules/hardware/pwm/config/CVS/Entries new file mode 100644 index 0000000..63bf6c2 --- /dev/null +++ b/modules/hardware/pwm/config/CVS/Entries @@ -0,0 +1,2 @@ +/pwm_config.h/1.2.6.3/Thu Sep 6 08:18:22 2007//Tb_zer0 +D diff --git a/modules/hardware/pwm/config/CVS/Repository b/modules/hardware/pwm/config/CVS/Repository new file mode 100644 index 0000000..d598f15 --- /dev/null +++ b/modules/hardware/pwm/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/pwm/config diff --git a/modules/hardware/pwm/config/CVS/Root b/modules/hardware/pwm/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/pwm/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/pwm/config/CVS/Tag b/modules/hardware/pwm/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/pwm/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/pwm/config/CVS/Template b/modules/hardware/pwm/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/pwm/config/pwm_config.h b/modules/hardware/pwm/config/pwm_config.h new file mode 100644 index 0000000..c00d8ce --- /dev/null +++ b/modules/hardware/pwm/config/pwm_config.h @@ -0,0 +1,128 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.2.6.3 2007-09-06 08:18:22 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ +/** \file pwm_config.h + \brief Module to operate all PWM outputs + + \test not tested + +*/ + + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +#define _PWM_CONFIG_VERSION_ 2 + +/* Which PWM are enabled ? */ +//#define PWM0_ENABLED +#define PWM1A_ENABLED +//#define PWM1B_ENABLED +//#define PWM1C_ENABLED +//#define PWM2_ENABLED +//#define PWM3A_ENABLED +//#define PWM3B_ENABLED +//#define PWM3C_ENABLED + + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +// timer configs (not all possibilities can be used at this time) +#define TIMER0_MODE TIMER_8_MODE_PWM +#define TIMER0_PRESCALE TIMER0_PRESCALER_DIV_64 + +#define TIMER1_MODE TIMER_16_MODE_PWM_10 +#define TIMER1_PRESCALE TIMER1_PRESCALER_DIV_8 + +#define TIMER2_MODE TIMER_8_MODE_PWM +#define TIMER2_PRESCALE TIMER1_PRESCALER_DIV_64 + +#define TIMER3_MODE TIMER_16_MODE_PWM_10 +#define TIMER3_PRESCALE TIMER3_PRESCALER_DIV_8 + + + + +/** config for pwm and signs + +The pwm mode is defined as follows : +you can add flags like the ones who follow : + +PWM_NORMAL : normal pwm, just to put a value if nothing else is needed +PWM_REVERSE : invert pwm output, not sign + +PWM_SIGNED : activate the sign output on a port (see config) +PWM_SIGN_INVERTED : invert sign output +PWM_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for low values, + else negative low values are near 100% + + +the values of PWMxx_SIGN_PORT and PWMxx_SIGN_BIT are simply ignored if the PWM is not signed + + +if you need for example a PWM1A with special sign mode you configure like this : + +#define PWM1A_MODE (PWM_SIGNED | PWM_SPECIAL_SIGN_MODE) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + +*/ + + + +// example for signed pwm1A +#define PWM1A_MODE (PWM_SIGNED) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + + + + + +/** +PWM synchronization. + +this makes the PWMs synchronized. +just activate the timers you want to synchronize + +to synch PWMs you need to enshure that the timers have same prescales. This is verified. +you need also to enshure that the PWM mode is the same, this is NOT verified !! +especially, for syncing 8 and 16 bit timers, the PWM mode should be 8 bit. + + +side effect : on some controllers prescalers are shared, so unwanted prescalers can be reset. + +This feature is not 100% shure for the moment, but has been tested on M32 and M128 +*/ + +//#define TIMER0_SYNCH +//#define TIMER1_SYNCH +//#define TIMER2_SYNCH +//#define TIMER3_SYNCH + + + +#endif + diff --git a/modules/hardware/pwm/pwm.c b/modules/hardware/pwm/pwm.c new file mode 100644 index 0000000..e438ed1 --- /dev/null +++ b/modules/hardware/pwm/pwm.c @@ -0,0 +1,664 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm.c,v 1.8.4.8 2008-04-06 17:33:57 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Implementation for PWM + */ +/** \file pwm.c + * \brief Implementation for the PWM module. + * + * \todo Test the module. + * + * \test The modul fonctions and had been tested by Lamygalle. + * + * This module provides functions for using a pwm + */ + +#include <aversive.h> + +#include "pwm.h" + +#include <aversive/parts.h> +#include <aversive/timers.h> + +#include <pwm_config.h> + +#include "timers_synch.h" + +#if _PWM_CONFIG_VERSION_ != 2 +#warning "You are using an old version of pwm_config.h file" +#warning "_PWM_CONFIG_VERSION_ is != 2" +#warning "Look in modules/base/pwm/config directory to import changes" +#warning "You should now use TIMERx_PRESCALER_DIV_XX from" +#warning "include/aversive/parts.h that is arch specific" +#endif + + +#ifdef TIMER1_MODE + +#if (TIMER1_MODE == TIMER_16_MODE_PWM_10) +#define TIMER1_PWM_BITS 10 +#elif (TIMER1_MODE == TIMER_16_MODE_PWM_9) +#define TIMER1_PWM_BITS 9 +#elif (TIMER1_MODE == TIMER_16_MODE_PWM_8) +#define TIMER1_PWM_BITS 8 +#else +#error TIMER1 mode not valid, check pwm_config.h +#endif + +#endif // TIMER1_MODE + +#ifdef TIMER3_MODE + +#if (TIMER3_MODE == TIMER_16_MODE_PWM_10) +#define TIMER3_PWM_BITS 10 +#elif (TIMER3_MODE == TIMER_16_MODE_PWM_9) +#define TIMER3_PWM_BITS 9 +#elif (TIMER3_MODE == TIMER_16_MODE_PWM_8) +#define TIMER3_PWM_BITS 8 +#else +#error TIMER3 mode not valid, check pwm_config.h +#endif + +#endif // TIMER3_MODE + +#if (PWM0_MODE & PWM_SIGNED) +#define pwm0_init_ddr() \ + sbi(DDR(PWM0_SIGN_PORT), PWM0_SIGN_BIT); \ + cbi(PWM0_SIGN_PORT, PWM0_SIGN_BIT); +#if (PWM0_MODE & PWM_SIGN_INVERTED) +#define pwm0_sign_set() sbi(PWM0_SIGN_PORT, PWM0_SIGN_BIT); +#define pwm0_sign_reset() cbi(PWM0_SIGN_PORT, PWM0_SIGN_BIT); +#else /* (PWM0_MODE & PWM_SIGN_INVERTED) */ +#define pwm0_sign_set() cbi(PWM0_SIGN_PORT, PWM0_SIGN_BIT); +#define pwm0_sign_reset() sbi(PWM0_SIGN_PORT, PWM0_SIGN_BIT); +#endif /* (PWM0_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM0_MODE & PWM_SIGNED) */ +#define pwm0_init_ddr() +#define pwm0_sign_set() +#define pwm0_sign_reset() +#endif /* (PWM0_MODE & PWM_SIGNED) */ + +#if (PWM1A_MODE & PWM_SIGNED) +#define pwm1A_init_ddr() \ + sbi(DDR(PWM1A_SIGN_PORT), PWM1A_SIGN_BIT); \ + cbi(PWM1A_SIGN_PORT, PWM1A_SIGN_BIT); +#if (PWM1A_MODE & PWM_SIGN_INVERTED) +#define pwm1A_sign_set() sbi(PWM1A_SIGN_PORT, PWM1A_SIGN_BIT); +#define pwm1A_sign_reset() cbi(PWM1A_SIGN_PORT, PWM1A_SIGN_BIT); +#else /* (PWM1A_MODE & PWM_SIGN_INVERTED) */ +#define pwm1A_sign_set() cbi(PWM1A_SIGN_PORT, PWM1A_SIGN_BIT); +#define pwm1A_sign_reset() sbi(PWM1A_SIGN_PORT, PWM1A_SIGN_BIT); +#endif /* (PWM1A_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM1A_MODE & PWM_SIGNED) */ +#define pwm1A_init_ddr() +#define pwm1A_sign_set() +#define pwm1A_sign_reset() +#endif /* (PWM1A_MODE & PWM_SIGNED) */ + +#if (PWM1B_MODE & PWM_SIGNED) +#define pwm1B_init_ddr() \ + sbi(DDR(PWM1B_SIGN_PORT), PWM1B_SIGN_BIT); \ + cbi(PWM1B_SIGN_PORT, PWM1B_SIGN_BIT); +#if (PWM1B_MODE & PWM_SIGN_INVERTED) +#define pwm1B_sign_set() sbi(PWM1B_SIGN_PORT, PWM1B_SIGN_BIT); +#define pwm1B_sign_reset() cbi(PWM1B_SIGN_PORT, PWM1B_SIGN_BIT); +#else /* (PWM1B_MODE & PWM_SIGN_INVERTED) */ +#define pwm1B_sign_set() cbi(PWM1B_SIGN_PORT, PWM1B_SIGN_BIT); +#define pwm1B_sign_reset() sbi(PWM1B_SIGN_PORT, PWM1B_SIGN_BIT); +#endif /* (PWM1B_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM1B_MODE & PWM_SIGNED) */ +#define pwm1B_init_ddr() +#define pwm1B_sign_set() +#define pwm1B_sign_reset() +#endif /* (PWM1B_MODE & PWM_SIGNED) */ + +#if (PWM1C_MODE & PWM_SIGNED) +#define pwm1C_init_ddr() \ + sbi(DDR(PWM1C_SIGN_PORT), PWM1C_SIGN_BIT); \ + cbi(PWM1C_SIGN_PORT, PWM1C_SIGN_BIT); +#if (PWM1C_MODE & PWM_SIGN_INVERTED) +#define pwm1C_sign_set() sbi(PWM1C_SIGN_PORT, PWM1C_SIGN_BIT); +#define pwm1C_sign_reset() cbi(PWM1C_SIGN_PORT, PWM1C_SIGN_BIT); +#else /* (PWM1C_MODE & PWM_SIGN_INVERTED) */ +#define pwm1C_sign_set() cbi(PWM1C_SIGN_PORT, PWM1C_SIGN_BIT); +#define pwm1C_sign_reset() sbi(PWM1C_SIGN_PORT, PWM1C_SIGN_BIT); +#endif /* (PWM1C_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM1C_MODE & PWM_SIGNED) */ +#define pwm1C_init_ddr() +#define pwm1C_sign_set() +#define pwm1C_sign_reset() +#endif /* (PWM1C_MODE & PWM_SIGNED) */ + +#if (PWM2_MODE & PWM_SIGNED) +#define pwm2_init_ddr() \ + sbi(DDR(PWM2_SIGN_PORT), PWM2_SIGN_BIT); \ + cbi(PWM2_SIGN_PORT, PWM2_SIGN_BIT); +#if (PWM2_MODE & PWM_SIGN_INVERTED) +#define pwm2_sign_set() sbi(PWM2_SIGN_PORT, PWM2_SIGN_BIT); +#define pwm2_sign_reset() cbi(PWM2_SIGN_PORT, PWM2_SIGN_BIT); +#else /* (PWM2_MODE & PWM_SIGN_INVERTED) */ +#define pwm2_sign_set() cbi(PWM2_SIGN_PORT, PWM2_SIGN_BIT); +#define pwm2_sign_reset() sbi(PWM2_SIGN_PORT, PWM2_SIGN_BIT); +#endif /* (PWM2_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM2_MODE & PWM_SIGNED) */ +#define pwm2_init_ddr() +#define pwm2_sign_set() +#define pwm2_sign_reset() +#endif /* (PWM2_MODE & PWM_SIGNED) */ + +#if (PWM3A_MODE & PWM_SIGNED) +#define pwm3A_init_ddr() \ + sbi(DDR(PWM3A_SIGN_PORT), PWM3A_SIGN_BIT); \ + cbi(PWM3A_SIGN_PORT, PWM3A_SIGN_BIT); +#if (PWM3A_MODE & PWM_SIGN_INVERTED) +#define pwm3A_sign_set() sbi(PWM3A_SIGN_PORT, PWM3A_SIGN_BIT); +#define pwm3A_sign_reset() cbi(PWM3A_SIGN_PORT, PWM3A_SIGN_BIT); +#else /* (PWM3A_MODE & PWM_SIGN_INVERTED) */ +#define pwm3A_sign_set() cbi(PWM3A_SIGN_PORT, PWM3A_SIGN_BIT); +#define pwm3A_sign_reset() sbi(PWM3A_SIGN_PORT, PWM3A_SIGN_BIT); +#endif /* (PWM3A_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM3A_MODE & PWM_SIGNED) */ +#define pwm3A_init_ddr() +#define pwm3A_sign_set() +#define pwm3A_sign_reset() +#endif /* (PWM3A_MODE & PWM_SIGNED) */ + +#if (PWM3B_MODE & PWM_SIGNED) +#define pwm3B_init_ddr() \ + sbi(DDR(PWM3B_SIGN_PORT), PWM3B_SIGN_BIT); \ + cbi(PWM3B_SIGN_PORT, PWM3B_SIGN_BIT); +#if (PWM3B_MODE & PWM_SIGN_INVERTED) +#define pwm3B_sign_set() sbi(PWM3B_SIGN_PORT, PWM3B_SIGN_BIT); +#define pwm3B_sign_reset() cbi(PWM3B_SIGN_PORT, PWM3B_SIGN_BIT); +#else /* (PWM3B_MODE & PWM_SIGN_INVERTED) */ +#define pwm3B_sign_set() cbi(PWM3B_SIGN_PORT, PWM3B_SIGN_BIT); +#define pwm3B_sign_reset() sbi(PWM3B_SIGN_PORT, PWM3B_SIGN_BIT); +#endif /* (PWM3B_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM3B_MODE & PWM_SIGNED) */ +#define pwm3B_init_ddr() +#define pwm3B_sign_set() +#define pwm3B_sign_reset() +#endif /* (PWM3B_MODE & PWM_SIGNED) */ + +#if (PWM3C_MODE & PWM_SIGNED) +#define pwm3C_init_ddr() \ + sbi(DDR(PWM3C_SIGN_PORT), PWM3C_SIGN_BIT); \ + cbi(PWM3C_SIGN_PORT, PWM3C_SIGN_BIT); +#if (PWM3C_MODE & PWM_SIGN_INVERTED) +#define pwm3C_sign_set() sbi(PWM3C_SIGN_PORT, PWM3C_SIGN_BIT); +#define pwm3C_sign_reset() cbi(PWM3C_SIGN_PORT, PWM3C_SIGN_BIT); +#else /* (PWM3C_MODE & PWM_SIGN_INVERTED) */ +#define pwm3C_sign_set() cbi(PWM3C_SIGN_PORT, PWM3C_SIGN_BIT); +#define pwm3C_sign_reset() sbi(PWM3C_SIGN_PORT, PWM3C_SIGN_BIT); +#endif /* (PWM3C_MODE & PWM_SIGN_INVERTED) */ +#else /* (PWM3C_MODE & PWM_SIGNED) */ +#define pwm3C_init_ddr() +#define pwm3C_sign_set() +#define pwm3C_sign_reset() +#endif /* (PWM3C_MODE & PWM_SIGNED) */ + + +#define pwm_invert_value(mode, value) \ +do { \ + if ( mode & PWM_SPECIAL_SIGN_MODE ) { \ + value = value & PWM_MAX; \ + } \ + else { \ + value = -value; \ + } \ +} while(0) + + +#define pwm_timer_8bits_init(n, mode, prescale, timer_mode) \ +do { \ + TCCR##n = ( ( ( timer_mode & 0x01 )?( 1 << WGM##n##0 ):0 ) | \ + ( ( timer_mode & 0x02 )?( 1 << WGM##n##1 ):0 ) | \ + ( ( prescale << CS##n##0 ) ) ); \ + if(mode & PWM_REVERSE) { \ + TCCR##n = ( ( (TCCR##n) & (~(0x03 << COM##n##0)) ) | \ + (0x01 << COM##n##0) ); \ + } \ + else { \ + TCCR##n = ( ( (TCCR##n) & (~(0x03 << COM##n##0)) ) | \ + (0x02 << COM##n##0) ); \ + } \ + OCR##n = 0x00; \ + sbi(OCR##n##_DDR,OCR##n##_BIT); \ + pwm##n##_init_ddr(); \ +} while(0) + +/***********************************************************/ + + +#define pwm_timer_16bits_init(n, m, mode, prescale, timer_mode) \ +do { \ + TCCR##n##A = (TCCR##n##A | \ + ( ( timer_mode & 0x01 )?( 1 << WGM##n##0 ):0 ) | \ + ( ( timer_mode & 0x02 )?( 1 << WGM##n##1 ):0 ) ) ; \ + \ + TCCR##n##B = ( ( ( timer_mode & 0x04 )?( 1 << WGM##n##2 ):0 ) | \ + ( ( timer_mode & 0x08 )?( 1 << WGM##n##3 ):0 ) | \ + ( ( prescale << CS##n##0 ) ) ); \ + if(mode & PWM_REVERSE) { \ + TCCR##n##A = ( ( (TCCR##n##A) & \ + (~(0x03 << COM##n##m##0)) ) | \ + (0x01 << COM##n##m##0) ); \ + } \ + else { \ + TCCR##n##A = ( ( (TCCR##n##A) & \ + (~(0x03 << COM##n##m##0)) ) | \ + (0x02 << COM##n##m##0) ); \ + } \ + OCR##n##m = 0; \ + sbi(OCR##n##m##_DDR,OCR##n##m##_BIT); \ + pwm##n##m##_init_ddr(); \ +} while(0) + +/***********************************************************/ + + +#define pwm_timer_8bits_set(n, value, mode) \ +do { \ + MAX(value, PWM_MAX); \ + if ( mode & PWM_SIGNED ) { \ + MIN(value, PWM_MIN); \ + if (value < 0) { \ + pwm##n##_sign_set(); \ + pwm_invert_value(mode, value); \ + } \ + else { \ + pwm##n##_sign_reset(); \ + } \ + } \ + else { \ + MIN(value, 0); \ + } \ + OCR##n =(uint8_t) ( value >> ( PWM_SIGNIFICANT_BITS - 8 )); \ +} while(0) + +/***********************************************************/ + + +#define pwm_timer_16bits_set(n, m, value, mode) \ +do { \ + MAX(value, PWM_MAX); \ + if ( mode & PWM_SIGNED ) { \ + MIN(value, PWM_MIN); \ + if (value < 0) { \ + pwm##n##m##_sign_set(); \ + pwm_invert_value(mode, value); \ + } \ + else { \ + pwm##n##m##_sign_reset(); \ + } \ + } \ + else { \ + MIN(value, 0); \ + } \ + OCR##n##m = ( value >> ( PWM_SIGNIFICANT_BITS \ + - TIMER##n##_PWM_BITS )) ; \ +} while(0) + + +/***********************************************************/ + +#if (defined PWM0_NUM) && (defined PWM0_ENABLED) +void pwm_init_0(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_8bits_init(0,PWM0_MODE,TIMER0_PRESCALE, TIMER0_MODE); + IRQ_UNLOCK(flags); +} + +/***********************************************************/ + +void pwm_set_0(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_8bits_set(0,value,PWM0_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM0_NUM) && (defined PWM0_ENABLED) + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM1A_NUM) && (defined PWM1A_ENABLED) +void pwm_init_1A(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_init(1,A,PWM1A_MODE,TIMER1_PRESCALE, TIMER1_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_1A(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_set(1,A,value,PWM1A_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM1A_NUM) && (defined PWM1A_ENABLED) + + + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM1B_NUM) && (defined PWM1B_ENABLED) +void pwm_init_1B(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_init(1,B,PWM1B_MODE,TIMER1_PRESCALE, TIMER1_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_1B(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_set(1,B,value,PWM1B_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM1B_NUM) && (defined PWM1B_ENABLED) + + + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM1C_NUM) && (defined PWM1C_ENABLED) +void pwm_init_1C(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_init(1,C,PWM1C_MODE,TIMER1_PRESCALE, TIMER1_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_1C(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_set(1,C,value, PWM1C_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM1C_NUM) && (defined PWM1C_ENABLED) + + + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM2_NUM) && (defined PWM2_ENABLED) +void pwm_init_2(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_8bits_init(2,PWM2_MODE,TIMER2_PRESCALE, TIMER2_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_2(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_8bits_set(2,value,PWM2_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM2_NUM) && (defined PWM2_ENABLED) + + + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM3A_NUM) && (defined PWM3A_ENABLED) +void pwm_init_3A(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_init(3,A,PWM3A_MODE,TIMER3_PRESCALE, TIMER3_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_3A(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_set(3,A,value,PWM3A_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM3A_NUM) && (defined PWM3A_ENABLED) + + + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM3B_NUM) && (defined PWM3B_ENABLED) +void pwm_init_3B(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_init(3,B,PWM3B_MODE,TIMER3_PRESCALE, TIMER3_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_3B(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_set(3,B,value,PWM3B_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM3B_NUM) && (defined PWM3B_ENABLED) + + + +/***********************************************************/ + + +/***********************************************************/ + +#if (defined PWM3C_NUM) && (defined PWM3C_ENABLED) +void pwm_init_3C(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_init(3,C,PWM3C_MODE,TIMER3_PRESCALE, TIMER3_MODE); + IRQ_UNLOCK(flags); +} + + +/***********************************************************/ + +void pwm_set_3C(int16_t value) +{ + uint8_t flags; + + IRQ_LOCK(flags); + pwm_timer_16bits_set(3,C,value,PWM3C_MODE); + IRQ_UNLOCK(flags); +} +#endif // (defined PWM3C_NUM) && (defined PWM3C_ENABLED) + + +/***********************************************************/ + + +/***********************************************************/ + +// global init +void pwm_init(void) +{ +#if (defined PWM0_NUM) && (defined PWM0_ENABLED) + pwm_init_0(); +#endif + +#if (defined PWM1A_NUM) && (defined PWM1A_ENABLED) + pwm_init_1A(); +#endif +#if (defined PWM1B_NUM) && (defined PWM1B_ENABLED) + pwm_init_1B(); +#endif +#if (defined PWM1C_NUM) && (defined PWM1C_ENABLED) + pwm_init_1C(); +#endif + +#if (defined PWM2_NUM) && (defined PWM2_ENABLED) + pwm_init_2(); +#endif + +#if (defined PWM3A_NUM) && (defined PWM3A_ENABLED) + pwm_init_3A(); +#endif +#if (defined PWM3B_NUM) && (defined PWM3B_ENABLED) + pwm_init_3B(); +#endif +#if (defined PWM3C_NUM) && (defined PWM3C_ENABLED) + pwm_init_3C(); +#endif + + +#if ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) ) + pwm_synch(); +#endif // ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) ) + + +} +/***********************************************************/ + + +/***********************************************************/ + +/* global SET FUNCTION : we use a (void *) to be compliant with + * control_system functions. For instance pwm_set((void *)(PWM1B_NUM), x) + * is equivalent to pwm_set_1B(x) */ +void pwm_set(void * data, int32_t value) +{ + uint8_t num = (uint8_t)(int)data; + S_MAX(value, 0x7FFF); + + switch(num) + { +#if (defined PWM0_NUM) && (defined PWM0_ENABLED) + case PWM0_NUM: + pwm_set_0(value); + break; +#endif + +#if (defined PWM1A_NUM) && (defined PWM1A_ENABLED) + case PWM1A_NUM: + pwm_set_1A(value); + break; +#endif +#if (defined PWM1B_NUM) && (defined PWM1B_ENABLED) + case PWM1B_NUM: + pwm_set_1B(value); + break; +#endif +#if (defined PWM1C_NUM) && (defined PWM1C_ENABLED) + case PWM1C_NUM: + pwm_set_1C(value); + break; +#endif + +#if (defined PWM2_NUM) && (defined PWM2_ENABLED) + case PWM2_NUM: + pwm_set_2(value); + break; +#endif + +#if (defined PWM3A_NUM) && (defined PWM3A_ENABLED) + case PWM3A_NUM: + pwm_set_3A(value); + break; +#endif +#if (defined PWM3B_NUM) && (defined PWM3B_ENABLED) + case PWM3B_NUM: + pwm_set_3B(value); + break; +#endif +#if (defined PWM3C_NUM) && (defined PWM3C_ENABLED) + case PWM3C_NUM: + pwm_set_3C(value); + break; +#endif + + default: + break; + } + +} + + + diff --git a/modules/hardware/pwm/pwm.h b/modules/hardware/pwm/pwm.h new file mode 100644 index 0000000..af7bd87 --- /dev/null +++ b/modules/hardware/pwm/pwm.h @@ -0,0 +1,104 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm.h,v 1.7.4.7 2008-04-06 17:33:57 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Implementation for PWM + */ +/** \file pwm.h + * \brief Interface for the PWM module. + * + * \todo Test the module. + * + * \test No tests for the moment. + * + * This module provides functions for using a pwm + */ + +#ifndef _PWM_H_ +#define _PWM_H_ + +#include <aversive.h> +#include <aversive/timers.h> +#include <aversive/parts.h> +#include <pwm_config.h> + + + +/** PWM signs & sign ligne inversion */ +#define PWM_NORMAL 0x00 +#define PWM_REVERSE 0x01 +#define PWM_SIGN_INVERTED 0x02 +#define PWM_SIGNED 0x04 +#define PWM_SPECIAL_SIGN_MODE 0x08 + +/** value to be used for limiting inputs */ +#define PWM_MAX ((1<< PWM_SIGNIFICANT_BITS)-1) +#define PWM_MIN (-PWM_MAX) + + + /** global functions*/ +extern void pwm_init(void); + +/** apply a PWM. + * \param data is a pointer that is casted in (uint8_t) to + * specify the number of the PWM. + * \param value is the value of the pwm. + */ +extern void pwm_set(void * data, int32_t value); + + +#if (defined PWM1A_NUM) && (defined PWM1A_ENABLED) +extern void pwm_init_1A(void); +extern void pwm_set_1A(int16_t value); +#endif // (defined PWM1A_NUM) && (defined PWM1A_ENABLED) + +#if (defined PWM1B_NUM) && (defined PWM1B_ENABLED) +extern void pwm_init_1B(void); +extern void pwm_set_1B(int16_t value); +#endif // (defined PWM1B_NUM) && (defined PWM1B_ENABLED) + +#if (defined PWM1C_NUM) && (defined PWM1C_ENABLED) +extern void pwm_init_1C(void); +extern void pwm_set_1C(int16_t value); +#endif // (defined PWM1C_NUM) && (defined PWM1C_ENABLED) + +#if (defined PWM2_NUM) && (defined PWM2_ENABLED) +extern void pwm_init_2(void); +extern void pwm_set_2(int16_t value); +#endif // (defined PWM2_NUM) && (defined PWM2_ENABLED) + +#if (defined PWM3A_NUM) && (defined PWM3A_ENABLED) +extern void pwm_init_3A(void); +extern void pwm_set_3A(int16_t value); +#endif // (defined PWM3A_NUM) && (defined PWM3A_ENABLED) + +#if (defined PWM3B_NUM) && (defined PWM3B_ENABLED) +extern void pwm_init_3B(void); +extern void pwm_set_3B(int16_t value); +#endif // (defined PWM3B_NUM) && (defined PWM3B_ENABLED) + +#if (defined PWM3C_NUM) && (defined PWM3C_ENABLED) +extern void pwm_init_3C(void); +extern void pwm_set_3C(int16_t value); +#endif // (defined PWM3C_NUM) && (defined PWM3C_ENABLED) + + +#endif // _PWM_H_ diff --git a/modules/hardware/pwm/pwm_archs.h b/modules/hardware/pwm/pwm_archs.h new file mode 100644 index 0000000..b26d7cd --- /dev/null +++ b/modules/hardware/pwm/pwm_archs.h @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_archs.h,v 1.1.10.3 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +// Microb Technology & EirBOT 2005 +// pwm_archs.h +// This file contains definitions used for timer use + +#ifndef _PWM_ARCHS_ +#define _PWM_ARCHS_ + +#error file replaced by include/aversive/timers.h + + +#endif diff --git a/modules/hardware/pwm/test/.config b/modules/hardware/pwm/test/.config new file mode 100644 index 0000000..d0d0774 --- /dev/null +++ b/modules/hardware/pwm/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +CONFIG_MODULE_PWM=y +CONFIG_MODULE_PWM_CREATE_CONFIG=y +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/hardware/pwm/test/CVS/Entries b/modules/hardware/pwm/test/CVS/Entries new file mode 100644 index 0000000..f57cbb3 --- /dev/null +++ b/modules/hardware/pwm/test/CVS/Entries @@ -0,0 +1,8 @@ +/.config/1.4.4.8/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/error_config.h/1.2.2.2/Thu Sep 6 08:13:36 2007//Tb_zer0 +/list_config.h/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/main.c/1.3.4.4/Wed May 23 17:18:14 2007//Tb_zer0 +/pwm_config.h/1.4.6.3/Sat May 12 16:42:40 2007//Tb_zer0 +/uart_config.h/1.1.2.1/Thu Sep 6 08:13:36 2007//Tb_zer0 +D diff --git a/modules/hardware/pwm/test/CVS/Repository b/modules/hardware/pwm/test/CVS/Repository new file mode 100644 index 0000000..e6ba9c1 --- /dev/null +++ b/modules/hardware/pwm/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/pwm/test diff --git a/modules/hardware/pwm/test/CVS/Root b/modules/hardware/pwm/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/pwm/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/pwm/test/CVS/Tag b/modules/hardware/pwm/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/pwm/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/pwm/test/CVS/Template b/modules/hardware/pwm/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/pwm/test/Makefile b/modules/hardware/pwm/test/Makefile new file mode 100644 index 0000000..ed79efe --- /dev/null +++ b/modules/hardware/pwm/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/hardware/pwm/test/error_config.h b/modules/hardware/pwm/test/error_config.h new file mode 100644 index 0000000..22f54fc --- /dev/null +++ b/modules/hardware/pwm/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.2.2.2 2007-09-06 08:13:36 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/hardware/pwm/test/list_config.h b/modules/hardware/pwm/test/list_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/pwm/test/main.c b/modules/hardware/pwm/test/main.c new file mode 100644 index 0000000..5238275 --- /dev/null +++ b/modules/hardware/pwm/test/main.c @@ -0,0 +1,69 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.3.4.4 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <aversive/parts.h> + +#include <aversive/wait.h> +#include <pwm.h> + +/* this little program tests a pwm output, with afew parameters. + * you can use this test with signed or non signed pwms. + * the normal output is: off, half, on, half, off... and then the same cycle reversed ... + */ + +/* pwm output to test */ +#define NUM ((void *)PWM1A_NUM) +/* maximal output */ +#define P_MAX 4095 +/* delay between tests */ +#define DELAY 1000 + +int main(void) +{ + int16_t signe = 1; + + DDRG=0x3; + PORTG=0x0; + + pwm_init(); + + + while(1) + { + pwm_set(NUM, 1 * signe); // not 0 to test for sign problems + wait_ms(2* DELAY); + + pwm_set(NUM, P_MAX /2 * signe); + wait_ms(DELAY); + + pwm_set(NUM, P_MAX* signe); + wait_ms(DELAY); + + pwm_set(NUM, P_MAX /2 * signe); + wait_ms(DELAY); + + signe *= -1; + } + + return 0; +} + + diff --git a/modules/hardware/pwm/test/pwm_config.h b/modules/hardware/pwm/test/pwm_config.h new file mode 100644 index 0000000..bbfe2ac --- /dev/null +++ b/modules/hardware/pwm/test/pwm_config.h @@ -0,0 +1,128 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.4.6.3 2007-05-12 16:42:40 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ +/** \file pwm_config.h + \brief Module to operate all PWM outputs + + \test not tested + +*/ + + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +#define _PWM_CONFIG_VERSION_ 2 + +/* Which PWM are enabled ? */ +//#define PWM0_ENABLED +#define PWM1A_ENABLED +//#define PWM1B_ENABLED +//#define PWM1C_ENABLED +//#define PWM2_ENABLED +//#define PWM3A_ENABLED +//#define PWM3B_ENABLED +//#define PWM3C_ENABLED + + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +// timer configs (not all possibilities can be used at this time) +#define TIMER0_MODE TIMER_8_MODE_PWM +#define TIMER0_PRESCALE TIMER0_PRESCALER_DIV_64 + +#define TIMER1_MODE TIMER_16_MODE_PWM_10 +#define TIMER1_PRESCALE TIMER1_PRESCALER_DIV_8 + +#define TIMER2_MODE TIMER_8_MODE_PWM +#define TIMER2_PRESCALE TIMER1_PRESCALER_DIV_64 + +#define TIMER3_MODE TIMER_16_MODE_PWM_10 +#define TIMER3_PRESCALE TIMER3_PRESCALER_DIV_8 + + + + +/** config for pwm and signs + +The pwm mode is defined as follows : +you can add flags like the ones who follow : + +PWM_NORMAL : normal pwm, just to put a value if nothing else is needed +PWM_REVERSE : invert pwm output, not sign + +PWM_SIGNED : activate the sign output on a port (see config) +PWM_SIGN_INVERTED : invert sign output +PWM_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for low values, + else negative low values are near 100% + + +the values of PWMxx_SIGN_PORT and PWMxx_SIGN_BIT are simply ignored if the PWM is not signed, but must be defined + + +if you need for example a PWM1A with special sign mode you configure like this : + +#define PWM1A_MODE (PWM_SIGNED | PWM_SPECIAL_SIGN_MODE) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + +*/ + + + +// example for signed pwm1A +#define PWM1A_MODE (PWM_SIGNED) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 2 + + + + + +/** +PWM synchronization. + +this makes the PWMs synchronized. +just activate the timers you want to synchronize + +to synch PWMs you need to enshure that the timers have same prescales. This is verified. +you need also to enshure that the PWM mode is the same, this is NOT verified !! +especially, for syncing 8 and 16 bit timers, the PWM mode should be 8 bit. + + +side effect : on some controllers prescalers are shared, so unwanted prescalers can be reset. + +This feature is not 100% shure for the moment, but has been tested on M32 and M128 +*/ + +//#define TIMER0_SYNCH +//#define TIMER1_SYNCH +//#define TIMER2_SYNCH +//#define TIMER3_SYNCH + + + +#endif + diff --git a/modules/hardware/pwm/test/uart_config.h b/modules/hardware/pwm/test/uart_config.h new file mode 100644 index 0000000..582f767 --- /dev/null +++ b/modules/hardware/pwm/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2007-09-06 08:13:36 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/hardware/pwm/timers_synch.c b/modules/hardware/pwm/timers_synch.c new file mode 100644 index 0000000..576810f --- /dev/null +++ b/modules/hardware/pwm/timers_synch.c @@ -0,0 +1,247 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timers_synch.c,v 1.4.4.2 2006-11-30 22:00:31 zer0 Exp $ + * + */ + + +/** \file timers_synch.c + * \brief this code synchronizes the timers in order to optain synchronous PWMs + * + * \todo Test this function on various uC + * \todo modify if there exists other prescaler configurations + * + * \test This feature is not 100% shure for the moment, but has been tested on M32 and M128 + * + * + * this code synchronizes the timers in order to optain synchronous PWMs, + * such a feature can be used for driving 3-phase motors with PWMS from different timers + * + * + * to synch PWMs you need to enshure that the timers have same prescales, + * and the same PWM mode + * + * There is one little side effect : if there are common prescalers in your controller they will all be reset + */ + + + +#include <avr/io.h> +#include <pwm.h> // for config + +#include <timers_synch.h> + + + +#if ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) ) + + +void pwm_synch(void) +{ + uint8_t flags; + +// computations of prescale for sync +#ifdef TIMER0_SYNCH + #undef PWM_SYNCH_PRESCALE + #define PWM_SYNCH_PRESCALE TIMER0_PRESCALE +#endif +#ifdef TIMER1_SYNCH + #undef PWM_SYNCH_PRESCALE + #define PWM_SYNCH_PRESCALE TIMER1_PRESCALE +#endif +#ifdef TIMER2_SYNCH + #undef PWM_SYNCH_PRESCALE + #define PWM_SYNCH_PRESCALE TIMER2_PRESCALE +#endif +#ifdef TIMER3_SYNCH + #undef PWM_SYNCH_PRESCALE + #define PWM_SYNCH_PRESCALE TIMER3_PRESCALE +#endif + +// verify that all the prescales are the same + +#ifdef TIMER0_SYNCH + #if (PWM_SYNCH_PRESCALE != TIMER0_PRESCALE) + #error TIMER0: not the same prescaler for synchronized PWMs, please verify your pwm_config.h + #endif +#endif +#ifdef TIMER1_SYNCH + #if (PWM_SYNCH_PRESCALE != TIMER1_PRESCALE) + #error TIMER1: not the same prescaler for synchronized PWMs, please verify your pwm_config.h + #endif +#endif +#ifdef TIMER2_SYNCH + #if (PWM_SYNCH_PRESCALE != TIMER2_PRESCALE) + #error TIMER2: not the same prescaler for synchronized PWMs, please verify your pwm_config.h + #endif +#endif +#ifdef TIMER3_SYNCH + #if (PWM_SYNCH_PRESCALE != TIMER3_PRESCALE) + #error TIMER3: not the same prescaler for synchronized PWMs, please verify your pwm_config.h + #endif +#endif + + + +// step between timer activations + +#if (PWM_SYNCH_PRESCALE == TIMER_8_PRESCALE_1) + #define STEP 1 +#else + #define STEP 0 +#endif + + + + IRQ_LOCK(flags); + + { + //*************************************************** + // register declarations + //*************************************************** + +#ifdef TIMER0_SYNCH + register uint8_t tccr0; +#endif +#ifdef TIMER1_SYNCH + register uint8_t tccr1b; +#endif +#ifdef TIMER2_SYNCH + register uint8_t tccr2; +#endif +#ifdef TIMER3_SYNCH + register uint8_t tccr3b; +#endif + + register uint8_t sfior; + + //*************************************************** + // save state and stop timers + //*************************************************** + +#ifdef TIMER0_SYNCH + tccr0 = TCCR0; + TCCR0 = 0x00; +#endif +#ifdef TIMER1_SYNCH + tccr1b = TCCR1B; + TCCR1B = 0x00; +#endif +#ifdef TIMER2_SYNCH + tccr2 = TCCR2; + TCCR2 = 0x00; +#endif +#ifdef TIMER3_SYNCH + tccr3b = TCCR3B; + TCCR3B = 0x00; +#endif + + //*************************************************** + // the timers are now stopped, we set the TCNT's to given values + // set timers to given values + // the timers would then be startes one after another, + // and synchronize themselves while starting with the right offset + //*************************************************** + +#ifdef TIMER0_SYNCH + TCNT0 = 0; +#endif +#ifdef TIMER1_SYNCH + TCNT1H = 0; + TCNT1L = 1l * STEP; +#endif +#ifdef TIMER2_SYNCH + TCNT2 = 2l * STEP; +#endif +#ifdef TIMER3_SYNCH + TCNT3H = 0; + TCNT3L = 4l * STEP; // one more, cause TCCR acess takes one instruction more (see TCCR3B acess, down) +#endif + + //*************************************************** + // resetting prescalers (some could influence unwanted timers, enshure that there are no problems with that ) + // this is done this manner to be absolutely synchronous + //*************************************************** + + sfior = SFIOR; + + // mega 128 +#if (defined PSR321) && ( (defined TIMER3_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER1_SYNCH) ) + sfior |= (1<<PSR321); +#endif +#if (defined PSR0) && (defined TIMER0_SYNCH) + sfior |= (1<<PSR0); +#endif + // mega 163, 32 ... +#if (defined PSR10) && ( (defined TIMER1_SYNCH) || (defined TIMER0_SYNCH)) + sfior |= (1<<PSR10); +#endif +#if (defined PSR2) && (defined TIMER2_SYNCH) + sfior |= (1<<PSR2); +#endif + + ////////////////////////////////////////////////// + // here begins the time critical section + // this all is done within less than 8 cycles, to assure function even with a prescaler set to 8 + ////////////////////////////////////////////////// + + + SFIOR = sfior; + + + //*************************************************** + // running timers + //*************************************************** + +#ifdef TIMER0_SYNCH + TCCR0 = tccr0; +#else + nop(); +#endif +#ifdef TIMER1_SYNCH + TCCR1B = tccr1b; +#else + nop(); +#endif +#ifdef TIMER2_SYNCH + TCCR2 = tccr2; +#else + nop(); +#endif +#ifdef TIMER3_SYNCH + TCCR3B = tccr3b; // this instruction takes 2 cycles (on ATMEGA128) +#else + /* nop(); // optimized, not necessary, coz nothing after + nop(); */ +#endif + + ////////////////////////////////////////////////// + // here ends the time critical section + // this all is done within less than 8 cycles, to assure function even with a prescaler set to 8 + ////////////////////////////////////////////////// + + + + + } + IRQ_UNLOCK(flags); + + +} + +#endif // ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) ) diff --git a/modules/hardware/pwm/timers_synch.h b/modules/hardware/pwm/timers_synch.h new file mode 100644 index 0000000..6f9c31d --- /dev/null +++ b/modules/hardware/pwm/timers_synch.h @@ -0,0 +1,51 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timers_synch.h,v 1.2.6.2 2006-11-30 22:00:31 zer0 Exp $ + * + */ + + +/** \file timers_synch.c + * \brief this code synchronizes the timers in order to optain synchronous PWMs + * + * \todo Test this function on various uC + * \todo modify if there exists other prescaler configurations + * + * \test This feature is not 100% shure for the moment, but has been tested on M32 and M128 + * + * + * this code synchronizes the timers in order to optain synchronous PWMs, + * such a feature can be used for driving 3-phase motors with PWMS from different timers + * + * + * to synch PWMs you need to enshure that the timers have same prescales, + * and the same PWM mode + * + * There is one little side effect : if there are common prescalers in your controller they will all be reset + */ + + +#ifndef _PWM_SYNCH_ +#define _PWM_SYNCH_ + + +#if ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) ) +extern void pwm_synch(void); +#endif // ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) ) + +#endif // _PWM_SYNCH_ diff --git a/modules/hardware/pwm_ng/CVS/Entries b/modules/hardware/pwm_ng/CVS/Entries new file mode 100644 index 0000000..2c23b5f --- /dev/null +++ b/modules/hardware/pwm_ng/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +/pwm_ng.c/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +/pwm_ng.h/1.1.2.2/Fri Feb 20 20:18:15 2009//Tb_zer0 +D/test//// diff --git a/modules/hardware/pwm_ng/CVS/Repository b/modules/hardware/pwm_ng/CVS/Repository new file mode 100644 index 0000000..2b5b5b6 --- /dev/null +++ b/modules/hardware/pwm_ng/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/pwm_ng diff --git a/modules/hardware/pwm_ng/CVS/Root b/modules/hardware/pwm_ng/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/pwm_ng/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/pwm_ng/CVS/Tag b/modules/hardware/pwm_ng/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/pwm_ng/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/pwm_ng/CVS/Template b/modules/hardware/pwm_ng/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/pwm_ng/Makefile b/modules/hardware/pwm_ng/Makefile new file mode 100644 index 0000000..5e5518e --- /dev/null +++ b/modules/hardware/pwm_ng/Makefile @@ -0,0 +1,6 @@ +TARGET = pwm_ng + +# List C source files here. (C dependencies are automatically generated.) +SRC = pwm_ng.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/hardware/pwm_ng/pwm_ng.c b/modules/hardware/pwm_ng/pwm_ng.c new file mode 100644 index 0000000..046bc8a --- /dev/null +++ b/modules/hardware/pwm_ng/pwm_ng.c @@ -0,0 +1,136 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright Droids-corporation - Olivier MATZ - 2009 + */ +#include <string.h> + +#include <aversive.h> +#include <aversive/parts.h> +#include <aversive/timers.h> + +#include "pwm_ng.h" + +/* value to be used for limiting inputs */ +#define PWM_SIGNIFICANT_BITS 12 +#define PWM_MAX ((1<< PWM_SIGNIFICANT_BITS)-1) +#define PWM_MIN (-PWM_MAX) + +#define PWM_NG_TYPE_8 0 +#define PWM_NG_TYPE_16 1 + +#define PWM_NG_NBITS_8 0 +#define PWM_NG_NBITS_9 1 +#define PWM_NG_NBITS_10 2 + +void pwm_ng_init(struct pwm_ng *pwm, uint8_t timer_nbits, + uint8_t pwm_nbits, uint8_t pwm_mode, + volatile void *ocrn, + uint8_t com0, volatile uint8_t *tccrn, + volatile uint8_t *pwm_port, uint8_t pwm_bit, + volatile uint8_t *sign_port, uint8_t sign_bit) +{ + memset(pwm, 0, sizeof(*pwm)); + + if (timer_nbits == 8) { + pwm->type = PWM_NG_TYPE_8; + pwm->u.ocr8 = ocrn; + *pwm->u.ocr8 = 0; + } + else { + pwm->type = PWM_NG_TYPE_16; + pwm->u.ocr16 = ocrn; + *pwm->u.ocr16 = 0; + } + switch (pwm_nbits) { + case 9: + pwm->nbits = PWM_NG_NBITS_9; + break; + case 10: + pwm->nbits = PWM_NG_NBITS_10; + break; + case 8: + default: + pwm->nbits = PWM_NG_NBITS_8; + break; + } + pwm->mode = pwm_mode; + + *tccrn &= ~(0x03 << com0); + if (pwm_mode & PWM_NG_MODE_REVERSE) + *tccrn |= (0x01 << com0); + else + *tccrn |= (0x02 << com0); + + DDR(*pwm_port) |= (1 << pwm_bit); + + if ((pwm_mode & PWM_NG_MODE_SIGNED) && (sign_port)) + DDR(*sign_port) |= (1 << sign_bit); + pwm->sign_port = sign_port; + pwm->sign_bit = sign_bit; +} + +static inline void pwm_sign_set(struct pwm_ng *pwm) +{ + if (pwm->mode & PWM_NG_MODE_SIGN_INVERTED) + *pwm->sign_port &= ~(1 << pwm->sign_bit); + else + *pwm->sign_port |= (1 << pwm->sign_bit); +} + +static inline void pwm_sign_reset(struct pwm_ng *pwm) +{ + if (pwm->mode &PWM_NG_MODE_SIGN_INVERTED) + *pwm->sign_port |= (1 << pwm->sign_bit); + else + *pwm->sign_port &= ~(1 << pwm->sign_bit); +} + +static inline int32_t pwm_invert_value(struct pwm_ng *pwm, int32_t value) +{ + if (pwm->mode & PWM_NG_MODE_SPECIAL_SIGN) + return value & PWM_MAX; + else + return -value; +} + +#include <stdio.h> +void pwm_ng_set(void *data, int32_t value) +{ + struct pwm_ng *pwm = data; + uint8_t nbits = 8 + pwm->nbits; + + MAX(value, PWM_MAX); + if (pwm->mode & PWM_NG_MODE_SIGNED) { + MIN(value, PWM_MIN); + if (value < 0) { + pwm_sign_set(pwm); + value = pwm_invert_value(pwm, value); + } + else { + pwm_sign_reset(pwm); + } + } + else { + MIN(value, 0); + } + if (pwm->type == PWM_NG_TYPE_8) + *pwm->u.ocr8 = (uint8_t) (value >> (PWM_SIGNIFICANT_BITS - 8)); + else + *pwm->u.ocr16 = (value >> (PWM_SIGNIFICANT_BITS - nbits)); +} + diff --git a/modules/hardware/pwm_ng/pwm_ng.h b/modules/hardware/pwm_ng/pwm_ng.h new file mode 100644 index 0000000..112e48e --- /dev/null +++ b/modules/hardware/pwm_ng/pwm_ng.h @@ -0,0 +1,175 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright Droids-corporation - Olivier MATZ - 2009 + */ + +#ifndef _PWM_NG_H_ +#define _PWM_NG_H_ + +#include <aversive.h> +#include <aversive/timers.h> +#include <aversive/parts.h> + +/* + * PWM signs & sign ligne inversion. + * The pwm mode is defined be the following flags: + * + * PWM_NG_MODE_NORMAL : normal pwm, just to put a value if + * nothing else is needed. + * PWM_NG_MODE_REVERSE : invert pwm output, not sign. + * PWM_NG_MODE_SIGNED : activate the sign output on another port + * PWM_NG_MODE_SIGN_INVERTED : invert sign output + * PWM_NG_MODE_SPECIAL_SIGN_MODE : if defined, the pwm is always near 0 for + * low values, else negative low values are + * near 100% + */ +#define PWM_NG_MODE_NORMAL 0x00 +#define PWM_NG_MODE_REVERSE 0x01 +#define PWM_NG_MODE_SIGN_INVERTED 0x02 +#define PWM_NG_MODE_SIGNED 0x04 +#define PWM_NG_MODE_SPECIAL_SIGN 0x08 + +/* + * Timer modes. + */ +#define PWM_NG_TIMER_0_MODE + +struct pwm_ng { + uint8_t mode:4, + type:1, /* timer 8 bits or 16 bits */ + nbits:2, /* 8, 9, or 10 bits pwm */ + reserved:1; + union { + volatile uint8_t *ocr8; + volatile uint16_t *ocr16; + } u; + volatile uint8_t *sign_port; + uint8_t sign_bit; +}; + + /** + * Initialize a 8 bits timer to do a PWM. This macro must + * be called before pwm_ng_init(). + * \param n is the number of the timer. + * \param t_mode can be TIMER_8_MODE_PWM_PC, TIMER_8_MODE_CTC, + * TIMER_8_MODE_PWM. + * \param prsc is the value to be loaded in + * the prescaler register for this timer. For instance, + * TIMER0_PRESCALER_DIV_256. + */ +#define PWM_NG_TIMER_8BITS_INIT(n, t_mode, prsc) \ + do { \ + TCCR##n = ( ((t_mode & 0x01) ? (1 << WGM##n##0):0) | \ + ((t_mode & 0x02) ? (1 << WGM##n##1):0) | \ + ((prsc << CS##n##0)) ); \ + } while(0) + +/** + * same, but with timer8 with several OCx (like on atm2560) + */ +#define PWM_NG_TIMER_8BITS_INIT_B(n, t_mode, prsc) \ + do { \ + TCCR##n##A = ( ((t_mode & 0x01) ? (1 << WGM##n##0):0) | \ + ((t_mode & 0x02) ? (1 << WGM##n##1):0) | \ + ((prsc << CS##n##0)) ); \ + TCCR##n##B = (prsc << CS##n##0); \ + } while(0) + + /** + * Initialize a 16 bits timer to do a PWM. This macro must + * be called before pwm_ng_init(). + * \param n is the number of the timer. + * \param timer_mode can be TIMER_16_MODE_PWM_PC, TIMER_16_MODE_CTC, + * TIMER_16_MODE_PWM... + * \param prsc is the value to be loaded in + * the prescaler register for this timer. For instance, + * TIMER1_PRESCALER_DIV_256. + */ +#define PWM_NG_TIMER_16BITS_INIT(n, t_mode, prsc) do { \ + TCCR##n##A &= ~((1 << WGM##n##0) | (1 << WGM##n##1)); \ + TCCR##n##A |= ((t_mode & 0x01) ? (1 << WGM##n##0):0) | \ + ((t_mode & 0x02) ? (1 << WGM##n##1):0); \ + TCCR##n##B = ((t_mode & 0x04) ? (1 << WGM##n##2):0) | \ + ((t_mode & 0x08 ) ? (1 << WGM##n##3):0) | \ + (prsc << CS##n##0); \ + } while(0) + + +/** + * Inititialize a PWM: set its mode, output pin DDR, DDR for sign + * bit if any. Example for 8 bits (for atmega128): + * pwm_ng_init(&pwm, 8, 8, PWM_NG_MODE_SIGNED|PWM_NG_MODE_SIGN_INVERTED, + * &OCR0, COM00, &TCCR0, &PORTB, 4, &PORTE, 3); + * Example for 16 bits (for atmega32): + * pwm_ng_init(&pwm, 16, 9, PWM_NG_MODE_NORMAL, + * &OCR1B, COM1B0, &TCCR1A, &PORTD, 5, NULL, 0); + * Note that you can use the helper macros PWM_NG_INIT8() or + * PWM_NG_INIT16() instead. + * \param pwm is the pointer to the pwm structure that will be + * filled. + * \param nbits is the number of bits for the timer (8 or 16). + * \param pwm_mode is the mode of the PWM. See the PWM_NG_MODE_xxx + * flags above. + * \param ocrn is a pointer to the OCRn register for this PWM. + * \param com0 is the COMn0 for this PWM. + * \param pwm_port is the pointer to the PORT of the pwm corresponding + * to the configured PWM. For instance &PORTB. This is specified in + * the datasheets, and depends on the AVR part. + * \param pwm_bit is the bitnum of the configured pwm output. This + * is specified in the datasheets, and depends on the AVR part. + * \param sign_port is a poinrter to the PORT for the sign bit if + * any, else, it can be set to NULL. + * \param sign_bit is the bitnum of the configured sign output. + */ +void pwm_ng_init(struct pwm_ng *pwm, uint8_t timer_nbits, + uint8_t pwm_nbits, uint8_t pwm_mode, + volatile void *ocrn, + uint8_t com0, volatile uint8_t *tccrn, + volatile uint8_t *pwm_port, uint8_t pwm_bit, + volatile uint8_t *sign_port, uint8_t sign_bit); + +#define PWM_NG_INIT8(pwm, n, pwm_nbits, pwm_mode, sign_port, sign_bit) \ + do { \ + pwm_ng_init(pwm, 8, pwm_nbits, pwm_mode, &OCR##n, \ + COM##n##0, &TCCR##n, &OC##n##_PORT, \ + OC##n##_BIT, sign_port, sign_bit); \ + } while(0) + +#define PWM_NG_INIT8_B(pwm, n, m, pwm_nbits, pwm_mode, sign_port, sign_bit) \ + do { \ + pwm_ng_init(pwm, 8, pwm_nbits, pwm_mode, &OCR##n##m, \ + COM##n##m##0, &TCCR##n##A, &OC##n##m##_PORT, \ + OC##n##m##_BIT, sign_port, sign_bit); \ + } while(0) + +#define PWM_NG_INIT16(pwm, n, m, pwm_nbits, pwm_mode, sign_port, sign_bit) \ + do { \ + pwm_ng_init(pwm, 16, pwm_nbits, pwm_mode, &OCR##n##m, \ + COM##n##m##0, &TCCR##n##A, \ + &OC##n##m##_PORT, OC##n##m##_BIT, \ + sign_port, sign_bit); \ + } while(0) + +/** apply a PWM. + * \param pwm is a pointer to the struct pwm. + * \param value is the value of the pwm. The value is between 0 and + * 4095 for a non-signed pwm or -4096 and 4095 for a signed one. + */ +void pwm_ng_set(void *pwm, int32_t value); + +#endif // _PWM_H_ diff --git a/modules/hardware/pwm_ng/test/.config b/modules/hardware/pwm_ng/test/.config new file mode 100644 index 0000000..f033a98 --- /dev/null +++ b/modules/hardware/pwm_ng/test/.config @@ -0,0 +1,254 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +CONFIG_MODULE_PWM_NG=y +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/hardware/pwm_ng/test/CVS/Entries b/modules/hardware/pwm_ng/test/CVS/Entries new file mode 100644 index 0000000..174b676 --- /dev/null +++ b/modules/hardware/pwm_ng/test/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +/Makefile/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +/error_config.h/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +/main.c/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +/uart_config.h/1.1.2.1/Fri Jan 23 23:04:16 2009//Tb_zer0 +D diff --git a/modules/hardware/pwm_ng/test/CVS/Repository b/modules/hardware/pwm_ng/test/CVS/Repository new file mode 100644 index 0000000..8df0e35 --- /dev/null +++ b/modules/hardware/pwm_ng/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/pwm_ng/test diff --git a/modules/hardware/pwm_ng/test/CVS/Root b/modules/hardware/pwm_ng/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/pwm_ng/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/pwm_ng/test/CVS/Tag b/modules/hardware/pwm_ng/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/pwm_ng/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/pwm_ng/test/CVS/Template b/modules/hardware/pwm_ng/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/pwm_ng/test/Makefile b/modules/hardware/pwm_ng/test/Makefile new file mode 100644 index 0000000..ed79efe --- /dev/null +++ b/modules/hardware/pwm_ng/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/hardware/pwm_ng/test/error_config.h b/modules/hardware/pwm_ng/test/error_config.h new file mode 100644 index 0000000..212055d --- /dev/null +++ b/modules/hardware/pwm_ng/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2009-01-23 23:04:16 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/hardware/pwm_ng/test/main.c b/modules/hardware/pwm_ng/test/main.c new file mode 100644 index 0000000..f7b0ef0 --- /dev/null +++ b/modules/hardware/pwm_ng/test/main.c @@ -0,0 +1,42 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.1 2009-01-23 23:04:16 zer0 Exp $ + * + */ + +#include <pwm_ng.h> + +/* this program tests pwm output */ + +int main(void) +{ + struct pwm_ng pwm; + + pwm_ng_timer_16bits_init(1, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + + pwm_ng_init(&pwm, 16, 10, PWM_NG_MODE_SIGNED, + &OCR1A, COM1A0, &TCCR1A, &PORTD, 3, &PORTE, 0); + + pwm_ng_set(&pwm, 100); + + while(1); + return 0; +} + + diff --git a/modules/hardware/pwm_ng/test/uart_config.h b/modules/hardware/pwm_ng/test/uart_config.h new file mode 100644 index 0000000..be2e2f9 --- /dev/null +++ b/modules/hardware/pwm_ng/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2009-01-23 23:04:16 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/hardware/timer/CVS/Entries b/modules/hardware/timer/CVS/Entries new file mode 100644 index 0000000..88d3ac5 --- /dev/null +++ b/modules/hardware/timer/CVS/Entries @@ -0,0 +1,47 @@ +/Makefile/1.1.2.4/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer.h/1.1.2.4/Wed May 23 17:18:14 2007//Tb_zer0 +/timer0_getset.c/1.1.2.2/Wed May 23 17:18:14 2007//Tb_zer0 +/timer0_prescaler.c/1.1.2.3/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer0_register_OC_at_tics.c/1.1.2.3/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer0_register_OC_in_us.c/1.1.2.3/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer0_register_OV.c/1.1.2.2/Wed May 23 17:18:14 2007//Tb_zer0 +/timer0_startstop.c/1.1.2.2/Wed May 23 17:18:14 2007//Tb_zer0 +/timer1_getset.c/1.1.2.2/Wed May 23 17:18:14 2007//Tb_zer0 +/timer1_prescaler.c/1.1.2.2/Wed May 23 17:18:14 2007//Tb_zer0 +/timer1_register_OC_at_tics.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer1_register_OC_in_us.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer1_register_OV.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer1_startstop.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer2_getset.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer2_prescaler.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer2_register_OC_at_tics.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer2_register_OC_in_us.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer2_register_OV.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer2_startstop.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer3_getset.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer3_prescaler.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer3_register_OC_at_tics.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer3_register_OC_in_us.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer3_register_OV.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer3_startstop.c/1.1.2.2/Wed May 23 17:18:15 2007//Tb_zer0 +/timer4_getset.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer4_prescaler.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer4_register_OC_at_tics.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer4_register_OC_in_us.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer4_register_OV.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer4_startstop.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer5_getset.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer5_prescaler.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer5_register_OC_at_tics.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer5_register_OC_in_us.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer5_register_OV.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer5_startstop.c/1.1.2.1/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer_conf_check.c/1.1.2.4/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer_declarations.h/1.1.2.2/Mon Dec 4 23:48:22 2006//Tb_zer0 +/timer_definitions.h/1.1.2.5/Tue Apr 7 20:00:46 2009//Tb_zer0 +/timer_init.c/1.1.2.4/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer_intr.c/1.1.2.4/Fri Jan 30 20:18:36 2009//Tb_zer0 +/timer_intr.h/1.1.2.3/Wed May 23 17:18:15 2007//Tb_zer0 +/timer_prescaler.h/1.1.2.4/Fri Jan 30 20:18:36 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/hardware/timer/CVS/Repository b/modules/hardware/timer/CVS/Repository new file mode 100644 index 0000000..6313da8 --- /dev/null +++ b/modules/hardware/timer/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/timer diff --git a/modules/hardware/timer/CVS/Root b/modules/hardware/timer/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/timer/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/timer/CVS/Tag b/modules/hardware/timer/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/timer/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/timer/CVS/Template b/modules/hardware/timer/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/timer/Makefile b/modules/hardware/timer/Makefile new file mode 100644 index 0000000..1afcd22 --- /dev/null +++ b/modules/hardware/timer/Makefile @@ -0,0 +1,44 @@ +TARGET = timer + +# List C source files here. (C dependencies are automatically generated.) +SRC = timer_init.c \ +timer_intr.c \ +timer_conf_check.c \ +timer0_startstop.c \ +timer1_startstop.c \ +timer2_startstop.c \ +timer3_startstop.c \ +timer4_startstop.c \ +timer5_startstop.c \ +timer0_getset.c \ +timer1_getset.c \ +timer2_getset.c \ +timer3_getset.c \ +timer4_getset.c \ +timer5_getset.c \ +timer0_register_OV.c \ +timer1_register_OV.c \ +timer2_register_OV.c \ +timer3_register_OV.c \ +timer4_register_OV.c \ +timer5_register_OV.c \ +timer0_register_OC_at_tics.c \ +timer1_register_OC_at_tics.c \ +timer2_register_OC_at_tics.c \ +timer3_register_OC_at_tics.c \ +timer4_register_OC_at_tics.c \ +timer5_register_OC_at_tics.c \ +timer0_register_OC_in_us.c \ +timer1_register_OC_in_us.c \ +timer2_register_OC_in_us.c \ +timer3_register_OC_in_us.c \ +timer4_register_OC_in_us.c \ +timer5_register_OC_in_us.c \ +timer0_prescaler.c \ +timer1_prescaler.c \ +timer2_prescaler.c \ +timer3_prescaler.c \ +timer4_prescaler.c \ +timer5_prescaler.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/hardware/timer/config/CVS/Entries b/modules/hardware/timer/config/CVS/Entries new file mode 100644 index 0000000..c82211b --- /dev/null +++ b/modules/hardware/timer/config/CVS/Entries @@ -0,0 +1,2 @@ +/timer_config.h/1.1.2.2/Fri Jan 30 20:18:36 2009//Tb_zer0 +D diff --git a/modules/hardware/timer/config/CVS/Repository b/modules/hardware/timer/config/CVS/Repository new file mode 100644 index 0000000..7deb613 --- /dev/null +++ b/modules/hardware/timer/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/timer/config diff --git a/modules/hardware/timer/config/CVS/Root b/modules/hardware/timer/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/timer/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/timer/config/CVS/Tag b/modules/hardware/timer/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/timer/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/timer/config/CVS/Template b/modules/hardware/timer/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/timer/config/timer_config.h b/modules/hardware/timer/config/timer_config.h new file mode 100644 index 0000000..9817f4c --- /dev/null +++ b/modules/hardware/timer/config/timer_config.h @@ -0,0 +1,53 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.2 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED +/* some archs have TIMER0A_ENABLED or TIMER0B_ENABLED */ + +#define TIMER1_ENABLED +#define TIMER1A_ENABLED +#define TIMER1B_ENABLED +#define TIMER1C_ENABLED + +#define TIMER2_ENABLED +/* some archs have TIMER2A_ENABLED or TIMER2B_ENABLED */ + +#define TIMER3_ENABLED +#define TIMER3A_ENABLED +#define TIMER3B_ENABLED +#define TIMER3C_ENABLED + +#define TIMER4_ENABLED +#define TIMER4A_ENABLED +#define TIMER4B_ENABLED +#define TIMER4C_ENABLED + +#define TIMER5_ENABLED +#define TIMER5A_ENABLED +#define TIMER5B_ENABLED +#define TIMER5C_ENABLED + +#define TIMER0_PRESCALER_DIV 1 +#define TIMER1_PRESCALER_DIV 1 +#define TIMER2_PRESCALER_DIV 1 +#define TIMER3_PRESCALER_DIV 1 +#define TIMER4_PRESCALER_DIV 1 +#define TIMER5_PRESCALER_DIV 1 diff --git a/modules/hardware/timer/test/.config b/modules/hardware/timer/test/.config new file mode 100644 index 0000000..0e3cd76 --- /dev/null +++ b/modules/hardware/timer/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +CONFIG_MODULE_SCHEDULER_USE_TIMERS=y +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +CONFIG_MODULE_TIMER_DYNAMIC=y +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/hardware/timer/test/CVS/Entries b/modules/hardware/timer/test/CVS/Entries new file mode 100644 index 0000000..9c5e03d --- /dev/null +++ b/modules/hardware/timer/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.1.2.8/Sun Apr 13 16:52:40 2008//Tb_zer0 +/Makefile/1.1.2.1/Thu Nov 30 21:58:35 2006//Tb_zer0 +/error_config.h/1.1.2.1/Thu Sep 6 08:13:36 2007//Tb_zer0 +/main.c/1.1.2.4/Wed May 23 17:18:15 2007//Tb_zer0 +/timer_config.h/1.1.2.3/Mon Dec 4 23:48:22 2006//Tb_zer0 +/uart_config.h/1.1.2.1/Thu Sep 6 08:13:36 2007//Tb_zer0 +D diff --git a/modules/hardware/timer/test/CVS/Repository b/modules/hardware/timer/test/CVS/Repository new file mode 100644 index 0000000..bffcb8b --- /dev/null +++ b/modules/hardware/timer/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/hardware/timer/test diff --git a/modules/hardware/timer/test/CVS/Root b/modules/hardware/timer/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/hardware/timer/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/hardware/timer/test/CVS/Tag b/modules/hardware/timer/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/hardware/timer/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/hardware/timer/test/CVS/Template b/modules/hardware/timer/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/hardware/timer/test/Makefile b/modules/hardware/timer/test/Makefile new file mode 100644 index 0000000..ed79efe --- /dev/null +++ b/modules/hardware/timer/test/Makefile @@ -0,0 +1,19 @@ +TARGET = main + +# Aversive root directory +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/hardware/timer/test/error_config.h b/modules/hardware/timer/test/error_config.h new file mode 100644 index 0000000..2071927 --- /dev/null +++ b/modules/hardware/timer/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-09-06 08:13:36 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/hardware/timer/test/main.c b/modules/hardware/timer/test/main.c new file mode 100644 index 0000000..b97f590 --- /dev/null +++ b/modules/hardware/timer/test/main.c @@ -0,0 +1,91 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.4 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <uart.h> +#include <aversive.h> +#include <aversive/wait.h> +#include <stdio.h> +#include <timer.h> + + +void callback_ov(void) +{ + static int i=0; + printf("CB%d\n", i++); +} + +void callback_oc(void) +{ + static int i=0; + + i++; + if ( (i%1000) == 0 ) { + printf("%d\n", i/1000); + if (i==5000) { + timer3A_register_OC_intr_in_us(NULL, 0); + return; + } + } + + timer3A_register_OC_intr_in_us(callback_oc, 1000); +} + +/* Todo : + * timer 8bits are differents... + * timer1A_register_OC_intr_in_tics + * functions with timer num as a parameter + * return an error in timer1A_register_OC_intr_in_us if not adapted to presc + * synch des timers (eventuellement) + * clear on compare match could be useful + * enhance help for funcs. Note that register_in_us is 100us long on a 16Mhz ATmega128 in dynamic mode + * + * aversive/parts.h can be included twice... bad + * aversive/ATxxx.h can be included directly... bad too + */ + +int main(void) +{ + int16_t a,b,c; + + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + timer_init(); + sei(); + + // printf("init\n"); + + a=timer3_get(); + timer3A_register_OC_intr_in_us(callback_oc, 1000); + b=timer3_get(); + c=timer3_get(); + printf("%d %d %d %d\n", a, b, c, OCR3A); + + timer1_register_OV_intr(callback_ov); + printf("timer = %d\n", timer1_get()); + wait_ms(10); + printf("timer = %d\n", timer1_get()); + wait_ms(10); + printf("timer = %d\n", timer1_get()); + + while(1); + + return 0; +} diff --git a/modules/hardware/timer/test/timer_config.h b/modules/hardware/timer/test/timer_config.h new file mode 100644 index 0000000..57da32b --- /dev/null +++ b/modules/hardware/timer/test/timer_config.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.3 2006-12-04 23:48:22 zer0 Exp $ + * + */ + +/* #define TIMER0_ENABLED */ + +#define TIMER1_ENABLED +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +#define TIMER3_ENABLED +#define TIMER3A_ENABLED +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 +#define TIMER1_PRESCALER_DIV 64 +#define TIMER2_PRESCALER_DIV 8 +#define TIMER3_PRESCALER_DIV 1 diff --git a/modules/hardware/timer/test/uart_config.h b/modules/hardware/timer/test/uart_config.h new file mode 100644 index 0000000..582f767 --- /dev/null +++ b/modules/hardware/timer/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2007-09-06 08:13:36 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/hardware/timer/timer.h b/modules/hardware/timer/timer.h new file mode 100644 index 0000000..daab02d --- /dev/null +++ b/modules/hardware/timer/timer.h @@ -0,0 +1,83 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer.h,v 1.1.2.4 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +/** + * Olivier MATZ - Droids-corp 2006 + * + * \brief Interface of the timer module + * + * The objective of this module is to provide a simple and portable + * interface to the hardware timers of AVR devices. + */ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include <aversive/parts.h> + +#include <aversive.h> +#include <timer_declarations.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +/** Init of all timers with static configutaion (see timer_config.h) */ +void timer_init(void); + +/* declare all timer functions (see timer_declarations.h) */ + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE +DECLARE_TIMER_FUNCS(0) +#endif + +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE +DECLARE_TIMER_FUNCS(1) +#endif + +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE +DECLARE_TIMER_FUNCS(2) +#endif + +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE +DECLARE_TIMER_FUNCS(3) +#endif + +/* define static inline functions (see timer_definitions.h) */ + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE +DEFINE_TIMER_US_CONVERSIONS(0) +#endif + +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE +DEFINE_TIMER_US_CONVERSIONS(1) +#endif + +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE +DEFINE_TIMER_US_CONVERSIONS(2) +#endif + +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE +DEFINE_TIMER_US_CONVERSIONS(3) +#endif + +#endif diff --git a/modules/hardware/timer/timer0_getset.c b/modules/hardware/timer/timer0_getset.c new file mode 100644 index 0000000..9704089 --- /dev/null +++ b/modules/hardware/timer/timer0_getset.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer0_getset.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_config.h> + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE +DEFINE_TIMER_GET_SET(0) +#endif + diff --git a/modules/hardware/timer/timer0_prescaler.c b/modules/hardware/timer/timer0_prescaler.c new file mode 100644 index 0000000..ab5ab5a --- /dev/null +++ b/modules/hardware/timer/timer0_prescaler.c @@ -0,0 +1,46 @@ +/* + * Copyright Droids-corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer0_prescaler.c,v 1.1.2.3 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#ifdef CONFIG_MODULE_TIMER_DYNAMIC + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE +DEFINE_DYNAMIC_PRESCALER_FUNCS(0) +#endif + +#else + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE +DEFINE_STATIC_PRESCALER_FUNCS(0) +#endif + +#endif + diff --git a/modules/hardware/timer/timer0_register_OC_at_tics.c b/modules/hardware/timer/timer0_register_OC_at_tics.c new file mode 100644 index 0000000..4387e15 --- /dev/null +++ b/modules/hardware/timer/timer0_register_OC_at_tics.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer0_register_OC_at_tics.c,v 1.1.2.3 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0 +DEFINE_REGISTER_OC_INTR_AT_TICS(0) +#endif + +#if defined TIMER0A_ENABLED && defined SIG_OUTPUT_COMPARE0A +DEFINE_REGISTER_OC_INTR_AT_TICS(0A) +#endif + +#if defined TIMER0B_ENABLED && defined SIG_OUTPUT_COMPARE0B +DEFINE_REGISTER_OC_INTR_AT_TICS(0B) +#endif + diff --git a/modules/hardware/timer/timer0_register_OC_in_us.c b/modules/hardware/timer/timer0_register_OC_in_us.c new file mode 100644 index 0000000..8eb0765 --- /dev/null +++ b/modules/hardware/timer/timer0_register_OC_in_us.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer0_register_OC_in_us.c,v 1.1.2.3 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0 +DEFINE_REGISTER_OC_INTR_IN_US(0,0) +#endif + +#if defined TIMER0A_ENABLED && defined SIG_OUTPUT_COMPARE0A +DEFINE_REGISTER_OC_INTR_IN_US(0,0A) +#endif + +#if defined TIMER0B_ENABLED && defined SIG_OUTPUT_COMPARE0B +DEFINE_REGISTER_OC_INTR_IN_US(0,0B) +#endif + diff --git a/modules/hardware/timer/timer0_register_OV.c b/modules/hardware/timer/timer0_register_OV.c new file mode 100644 index 0000000..4d24614 --- /dev/null +++ b/modules/hardware/timer/timer0_register_OV.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer0_register_OV.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER0_ENABLED && defined SIG_OVERFLOW0 +DEFINE_REGISTER_OV_INTR(0) +#endif + diff --git a/modules/hardware/timer/timer0_startstop.c b/modules/hardware/timer/timer0_startstop.c new file mode 100644 index 0000000..96c9eb1 --- /dev/null +++ b/modules/hardware/timer/timer0_startstop.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer0_startstop.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> +#include <timer_config.h> + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE +DEFINE_TIMER_START_STOP(0) +#endif + diff --git a/modules/hardware/timer/timer1_getset.c b/modules/hardware/timer/timer1_getset.c new file mode 100644 index 0000000..43d4dc8 --- /dev/null +++ b/modules/hardware/timer/timer1_getset.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer1_getset.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_config.h> + +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE +DEFINE_TIMER_GET_SET(1) +#endif + diff --git a/modules/hardware/timer/timer1_prescaler.c b/modules/hardware/timer/timer1_prescaler.c new file mode 100644 index 0000000..b3e5350 --- /dev/null +++ b/modules/hardware/timer/timer1_prescaler.c @@ -0,0 +1,46 @@ +/* + * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer1_prescaler.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#ifdef CONFIG_MODULE_TIMER_DYNAMIC + +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE +DEFINE_DYNAMIC_PRESCALER_FUNCS(1) +#endif + +#else + +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE +DEFINE_STATIC_PRESCALER_FUNCS(1) +#endif + +#endif + diff --git a/modules/hardware/timer/timer1_register_OC_at_tics.c b/modules/hardware/timer/timer1_register_OC_at_tics.c new file mode 100644 index 0000000..fa8ab8d --- /dev/null +++ b/modules/hardware/timer/timer1_register_OC_at_tics.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer1_register_OC_at_tics.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER1A_ENABLED && defined SIG_OUTPUT_COMPARE1A +DEFINE_REGISTER_OC_INTR_AT_TICS(1A) +#endif + +#if defined TIMER1B_ENABLED && defined SIG_OUTPUT_COMPARE1B +DEFINE_REGISTER_OC_INTR_AT_TICS(1B) +#endif + +#if defined TIMER1C_ENABLED && defined SIG_OUTPUT_COMPARE1C +DEFINE_REGISTER_OC_INTR_AT_TICS(1C) +#endif + diff --git a/modules/hardware/timer/timer1_register_OC_in_us.c b/modules/hardware/timer/timer1_register_OC_in_us.c new file mode 100644 index 0000000..81af93a --- /dev/null +++ b/modules/hardware/timer/timer1_register_OC_in_us.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer1_register_OC_in_us.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER1A_ENABLED && defined SIG_OUTPUT_COMPARE1A +DEFINE_REGISTER_OC_INTR_IN_US(1,1A) +#endif + +#if defined TIMER1B_ENABLED && defined SIG_OUTPUT_COMPARE1B +DEFINE_REGISTER_OC_INTR_IN_US(1,1B) +#endif + +#if defined TIMER1C_ENABLED && defined SIG_OUTPUT_COMPARE1C +DEFINE_REGISTER_OC_INTR_IN_US(1,1C) +#endif + diff --git a/modules/hardware/timer/timer1_register_OV.c b/modules/hardware/timer/timer1_register_OV.c new file mode 100644 index 0000000..be2a049 --- /dev/null +++ b/modules/hardware/timer/timer1_register_OV.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer1_register_OV.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER1_ENABLED && defined SIG_OVERFLOW1 +DEFINE_REGISTER_OV_INTR(1) +#endif + diff --git a/modules/hardware/timer/timer1_startstop.c b/modules/hardware/timer/timer1_startstop.c new file mode 100644 index 0000000..3a55888 --- /dev/null +++ b/modules/hardware/timer/timer1_startstop.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer1_startstop.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> +#include <timer_config.h> + +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE +DEFINE_TIMER_START_STOP(1) +#endif + diff --git a/modules/hardware/timer/timer2_getset.c b/modules/hardware/timer/timer2_getset.c new file mode 100644 index 0000000..2b9b750 --- /dev/null +++ b/modules/hardware/timer/timer2_getset.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer2_getset.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_config.h> + +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE +DEFINE_TIMER_GET_SET(2) +#endif + diff --git a/modules/hardware/timer/timer2_prescaler.c b/modules/hardware/timer/timer2_prescaler.c new file mode 100644 index 0000000..2ba8791 --- /dev/null +++ b/modules/hardware/timer/timer2_prescaler.c @@ -0,0 +1,46 @@ +/* + * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer2_prescaler.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#ifdef CONFIG_MODULE_TIMER_DYNAMIC + +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE +DEFINE_DYNAMIC_PRESCALER_FUNCS(2) +#endif + +#else + +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE +DEFINE_STATIC_PRESCALER_FUNCS(2) +#endif + +#endif + diff --git a/modules/hardware/timer/timer2_register_OC_at_tics.c b/modules/hardware/timer/timer2_register_OC_at_tics.c new file mode 100644 index 0000000..84c5c2b --- /dev/null +++ b/modules/hardware/timer/timer2_register_OC_at_tics.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer2_register_OC_at_tics.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2 +DEFINE_REGISTER_OC_INTR_AT_TICS(2) +#endif + diff --git a/modules/hardware/timer/timer2_register_OC_in_us.c b/modules/hardware/timer/timer2_register_OC_in_us.c new file mode 100644 index 0000000..dbe0f7a --- /dev/null +++ b/modules/hardware/timer/timer2_register_OC_in_us.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer2_register_OC_in_us.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2 +DEFINE_REGISTER_OC_INTR_IN_US(2,2) +#endif + diff --git a/modules/hardware/timer/timer2_register_OV.c b/modules/hardware/timer/timer2_register_OV.c new file mode 100644 index 0000000..3485565 --- /dev/null +++ b/modules/hardware/timer/timer2_register_OV.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer2_register_OV.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER2_ENABLED && defined SIG_OVERFLOW2 +DEFINE_REGISTER_OV_INTR(2) +#endif + diff --git a/modules/hardware/timer/timer2_startstop.c b/modules/hardware/timer/timer2_startstop.c new file mode 100644 index 0000000..4cb47e7 --- /dev/null +++ b/modules/hardware/timer/timer2_startstop.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer2_startstop.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> +#include <timer_config.h> + +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE +DEFINE_TIMER_START_STOP(2) +#endif + diff --git a/modules/hardware/timer/timer3_getset.c b/modules/hardware/timer/timer3_getset.c new file mode 100644 index 0000000..d23e4ad --- /dev/null +++ b/modules/hardware/timer/timer3_getset.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer3_getset.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_config.h> + +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE +DEFINE_TIMER_GET_SET(3) +#endif + diff --git a/modules/hardware/timer/timer3_prescaler.c b/modules/hardware/timer/timer3_prescaler.c new file mode 100644 index 0000000..c1a26d7 --- /dev/null +++ b/modules/hardware/timer/timer3_prescaler.c @@ -0,0 +1,46 @@ +/* + * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer3_prescaler.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#ifdef CONFIG_MODULE_TIMER_DYNAMIC + +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE +DEFINE_DYNAMIC_PRESCALER_FUNCS(3) +#endif + +#else + +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE +DEFINE_STATIC_PRESCALER_FUNCS(3) +#endif + +#endif + diff --git a/modules/hardware/timer/timer3_register_OC_at_tics.c b/modules/hardware/timer/timer3_register_OC_at_tics.c new file mode 100644 index 0000000..1af1df0 --- /dev/null +++ b/modules/hardware/timer/timer3_register_OC_at_tics.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer3_register_OC_at_tics.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER3A_ENABLED && defined SIG_OUTPUT_COMPARE3A +DEFINE_REGISTER_OC_INTR_AT_TICS(3A) +#endif + +#if defined TIMER3B_ENABLED && defined SIG_OUTPUT_COMPARE3B +DEFINE_REGISTER_OC_INTR_AT_TICS(3B) +#endif + +#if defined TIMER3C_ENABLED && defined SIG_OUTPUT_COMPARE3C +DEFINE_REGISTER_OC_INTR_AT_TICS(3C) +#endif + diff --git a/modules/hardware/timer/timer3_register_OC_in_us.c b/modules/hardware/timer/timer3_register_OC_in_us.c new file mode 100644 index 0000000..21c4e73 --- /dev/null +++ b/modules/hardware/timer/timer3_register_OC_in_us.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer3_register_OC_in_us.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER3A_ENABLED && defined SIG_OUTPUT_COMPARE3A +DEFINE_REGISTER_OC_INTR_IN_US(3,3A) +#endif + +#if defined TIMER3B_ENABLED && defined SIG_OUTPUT_COMPARE3B +DEFINE_REGISTER_OC_INTR_IN_US(3,3B) +#endif + +#if defined TIMER3C_ENABLED && defined SIG_OUTPUT_COMPARE3C +DEFINE_REGISTER_OC_INTR_IN_US(3,3C) +#endif + diff --git a/modules/hardware/timer/timer3_register_OV.c b/modules/hardware/timer/timer3_register_OV.c new file mode 100644 index 0000000..72232c8 --- /dev/null +++ b/modules/hardware/timer/timer3_register_OV.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer3_register_OV.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER3_ENABLED && defined SIG_OVERFLOW3 +DEFINE_REGISTER_OV_INTR(3) +#endif + diff --git a/modules/hardware/timer/timer3_startstop.c b/modules/hardware/timer/timer3_startstop.c new file mode 100644 index 0000000..f72bfb1 --- /dev/null +++ b/modules/hardware/timer/timer3_startstop.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer3_startstop.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> +#include <timer_config.h> + +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE +DEFINE_TIMER_START_STOP(3) +#endif + diff --git a/modules/hardware/timer/timer4_getset.c b/modules/hardware/timer/timer4_getset.c new file mode 100644 index 0000000..62ac7d5 --- /dev/null +++ b/modules/hardware/timer/timer4_getset.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer4_getset.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_config.h> + +#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE +DEFINE_TIMER_GET_SET(4) +#endif + diff --git a/modules/hardware/timer/timer4_prescaler.c b/modules/hardware/timer/timer4_prescaler.c new file mode 100644 index 0000000..f898756 --- /dev/null +++ b/modules/hardware/timer/timer4_prescaler.c @@ -0,0 +1,46 @@ +/* + * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer4_prescaler.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#ifdef CONFIG_MODULE_TIMER_DYNAMIC + +#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE +DEFINE_DYNAMIC_PRESCALER_FUNCS(4) +#endif + +#else + +#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE +DEFINE_STATIC_PRESCALER_FUNCS(4) +#endif + +#endif + diff --git a/modules/hardware/timer/timer4_register_OC_at_tics.c b/modules/hardware/timer/timer4_register_OC_at_tics.c new file mode 100644 index 0000000..02c3294 --- /dev/null +++ b/modules/hardware/timer/timer4_register_OC_at_tics.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer4_register_OC_at_tics.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER4A_ENABLED && defined SIG_OUTPUT_COMPARE4A +DEFINE_REGISTER_OC_INTR_AT_TICS(4A) +#endif + +#if defined TIMER4B_ENABLED && defined SIG_OUTPUT_COMPARE4B +DEFINE_REGISTER_OC_INTR_AT_TICS(4B) +#endif + +#if defined TIMER4C_ENABLED && defined SIG_OUTPUT_COMPARE4C +DEFINE_REGISTER_OC_INTR_AT_TICS(4C) +#endif + diff --git a/modules/hardware/timer/timer4_register_OC_in_us.c b/modules/hardware/timer/timer4_register_OC_in_us.c new file mode 100644 index 0000000..a52ba68 --- /dev/null +++ b/modules/hardware/timer/timer4_register_OC_in_us.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer4_register_OC_in_us.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER4A_ENABLED && defined SIG_OUTPUT_COMPARE4A +DEFINE_REGISTER_OC_INTR_IN_US(4,4A) +#endif + +#if defined TIMER4B_ENABLED && defined SIG_OUTPUT_COMPARE4B +DEFINE_REGISTER_OC_INTR_IN_US(4,4B) +#endif + +#if defined TIMER4C_ENABLED && defined SIG_OUTPUT_COMPARE4C +DEFINE_REGISTER_OC_INTR_IN_US(4,4C) +#endif + diff --git a/modules/hardware/timer/timer4_register_OV.c b/modules/hardware/timer/timer4_register_OV.c new file mode 100644 index 0000000..7fcb74e --- /dev/null +++ b/modules/hardware/timer/timer4_register_OV.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer4_register_OV.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER4_ENABLED && defined SIG_OVERFLOW4 +DEFINE_REGISTER_OV_INTR(4) +#endif + diff --git a/modules/hardware/timer/timer4_startstop.c b/modules/hardware/timer/timer4_startstop.c new file mode 100644 index 0000000..700f3bb --- /dev/null +++ b/modules/hardware/timer/timer4_startstop.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer4_startstop.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> +#include <timer_config.h> + +#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE +DEFINE_TIMER_START_STOP(4) +#endif + diff --git a/modules/hardware/timer/timer5_getset.c b/modules/hardware/timer/timer5_getset.c new file mode 100644 index 0000000..cdab3f3 --- /dev/null +++ b/modules/hardware/timer/timer5_getset.c @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer5_getset.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_config.h> + +#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE +DEFINE_TIMER_GET_SET(5) +#endif + diff --git a/modules/hardware/timer/timer5_prescaler.c b/modules/hardware/timer/timer5_prescaler.c new file mode 100644 index 0000000..25b8741 --- /dev/null +++ b/modules/hardware/timer/timer5_prescaler.c @@ -0,0 +1,46 @@ +/* + * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer5_prescaler.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#ifdef CONFIG_MODULE_TIMER_DYNAMIC + +#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE +DEFINE_DYNAMIC_PRESCALER_FUNCS(5) +#endif + +#else + +#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE +DEFINE_STATIC_PRESCALER_FUNCS(5) +#endif + +#endif + diff --git a/modules/hardware/timer/timer5_register_OC_at_tics.c b/modules/hardware/timer/timer5_register_OC_at_tics.c new file mode 100644 index 0000000..99eb009 --- /dev/null +++ b/modules/hardware/timer/timer5_register_OC_at_tics.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer5_register_OC_at_tics.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER5A_ENABLED && defined SIG_OUTPUT_COMPARE5A +DEFINE_REGISTER_OC_INTR_AT_TICS(5A) +#endif + +#if defined TIMER5B_ENABLED && defined SIG_OUTPUT_COMPARE5B +DEFINE_REGISTER_OC_INTR_AT_TICS(5B) +#endif + +#if defined TIMER5C_ENABLED && defined SIG_OUTPUT_COMPARE5C +DEFINE_REGISTER_OC_INTR_AT_TICS(5C) +#endif + diff --git a/modules/hardware/timer/timer5_register_OC_in_us.c b/modules/hardware/timer/timer5_register_OC_in_us.c new file mode 100644 index 0000000..a65154e --- /dev/null +++ b/modules/hardware/timer/timer5_register_OC_in_us.c @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer5_register_OC_in_us.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER5A_ENABLED && defined SIG_OUTPUT_COMPARE5A +DEFINE_REGISTER_OC_INTR_IN_US(5,5A) +#endif + +#if defined TIMER5B_ENABLED && defined SIG_OUTPUT_COMPARE5B +DEFINE_REGISTER_OC_INTR_IN_US(5,5B) +#endif + +#if defined TIMER5C_ENABLED && defined SIG_OUTPUT_COMPARE5C +DEFINE_REGISTER_OC_INTR_IN_US(5,5C) +#endif + diff --git a/modules/hardware/timer/timer5_register_OV.c b/modules/hardware/timer/timer5_register_OV.c new file mode 100644 index 0000000..b10ab02 --- /dev/null +++ b/modules/hardware/timer/timer5_register_OV.c @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer5_register_OV.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> +#include <timer_config.h> + + +#if defined TIMER5_ENABLED && defined SIG_OVERFLOW5 +DEFINE_REGISTER_OV_INTR(5) +#endif + diff --git a/modules/hardware/timer/timer5_startstop.c b/modules/hardware/timer/timer5_startstop.c new file mode 100644 index 0000000..ccdaf7f --- /dev/null +++ b/modules/hardware/timer/timer5_startstop.c @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer5_startstop.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> +#include <timer_config.h> + +#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE +DEFINE_TIMER_START_STOP(5) +#endif + diff --git a/modules/hardware/timer/timer_conf_check.c b/modules/hardware/timer/timer_conf_check.c new file mode 100644 index 0000000..9935b23 --- /dev/null +++ b/modules/hardware/timer/timer_conf_check.c @@ -0,0 +1,491 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_conf_check.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + + +#if defined TIMER0_ENABLED && ! defined TIMER0_AVAILABLE +#error This arch has no TIMER0 +#endif + +#if defined TIMER1_ENABLED && ! defined TIMER1_AVAILABLE +#error This arch has no TIMER1 +#endif + +#if defined TIMER2_ENABLED && ! defined TIMER2_AVAILABLE +#error This arch has no TIMER2 +#endif + +#if defined TIMER3_ENABLED && ! defined TIMER3_AVAILABLE +#error This arch has no TIMER3 +#endif + +#if defined TIMER4_ENABLED && ! defined TIMER4_AVAILABLE +#error This arch has no TIMER4 +#endif + +#if defined TIMER5_ENABLED && ! defined TIMER5_AVAILABLE +#error This arch has no TIMER5 +#endif + + +#if defined TIMER0_ENABLED + +#if defined TIMER0_PRESCALER_REG_0 && TIMER0_PRESCALER_REG_0 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_1 && TIMER0_PRESCALER_REG_1 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_2 && TIMER0_PRESCALER_REG_2 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_3 && TIMER0_PRESCALER_REG_3 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_4 && TIMER0_PRESCALER_REG_4 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_5 && TIMER0_PRESCALER_REG_5 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_6 && TIMER0_PRESCALER_REG_6 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_7 && TIMER0_PRESCALER_REG_7 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_8 && TIMER0_PRESCALER_REG_8 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_9 && TIMER0_PRESCALER_REG_9 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_10 && TIMER0_PRESCALER_REG_10 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_11 && TIMER0_PRESCALER_REG_11 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_12 && TIMER0_PRESCALER_REG_12 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_13 && TIMER0_PRESCALER_REG_13 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_14 && TIMER0_PRESCALER_REG_14 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#if defined TIMER0_PRESCALER_REG_15 && TIMER0_PRESCALER_REG_15 == TIMER0_PRESCALER_DIV +#define TIMER0_CONF_OK +#endif + +#ifndef TIMER0_CONF_OK +#error TIMER0 has a bad prescaler value +#endif + +#endif + + + +#if defined TIMER1_ENABLED + +#if defined TIMER1_PRESCALER_REG_0 && TIMER1_PRESCALER_REG_0 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_1 && TIMER1_PRESCALER_REG_1 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_2 && TIMER1_PRESCALER_REG_2 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_3 && TIMER1_PRESCALER_REG_3 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_4 && TIMER1_PRESCALER_REG_4 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_5 && TIMER1_PRESCALER_REG_5 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_6 && TIMER1_PRESCALER_REG_6 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_7 && TIMER1_PRESCALER_REG_7 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_8 && TIMER1_PRESCALER_REG_8 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_9 && TIMER1_PRESCALER_REG_9 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_10 && TIMER1_PRESCALER_REG_10 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_11 && TIMER1_PRESCALER_REG_11 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_12 && TIMER1_PRESCALER_REG_12 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_13 && TIMER1_PRESCALER_REG_13 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_14 && TIMER1_PRESCALER_REG_14 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#if defined TIMER1_PRESCALER_REG_15 && TIMER1_PRESCALER_REG_15 == TIMER1_PRESCALER_DIV +#define TIMER1_CONF_OK +#endif + +#ifndef TIMER1_CONF_OK +#error TIMER1 has a bad prescaler value +#endif + +#endif + + +#if defined TIMER2_ENABLED + +#if defined TIMER2_PRESCALER_REG_0 && TIMER2_PRESCALER_REG_0 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_1 && TIMER2_PRESCALER_REG_1 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_2 && TIMER2_PRESCALER_REG_2 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_3 && TIMER2_PRESCALER_REG_3 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_4 && TIMER2_PRESCALER_REG_4 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_5 && TIMER2_PRESCALER_REG_5 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_6 && TIMER2_PRESCALER_REG_6 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_7 && TIMER2_PRESCALER_REG_7 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_8 && TIMER2_PRESCALER_REG_8 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_9 && TIMER2_PRESCALER_REG_9 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_10 && TIMER2_PRESCALER_REG_10 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_11 && TIMER2_PRESCALER_REG_11 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_12 && TIMER2_PRESCALER_REG_12 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_13 && TIMER2_PRESCALER_REG_13 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_14 && TIMER2_PRESCALER_REG_14 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#if defined TIMER2_PRESCALER_REG_15 && TIMER2_PRESCALER_REG_15 == TIMER2_PRESCALER_DIV +#define TIMER2_CONF_OK +#endif + +#ifndef TIMER2_CONF_OK +#error TIMER2 has a bad prescaler value +#endif + +#endif + + +#if defined TIMER3_ENABLED + +#if defined TIMER3_PRESCALER_REG_0 && TIMER3_PRESCALER_REG_0 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_1 && TIMER3_PRESCALER_REG_1 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_2 && TIMER3_PRESCALER_REG_2 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_3 && TIMER3_PRESCALER_REG_3 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_4 && TIMER3_PRESCALER_REG_4 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_5 && TIMER3_PRESCALER_REG_5 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_6 && TIMER3_PRESCALER_REG_6 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_7 && TIMER3_PRESCALER_REG_7 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_8 && TIMER3_PRESCALER_REG_8 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_9 && TIMER3_PRESCALER_REG_9 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_10 && TIMER3_PRESCALER_REG_10 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_11 && TIMER3_PRESCALER_REG_11 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_12 && TIMER3_PRESCALER_REG_12 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_13 && TIMER3_PRESCALER_REG_13 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_14 && TIMER3_PRESCALER_REG_14 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#if defined TIMER3_PRESCALER_REG_15 && TIMER3_PRESCALER_REG_15 == TIMER3_PRESCALER_DIV +#define TIMER3_CONF_OK +#endif + +#ifndef TIMER3_CONF_OK +#error TIMER3 has a bad prescaler value +#endif + +#endif + +#if defined TIMER4_ENABLED + +#if defined TIMER4_PRESCALER_REG_0 && TIMER4_PRESCALER_REG_0 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_1 && TIMER4_PRESCALER_REG_1 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_2 && TIMER4_PRESCALER_REG_2 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_3 && TIMER4_PRESCALER_REG_3 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_4 && TIMER4_PRESCALER_REG_4 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_5 && TIMER4_PRESCALER_REG_5 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_6 && TIMER4_PRESCALER_REG_6 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_7 && TIMER4_PRESCALER_REG_7 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_8 && TIMER4_PRESCALER_REG_8 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_9 && TIMER4_PRESCALER_REG_9 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_10 && TIMER4_PRESCALER_REG_10 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_11 && TIMER4_PRESCALER_REG_11 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_12 && TIMER4_PRESCALER_REG_12 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_13 && TIMER4_PRESCALER_REG_13 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_14 && TIMER4_PRESCALER_REG_14 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#if defined TIMER4_PRESCALER_REG_15 && TIMER4_PRESCALER_REG_15 == TIMER4_PRESCALER_DIV +#define TIMER4_CONF_OK +#endif + +#ifndef TIMER4_CONF_OK +#error TIMER4 has a bad prescaler value +#endif + +#endif + +#if defined TIMER5_ENABLED + +#if defined TIMER5_PRESCALER_REG_0 && TIMER5_PRESCALER_REG_0 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_1 && TIMER5_PRESCALER_REG_1 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_2 && TIMER5_PRESCALER_REG_2 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_3 && TIMER5_PRESCALER_REG_3 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_4 && TIMER5_PRESCALER_REG_4 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_5 && TIMER5_PRESCALER_REG_5 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_6 && TIMER5_PRESCALER_REG_6 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_7 && TIMER5_PRESCALER_REG_7 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_8 && TIMER5_PRESCALER_REG_8 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_9 && TIMER5_PRESCALER_REG_9 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_10 && TIMER5_PRESCALER_REG_10 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_11 && TIMER5_PRESCALER_REG_11 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_12 && TIMER5_PRESCALER_REG_12 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_13 && TIMER5_PRESCALER_REG_13 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_14 && TIMER5_PRESCALER_REG_14 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#if defined TIMER5_PRESCALER_REG_15 && TIMER5_PRESCALER_REG_15 == TIMER5_PRESCALER_DIV +#define TIMER5_CONF_OK +#endif + +#ifndef TIMER5_CONF_OK +#error TIMER5 has a bad prescaler value +#endif + +#endif + diff --git a/modules/hardware/timer/timer_declarations.h b/modules/hardware/timer/timer_declarations.h new file mode 100644 index 0000000..e3de549 --- /dev/null +++ b/modules/hardware/timer/timer_declarations.h @@ -0,0 +1,94 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_declarations.h,v 1.1.2.2 2006-12-04 23:48:22 zer0 Exp $ + * + */ + +#ifndef _TIMER_DECLARATIONS_H +#define _TIMER_DECLARATIONS_H_ + +#define DECLARE_TIMER_FUNCS(x) \ + \ +/** start the timer at initial prescaler */ \ +void timer##x##_start(void); \ + \ +/** stop the timer */ \ +void timer##x##_stop(void); \ + \ +/** Set the timer value */ \ +void timer##x##_set(uint16_t t); \ + \ +/** return the value of the timer */ \ +uint16_t timer##x##_get(void); \ + \ + \ +/** Enable overflow interruption, and register a function to be called */ \ +/* every interrupt. If func is NULL, unregisters interrupt. */ \ +void timer##x##_register_OV_intr(void (*func)(void)); \ + \ +/** Enable output compare interruption, and register a function to be */ \ +/* called every output compare interrupt. Note that interruption */ \ +/* will occur when the timer will reach the same value than t. If */ \ +/* func is NULL, unregisters interrupt (other arg is useless). */ \ +void timer##x##A_register_OC_intr_at_tics(void (*func)(void), uint16_t t); \ +void timer##x##B_register_OC_intr_at_tics(void (*func)(void), uint16_t t); \ +void timer##x##C_register_OC_intr_at_tics(void (*func)(void), uint16_t t); \ + \ +/** Enable output compare interruption, and register a function to be */ \ +/* called every output compare interrupt. Note that interruption */ \ +/* will occur when the timer will reach CURRENT_TIMER + t_us */ \ +/* (parameter is in microseconds). If func is NULL, unregisters */ \ +/* interrupt (other arg is useless). return 0 on success */ \ +/* WARNING : this function can be slower due to float conversion */ \ +/* If you are in static timer mode (no dynamic modifications of */ \ +/* the prescaler), and if your value is a constant, you should use */ \ +/* a code like this to allow beeing optmized by the preprocessor: */ \ +/* timerxy_register_OC_intr_in_tics(timerx_us_to_tics(1000)); */ \ +/* Indeed this code is optimized. In any case, it is better to */ \ +/* them in 2 separated funcs, because you can save the result of */ \ +/* timerx_us_to_tics() in a variable. */ \ +int8_t timer##x##A_register_OC_intr_in_us(void (*func)(void), uint16_t t); \ +int8_t timer##x##B_register_OC_intr_in_us(void (*func)(void), uint16_t t); \ +int8_t timer##x##C_register_OC_intr_in_us(void (*func)(void), uint16_t t); \ + \ +/** Return current prescaler divisor. If CONFIG_MODULE_TIMER_DYNAMIC */ \ +/* is not defined, it only returns TIMERX_PRESCALER specified in */ \ +/* configuration. If you use a dynamic configuration, it reads the */ \ +/* current prescaler register value and converts it to divisor */ \ +/* value. */ \ +uint16_t timer##x##_get_prescaler_div(void); \ + \ +/** Configure the prescaler register depending on divisor param. */ \ +/* only defined if CONFIG_MODULE_TIMER_DYNAMIC is 'y' */ \ +void timer##x##_set_prescaler_div(uint16_t); \ + \ +/** Use timerX_get_prescaler_div() and CONFIG_QUARTZ to do the */ \ +/* conversion from microseconds to tics (timer unit) */ \ +/* Be carreful, this function is inline static, so if you use it */ \ +/* quite often, you should include it in a standard function and call */ \ +/* this function instead */ \ +static inline float timer##x##_us_to_tics(float us); \ + \ +/** Use timerX_get_prescaler_div() and CONFIG_QUARTZ to do the */ \ +/* conversion from tics to microseconds */ \ +/* Be carreful, this function is inline static, so if you use it */ \ +/* quite often, you should include it in a standard function and call */ \ +/* this function instead */ \ +static inline float timer##x##_tics_to_us(float t); + +#endif diff --git a/modules/hardware/timer/timer_definitions.h b/modules/hardware/timer/timer_definitions.h new file mode 100644 index 0000000..6bd1c1f --- /dev/null +++ b/modules/hardware/timer/timer_definitions.h @@ -0,0 +1,190 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_definitions.h,v 1.1.2.5 2009-04-07 20:00:46 zer0 Exp $ + * + */ + +#ifndef _TIMER_DEFINITIONS_H_ +#define _TIMER_DEFINITIONS_H_ + +/* needed by nearly all .c */ +#include <aversive/parts.h> + +#define DEFINE_TIMER_START_STOP(x) \ + \ +/** start the timer */ \ +void timer##x##_start(void) \ +{ \ + TCNT##x = 0; \ + CS##x##0_REG = __timer##x##_div_to_reg(TIMER##x##_PRESCALER_DIV) << CS##x##0 ; \ +} \ + \ +/** stop the timer */ \ +void timer##x##_stop(void) \ +{ \ + CS##x##0_REG = 0; \ + TCNT##x = 0; \ +} + + + +#define DEFINE_TIMER_GET_SET(x) \ + \ +uint16_t timer##x##_get(void) \ +{ \ + return TCNT##x ; \ +} \ + \ +void timer##x##_set(uint16_t t) \ +{ \ + TCNT##x = t; \ +} + + +#define DEFINE_OV_INTR(x) \ +SIGNAL(x) \ +{ \ + if(timer_OV_callback_table[x##_NUM]) \ + timer_OV_callback_table[x##_NUM](); \ +} + + +#define DEFINE_OC_INTR(x) \ +SIGNAL(x) \ +{ \ + if(timer_OC_callback_table[x##_NUM]) \ + timer_OC_callback_table[x##_NUM](); \ +} + + +#define DEFINE_REGISTER_OV_INTR(x) \ + \ +void timer##x##_register_OV_intr(void (*func)(void)) \ +{ \ + uint8_t flags; \ + \ + IRQ_LOCK(flags); \ + timer_OV_callback_table[SIG_OVERFLOW##x##_NUM] = func; \ + if (func) { \ + TOIE##x##_REG |= (1<<TOIE##x); \ + } \ + else { \ + TOIE##x##_REG &= (uint8_t)(~(1<<TOIE##x)); \ + } \ + IRQ_UNLOCK(flags); \ +} + + +#define DEFINE_REGISTER_OC_INTR_AT_TICS(x) \ + \ +void timer##x##_register_OC_intr_at_tics(void (*func)(void), uint16_t t) \ +{ \ + uint8_t flags; \ + \ + IRQ_LOCK(flags); \ + timer_OC_callback_table[SIG_OUTPUT_COMPARE##x##_NUM] = func; \ + if (func) { \ + OCIE##x##_REG |= (1<<OCIE##x); \ + OCR##x = t; \ + } \ + else { \ + OCIE##x##_REG &= (uint8_t)(~(1<<OCIE##x)); \ + } \ + IRQ_UNLOCK(flags); \ +} + + +#define DEFINE_REGISTER_OC_INTR_IN_US(x,y) \ + \ +int8_t timer##y##_register_OC_intr_in_us(void (*func)(void), uint16_t t) \ +{ \ + uint8_t flags; \ + float tics; \ + \ + IRQ_LOCK(flags); \ + if (! func) { \ + timer_OC_callback_table[SIG_OUTPUT_COMPARE##y##_NUM] = func; \ + OCIE##y##_REG &= (uint8_t)(~(1<<OCIE##y)); \ + IRQ_UNLOCK(flags); \ + return 0; \ + } \ + \ + tics = timer##x##_us_to_tics(t); \ + if ( tics > 0xFFFF ) { /* XXX use MAX_TIMER */ \ + IRQ_UNLOCK(flags); \ + return -1; \ + } \ + \ + OCR##y = TCNT##x + tics; \ + timer_OC_callback_table[SIG_OUTPUT_COMPARE##y##_NUM] = func; \ + OCIE##y##_REG |= (1<<OCIE##y); \ + IRQ_UNLOCK(flags); \ + return 0; \ +} + + +#define DEFINE_DYNAMIC_PRESCALER_FUNCS(x) \ + \ +int16_t timer##x##_div_to_reg(uint16_t div) \ +{ \ + return __timer##x##_div_to_reg(div); \ +} \ + \ +int16_t timer##x##_reg_to_div(uint8_t reg) \ +{ \ + return __timer##x##_reg_to_div(reg); \ +} \ + \ +uint16_t timer##x##_get_prescaler_div(void) \ +{ \ + return __timer##x##_reg_to_div(CS##x##0_REG >> CS##x##0); \ +} \ + \ +void timer##x##_set_prescaler_div(uint16_t div) \ +{ \ + CS##x##0_REG = __timer##x##_div_to_reg(div) << CS##x##0 ; \ +} + + +#define DEFINE_STATIC_PRESCALER_FUNCS(x) \ + \ +int16_t timer##x##_div_to_reg(__attribute__((unused)) uint16_t div) \ +{ \ + return __timer##x##_div_to_reg(TIMER##x##_PRESCALER_DIV); \ +} \ + \ +uint16_t timer##x##_get_prescaler_div(void) \ +{ \ + return TIMER##x##_PRESCALER_DIV; \ +} + +#define DEFINE_TIMER_US_CONVERSIONS(x) \ + \ +static inline float timer##x##_us_to_tics(float us) \ +{ \ + return ((float)CONFIG_QUARTZ / \ + ((float)MHz * timer##x##_get_prescaler_div()) ) * us; \ +} \ + \ +static inline float timer##x##_tics_to_us(float t) \ +{ \ + return t / ((float)CONFIG_QUARTZ / \ + ((float)MHz * timer##x##_get_prescaler_div()) ); \ +} + +#endif diff --git a/modules/hardware/timer/timer_init.c b/modules/hardware/timer/timer_init.c new file mode 100644 index 0000000..4b96b71 --- /dev/null +++ b/modules/hardware/timer/timer_init.c @@ -0,0 +1,62 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_init.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <aversive/timers.h> +#include <timer.h> +#include <timer_intr.h> +#include <timer_prescaler.h> + +#include <timer_config.h> + +/** Init of all timers with static configutaion (see timer_config.h) */ +void timer_init(void) +{ + uint8_t flags; + + IRQ_LOCK(flags); + timer_intr_init(); + +#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE + CS00_REG = __timer0_div_to_reg(TIMER0_PRESCALER_DIV) << CS00 ; + TCNT0 = 0; +#endif +#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE + CS10_REG = __timer1_div_to_reg(TIMER1_PRESCALER_DIV) << CS10 ; + TCNT1 = 0; +#endif +#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE + CS20_REG = __timer2_div_to_reg(TIMER2_PRESCALER_DIV) << CS20 ; + TCNT2 = 0; +#endif +#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE + CS30_REG = __timer3_div_to_reg(TIMER3_PRESCALER_DIV) << CS30 ; + TCNT3 = 0; +#endif +#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE + CS40_REG = __timer4_div_to_reg(TIMER4_PRESCALER_DIV) << CS40 ; + TCNT4 = 0; +#endif +#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE + CS50_REG = __timer5_div_to_reg(TIMER5_PRESCALER_DIV) << CS50 ; + TCNT5 = 0; +#endif + IRQ_UNLOCK(flags); +} diff --git a/modules/hardware/timer/timer_intr.c b/modules/hardware/timer/timer_intr.c new file mode 100644 index 0000000..33e6870 --- /dev/null +++ b/modules/hardware/timer/timer_intr.c @@ -0,0 +1,152 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_intr.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#include <stdint.h> +#include <string.h> + +#include <aversive/timers.h> + +#include <timer.h> +#include <timer_definitions.h> +#include <timer_intr.h> + +#include <timer_config.h> + +volatile timer_callback_t timer_OV_callback_table[SIG_OVERFLOW_TOTAL_NUM]; +volatile timer_callback_t timer_OC_callback_table[SIG_OUTPUT_COMPARE_TOTAL_NUM]; + +/*************************/ + +#if defined TIMER0_ENABLED && defined SIG_OVERFLOW0 +DEFINE_OV_INTR(SIG_OVERFLOW0) +#endif + +#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0 +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE0) +#endif + +#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0A +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE0A) +#endif + +#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0B +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE0B) +#endif + +/*************************/ + +#if defined TIMER1_ENABLED && defined SIG_OVERFLOW1 +DEFINE_OV_INTR(SIG_OVERFLOW1) +#endif + +#if defined TIMER1A_ENABLED && defined SIG_OUTPUT_COMPARE1A +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE1A) +#endif + +#if defined TIMER1B_ENABLED && defined SIG_OUTPUT_COMPARE1B +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE1B) +#endif + +#if defined TIMER1C_ENABLED && defined SIG_OUTPUT_COMPARE1C +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE1C) +#endif + +/*************************/ + +#if defined TIMER2_ENABLED && defined SIG_OVERFLOW2 +DEFINE_OV_INTR(SIG_OVERFLOW2) +#endif + +#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2 +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE2) +#endif + +#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2A +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE2A) +#endif + +#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2B +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE2B) +#endif + +/*************************/ + +#if defined TIMER3_ENABLED && defined SIG_OVERFLOW3 +DEFINE_OV_INTR(SIG_OVERFLOW3) +#endif + +#if defined TIMER3A_ENABLED && defined SIG_OUTPUT_COMPARE3A +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE3A) +#endif + +#if defined TIMER3B_ENABLED && defined SIG_OUTPUT_COMPARE3B +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE3B) +#endif + +#if defined TIMER3C_ENABLED && defined SIG_OUTPUT_COMPARE3C +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE3C) +#endif + +/*************************/ + +#if defined TIMER4_ENABLED && defined SIG_OVERFLOW4 +DEFINE_OV_INTR(SIG_OVERFLOW4) +#endif + +#if defined TIMER4A_ENABLED && defined SIG_OUTPUT_COMPARE4A +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE4A) +#endif + +#if defined TIMER4B_ENABLED && defined SIG_OUTPUT_COMPARE4B +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE4B) +#endif + +#if defined TIMER4C_ENABLED && defined SIG_OUTPUT_COMPARE4C +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE4C) +#endif + +/*************************/ + +#if defined TIMER5_ENABLED && defined SIG_OVERFLOW5 +DEFINE_OV_INTR(SIG_OVERFLOW5) +#endif + +#if defined TIMER5A_ENABLED && defined SIG_OUTPUT_COMPARE5A +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE5A) +#endif + +#if defined TIMER5B_ENABLED && defined SIG_OUTPUT_COMPARE5B +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE5B) +#endif + +#if defined TIMER5C_ENABLED && defined SIG_OUTPUT_COMPARE5C +DEFINE_OC_INTR(SIG_OUTPUT_COMPARE5C) +#endif + +/*************************/ + +void timer_intr_init(void) +{ + memset((void*)timer_OV_callback_table, 0, sizeof(timer_OV_callback_table)); + memset((void*)timer_OC_callback_table, 0, sizeof(timer_OC_callback_table)); +} + + diff --git a/modules/hardware/timer/timer_intr.h b/modules/hardware/timer/timer_intr.h new file mode 100644 index 0000000..e14afb6 --- /dev/null +++ b/modules/hardware/timer/timer_intr.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_intr.h,v 1.1.2.3 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +#include <aversive/parts.h> + +typedef void (*timer_callback_t)(void); + +extern volatile timer_callback_t timer_OV_callback_table[SIG_OVERFLOW_TOTAL_NUM]; +extern volatile timer_callback_t timer_OC_callback_table[SIG_OUTPUT_COMPARE_TOTAL_NUM]; + +/* initialisation of callback table */ +void timer_intr_init(void); diff --git a/modules/hardware/timer/timer_prescaler.h b/modules/hardware/timer/timer_prescaler.h new file mode 100644 index 0000000..e30e34b --- /dev/null +++ b/modules/hardware/timer/timer_prescaler.h @@ -0,0 +1,1113 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_prescaler.h,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $ + * + */ + +#ifndef _TIMER_PRESCALER_H_ +#define _TIMER_PRESCALER_H_ + +/* return <0 on error, else return reg value */ +/* This static inline function is very optimized if div is + * a constant */ +static inline int16_t __timer0_div_to_reg(uint16_t div) +{ + switch(div) { +#if defined TIMER0_PRESCALER_REG_0 && TIMER0_PRESCALER_REG_0 >= 0 + case TIMER0_PRESCALER_REG_0: + return 0; +#endif + +#if defined TIMER0_PRESCALER_REG_1 && TIMER0_PRESCALER_REG_1 >= 0 + case TIMER0_PRESCALER_REG_1: + return 1; +#endif + +#if defined TIMER0_PRESCALER_REG_2 && TIMER0_PRESCALER_REG_2 >= 0 + case TIMER0_PRESCALER_REG_2: + return 2; +#endif + +#if defined TIMER0_PRESCALER_REG_3 && TIMER0_PRESCALER_REG_3 >= 0 + case TIMER0_PRESCALER_REG_3: + return 3; +#endif + +#if defined TIMER0_PRESCALER_REG_4 && TIMER0_PRESCALER_REG_4 >= 0 + case TIMER0_PRESCALER_REG_4: + return 4; +#endif + +#if defined TIMER0_PRESCALER_REG_5 && TIMER0_PRESCALER_REG_5 >= 0 + case TIMER0_PRESCALER_REG_5: + return 5; +#endif + +#if defined TIMER0_PRESCALER_REG_6 && TIMER0_PRESCALER_REG_6 >= 0 + case TIMER0_PRESCALER_REG_6: + return 6; +#endif + +#if defined TIMER0_PRESCALER_REG_7 && TIMER0_PRESCALER_REG_7 >= 0 + case TIMER0_PRESCALER_REG_7: + return 7; +#endif + +#if defined TIMER0_PRESCALER_REG_8 && TIMER0_PRESCALER_REG_8 >= 0 + case TIMER0_PRESCALER_REG_8: + return 8; +#endif + +#if defined TIMER0_PRESCALER_REG_9 && TIMER0_PRESCALER_REG_9 >= 0 + case TIMER0_PRESCALER_REG_9: + return 9; +#endif + +#if defined TIMER0_PRESCALER_REG_10 && TIMER0_PRESCALER_REG_10 >= 0 + case TIMER0_PRESCALER_REG_10: + return 10; +#endif + +#if defined TIMER0_PRESCALER_REG_11 && TIMER0_PRESCALER_REG_11 >= 0 + case TIMER0_PRESCALER_REG_11: + return 11; +#endif + +#if defined TIMER0_PRESCALER_REG_12 && TIMER0_PRESCALER_REG_12 >= 0 + case TIMER0_PRESCALER_REG_12: + return 12; +#endif + +#if defined TIMER0_PRESCALER_REG_13 && TIMER0_PRESCALER_REG_13 >= 0 + case TIMER0_PRESCALER_REG_13: + return 13; +#endif + +#if defined TIMER0_PRESCALER_REG_14 && TIMER0_PRESCALER_REG_14 >= 0 + case TIMER0_PRESCALER_REG_14: + return 14; +#endif + +#if defined TIMER0_PRESCALER_REG_15 && TIMER0_PRESCALER_REG_15 >= 0 + case TIMER0_PRESCALER_REG_15: + return 15; +#endif + default: + return -1; + } +} + +/* return <0 on error, else return div value */ +/* This static inline function is very optimized if reg is + * a constant */ +static inline int16_t __timer0_reg_to_div(uint8_t reg) +{ + switch(reg) { +#if defined TIMER0_PRESCALER_DIV_0 + case TIMER0_PRESCALER_DIV_0: + return 0; +#endif + +#if defined TIMER0_PRESCALER_DIV_1 + case TIMER0_PRESCALER_DIV_1: + return 1; +#endif + +#if defined TIMER0_PRESCALER_DIV_2 + case TIMER0_PRESCALER_DIV_2: + return 2; +#endif + +#if defined TIMER0_PRESCALER_DIV_4 + case TIMER0_PRESCALER_DIV_4: + return 4; +#endif + +#if defined TIMER0_PRESCALER_DIV_8 + case TIMER0_PRESCALER_DIV_8: + return 8; +#endif + +#if defined TIMER0_PRESCALER_DIV_16 + case TIMER0_PRESCALER_DIV_16: + return 16; +#endif + +#if defined TIMER0_PRESCALER_DIV_32 + case TIMER0_PRESCALER_DIV_32: + return 32; +#endif + +#if defined TIMER0_PRESCALER_DIV_64 + case TIMER0_PRESCALER_DIV_64: + return 64; +#endif + +#if defined TIMER0_PRESCALER_DIV_128 + case TIMER0_PRESCALER_DIV_128: + return 128; +#endif + +#if defined TIMER0_PRESCALER_DIV_256 + case TIMER0_PRESCALER_DIV_256: + return 256; +#endif + +#if defined TIMER0_PRESCALER_DIV_512 + case TIMER0_PRESCALER_DIV_512: + return 512; +#endif + +#if defined TIMER0_PRESCALER_DIV_1024 + case TIMER0_PRESCALER_DIV_1024: + return 1024; +#endif + +#if defined TIMER0_PRESCALER_DIV_2048 + case TIMER0_PRESCALER_DIV_2048: + return 2048; +#endif + +#if defined TIMER0_PRESCALER_DIV_4096 + case TIMER0_PRESCALER_DIV_4096: + return 4096; +#endif + +#if defined TIMER0_PRESCALER_DIV_8192 + case TIMER0_PRESCALER_DIV_8192: + return 8192; +#endif + +#if defined TIMER0_PRESCALER_DIV_16384 + case TIMER0_PRESCALER_DIV_16384: + return 16384; +#endif + + default: + return -1; + } +} + + +/* return <0 on error, else return reg value */ +/* This static inline function is very optimized if div is + * a constant */ +static inline int16_t __timer1_div_to_reg(uint16_t div) +{ + switch(div) { +#if defined TIMER1_PRESCALER_REG_0 && TIMER1_PRESCALER_REG_0 >= 0 + case TIMER1_PRESCALER_REG_0: + return 0; +#endif + +#if defined TIMER1_PRESCALER_REG_1 && TIMER1_PRESCALER_REG_1 >= 0 + case TIMER1_PRESCALER_REG_1: + return 1; +#endif + +#if defined TIMER1_PRESCALER_REG_2 && TIMER1_PRESCALER_REG_2 >= 0 + case TIMER1_PRESCALER_REG_2: + return 2; +#endif + +#if defined TIMER1_PRESCALER_REG_3 && TIMER1_PRESCALER_REG_3 >= 0 + case TIMER1_PRESCALER_REG_3: + return 3; +#endif + +#if defined TIMER1_PRESCALER_REG_4 && TIMER1_PRESCALER_REG_4 >= 0 + case TIMER1_PRESCALER_REG_4: + return 4; +#endif + +#if defined TIMER1_PRESCALER_REG_5 && TIMER1_PRESCALER_REG_5 >= 0 + case TIMER1_PRESCALER_REG_5: + return 5; +#endif + +#if defined TIMER1_PRESCALER_REG_6 && TIMER1_PRESCALER_REG_6 >= 0 + case TIMER1_PRESCALER_REG_6: + return 6; +#endif + +#if defined TIMER1_PRESCALER_REG_7 && TIMER1_PRESCALER_REG_7 >= 0 + case TIMER1_PRESCALER_REG_7: + return 7; +#endif + +#if defined TIMER1_PRESCALER_REG_8 && TIMER1_PRESCALER_REG_8 >= 0 + case TIMER1_PRESCALER_REG_8: + return 8; +#endif + +#if defined TIMER1_PRESCALER_REG_9 && TIMER1_PRESCALER_REG_9 >= 0 + case TIMER1_PRESCALER_REG_9: + return 9; +#endif + +#if defined TIMER1_PRESCALER_REG_10 && TIMER1_PRESCALER_REG_10 >= 0 + case TIMER1_PRESCALER_REG_10: + return 10; +#endif + +#if defined TIMER1_PRESCALER_REG_11 && TIMER1_PRESCALER_REG_11 >= 0 + case TIMER1_PRESCALER_REG_11: + return 11; +#endif + +#if defined TIMER1_PRESCALER_REG_12 && TIMER1_PRESCALER_REG_12 >= 0 + case TIMER1_PRESCALER_REG_12: + return 12; +#endif + +#if defined TIMER1_PRESCALER_REG_13 && TIMER1_PRESCALER_REG_13 >= 0 + case TIMER1_PRESCALER_REG_13: + return 13; +#endif + +#if defined TIMER1_PRESCALER_REG_14 && TIMER1_PRESCALER_REG_14 >= 0 + case TIMER1_PRESCALER_REG_14: + return 14; +#endif + +#if defined TIMER1_PRESCALER_REG_15 && TIMER1_PRESCALER_REG_15 >= 0 + case TIMER1_PRESCALER_REG_15: + return 15; +#endif + default: + return -1; + } +} + +/* return <0 on error, else return div value */ +/* This static inline function is very optimized if reg is + * a constant */ +static inline int16_t __timer1_reg_to_div(uint8_t reg) +{ + switch(reg) { +#if defined TIMER1_PRESCALER_DIV_0 + case TIMER1_PRESCALER_DIV_0: + return 0; +#endif + +#if defined TIMER1_PRESCALER_DIV_1 + case TIMER1_PRESCALER_DIV_1: + return 1; +#endif + +#if defined TIMER1_PRESCALER_DIV_2 + case TIMER1_PRESCALER_DIV_2: + return 2; +#endif + +#if defined TIMER1_PRESCALER_DIV_4 + case TIMER1_PRESCALER_DIV_4: + return 4; +#endif + +#if defined TIMER1_PRESCALER_DIV_8 + case TIMER1_PRESCALER_DIV_8: + return 8; +#endif + +#if defined TIMER1_PRESCALER_DIV_16 + case TIMER1_PRESCALER_DIV_16: + return 16; +#endif + +#if defined TIMER1_PRESCALER_DIV_32 + case TIMER1_PRESCALER_DIV_32: + return 32; +#endif + +#if defined TIMER1_PRESCALER_DIV_64 + case TIMER1_PRESCALER_DIV_64: + return 64; +#endif + +#if defined TIMER1_PRESCALER_DIV_128 + case TIMER1_PRESCALER_DIV_128: + return 128; +#endif + +#if defined TIMER1_PRESCALER_DIV_256 + case TIMER1_PRESCALER_DIV_256: + return 256; +#endif + +#if defined TIMER1_PRESCALER_DIV_512 + case TIMER1_PRESCALER_DIV_512: + return 512; +#endif + +#if defined TIMER1_PRESCALER_DIV_1024 + case TIMER1_PRESCALER_DIV_1024: + return 1024; +#endif + +#if defined TIMER1_PRESCALER_DIV_2048 + case TIMER1_PRESCALER_DIV_2048: + return 2048; +#endif + +#if defined TIMER1_PRESCALER_DIV_4096 + case TIMER1_PRESCALER_DIV_4096: + return 4096; +#endif + +#if defined TIMER1_PRESCALER_DIV_8192 + case TIMER1_PRESCALER_DIV_8192: + return 8192; +#endif + +#if defined TIMER1_PRESCALER_DIV_16384 + case TIMER1_PRESCALER_DIV_16384: + return 16384; +#endif + + default: + return -1; + } +} + + + +/* return <0 on error, else return reg value */ +/* This static inline function is very optimized if div is + * a constant */ +static inline int16_t __timer2_div_to_reg(uint16_t div) +{ + switch(div) { +#if defined TIMER2_PRESCALER_REG_0 && TIMER2_PRESCALER_REG_0 >= 0 + case TIMER2_PRESCALER_REG_0: + return 0; +#endif + +#if defined TIMER2_PRESCALER_REG_1 && TIMER2_PRESCALER_REG_1 >= 0 + case TIMER2_PRESCALER_REG_1: + return 1; +#endif + +#if defined TIMER2_PRESCALER_REG_2 && TIMER2_PRESCALER_REG_2 >= 0 + case TIMER2_PRESCALER_REG_2: + return 2; +#endif + +#if defined TIMER2_PRESCALER_REG_3 && TIMER2_PRESCALER_REG_3 >= 0 + case TIMER2_PRESCALER_REG_3: + return 3; +#endif + +#if defined TIMER2_PRESCALER_REG_4 && TIMER2_PRESCALER_REG_4 >= 0 + case TIMER2_PRESCALER_REG_4: + return 4; +#endif + +#if defined TIMER2_PRESCALER_REG_5 && TIMER2_PRESCALER_REG_5 >= 0 + case TIMER2_PRESCALER_REG_5: + return 5; +#endif + +#if defined TIMER2_PRESCALER_REG_6 && TIMER2_PRESCALER_REG_6 >= 0 + case TIMER2_PRESCALER_REG_6: + return 6; +#endif + +#if defined TIMER2_PRESCALER_REG_7 && TIMER2_PRESCALER_REG_7 >= 0 + case TIMER2_PRESCALER_REG_7: + return 7; +#endif + +#if defined TIMER2_PRESCALER_REG_8 && TIMER2_PRESCALER_REG_8 >= 0 + case TIMER2_PRESCALER_REG_8: + return 8; +#endif + +#if defined TIMER2_PRESCALER_REG_9 && TIMER2_PRESCALER_REG_9 >= 0 + case TIMER2_PRESCALER_REG_9: + return 9; +#endif + +#if defined TIMER2_PRESCALER_REG_10 && TIMER2_PRESCALER_REG_10 >= 0 + case TIMER2_PRESCALER_REG_10: + return 10; +#endif + +#if defined TIMER2_PRESCALER_REG_11 && TIMER2_PRESCALER_REG_11 >= 0 + case TIMER2_PRESCALER_REG_11: + return 11; +#endif + +#if defined TIMER2_PRESCALER_REG_12 && TIMER2_PRESCALER_REG_12 >= 0 + case TIMER2_PRESCALER_REG_12: + return 12; +#endif + +#if defined TIMER2_PRESCALER_REG_13 && TIMER2_PRESCALER_REG_13 >= 0 + case TIMER2_PRESCALER_REG_13: + return 13; +#endif + +#if defined TIMER2_PRESCALER_REG_14 && TIMER2_PRESCALER_REG_14 >= 0 + case TIMER2_PRESCALER_REG_14: + return 14; +#endif + +#if defined TIMER2_PRESCALER_REG_15 && TIMER2_PRESCALER_REG_15 >= 0 + case TIMER2_PRESCALER_REG_15: + return 15; +#endif + default: + return -1; + } +} + +/* return <0 on error, else return div value */ +/* This static inline function is very optimized if reg is + * a constant */ +static inline int16_t __timer2_reg_to_div(uint8_t reg) +{ + switch(reg) { +#if defined TIMER2_PRESCALER_DIV_0 + case TIMER2_PRESCALER_DIV_0: + return 0; +#endif + +#if defined TIMER2_PRESCALER_DIV_1 + case TIMER2_PRESCALER_DIV_1: + return 1; +#endif + +#if defined TIMER2_PRESCALER_DIV_2 + case TIMER2_PRESCALER_DIV_2: + return 2; +#endif + +#if defined TIMER2_PRESCALER_DIV_4 + case TIMER2_PRESCALER_DIV_4: + return 4; +#endif + +#if defined TIMER2_PRESCALER_DIV_8 + case TIMER2_PRESCALER_DIV_8: + return 8; +#endif + +#if defined TIMER2_PRESCALER_DIV_16 + case TIMER2_PRESCALER_DIV_16: + return 16; +#endif + +#if defined TIMER2_PRESCALER_DIV_32 + case TIMER2_PRESCALER_DIV_32: + return 32; +#endif + +#if defined TIMER2_PRESCALER_DIV_64 + case TIMER2_PRESCALER_DIV_64: + return 64; +#endif + +#if defined TIMER2_PRESCALER_DIV_128 + case TIMER2_PRESCALER_DIV_128: + return 128; +#endif + +#if defined TIMER2_PRESCALER_DIV_256 + case TIMER2_PRESCALER_DIV_256: + return 256; +#endif + +#if defined TIMER2_PRESCALER_DIV_512 + case TIMER2_PRESCALER_DIV_512: + return 512; +#endif + +#if defined TIMER2_PRESCALER_DIV_1024 + case TIMER2_PRESCALER_DIV_1024: + return 1024; +#endif + +#if defined TIMER2_PRESCALER_DIV_2048 + case TIMER2_PRESCALER_DIV_2048: + return 2048; +#endif + +#if defined TIMER2_PRESCALER_DIV_4096 + case TIMER2_PRESCALER_DIV_4096: + return 4096; +#endif + +#if defined TIMER2_PRESCALER_DIV_8192 + case TIMER2_PRESCALER_DIV_8192: + return 8192; +#endif + +#if defined TIMER2_PRESCALER_DIV_16384 + case TIMER2_PRESCALER_DIV_16384: + return 16384; +#endif + + default: + return -1; + } +} + + + +/* return <0 on error, else return reg value */ +/* This static inline function is very optimized if div is + * a constant */ +static inline int16_t __timer3_div_to_reg(uint16_t div) +{ + switch(div) { +#if defined TIMER3_PRESCALER_REG_0 && TIMER3_PRESCALER_REG_0 >= 0 + case TIMER3_PRESCALER_REG_0: + return 0; +#endif + +#if defined TIMER3_PRESCALER_REG_1 && TIMER3_PRESCALER_REG_1 >= 0 + case TIMER3_PRESCALER_REG_1: + return 1; +#endif + +#if defined TIMER3_PRESCALER_REG_2 && TIMER3_PRESCALER_REG_2 >= 0 + case TIMER3_PRESCALER_REG_2: + return 2; +#endif + +#if defined TIMER3_PRESCALER_REG_3 && TIMER3_PRESCALER_REG_3 >= 0 + case TIMER3_PRESCALER_REG_3: + return 3; +#endif + +#if defined TIMER3_PRESCALER_REG_4 && TIMER3_PRESCALER_REG_4 >= 0 + case TIMER3_PRESCALER_REG_4: + return 4; +#endif + +#if defined TIMER3_PRESCALER_REG_5 && TIMER3_PRESCALER_REG_5 >= 0 + case TIMER3_PRESCALER_REG_5: + return 5; +#endif + +#if defined TIMER3_PRESCALER_REG_6 && TIMER3_PRESCALER_REG_6 >= 0 + case TIMER3_PRESCALER_REG_6: + return 6; +#endif + +#if defined TIMER3_PRESCALER_REG_7 && TIMER3_PRESCALER_REG_7 >= 0 + case TIMER3_PRESCALER_REG_7: + return 7; +#endif + +#if defined TIMER3_PRESCALER_REG_8 && TIMER3_PRESCALER_REG_8 >= 0 + case TIMER3_PRESCALER_REG_8: + return 8; +#endif + +#if defined TIMER3_PRESCALER_REG_9 && TIMER3_PRESCALER_REG_9 >= 0 + case TIMER3_PRESCALER_REG_9: + return 9; +#endif + +#if defined TIMER3_PRESCALER_REG_10 && TIMER3_PRESCALER_REG_10 >= 0 + case TIMER3_PRESCALER_REG_10: + return 10; +#endif + +#if defined TIMER3_PRESCALER_REG_11 && TIMER3_PRESCALER_REG_11 >= 0 + case TIMER3_PRESCALER_REG_11: + return 11; +#endif + +#if defined TIMER3_PRESCALER_REG_12 && TIMER3_PRESCALER_REG_12 >= 0 + case TIMER3_PRESCALER_REG_12: + return 12; +#endif + +#if defined TIMER3_PRESCALER_REG_13 && TIMER3_PRESCALER_REG_13 >= 0 + case TIMER3_PRESCALER_REG_13: + return 13; +#endif +#if defined TIMER3_PRESCALER_REG_14 && TIMER3_PRESCALER_REG_14 >= 0 + case TIMER3_PRESCALER_REG_14: + return 14; +#endif + +#if defined TIMER3_PRESCALER_REG_15 && TIMER3_PRESCALER_REG_15 >= 0 + case TIMER3_PRESCALER_REG_15: + return 15; +#endif + default: + return -1; + } +} + +/* return <0 on error, else return div value */ +/* This static inline function is very optimized if reg is + * a constant */ +static inline int16_t __timer3_reg_to_div(uint8_t reg) +{ + switch(reg) { +#if defined TIMER3_PRESCALER_DIV_0 + case TIMER3_PRESCALER_DIV_0: + return 0; +#endif + +#if defined TIMER3_PRESCALER_DIV_1 + case TIMER3_PRESCALER_DIV_1: + return 1; +#endif + +#if defined TIMER3_PRESCALER_DIV_2 + case TIMER3_PRESCALER_DIV_2: + return 2; +#endif + +#if defined TIMER3_PRESCALER_DIV_4 + case TIMER3_PRESCALER_DIV_4: + return 4; +#endif + +#if defined TIMER3_PRESCALER_DIV_8 + case TIMER3_PRESCALER_DIV_8: + return 8; +#endif + +#if defined TIMER3_PRESCALER_DIV_16 + case TIMER3_PRESCALER_DIV_16: + return 16; +#endif + +#if defined TIMER3_PRESCALER_DIV_32 + case TIMER3_PRESCALER_DIV_32: + return 32; +#endif + +#if defined TIMER3_PRESCALER_DIV_64 + case TIMER3_PRESCALER_DIV_64: + return 64; +#endif + +#if defined TIMER3_PRESCALER_DIV_128 + case TIMER3_PRESCALER_DIV_128: + return 128; +#endif + +#if defined TIMER3_PRESCALER_DIV_256 + case TIMER3_PRESCALER_DIV_256: + return 256; +#endif + +#if defined TIMER3_PRESCALER_DIV_512 + case TIMER3_PRESCALER_DIV_512: + return 512; +#endif + +#if defined TIMER3_PRESCALER_DIV_1024 + case TIMER3_PRESCALER_DIV_1024: + return 1024; +#endif + +#if defined TIMER3_PRESCALER_DIV_2048 + case TIMER3_PRESCALER_DIV_2048: + return 2048; +#endif + +#if defined TIMER3_PRESCALER_DIV_4096 + case TIMER3_PRESCALER_DIV_4096: + return 4096; +#endif + +#if defined TIMER3_PRESCALER_DIV_8192 + case TIMER3_PRESCALER_DIV_8192: + return 8192; +#endif + +#if defined TIMER3_PRESCALER_DIV_16384 + case TIMER3_PRESCALER_DIV_16384: + return 16384; +#endif + + default: + return -1; + } +} + +/* return <0 on error, else return reg value */ +/* This static inline function is very optimized if div is + * a constant */ +static inline int16_t __timer4_div_to_reg(uint16_t div) +{ + switch(div) { +#if defined TIMER4_PRESCALER_REG_0 && TIMER4_PRESCALER_REG_0 >= 0 + case TIMER4_PRESCALER_REG_0: + return 0; +#endif + +#if defined TIMER4_PRESCALER_REG_1 && TIMER4_PRESCALER_REG_1 >= 0 + case TIMER4_PRESCALER_REG_1: + return 1; +#endif + +#if defined TIMER4_PRESCALER_REG_2 && TIMER4_PRESCALER_REG_2 >= 0 + case TIMER4_PRESCALER_REG_2: + return 2; +#endif + +#if defined TIMER4_PRESCALER_REG_3 && TIMER4_PRESCALER_REG_3 >= 0 + case TIMER4_PRESCALER_REG_3: + return 3; +#endif + +#if defined TIMER4_PRESCALER_REG_4 && TIMER4_PRESCALER_REG_4 >= 0 + case TIMER4_PRESCALER_REG_4: + return 4; +#endif + +#if defined TIMER4_PRESCALER_REG_5 && TIMER4_PRESCALER_REG_5 >= 0 + case TIMER4_PRESCALER_REG_5: + return 5; +#endif + +#if defined TIMER4_PRESCALER_REG_6 && TIMER4_PRESCALER_REG_6 >= 0 + case TIMER4_PRESCALER_REG_6: + return 6; +#endif + +#if defined TIMER4_PRESCALER_REG_7 && TIMER4_PRESCALER_REG_7 >= 0 + case TIMER4_PRESCALER_REG_7: + return 7; +#endif + +#if defined TIMER4_PRESCALER_REG_8 && TIMER4_PRESCALER_REG_8 >= 0 + case TIMER4_PRESCALER_REG_8: + return 8; +#endif + +#if defined TIMER4_PRESCALER_REG_9 && TIMER4_PRESCALER_REG_9 >= 0 + case TIMER4_PRESCALER_REG_9: + return 9; +#endif + +#if defined TIMER4_PRESCALER_REG_10 && TIMER4_PRESCALER_REG_10 >= 0 + case TIMER4_PRESCALER_REG_10: + return 10; +#endif + +#if defined TIMER4_PRESCALER_REG_11 && TIMER4_PRESCALER_REG_11 >= 0 + case TIMER4_PRESCALER_REG_11: + return 11; +#endif + +#if defined TIMER4_PRESCALER_REG_12 && TIMER4_PRESCALER_REG_12 >= 0 + case TIMER4_PRESCALER_REG_12: + return 12; +#endif + +#if defined TIMER4_PRESCALER_REG_13 && TIMER4_PRESCALER_REG_13 >= 0 + case TIMER4_PRESCALER_REG_13: + return 13; +#endif +#if defined TIMER4_PRESCALER_REG_14 && TIMER4_PRESCALER_REG_14 >= 0 + case TIMER4_PRESCALER_REG_14: + return 14; +#endif + +#if defined TIMER4_PRESCALER_REG_15 && TIMER4_PRESCALER_REG_15 >= 0 + case TIMER4_PRESCALER_REG_15: + return 15; +#endif + default: + return -1; + } +} + +/* return <0 on error, else return div value */ +/* This static inline function is very optimized if reg is + * a constant */ +static inline int16_t __timer4_reg_to_div(uint8_t reg) +{ + switch(reg) { +#if defined TIMER4_PRESCALER_DIV_0 + case TIMER4_PRESCALER_DIV_0: + return 0; +#endif + +#if defined TIMER4_PRESCALER_DIV_1 + case TIMER4_PRESCALER_DIV_1: + return 1; +#endif + +#if defined TIMER4_PRESCALER_DIV_2 + case TIMER4_PRESCALER_DIV_2: + return 2; +#endif + +#if defined TIMER4_PRESCALER_DIV_4 + case TIMER4_PRESCALER_DIV_4: + return 4; +#endif + +#if defined TIMER4_PRESCALER_DIV_8 + case TIMER4_PRESCALER_DIV_8: + return 8; +#endif + +#if defined TIMER4_PRESCALER_DIV_16 + case TIMER4_PRESCALER_DIV_16: + return 16; +#endif + +#if defined TIMER4_PRESCALER_DIV_32 + case TIMER4_PRESCALER_DIV_32: + return 32; +#endif + +#if defined TIMER4_PRESCALER_DIV_64 + case TIMER4_PRESCALER_DIV_64: + return 64; +#endif + +#if defined TIMER4_PRESCALER_DIV_128 + case TIMER4_PRESCALER_DIV_128: + return 128; +#endif + +#if defined TIMER4_PRESCALER_DIV_256 + case TIMER4_PRESCALER_DIV_256: + return 256; +#endif + +#if defined TIMER4_PRESCALER_DIV_512 + case TIMER4_PRESCALER_DIV_512: + return 512; +#endif + +#if defined TIMER4_PRESCALER_DIV_1024 + case TIMER4_PRESCALER_DIV_1024: + return 1024; +#endif + +#if defined TIMER4_PRESCALER_DIV_2048 + case TIMER4_PRESCALER_DIV_2048: + return 2048; +#endif + +#if defined TIMER4_PRESCALER_DIV_4096 + case TIMER4_PRESCALER_DIV_4096: + return 4096; +#endif + +#if defined TIMER4_PRESCALER_DIV_8192 + case TIMER4_PRESCALER_DIV_8192: + return 8192; +#endif + +#if defined TIMER4_PRESCALER_DIV_16384 + case TIMER4_PRESCALER_DIV_16384: + return 16384; +#endif + + default: + return -1; + } +} + +/* return <0 on error, else return reg value */ +/* This static inline function is very optimized if div is + * a constant */ +static inline int16_t __timer5_div_to_reg(uint16_t div) +{ + switch(div) { +#if defined TIMER5_PRESCALER_REG_0 && TIMER5_PRESCALER_REG_0 >= 0 + case TIMER5_PRESCALER_REG_0: + return 0; +#endif + +#if defined TIMER5_PRESCALER_REG_1 && TIMER5_PRESCALER_REG_1 >= 0 + case TIMER5_PRESCALER_REG_1: + return 1; +#endif + +#if defined TIMER5_PRESCALER_REG_2 && TIMER5_PRESCALER_REG_2 >= 0 + case TIMER5_PRESCALER_REG_2: + return 2; +#endif + +#if defined TIMER5_PRESCALER_REG_3 && TIMER5_PRESCALER_REG_3 >= 0 + case TIMER5_PRESCALER_REG_3: + return 3; +#endif + +#if defined TIMER5_PRESCALER_REG_4 && TIMER5_PRESCALER_REG_4 >= 0 + case TIMER5_PRESCALER_REG_4: + return 4; +#endif + +#if defined TIMER5_PRESCALER_REG_5 && TIMER5_PRESCALER_REG_5 >= 0 + case TIMER5_PRESCALER_REG_5: + return 5; +#endif + +#if defined TIMER5_PRESCALER_REG_6 && TIMER5_PRESCALER_REG_6 >= 0 + case TIMER5_PRESCALER_REG_6: + return 6; +#endif + +#if defined TIMER5_PRESCALER_REG_7 && TIMER5_PRESCALER_REG_7 >= 0 + case TIMER5_PRESCALER_REG_7: + return 7; +#endif + +#if defined TIMER5_PRESCALER_REG_8 && TIMER5_PRESCALER_REG_8 >= 0 + case TIMER5_PRESCALER_REG_8: + return 8; +#endif + +#if defined TIMER5_PRESCALER_REG_9 && TIMER5_PRESCALER_REG_9 >= 0 + case TIMER5_PRESCALER_REG_9: + return 9; +#endif + +#if defined TIMER5_PRESCALER_REG_10 && TIMER5_PRESCALER_REG_10 >= 0 + case TIMER5_PRESCALER_REG_10: + return 10; +#endif + +#if defined TIMER5_PRESCALER_REG_11 && TIMER5_PRESCALER_REG_11 >= 0 + case TIMER5_PRESCALER_REG_11: + return 11; +#endif + +#if defined TIMER5_PRESCALER_REG_12 && TIMER5_PRESCALER_REG_12 >= 0 + case TIMER5_PRESCALER_REG_12: + return 12; +#endif + +#if defined TIMER5_PRESCALER_REG_13 && TIMER5_PRESCALER_REG_13 >= 0 + case TIMER5_PRESCALER_REG_13: + return 13; +#endif +#if defined TIMER5_PRESCALER_REG_14 && TIMER5_PRESCALER_REG_14 >= 0 + case TIMER5_PRESCALER_REG_14: + return 14; +#endif + +#if defined TIMER5_PRESCALER_REG_15 && TIMER5_PRESCALER_REG_15 >= 0 + case TIMER5_PRESCALER_REG_15: + return 15; +#endif + default: + return -1; + } +} + +/* return <0 on error, else return div value */ +/* This static inline function is very optimized if reg is + * a constant */ +static inline int16_t __timer5_reg_to_div(uint8_t reg) +{ + switch(reg) { +#if defined TIMER5_PRESCALER_DIV_0 + case TIMER5_PRESCALER_DIV_0: + return 0; +#endif + +#if defined TIMER5_PRESCALER_DIV_1 + case TIMER5_PRESCALER_DIV_1: + return 1; +#endif + +#if defined TIMER5_PRESCALER_DIV_2 + case TIMER5_PRESCALER_DIV_2: + return 2; +#endif + +#if defined TIMER5_PRESCALER_DIV_4 + case TIMER5_PRESCALER_DIV_4: + return 4; +#endif + +#if defined TIMER5_PRESCALER_DIV_8 + case TIMER5_PRESCALER_DIV_8: + return 8; +#endif + +#if defined TIMER5_PRESCALER_DIV_16 + case TIMER5_PRESCALER_DIV_16: + return 16; +#endif + +#if defined TIMER5_PRESCALER_DIV_32 + case TIMER5_PRESCALER_DIV_32: + return 32; +#endif + +#if defined TIMER5_PRESCALER_DIV_64 + case TIMER5_PRESCALER_DIV_64: + return 64; +#endif + +#if defined TIMER5_PRESCALER_DIV_128 + case TIMER5_PRESCALER_DIV_128: + return 128; +#endif + +#if defined TIMER5_PRESCALER_DIV_256 + case TIMER5_PRESCALER_DIV_256: + return 256; +#endif + +#if defined TIMER5_PRESCALER_DIV_512 + case TIMER5_PRESCALER_DIV_512: + return 512; +#endif + +#if defined TIMER5_PRESCALER_DIV_1024 + case TIMER5_PRESCALER_DIV_1024: + return 1024; +#endif + +#if defined TIMER5_PRESCALER_DIV_2048 + case TIMER5_PRESCALER_DIV_2048: + return 2048; +#endif + +#if defined TIMER5_PRESCALER_DIV_4096 + case TIMER5_PRESCALER_DIV_4096: + return 4096; +#endif + +#if defined TIMER5_PRESCALER_DIV_8192 + case TIMER5_PRESCALER_DIV_8192: + return 8192; +#endif + +#if defined TIMER5_PRESCALER_DIV_16384 + case TIMER5_PRESCALER_DIV_16384: + return 16384; +#endif + + default: + return -1; + } +} + +#endif diff --git a/modules/ihm/CVS/Entries b/modules/ihm/CVS/Entries new file mode 100644 index 0000000..f2673c1 --- /dev/null +++ b/modules/ihm/CVS/Entries @@ -0,0 +1,4 @@ +D/menu//// +D/parse//// +D/rdline//// +D/vt100//// diff --git a/modules/ihm/CVS/Repository b/modules/ihm/CVS/Repository new file mode 100644 index 0000000..6d632e7 --- /dev/null +++ b/modules/ihm/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm diff --git a/modules/ihm/CVS/Root b/modules/ihm/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/CVS/Tag b/modules/ihm/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/CVS/Template b/modules/ihm/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/menu/CVS/Entries b/modules/ihm/menu/CVS/Entries new file mode 100644 index 0000000..854672b --- /dev/null +++ b/modules/ihm/menu/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.2.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/menu.c/1.3.4.2/Wed May 23 17:18:15 2007//Tb_zer0 +/menu.h/1.3.4.2/Wed May 23 17:18:15 2007//Tb_zer0 +D/test//// diff --git a/modules/ihm/menu/CVS/Repository b/modules/ihm/menu/CVS/Repository new file mode 100644 index 0000000..a409a0c --- /dev/null +++ b/modules/ihm/menu/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/menu diff --git a/modules/ihm/menu/CVS/Root b/modules/ihm/menu/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/menu/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/menu/CVS/Tag b/modules/ihm/menu/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/menu/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/menu/CVS/Template b/modules/ihm/menu/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/menu/Makefile b/modules/ihm/menu/Makefile new file mode 100644 index 0000000..53afb8b --- /dev/null +++ b/modules/ihm/menu/Makefile @@ -0,0 +1,6 @@ +TARGET = menu + +# List C source files here. (C dependencies are automatically generated.) +SRC = menu.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/ihm/menu/menu.c b/modules/ihm/menu/menu.c new file mode 100644 index 0000000..4b1041e --- /dev/null +++ b/modules/ihm/menu/menu.c @@ -0,0 +1,355 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: menu.c,v 1.3.4.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2006 + * Implementation of a static menu + */ + +#include <stdio.h> +#include <stdlib.h> + +#include <aversive.h> + +#include "menu.h" + +/** return name of a menu, if the type is correct */ +char * menu_get_name(struct menu * m) { + if (!m) + return NULL; + + if ( m->type == MENU_TYPE_MENU || + m->type == MENU_TYPE_ROOT || + m->type == MENU_TYPE_FCT_HDR ) + return (char *)m->data; + + return NULL; +} + +/** return type of a menu */ +uint8_t menu_get_type(struct menu * m) { + if (!m) + return MENU_TYPE_UNKNOWN; + + return m->type; +} + +static uint8_t menu_is_a_submenu(struct menu * m) +{ + if (!m) + return 0; + + return ( m->type == MENU_TYPE_MENU || m->type == MENU_TYPE_ROOT ); +} + + +/** call the function described by the menu, and return 0 on success */ +uint8_t menu_call_fct(struct menu * m) { + void (*f)(void *); + + if (!m) + return 1; + + if ( m->type != MENU_TYPE_FCT_HDR ) + return 1; + + f = (void (*)(void *) )(m+1)->data; + + if ( (m+1)->type != MENU_TYPE_FCT_PTR || f == NULL ) + return 1; + + if ( (m+2)->type != MENU_TYPE_FCT_DATA ) + return 1; + + f( (m+2)->data ); + return 0; +} + + +/** get previous menu on same level, return NULL if no one */ +struct menu * menu_get_previous(struct menu * m) { + int8_t level = 0; + + if (!m) + return NULL; + + if(m->type == MENU_TYPE_ROOT) + return NULL; + + m --; + while ( level >= 0 ) { + + if ( m->type == MENU_TYPE_ROOT ) { + return NULL; + } + if ( m->type == MENU_TYPE_END ) { + level ++; + } + if ( m->type == MENU_TYPE_MENU ) { + level --; + } + if ( level == 0 ) { + if ( m->type == MENU_TYPE_FCT_HDR || + m->type == MENU_TYPE_MENU ) { + return m; + } + } + m--; + } + return NULL; +} + +/** get next menu on same level, return NULL if no one */ +struct menu * menu_get_next(struct menu * m) { + int8_t level = 0; + + if (!m) + return NULL; + + if(m->type == MENU_TYPE_ROOT) + return NULL; + + if ( m->type == MENU_TYPE_MENU ) { + level ++; + } + + m ++; + while ( level >= 0 ) { + + if ( level == 0 ) { + if ( m->type == MENU_TYPE_FCT_HDR || + m->type == MENU_TYPE_MENU ) { + return m; + } + } + if ( m->type == MENU_TYPE_END ) { + level --; + } + if ( m->type == MENU_TYPE_MENU ) { + level ++; + } + m++; + } + return NULL; +} + +/** get the parent of the menu - return NULL if no parent */ +struct menu * menu_get_parent(struct menu * m) +{ + struct menu * ret; + + if (!m) + return NULL; + + /* return null if root */ + if(m->type == MENU_TYPE_ROOT) + return NULL; + + do { + ret = m; + } while ( (m=menu_get_previous(ret)) ) ; + + /* get the previous one and return it if it is a submenu, else return NULL */ + ret--; + if ( menu_is_a_submenu(ret) ) + return ret; + else + return NULL; +} + +/** return first son or NULL if there is no son */ +struct menu * menu_get_first_son(struct menu * m) +{ + if (!m) + return NULL; + + if (menu_is_a_submenu(m)) { + return m+1; + } + else return NULL; +} + +/** get the submenu 'num' -> can return NULL if does not exist */ +struct menu * menu_get_sub(struct menu * m, uint8_t num) { + if (!m) + return NULL; + + m = menu_get_first_son(m); + while(m && num) { + num --; + m = menu_get_next(m); + } + return m; +} + +/** return number of submenus in a menu */ +uint8_t menu_get_sub_howmany(struct menu * m) { + uint8_t num=0; + + if (!m) + return 0; + + m = menu_get_first_son(m); + while(m) { + num ++; + m = menu_get_next(m); + } + return num; +} + + +/** get the parent of the menu - never return NULL except if m is null */ +struct menu * menu_left(struct menu * m) +{ + struct menu * ret; + + if (!m) + return NULL; + + if ( (ret = menu_get_parent(m)) ) + return ret; + else + return m; +} + +/** get the son number 'num' or self if it does not exist, + try to call the function if it exists, does not return null + except if m is null */ +struct menu * menu_right(struct menu * m) +{ + struct menu * ret ; + if (!m) + return NULL; + + if ( (ret=menu_get_first_son(m)) ) + return ret; + + menu_call_fct(m); + + return m; +} + +/** return the next menu on same level (if it is the last, go back to beginning */ +struct menu * menu_up(struct menu * m) +{ + struct menu * ret; + + if (!m) + return NULL; + + /* if there is a menu before, return it */ + if ( (ret=menu_get_previous(m)) ) + return ret; + + /* if there is no before and no next, return self */ + if ( ! (ret = menu_get_next(m) ) ) + return m; + + /* return the next, next, next, ... until the end of menu */ + do { + ret = m; + } while ( (m=menu_get_next(ret)) ) ; + + return ret; +} + +/** return the next menu on same level (if it is the first, go back to the end */ +struct menu * menu_down(struct menu * m) +{ + struct menu * ret; + + if (!m) + return NULL; + + /* if there is a menu after, return it */ + if ( (ret=menu_get_next(m)) ) + return ret; + + /* if there is no before and no next, return self */ + if ( ! (ret = menu_get_previous(m) ) ) + return m; + + /* return the previous, previous, previous, ... until the end of menu */ + do { + ret = m; + } while ( (m=menu_get_previous(ret)) ) ; + + return ret; +} + + +/** move in the menu, depending on the action */ +struct menu * menu_default_update(struct menu * m, char c) +{ + struct menu * ret; + + switch(c) { + case 'b': + return menu_up(m); + case 'f': + return menu_down(m); + case 'n': + return menu_right(m); + case 'p': + return menu_left(m); + default: + if(c >= '0' && c <= '9') { + if ( m->type == MENU_TYPE_ROOT && c == '0' ) { + ret = menu_right(m); + if (ret) return ret; + } + else if ( (ret = menu_right(menu_get_sub(menu_get_parent(m), c-'0'))) ) { + return ret; + } + } + return m; + } +} + + +/** default function to display a menu, you can reimplement it */ +void menu_default_display(struct menu * m) +{ + struct menu * parent = menu_get_parent(m); + struct menu * son ; + uint8_t i ; + + /* clear term */ + printf(""); + + if(parent) { + printf("%s\r\n", menu_get_name(parent)); + + for (i=0 ; i<menu_get_sub_howmany(parent) ; i++) { + son = menu_get_sub(parent, i); + if( son == m ) + printf("> %d: %s", i, menu_get_name(son)); + else + printf(" %d: %s", i, menu_get_name(son)); + if(menu_is_a_submenu(son)) + printf(" -->"); + printf("\r\n"); + } + } + else { + printf("| 0: %s -->", menu_get_name(m)); + } +} + diff --git a/modules/ihm/menu/menu.h b/modules/ihm/menu/menu.h new file mode 100644 index 0000000..37f235b --- /dev/null +++ b/modules/ihm/menu/menu.h @@ -0,0 +1,257 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: menu.h,v 1.3.4.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +/** + * + * This is the documentation of the menu module. + * + * RESUME + * ====== + * + * The aim of this module is to provide some simple functions to use a + * tree-based menu in a program. The displaying of the menu can be done + * in several ways: uart, lcd, ... This module tries to be independant of + * the way it is displayed. + * + * MAIN FUNCTIONS + * ============== + * + * The main functions that can be used are : menu_left(), menu_right(), + * menu_up() and menu_down(). they are used to browse the menu. Each of + * these functions take a pointer to a menu as an argument and return + * another one. The directions correspond to (one of) the natural + * representation of a tree. + * + * + * root ----- submenu1 ----- leaf1 + * | | + * | |--- leaf2 + * | | + * | |--- submenu2 ----- leaf3 + * | | + * | |--- leaf4 + * | + * ---- leaf5 + * + * Left goes to the parent. + * Right goes to the first son + * Up goes to the menu before, on the same level. + * Down goes to the menu after, on the same level. + * + * These functions try to be tolerant : for example, doing a menu_left() + * on the root menu return the root menu. Doing a menu_down() on the last + * menu of a level returns the first menu on the same level. + * + * The module provide one function for displaying a menu and another to + * do an action depending on a character. These functions can be + * reimplemented by the user to be more adapted to his application. + * + * The default display function clear the screen, print the parent of the + * menu, then all other menus on the same level, highlighting the menu + * given in parameter. + * + * The default menu_update() function takes a character as parameter. + * - 'n' (next) is equivalent to menu_right. + * - 'p' (previous) is equivalent to menu_left. + * - 'f' (forward) is equivalent to menu_down. + * - 'b' (backward) is equivalent to menu_up. + * - '0', '1', ..., '9' selects the menu n on the same level. + * + * + * IMPLEMENTATION + * ============== + * + * A menu is a static table of a menu element. Each menu element is a + * struct menu : + * + * struct menu { + * uint8_t type; + * void * data; + * } + * + * An element type can be : MENU_TYPE_ROOT if the element is the root of + * the menu, MENU_TYPE_MENU if it is a submenu under the root, + * MENU_TYPE_FCT_HDR, MENU_TYPE_FCT_PTR, MENU_TYPE_FCT_DATA, to declare a + * leaf that executes a function, or MENU_TYPE_END to mark the end of a + * submenu or the end of the root menu. + * + * For each of these types, the data field points to different things : + * MENU_TYPE_ROOT data -> (char *) title of the menu + * MENU_TYPE_MENU data -> (char *) title of the menu + * MENU_TYPE_FCT_HDR data -> (char *) title of the menu + * MENU_TYPE_FCT_PTR data -> void (*f)(void *) function that will be called + * MENU_TYPE_FCT_DATA data -> (void *) parameter of this function + * MENU_TYPE_END data -> NULL + * + * + * Here is an exemple : + * + * root ----- submenu1 ----- leaf1 + * | | + * | |--- leaf2 + * | | + * | |--- submenu2 ----- leaf3 + * | | + * | |--- leaf4 + * | + * ---- leaf5 + * + * will be represented as : + * + * MENU_TYPE_ROOT, "root" + * MENU_TYPE_MENU, "submenu1" + * MENU_TYPE_FCT_HDR, "leaf1" + * MENU_TYPE_FCT_PTR, fct_leaf1 + * MENU_TYPE_FCT_DATA, leaf1_data + * MENU_TYPE_FCT_HDR, "leaf2" + * MENU_TYPE_FCT_PTR, fct_leaf2 + * MENU_TYPE_FCT_DATA, leaf2_data + * MENU_TYPE_MENU, "submenu2" + * MENU_TYPE_FCT_HDR, "leaf3" + * MENU_TYPE_FCT_PTR, fct_leaf3 + * MENU_TYPE_FCT_DATA, leaf3_data + * MENU_TYPE_FCT_HDR, "leaf4" + * MENU_TYPE_FCT_PTR, fct_leaf4 + * MENU_TYPE_FCT_DATA, leaf4_data + * MENU_TYPE_END, NULL + * MENU_TYPE_END, NULL + * MENU_TYPE_FCT_HDR, "leaf5" + * MENU_TYPE_FCT_PTR, fct_leaf5 + * MENU_TYPE_FCT_DATA, leaf5_data + * MENU_TYPE_END, NULL + * + * For AVR version, all is stored in program memory. (TODO : store the + * menu table in program memory, currently only text is stored there) + */ + +/* Olivier MATZ, Droids-corp 2004 - 2006 + * Implementation of a static menu + */ + +#include <aversive.h> + +/** + * The structure that defines a menu element. + * A menu is composed of several struct a this type, see the + * documentation for more informations + */ +struct menu { + uint8_t type; + void * data; +}; + +/* ************************************************************* */ + +/* Functions that you should use to move in a menu, they try + to never return NULL, except if param is NULL */ + +/** get the parent of the menu - never return NULL except if param is null */ +struct menu * menu_left(struct menu * m); + +/** get the first son number self if it does not exist, try to call + the fonction if it exists, never return NULL except if param is + null */ +struct menu * menu_right(struct menu * m); + +/** return the next menu on same level (if it is the last, go back to + beginning, never return NULL except if param is null */ +struct menu * menu_down(struct menu * m); + +/** return the next menu on same level (if it is the first, go back to + the end, never return NULL except if param is null */ +struct menu * menu_up(struct menu * m); + + +/* ************************************************************* */ + +/* Functions used to interact with the user (in and out : keyboard + * and display) + * These functions can be reimplemented by the user to change the + * manner that the menu is displayed or the manner that the user + * moves in the menu. + */ + + +/** move in the menu, depending on the action (the character c) */ +struct menu * menu_default_update(struct menu * m, char c); + +/** default function to display a menu, you can reimplement it */ +void menu_default_display(struct menu * m); + + +/* ************************************************************* */ + +/* Functions that can be usefull, but warning : some of these return + * a NULL pointer, that need to be handled */ + +/** return name of a menu, if the type is correct */ +char * menu_get_name(struct menu * m); + +/** return type of a menu */ +uint8_t menu_get_type(struct menu * m); + +/** call the function described by the menu, and return 0 on + success */ +uint8_t menu_call_fct(struct menu * m); + +/** get previous menu on same level, return NULL if no one */ +struct menu * menu_get_previous(struct menu * m); + +/** get next menu on same level, return NULL if no one */ +struct menu * menu_get_next(struct menu * m); + +/** get the parent of the menu - return NULL if no parent */ +struct menu * menu_get_parent(struct menu * m); + +/** return first son or NULL if there is no son */ +struct menu * menu_get_first_son(struct menu * m); + +/** get the submenu 'num' -> can return NULL if does not exist */ +struct menu * menu_get_sub(struct menu * m, uint8_t num); + +/** return number of submenus in a menu */ +uint8_t menu_get_sub_howmany(struct menu * m); + + +/* ************************************************************* */ + +/* macros used to declare a menu */ + +#define MENU_TYPE_ROOT 0 +#define MENU_TYPE_MENU 1 +#define MENU_TYPE_FCT_HDR 2 +#define MENU_TYPE_FCT_PTR 3 +#define MENU_TYPE_FCT_DATA 4 +#define MENU_TYPE_END 5 +#define MENU_TYPE_UNKNOWN 255 + +#define MENU_ROOT(text) { MENU_TYPE_ROOT, (void *)text } + +#define MENU_START(text) { MENU_TYPE_MENU, (void *)text } + +#define MENU_END() { MENU_TYPE_END, NULL } + +#define MENU_FCT(text, f, data) \ + { MENU_TYPE_FCT_HDR, (void *)text }, \ + { MENU_TYPE_FCT_PTR, (void *)f }, \ + { MENU_TYPE_FCT_DATA, (void *)data } + + diff --git a/modules/ihm/menu/test/.config b/modules/ihm/menu/test/.config new file mode 100644 index 0000000..6a5e825 --- /dev/null +++ b/modules/ihm/menu/test/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +CONFIG_MODULE_MENU=y +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/ihm/menu/test/CVS/Entries b/modules/ihm/menu/test/CVS/Entries new file mode 100644 index 0000000..6fc2f70 --- /dev/null +++ b/modules/ihm/menu/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.6.4.9/Sun Apr 13 16:52:41 2008//Tb_zer0 +/Makefile/1.2.6.2/Wed Sep 12 17:52:20 2007//Tb_zer0 +/error_config.h/1.3.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/main.c/1.3.4.2/Wed May 23 17:18:15 2007//Tb_zer0 +/uart_config.h/1.2.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/wait_config.h/1.2.6.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +D diff --git a/modules/ihm/menu/test/CVS/Repository b/modules/ihm/menu/test/CVS/Repository new file mode 100644 index 0000000..fcdfea2 --- /dev/null +++ b/modules/ihm/menu/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/menu/test diff --git a/modules/ihm/menu/test/CVS/Root b/modules/ihm/menu/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/menu/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/menu/test/CVS/Tag b/modules/ihm/menu/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/menu/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/menu/test/CVS/Template b/modules/ihm/menu/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/menu/test/Makefile b/modules/ihm/menu/test/Makefile new file mode 100644 index 0000000..73ab23b --- /dev/null +++ b/modules/ihm/menu/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/ihm/menu/test/error_config.h b/modules/ihm/menu/test/error_config.h new file mode 100644 index 0000000..80902a5 --- /dev/null +++ b/modules/ihm/menu/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.3.6.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/ihm/menu/test/main.c b/modules/ihm/menu/test/main.c new file mode 100644 index 0000000..548e7d1 --- /dev/null +++ b/modules/ihm/menu/test/main.c @@ -0,0 +1,111 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.3.4.2 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +/* Olivier MATZ, Droids-corp 2004 - 2006 + * Test program for a menu + */ + +#include <stdio.h> +#include <stdlib.h> + +#include <aversive/wait.h> +#include <uart.h> +#include <menu.h> + +int myparam=0; + +void f(void * data) +{ + printf("POUET\n"); +} + +struct menu my_menu[] = { + MENU_ROOT("racine"), + MENU_FCT("a", f, &myparam), + MENU_START("sub1"), + MENU_FCT("b", f, &myparam), + MENU_FCT("c", f, &myparam), + MENU_FCT("d", f, &myparam), + MENU_END(), + MENU_START("sub2"), + MENU_FCT("e", f, &myparam), + MENU_END(), + MENU_FCT("f", f, &myparam), + MENU_END(), +}; + + + +int main(void) +{ + struct menu *m = my_menu; + char c; + +#ifndef HOST_VERSION + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + sei(); +#endif + + /* tests */ + printf("Root is %s\n", menu_get_name(m)); + m = menu_down(m); + printf("1st son of root is %s\n", menu_get_name(m)); + m = menu_right(m); + printf("The submenu is %s\n", menu_get_name(m)); + + + m = menu_get_first_son(m); + printf("1st son is %s\n", menu_get_name(m)); + m = menu_right(m); + printf("2nd son is %s\n", menu_get_name(m)); + m = menu_right(m); + printf("3rd son is %s\n", menu_get_name(m)); + m = menu_right(m); + printf("return to 1st son : %s\n", menu_get_name(m)); + + m = menu_left(m); + printf("3rd son is %s\n", menu_get_name(m)); + m = menu_left(m); + printf("2nd son is %s\n", menu_get_name(m)); + m = menu_left(m); + printf("1st son is %s\n", menu_get_name(m)); + m = menu_left(m); + + + wait_ms(1000); + + // exit(0); + + + m = my_menu; + while (1) { + menu_default_display(m); +#ifdef HOST_VERSION + scanf("%c",&c); +#else + c=uart0_recv(); +#endif + m=menu_default_update(m, c); + } + + return 0; +} diff --git a/modules/ihm/menu/test/uart_config.h b/modules/ihm/menu/test/uart_config.h new file mode 100644 index 0000000..5907ca3 --- /dev/null +++ b/modules/ihm/menu/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.6.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/ihm/menu/test/wait_config.h b/modules/ihm/menu/test/wait_config.h new file mode 100644 index 0000000..4fbdfcd --- /dev/null +++ b/modules/ihm/menu/test/wait_config.h @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: wait_config.h,v 1.2.6.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +#ifndef _WAIT_CONFIG_ +#define _WAIT_CONFIG_ 1.0 // version + +// wait_config.h +// This file is the local config file to be used with the wait module. +// This is an example file +//can we perhaps delete this file? + + + +#endif diff --git a/modules/ihm/parse/CVS/Entries b/modules/ihm/parse/CVS/Entries new file mode 100644 index 0000000..55953f5 --- /dev/null +++ b/modules/ihm/parse/CVS/Entries @@ -0,0 +1,8 @@ +/Makefile/1.1.2.1/Mon Sep 17 20:53:28 2007//Tb_zer0 +/parse.c/1.1.2.11/Tue Apr 7 20:00:46 2009//Tb_zer0 +/parse.h/1.1.2.9/Sat Jan 3 16:25:13 2009//Tb_zer0 +/parse_num.c/1.1.2.8/Fri Feb 27 21:41:31 2009//Tb_zer0 +/parse_num.h/1.1.2.7/Fri Feb 27 21:41:31 2009//Tb_zer0 +/parse_string.c/1.1.2.7/Fri Feb 27 21:41:31 2009//Tb_zer0 +/parse_string.h/1.1.2.8/Sat Jan 3 16:25:13 2009//Tb_zer0 +D/test//// diff --git a/modules/ihm/parse/CVS/Repository b/modules/ihm/parse/CVS/Repository new file mode 100644 index 0000000..a8634f9 --- /dev/null +++ b/modules/ihm/parse/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/parse diff --git a/modules/ihm/parse/CVS/Root b/modules/ihm/parse/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/parse/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/parse/CVS/Tag b/modules/ihm/parse/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/parse/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/parse/CVS/Template b/modules/ihm/parse/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/parse/Makefile b/modules/ihm/parse/Makefile new file mode 100644 index 0000000..7672c25 --- /dev/null +++ b/modules/ihm/parse/Makefile @@ -0,0 +1,6 @@ +TARGET = parse + +# List C source files here. (C dependencies are automatically generated.) +SRC = parse.c parse_num.c parse_string.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/ihm/parse/parse.c b/modules/ihm/parse/parse.c new file mode 100644 index 0000000..37f365d --- /dev/null +++ b/modules/ihm/parse/parse.c @@ -0,0 +1,437 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: parse.c,v 1.1.2.11 2009-04-07 20:00:46 zer0 Exp $ + * + * + */ + +#include <stdio.h> +#include <string.h> +#include <inttypes.h> +#include <ctype.h> + +#include <aversive/pgmspace.h> + +#include "parse.h" + +//#define CMDLINE_DEBUG +//#define debug_printf printf +#define debug_printf(args...) do {} while(0) + + +static int +isendofline(char c) +{ + if (c == '\n' || + c == '\r' ) + return 1; + return 0; +} + +static int +iscomment(char c) +{ + if (c == '#') + return 1; + return 0; +} + +int +isendoftoken(char c) +{ + if (!c || iscomment(c) || isblank(c) || isendofline(c)) + return 1; + return 0; +} + +static uint8_t +nb_common_chars(const char * s1, const char * s2) +{ + uint8_t i=0; + + while (*s1==*s2 && *s1 && *s2) { + s1++; + s2++; + i++; + } + return i; +} + +/** + * try to match the buffer with an instruction (only the first + * nb_match_token tokens if != 0). Return 0 if we match all the + * tokens, else the number of matched tokens, else -1. + */ +static int8_t +match_inst(parse_pgm_inst_t *inst, const char * buf, uint8_t nb_match_token, + void * result_buf) +{ + uint8_t token_num=0; + parse_pgm_token_hdr_t * token_p; + uint8_t i=0; + int8_t n = 0; + struct token_hdr token_hdr; + + token_p = (parse_pgm_token_hdr_t *)pgm_read_word(&inst->tokens[token_num]); + if (token_p) + memcpy_P(&token_hdr, token_p, sizeof(token_hdr)); + + /* check if we match all tokens of inst */ + while (token_p && (!nb_match_token || i<nb_match_token)) { + debug_printf("TK\n"); + /* skip spaces */ + while (isblank(*buf)) { + buf++; + } + + /* end of buf */ + if ( isendofline(*buf) || iscomment(*buf) ) + break; + + n = token_hdr.ops->parse(token_p, buf, (result_buf ? result_buf+token_hdr.offset : NULL)); + if ( n < 0 ) + break; + debug_printf("TK parsed (len=%d)\n", n); + i++; + buf += n; + + token_num ++; + token_p = (parse_pgm_token_hdr_t *)pgm_read_word(&inst->tokens[token_num]); + if (token_p) + memcpy_P(&token_hdr, token_p, sizeof(token_hdr)); + } + + /* does not match */ + if (i==0) + return -1; + + /* in case we want to match a specific num of token */ + if (nb_match_token) { + if (i == nb_match_token) { + return 0; + } + return i; + } + + /* we don't match all the tokens */ + if (token_p) { + return i; + } + + /* are there are some tokens more */ + while (isblank(*buf)) { + buf++; + } + + /* end of buf */ + if ( isendofline(*buf) || iscomment(*buf) ) + return 0; + + /* garbage after inst */ + return i; +} + + +int8_t +parse(parse_pgm_ctx_t ctx[], const char * buf) +{ + uint8_t inst_num=0; + parse_pgm_inst_t * inst; + const char * curbuf; + char result_buf[256]; /* XXX align, size zé in broblém */ + void (*f)(void *, void *) = NULL; + void * data = NULL; + int comment = 0; + int linelen = 0; + int parse_it = 0; + int8_t err = PARSE_NOMATCH; + int8_t tok; +#ifdef CMDLINE_DEBUG + char debug_buf[64]; +#endif + + /* + * - look if the buffer contains at least one line + * - look if line contains only spaces or comments + * - count line length + */ + curbuf = buf; + while (! isendofline(*curbuf)) { + if ( *curbuf == '\0' ) { + debug_printf("Incomplete buf (len=%d)\n", linelen); + return 0; + } + if ( iscomment(*curbuf) ) { + comment = 1; + } + if ( ! isblank(*curbuf) && ! comment) { + parse_it = 1; + } + curbuf++; + linelen++; + } + + /* skip all endofline chars */ + while (isendofline(buf[linelen])) { + linelen++; + } + + /* empty line */ + if ( parse_it == 0 ) { + debug_printf("Empty line (len=%d)\n", linelen); + return linelen; + } + +#ifdef CMDLINE_DEBUG + snprintf(debug_buf, (linelen>64 ? 64 : linelen), "%s", buf); + debug_printf("Parse line : len=%d, <%s>\n", linelen, debug_buf); +#endif + + /* parse it !! */ + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + while (inst) { + debug_printf("INST\n"); + + /* fully parsed */ + tok = match_inst(inst, buf, 0, result_buf); + + if (tok > 0) /* we matched at least one token */ + err = PARSE_BAD_ARGS; + + else if (!tok) { + debug_printf("INST fully parsed\n"); + /* skip spaces */ + while (isblank(*curbuf)) { + curbuf++; + } + + /* if end of buf -> there is no garbage after inst */ + if (isendofline(*curbuf) || iscomment(*curbuf)) { + if (!f) { + memcpy_P(&f, &inst->f, sizeof(f)); + memcpy_P(&data, &inst->data, sizeof(data)); + } + else { + /* more than 1 inst matches */ + err = PARSE_AMBIGUOUS; + f=NULL; + debug_printf("Ambiguous cmd\n"); + break; + } + } + } + + inst_num ++; + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + } + + /* call func */ + if (f) { + f(result_buf, data); + } + + /* no match */ + else { + debug_printf("No match err=%d\n", err); + return err; + } + + return linelen; +} + +int8_t +complete(parse_pgm_ctx_t ctx[], const char *buf, int16_t *state, + char *dst, uint8_t size) +{ + const char * incomplete_token = buf; + uint8_t inst_num = 0; + parse_pgm_inst_t *inst; + parse_pgm_token_hdr_t *token_p; + struct token_hdr token_hdr; + char tmpbuf[64], completion_buf[64]; + uint8_t incomplete_token_len; + int8_t completion_len = -1; + int8_t nb_token = 0; + uint8_t i, n; + int8_t l; + uint8_t nb_completable; + uint8_t nb_non_completable; + int16_t local_state=0; + prog_char *help_str; + + debug_printf("%s called\n", __FUNCTION__); + /* count the number of complete token to parse */ + for (i=0 ; buf[i] ; i++) { + if (!isblank(buf[i]) && isblank(buf[i+1])) + nb_token++; + if (isblank(buf[i]) && !isblank(buf[i+1])) + incomplete_token = buf+i+1; + } + incomplete_token_len = strlen(incomplete_token); + + /* first call -> do a first pass */ + if (*state <= 0) { + debug_printf("try complete <%s>\n", buf); + debug_printf("there is %d complete tokens, <%s> is incomplete\n", nb_token, incomplete_token); + + nb_completable = 0; + nb_non_completable = 0; + + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + while (inst) { + /* parse the first tokens of the inst */ + if (nb_token && match_inst(inst, buf, nb_token, NULL)) + goto next; + + debug_printf("instruction match \n"); + token_p = (parse_pgm_token_hdr_t *) pgm_read_word(&inst->tokens[nb_token]); + if (token_p) + memcpy_P(&token_hdr, token_p, sizeof(token_hdr)); + + /* non completable */ + if (!token_p || + !token_hdr.ops->complete_get_nb || + !token_hdr.ops->complete_get_elt || + (n = token_hdr.ops->complete_get_nb(token_p)) == 0) { + nb_non_completable++; + goto next; + } + + debug_printf("%d choices for this token\n", n); + for (i=0 ; i<n ; i++) { + if (token_hdr.ops->complete_get_elt(token_p, i, tmpbuf, sizeof(tmpbuf)) < 0) + continue; + strcat_P(tmpbuf, PSTR(" ")); /* we have at least room for one char */ + debug_printf(" choice <%s>\n", tmpbuf); + /* does the completion match the beginning of the word ? */ + if (!strncmp(incomplete_token, tmpbuf, incomplete_token_len)) { + if (completion_len == -1) { + strcpy(completion_buf, tmpbuf+incomplete_token_len); + completion_len = strlen(tmpbuf+incomplete_token_len); + + } + else { + completion_len = nb_common_chars(completion_buf, + tmpbuf+incomplete_token_len); + completion_buf[completion_len] = 0; + } + nb_completable++; + } + } + next: + inst_num ++; + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + } + + debug_printf("total choices %d for this completion\n", nb_completable); + + /* no possible completion */ + if (nb_completable == 0 && nb_non_completable == 0) + return 0; + + /* if multichoice is not required */ + if (*state == 0 && incomplete_token_len > 0) { + /* one or several choices starting with the + same chars */ + if (completion_len > 0) { + if (completion_len + 1 > size) + return 0; + + strcpy(dst, completion_buf); + return 2; + } + } + } + + /* init state correctly */ + if (*state == -1) + *state = 0; + + debug_printf("Multiple choice STATE=%d\n", *state); + + inst_num = 0; + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + while (inst) { + /* we need to redo it */ + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + + if (nb_token && match_inst(inst, buf, nb_token, NULL)) + goto next2; + + token_p = (parse_pgm_token_hdr_t *)pgm_read_word(&inst->tokens[nb_token]); + if (token_p) + memcpy_P(&token_hdr, token_p, sizeof(token_hdr)); + + /* one choice for this token */ + if (!token_p || + !token_hdr.ops->complete_get_nb || + !token_hdr.ops->complete_get_elt || + (n = token_hdr.ops->complete_get_nb(token_p)) == 0) { + if (local_state < *state) { + local_state++; + goto next2; + } + (*state)++; + if (token_p && token_hdr.ops->get_help) { + token_hdr.ops->get_help(token_p, tmpbuf, sizeof(tmpbuf)); + help_str = (prog_char *) pgm_read_word(&inst->help_str); + if (help_str) + snprintf_P(dst, size, PSTR("[%s]: %S"), tmpbuf, help_str); + else + snprintf_P(dst, size, PSTR("[%s]: No help"), tmpbuf); + } + else { + snprintf_P(dst, size, PSTR("[RETURN]")); + } + return 1; + } + + /* several choices */ + for (i=0 ; i<n ; i++) { + if (token_hdr.ops->complete_get_elt(token_p, i, tmpbuf, sizeof(tmpbuf)) < 0) + continue; + strcat_P(tmpbuf, PSTR(" ")); /* we have at least room for one char */ + debug_printf(" choice <%s>\n", tmpbuf); + /* does the completion match the beginning of the word ? */ + if (!strncmp(incomplete_token, tmpbuf, incomplete_token_len)) { + if (local_state < *state) { + local_state++; + continue; + } + (*state)++; + l=snprintf(dst, size, "%s", tmpbuf); + if (l>=0 && token_hdr.ops->get_help) { + token_hdr.ops->get_help(token_p, tmpbuf, sizeof(tmpbuf)); + help_str = (prog_char *) pgm_read_word(&inst->help_str); + if (help_str) + snprintf_P(dst+l, size-l, PSTR("[%s]: %S"), tmpbuf, help_str); + else + snprintf_P(dst+l, size-l, PSTR("[%s]: No help"), tmpbuf); + } + + return 1; + } + } + next2: + inst_num ++; + inst = (parse_pgm_inst_t *)pgm_read_word(ctx+inst_num); + } + return 0; +} + diff --git a/modules/ihm/parse/parse.h b/modules/ihm/parse/parse.h new file mode 100644 index 0000000..2760ca6 --- /dev/null +++ b/modules/ihm/parse/parse.h @@ -0,0 +1,146 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: parse.h,v 1.1.2.9 2009-01-03 16:25:13 zer0 Exp $ + * + * + */ + +#ifndef _PARSE_H_ +#define _PARSE_H_ + +#include <aversive/pgmspace.h> +#include <aversive/types.h> + +#ifndef offsetof +#define offsetof(type, field) ((size_t) &( ((type *)0)->field) ) +#endif + +#define PARSE_SUCCESS 0 +#define PARSE_AMBIGUOUS -1 +#define PARSE_NOMATCH -2 +#define PARSE_BAD_ARGS -3 + +/** + * Stores a pointer to the ops struct, and the offset: the place to + * write the parsed result in the destination structure. + */ +struct token_hdr { + struct token_ops *ops; + uint8_t offset; +}; +typedef struct token_hdr parse_token_hdr_t; + +struct token_hdr_pgm { + struct token_ops *ops; + uint8_t offset; +} PROGMEM; +typedef struct token_hdr_pgm parse_pgm_token_hdr_t; + +/** + * A token is defined by this structure. + * + * parse() takes the token as first argument, then the source buffer + * starting at the token we want to parse. The 3rd arg is a pointer + * where we store the parsed data (as binary). It returns the number of + * parsed chars on success and a negative value on error. + * + * complete_get_nb() returns the number of possible values for this + * token if completion is possible. If it is NULL or if it returns 0, + * no completion is possible. + * + * complete_get_elt() copy in dstbuf (the size is specified in the + * parameter) the i-th possible completion for this token. returns 0 + * on success or and a negative value on error. + * + * get_help() fills the dstbuf with the help for the token. It returns + * -1 on error and 0 on success. + */ +struct token_ops { + /** parse(token ptr, buf, res pts) */ + int8_t (*parse)(parse_pgm_token_hdr_t *, const char *, void *); + /** return the num of possible choices for this token */ + int8_t (*complete_get_nb)(parse_pgm_token_hdr_t *); + /** return the elt x for this token (token, idx, dstbuf, size) */ + int8_t (*complete_get_elt)(parse_pgm_token_hdr_t *, int8_t, char *, uint8_t); + /** get help for this token (token, dstbuf, size) */ + int8_t (*get_help)(parse_pgm_token_hdr_t *, char *, uint8_t); +}; + +/** + * Store a instruction, which is a pointer to a callback function and + * its parameter that is called when the instruction is parsed, a help + * string, and a list of token composing this instruction. + */ +struct inst { + /* f(parsed_struct, data) */ + void (*f)(void *, void *); + void * data; + char * help_str; + prog_void * tokens[]; +}; +typedef struct inst parse_inst_t; +struct inst_pgm { + /* f(parsed_struct, data) */ + void (*f)(void *, void *); + void * data; + char * help_str; + prog_void * tokens[]; +} PROGMEM; +typedef struct inst_pgm parse_pgm_inst_t; + +/** + * A context is identified by its name, and contains a list of + * instruction + * + */ +typedef parse_pgm_inst_t * parse_ctx_t; +typedef PROGMEM parse_ctx_t parse_pgm_ctx_t; + +/** + * Try to parse a buffer according to the specified context. The + * argument buf must ends with "\n\0". The function returns + * PARSE_AMBIGUOUS, PARSE_NOMATCH or PARSE_BAD_ARGS on error. Else it + * calls the associated function (defined in the context) and returns + * 0 (PARSE_SUCCESS). + */ +int8_t parse(parse_pgm_ctx_t ctx[], const char * buf); + +/** + * complete() must be called with *state==0. + * It returns < 0 on error. + * + * Else it returns: + * 2 on completion (one possible choice). In this case, the chars + * are appended in dst buffer. + * 1 if there is several possible choices. In this case, you must + * call the function again, keeping the value of state intact. + * 0 when the iteration is finished. The dst is not valid for this + * last call. + * + * The returned dst buf ends with \0. + * + */ +int8_t complete(parse_pgm_ctx_t ctx[], const char *buf, int16_t *state, + char *dst, uint8_t size); + + +/* true if(!c || iscomment(c) || isblank(c) || isendofline(c)) */ +int isendoftoken(char c); + +#endif /* _PARSE_H_ */ diff --git a/modules/ihm/parse/parse_num.c b/modules/ihm/parse/parse_num.c new file mode 100644 index 0000000..7bbc7ce --- /dev/null +++ b/modules/ihm/parse/parse_num.c @@ -0,0 +1,436 @@ +#include <stdio.h> +#include <inttypes.h> +#include <ctype.h> +#include <string.h> + +#include "parse.h" +#include "parse_num.h" + +//#define debug_printf(args...) printf(args) +#define debug_printf(args...) do {} while(0) + +/* XXX to remove ?? */ +#define U08_MIN 0x00 +#define U08_MAX 0xFF +#define U16_MIN 0x0000 +#define U16_MAX 0xFFFF +#define U32_MIN 0x00000000 +#define U32_MAX 0xFFFFFFFF +#define S08_MIN 0x80 +#define S08_MAX 0x7F +#define S16_MIN 0x8000 +#define S16_MAX 0x7FFF +#define S32_MIN 0x80000000 +#define S32_MAX 0x7FFFFFFF + + +struct token_ops token_num_ops = { + .parse = parse_num, + .complete_get_nb = NULL, + .complete_get_elt = NULL, + .get_help = get_help_num, +}; + + +enum num_parse_state_t { + START, + DEC_NEG, + BIN, + HEX, + FLOAT_POS, + FLOAT_NEG, + ERROR, + + FIRST_OK, /* not used */ + ZERO_OK, + HEX_OK, + OCTAL_OK, + BIN_OK, + DEC_NEG_OK, + DEC_POS_OK, + FLOAT_POS_OK, + FLOAT_NEG_OK, +}; + +/* Keep it sync with enum in .h */ +static const prog_char help1[] = "UINT8"; +static const prog_char help2[] = "UINT16"; +static const prog_char help3[] = "UINT32"; +static const prog_char help4[] = "INT8"; +static const prog_char help5[] = "INT16"; +static const prog_char help6[] = "INT32"; +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT +static const prog_char help7[] = "FLOAT"; +#endif +static const prog_char * num_help[] = { + help1, help2, help3, help4, + help5, help6, +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + help7, +#endif +}; + +static inline int8_t +add_to_res(uint8_t c, uint32_t * res, uint8_t base) +{ + /* overflow */ + if ( (U32_MAX - c) / base < *res ) { + return -1; + } + + *res = *res * base + c ; + return 0; +} + + +/* parse an int or a float */ +int8_t +parse_num(parse_pgm_token_hdr_t * tk, const char * srcbuf, void * res) +{ + struct token_num_data nd; + enum num_parse_state_t st = START; + const char * buf = srcbuf; + char c = *buf; + uint32_t res1=0, res2=0, res3=1; + + memcpy_P(&nd, &((struct token_num *)tk)->num_data, sizeof(nd)); + + while ( st != ERROR && c && ! isendoftoken(c) ) { + debug_printf("%c %x -> ", c, c); + switch (st) { + case START: + if (c == '-') { + st = DEC_NEG; + } + else if (c == '0') { + st = ZERO_OK; + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if (c == '.') { + st = FLOAT_POS; + res1 = 0; + } +#endif + else if (c >= '1' && c <= '9') { + if (add_to_res(c - '0', &res1, 10) < 0) + st = ERROR; + else + st = DEC_POS_OK; + } + else { + st = ERROR; + } + break; + + case ZERO_OK: + if (c == 'x') { + st = HEX; + } + else if (c == 'b') { + st = BIN; + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if (c == '.') { + st = FLOAT_POS; + res1 = 0; + } +#endif + else if (c >= '0' && c <= '7') { + if (add_to_res(c - '0', &res1, 10) < 0) + st = ERROR; + else + st = OCTAL_OK; + } + else { + st = ERROR; + } + break; + + case DEC_NEG: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res1, 10) < 0) + st = ERROR; + else + st = DEC_NEG_OK; + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if (c == '.') { + res1 = 0; + st = FLOAT_NEG; + } +#endif + else { + st = ERROR; + } + break; + + case DEC_NEG_OK: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res1, 10) < 0) + st = ERROR; + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if (c == '.') { + st = FLOAT_NEG; + } +#endif + else { + st = ERROR; + } + break; + + case DEC_POS_OK: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res1, 10) < 0) + st = ERROR; + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if (c == '.') { + st = FLOAT_POS; + } +#endif + else { + st = ERROR; + } + break; + + case HEX: + st = HEX_OK; + /* no break */ + case HEX_OK: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res1, 16) < 0) + st = ERROR; + } + else if (c >= 'a' && c <= 'f') { + if (add_to_res(c - 'a' + 10, &res1, 16) < 0) + st = ERROR; + } + else if (c >= 'A' && c <= 'F') { + if (add_to_res(c - 'A' + 10, &res1, 16) < 0) + st = ERROR; + } + else { + st = ERROR; + } + break; + + + case OCTAL_OK: + if (c >= '0' && c <= '7') { + if (add_to_res(c - '0', &res1, 8) < 0) + st = ERROR; + } + else { + st = ERROR; + } + break; + + case BIN: + st = BIN_OK; + /* no break */ + case BIN_OK: + if (c >= '0' && c <= '1') { + if (add_to_res(c - '0', &res1, 2) < 0) + st = ERROR; + } + else { + st = ERROR; + } + break; + +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + case FLOAT_POS: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res2, 10) < 0) + st = ERROR; + else + st = FLOAT_POS_OK; + res3 = 10; + } + else { + st = ERROR; + } + break; + + case FLOAT_NEG: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res2, 10) < 0) + st = ERROR; + else + st = FLOAT_NEG_OK; + res3 = 10; + } + else { + st = ERROR; + } + break; + + case FLOAT_POS_OK: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res2, 10) < 0) + st = ERROR; + if (add_to_res(0, &res3, 10) < 0) + st = ERROR; + } + else { + st = ERROR; + } + break; + + case FLOAT_NEG_OK: + if (c >= '0' && c <= '9') { + if (add_to_res(c - '0', &res2, 10) < 0) + st = ERROR; + if (add_to_res(0, &res3, 10) < 0) + st = ERROR; + } + else { + st = ERROR; + } + break; +#endif + + default: + debug_printf("not impl "); + + } + + /* XXX uint32_t et %d */ + debug_printf("(%d) (%d) (%d)\n", res1, res2, res3); + + buf ++; + c = *buf; + + /* token too long */ + if (buf-srcbuf > 127) + return -1; + } + + switch (st) { + case ZERO_OK: + case DEC_POS_OK: + case HEX_OK: + case OCTAL_OK: + case BIN_OK: + if ( nd.type == INT8 && res1 <= S08_MAX ) { + if (res) + *(int8_t *)res = (int8_t) res1; + return (buf-srcbuf); + } + else if ( nd.type == INT16 && res1 <= S16_MAX ) { + if (res) + *(int16_t *)res = (int16_t) res1; + return (buf-srcbuf); + } + else if ( nd.type == INT32 && res1 <= S32_MAX ) { + if (res) + *(int32_t *)res = (int32_t) res1; + return (buf-srcbuf); + } + else if ( nd.type == UINT8 && res1 <= U08_MAX ) { + if (res) + *(uint8_t *)res = (uint8_t) res1; + return (buf-srcbuf); + } + else if (nd.type == UINT16 && res1 <= U16_MAX ) { + if (res) + *(uint16_t *)res = (uint16_t) res1; + return (buf-srcbuf); + } + else if ( nd.type == UINT32 ) { + if (res) + *(uint32_t *)res = (uint32_t) res1; + return (buf-srcbuf); + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if ( nd.type == FLOAT ) { + if (res) + *(float *)res = (float)res1; + return (buf-srcbuf); + } +#endif + else { + return -1; + } + break; + + case DEC_NEG_OK: + if ( nd.type == INT8 && res1 <= S08_MAX + 1 ) { + if (res) + *(int8_t *)res = - (int8_t) res1; + return (buf-srcbuf); + } + else if ( nd.type == INT16 && res1 <= (uint16_t)S16_MAX + 1 ) { + if (res) + *(int16_t *)res = - (int16_t) res1; + return (buf-srcbuf); + } + else if ( nd.type == INT32 && res1 <= (uint32_t)S32_MAX + 1 ) { + if (res) + *(int32_t *)res = - (int32_t) res1; + return (buf-srcbuf); + } +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + else if ( nd.type == FLOAT ) { + if (res) + *(float *)res = - (float)res1; + return (buf-srcbuf); + } +#endif + else { + return -1; + } + break; + +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + case FLOAT_POS: + case FLOAT_POS_OK: + if ( nd.type == FLOAT ) { + if (res) + *(float *)res = (float)res1 + ((float)res2 / (float)res3); + return (buf-srcbuf); + + } + else { + return -1; + } + break; + + case FLOAT_NEG: + case FLOAT_NEG_OK: + if ( nd.type == FLOAT ) { + if (res) + *(float *)res = - ((float)res1 + ((float)res2 / (float)res3)); + return (buf-srcbuf); + + } + else { + return -1; + } + break; +#endif + default: + debug_printf("error\n"); + return -1; + } + return -1; +} + + +/* parse an int or a float */ +int8_t +get_help_num(parse_pgm_token_hdr_t * tk, char * dstbuf, uint8_t size) +{ + struct token_num_data nd; + + memcpy_P(&nd, &((struct token_num *)tk)->num_data, sizeof(nd)); + + /* should not happen.... don't so this test */ +/* if (nd.type >= (sizeof(num_help)/sizeof(const char *))) */ +/* return -1; */ + + strncpy_P(dstbuf, num_help[nd.type], size); + dstbuf[size-1] = '\0'; + return 0; +} diff --git a/modules/ihm/parse/parse_num.h b/modules/ihm/parse/parse_num.h new file mode 100644 index 0000000..de10e7d --- /dev/null +++ b/modules/ihm/parse/parse_num.h @@ -0,0 +1,51 @@ +#ifndef _PARSE_NUM_H_ +#define _PARSE_NUM_H_ + +#include "parse.h" + +enum numtype { + UINT8 = 0, + UINT16, + UINT32, + INT8, + INT16, + INT32, +#ifndef CONFIG_MODULE_PARSE_NO_FLOAT + FLOAT, +#endif +}; + +struct token_num_data { + enum numtype type; +}; + +struct token_num { + struct token_hdr hdr; + struct token_num_data num_data; +}; +typedef struct token_num parse_token_num_t; +struct token_num_pgm { + struct token_hdr hdr; + struct token_num_data num_data; +} PROGMEM; +typedef struct token_num_pgm parse_pgm_token_num_t; + +extern struct token_ops token_num_ops; + +int8_t parse_num(parse_pgm_token_hdr_t * tk, + const char * srcbuf, void * res); +int8_t get_help_num(parse_pgm_token_hdr_t * tk, + char * dstbuf, uint8_t size); + +#define TOKEN_NUM_INITIALIZER(structure, field, numtype) \ +{ \ + .hdr = { \ + .ops = &token_num_ops, \ + .offset = offsetof(structure, field), \ + }, \ + .num_data = { \ + .type = numtype, \ + }, \ +} + +#endif /* _PARSE_NUM_H_ */ diff --git a/modules/ihm/parse/parse_string.c b/modules/ihm/parse/parse_string.c new file mode 100644 index 0000000..abfe8bb --- /dev/null +++ b/modules/ihm/parse/parse_string.c @@ -0,0 +1,169 @@ +#include <stdio.h> +#include <inttypes.h> +#include <ctype.h> +#include <string.h> + +#include "parse.h" +#include "parse_string.h" + +struct token_ops token_string_ops = { + .parse = parse_string, + .complete_get_nb = complete_get_nb_string, + .complete_get_elt = complete_get_elt_string, + .get_help = get_help_string, +}; + +#define MULTISTRING_HELP PSTR("Mul-choice STRING") +#define ANYSTRING_HELP PSTR("Any STRING") +#define FIXEDSTRING_HELP PSTR("Fixed STRING") + +static uint8_t +get_token_len(const prog_char * s) +{ + prog_char c; + uint8_t i=0; + + c = pgm_read_byte(s+i); + while (c!='#' && c!='\0') { + i++; + c = pgm_read_byte(s+i); + } + return i; +} + +static const prog_char * +get_next_token(const prog_char * s) +{ + uint8_t i; + i = get_token_len(s); + if (pgm_read_byte(s+i) == '#') + return s+i+1; + return NULL; +} + +int8_t +parse_string(parse_pgm_token_hdr_t * tk, const char * buf, void * res) +{ + struct token_string_data sd; + uint8_t token_len; + const prog_char * str; + + if (! *buf) + return -1; + + memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd)); + + /* fixed string */ + if (sd.str) { + str = sd.str; + do { + token_len = get_token_len(str); + + /* if token is too big... */ + if (token_len >= STR_TOKEN_SIZE - 1) { + continue; + } + + if ( strncmp_P(buf, str, token_len) ) { + continue; + } + + if ( !isendoftoken(*(buf+token_len)) ) { + continue; + } + + break; + } while ( (str = get_next_token(str)) != NULL ); + + if (!str) + return -1; + } + /* unspecified string */ + else { + token_len=0; + while(!isendoftoken(buf[token_len]) && + token_len < (STR_TOKEN_SIZE-1)) + token_len++; + + /* return if token too long */ + if (token_len >= STR_TOKEN_SIZE - 1) { + return -1; + } + } + + if (res) { + /* we are sure that token_len is < STR_TOKEN_SIZE-1 */ + strncpy(res, buf, token_len); + *((char *)res + token_len) = 0; + } + + return token_len; +} + +int8_t complete_get_nb_string(parse_pgm_token_hdr_t * tk) +{ + struct token_string_data sd; + int8_t ret=1; + + memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd)); + + if (!sd.str) + return 0; + + while( (sd.str = get_next_token(sd.str)) != NULL ) { + ret++; + } + return ret; +} + +int8_t complete_get_elt_string(parse_pgm_token_hdr_t * tk, int8_t idx, + char * dstbuf, uint8_t size) +{ + struct token_string_data sd; + const prog_char * s; + uint8_t len; + + memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd)); + s = sd.str; + + while (idx-- && s) + s = get_next_token(s); + + if (!s) + return -1; + + len = get_token_len(s); + if (len > size - 1) + return -1; + + memcpy_P(dstbuf, s, len); + dstbuf[len] = '\0'; + + return 0; +} + + +int8_t get_help_string(parse_pgm_token_hdr_t * tk, char * dstbuf, uint8_t size) +{ + struct token_string_data sd; + const prog_char * s; + + memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd)); + s = sd.str; + + if (s) { + if (get_next_token(s)) { + strncpy_P(dstbuf, MULTISTRING_HELP, size); + } + else { + strncpy_P(dstbuf, FIXEDSTRING_HELP, size); + } + } + else { + strncpy_P(dstbuf, ANYSTRING_HELP, size); + } + + dstbuf[size-1] = '\0'; + + return 0; +} diff --git a/modules/ihm/parse/parse_string.h b/modules/ihm/parse/parse_string.h new file mode 100644 index 0000000..0d09892 --- /dev/null +++ b/modules/ihm/parse/parse_string.h @@ -0,0 +1,45 @@ +#ifndef _PARSE_STRING_H_ +#define _PARSE_STRING_H_ + +#include "parse.h" + +/* size of a parsed string */ +#define STR_TOKEN_SIZE 32 + +typedef char fixed_string_t[STR_TOKEN_SIZE]; + +struct token_string_data { + const prog_char * str; +}; + +struct token_string { + struct token_hdr hdr; + struct token_string_data string_data; +}; +typedef struct token_string parse_token_string_t; +struct token_string_pgm { + struct token_hdr hdr; + struct token_string_data string_data; +} PROGMEM; +typedef struct token_string_pgm parse_pgm_token_string_t; + +extern struct token_ops token_string_ops; + +int8_t parse_string(parse_pgm_token_hdr_t * tk, const char * srcbuf, void * res); +int8_t complete_get_nb_string(parse_pgm_token_hdr_t * tk); +int8_t complete_get_elt_string(parse_pgm_token_hdr_t * tk, int8_t idx, + char * dstbuf, uint8_t size); +int8_t get_help_string(parse_pgm_token_hdr_t * tk, char * dstbuf, uint8_t size); + +#define TOKEN_STRING_INITIALIZER(structure, field, string) \ +{ \ + .hdr = { \ + .ops = &token_string_ops, \ + .offset = offsetof(structure, field), \ + }, \ + .string_data = { \ + .str = string, \ + }, \ +} + +#endif /* _PARSE_STRING_H_ */ diff --git a/modules/ihm/parse/test/.config b/modules/ihm/parse/test/.config new file mode 100644 index 0000000..0190ac5 --- /dev/null +++ b/modules/ihm/parse/test/.config @@ -0,0 +1,244 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_ADVANCED_PRINTF=y +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_9BITS is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +# CONFIG_AVRDUDE is not set +CONFIG_AVARICE=y + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/ihm/parse/test/CVS/Entries b/modules/ihm/parse/test/CVS/Entries new file mode 100644 index 0000000..b4f39e0 --- /dev/null +++ b/modules/ihm/parse/test/CVS/Entries @@ -0,0 +1,8 @@ +/.config/1.1.2.6/Fri Feb 27 21:41:31 2009//Tb_zer0 +/Makefile/1.1.2.2/Sat Sep 22 18:15:55 2007//Tb_zer0 +/commands.c/1.1.2.3/Sat Nov 24 22:57:54 2007//Tb_zer0 +/error_config.h/1.1.2.1/Mon Sep 17 20:53:28 2007//Tb_zer0 +/main.c/1.1.2.6/Sat Nov 24 22:57:54 2007//Tb_zer0 +/rdline_config.h/1.1.2.1/Sat Sep 22 14:27:41 2007//Tb_zer0 +/uart_config.h/1.1.2.2/Sat Nov 24 22:57:54 2007//Tb_zer0 +D diff --git a/modules/ihm/parse/test/CVS/Repository b/modules/ihm/parse/test/CVS/Repository new file mode 100644 index 0000000..896c80a --- /dev/null +++ b/modules/ihm/parse/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/parse/test diff --git a/modules/ihm/parse/test/CVS/Root b/modules/ihm/parse/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/parse/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/parse/test/CVS/Tag b/modules/ihm/parse/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/parse/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/parse/test/CVS/Template b/modules/ihm/parse/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/parse/test/Makefile b/modules/ihm/parse/test/Makefile new file mode 100644 index 0000000..ee00c1f --- /dev/null +++ b/modules/ihm/parse/test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c commands.c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/ihm/parse/test/commands.c b/modules/ihm/parse/test/commands.c new file mode 100644 index 0000000..ccc8698 --- /dev/null +++ b/modules/ihm/parse/test/commands.c @@ -0,0 +1,152 @@ +#include <math.h> +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <parse.h> +#include <parse_num.h> +#include <parse_string.h> + + + +/**********************************************************/ +/* operations on float */ + +/* this structure is filled when cmd_float is parsed successfully */ +struct cmd_float_result { + float a; + fixed_string_t op; + float b; +}; + +/* function called when cmd_float is parsed successfully */ +static void cmd_float_parsed(void * parsed_result, void * data) +{ + struct cmd_float_result * cmd = (struct cmd_float_result *) parsed_result; + float res=0.; + + switch(cmd->op[0]) { + case '+': res = cmd->a + cmd->b; break; + case '-': res = cmd->a - cmd->b; break; + case '*': res = cmd->a * cmd->b; break; + case '/': res = cmd->a / cmd->b; break; + default: break; + } + printf_P(PSTR("%f\n"), res); +} + +parse_pgm_token_num_t cmd_float_a = TOKEN_NUM_INITIALIZER(struct cmd_float_result, a, FLOAT); +prog_char str_float_op[] = "+#-#*#/"; +parse_pgm_token_string_t cmd_float_op = TOKEN_STRING_INITIALIZER(struct cmd_float_result, op, str_float_op); +parse_pgm_token_num_t cmd_float_b = TOKEN_NUM_INITIALIZER(struct cmd_float_result, b, FLOAT); + +prog_char help_float[] = "Operation on float (ex: '2 + 5.4')"; +parse_pgm_inst_t cmd_float = { + .f = cmd_float_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_float, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_float_a, + (prog_void *)&cmd_float_op, + (prog_void *)&cmd_float_b, + NULL, + }, +}; + + +/**********************************************************/ +/* operations on trigo */ + +/* this structure is filled when cmd_trigo is parsed successfully */ +struct cmd_trigo_result { + fixed_string_t op; + float a; +}; + +/* function called when cmd_trigo is parsed successfully */ +static void cmd_trigo_parsed(void * parsed_result, void * data) +{ + struct cmd_trigo_result * cmd = (struct cmd_trigo_result *) parsed_result; + float res=0.; + + if (!strcmp_P(cmd->op, PSTR("sin"))) { + res = sin(cmd->a); + } + + else if (!strcmp_P(cmd->op, PSTR("cos"))) { + res = cos(cmd->a); + } + + else if (!strcmp_P(cmd->op, PSTR("tan"))) { + res = tan(cmd->a); + } + + printf_P(PSTR("%f\n"), res); +} + +prog_char str_trigo_op[] = "sin#tan#cos"; +parse_pgm_token_string_t cmd_trigo_op = TOKEN_STRING_INITIALIZER(struct cmd_trigo_result, op, str_trigo_op); +parse_pgm_token_num_t cmd_trigo_a = TOKEN_NUM_INITIALIZER(struct cmd_trigo_result, a, FLOAT); + +prog_char help_trigo[] = "Trigonometric operations (ex: 'sin 2.03')"; +parse_pgm_inst_t cmd_trigo = { + .f = cmd_trigo_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_trigo, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_trigo_op, + (prog_void *)&cmd_trigo_a, + NULL, + }, +}; + + +/**********************************************************/ +/* Help */ + +/* this structure is filled when cmd_help is parsed successfully */ +struct cmd_help_result { + fixed_string_t arg0; +}; + +/* function called when cmd_help is parsed successfully */ +static void cmd_help_parsed(void * parsed_result, void * data) +{ + printf_P(PSTR("== Simple calculator program ==\n" + "You can do simple operations on floats, like '1 + 3'\n" + "or '4.4 * 2.' (space is important).\n" + "Some trigonometric operations are available, like\n" + "'sin 4.5'.\n")); +} + +prog_char str_help_arg0[] = "help"; +parse_pgm_token_string_t cmd_help_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_help_result, arg0, str_help_arg0); + +prog_char help_help[] = "Display help"; +parse_pgm_inst_t cmd_help = { + .f = cmd_help_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_help, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_help_arg0, + NULL, + }, +}; + + + + +/**********************************************************/ +/**********************************************************/ +/****** CONTEXT (list of instruction) */ + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + (parse_pgm_inst_t *)&cmd_float, + (parse_pgm_inst_t *)&cmd_trigo, + (parse_pgm_inst_t *)&cmd_help, + NULL, +}; + diff --git a/modules/ihm/parse/test/error_config.h b/modules/ihm/parse/test/error_config.h new file mode 100644 index 0000000..f771246 --- /dev/null +++ b/modules/ihm/parse/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-09-17 20:53:28 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/ihm/parse/test/main.c b/modules/ihm/parse/test/main.c new file mode 100644 index 0000000..64173f2 --- /dev/null +++ b/modules/ihm/parse/test/main.c @@ -0,0 +1,143 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.6 2007-11-24 22:57:54 zer0 Exp $ + * + */ + + +#include <stdio.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/error.h> +#include <aversive/wait.h> + +#include <rdline.h> +#include <parse.h> + +struct rdline rdl; +char prompt[RDLINE_PROMPT_SIZE]; +extern parse_pgm_ctx_t main_ctx[]; +extern void cmd_event_parsed(void * parsed_result, void * data); + +#include <stdlib.h> +#include <stdarg.h> +#include <inttypes.h> +#include <ctype.h> + +#ifdef HOST_VERSION +#include <unistd.h> +#include <termios.h> + +/* for rdline */ +void +write_char(char c) { + write(1, &c, 1); +} + +#else +#include <uart.h> + +void +write_char(char c) { + uart0_send(c); +} +#endif + +void +valid_buffer(const char * buf, uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\n")); +} + +int8_t +complete_buffer(const char * buf, char * dstbuf, uint8_t dstsize, + int16_t * state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + + +/*** main */ + +int main(void) +{ +#ifdef HOST_VERSION + struct termios oldterm, term; + int n; +#endif + int8_t ret; + char c; + +#ifdef HOST_VERSION + tcgetattr(0, &oldterm); + memcpy(&term, &oldterm, sizeof(term)); + term.c_lflag &= ~(ICANON | ECHO | ISIG); + tcsetattr(0, TCSANOW, &term); + setbuf(stdin, NULL); +#else + fdevopen(uart0_dev_send, uart0_dev_recv); + uart_init(); + sei(); +#endif + + printf_P(PSTR("Start\n")); + wait_ms(500); + + rdline_init(&rdl, write_char, valid_buffer, complete_buffer); + snprintf(prompt, sizeof(prompt), "main > "); + + rdline_newline(&rdl, prompt); + + c = -1; + while (1) { +#ifdef HOST_VERSION + n=read(0, &c, 1); + if (n<=0) + break; +#else + c=uart0_recv(); +#endif + + ret = rdline_char_in(&rdl, c); + if (ret == -2) + break; + + if (ret != 2 && ret != 0) { + rdline_add_history(&rdl, rdline_get_buffer(&rdl)); + rdline_newline(&rdl, prompt); + } + } + +#ifdef HOST_VERSION + tcsetattr(0, TCSANOW, &oldterm); +#endif + printf("\n"); + + return 0; +} + + diff --git a/modules/ihm/parse/test/rdline_config.h b/modules/ihm/parse/test/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/parse/test/uart_config.h b/modules/ihm/parse/test/uart_config.h new file mode 100644 index 0000000..9350c74 --- /dev/null +++ b/modules/ihm/parse/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.2 2007-11-24 22:57:54 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/ihm/rdline/CVS/Entries b/modules/ihm/rdline/CVS/Entries new file mode 100644 index 0000000..c0bad83 --- /dev/null +++ b/modules/ihm/rdline/CVS/Entries @@ -0,0 +1,5 @@ +/Makefile/1.1.2.1/Wed Sep 12 17:52:21 2007//Tb_zer0 +/rdline.c/1.1.2.9/Fri Feb 27 21:41:31 2009//Tb_zer0 +/rdline.h/1.1.2.6/Fri Feb 27 21:41:31 2009//Tb_zer0 +D/config//// +D/test//// diff --git a/modules/ihm/rdline/CVS/Repository b/modules/ihm/rdline/CVS/Repository new file mode 100644 index 0000000..3ff2a17 --- /dev/null +++ b/modules/ihm/rdline/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/rdline diff --git a/modules/ihm/rdline/CVS/Root b/modules/ihm/rdline/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/rdline/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/rdline/CVS/Tag b/modules/ihm/rdline/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/rdline/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/rdline/CVS/Template b/modules/ihm/rdline/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/rdline/Makefile b/modules/ihm/rdline/Makefile new file mode 100644 index 0000000..23f9616 --- /dev/null +++ b/modules/ihm/rdline/Makefile @@ -0,0 +1,6 @@ +TARGET = rdline + +# List C source files here. (C dependencies are automatically generated.) +SRC = rdline.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/ihm/rdline/config/CVS/Entries b/modules/ihm/rdline/config/CVS/Entries new file mode 100644 index 0000000..e773a6c --- /dev/null +++ b/modules/ihm/rdline/config/CVS/Entries @@ -0,0 +1,2 @@ +/rdline_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +D diff --git a/modules/ihm/rdline/config/CVS/Repository b/modules/ihm/rdline/config/CVS/Repository new file mode 100644 index 0000000..b8ef41f --- /dev/null +++ b/modules/ihm/rdline/config/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/rdline/config diff --git a/modules/ihm/rdline/config/CVS/Root b/modules/ihm/rdline/config/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/rdline/config/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/rdline/config/CVS/Tag b/modules/ihm/rdline/config/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/rdline/config/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/rdline/config/CVS/Template b/modules/ihm/rdline/config/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/rdline/config/rdline_config.h b/modules/ihm/rdline/config/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/rdline/rdline.c b/modules/ihm/rdline/rdline.c new file mode 100644 index 0000000..bb0169d --- /dev/null +++ b/modules/ihm/rdline/rdline.c @@ -0,0 +1,585 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: rdline.c,v 1.1.2.9 2009-02-27 21:41:31 zer0 Exp $ + * + * + */ + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <stdarg.h> +#include <ctype.h> + +#include <aversive/pgmspace.h> + +#include <cirbuf.h> +#include "rdline.h" + +static void rdline_puts_P(struct rdline * rdl, const prog_char * buf); +static void rdline_miniprintf_P(struct rdline * rdl, + const prog_char * buf, uint8_t val); + +#ifdef CONFIG_MODULE_RDLINE_HISTORY +static void rdline_remove_old_history_item(struct rdline * rdl); +static void rdline_remove_first_history_item(struct rdline * rdl); +static uint8_t rdline_get_history_size(struct rdline * rdl); +#endif /* CONFIG_MODULE_RDLINE_HISTORY */ + + +void rdline_init(struct rdline *rdl, + rdline_write_char_t *write_char, + rdline_validate_t *validate, + rdline_complete_t *complete) +{ + memset(rdl, 0, sizeof(*rdl)); + rdl->validate = validate; + rdl->complete = complete; + rdl->write_char = write_char; + rdl->status = RDLINE_INIT; +#ifdef CONFIG_MODULE_RDLINE_HISTORY + cirbuf_init(&rdl->history, rdl->history_buf, 0, RDLINE_HISTORY_BUF_SIZE); +#endif /* CONFIG_MODULE_RDLINE_HISTORY */ +} + +void +rdline_newline(struct rdline * rdl, const char * prompt) +{ + uint8_t i; + + vt100_init(&rdl->vt100); + cirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE); + cirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE); + + if (prompt != rdl->prompt) + memcpy(rdl->prompt, prompt, sizeof(rdl->prompt)-1); + rdl->prompt_size = strlen(prompt); + + for (i=0 ; i<rdl->prompt_size ; i++) + rdl->write_char(rdl->prompt[i]); + rdl->status = RDLINE_RUNNING; + +#ifdef CONFIG_MODULE_RDLINE_HISTORY + rdl->history_cur_line = -1; +#endif /* CONFIG_MODULE_RDLINE_HISTORY */ +} + +void +rdline_stop(struct rdline * rdl) +{ + rdl->status = RDLINE_INIT; +} + +void +rdline_restart(struct rdline * rdl) +{ + rdl->status = RDLINE_RUNNING; +} + +const char * +rdline_get_buffer(struct rdline * rdl) +{ + uint8_t len_l, len_r; + cirbuf_align_left(&rdl->left); + cirbuf_align_left(&rdl->right); + + len_l = CIRBUF_GET_LEN(&rdl->left); + len_r = CIRBUF_GET_LEN(&rdl->right); + memcpy(rdl->left_buf+len_l, rdl->right_buf, len_r); + + rdl->left_buf[len_l + len_r] = '\n'; + rdl->left_buf[len_l + len_r + 1] = '\0'; + return rdl->left_buf; +} + +static void +display_right_buffer(struct rdline * rdl) +{ + uint8_t i; + char tmp; + + rdline_puts_P(rdl, PSTR(vt100_clear_right)); + if (!CIRBUF_IS_EMPTY(&rdl->right)) { + CIRBUF_FOREACH(&rdl->right, i, tmp) { + rdl->write_char(tmp); + } + rdline_miniprintf_P(rdl, PSTR(vt100_multi_left), + CIRBUF_GET_LEN(&rdl->right)); + } +} + +void rdline_redisplay(struct rdline * rdl) +{ + uint8_t i; + char tmp; + + rdline_puts_P(rdl, PSTR(vt100_home)); + for (i=0 ; i<rdl->prompt_size ; i++) + rdl->write_char(rdl->prompt[i]); + CIRBUF_FOREACH(&rdl->left, i, tmp) { + rdl->write_char(tmp); + } + display_right_buffer(rdl); +} + +int8_t +rdline_char_in(struct rdline * rdl, char c) +{ + uint8_t i; + int8_t cmd; + char tmp; +#ifdef CONFIG_MODULE_RDLINE_HISTORY + char * buf; +#endif + + if (rdl->status != RDLINE_RUNNING) + return -1; + + cmd = vt100_parser(&rdl->vt100, c); + if (cmd == -2) + return 0; + + if (cmd >= 0) { + switch (cmd) { + case KEY_CTRL_B: + case KEY_LEFT_ARR: + if (CIRBUF_IS_EMPTY(&rdl->left)) + break; + tmp = cirbuf_get_tail(&rdl->left); + cirbuf_del_tail(&rdl->left); + cirbuf_add_head(&rdl->right, tmp); + rdline_puts_P(rdl, PSTR(vt100_left_arr)); + break; + + case KEY_CTRL_F: + case KEY_RIGHT_ARR: + if (CIRBUF_IS_EMPTY(&rdl->right)) + break; + tmp = cirbuf_get_head(&rdl->right); + cirbuf_del_head(&rdl->right); + cirbuf_add_tail(&rdl->left, tmp); + rdline_puts_P(rdl, PSTR(vt100_right_arr)); + break; + + case KEY_WLEFT: + while (! CIRBUF_IS_EMPTY(&rdl->left) && + (tmp = cirbuf_get_tail(&rdl->left)) && + isblank(tmp)) { + rdline_puts_P(rdl, PSTR(vt100_left_arr)); + cirbuf_del_tail(&rdl->left); + cirbuf_add_head(&rdl->right, tmp); + } + while (! CIRBUF_IS_EMPTY(&rdl->left) && + (tmp = cirbuf_get_tail(&rdl->left)) && + !isblank(tmp)) { + rdline_puts_P(rdl, PSTR(vt100_left_arr)); + cirbuf_del_tail(&rdl->left); + cirbuf_add_head(&rdl->right, tmp); + } + break; + + case KEY_WRIGHT: + while (! CIRBUF_IS_EMPTY(&rdl->right) && + (tmp = cirbuf_get_head(&rdl->right)) && + isblank(tmp)) { + rdline_puts_P(rdl, PSTR(vt100_right_arr)); + cirbuf_del_head(&rdl->right); + cirbuf_add_tail(&rdl->left, tmp); + } + while (! CIRBUF_IS_EMPTY(&rdl->right) && + (tmp = cirbuf_get_head(&rdl->right)) && + !isblank(tmp)) { + rdline_puts_P(rdl, PSTR(vt100_right_arr)); + cirbuf_del_head(&rdl->right); + cirbuf_add_tail(&rdl->left, tmp); + } + break; + + case KEY_BKSPACE: + if(!cirbuf_del_tail_safe(&rdl->left)) { + rdline_puts_P(rdl, PSTR(vt100_bs)); + display_right_buffer(rdl); + } + break; + + case KEY_META_BKSPACE: + while (! CIRBUF_IS_EMPTY(&rdl->left) && isblank(cirbuf_get_tail(&rdl->left))) { + rdline_puts_P(rdl, PSTR(vt100_bs)); + cirbuf_del_tail(&rdl->left); + } + while (! CIRBUF_IS_EMPTY(&rdl->left) && !isblank(cirbuf_get_tail(&rdl->left))) { + rdline_puts_P(rdl, PSTR(vt100_bs)); + cirbuf_del_tail(&rdl->left); + } + display_right_buffer(rdl); + break; + + case KEY_SUPPR: + case KEY_CTRL_D: + if(!cirbuf_del_head_safe(&rdl->right)) { + display_right_buffer(rdl); + } + if (cmd == KEY_CTRL_D && + CIRBUF_IS_EMPTY(&rdl->left) && + CIRBUF_IS_EMPTY(&rdl->right)) { + return -2; + } + break; + + case KEY_CTRL_A: + if (CIRBUF_IS_EMPTY(&rdl->left)) + break; + rdline_miniprintf_P(rdl, PSTR(vt100_multi_left), + CIRBUF_GET_LEN(&rdl->left)); + while (! CIRBUF_IS_EMPTY(&rdl->left)) { + tmp = cirbuf_get_tail(&rdl->left); + cirbuf_del_tail(&rdl->left); + cirbuf_add_head(&rdl->right, tmp); + } + break; + + case KEY_CTRL_E: + if (CIRBUF_IS_EMPTY(&rdl->right)) + break; + rdline_miniprintf_P(rdl, PSTR(vt100_multi_right), + CIRBUF_GET_LEN(&rdl->right)); + while (! CIRBUF_IS_EMPTY(&rdl->right)) { + tmp = cirbuf_get_head(&rdl->right); + cirbuf_del_head(&rdl->right); + cirbuf_add_tail(&rdl->left, tmp); + } + break; + +#ifdef CONFIG_MODULE_RDLINE_KILL_BUF + case KEY_CTRL_K: + cirbuf_get_buf_head(&rdl->right, rdl->kill_buf, RDLINE_BUF_SIZE); + rdl->kill_size = CIRBUF_GET_LEN(&rdl->right); + cirbuf_del_buf_head(&rdl->right, rdl->kill_size); + rdline_puts_P(rdl, PSTR(vt100_clear_right)); + break; + + case KEY_CTRL_Y: + i=0; + while(CIRBUF_GET_LEN(&rdl->right) + CIRBUF_GET_LEN(&rdl->left) < + RDLINE_BUF_SIZE && + i < rdl->kill_size) { + cirbuf_add_tail(&rdl->left, rdl->kill_buf[i]); + rdl->write_char(rdl->kill_buf[i]); + i++; + } + display_right_buffer(rdl); + break; +#endif /* CONFIG_MODULE_RDLINE_KILL_BUF */ + + case KEY_CTRL_C: + rdline_puts_P(rdl, PSTR("\r\n")); + rdline_newline(rdl, rdl->prompt); + break; + + case KEY_CTRL_L: + rdline_redisplay(rdl); + break; + + case KEY_TAB: + case KEY_HELP: + cirbuf_align_left(&rdl->left); + rdl->left_buf[CIRBUF_GET_LEN(&rdl->left)] = '\0'; + if (rdl->complete) { + char tmp_buf[127]; /* XXX */ + int16_t complete_state; + int8_t ret; + int tmp_size; + + if (cmd == KEY_TAB) + complete_state = 0; + else + complete_state = -1; + + ret = rdl->complete(rdl->left_buf, tmp_buf, sizeof(tmp_buf), + &complete_state); + /* no completion or error */ + if (ret <= 0) { + return 2; + } + + tmp_size = strlen(tmp_buf); + /* add chars */ + if (ret == 2) { + i=0; + while(CIRBUF_GET_LEN(&rdl->right) + CIRBUF_GET_LEN(&rdl->left) < + RDLINE_BUF_SIZE && + i < tmp_size) { + cirbuf_add_tail(&rdl->left, tmp_buf[i]); + rdl->write_char(tmp_buf[i]); + i++; + } + display_right_buffer(rdl); + return 2; /* ?? */ + } + + /* choice */ + rdline_puts_P(rdl, PSTR("\r\n")); + while (ret) { + rdl->write_char(' '); + for (i=0 ; tmp_buf[i] ; i++) + rdl->write_char(tmp_buf[i]); + rdline_puts_P(rdl, PSTR("\r\n")); + ret = rdl->complete(rdl->left_buf, tmp_buf, + sizeof(tmp_buf), &complete_state); + } + + rdline_redisplay(rdl); + } + return 2; + + case KEY_RETURN: + case KEY_RETURN2: + rdline_get_buffer(rdl); + rdl->status = RDLINE_INIT; + rdline_puts_P(rdl, PSTR("\r\n")); +#ifdef CONFIG_MODULE_RDLINE_HISTORY + if (rdl->history_cur_line != -1) + rdline_remove_first_history_item(rdl); +#endif + + if (rdl->validate) + rdl->validate(rdl->left_buf, CIRBUF_GET_LEN(&rdl->left)+2); + return 1; + +#ifdef CONFIG_MODULE_RDLINE_HISTORY + case KEY_UP_ARR: + if (rdl->history_cur_line == 0) { + rdline_remove_first_history_item(rdl); + } + if (rdl->history_cur_line <= 0) { + rdline_add_history(rdl, rdline_get_buffer(rdl)); + rdl->history_cur_line = 0; + } + + buf = rdline_get_history_item(rdl, rdl->history_cur_line + 1); + if (!buf) + break; + + rdl->history_cur_line ++; + vt100_init(&rdl->vt100); + cirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE); + cirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE); + cirbuf_add_buf_tail(&rdl->left, buf, strlen(buf)); + rdline_redisplay(rdl); + break; + + case KEY_DOWN_ARR: + if (rdl->history_cur_line - 1 < 0) + break; + + rdl->history_cur_line --; + buf = rdline_get_history_item(rdl, rdl->history_cur_line); + if (!buf) + break; + vt100_init(&rdl->vt100); + cirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE); + cirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE); + cirbuf_add_buf_tail(&rdl->left, buf, strlen(buf)); + rdline_redisplay(rdl); + + break; +#endif /* CONFIG_MODULE_RDLINE_HISTORY */ + + + default: + break; + } + + return 0; + } + + if (! isprint(c)) + return 0; + + /* standard chars */ + if (CIRBUF_GET_LEN(&rdl->left) + CIRBUF_GET_LEN(&rdl->right) >= RDLINE_BUF_SIZE) + return 0; + + if (cirbuf_add_tail_safe(&rdl->left, c)) + return 0; + + rdl->write_char(c); + display_right_buffer(rdl); + + return 0; +} + + +/* HISTORY */ + +#ifdef CONFIG_MODULE_RDLINE_HISTORY +static void +rdline_remove_old_history_item(struct rdline * rdl) +{ + char tmp; + + while (! CIRBUF_IS_EMPTY(&rdl->history) ) { + tmp = cirbuf_get_head(&rdl->history); + cirbuf_del_head(&rdl->history); + if (!tmp) + break; + } +} + +static void +rdline_remove_first_history_item(struct rdline * rdl) +{ + char tmp; + + if ( CIRBUF_IS_EMPTY(&rdl->history) ) { + return; + } + else { + cirbuf_del_tail(&rdl->history); + } + + while (! CIRBUF_IS_EMPTY(&rdl->history) ) { + tmp = cirbuf_get_tail(&rdl->history); + if (!tmp) + break; + cirbuf_del_tail(&rdl->history); + } +} + +static uint8_t +rdline_get_history_size(struct rdline * rdl) +{ + uint8_t i, tmp, ret=0; + + CIRBUF_FOREACH(&rdl->history, i, tmp) { + if (tmp == 0) + ret ++; + } + + return ret; +} + +char * +rdline_get_history_item(struct rdline * rdl, uint8_t idx) +{ + uint8_t len, i, tmp; + + len = rdline_get_history_size(rdl); + if ( idx >= len ) { + return NULL; + } + + cirbuf_align_left(&rdl->history); + + CIRBUF_FOREACH(&rdl->history, i, tmp) { + if ( idx == len - 1) { + return rdl->history_buf + i; + } + if (tmp == 0) + len --; + } + + return NULL; +} + +int8_t +rdline_add_history(struct rdline * rdl, const char * buf) +{ + cirbuf_uint len, i; + + len = strlen(buf); + for (i=0; i<len ; i++) { + if (buf[i] == '\n') { + len = i; + break; + } + } + + if ( len >= RDLINE_HISTORY_BUF_SIZE ) + return -1; + + while ( len >= CIRBUF_GET_FREELEN(&rdl->history) ) { + rdline_remove_old_history_item(rdl); + } + + cirbuf_add_buf_tail(&rdl->history, buf, len); + cirbuf_add_tail(&rdl->history, 0); + + return 0; +} + +void +rdline_clear_history(struct rdline * rdl) +{ + cirbuf_init(&rdl->history, rdl->history_buf, 0, RDLINE_HISTORY_BUF_SIZE); +} + +#else /* CONFIG_MODULE_RDLINE_HISTORY */ + +int8_t rdline_add_history(struct rdline * rdl, const char * buf) {return -1;} +void rdline_clear_history(struct rdline * rdl) {} +char * rdline_get_history_item(struct rdline * rdl, uint8_t i) {return NULL;} + + +#endif /* CONFIG_MODULE_RDLINE_HISTORY */ + + +/* STATIC USEFUL FUNCS */ + +static void +rdline_puts_P(struct rdline * rdl, const prog_char * buf) +{ + char c; + while ( (c=pgm_read_byte(buf++)) != '\0' ) { + rdl->write_char(c); + } +} + +/* a very very basic printf with one arg and one format 'u' */ +static void +rdline_miniprintf_P(struct rdline * rdl, const prog_char * buf, uint8_t val) +{ + char c, started=0, div=100; + + while ( (c=pgm_read_byte(buf++)) ) { + if (c=='%') { + c = pgm_read_byte(buf++); + + if (c=='u') { /* val is never more than 255 */ + while (div) { + c = val / div; + if (c || started) { + rdl->write_char(c+'0'); + started = 1; + } + val %= div; + div /= 10; + } + } + else { + rdl->write_char('%'); + rdl->write_char(c); + } + } + else { + rdl->write_char(c); + } + } +} + diff --git a/modules/ihm/rdline/rdline.h b/modules/ihm/rdline/rdline.h new file mode 100644 index 0000000..9e330b7 --- /dev/null +++ b/modules/ihm/rdline/rdline.h @@ -0,0 +1,192 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: rdline.h,v 1.1.2.6 2009-02-27 21:41:31 zer0 Exp $ + * + * + */ + +#ifndef _RDLINE_H_ +#define _RDLINE_H_ + +/** + * This library is a small equivalent to the GNU readline library, but + * it is designed for small systems, like Atmel AVR microcontrollers + * (8 bits). Indeed, we don't use any malloc that is sometimes not + * implemented on such systems. + */ + +#include <cirbuf.h> +#include <vt100.h> + +#define vt100_bell "\007" +#define vt100_bs "\010" +#define vt100_bs_clear "\010 \010" +#define vt100_tab "\011" +#define vt100_crnl "\012\015" +#define vt100_clear_right "\033[0K" +#define vt100_clear_left "\033[1K" +#define vt100_clear_down "\033[0J" +#define vt100_clear_up "\033[1J" +#define vt100_clear_line "\033[2K" +#define vt100_clear_screen "\033[2J" +#define vt100_up_arr "\033\133\101" +#define vt100_down_arr "\033\133\102" +#define vt100_right_arr "\033\133\103" +#define vt100_left_arr "\033\133\104" +#define vt100_multi_right "\033\133%uC" +#define vt100_multi_left "\033\133%uD" +#define vt100_suppr "\033\133\063\176" +#define vt100_home "\033M\033E" +#define vt100_word_left "\033\142" +#define vt100_word_right "\033\146" + +/* configuration */ +#define RDLINE_BUF_SIZE 64 +#define RDLINE_PROMPT_SIZE 16 +#define RDLINE_VT100_BUF_SIZE 8 +#define RDLINE_HISTORY_BUF_SIZE 128 +#define RDLINE_HISTORY_MAX_LINE 64 + +enum rdline_status { + RDLINE_INIT, + RDLINE_RUNNING, +}; + +struct rdline; + +typedef void (rdline_write_char_t)(char); +typedef void (rdline_validate_t)(const char *buf, uint8_t size); +typedef int8_t (rdline_complete_t)(const char *buf, char *dstbuf, + uint8_t dstsize, int16_t *state); + +struct rdline { + enum rdline_status status; + /* rdline bufs */ + struct cirbuf left; + struct cirbuf right; + char left_buf[RDLINE_BUF_SIZE+2]; /* reserve 2 chars for the \n\0 */ + char right_buf[RDLINE_BUF_SIZE]; + + char prompt[RDLINE_PROMPT_SIZE]; + uint8_t prompt_size; + +#ifdef CONFIG_MODULE_RDLINE_KILL_BUF + char kill_buf[RDLINE_BUF_SIZE]; + uint8_t kill_size; +#endif + +#ifdef CONFIG_MODULE_RDLINE_HISTORY + /* history */ + struct cirbuf history; + char history_buf[RDLINE_HISTORY_BUF_SIZE]; + int8_t history_cur_line; +#endif + + /* callbacks and func pointers */ + rdline_write_char_t *write_char; + rdline_validate_t *validate; + rdline_complete_t *complete; + + /* vt100 parser */ + struct vt100 vt100; +}; + +/** + * Init fields for a struct rdline. Call this only once at the beginning + * of your program. + * \param rdl A pointer to an uninitialized struct rdline + * \param write_char The function used by the function to write a character + * \param validate A pointer to the function to execute when the + * user validates the buffer. + * \param complete A pointer to the function to execute when the + * user completes the buffer. + */ +void rdline_init(struct rdline *rdl, + rdline_write_char_t *write_char, + rdline_validate_t *validate, + rdline_complete_t *complete); + + +/** + * Init the current buffer, and display a prompt. + * \param rdl A pointer to a struct rdline + * \param prompt A string containing the prompt + */ +void rdline_newline(struct rdline *rdl, const char *prompt); + +/** + * Call it and all received chars will be ignored. + * \param rdl A pointer to a struct rdline + */ +void rdline_stop(struct rdline *rdl); + +/** + * Restart after a call to rdline_stop() + * \param rdl A pointer to a struct rdline + */ +void rdline_restart(struct rdline *rdl); + +/** + * Redisplay the current buffer + * \param rdl A pointer to a struct rdline + */ +void rdline_redisplay(struct rdline *rdl); + + +/** + * append a char to the readline buffer. + * Return 1 when the line has been validated. + * Return 2 when the user asked to complete the buffer. + * Return -1 if it is not running. + * Return -2 if EOF (ctrl-d on an empty line). + * Else return 0. + * XXX error case when the buffer is full ? + * + * \param rdl A pointer to a struct rdline + * \param c The character to append + */ +int8_t rdline_char_in(struct rdline * rdl, char c); + +/** + * Return the current buffer, terminated by '\0'. + * \param rdl A pointer to a struct rdline + */ +const char *rdline_get_buffer(struct rdline *rdl); + + +/** + * Add the buffer to history. + * return < 0 on error. + * \param rdl A pointer to a struct rdline + * \param buf A buffer that is terminated by '\0' + */ +int8_t rdline_add_history(struct rdline *rdl, const char *buf); + +/** + * Clear current history + * \param rdl A pointer to a struct rdline + */ +void rdline_clear_history(struct rdline *rdl); + +/** + * Get the i-th history item + */ +char *rdline_get_history_item(struct rdline *rdl, uint8_t i); + +#endif /* _RDLINE_H_ */ diff --git a/modules/ihm/rdline/test/.config b/modules/ihm/rdline/test/.config new file mode 100644 index 0000000..72090df --- /dev/null +++ b/modules/ihm/rdline/test/.config @@ -0,0 +1,217 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +CONFIG_OPTM_0=y +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +# CONFIG_OPTM_S is not set +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/modules/ihm/rdline/test/CVS/Entries b/modules/ihm/rdline/test/CVS/Entries new file mode 100644 index 0000000..f57e558 --- /dev/null +++ b/modules/ihm/rdline/test/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.1.2.3/Wed Nov 21 21:54:39 2007//Tb_zer0 +/Makefile/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/error_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/main.c/1.1.2.3/Thu Nov 15 11:18:00 2007//Tb_zer0 +/rdline_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/uart_config.h/1.1.2.2/Wed Sep 12 19:03:08 2007//Tb_zer0 +D diff --git a/modules/ihm/rdline/test/CVS/Repository b/modules/ihm/rdline/test/CVS/Repository new file mode 100644 index 0000000..7f7d268 --- /dev/null +++ b/modules/ihm/rdline/test/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/rdline/test diff --git a/modules/ihm/rdline/test/CVS/Root b/modules/ihm/rdline/test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/rdline/test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/rdline/test/CVS/Tag b/modules/ihm/rdline/test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/rdline/test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/rdline/test/CVS/Template b/modules/ihm/rdline/test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/rdline/test/Makefile b/modules/ihm/rdline/test/Makefile new file mode 100644 index 0000000..639fab0 --- /dev/null +++ b/modules/ihm/rdline/test/Makefile @@ -0,0 +1,20 @@ +TARGET = main + +AVERSIVE_DIR = ../../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/modules/ihm/rdline/test/error_config.h b/modules/ihm/rdline/test/error_config.h new file mode 100644 index 0000000..872fb0b --- /dev/null +++ b/modules/ihm/rdline/test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/modules/ihm/rdline/test/main.c b/modules/ihm/rdline/test/main.c new file mode 100644 index 0000000..1165fb0 --- /dev/null +++ b/modules/ihm/rdline/test/main.c @@ -0,0 +1,254 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.3 2007-11-15 11:18:00 zer0 Exp $ + * + * + */ + +/* test program for rdline, works on AVR and HOST... but there are a + * lot of defines... ;) */ + +#include <stdio.h> +#include <string.h> + +//#define DEBUG_SOCKET + + +#ifdef HOST_VERSION +#include <unistd.h> +#include <stdlib.h> +#include <stdarg.h> +#include <inttypes.h> +#include <termios.h> +#include <ctype.h> + +#include <sys/socket.h> +#include <netinet/in.h> +#include <sys/socket.h> +#include <sys/un.h> +#endif + +#include <aversive/wait.h> +#include <uart.h> +#include "rdline.h" + +/* globals */ +struct rdline rdl; +char prompt[RDLINE_PROMPT_SIZE]; +int cpt=0; + + +#ifdef DEBUG_SOCKET /* debug... keep it because it is nice */ + +int s = -1; + +void sock_printf(const char * fmt, ...) +{ + va_list ap; + char buf[BUFSIZ]; + int n; + + va_start(ap, fmt); + n=vsnprintf(buf, BUFSIZ, fmt, ap); + if (s>0) write(s, buf, n); + va_end(ap); +} + +void dump_it(struct cirbuf * cbuf) +{ + int i; + char e; + + sock_printf("sta=%2.2d end=%2.2d len=%2.2d/%2.2d { ", + cbuf->start, cbuf->end, + CIRBUF_GET_LEN(cbuf), + CIRBUF_GET_MAXLEN(cbuf)); + + sock_printf("[ "); + CIRBUF_FOREACH(cbuf, i, e) { + sock_printf("%2.2x, ", e&0xFF); + } + sock_printf("]\n"); +} + +#else + +void sock_printf(const char * fmt, ...) {} +void dump_it(struct cirbuf * cbuf) {} + +#endif /* DEBUG_SOCKET */ + + +#ifdef HOST_VERSION +void +write_char(char c) { + write(1, &c, 1); +} +#else +void +write_char(char c) { + uart0_send(c); +} + +static void +rx(char c) +{ + int8_t ret; + ret = rdline_char_in(&rdl, c); + if (ret == 1) { + rdline_add_history(&rdl, rdline_get_buffer(&rdl)); + snprintf(prompt, sizeof(prompt), "toto[%d] > ", cpt++); + rdline_newline(&rdl, prompt); + } + else if (ret == -2) { + rdline_stop(&rdl); + printf("END\n"); + } +} + +#endif + + +void display_buffer(const char * buf, uint8_t size) +{ + printf("**** GOT (%d) >> %s", size, buf); +} + +const char * dummy_complete[] = { + "toto", + "titi", + "pouet", + "coin", +}; + +#define TEST_COMPLETION 1 +//#define TEST_COMPLETION 2 +int8_t complete_buffer(const char * buf, uint8_t size, + char * dstbuf, uint8_t dstsize, + int * state) +{ + sock_printf("complete -> %d\n", *state); +#if TEST_COMPLETION == 1 + if (*state < (sizeof(dummy_complete)/sizeof(const char *))) { + /* pourri mais bon c'est temporaire */ + strcpy(dstbuf, dummy_complete[*state]); + (*state) ++; + return 1; + } + return 0; +#else + dstbuf[0] = 'x'; + dstbuf[1] = 'y'; + dstbuf[2] = 'z'; + dstbuf[3] = '\0'; + return 2; +#endif +} + + + +int main(void) +{ +#ifdef HOST_VERSION + struct termios oldterm, term; + char buf[BUFSIZ]; + int n, i; + int8_t ret; +#endif +#ifdef DEBUG_SOCKET + struct sockaddr_in sin_ci; + + + s = socket(PF_INET, SOCK_STREAM, 0); + if (s < 0) { + printf("socket() failed\n"); + } + + memset(&sin_ci, 0, sizeof(sin_ci)); + sin_ci.sin_family = AF_INET; + sin_ci.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + sin_ci.sin_port = htons(31337); +#ifndef __linux__ + sin_ci.sin_len = sizeof(sin_ci); +#endif + + if (s > 0 && connect(s, (struct sockaddr *)&sin_ci, sizeof(sin_ci)) < 0) { + printf("connect() failed\n"); + s = -1; + } +#endif /* DEBUG_SOCKET */ + +#ifdef HOST_VERSION + tcgetattr(0, &oldterm); + memcpy(&term, &oldterm, sizeof(term)); + term.c_lflag &= ~(ICANON | ECHO | ISIG); + tcsetattr(0, TCSANOW, &term); + setbuf(stdin, NULL); +#else + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + + wait_ms(5000); + printf("Start\n"); + uart0_register_rx_event(rx); + + sei(); +#endif + + + /* common init */ + rdline_init(&rdl, write_char, display_buffer, complete_buffer); + snprintf(prompt, sizeof(prompt), "toto[%d] > ", cpt++); + rdline_newline(&rdl, prompt); + + + /* loop to send chars on host */ +#ifdef HOST_VERSION + while ((n=read(0, buf, BUFSIZ-1)) > 0) { + buf[n] = 0; + + for (i=0 ; i<n ; i++) { + sock_printf("%o ", buf[i]&0xff); + } + sock_printf(" RECV\n"); + for (i=0 ; i<n ; i++) { + ret = rdline_char_in(&rdl, buf[i]); + if (ret == 1) { + rdline_add_history(&rdl, rdline_get_buffer(&rdl)); + snprintf(prompt, sizeof(prompt), "toto[%d] > ", cpt++); + rdline_newline(&rdl, prompt); + } + else if (ret == -2) { + tcsetattr(0, TCSANOW, &oldterm); + printf("\n"); + return 0; + } + } + } + + tcsetattr(0, TCSANOW, &oldterm); + printf("\n"); + + /* irq driven on avr, see rx() */ +#else + while(1); +#endif + + return 0; +} diff --git a/modules/ihm/rdline/test/rdline_config.h b/modules/ihm/rdline/test/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/rdline/test/uart_config.h b/modules/ihm/rdline/test/uart_config.h new file mode 100644 index 0000000..16eef08 --- /dev/null +++ b/modules/ihm/rdline/test/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.2 2007-09-12 19:03:08 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/modules/ihm/vt100/CVS/Entries b/modules/ihm/vt100/CVS/Entries new file mode 100644 index 0000000..7bfcd97 --- /dev/null +++ b/modules/ihm/vt100/CVS/Entries @@ -0,0 +1,4 @@ +/Makefile/1.1.2.1/Sat Jan 5 22:46:28 2008//Tb_zer0 +/vt100.c/1.1.2.1/Sat Jan 5 22:46:28 2008//Tb_zer0 +/vt100.h/1.1.2.2/Tue Apr 7 20:01:16 2009//Tb_zer0 +D diff --git a/modules/ihm/vt100/CVS/Repository b/modules/ihm/vt100/CVS/Repository new file mode 100644 index 0000000..2031337 --- /dev/null +++ b/modules/ihm/vt100/CVS/Repository @@ -0,0 +1 @@ +aversive/modules/ihm/vt100 diff --git a/modules/ihm/vt100/CVS/Root b/modules/ihm/vt100/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/modules/ihm/vt100/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/modules/ihm/vt100/CVS/Tag b/modules/ihm/vt100/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/modules/ihm/vt100/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/modules/ihm/vt100/CVS/Template b/modules/ihm/vt100/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/modules/ihm/vt100/Makefile b/modules/ihm/vt100/Makefile new file mode 100644 index 0000000..5a57b3c --- /dev/null +++ b/modules/ihm/vt100/Makefile @@ -0,0 +1,6 @@ +TARGET = vt100 + +# List C source files here. (C dependencies are automatically generated.) +SRC = vt100.c + +include $(AVERSIVE_DIR)/mk/aversive_module.mk diff --git a/modules/ihm/vt100/vt100.c b/modules/ihm/vt100/vt100.c new file mode 100644 index 0000000..f006119 --- /dev/null +++ b/modules/ihm/vt100/vt100.c @@ -0,0 +1,146 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: vt100.c,v 1.1.2.1 2008-01-05 22:46:28 zer0 Exp $ + * + * + */ + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <stdarg.h> +#include <ctype.h> + +#include <aversive/pgmspace.h> + +#include "vt100.h" + +static const prog_char cmd0[] = vt100_up_arr; +static const prog_char cmd1[] = vt100_down_arr; +static const prog_char cmd2[] = vt100_right_arr; +static const prog_char cmd3[] = vt100_left_arr; +static const prog_char cmd4[] = "\177"; +static const prog_char cmd5[] = "\n"; +static const prog_char cmd6[] = "\001"; +static const prog_char cmd7[] = "\005"; +static const prog_char cmd8[] = "\013"; +static const prog_char cmd9[] = "\031"; +static const prog_char cmd10[] = "\003"; +static const prog_char cmd11[] = "\006"; +static const prog_char cmd12[] = "\002"; +static const prog_char cmd13[] = vt100_suppr; +static const prog_char cmd14[] = vt100_tab; +static const prog_char cmd15[] = "\004"; +static const prog_char cmd16[] = "\014"; +static const prog_char cmd17[] = "\r"; +static const prog_char cmd18[] = "\033\177"; +static const prog_char cmd19[] = vt100_word_left; +static const prog_char cmd20[] = vt100_word_right; +static const prog_char cmd21[] = "?"; + +const prog_char * vt100_commands[] PROGMEM = { + cmd0, cmd1, cmd2, cmd3, cmd4, cmd5, cmd6, cmd7, + cmd8, cmd9, cmd10, cmd11, cmd12, cmd13, cmd14, + cmd15, cmd16, cmd17, cmd18, cmd19, cmd20, + cmd21, +}; + +void +vt100_init(struct vt100 * vt) +{ + vt->state = VT100_INIT; +} + + +static int8_t +match_command(char * buf, uint8_t size) +{ + const prog_char * cmd; + uint8_t i = 0; + + for (i=0 ; i<sizeof(vt100_commands)/sizeof(const prog_char *) ; i++) { +#ifdef HOST_VERSION + cmd = *(vt100_commands + i); +#else + cmd = (const prog_char *) pgm_read_word (vt100_commands + i); +#endif + + if (size == strlen_P(cmd) && + !strncmp_P(buf, cmd, strlen_P(cmd))) { + return i; + } + } + + return -1; +} + +int8_t +vt100_parser(struct vt100 *vt, char ch) +{ + uint8_t size; + uint8_t c = (uint8_t) ch; + + if (vt->bufpos > VT100_BUF_SIZE) { + vt->state = VT100_INIT; + vt->bufpos = 0; + } + + vt->buf[vt->bufpos++] = c; + size = vt->bufpos; + + switch (vt->state) { + case VT100_INIT: + if (c == 033) { + vt->state = VT100_ESCAPE; + } + else { + vt->bufpos = 0; + goto match_command; + } + break; + + case VT100_ESCAPE: + if (c == 0133) { + vt->state = VT100_ESCAPE_CSI; + } + else if (c >= 060 && c <= 0177) { /* XXX 0177 ? */ + vt->bufpos = 0; + vt->state = VT100_INIT; + goto match_command; + } + break; + + case VT100_ESCAPE_CSI: + if (c >= 0100 && c <= 0176) { + vt->bufpos = 0; + vt->state = VT100_INIT; + goto match_command; + } + break; + + default: + vt->bufpos = 0; + break; + } + + return -2; + + match_command: + return match_command(vt->buf, size); +} diff --git a/modules/ihm/vt100/vt100.h b/modules/ihm/vt100/vt100.h new file mode 100644 index 0000000..c41becd --- /dev/null +++ b/modules/ihm/vt100/vt100.h @@ -0,0 +1,103 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: vt100.h,v 1.1.2.2 2009-04-07 20:01:16 zer0 Exp $ + * + * + */ + +#ifndef _VT100_H_ +#define _VT100_H_ + +#define vt100_bell "\007" +#define vt100_bs "\010" +#define vt100_bs_clear "\010 \010" +#define vt100_tab "\011" +#define vt100_crnl "\012\015" +#define vt100_clear_right "\033[0K" +#define vt100_clear_left "\033[1K" +#define vt100_clear_down "\033[0J" +#define vt100_clear_up "\033[1J" +#define vt100_clear_line "\033[2K" +#define vt100_clear_screen "\033[2J" +#define vt100_up_arr "\033\133\101" +#define vt100_down_arr "\033\133\102" +#define vt100_right_arr "\033\133\103" +#define vt100_left_arr "\033\133\104" +#define vt100_multi_right "\033\133%uC" +#define vt100_multi_left "\033\133%uD" +#define vt100_suppr "\033\133\063\176" +#define vt100_home "\033M\033E" +#define vt100_word_left "\033\142" +#define vt100_word_right "\033\146" + + +/* Result of parsing : it must be synchronized with vt100_commands[] + * in vt100.c */ +#define KEY_UP_ARR 0 +#define KEY_DOWN_ARR 1 +#define KEY_RIGHT_ARR 2 +#define KEY_LEFT_ARR 3 +#define KEY_BKSPACE 4 +#define KEY_RETURN 5 +#define KEY_CTRL_A 6 +#define KEY_CTRL_E 7 +#define KEY_CTRL_K 8 +#define KEY_CTRL_Y 9 +#define KEY_CTRL_C 10 +#define KEY_CTRL_F 11 +#define KEY_CTRL_B 12 +#define KEY_SUPPR 13 +#define KEY_TAB 14 +#define KEY_CTRL_D 15 +#define KEY_CTRL_L 16 +#define KEY_RETURN2 17 +#define KEY_META_BKSPACE 18 +#define KEY_WLEFT 19 +#define KEY_WRIGHT 20 +#define KEY_HELP 21 + +extern const prog_char * vt100_commands[] PROGMEM; + +enum vt100_parser_state { + VT100_INIT, + VT100_ESCAPE, + VT100_ESCAPE_CSI, +}; + +#define VT100_BUF_SIZE 8 +struct vt100 { + uint8_t bufpos; + char buf[VT100_BUF_SIZE]; + enum vt100_parser_state state; +}; + +/** + * Init + */ +void vt100_init(struct vt100 *vt); + +/** + * Input a new character. + * Return -1 if the character is not part of a control sequence + * Return -2 if c is not the last char of a control sequence + * Else return the index in vt100_commands[] + */ +int8_t vt100_parser(struct vt100 *vt, char c); + +#endif diff --git a/projects/CVS/Entries b/projects/CVS/Entries new file mode 100644 index 0000000..de013f5 --- /dev/null +++ b/projects/CVS/Entries @@ -0,0 +1,7 @@ +D/example1//// +D/example2//// +D/firefly_example1//// +D/kbd_uart_test//// +D/profiling_example//// +D/microb2009//// +D/microb2010//// diff --git a/projects/CVS/Repository b/projects/CVS/Repository new file mode 100644 index 0000000..745149f --- /dev/null +++ b/projects/CVS/Repository @@ -0,0 +1 @@ +aversive/projects diff --git a/projects/CVS/Root b/projects/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/CVS/Tag b/projects/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/projects/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/projects/CVS/Template b/projects/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/example1/.config b/projects/example1/.config new file mode 100644 index 0000000..f4fb1ab --- /dev/null +++ b/projects/example1/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +CONFIG_MODULE_FIXED_POINT=y +CONFIG_MODULE_VECT2=y +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +CONFIG_MODULE_SCHEDULER_USE_TIMERS=y +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +CONFIG_MODULE_TIME=y +CONFIG_MODULE_TIME_CREATE_CONFIG=y + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +CONFIG_MODULE_QUADRAMP_DERIVATE=y +CONFIG_MODULE_BIQUAD=y + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +CONFIG_MODULE_AES=y +CONFIG_MODULE_AES_CTR=y +CONFIG_MODULE_MD5=y +CONFIG_MODULE_MD5_HMAC=y +CONFIG_MODULE_RC4=y + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/example1/CVS/Entries b/projects/example1/CVS/Entries new file mode 100644 index 0000000..ee56801 --- /dev/null +++ b/projects/example1/CVS/Entries @@ -0,0 +1,9 @@ +/.config/1.5.4.8/Sun Apr 13 16:52:41 2008//Tb_zer0 +/Makefile/1.8.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/error_config.h/1.3.4.2/Thu Dec 6 08:58:00 2007//Tb_zer0 +/main.c/1.11.4.2/Wed May 23 17:18:15 2007//Tb_zer0 +/scheduler_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/time_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/timer_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/uart_config.h/1.2.8.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +D diff --git a/projects/example1/CVS/Repository b/projects/example1/CVS/Repository new file mode 100644 index 0000000..72cb1c0 --- /dev/null +++ b/projects/example1/CVS/Repository @@ -0,0 +1 @@ +aversive/projects/example1 diff --git a/projects/example1/CVS/Root b/projects/example1/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/example1/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/example1/CVS/Tag b/projects/example1/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/projects/example1/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/projects/example1/CVS/Template b/projects/example1/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/example1/Makefile b/projects/example1/Makefile new file mode 100644 index 0000000..6d5d8e2 --- /dev/null +++ b/projects/example1/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR =../..# VALUE, absolute or relative path : example ../.. # + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/projects/example1/error_config.h b/projects/example1/error_config.h new file mode 100644 index 0000000..95c3076 --- /dev/null +++ b/projects/example1/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.3.4.2 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/example1/main.c b/projects/example1/main.c new file mode 100644 index 0000000..44ba583 --- /dev/null +++ b/projects/example1/main.c @@ -0,0 +1,402 @@ +#include <stdio.h> +#include <string.h> + +#include <aversive/wait.h> +#include <aversive/list.h> +#include <uart.h> + + +LIST_TYPEDEF(fifo_t, char, 32); +volatile fifo_t my_fifo; + +#define SCANCODE_MAX_SIZE 8 + +#define SCANCODE_BREAK 1 /* break code */ +#define SCANCODE_EXTENDED 2 /* is extended */ +#define SCANCODE_HAS_NO_BREAK 4 /* no associated break code */ + +struct scancode { + uint8_t buf[SCANCODE_MAX_SIZE]; + uint8_t size; + uint8_t idx; + uint8_t flags; +}; + +char tab[] = { + /***** 0x00 */ + 0, + 0, /* F9 */ + 0, + 0, /* F5 */ + 0, /* F3 */ + 0, /* F1 */ + 0, /* F2 */ + 0, /* F12 */ + 0, + 0, /* F10 */ + 0, /* F8 */ + 0, /* F6 */ + 0, /* F4 */ + 0, /* TAB */ + 'E', /* E */ + 0, + + /***** 0x10 */ + 0, + 0, /* AltL */ + 0, /* ShiftL */ + 0, + 0, /* CtrlL */ + 'Q', /* Q */ + '1', /* 1 */ + 0, + 0, + 0, + 'Z', /* Z */ + 'S', /* S */ + 'A', /* A */ + 'W', /* W */ + '2', /* 2 */ + 0, + + /***** 0x20 */ + 0, + 'C', /* C */ + 'X', /* X */ + 'D', /* D */ + 'E', /* E */ + '4', /* 4 */ + '3', /* 3 */ + 0, + 0, + 0, /* Space */ + 'V', /* V */ + 'F', /* F */ + 'T', /* T */ + 'R', /* R */ + '5', /* 5 */ + 0, + + /***** 0x30 */ + 0, + 'N', /* N */ + 'B', /* B */ + 'H', /* H */ + 'G', /* G */ + 'Y', /* Y */ + '6', /* 6 */ + 0, + 0, + 0, + 'M', /* M */ + 'J', /* J */ + 'U', /* U */ + '7', /* 7 */ + '8', /* 8 */ + 0, + + /***** 0x40 */ + 0, + '<', /* < */ + 'K', /* K */ + 'I', /* I */ + 'O', /* O */ + '0', /* 0 */ + '9', /* 9 */ + 0, + 0, + '>', /* > */ + '?', /* ? */ + 'L', /* L */ + ':', /* : */ + 'P', /* P */ + '-', /* - */ + 0, + + /***** 0x50 */ + 0, + 0, + '"', /* " */ + 0, + '[', /* [ */ + 'a', /* a */ + 0, + 0, + 0, /* CapsLk */ + 0, /* ShiftR */ + 0, /* EnterL */ + ']', /* ] */ + 0, + '\\', /* \\ */ + 0, + 0, + + /***** 0x60 */ + 0, + 0, /* Macro */ + 0, + 0, + 0, + 0, + 0, /* BS */ + 0, + 0, + '1', /* 1 */ + 0, + '4', /* 4 */ + '7', /* 7 */ + 0, + 0, + 0, + + /***** 0x70 */ + '0', /* 0 */ + 0, /* Del */ + '2', /* 2 */ + '5', /* 5 */ + '6', /* 6 */ + '8', /* 8 */ + 0, /* Esc */ + 0, /* NumLk */ + 0, /* F11 */ + '+', /* + */ + '3', /* 3 */ + '-', /* - */ + '*', /* * */ + '9', /* 9 */ + 0, /* ScrLk */ + 0, + + /***** 0x80 */ + 0, + 0, + 0, + 0, /* F7 */ + 0, /* Alt-PRTSC */ + +#define SCANCODE_EXTENDED_LIST "\x11\x14\x4A\x5A\x69\x6B\x6C\x70\x71\x72\x74\x75\x7A\x7C\x7D" +#define SCANCODE_EXTENDED_LIST_SIZE 15 +#define SCANCODE_EXTENDED_LIST_OFFSET 0x85 + + 0, /* 0x0E11 AltR */ + 0, /* 0x0E14 CtrlR */ + 0, /* 0x0E4A / */ + 0, /* 0x0E5A Enter */ + 0, /* 0x0E69 End */ + 0, /* 0x0E6B Left */ + 0, /* 0x0E6C Home */ + 0, /* 0x0E70 Insert */ + 0, /* 0x0E71 Delete */ + 0, /* 0x0E72 Down */ + 0, /* 0x0E74 Right */ + + /***** 0x90 */ + 0, /* 0x0E75 Up */ + 0, /* 0x0E7A Pgdn */ + 0, /* 0x0E7C Ctrl-Prtscr */ + 0, /* 0x0E7D Pgup */ + + + + /* Exceptions */ + +#define SCANCODE_VAL_PAUSE "\xE1\x14\x77\xE1\xF0\x14\xF0\x77" +#define SCANCODE_VAL_PAUSE_SIZE 8 +#define SCANCODE_VAL_PAUSE_OFFSET 0 + +#define SCANCODE_VAL_PRTSCR_BREAK "\xE0\xF0\x12\xE0\xF0\x7C" +#define SCANCODE_VAL_PRTSCR_BREAK_SIZE 6 +#define SCANCODE_VAL_PRTSCR_BREAK_OFFSET 1 + +#define SCANCODE_VAL_CTRL_PAUSE "\xE0\x7E\xE0\xF0\x7E" +#define SCANCODE_VAL_CTRL_PAUSE_SIZE 5 +#define SCANCODE_VAL_CTRL_PAUSE_OFFSET 2 + +#define SCANCODE_VAL_SHIFT_SLASH "\xE0\xF0\x12\xE0\x4A" +#define SCANCODE_VAL_SHIFT_SLASH_SIZE 5 +#define SCANCODE_VAL_SHIFT_SLASH_OFFSET 3 + +#define SCANCODE_VAL_SHIFT_SLASH_BREAK "\xE0\xF0\x4A\xE0\x12" +#define SCANCODE_VAL_SHIFT_SLASH_BREAK_SIZE 5 +#define SCANCODE_VAL_SHIFT_SLASH_BREAK_OFFSET 3 + +#define SCANCODE_VAL_PRTSCR "\xE0\x12\xE0\x7C" +#define SCANCODE_VAL_PRTSCR_SIZE 4 +#define SCANCODE_VAL_PRTSCR_OFFSET 1 + + + 0, /* E11477E1F014F077 PAUSE */ + 0, /* E012E07C PRTSCR */ + 0, /* E07EE0F07E CTRL_PAUSE */ + 0, /* E0F012E04A SHIFT_SLASH */ + 0, /* E012E07C */ +}; + +char * scancode_extended_list = SCANCODE_EXTENDED_LIST; + + + + +int8_t get_scancode(struct scancode *s) +{ + char * p; + + s->flags = 0; + s->size = LIST_TO_ARRAY(my_fifo, s->buf, SCANCODE_MAX_SIZE); + printf("%d\n", s->size); + + if (!s->size) + return -1; + + /* special case for 'pause' */ + if (s->size >= SCANCODE_VAL_PAUSE_SIZE && + !memcmp(SCANCODE_VAL_PAUSE, s->buf, SCANCODE_VAL_PAUSE_SIZE)) { + s->flags |= (SCANCODE_EXTENDED | SCANCODE_HAS_NO_BREAK); + s->size = SCANCODE_VAL_PAUSE_SIZE; + s->idx = SCANCODE_EXTENDED_LIST_OFFSET + SCANCODE_EXTENDED_LIST_SIZE + SCANCODE_VAL_PAUSE_OFFSET; + return 0; + } + + + /* extended codes */ + if (s->buf[0] == 0xE0 && s->size >= 2) { + s->flags |= SCANCODE_EXTENDED; + + /* special case for 'prtscr break' */ + if (s->size >= SCANCODE_VAL_PRTSCR_BREAK_SIZE && + !memcmp(SCANCODE_VAL_PRTSCR_BREAK, s->buf, SCANCODE_VAL_PRTSCR_BREAK_SIZE)) { + s->flags |= SCANCODE_BREAK; + s->size = SCANCODE_VAL_PRTSCR_BREAK_SIZE; + s->idx = SCANCODE_EXTENDED_LIST_OFFSET + SCANCODE_EXTENDED_LIST_SIZE + SCANCODE_VAL_PRTSCR_BREAK_OFFSET; + return 0; + } + + /* special case for 'ctrl_pause' */ + if (s->size >= SCANCODE_VAL_CTRL_PAUSE_SIZE && + !memcmp(SCANCODE_VAL_CTRL_PAUSE, s->buf, SCANCODE_VAL_CTRL_PAUSE_SIZE)) { + s->flags |= SCANCODE_HAS_NO_BREAK; + s->size = SCANCODE_VAL_CTRL_PAUSE_SIZE; + s->idx = SCANCODE_EXTENDED_LIST_OFFSET + SCANCODE_EXTENDED_LIST_SIZE + SCANCODE_VAL_CTRL_PAUSE_OFFSET; + return 0; + } + + /* special case for 'shift_slash' */ + if (s->size >= SCANCODE_VAL_SHIFT_SLASH_SIZE && + !memcmp(SCANCODE_VAL_SHIFT_SLASH, s->buf, SCANCODE_VAL_SHIFT_SLASH_SIZE)) { + s->size = SCANCODE_VAL_SHIFT_SLASH_SIZE; + s->idx = SCANCODE_EXTENDED_LIST_OFFSET + SCANCODE_EXTENDED_LIST_SIZE + SCANCODE_VAL_SHIFT_SLASH_OFFSET; + return 0; + } + + /* special case for 'shift_slash_break' */ + if (s->size >= SCANCODE_VAL_SHIFT_SLASH_BREAK_SIZE && + !memcmp(SCANCODE_VAL_SHIFT_SLASH_BREAK, s->buf, SCANCODE_VAL_SHIFT_SLASH_BREAK_SIZE)) { + s->flags |= SCANCODE_BREAK; + s->size = SCANCODE_VAL_SHIFT_SLASH_BREAK_SIZE; + s->idx = SCANCODE_EXTENDED_LIST_OFFSET + SCANCODE_EXTENDED_LIST_SIZE + SCANCODE_VAL_SHIFT_SLASH_BREAK_OFFSET; + return 0; + } + + /* special case for 'prtscr' */ + if (s->size >= SCANCODE_VAL_PRTSCR_SIZE && + !memcmp(SCANCODE_VAL_PRTSCR, s->buf, SCANCODE_VAL_PRTSCR_SIZE)) { + s->size = SCANCODE_VAL_PRTSCR_SIZE; + s->idx = SCANCODE_EXTENDED_LIST_OFFSET +SCANCODE_EXTENDED_LIST_SIZE + SCANCODE_VAL_PRTSCR_OFFSET; + return 0; + } + + /* break for extended codes */ + if (s->size >= 3 && s->buf[1] == 0xF0) { + s->flags |= SCANCODE_BREAK; + s->size = 3; + p = strchr(scancode_extended_list, s->buf[2]); + if (!p) + return -1; + s->idx = (p - scancode_extended_list) + SCANCODE_EXTENDED_LIST_OFFSET; + return 0; + } + + /* ext scancode, 2 bytes */ + s->size = 2; + p = strchr(scancode_extended_list, s->buf[2]); + if (!p) + return -1; + s->idx = (p - scancode_extended_list) + SCANCODE_EXTENDED_LIST_OFFSET; + return 0; + } + + /* break scancode (2 bytes) */ + if (s->buf[0] == 0xF0) { + s->flags |= SCANCODE_BREAK; + s->size = 2; + s->idx = s->buf[1]; + if (s->idx >= SCANCODE_EXTENDED_LIST_OFFSET) + return -1; + return 0; + } + + /* simple scancode, 1 byte */ + s->idx = s->buf[0]; + if (s->idx >= SCANCODE_EXTENDED_LIST_OFFSET) + return -1; + + s->size = 1; + return 0; +} + +void print_scancode(struct scancode *s) +{ + uint8_t i; + printf("[ "); + for (i=0 ; i<s->size ; i++) + printf("%.2x ", s->buf[i]); + printf("] '%c' ", tab[s->idx]); + if (s->flags & SCANCODE_BREAK) + printf("BREAK "); + if (s->flags & SCANCODE_EXTENDED) + printf("EXTENDED "); + if (s->flags & SCANCODE_HAS_NO_BREAK) + printf("HAS_NO_BREAK "); + printf("idx=%d\r\n", s->idx); +} + +int main(void) +{ + struct scancode s; + char c; + + LIST_INIT(my_fifo, 0); + + LIST_PUSH_END(my_fifo, 0x35); + LIST_PUSH_END(my_fifo, 0xF0); + LIST_PUSH_END(my_fifo, 0x35); + + LIST_PUSH_END(my_fifo, 0xE1); + LIST_PUSH_END(my_fifo, 0x14); + LIST_PUSH_END(my_fifo, 0x77); + LIST_PUSH_END(my_fifo, 0xE1); + LIST_PUSH_END(my_fifo, 0xF0); + LIST_PUSH_END(my_fifo, 0x14); + LIST_PUSH_END(my_fifo, 0xF0); + LIST_PUSH_END(my_fifo, 0x77); + + LIST_PUSH_END(my_fifo, 0xE0); + LIST_PUSH_END(my_fifo, 0xF0); + LIST_PUSH_END(my_fifo, 0x12); + LIST_PUSH_END(my_fifo, 0xE0); + LIST_PUSH_END(my_fifo, 0x4A); + + LIST_PUSH_END(my_fifo, 0xE0); + LIST_PUSH_END(my_fifo, 0xF0); + LIST_PUSH_END(my_fifo, 0x11); + + + + while(get_scancode(&s) >= 0) { + print_scancode(&s); + while(s.size--) + LIST_PULL_START(my_fifo, &c); + } + + return 0; +} diff --git a/projects/example1/scheduler_config.h b/projects/example1/scheduler_config.h new file mode 100644 index 0000000..358df1d --- /dev/null +++ b/projects/example1/scheduler_config.h @@ -0,0 +1,77 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1.2.1 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 5 + + +/* define it only if CONFIG_MODULE_SCHEDULER_USE_TIMERS is enabled. In + this case, precaler is defined in timers_config.h in your project + directory. */ +#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS +/** the num of the timer to use for the scheduler */ +#define SCHEDULER_TIMER_NUM 0 + +/* or set the prescaler manually (in this case, you use must TIMER0, + and the prescaler must be a correct value regarding the AVR device + you are using (look in include/aversive/parts.h). Obviously, the + values of SCHEDULER_CK and SCHEDULER_CLOCK_PRESCALER must also be + coherent (TIMER0_PRESCALER_DIV_VALUE and VALUE) */ +#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */ + + +#ifdef CONFIG_MODULE_SCHEDULER_TIMER0 +/* The 2 values below MUST be coherent: + * if SCHEDULER_CK = TIMER0_PRESCALER_DIV_x, then + * you must have SCHEDULER_CLOCK_PRESCALER = x too !!! */ +#define SCHEDULER_CK TIMER0_PRESCALER_DIV_8 +#define SCHEDULER_CLOCK_PRESCALER 8 + +#endif /* CONFIG_MODULE_SCHEDULER_TIMER0 */ + +/* last case, the scheduler is called manually. The user has to + define the period here */ +#ifdef CONFIG_MODULE_SCHEDULER_MANUAL + +#define SCHEDULER_UNIT_FLOAT 1000.0 +#define SCHEDULER_UNIT 1000UL + +#endif /* CONFIG_MODULE_SCHEDULER_MANUAL */ + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/example1/time_config.h b/projects/example1/time_config.h new file mode 100644 index 0000000..94b541d --- /dev/null +++ b/projects/example1/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.1.2.1 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000l diff --git a/projects/example1/timer_config.h b/projects/example1/timer_config.h new file mode 100644 index 0000000..b27e570 --- /dev/null +++ b/projects/example1/timer_config.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.1 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +#define TIMER1_ENABLED +#define TIMER1A_ENABLED +#define TIMER1B_ENABLED +#define TIMER1C_ENABLED + +#define TIMER2_ENABLED + +#define TIMER3_ENABLED +#define TIMER3A_ENABLED +#define TIMER3B_ENABLED +#define TIMER3C_ENABLED + +#define TIMER0_PRESCALER_DIV 1 +#define TIMER1_PRESCALER_DIV 1 +#define TIMER2_PRESCALER_DIV 1 +#define TIMER3_PRESCALER_DIV 1 diff --git a/projects/example1/uart_config.h b/projects/example1/uart_config.h new file mode 100644 index 0000000..1e38d99 --- /dev/null +++ b/projects/example1/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2.8.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/projects/example2/.config b/projects/example2/.config new file mode 100644 index 0000000..22a4c76 --- /dev/null +++ b/projects/example2/.config @@ -0,0 +1,248 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/example2/CVS/Entries b/projects/example2/CVS/Entries new file mode 100644 index 0000000..4016a5d --- /dev/null +++ b/projects/example2/CVS/Entries @@ -0,0 +1,6 @@ +/.config/1.2.2.6/Sun Apr 13 16:52:41 2008//Tb_zer0 +/Makefile/1.5.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/error_config.h/1.1.2.1/Thu Dec 6 08:58:00 2007//Tb_zer0 +/main.c/1.4.6.3/Mon May 28 12:55:48 2007//Tb_zer0 +/uart_config.h/1.1.2.1/Wed May 23 17:18:15 2007//Tb_zer0 +D diff --git a/projects/example2/CVS/Repository b/projects/example2/CVS/Repository new file mode 100644 index 0000000..57a2760 --- /dev/null +++ b/projects/example2/CVS/Repository @@ -0,0 +1 @@ +aversive/projects/example2 diff --git a/projects/example2/CVS/Root b/projects/example2/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/example2/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/example2/CVS/Tag b/projects/example2/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/projects/example2/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/projects/example2/CVS/Template b/projects/example2/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/example2/Makefile b/projects/example2/Makefile new file mode 100644 index 0000000..6d5d8e2 --- /dev/null +++ b/projects/example2/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR =../..# VALUE, absolute or relative path : example ../.. # + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/projects/example2/error_config.h b/projects/example2/error_config.h new file mode 100644 index 0000000..872fb0b --- /dev/null +++ b/projects/example2/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2007-12-06 08:58:00 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/example2/main.c b/projects/example2/main.c new file mode 100644 index 0000000..da4134f --- /dev/null +++ b/projects/example2/main.c @@ -0,0 +1,273 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4.6.3 2007-05-28 12:55:48 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/list.h> + +#include <uart.h> + +#include <stdio.h> +#include <string.h> + +LIST_TYPEDEF(my_list_type, u08, 4); +LIST_TYPEDEF(my_another_list_type, u08, 10); + +void dumplist(struct generic_list * l) +{ + u08 i; + + for(i=0 ; i < l->hdr.size ; i++) + printf( (i != l->hdr.size-1 ? + "|-------" : "|-------|"CR) ); + + for(i=0 ; i < l->hdr.size ; i++) { + if (( i < l->hdr.beg_indice ) && (l->hdr.cur_size > 0)) { + if (i < (l->hdr.beg_indice + + l->hdr.cur_size) + % l->hdr.size) { + printf(" %.3d ", l->elt[i]); + + } + else { + printf(" XXX "); + } + } + else if (l->hdr.cur_size > 0){ + if (i < l->hdr.beg_indice + l->hdr.cur_size) { + printf(" %.3d ", l->elt[i]); + } + else { + printf(" XXX "); + } + } + else { + printf(" XXX "); + } + } + + printf(" cur_size=%d"CR,l->hdr.cur_size); + + for(i=0 ; i < l->hdr.size ; i++) + printf( (i != l->hdr.size-1 ? + "|-------" : "|-------|"CR) ); + + for(i=0 ; i < l->hdr.size ; i++) + { + if((i == l->hdr.beg_indice) && (l->hdr.cur_size <= 1)) + printf(" beg^end"); + else if(i == l->hdr.beg_indice) + printf(" beg^ "); + else if((l->hdr.cur_size > 1) && + (i == ((l->hdr.beg_indice + l->hdr.cur_size -1) + % l->hdr.size))) + printf(" end^ "); + else + printf(" "); + printf( (i != l->hdr.size-1 ? + "" : CR) ); + } + + for(i=0 ; i < l->hdr.size ; i++) + { + if(i == ((l->hdr.beg_indice + l->hdr.read_cursor) + % l->hdr.size)) + printf(" cur^ "); + else + printf(" "); + printf( (i != l->hdr.size-1 ? + "" : CR) ); + } + +} + +int main(void) +{ + u08 tmp=0; + u08 tab1[4]= "0123"; + u08 tab2[4]; + +#ifndef HOST_VERSION +/* uart_init(); */ +/* fdevopen((int (*)(char))uart0_send,(int (*)(void))uart0_recv,0); */ +#endif + my_list_type my_list ; + my_another_list_type another_list ; + + LIST_INIT(my_list, 0); + LIST_INIT(another_list, 8); + + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_PUSH_END(my_list, 2); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_PUSH_END(my_list, 3); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_PUSH_START(my_list, 1); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_PUSH_END(my_list, 4); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_PUSH_END(my_list, 5); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + + LIST_PULL_END(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + + LIST_READ_START(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_END(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_GOTO(my_list, &tmp, 0); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_GOTO(my_list, &tmp, 1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_GOTO(my_list, &tmp, 2); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_GOTO(my_list, &tmp, 3); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 2); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 3); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 2); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, 3); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, -1); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, -2); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_READ_MOVE(my_list, &tmp, -3); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + + + LIST_PULL_END(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_PULL_START(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_PULL_START(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf("tmp = %d"CR CR CR,tmp); + + LIST_PULL_START(my_list, &tmp); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + printf(CR CR); + + + LIST_ARRAY_PUSH_START(another_list, tab1, 4); + dumplist((struct generic_list *)&another_list); + printf(CR CR); + + LIST_ARRAY_PUSH_END(another_list, "abcde", 5); + dumplist((struct generic_list *)&another_list); + printf(CR CR); + + LIST_ARRAY_PULL_START(another_list, tab2, 4); + dumplist((struct generic_list *)&another_list); + printf(CR CR); + + LIST_ARRAY_PULL_END(another_list, tab2, 2); + dumplist((struct generic_list *)&another_list); + printf(CR CR); + + LIST_ALIGN_LEFT(another_list); + dumplist((struct generic_list *)&another_list); + printf(CR CR); + + + LIST_INIT(my_list,0); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_ARRAY_PUSH_START(my_list, tab1, 3); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + LIST_ALIGN_LEFT(my_list); + dumplist((struct generic_list *)&my_list); + printf(CR CR); + + + return 0; +} diff --git a/projects/example2/uart_config.h b/projects/example2/uart_config.h new file mode 100644 index 0000000..b4b5ca3 --- /dev/null +++ b/projects/example2/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2007-05-23 17:18:15 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 38400 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 4 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/projects/firefly_example1/.config b/projects/firefly_example1/.config new file mode 100644 index 0000000..47a966b --- /dev/null +++ b/projects/firefly_example1/.config @@ -0,0 +1,238 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +CONFIG_MCU_ATMEGA1281=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=8000000 + +# +# Generation options +# +CONFIG_OPTM_0=y +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +# CONFIG_OPTM_S is not set +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +CONFIG_MODULE_SCHEDULER_USE_TIMERS=y +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +CONFIG_MODULE_TIME_EXT=y +CONFIG_MODULE_TIME_EXT_CREATE_CONFIG=y + +# +# Communication modules +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +CONFIG_MODULE_TIMER_DYNAMIC=y +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +CONFIG_MODULE_CC2420=y +CONFIG_MODULE_CC2420_CREATE_CONFIG=y + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +# CONFIG_AVRDUDE_PROG_STK200 is not set +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PROG_AVR109=y +CONFIG_AVRDUDE_PORT="/dev/ttyUSB1" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/firefly_example1/CVS/Entries b/projects/firefly_example1/CVS/Entries new file mode 100644 index 0000000..849e316 --- /dev/null +++ b/projects/firefly_example1/CVS/Entries @@ -0,0 +1,11 @@ +/.config/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/Makefile/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/cc2420_config.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/error_config.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/firefly2_2.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/main.c/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/spi_config.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/time_ext_config.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/timer_config.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +/uart_config.h/1.1.2.1/Fri Jan 30 20:32:09 2009//Tb_zer0 +D diff --git a/projects/firefly_example1/CVS/Repository b/projects/firefly_example1/CVS/Repository new file mode 100644 index 0000000..552fec4 --- /dev/null +++ b/projects/firefly_example1/CVS/Repository @@ -0,0 +1 @@ +aversive/projects/firefly_example1 diff --git a/projects/firefly_example1/CVS/Root b/projects/firefly_example1/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/firefly_example1/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/firefly_example1/CVS/Tag b/projects/firefly_example1/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/projects/firefly_example1/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/projects/firefly_example1/CVS/Template b/projects/firefly_example1/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/firefly_example1/Makefile b/projects/firefly_example1/Makefile new file mode 100644 index 0000000..183250c --- /dev/null +++ b/projects/firefly_example1/Makefile @@ -0,0 +1,24 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR =../..# VALUE, absolute or relative path : example ../.. # + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +# Add special avrdude flags here +AVRDUDE_FLAGS_OPT += -b115200 + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/projects/firefly_example1/cc2420_config.h b/projects/firefly_example1/cc2420_config.h new file mode 100644 index 0000000..eccf5d9 --- /dev/null +++ b/projects/firefly_example1/cc2420_config.h @@ -0,0 +1,93 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#ifndef _CC2420_CONFIG_H +#define _CC2420_CONFIG_H + +/* + * Configure HERE your hardware connections to the device + * Here is the list of connections between the CC2420 and the AVR: + * - VREG_EN Enable the onchip voltage regulator + * - RESET Drive the CC2420 reset line + * - FIFO RX FIFO status line + * - FIFOP RX FIFO status line + * - CCA Clear Channel Assessment + * - SFD Timing information + * + * In addition the chip communicates through a 4-wire SPI connection + * Thus you have to enable the SPI module in Aversive. The CC2420 is a slave + * on the SPI bus. + * + * For more information please see the CC2420 DataSheet. + */ + + +/* + * VREG_EN - Enable the CC2420 voltage regulator + */ + +/* Comment if you don't drive VREG_EN from the microcontroller */ +#define CC2420_VREG_ENABLE +#define CC2420_VREG_EN_PORT PORTA +#define CC2420_VREG_EN_PIN 5 + +/* + * RESET - Drive the CC2420 reset line + */ + +/* Comment if you don't drive RESET from the microcontroller */ +#define CC2420_RESET_ENABLE +#define CC2420_RESET_PORT PORTA +#define CC2420_RESET_PIN 6 + +/* + * FIFO status lines + */ +#define CC2420_FIFO_PORT PORTC +#define CC2420_FIFO_PIN 1 + +#define CC2420_FIFOP_PORT PORTE +#define CC2420_FIFOP_PIN 7 + +/* + * CCA status line + */ +#define CC2420_CCA_PORT PORTD +#define CC2420_CCA_PIN 4 + +/* + * SFD status line + */ +#define CC2420_SFD_PORT PORTD +#define CC2420_SFD_PIN 6 + +/* + * SPI Slave Select (SS pin) configuration + */ +#define CC2420_SS_DDR DDRC +#define CC2420_SS_PORT PORTC +#define CC2420_SS_PIN 0 + + + +#endif /* _CC2420_CONFIG_H */ diff --git a/projects/firefly_example1/error_config.h b/projects/firefly_example1/error_config.h new file mode 100644 index 0000000..5c6c4e9 --- /dev/null +++ b/projects/firefly_example1/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1.2.1 2009-01-30 20:32:09 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +//#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/firefly_example1/firefly2_2.h b/projects/firefly_example1/firefly2_2.h new file mode 100644 index 0000000..aaf2c5a --- /dev/null +++ b/projects/firefly_example1/firefly2_2.h @@ -0,0 +1,51 @@ +#ifndef FIREFLY2_2_H +#define FIREFLY2_2_H + + +/* Firefly2_2 hardware */ +#define INPUT_PIN 0 +#define OUTPUT_PIN 1 + +/* SPI */ +#define SPI_SS 0 // PB.0 - Output: SPI Slave Select +#define SCK 1 // PB.1 - Output: SPI Serial Clock +#define MOSI 2 // PB.2 +#define CSN 0 // PC.0 - Output: SPI Chip Select (CS_N) + + +/* User interface */ +#define LED_DDR DDRE +#define LED_PORT PORTE +#define LED_ORANGE 2 // PE.2 +#define LED_BLUE 3 // PE.3 +#define LED_GREEN 4 // PE.4 +#define LED_RED 5 // PE.5 + +#define BUTTON_DDR DDRA +#define BUTTON_PORT PINA +#define BUTTON_PIN 7 // PA.7 + +/* Debug interface */ +#define DEBUG_0 3 // PA.3 +#define DEBUG_1 4 // PA.4 +#define DEBUG_2 0 // PD.0 +#define DEBUG_3 1 // PD.1 + + + +/* Useful routines */ + +/* use sbi() and cbi() instead */ +#define SET(port, pin) port |= (1<<(pin)) +#define CLR(port, pin) port &= ~(1<<(pin)) + +/* test of bit (pin) of (port) + * Substitutes as 1 if pin is set, or 0 if not */ +#define TST(port, pin) ((port & (1<<(pin)))>>(pin)) + +/* To set leds you have to clear the bit (yeah, I know...) */ +#define LED_SET(led) cbi(LED_PORT, (led)) +#define LED_CLR(led) sbi(LED_PORT, (led)) + + +#endif diff --git a/projects/firefly_example1/main.c b/projects/firefly_example1/main.c new file mode 100644 index 0000000..19e1b77 --- /dev/null +++ b/projects/firefly_example1/main.c @@ -0,0 +1,273 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/error.h> +#include <aversive/errno.h> +#include <aversive/wait.h> +#include <avr/interrupt.h> + +#include <stdio.h> +#include <string.h> +#include <math.h> + +#include <uart.h> +#include <spi.h> +#include <cc2420.h> +#include <cc2420_arch.h> +#include <time_ext.h> + + +#include "firefly2_2.h" + + +uint8_t i; + + + +/* + * When an unexpected interrupt occurs + */ +ISR(__vector_default) +{ + /* Notify the user */ + EMERG(EFAULT, "Bad interrupt vector !"); + + /* Loop and blink the leds */ + while(TRUE) + { + LED_SET(LED_BLUE); + LED_SET(LED_GREEN); + LED_SET(LED_ORANGE); + LED_SET(LED_RED); + wait_ms(100); + + LED_CLR(LED_BLUE); + LED_CLR(LED_RED); + LED_CLR(LED_ORANGE); + LED_CLR(LED_GREEN); + wait_ms(100); + } +} + + +/* + * LOG function + */ +void mylog(struct error * e, ...) +{ + char *severity; + char *module; + va_list ap; + uint16_t stream_flags = stdout->flags; + volatile time_ext_t time = time_ext_get(); + + + switch(e->severity) + { + case ERROR_SEVERITY_EMERG: severity = "[EMERG]"; break; + case ERROR_SEVERITY_ERROR: severity = "[ERROR]"; break; + case ERROR_SEVERITY_WARNING: severity = "[WARNING]"; break; + case ERROR_SEVERITY_NOTICE: severity = "[NOTICE]"; break; + case ERROR_SEVERITY_DEBUG: severity = "[DEBUG]"; break; + default: severity = "[DEFAULT]"; break; + } + + switch(e->err_num) + { + case E_SPI: module = "[SPI] "; break; + case E_CC2420: module = "[CC2420]"; break; + case E_TIME_EXT: module = "[TIME] "; break; + default: module = ""; break; + } + + va_start(ap, e); + //vfprintf_P(stdout, severity, ap); + //vfprintf_P(stdout, module, ap); + printf_P(PSTR("(%lu %lu) "), time.sec, time.nano); + printf_P(PSTR("%s"), severity); + printf_P(PSTR("%s "), module); + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR("\r\n")); + va_end(ap); + stdout->flags = stream_flags; +} + + +void init_ports(void) +{ + /* No pull-up resistor */ + MCUCR |= (1<<PUD); + + /* Leds -> ouputs */ + LED_DDR = _BV(LED_ORANGE) | _BV(LED_BLUE) | _BV(LED_GREEN) | _BV(LED_RED); + + /* Button -> output */ + cbi(BUTTON_DDR, BUTTON_PIN); +} + + +int main(void) +{ + uint16_t reg; + uint8_t buffer[368]; + uint16_t i; + uint8_t j; + + /* Initialize Time module */ + time_ext_init(); + time_ext_set(0, 0); + //sei(); + + /* Initialize firefly ports */ + init_ports(); + + /* Initialize uart1 to send debug messages */ + uart_init(); + fdevopen(uart1_dev_send, uart1_dev_recv); + + /* register log function */ + error_register_emerg(mylog); + error_register_error(mylog); + error_register_warning(mylog); + error_register_notice(mylog); + error_register_debug(mylog); + + NOTICE(ESUCCESS, "\r\n\r\n\r\n\r\n\r\n\r\n **************************************"); + NOTICE(ESUCCESS, "MCUSR = 0x%x", MCUSR); + + + /* Clear all leds*/ + LED_CLR(LED_GREEN); + LED_CLR(LED_ORANGE); + LED_CLR(LED_RED); + LED_CLR(LED_BLUE); + + /* Light up yellow led */ + LED_SET(LED_ORANGE); + + cc2420_init(); + + + NOTICE(ESUCCESS, "Ready !"); + + + /* Test SPI link: reading CC2420 registers */ + // MAIN - default = 0xF800 + reg = cc2420_read_register(MAIN); + if(reg == 0xF800) + NOTICE(ESUCCESS, "MAIN read [OK]"); + else + ERROR(42, "MAIN should be 0xF800, read 0x%x", reg); + + + NOTICE(ESUCCESS, "MANFIDH = 0x%x", cc2420_read_register(MANFIDH)); + NOTICE(ESUCCESS, "MANFIDL = 0x%x", cc2420_read_register(MANFIDL)); + NOTICE(ESUCCESS, "SYNCWORD = 0x%x", cc2420_read_register(SYNCWORD)); + cc2420_write_register(SYNCWORD, 0xdead); + NOTICE(ESUCCESS, "SYNCWORD = 0x%x", cc2420_read_register(SYNCWORD)); + NOTICE(ESUCCESS, "STAT = 0x%x", cc2420_get_status()); + + + uint8_t tmp = 0x42; + cc2420_read_ram(RAM_IEEEADR, &tmp, 1); + NOTICE(ESUCCESS, "RAM_IEEEADR = 0x%x", tmp); + NOTICE(ESUCCESS, "STAT = 0x%x", cc2420_get_status()); + tmp = 0x42; + cc2420_write_ram(RAM_IEEEADR, &tmp, 1); + NOTICE(ESUCCESS, "STAT = 0x%x", cc2420_get_status()); + cc2420_read_ram(RAM_IEEEADR, &tmp, 1); + NOTICE(ESUCCESS, "RAM_IEEEADR = 0x%x", tmp); + NOTICE(ESUCCESS, "STAT = 0x%x", cc2420_get_status()); + + +//#if 0 + /* test TXFIFO and RAM access */ + for(i = 0; i < 128; i++) + buffer[i] = i; + NOTICE(ESUCCESS, "Writing to RXFIFO..."); + cc2420_write_rxfifo(buffer, 128); + /* Read all RAM */ + NOTICE(ESUCCESS, "Reading RXFIFO..."); + cc2420_read_rxfifo(buffer, 128); + + /* Dump buffer contents */ + NOTICE(ESUCCESS, "RAM content after RXFIFO write"); + for(i = 0; i < 23; i++) + { + printf("0x%x \t| ", i*16); + for(j = 0; j < 16; j++) + printf("%x ", buffer[i*16+j]); + printf("\r\n"); + } + + + /* Write and Read RAM */ + for(i = 0; i < 128; i++) + buffer[i] = i; + NOTICE(ESUCCESS, "Writing to RAM..."); + cc2420_write_ram(RAM_TXFIFO, buffer, 128); + /* Read all RAM */ + NOTICE(ESUCCESS, "Reading RAM..."); + cc2420_read_ram(RAM_TXFIFO, buffer, 368); + + /* Dump buffer contents */ + NOTICE(ESUCCESS, "RAM content after write to RAM"); + for(i = 0; i < 23; i++) + { + printf("0x%x \t| ", i*16); + for(j = 0; j < 16; j++) + printf("%x ", buffer[i*16+j]); + printf("\r\n"); + } +//#endif + + + /* + * TEST for PORT and DDR and stuff + */ + NOTICE(ESUCCESS, "&PORTC = 0x%x | PORTC = 0x%x | *(&PORTC) = 0x%x", + &PORTC, PORTC, *(&PORTC)); + spi_display_ss_lines(); + + + /* Infinite loop */ + while(1) + { + if(!TST(BUTTON_PORT, BUTTON_PIN)) + { + time_ext_t local_time = time_ext_get(); + LED_SET(LED_BLUE); + NOTICE(ESUCCESS, "Button event at %ld %ld", + local_time.sec, local_time.nano); + NOTICE(ESUCCESS, "STAT = 0x%x", cc2420_get_status()); + NOTICE(ESUCCESS, "DDRC = 0x%x | PORTC = 0x%x", DDRC, PORTC); + while(!TST(BUTTON_PORT, BUTTON_PIN)) + ; + NOTICE(ESUCCESS, "STAT = 0x%x", cc2420_get_status()); + } + else + LED_CLR(LED_BLUE); + } +} diff --git a/projects/firefly_example1/spi_config.h b/projects/firefly_example1/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/firefly_example1/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/firefly_example1/time_ext_config.h b/projects/firefly_example1/time_ext_config.h new file mode 100644 index 0000000..e514a6e --- /dev/null +++ b/projects/firefly_example1/time_ext_config.h @@ -0,0 +1,40 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ +#ifndef _TIME_EXT_CONFIG_H_ +#define _TIME_EXT_CONFIG_H_ + + +/* + * Speed of your external Quartz (in Hertz) + * Typically you want it to be a 32.768kHz watch-like quartz + */ +#define TIME_EXT_QUARTZ_FREQ 32768000UL + +/* Quartz period (1/freq) in NANO-SECONDS + * The rounding error here, for a 32768kHz quartz, + * is of 36450 ns per 24 hours. + */ +#define TIME_EXT_QUARTZ_PERIOD 30518UL + + +#endif /* _TIME_EXT_CONFIG_H_ */ diff --git a/projects/firefly_example1/timer_config.h b/projects/firefly_example1/timer_config.h new file mode 100644 index 0000000..63be6f8 --- /dev/null +++ b/projects/firefly_example1/timer_config.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.1 2009-01-30 20:32:09 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +#define TIMER1_ENABLED +#define TIMER1A_ENABLED +#define TIMER1B_ENABLED +#define TIMER1C_ENABLED + +#define TIMER2_ENABLED + +#define TIMER3_ENABLED +#define TIMER3A_ENABLED +#define TIMER3B_ENABLED +#define TIMER3C_ENABLED + +#define TIMER0_PRESCALER_DIV 1 +#define TIMER1_PRESCALER_DIV 1 +#define TIMER2_PRESCALER_DIV 1 +#define TIMER3_PRESCALER_DIV 1 diff --git a/projects/firefly_example1/uart_config.h b/projects/firefly_example1/uart_config.h new file mode 100644 index 0000000..ed58967 --- /dev/null +++ b/projects/firefly_example1/uart_config.h @@ -0,0 +1,109 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2009-01-30 20:32:09 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +//#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 0 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 0 + +#define UART0_BAUDRATE 115200 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 1 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 32 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +/* + * UART1 definitions + */ + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 0 + +#define UART1_BAUDRATE 115200 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 0 +//#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 32 +#define UART1_TX_FIFO_SIZE 16 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +#define UART1_STOP_BIT UART_STOP_BITS_1 +//#define UART1_STOP_BIT UART_STOP_BITS_2 + +#endif + diff --git a/projects/kbd_uart_test/CVS/Entries b/projects/kbd_uart_test/CVS/Entries new file mode 100644 index 0000000..4cb02db --- /dev/null +++ b/projects/kbd_uart_test/CVS/Entries @@ -0,0 +1,11 @@ +/Makefile/1.10.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/hour_config.h/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/kbd_config.h/1.2.4.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/kbd_simple_config.h/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/lcd_config.h/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/main.c/1.14.4.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/menu.txt/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/scheduler_config.h/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/time_config.h/1.1.10.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +/uart_config.h/1.3.4.1/Sun Nov 26 21:06:06 2006//Tb_zer0 +D diff --git a/projects/kbd_uart_test/CVS/Repository b/projects/kbd_uart_test/CVS/Repository new file mode 100644 index 0000000..c726a71 --- /dev/null +++ b/projects/kbd_uart_test/CVS/Repository @@ -0,0 +1 @@ +aversive/projects/kbd_uart_test diff --git a/projects/kbd_uart_test/CVS/Root b/projects/kbd_uart_test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/kbd_uart_test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/kbd_uart_test/CVS/Tag b/projects/kbd_uart_test/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/projects/kbd_uart_test/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/projects/kbd_uart_test/CVS/Template b/projects/kbd_uart_test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/kbd_uart_test/Makefile b/projects/kbd_uart_test/Makefile new file mode 100644 index 0000000..6d5d8e2 --- /dev/null +++ b/projects/kbd_uart_test/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR =../..# VALUE, absolute or relative path : example ../.. # + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/projects/kbd_uart_test/hour_config.h b/projects/kbd_uart_test/hour_config.h new file mode 100644 index 0000000..dbad747 --- /dev/null +++ b/projects/kbd_uart_test/hour_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: hour_config.h,v 1.1.10.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000l diff --git a/projects/kbd_uart_test/kbd_config.h b/projects/kbd_uart_test/kbd_config.h new file mode 100644 index 0000000..8cf8ee0 --- /dev/null +++ b/projects/kbd_uart_test/kbd_config.h @@ -0,0 +1,63 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: kbd_config.h,v 1.2.4.1 2006-11-26 21:06:06 zer0 Exp $ + * + */ + +#ifndef _KBD_CONFIG_H_ +#define _KBD_CONFIG_H_ _SIMPLE + +/* this config file is only for use with the kbd_simple module*/ + +//do not change for this line please +typedef uint8_t kbd_type; + + +#define KBD_FIFO_SIZE 4 + +#define KBD_COL1ROW1 '1' +#define KBD_COL1ROW2 '2' +#define KBD_COL1ROW3 '3' +#define KBD_COL1ROW4 '4' +#define KBD_COL2ROW1 '5' +#define KBD_COL2ROW2 '6' +#define KBD_COL2ROW3 '7' +#define KBD_COL2ROW4 '8' +#define KBD_COL3ROW1 '9' +#define KBD_COL3ROW2 '0' +#define KBD_COL3ROW3 '*' +#define KBD_COL3ROW4 '#' + + +#define KBD_PORT PORTA +#define KBD_DDR DDRA +#define KBD_PIN PINA + +#define KBD_COL1_BIT 4 +#define KBD_COL2_BIT 5 +#define KBD_COL3_BIT 6 + +#define KBD_ROW1_BIT 0 +/* Implicit, don't define it +#define KBD_ROW2_BIT (KBD_ROW1_BIT+1) +#define KBD_ROW3_BIT (KBD_ROW1_BIT+2) +#define KBD_ROW4_BIT (KBD_ROW1_BIT+3) +*/ + + +#endif diff --git a/projects/kbd_uart_test/kbd_simple_config.h b/projects/kbd_uart_test/kbd_simple_config.h new file mode 100644 index 0000000..3239c8a --- /dev/null +++ b/projects/kbd_uart_test/kbd_simple_config.h @@ -0,0 +1,36 @@ +#ifndef _KBD_CONFIG_H_ +#define _KBD_CONFIG_H_ + +#define KBD_FIFO_SIZE 4 + +#define KBD_COL1ROW1 '1' +#define KBD_COL1ROW2 '4' +#define KBD_COL1ROW3 '7' +#define KBD_COL1ROW4 '*' +#define KBD_COL2ROW1 '2' +#define KBD_COL2ROW2 '5' +#define KBD_COL2ROW3 '8' +#define KBD_COL2ROW4 '0' +#define KBD_COL3ROW1 '3' +#define KBD_COL3ROW2 '6' +#define KBD_COL3ROW3 '9' +#define KBD_COL3ROW4 '#' + + +#define KBD_PORT PORTA +#define KBD_DDR DDRA +#define KBD_PIN PINA + +#define KBD_COL1_BIT 4 +#define KBD_COL2_BIT 5 +#define KBD_COL3_BIT 6 + +#define KBD_ROW1_BIT 0 +/* Implicit, don't define it +#define KBD_ROW2_BIT (KBD_ROW1_BIT+1) +#define KBD_ROW3_BIT (KBD_ROW1_BIT+2) +#define KBD_ROW4_BIT (KBD_ROW1_BIT+3) +*/ + + +#endif diff --git a/projects/kbd_uart_test/lcd_config.h b/projects/kbd_uart_test/lcd_config.h new file mode 100644 index 0000000..a8ad98f --- /dev/null +++ b/projects/kbd_uart_test/lcd_config.h @@ -0,0 +1,27 @@ +/* change these definitions to adapt setting */ +// changed PIN in BIT to avoid confusion, don'use old version +#define LCD_PORT PORTC + +/* If the LCD module is a 1 line version with double addressing (8 + chars by segment), you need to define LCD_LINES to 2 and + LCD_DOUBLE_ADDRESSING to 1. This is the case with for example + SAMSUNG LTN 211 - N01. +*/ + +#define LCD_LINES 2 /* visible lines */ +#define LCD_LINE_LENGTH 0x40 /* internal line length */ +#define LCD_START_LINE1 0x00 /* DDRAM address of first char of line 1 */ +#define LCD_START_LINE2 0x40 /* DDRAM address of first char of line 2 */ +#define LCD_START_LINE3 0x14 /* DDRAM address of first char of line 3 */ +#define LCD_START_LINE4 0x54 /* DDRAM address of first char of line 4 */ + +#define LCD_DOUBLE_ADDRESSING 1 + +#define LCD_DATA_PORT LCD_PORT /* port for 4bit data */ +#define LCD_FIRST_DATA_BIT 3 +#define LCD_RS_PORT LCD_PORT /* port for RS line */ +#define LCD_RS_BIT 0 +#define LCD_RW_PORT LCD_PORT /* port for RW line */ +#define LCD_RW_BIT 1 +#define LCD_E_PORT LCD_PORT /* port for Enable line */ +#define LCD_E_BIT 2 diff --git a/projects/kbd_uart_test/main.c b/projects/kbd_uart_test/main.c new file mode 100644 index 0000000..35c66ef --- /dev/null +++ b/projects/kbd_uart_test/main.c @@ -0,0 +1,225 @@ +#include <stdio.h> +#include <string.h> + +#include <base/fifo/fifo.h> +#include <comm/uart/uart.h> +#include <other/kbd/kbd.h> +#include <base/wait/wait.h> +#include <time/scheduler/scheduler.h> +#include <time/hour/hour.h> +//#include <other/menu/menu.h> +#include <other/lcd/lcd.h> + +uint8_t global=16; +FILE * lcd; + + + +void process(uint8_t c) +{ + char tab[16]; + uint16_t nb; + int add; + + tab[0] = 0; + + uart0_send(c); + + if(c=='\r') + { + nb=scanf("%s %d",tab,&add); + + if( !strcmp(tab,"set")) + { + time_set(add,0); + printf("\r\n>> time set to %d\r\n",add); + } + else if (!strcmp(tab,"get")) + printf("\r\n>> %d secondes\r\n",time_get_s()); + else if (!strcmp(tab,"show")) + printf("\r\n>> Value at 0x%X : %d\r\n",add,*(uint8_t *)add); + else + printf("\r\n>> command not found\r\n"); + } +} + + + + +/* void menu_print(void) */ +/* { */ +/* int8_t tmp=menu_current(); */ + +/* menu_init_brother_list(); */ + +/* lcd_clrscr(); */ +/* while(tmp != 0) */ +/* { */ +/* fprintf(lcd,"|"); */ +/* tmp=menu_up(tmp); */ +/* } */ +/* fprintf(lcd,"%s%s",(menu_is_leaf(menu_current())?"* ":"> "),menu_txt(menu_current())); */ + +/* } */ + + + +/* void menu_control(uint8_t c) */ +/* { */ +/* if(c == '0') */ +/* menu_set(menu_left(menu_current())); */ +/* else if(c=='8') */ +/* menu_set(menu_right(menu_current())); */ +/* else if(c=='*') */ +/* { */ +/* if(menu_action_is_allowed()) */ +/* menu_action_disallow(); */ +/* else */ +/* menu_set(menu_up(menu_current())); */ +/* } */ +/* else if(c=='#') */ +/* { */ +/* if(menu_is_leaf(menu_current())) */ +/* menu_action_allow(); */ +/* else */ +/* menu_set(menu_down(menu_current())); */ +/* } */ + +/* menu_print(); */ +/* } */ + +FIFO_DECLARE_TYPE(g_read_fifo, uint8_t, 16); +FIFO_DEFINE(g_read_fifo); +FIFO_DEFINE_FUNCTIONS(uint8_t); + +int kbd_get_next(void) +{ + uint8_t c; + + if(FIFO_IS_FULL(g_read_fifo)) + return -1; + + FIFO_DEL_ELT(&c, g_read_fifo); + + return c; +} + + +/* void menu_add_char(uint8_t c) */ +/* { */ +/* int val; */ + +/* // exit */ +/* if(c=='*') */ +/* { */ +/* FIFO_ADD_ELT(' ', g_read_fifo, uint8_t); */ +/* menu_action_disallow(); */ +/* kbd_register_event(menu_control); */ +/* fscanf(lcd,"%d",&val); */ +/* time_set(val,0); */ +/* printf("\r\nLCD: time set to %d\r\n",val); */ +/* menu_print(); */ +/* return; */ +/* } */ + +/* lcd_putc(c); */ +/* FIFO_ADD_ELT(c, g_read_fifo, uint8_t); */ +/* } */ + + + + +// PE1 PE3 PB3 PB4 +void leds(void) +{ + static uint8_t a=0; + + PORTB=a++; +} + +int main(void) +{ + /* LEDS */ + DDRB=0x18; + + uart_init(); + // kbd_init(); + scheduler_init(); + // lcd_init(LCD_DISP_ON); + // menu_init(); + + FIFO_INIT(g_read_fifo, uint8_t, 16); + + // scheduler_add_periodical_event(leds, 20000l/SCHEDULER_UNIT); + /* ajoute la scrutation du clavier */ + // scheduler_add_periodical_event(kbd_manage, 100); + + /* envoie les caracteres du clavier vers le LCD */ + // kbd_register_event(menu_control); + + /* appele la fonction process a chaque reception de caractere */ + // uart0_register_rx_event(process); + + /* creation du device uart */ + fdevopen(uart0_dev_send,uart0_dev_recv); + + /* creation du device lcd */ + // lcd=fdevopen(lcd_dev_putc,kbd_dev_get_next); + + sei(); + + time_init(); + // menu_print(); + time_set(10,0); +/* printf_P(PSTR("\r\nWelcome to this demo\r\n")); */ +/* printf_P(PSTR("\r\n")); */ +/* printf_P(PSTR(" \r\n")); */ +/* printf_P(PSTR(" .__,. ___. \r\n")); */ +/* printf_P(PSTR(" _%i~` -'i;_ \r\n")); */ +/* printf_P(PSTR(" _=Xr~ '{a__ \r\n")); */ +/* printf_P(PSTR(" <ln2 :|2S=; \r\n")); */ +/* printf_P(PSTR(" _xnxn :=oox>. \r\n")); */ +/* printf_P(PSTR(" .nnvno ..______.. :=oonss \r\n")); */ +/* printf_P(PSTR(" .onvnn_. __s>ss%xixaii_,_ =Invv1n \r\n")); */ +/* printf_P(PSTR(" :vnnnnns_+''^~-` ---^^'(;sxvnnnn1 \r\n")); */ +/* printf_P(PSTR(" .__onvnvnxn_,. __svvvnnnnv_, \r\n")); */ +/* printf_P(PSTR(" _i%vnn2nvnnvnvn2n2nss;.;<aIvo2nxxnnvnx1nnnas_. \r\n")); */ +/* printf_P(PSTR(" i)nnvnnnnxnvnnnnvnnnn1(-=]SIvnnvnnvnnnnnnnnnnx>_ \r\n")); */ +/* printf_P(PSTR(" =innonn|=;::+<innnvvvvv .:o2vvo2oo===;==)vnvvn2:. \r\n")); */ +/* printf_P(PSTR(" _Jn!^~` <xs;. -^11oc+ **v}!-` i<a;. --'{lu( \r\n")); */ +/* printf_P(PSTR(" Xc| Ixoc| .: .: vvn(. nc| \r\n")); */ +/* printf_P(PSTR(" ..v; ~)n1x .)n21vvnoIl ._XuI' ~<i \r\n")); */ +/* printf_P(PSTR(" .i; =ix2v; =innnnnn=+ :)onv. =i \r\n")); */ +/* printf_P(PSTR(" i; -'o1v_,.=vnvnvxo+| =snxI~~ -+ \r\n")); */ +/* printf_P(PSTR(" +: -)ol=;)nnvvnnvvv:)n+; . \r\n")); */ +/* printf_P(PSTR(" .<xxnvnvv1nnn<, . \r\n")); */ +/* printf_P(PSTR(" ===. :iooonnnnno2ovvn1l |; \r\n")); */ +/* printf_P(PSTR(" --'=<__s_asxuonx1}|^`---'**nnnnnaii_s__/+^^ \r\n")); */ +/* printf_P(PSTR(" ==+==;=; .=;;::=.. \r\n")); */ +/* printf_P(PSTR("\r\n")); */ +/* printf_P(PSTR(" Microb Technology\r\n")); */ +/* printf_P(PSTR("\r\n")); */ +// printf("\r\n>> Time set to %d seconds\r\n",time_get_s()); + + while(1) + { + +/* wait_ms(1); */ +/* uart0_send(0x00); */ +/* wait_ms(1); */ +/* uart0_send(0x03); */ +/* wait_ms(1); */ +/* uart0_send(0xAA); */ +/* wait_ms(1); */ +/* uart0_send(0x55); */ +/* wait_ms(1); */ +/* uart0_send(0xFF); */ +/* wait_ms(1); */ +/* wait_ms(1); */ + printf("\r\n>> Time set to %d seconds\r\n",time_get_s()); + // menu_action(); + } + return 0; +} + + diff --git a/projects/kbd_uart_test/menu.txt b/projects/kbd_uart_test/menu.txt new file mode 100644 index 0000000..7af6a5e --- /dev/null +++ b/projects/kbd_uart_test/menu.txt @@ -0,0 +1,17 @@ +header="" + +menu=[ "Microb", + [ "Test1", + [ "Pouet", + [ "f1", "PORTB=0x01;" ], + [ "f6", "PORTB=0x02;" ], + [ "f2", "PORTB=0x03;" ] ], + [ "Pouet_f", "PORTB=0x04;" ] ], + + [ "Test2", + [ "Pouet3", + [ "f3", "PORTB=0x05;" ], + [ "f4", "PORTB=0x06;" ] ], + [ "Pouet_f2", "PORTB=0x07;" ] ] ] + +footer="" \ No newline at end of file diff --git a/projects/kbd_uart_test/scheduler_config.h b/projects/kbd_uart_test/scheduler_config.h new file mode 100644 index 0000000..7acac9c --- /dev/null +++ b/projects/kbd_uart_test/scheduler_config.h @@ -0,0 +1,9 @@ +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + + +#define SCHEDULER_NB_MAX_EVENT 5 +#define SCHEDULER_CLOCK_PRESCALER 8 +#define SCHEDULER_MCU_CLOCK 16000 // Khz + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/kbd_uart_test/time_config.h b/projects/kbd_uart_test/time_config.h new file mode 100644 index 0000000..9ac4aef --- /dev/null +++ b/projects/kbd_uart_test/time_config.h @@ -0,0 +1,2 @@ +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000 diff --git a/projects/kbd_uart_test/uart_config.h b/projects/kbd_uart_test/uart_config.h new file mode 100644 index 0000000..27fef8e --- /dev/null +++ b/projects/kbd_uart_test/uart_config.h @@ -0,0 +1,75 @@ +// Droids-corp 2004 - Zer0 +// config for uart module + +/* + * This is the configuration file for the uart module. + * This module provides : + * - Tx and Rx with fifo + * - two modes : the first one tries to be faster ; when you try to + * send data and the fifo is full, the byte is dropped. The second + * one (with UART1_DONT_LOOSE_DATA defined) can be slower ; when the + * fifo is full, the writing of a data blocks in the interrupt. + * - Speed selection (for the moment the module don't use the UBRRxH + * register so the speed cannot be too low. (min is 4800 at 16 Mhz) + * - Parity selection (if the uC support it) + * - 5 to 9 data bits (if the uC support it). Warning : when you use + * 9 bits, the prototypes of the functions change (uint8_t become uint16_t). + * - 1 or 2 stop bits (if the uC support it). + * - 2 UARTs (if the uC support it). + * + * + * + * Number of bits in frame for tx and rx are the same + * + * It doesn't support some USART capabilities : + * - Synchronous mode + * - Multiprocessor communication + */ + + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * Global configuration (config that is used for each uart) + */ +#define UART_MCU_QUARTZ 16000 + + + +/* + * UART0 definitions + */ +#define UART0_TX_ENABLED /* enable uart0 emission */ +#define UART0_RX_ENABLED /* enable uart0 reception */ + +/* this means that the function uart_sendchar will block if the fifo is full */ +#define UART0_DONT_LOOSE_DATA + +#define UART0_BAUDRATE 9600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 16 +#define UART0_TX_FIFO_SIZE 16 + +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT 1 +//#define UART0_STOP_BIT 2 + +#endif + diff --git a/projects/microb2009/CVS/Entries b/projects/microb2009/CVS/Entries new file mode 100644 index 0000000..a16cd1e --- /dev/null +++ b/projects/microb2009/CVS/Entries @@ -0,0 +1,7 @@ +D/bootloader//// +D/common//// +D/mainboard//// +D/mechboard//// +D/microb_cmd//// +D/sensorboard//// +D/tests//// diff --git a/projects/microb2009/CVS/Repository b/projects/microb2009/CVS/Repository new file mode 100644 index 0000000..1d91fcb --- /dev/null +++ b/projects/microb2009/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009 diff --git a/projects/microb2009/CVS/Root b/projects/microb2009/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/CVS/Template b/projects/microb2009/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/bootloader/.config b/projects/microb2009/bootloader/.config new file mode 100644 index 0000000..b70ba89 --- /dev/null +++ b/projects/microb2009/bootloader/.config @@ -0,0 +1,278 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_MCU_ATMEGA2560=y +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +# CONFIG_MATH_LIB is not set +# CONFIG_FDEVOPEN_COMPAT is not set +CONFIG_NO_PRINTF=y +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_GEOMETRY is not set +# CONFIG_MODULE_GEOMETRY_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_9BITS is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/projects/microb2009/bootloader/CVS/Entries b/projects/microb2009/bootloader/CVS/Entries new file mode 100644 index 0000000..ed81ba6 --- /dev/null +++ b/projects/microb2009/bootloader/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.3/Wed May 27 20:04:06 2009// +/Makefile/1.2/Wed May 27 20:04:06 2009// +/main.c/1.4/Wed May 27 20:04:06 2009// +/uart_config.h/1.3/Wed May 27 20:04:06 2009// +D diff --git a/projects/microb2009/bootloader/CVS/Repository b/projects/microb2009/bootloader/CVS/Repository new file mode 100644 index 0000000..f7c7782 --- /dev/null +++ b/projects/microb2009/bootloader/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/bootloader diff --git a/projects/microb2009/bootloader/CVS/Root b/projects/microb2009/bootloader/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/bootloader/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/bootloader/CVS/Template b/projects/microb2009/bootloader/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/bootloader/Makefile b/projects/microb2009/bootloader/Makefile new file mode 100755 index 0000000..04c078e --- /dev/null +++ b/projects/microb2009/bootloader/Makefile @@ -0,0 +1,41 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../.. +# VALUE, absolute or relative path : example ../.. # + +CFLAGS += -Werror + +# atm128 +# address is 0xf000 (in words) +# LDFLAGS += -Wl,--section-start=.text=1e000 +# UART_NUM = 0 + +# atm2560 +# address is 0x1f800 (in words) +LDFLAGS += -Wl,--section-start=.text=3f000 +UART_NUM = 1 + +CFLAGS += -DUART_NUM=$(UART_NUM) + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/bootloader/main.c b/projects/microb2009/bootloader/main.c new file mode 100755 index 0000000..8595d72 --- /dev/null +++ b/projects/microb2009/bootloader/main.c @@ -0,0 +1,361 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4 2009-05-27 20:04:06 zer0 Exp $ + * + */ + +/* + * A simple bootloader example. + */ + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/pgmspace.h> + +#include <stdlib.h> +#include <string.h> +#include <util/crc16.h> +#include <avr/boot.h> + +#define BRAKE_DDR() do { DDRJ |= 0xF0; } while(0) +#define BRAKE_ON() do { PORTJ |= 0xF0; } while(0) +#define BRAKE_OFF() do { PORTJ &= 0x0F; } while(0) + +#define LED1_ON() sbi(PORTJ, 2) +#define LED1_OFF() cbi(PORTJ, 2) + +#define LED2_ON() sbi(PORTJ, 3) +#define LED2_OFF() cbi(PORTJ, 3) + + +#define NOECHO + +#ifdef NOECHO +#define echo(c) do {} while(0) +#else +#define echo(c) uart_send(c) +#endif + +#if UART_NUM == 0 + +#define UCSRxA UCSR0A +#define UCSRxB UCSR0B +#define UCSRxC UCSR0C +#define RXCx RXC0 +#define UDRx UDR0 +#define UDREx UDRE0 +#define U2Xx U2X0 +#define RXENx RXEN0 +#define TXENx TXEN0 +#define UCSZx0 UCSZ00 +#define UCSZx1 UCSZ01 +#define UBRRx UBRR0 + +#elif UART_NUM == 1 + +#define UCSRxA UCSR1A +#define UCSRxB UCSR1B +#define UCSRxC UCSR1C +#define RXCx RXC1 +#define UDRx UDR1 +#define UDREx UDRE1 +#define U2Xx U2X1 +#define RXENx RXEN1 +#define TXENx TXEN1 +#define UCSZx0 UCSZ10 +#define UCSZx1 UCSZ11 +#define UBRRx UBRR1 + +#elif UART_NUM == 2 + +#define UCSRxA UCSR2A +#define UCSRxB UCSR2B +#define UCSRxC UCSR2C +#define RXCx RXC2 +#define UDRx UDR2 +#define UDREx UDRE2 +#define U2Xx U2X2 +#define RXENx RXEN2 +#define TXENx TXEN2 +#define UCSZx0 UCSZ20 +#define UCSZx1 UCSZ21 +#define UBRRx UBRR2 + +#elif UART_NUM == 3 + +#define UCSRxA UCSR3A +#define UCSRxB UCSR3B +#define UCSRxC UCSR3C +#define RXCx RXC3 +#define UDRx UDR3 +#define UDREx UDRE3 +#define U2Xx U2X3 +#define RXENx RXEN3 +#define TXENx TXEN3 +#define UCSZx0 UCSZ30 +#define UCSZx1 UCSZ31 +#define UBRRx UBRR3 + +#endif + + +static char uart_recv(void) +{ + while ( !(UCSRxA & (1<<RXCx)) ) ; + return UDRx; +} + +static void uart_send(char c) +{ + while ( !( UCSRxA & (1<<UDREx)) ) ; + UDRx = c; +} + +static void uart_puts(const char *buf) +{ + while (*buf) + uart_send(*(buf++)); +} + +static int8_t bootloader_query_hex(uint32_t *val) +{ + uint32_t tmp = 0; + int c; + + while (1) { + c = uart_recv(); + echo(c); + + if (c == '\n' || c == '\r') { + *val = tmp; + return 0; + } + else if (c >= '0' && c <= '9') { + tmp <<= 4; + tmp += (c - '0'); + } + else if (c >= 'a' && c <= 'f') { + tmp <<= 4; + tmp += (c - 'a' + 10); + } + else if (c >= 'A' && c <= 'F') { + tmp <<= 4; + tmp += (c - 'A' + 10); + } + else + return -1; + } + return 0; +} + +/* launch application */ +static void launch_app(void) +{ + uart_puts("Boot..."); + MCUCR = (1 << IVCE); + MCUCR = (0 << IVSEL); + reset(); +} + +static void disp_digit(uint8_t x) +{ + if (x < 10) + x += '0'; + else + x += 'a' - 10 ; + uart_send(x); +} + +static void disp_hex8(uint8_t x) +{ + disp_digit(x>>4); + disp_digit(x&0xf); +} + +static void disp_hex16(uint16_t x) +{ + disp_hex8(x>>8); + disp_hex8(x); +} + +static void crc_app(void) +{ + uint32_t start_addr, addr, size; + uint8_t c; + uint16_t crc = 0xffff; + uint16_t sum = 0; + + uart_puts("addr?\r\n"); + if (bootloader_query_hex(&start_addr)) + goto fail; + if (start_addr > FLASHEND) + goto fail; + uart_puts("size?\r\n"); + if (bootloader_query_hex(&size)) + goto fail; + if (start_addr + size > FLASHEND) + goto fail; + for (addr=start_addr; addr<start_addr+size; addr++) { +#if 0 + /* ignore the 2nd page, it contains microb infos */ + if (addr >= 256 && addr < 512) + continue; +#endif + c = pgm_read_byte_far(addr); + crc = _crc_ccitt_update(crc, c); + sum += c; + } + disp_hex16(crc); + disp_hex16(sum); + return; + fail: + uart_puts("KO"); +} + +static void read32(void) +{ + uint32_t start_addr, val = 0; + uint8_t c, i; + + uart_puts("addr?\r\n"); + if (bootloader_query_hex(&start_addr)) + goto fail; + if (start_addr > FLASHEND) + goto fail; + for (i=0; i<4; i++) { + c = pgm_read_byte_far(start_addr+i); + val <<= 8; + val |= c; + } + disp_hex16(val); + return; + fail: + uart_puts("KO"); +} + +static void prog_page(void) +{ + int c; + uint32_t addr; + uint16_t i; + uint16_t crc = 0xffff; + uint16_t sum = 0; + uint8_t buf[SPM_PAGESIZE]; + +#define SPM_PAGEMASK ((uint32_t)SPM_PAGESIZE-1) + uart_puts("addr?\r\n"); + if (bootloader_query_hex(&addr)) + goto fail; + if (addr > FLASHEND) + goto fail; + /* start_addr must be page aligned */ + if (addr & SPM_PAGEMASK) + goto fail; + + uart_puts("ok\r\n"); + + PORTJ = 0xF0; + + /* data is received like the .bin format (which is already in + * little endian) */ + for (i=0; i<SPM_PAGESIZE; i++) { + c = uart_recv(); + crc = _crc_ccitt_update(crc, c); + sum += c; + buf[i] = c; + } + disp_hex16(crc); + disp_hex16(sum); + uart_puts(" (y?)\r\n"); + c = uart_recv(); + if (c != 'y') + goto fail; + + /* erase page */ + eeprom_busy_wait(); + boot_page_erase(addr); + boot_spm_busy_wait(); + + /* Set up little-endian word and fill tmp buf. */ + for (i=0; i<SPM_PAGESIZE; i+=2) { + uint16_t w = buf[i] + ((uint16_t)(buf[i+1]) << 8); + boot_page_fill(addr + i, w); + } + + PORTJ = 0xFC; + + boot_page_write(addr); + boot_spm_busy_wait(); + + /* Reenable RWW-section again. We need this if we want to jump + * back to the application after bootloading. */ + boot_rww_enable(); + + uart_puts("OK"); + return; + fail: + uart_puts("KO"); +} + +int main(void) +{ + int c; + uint32_t i=0; + + /* disable all motors and switch on leds */ + DDRJ = 0xFC; + PORTJ = 0xFC; + + UCSRxA = _BV(U2Xx); + UCSRxB = _BV(RXENx) | _BV(TXENx); + UCSRxC = _BV(UCSZx1) | _BV(UCSZx0); /* 8 bits no parity 1 stop */ + UBRRx = 34; /* 57600 at 16 Mhz */ + + /* move interrupt vector in bootloader section */ + MCUCR = (1 << IVCE); + MCUCR = (1 << IVSEL); + + sei(); + + uart_puts("\r\ncmd> "); + + /* timeout */ + while ( !(UCSRxA & (1<<RXCx)) ) { + i++; + if (i>1000000) /* wait about 1 sec */ + launch_app(); + } + + while (1) { + uart_puts("\r\ncmd> "); + c = uart_recv(); + if (c == 'x') + launch_app(); + else if (c == 'c') + crc_app(); + else if (c == 'p') + prog_page(); + else if (c == 'd') + read32(); + else + uart_puts("p:prog_page c:crc x:exec d:dump32"); + } + + return 0; +} diff --git a/projects/microb2009/bootloader/uart_config.h b/projects/microb2009/bootloader/uart_config.h new file mode 100755 index 0000000..506806b --- /dev/null +++ b/projects/microb2009/bootloader/uart_config.h @@ -0,0 +1,120 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.3 2009-05-27 20:04:06 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +#if UART_NUM == 0 + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +#define UART0_USE_DOUBLE_SPEED 0 + +#define UART0_RX_FIFO_SIZE 64 +#define UART0_TX_FIFO_SIZE 16 + +#define UART0_NBITS 8 +#define UART0_PARITY UART_PARTITY_NONE +#define UART0_STOP_BIT UART_STOP_BITS_1 + +#elif UART_NUM == 1 + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +#define UART1_USE_DOUBLE_SPEED 0 + +#define UART1_RX_FIFO_SIZE 32 +#define UART1_TX_FIFO_SIZE 4 + +#define UART1_NBITS 8 +#define UART1_PARITY UART_PARTITY_NONE +#define UART1_STOP_BIT UART_STOP_BITS_1 + +#elif UART_NUM == 2 + +/* compile uart2 fonctions, undefine it to pass compilation */ +#define UART2_COMPILE + +/* enable uart2 if == 1, disable if == 0 */ +#define UART2_ENABLED 1 + +/* enable uart2 interrupts if == 1, disable if == 0 */ +#define UART2_INTERRUPT_ENABLED 1 + +#define UART2_BAUDRATE 57600 + +#define UART2_USE_DOUBLE_SPEED 0 + +#define UART2_RX_FIFO_SIZE 32 +#define UART2_TX_FIFO_SIZE 4 + +#define UART2_NBITS 8 +#define UART2_PARITY UART_PARTITY_NONE +#define UART2_STOP_BIT UART_STOP_BITS_1 + +#elif UART_NUM == 3 + +/* compile uart3 fonctions, undefine it to pass compilation */ +#define UART3_COMPILE + +/* enable uart3 if == 1, disable if == 0 */ +#define UART3_ENABLED 1 + +/* enable uart3 interrupts if == 1, disable if == 0 */ +#define UART3_INTERRUPT_ENABLED 1 + +#define UART3_BAUDRATE 57600 + +#define UART3_USE_DOUBLE_SPEED 0 + +#define UART3_RX_FIFO_SIZE 32 +#define UART3_TX_FIFO_SIZE 4 + +#define UART3_NBITS 8 +#define UART3_PARITY UART_PARTITY_NONE +#define UART3_STOP_BIT UART_STOP_BITS_1 + +#endif /* uart num */ + +#endif + diff --git a/projects/microb2009/common/CVS/Entries b/projects/microb2009/common/CVS/Entries new file mode 100644 index 0000000..822abc7 --- /dev/null +++ b/projects/microb2009/common/CVS/Entries @@ -0,0 +1,4 @@ +/avr6.x/1.1/Fri Apr 24 19:30:41 2009// +/eeprom_mapping.h/1.2/Wed May 27 20:04:06 2009// +/i2c_commands.h/1.9/Wed May 27 20:04:06 2009// +D diff --git a/projects/microb2009/common/CVS/Repository b/projects/microb2009/common/CVS/Repository new file mode 100644 index 0000000..938b9ee --- /dev/null +++ b/projects/microb2009/common/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/common diff --git a/projects/microb2009/common/CVS/Root b/projects/microb2009/common/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/common/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/common/CVS/Template b/projects/microb2009/common/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/common/avr6.x b/projects/microb2009/common/avr6.x new file mode 100644 index 0000000..a758e96 --- /dev/null +++ b/projects/microb2009/common/avr6.x @@ -0,0 +1,269 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-avr","elf32-avr","elf32-avr") +OUTPUT_ARCH(avr:6) +MEMORY +{ + text (rx) : ORIGIN = 0, LENGTH = 1024K + data (rw!x) : ORIGIN = 0x800200, LENGTH = 0xfe00 + eeprom (rw!x) : ORIGIN = 0x810000, LENGTH = 64K + fuse (rw!x) : ORIGIN = 0x820000, LENGTH = 1K + lock (rw!x) : ORIGIN = 0x830000, LENGTH = 1K + signature (rw!x) : ORIGIN = 0x840000, LENGTH = 1K +} +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + /* Internal text space or external memory. */ + .text : + { + *(.vectors) + KEEP(*(.vectors)) + . = 256 + ALIGN(256); /* placeholder for misc microb infos */ + /* For data that needs to reside in the lower 64k of progmem. */ + *(.progmem.gcc*) + *(.progmem*) + . = ALIGN(2048); + __trampolines_start = . ; + /* The jump trampolines for the 16-bit limited relocs will reside here. */ + *(.trampolines) + *(.trampolines*) + __trampolines_end = . ; + /* For future tablejump instruction arrays for 3 byte pc devices. + We don't relax jump/call instructions within these sections. */ + *(.jumptables) + *(.jumptables*) + /* For code that needs to reside in the lower 128k progmem. */ + *(.lowtext) + *(.lowtext*) + __ctors_start = . ; + *(.ctors) + __ctors_end = . ; + __dtors_start = . ; + *(.dtors) + __dtors_end = . ; + KEEP(SORT(*)(.ctors)) + KEEP(SORT(*)(.dtors)) + /* From this point on, we don't bother about wether the insns are + below or above the 16 bits boundary. */ + *(.init0) /* Start here after reset. */ + KEEP (*(.init0)) + *(.init1) + KEEP (*(.init1)) + *(.init2) /* Clear __zero_reg__, set up stack pointer. */ + KEEP (*(.init2)) + *(.init3) + KEEP (*(.init3)) + *(.init4) /* Initialize data and BSS. */ + KEEP (*(.init4)) + *(.init5) + KEEP (*(.init5)) + *(.init6) /* C++ constructors. */ + KEEP (*(.init6)) + *(.init7) + KEEP (*(.init7)) + *(.init8) + KEEP (*(.init8)) + *(.init9) /* Call main(). */ + KEEP (*(.init9)) + *(.text.*) /* trucs de gcc ? */ + . = ALIGN(2048); + uart*(.text) + pwm*(.text) + parse*(.text) + rdline*(.text) + vt100*(.text) + scheduler*(.text) + control_system*(.text) + pid*(.text) + f08*(.text) + f16*(.text) + f32*(.text) + f64*(.text) + vect2*(.text) + quadramp*(.text) + blocking*(.text) + obstacle*(.text) + trajectory*(.text) + position*(.text) + adc*(.text) + robot*(.text) + error*(.text) + encoders*(.text) + time*(.text) + cirbuf*(.text) + i2c*(.text) + spi*(.text) + ax12*(.text) + . = ALIGN(2048); + /* some libc stuff */ + str*(.text) + mem*(.text) + printf*(.text) + vfprintf*(.text) + sprintf*(.text) + snprintf*(.text) + malloc*(.text) + free*(.text) + fdevopen*(.text) + fputc*(.text) + . = ALIGN(2048); + *(.text) + . = ALIGN(2); + *(.fini9) /* _exit() starts here. */ + KEEP (*(.fini9)) + *(.fini8) + KEEP (*(.fini8)) + *(.fini7) + KEEP (*(.fini7)) + *(.fini6) /* C++ destructors. */ + KEEP (*(.fini6)) + *(.fini5) + KEEP (*(.fini5)) + *(.fini4) + KEEP (*(.fini4)) + *(.fini3) + KEEP (*(.fini3)) + *(.fini2) + KEEP (*(.fini2)) + *(.fini1) + KEEP (*(.fini1)) + *(.fini0) /* Infinite loop after program termination. */ + KEEP (*(.fini0)) + _etext = . ; + } > text + .data : AT (ADDR (.text) + SIZEOF (.text)) + { + PROVIDE (__data_start = .) ; + *(.data) + *(.data*) + *(.rodata) /* We need to include .rodata here if gcc is used */ + *(.rodata*) /* with -fdata-sections. */ + *(.gnu.linkonce.d*) + . = ALIGN(2); + _edata = . ; + PROVIDE (__data_end = .) ; + } > data + .bss SIZEOF(.data) + ADDR(.data) : + { + PROVIDE (__bss_start = .) ; + *(.bss) + *(.bss*) + *(COMMON) + PROVIDE (__bss_end = .) ; + } > data + __data_load_start = LOADADDR(.data); + __data_load_end = __data_load_start + SIZEOF(.data); + /* Global data not cleared after reset. */ + .noinit SIZEOF(.bss) + ADDR(.bss) : + { + PROVIDE (__noinit_start = .) ; + *(.noinit*) + PROVIDE (__noinit_end = .) ; + _end = . ; + PROVIDE (__heap_start = .) ; + } > data + .eeprom : + { + *(.eeprom*) + __eeprom_end = . ; + } > eeprom + .fuse : + { + KEEP(*(.fuse)) + KEEP(*(.lfuse)) + KEEP(*(.hfuse)) + KEEP(*(.efuse)) + } > fuse + .lock : + { + KEEP(*(.lock*)) + } > lock + .signature : + { + KEEP(*(.signature*)) + } > signature + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } +} diff --git a/projects/microb2009/common/eeprom_mapping.h b/projects/microb2009/common/eeprom_mapping.h new file mode 100644 index 0000000..01bd6e3 --- /dev/null +++ b/projects/microb2009/common/eeprom_mapping.h @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: eeprom_mapping.h,v 1.2 2009-05-27 20:04:06 zer0 Exp $ + * + */ + +#ifndef _EEPROM_MAPPING_H_ +#define _EEPROM_MAPPING_H_ + +#define EEPROM_MAGIC_MAINBOARD 1 +#define EEPROM_MAGIC_MECHBOARD 2 +#define EEPROM_MAGIC_SENSORBOARD 3 + +#define EEPROM_MAGIC_ADDRESS ((uint8_t *)0x100) + +#define EEPROM_TIME_ADDRESS ((uint16_t *)0x110) + +#endif diff --git a/projects/microb2009/common/i2c_commands.h b/projects/microb2009/common/i2c_commands.h new file mode 100644 index 0000000..d3072bc --- /dev/null +++ b/projects/microb2009/common/i2c_commands.h @@ -0,0 +1,291 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_commands.h,v 1.9 2009-05-27 20:04:06 zer0 Exp $ + * + */ + +#ifndef _I2C_COMMANDS_H_ +#define _I2C_COMMANDS_H_ + +#define I2C_MAINBOARD_ADDR 1 +#define I2C_MECHBOARD_ADDR 2 +#define I2C_SENSORBOARD_ADDR 3 + +#define I2C_LEFT_SIDE 0 +#define I2C_RIGHT_SIDE 1 +#define I2C_AUTO_SIDE 2 /* for prepare_pickup */ +#define I2C_CENTER_SIDE 3 /* for prepare_pickup */ + +#define I2C_COLOR_RED 0 +#define I2C_COLOR_GREEN 1 + +#define I2C_AUTOBUILD_DEFAULT_DIST 210 + +struct i2c_cmd_hdr { + uint8_t cmd; +}; + +/****/ +/* commands that do not need and answer */ +/****/ + +#define I2C_CMD_GENERIC_LED_CONTROL 0x00 + +struct i2c_cmd_led_control { + struct i2c_cmd_hdr hdr; + uint8_t led_num:7; + uint8_t state:1; +}; + +/****/ + +#define I2C_CMD_GENERIC_SET_COLOR 0x01 + +struct i2c_cmd_generic_color { + struct i2c_cmd_hdr hdr; + uint8_t color; +}; + +/****/ + +#define I2C_CMD_MECHBOARD_SET_MODE 0x02 + +struct i2c_cmd_mechboard_set_mode { + struct i2c_cmd_hdr hdr; +#define I2C_MECHBOARD_MODE_MANUAL 0x00 +#define I2C_MECHBOARD_MODE_HARVEST 0x01 +#define I2C_MECHBOARD_MODE_PREPARE_PICKUP 0x02 +#define I2C_MECHBOARD_MODE_PICKUP 0x03 +#define I2C_MECHBOARD_MODE_PREPARE_BUILD 0x04 +#define I2C_MECHBOARD_MODE_AUTOBUILD 0x05 +#define I2C_MECHBOARD_MODE_WAIT 0x06 +#define I2C_MECHBOARD_MODE_INIT 0x07 +#define I2C_MECHBOARD_MODE_PREPARE_GET_LINTEL 0x08 +#define I2C_MECHBOARD_MODE_GET_LINTEL 0x09 +#define I2C_MECHBOARD_MODE_PUT_LINTEL 0x0A +#define I2C_MECHBOARD_MODE_PREPARE_EJECT 0x0B +#define I2C_MECHBOARD_MODE_EJECT 0x0C +#define I2C_MECHBOARD_MODE_CLEAR 0x0D +#define I2C_MECHBOARD_MODE_LAZY_HARVEST 0x0E +#define I2C_MECHBOARD_MODE_LOADED 0x0F +#define I2C_MECHBOARD_MODE_PREPARE_INSIDE 0x10 +#define I2C_MECHBOARD_MODE_STORE 0x11 +#define I2C_MECHBOARD_MODE_LAZY_PICKUP 0x12 +#define I2C_MECHBOARD_MODE_MANIVELLE 0x13 +#define I2C_MECHBOARD_MODE_PUSH_TEMPLE 0x14 +#define I2C_MECHBOARD_MODE_PUSH_TEMPLE_DISC 0x15 +#define I2C_MECHBOARD_MODE_EXIT 0xFF + uint8_t mode; + union { + struct { + + } manual; + + struct { + uint8_t side; + uint8_t next_mode; + } prep_pickup; + + struct { + uint8_t level_l; + uint8_t level_r; + } prep_build; + + struct { + uint8_t side; + } push_temple_disc; + + struct { + uint8_t level_left; + uint8_t level_right; + uint8_t count_left; + uint8_t count_right; + uint8_t distance_left; + uint8_t distance_right; + uint8_t do_lintel; + } autobuild; + + struct { + uint8_t level_l; + uint8_t level_r; + } prep_inside; + }; +}; + +/****/ + +/* only valid in manual mode */ +#define I2C_CMD_MECHBOARD_ARM_GOTO 0x03 + +struct i2c_cmd_mechboard_arm_goto { + struct i2c_cmd_hdr hdr; +#define I2C_MECHBOARD_ARM_LEFT 0 +#define I2C_MECHBOARD_ARM_RIGHT 1 +#define I2C_MECHBOARD_ARM_BOTH 2 + uint8_t which; + + uint8_t height; /* in cm */ + uint8_t distance; /* in cm */ +}; + +/****/ + +#define I2C_CMD_SENSORBOARD_SET_BEACON 0x04 + +struct i2c_cmd_sensorboard_start_beacon { + struct i2c_cmd_hdr hdr; + uint8_t enable; +}; + + +/****/ + +#define I2C_CMD_SENSORBOARD_SET_SCANNER 0x05 + +struct i2c_cmd_sensorboard_scanner { + struct i2c_cmd_hdr hdr; + +#define I2C_SENSORBOARD_SCANNER_STOP 0x00 +#define I2C_SENSORBOARD_SCANNER_PREPARE 0x01 +#define I2C_SENSORBOARD_SCANNER_START 0x02 + uint8_t mode; +}; + +/*****/ + +#define I2C_CMD_SENSORBOARD_CALIB_SCANNER 0x06 +struct i2c_cmd_sensorboard_calib_scanner { + struct i2c_cmd_hdr hdr; +}; + +/*****/ + +#define I2C_CMD_SENSORBOARD_SCANNER_ALGO 0x07 +struct i2c_cmd_sensorboard_scanner_algo { + struct i2c_cmd_hdr hdr; + +#define I2C_SCANNER_ALGO_COLUMN_DROPZONE 1 +#define I2C_SCANNER_ALGO_CHECK_TEMPLE 2 +#define I2C_SCANNER_ALGO_TEMPLE_DROPZONE 3 + uint8_t algo; + + union { + struct { +#define I2C_SCANNER_ZONE_0 0 +#define I2C_SCANNER_ZONE_1 1 +#define I2C_SCANNER_ZONE_DISC 2 + uint8_t working_zone; + int16_t center_x; + int16_t center_y; + } drop_zone; + + struct { + uint8_t level; + int16_t temple_x; + int16_t temple_y; + } check_temple; + }; +}; + +/****/ +/* requests and their answers */ +/****/ + + +#define I2C_REQ_MECHBOARD_STATUS 0x80 + +struct i2c_req_mechboard_status { + struct i2c_cmd_hdr hdr; + + int16_t pump_left1_current; + int16_t pump_left2_current; +}; + +#define I2C_ANS_MECHBOARD_STATUS 0x81 + +struct i2c_ans_mechboard_status { + struct i2c_cmd_hdr hdr; + /* mode type are defined above: I2C_MECHBOARD_MODE_xxx */ + uint8_t mode; + +#define I2C_MECHBOARD_STATUS_F_READY 0x00 +#define I2C_MECHBOARD_STATUS_F_BUSY 0x01 +#define I2C_MECHBOARD_STATUS_F_EXCPT 0x02 + uint8_t status; + + uint8_t lintel_count; + + /* flag is there if column was taken by this pump. Note that + * we should also check ADC (current) to see if the column is + * still there. */ +#define I2C_MECHBOARD_COLUMN_L1 0x01 +#define I2C_MECHBOARD_COLUMN_L2 0x02 +#define I2C_MECHBOARD_COLUMN_R1 0x04 +#define I2C_MECHBOARD_COLUMN_R2 0x08 + uint8_t column_flags; + + int16_t pump_left1; + int16_t pump_right1; + int16_t pump_left2; + int16_t pump_right2; + +#define I2C_MECHBOARD_CURRENT_COLUMN 85 + int16_t pump_right1_current; + int16_t pump_right2_current; + + uint16_t servo_lintel_left; + uint16_t servo_lintel_right; +}; + +#define I2C_REQ_SENSORBOARD_STATUS 0x82 + +struct i2c_req_sensorboard_status { + struct i2c_cmd_hdr hdr; + + /* position sent by mainboard */ + int16_t x; + int16_t y; + int16_t a; + + /* PWM for pickup */ + uint8_t enable_pickup_wheels; +}; + +#define I2C_ANS_SENSORBOARD_STATUS 0x83 + +struct i2c_ans_sensorboard_status { + struct i2c_cmd_hdr hdr; + + uint8_t status; +#define I2C_OPPONENT_NOT_THERE -1000 + int16_t opponent_x; + int16_t opponent_y; + int16_t opponent_a; + int16_t opponent_d; + +#define I2C_SCAN_DONE 1 +#define I2C_SCAN_MAX_COLUMN 2 + uint8_t scan_status; + +#define I2C_COLUMN_NO_DROPZONE -1 + int8_t dropzone_h; + int16_t dropzone_x; + int16_t dropzone_y; +}; + +#endif /* _I2C_PROTOCOL_H_ */ diff --git a/projects/microb2009/mainboard/.config b/projects/microb2009/mainboard/.config new file mode 100644 index 0000000..860d979 --- /dev/null +++ b/projects/microb2009/mainboard/.config @@ -0,0 +1,251 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_MCU_ATMEGA2560=y +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_ADVANCED_PRINTF=y +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +CONFIG_MODULE_FIXED_POINT=y +CONFIG_MODULE_VECT2=y +CONFIG_MODULE_GEOMETRY=y +CONFIG_MODULE_SCHEDULER=y +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +CONFIG_MODULE_TIME=y +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +CONFIG_MODULE_I2C=y +CONFIG_MODULE_I2C_MASTER=y +# CONFIG_MODULE_I2C_MULTIMASTER is not set +CONFIG_MODULE_I2C_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +CONFIG_MODULE_PWM_NG=y +CONFIG_MODULE_ADC=y +CONFIG_MODULE_ADC_CREATE_CONFIG=y + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +CONFIG_MODULE_AX12=y +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +CONFIG_MODULE_ENCODERS_SPI=y +CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG=y + +# +# Robot specific modules +# +CONFIG_MODULE_ROBOT_SYSTEM=y +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +CONFIG_MODULE_POSITION_MANAGER=y +CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE=y +CONFIG_MODULE_TRAJECTORY_MANAGER=y +CONFIG_MODULE_BLOCKING_DETECTION_MANAGER=y +CONFIG_MODULE_OBSTACLE_AVOIDANCE=y +CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG=y + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y +CONFIG_MODULE_PID=y +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +CONFIG_MODULE_DIAGNOSTIC=y +CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG=y +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/projects/microb2009/mainboard/CVS/Entries b/projects/microb2009/mainboard/CVS/Entries new file mode 100644 index 0000000..4b47b82 --- /dev/null +++ b/projects/microb2009/mainboard/CVS/Entries @@ -0,0 +1,51 @@ +/.config/1.5/Wed May 27 20:04:06 2009// +/Makefile/1.6/Wed May 27 20:04:06 2009// +/actuator.c/1.3/Sat May 2 10:08:09 2009// +/actuator.h/1.2/Fri Apr 24 19:30:41 2009// +/adc_config.h/1.1/Fri Feb 20 21:10:01 2009// +/ax12_config.h/1.1/Fri Feb 20 21:10:01 2009// +/ax12_user.c/1.3/Sat May 2 10:08:09 2009// +/ax12_user.h/1.2/Tue Apr 7 20:03:48 2009// +/beacon_test.png/1.1/Sun Nov 8 17:36:07 2009// +/cmdline.c/1.7/Sun Nov 8 17:24:33 2009// +/cmdline.h/1.4/Sun Nov 8 17:24:33 2009// +/commands.c/1.9/Sun Nov 8 17:24:33 2009// +/commands_ax12.c/1.3/Sat May 2 10:08:09 2009// +/commands_cs.c/1.4/Sat May 2 10:08:09 2009// +/commands_gen.c/1.8/Sun Nov 8 17:24:33 2009// +/commands_mainboard.c/1.9/Sun Nov 8 17:24:33 2009// +/commands_traj.c/1.8/Sun Nov 8 17:24:33 2009// +/cs.c/1.9/Sun Nov 8 17:24:33 2009// +/cs.h/1.3/Sun Mar 29 18:42:41 2009// +/diagnostic_config.h/1.1/Fri Feb 27 22:23:37 2009// +/encoders_spi_config.h/1.1/Fri Feb 20 21:10:01 2009// +/error_config.h/1.1/Fri Feb 27 22:23:37 2009// +/i2c_config.h/1.2/Thu Mar 5 23:01:32 2009// +/i2c_protocol.c/1.8/Sun Nov 8 17:24:33 2009// +/i2c_protocol.h/1.6/Sun Nov 8 17:24:33 2009// +/main.c/1.10/Sun Nov 8 17:24:33 2009// +/main.h/1.10/Sun Nov 8 17:24:33 2009// +/obstacle_avoidance_config.h/1.5/Sun Nov 8 17:24:33 2009// +/pid_config.h/1.1/Fri Feb 20 21:10:01 2009// +/rdline_config.h/1.1/Fri Feb 20 21:10:01 2009// +/scheduler_config.h/1.2/Sun Mar 15 20:18:33 2009// +/sensor.c/1.8/Sun Nov 8 17:24:33 2009// +/sensor.h/1.6/Sun Nov 8 17:24:33 2009// +/spi_config.h/1.1/Fri Feb 20 21:10:01 2009// +/strat.c/1.6/Sun Nov 8 17:24:33 2009// +/strat.h/1.7/Sun Nov 8 17:24:33 2009// +/strat_avoid.c/1.5/Sun Nov 8 17:24:33 2009// +/strat_avoid.h/1.5/Sun Nov 8 17:24:33 2009// +/strat_base.c/1.8/Sun Nov 8 17:24:33 2009// +/strat_base.h/1.5/Sun Nov 8 17:24:33 2009// +/strat_building.c/1.5/Sun Nov 8 17:24:33 2009// +/strat_column_disp.c/1.5/Sun Nov 8 17:24:33 2009// +/strat_lintel.c/1.5/Sun Nov 8 17:24:33 2009// +/strat_scan.c/1.2/Sun Nov 8 17:24:33 2009// +/strat_static_columns.c/1.5/Sun Nov 8 17:24:33 2009// +/strat_utils.c/1.7/Sun Nov 8 17:24:33 2009// +/strat_utils.h/1.5/Sun Nov 8 17:24:33 2009// +/time_config.h/1.1/Fri Feb 20 21:10:01 2009// +/timer_config.h/1.1/Fri Feb 20 21:10:01 2009// +/uart_config.h/1.5/Sun Nov 8 17:24:33 2009// +D diff --git a/projects/microb2009/mainboard/CVS/Repository b/projects/microb2009/mainboard/CVS/Repository new file mode 100644 index 0000000..aaf34e4 --- /dev/null +++ b/projects/microb2009/mainboard/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/mainboard diff --git a/projects/microb2009/mainboard/CVS/Root b/projects/microb2009/mainboard/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/mainboard/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/mainboard/CVS/Template b/projects/microb2009/mainboard/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/mainboard/Makefile b/projects/microb2009/mainboard/Makefile new file mode 100755 index 0000000..1a53746 --- /dev/null +++ b/projects/microb2009/mainboard/Makefile @@ -0,0 +1,29 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../.. + +SRC = $(TARGET).c cmdline.c commands_ax12.c commands_gen.c +SRC += commands_cs.c commands_mainboard.c commands_traj.c commands.c +SRC += i2c_protocol.c sensor.c actuator.c cs.c ax12_user.c +SRC += strat_utils.c strat_base.c strat_avoid.c strat.c +SRC += strat_static_columns.c strat_lintel.c +SRC += strat_column_disp.c strat_building.c strat_scan.c + +ASRC = + +CFLAGS += -Wall -Werror +#CFLAGS += -DHOMOLOGATION +LDFLAGS = -T ../common/avr6.x + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +AVRDUDE_DELAY=50 + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/mainboard/actuator.c b/projects/microb2009/mainboard/actuator.c new file mode 100644 index 0000000..19d2fc7 --- /dev/null +++ b/projects/microb2009/mainboard/actuator.c @@ -0,0 +1,77 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: actuator.c,v 1.3 2009-05-02 10:08:09 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> + +#include "main.h" + +void pwm_set_and_save(void *pwm, int32_t val) +{ + /* we need to do the saturation here, before saving the + * value */ + if (val > 4095) + val = 4095; + if (val < -4095) + val = -4095; + + if (pwm == LEFT_PWM) + mainboard.pwm_l = val; + else if (pwm == RIGHT_PWM) + mainboard.pwm_r = val; + pwm_ng_set(pwm, val); +} + +void pickup_wheels_on(void) +{ + mainboard.enable_pickup_wheels = 1; +} + +void pickup_wheels_off(void) +{ + mainboard.enable_pickup_wheels = 0; +} + diff --git a/projects/microb2009/mainboard/actuator.h b/projects/microb2009/mainboard/actuator.h new file mode 100644 index 0000000..9c7174a --- /dev/null +++ b/projects/microb2009/mainboard/actuator.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: actuator.h,v 1.2 2009-04-24 19:30:41 zer0 Exp $ + * + */ + +void pwm_set_and_save(void *pwm, int32_t val); +void pickup_wheels_on(void); +void pickup_wheels_off(void); + diff --git a/projects/microb2009/mainboard/adc_config.h b/projects/microb2009/mainboard/adc_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/mainboard/ax12_config.h b/projects/microb2009/mainboard/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/projects/microb2009/mainboard/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/projects/microb2009/mainboard/ax12_user.c b/projects/microb2009/mainboard/ax12_user.c new file mode 100644 index 0000000..575f5bc --- /dev/null +++ b/projects/microb2009/mainboard/ax12_user.c @@ -0,0 +1,176 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12_user.c,v 1.3 2009-05-02 10:08:09 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/list.h> +#include <aversive/error.h> + +#include <i2c.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" + +/* + * Cmdline interface for AX12. Use the PC to command a daisy-chain of + * AX12 actuators with a nice command line interface. + * + * The circuit should be as following: + * + * |----------| + * | uart3|------->--- PC (baudrate=57600) + * | |-------<--- + * | atmega128| + * | | + * | uart0|---->---+-- AX12 (baudrate 115200) + * | |----<---| + * |----------| + * + * Note that RX and TX pins of UART1 are connected together to provide + * a half-duplex UART emulation. + * + */ + +#define UART_AX12_NUM 0 +#define UCSRxB UCSR0B +#define AX12_TIMEOUT 5000UL /* in us */ + +/********************************* AX12 commands */ + +/* + * We use synchronous access (not interrupt driven) to the hardware + * UART, because we have to be sure that the transmission/reception is + * really finished when we return from the functions. + * + * We don't use the CM-5 circuit as described in the AX12 + * documentation, we simply connect TX and RX and use TXEN + RXEN + + * DDR to manage the port directions. + */ + +static volatile uint8_t ax12_state = AX12_STATE_READ; +extern volatile struct cirbuf g_tx_fifo[]; /* uart fifo */ +static volatile uint8_t ax12_nsent = 0; + +/* Called by ax12 module to send a character on serial line. Count the + * number of transmitted bytes. It will be used in ax12_recv_char() to + * drop the bytes that we transmitted. */ +static int8_t ax12_send_char(uint8_t c) +{ + uart_send(UART_AX12_NUM, c); + ax12_nsent++; + return 0; +} + +/* for atmega256 */ +#ifndef TXEN +#define TXEN TXEN0 +#endif + +/* called by uart module when the character has been written in + * UDR. It does not mean that the byte is physically transmitted. */ +static void ax12_send_callback(char c) +{ + if (ax12_state == AX12_STATE_READ) { + /* disable TX when last byte is pushed. */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[UART_AX12_NUM])) + UCSRxB &= ~(1<<TXEN); + } +} + +/* Called by ax12 module when we want to receive a char. Note that we + * also receive the bytes we sent ! So we need to drop them. */ +static int16_t ax12_recv_char(void) +{ + microseconds t = time_get_us2(); + int c; + while (1) { + c = uart_recv_nowait(UART_AX12_NUM); + if (c != -1) { + if (ax12_nsent == 0) + return c; + ax12_nsent --; + } + + /* 5 ms timeout */ + if ((time_get_us2() - t) > AX12_TIMEOUT) + return -1; + } + return c; +} + +/* called by ax12 module when we want to switch serial line. As we + * work in interruption mode, this function can be called to switch + * back in read mode even if the bytes are not really transmitted on + * the line. That's why in this case we do nothing, we will fall back + * in read mode in any case when xmit is finished -- see in + * ax12_send_callback() -- */ +static void ax12_switch_uart(uint8_t state) +{ + uint8_t flags; + + if (state == AX12_STATE_WRITE) { + IRQ_LOCK(flags); + ax12_nsent=0; + while (uart_recv_nowait(UART_AX12_NUM) != -1); + UCSRxB |= (1<<TXEN); + ax12_state = AX12_STATE_WRITE; + IRQ_UNLOCK(flags); + } + else { + IRQ_LOCK(flags); + if (CIRBUF_IS_EMPTY(&g_tx_fifo[UART_AX12_NUM])) + UCSRxB &= ~(1<<TXEN); + ax12_state = AX12_STATE_READ; + IRQ_UNLOCK(flags); + } +} + + +void ax12_user_init(void) +{ + /* AX12 */ + AX12_init(&gen.ax12); + AX12_set_hardware_send(&gen.ax12, ax12_send_char); + AX12_set_hardware_recv(&gen.ax12, ax12_recv_char); + AX12_set_hardware_switch(&gen.ax12, ax12_switch_uart); + uart_register_tx_event(UART_AX12_NUM, ax12_send_callback); +} diff --git a/projects/microb2009/mainboard/ax12_user.h b/projects/microb2009/mainboard/ax12_user.h new file mode 100644 index 0000000..4091709 --- /dev/null +++ b/projects/microb2009/mainboard/ax12_user.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12_user.h,v 1.2 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +/* This is the ax12 user interface. It initializes the aversive AX12 + * module so that it works in background, using interrupt driver uart. + * + * Be carreful, a call to AX12 module is synchronous and uses + * interruptions, so interrupts must be enabled. On the other side, a + * call _must not_ interrupt another one. That's why all calls to the + * module are done either in init() functions or in a scheduler event + * with prio=ARM_PRIO. + */ + +/* XXX do a safe_ax12() function that will retry once or twice if we + * see some problems. */ + +void ax12_user_init(void); diff --git a/projects/microb2009/mainboard/beacon_test.png b/projects/microb2009/mainboard/beacon_test.png new file mode 100644 index 0000000..c669f2e Binary files /dev/null and b/projects/microb2009/mainboard/beacon_test.png differ diff --git a/projects/microb2009/mainboard/cmdline.c b/projects/microb2009/mainboard/cmdline.c new file mode 100644 index 0000000..7c3ec9e --- /dev/null +++ b/projects/microb2009/mainboard/cmdline.c @@ -0,0 +1,172 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cmdline.c,v 1.7 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <parse.h> +#include <rdline.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include "main.h" +#include "cmdline.h" +#include "strat_base.h" + + +/******** See in commands.c for the list of commands. */ +extern parse_pgm_ctx_t main_ctx[]; + +static void write_char(char c) +{ + uart_send(CMDLINE_UART, c); +} + +static void +valid_buffer(const char *buf, uint8_t size) +{ + int8_t ret; + + /* reset CTRL-C for trajectory interruption each time we + * receive a new command */ + interrupt_traj_reset(); + + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char *buf, char *dstbuf, uint8_t dstsize, + int16_t *state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + + +/* sending "pop" on cmdline uart resets the robot */ +void emergency(char c) +{ + static uint8_t i = 0; + + /* interrupt traj here */ + if (c == '\003') + interrupt_traj(); + + if ((i == 0 && c == 'p') || + (i == 1 && c == 'o') || + (i == 2 && c == 'p')) + i++; + else if ( !(i == 1 && c == 'p') ) + i = 0; + if (i == 3) + reset(); +} + +/* log function, add a command to configure + * it dynamically */ +void mylog(struct error * e, ...) +{ + va_list ap; + u16 stream_flags = stdout->flags; + uint8_t i; + time_h tv; + + if (e->severity > ERROR_SEVERITY_ERROR) { + if (gen.log_level < e->severity) + return; + + for (i=0; i<NB_LOGS+1; i++) + if (gen.logs[i] == e->err_num) + break; + if (i == NB_LOGS+1) + return; + } + + va_start(ap, e); + tv = time_get_time(); + printf_P(PSTR("%ld.%.3ld: "), tv.s, (tv.us/1000UL)); + + printf_P(PSTR("(%d,%d,%d) "), + position_get_x_s16(&mainboard.pos), + position_get_y_s16(&mainboard.pos), + position_get_a_deg_s16(&mainboard.pos)); + + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR("\r\n")); + va_end(ap); + stdout->flags = stream_flags; +} + +int cmdline_interact(void) +{ + const char *history, *buffer; + int8_t ret, same = 0; + int16_t c; + + rdline_init(&gen.rdl, write_char, valid_buffer, complete_buffer); + snprintf(gen.prompt, sizeof(gen.prompt), "mainboard > "); + rdline_newline(&gen.rdl, gen.prompt); + + while (1) { + c = uart_recv_nowait(CMDLINE_UART); + if (c == -1) + continue; + ret = rdline_char_in(&gen.rdl, c); + if (ret != 2 && ret != 0) { + buffer = rdline_get_buffer(&gen.rdl); + history = rdline_get_history_item(&gen.rdl, 0); + if (history) { + same = !memcmp(buffer, history, strlen(history)) && + buffer[strlen(history)] == '\n'; + } + else + same = 0; + if (strlen(buffer) > 1 && !same) + rdline_add_history(&gen.rdl, buffer); + rdline_newline(&gen.rdl, gen.prompt); + } + } + + return 0; +} diff --git a/projects/microb2009/mainboard/cmdline.h b/projects/microb2009/mainboard/cmdline.h new file mode 100644 index 0000000..f80b9b3 --- /dev/null +++ b/projects/microb2009/mainboard/cmdline.h @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cmdline.h,v 1.4 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#define CMDLINE_UART 1 + +/* uart rx callback for reset() */ +void emergency(char c); + +/* log function */ +void mylog(struct error * e, ...); + +/* launch cmdline */ +int cmdline_interact(void); + +static inline uint8_t cmdline_keypressed(void) { + return (uart_recv_nowait(CMDLINE_UART) != -1); +} + +static inline int16_t cmdline_getchar(void) { + return uart_recv_nowait(CMDLINE_UART); +} + +static inline uint8_t cmdline_getchar_wait(void) { + return uart_recv(CMDLINE_UART); +} diff --git a/projects/microb2009/mainboard/commands.c b/projects/microb2009/mainboard/commands.c new file mode 100644 index 0000000..107606e --- /dev/null +++ b/projects/microb2009/mainboard/commands.c @@ -0,0 +1,219 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.9 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdlib.h> +#include <aversive/pgmspace.h> +#include <parse.h> + +/* commands_gen.c */ +extern parse_pgm_inst_t cmd_reset; +extern parse_pgm_inst_t cmd_bootloader; +extern parse_pgm_inst_t cmd_encoders; +extern parse_pgm_inst_t cmd_pwm; +extern parse_pgm_inst_t cmd_adc; +extern parse_pgm_inst_t cmd_sensor; +extern parse_pgm_inst_t cmd_log; +extern parse_pgm_inst_t cmd_log_show; +extern parse_pgm_inst_t cmd_log_type; +extern parse_pgm_inst_t cmd_stack_space; +extern parse_pgm_inst_t cmd_scheduler; + +/* commands_ax12.c */ +extern parse_pgm_inst_t cmd_baudrate; +extern parse_pgm_inst_t cmd_uint16_read; +extern parse_pgm_inst_t cmd_uint16_write; +extern parse_pgm_inst_t cmd_uint8_read; +extern parse_pgm_inst_t cmd_uint8_write; + +/* commands_cs.c */ +extern parse_pgm_inst_t cmd_gain; +extern parse_pgm_inst_t cmd_gain_show; +extern parse_pgm_inst_t cmd_speed; +extern parse_pgm_inst_t cmd_speed_show; +extern parse_pgm_inst_t cmd_derivate_filter; +extern parse_pgm_inst_t cmd_derivate_filter_show; +extern parse_pgm_inst_t cmd_consign; +extern parse_pgm_inst_t cmd_maximum; +extern parse_pgm_inst_t cmd_maximum_show; +extern parse_pgm_inst_t cmd_quadramp; +extern parse_pgm_inst_t cmd_quadramp_show; +extern parse_pgm_inst_t cmd_cs_status; +extern parse_pgm_inst_t cmd_blocking_i; +extern parse_pgm_inst_t cmd_blocking_i_show; + +/* commands_mainboard.c */ +extern parse_pgm_inst_t cmd_event; +extern parse_pgm_inst_t cmd_spi_test; +extern parse_pgm_inst_t cmd_opponent; +extern parse_pgm_inst_t cmd_opponent_set; +extern parse_pgm_inst_t cmd_start; +extern parse_pgm_inst_t cmd_interact; +extern parse_pgm_inst_t cmd_color; +extern parse_pgm_inst_t cmd_rs; +extern parse_pgm_inst_t cmd_i2cdebug; +extern parse_pgm_inst_t cmd_mechboard_show; +extern parse_pgm_inst_t cmd_mechboard_setmode1; +extern parse_pgm_inst_t cmd_mechboard_setmode2; +extern parse_pgm_inst_t cmd_mechboard_setmode3; +extern parse_pgm_inst_t cmd_mechboard_setmode4; +extern parse_pgm_inst_t cmd_mechboard_setmode5; +extern parse_pgm_inst_t cmd_pickup_wheels; +extern parse_pgm_inst_t cmd_beacon_start; +extern parse_pgm_inst_t cmd_pump_current; +extern parse_pgm_inst_t cmd_build_test; +extern parse_pgm_inst_t cmd_column_test; +extern parse_pgm_inst_t cmd_column_test2; +extern parse_pgm_inst_t cmd_lintel_test; +extern parse_pgm_inst_t cmd_pickup_test; +extern parse_pgm_inst_t cmd_scan_test; +extern parse_pgm_inst_t cmd_scan_test2; +extern parse_pgm_inst_t cmd_time_monitor; +extern parse_pgm_inst_t cmd_scanner; +extern parse_pgm_inst_t cmd_build_z1; +#ifdef TEST_BEACON +extern parse_pgm_inst_t cmd_beacon_opp_dump; +#endif +extern parse_pgm_inst_t cmd_test; + +/* commands_traj.c */ +extern parse_pgm_inst_t cmd_traj_speed; +extern parse_pgm_inst_t cmd_traj_speed_show; +extern parse_pgm_inst_t cmd_trajectory; +extern parse_pgm_inst_t cmd_trajectory_show; +extern parse_pgm_inst_t cmd_rs_gains; +extern parse_pgm_inst_t cmd_rs_gains_show; +extern parse_pgm_inst_t cmd_track; +extern parse_pgm_inst_t cmd_track_show; +extern parse_pgm_inst_t cmd_pt_list; +extern parse_pgm_inst_t cmd_pt_list_append; +extern parse_pgm_inst_t cmd_pt_list_del; +extern parse_pgm_inst_t cmd_pt_list_show; +extern parse_pgm_inst_t cmd_goto1; +extern parse_pgm_inst_t cmd_goto2; +extern parse_pgm_inst_t cmd_goto3; +extern parse_pgm_inst_t cmd_position; +extern parse_pgm_inst_t cmd_position_set; +extern parse_pgm_inst_t cmd_strat_infos; +extern parse_pgm_inst_t cmd_strat_conf; +extern parse_pgm_inst_t cmd_strat_conf2; +extern parse_pgm_inst_t cmd_strat_conf3; +extern parse_pgm_inst_t cmd_strat_conf4; +extern parse_pgm_inst_t cmd_subtraj; + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + + /* commands_gen.c */ + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_bootloader, + (parse_pgm_inst_t *)&cmd_encoders, + (parse_pgm_inst_t *)&cmd_pwm, + (parse_pgm_inst_t *)&cmd_adc, + (parse_pgm_inst_t *)&cmd_sensor, + (parse_pgm_inst_t *)&cmd_log, + (parse_pgm_inst_t *)&cmd_log_show, + (parse_pgm_inst_t *)&cmd_log_type, + (parse_pgm_inst_t *)&cmd_stack_space, + (parse_pgm_inst_t *)&cmd_scheduler, + + /* commands_ax12.c */ + (parse_pgm_inst_t *)&cmd_baudrate, + (parse_pgm_inst_t *)&cmd_uint16_read, + (parse_pgm_inst_t *)&cmd_uint16_write, + (parse_pgm_inst_t *)&cmd_uint8_read, + (parse_pgm_inst_t *)&cmd_uint8_write, + + /* commands_cs.c */ + (parse_pgm_inst_t *)&cmd_gain, + (parse_pgm_inst_t *)&cmd_gain_show, + (parse_pgm_inst_t *)&cmd_speed, + (parse_pgm_inst_t *)&cmd_speed_show, + (parse_pgm_inst_t *)&cmd_consign, + (parse_pgm_inst_t *)&cmd_derivate_filter, + (parse_pgm_inst_t *)&cmd_derivate_filter_show, + (parse_pgm_inst_t *)&cmd_maximum, + (parse_pgm_inst_t *)&cmd_maximum_show, + (parse_pgm_inst_t *)&cmd_quadramp, + (parse_pgm_inst_t *)&cmd_quadramp_show, + (parse_pgm_inst_t *)&cmd_cs_status, + (parse_pgm_inst_t *)&cmd_blocking_i, + (parse_pgm_inst_t *)&cmd_blocking_i_show, + + /* commands_mainboard.c */ + (parse_pgm_inst_t *)&cmd_event, + (parse_pgm_inst_t *)&cmd_spi_test, + (parse_pgm_inst_t *)&cmd_opponent, + (parse_pgm_inst_t *)&cmd_opponent_set, + (parse_pgm_inst_t *)&cmd_start, + (parse_pgm_inst_t *)&cmd_interact, + (parse_pgm_inst_t *)&cmd_color, + (parse_pgm_inst_t *)&cmd_rs, + (parse_pgm_inst_t *)&cmd_i2cdebug, + (parse_pgm_inst_t *)&cmd_mechboard_show, + (parse_pgm_inst_t *)&cmd_mechboard_setmode1, + (parse_pgm_inst_t *)&cmd_mechboard_setmode2, + (parse_pgm_inst_t *)&cmd_mechboard_setmode3, + (parse_pgm_inst_t *)&cmd_mechboard_setmode4, + (parse_pgm_inst_t *)&cmd_mechboard_setmode5, + (parse_pgm_inst_t *)&cmd_pickup_wheels, + (parse_pgm_inst_t *)&cmd_beacon_start, + (parse_pgm_inst_t *)&cmd_pump_current, + (parse_pgm_inst_t *)&cmd_build_test, + (parse_pgm_inst_t *)&cmd_column_test, + (parse_pgm_inst_t *)&cmd_column_test2, + (parse_pgm_inst_t *)&cmd_lintel_test, + (parse_pgm_inst_t *)&cmd_pickup_test, + (parse_pgm_inst_t *)&cmd_scan_test, + (parse_pgm_inst_t *)&cmd_scan_test2, + (parse_pgm_inst_t *)&cmd_time_monitor, + (parse_pgm_inst_t *)&cmd_scanner, + (parse_pgm_inst_t *)&cmd_build_z1, +#ifdef TEST_BEACON + (parse_pgm_inst_t *)&cmd_beacon_opp_dump, +#endif + (parse_pgm_inst_t *)&cmd_test, + + /* commands_traj.c */ + (parse_pgm_inst_t *)&cmd_traj_speed, + (parse_pgm_inst_t *)&cmd_traj_speed_show, + (parse_pgm_inst_t *)&cmd_trajectory, + (parse_pgm_inst_t *)&cmd_trajectory_show, + (parse_pgm_inst_t *)&cmd_rs_gains, + (parse_pgm_inst_t *)&cmd_rs_gains_show, + (parse_pgm_inst_t *)&cmd_track, + (parse_pgm_inst_t *)&cmd_track_show, + (parse_pgm_inst_t *)&cmd_pt_list, + (parse_pgm_inst_t *)&cmd_pt_list_append, + (parse_pgm_inst_t *)&cmd_pt_list_del, + (parse_pgm_inst_t *)&cmd_pt_list_show, + (parse_pgm_inst_t *)&cmd_goto1, + (parse_pgm_inst_t *)&cmd_goto2, + (parse_pgm_inst_t *)&cmd_position, + (parse_pgm_inst_t *)&cmd_position_set, + (parse_pgm_inst_t *)&cmd_strat_infos, + (parse_pgm_inst_t *)&cmd_strat_conf, + (parse_pgm_inst_t *)&cmd_strat_conf2, + (parse_pgm_inst_t *)&cmd_strat_conf3, + (parse_pgm_inst_t *)&cmd_strat_conf4, + (parse_pgm_inst_t *)&cmd_subtraj, + NULL, +}; diff --git a/projects/microb2009/mainboard/commands_ax12.c b/projects/microb2009/mainboard/commands_ax12.c new file mode 100644 index 0000000..804e084 --- /dev/null +++ b/projects/microb2009/mainboard/commands_ax12.c @@ -0,0 +1,375 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_ax12.c,v 1.3 2009-05-02 10:08:09 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" + +uint8_t addr_from_string(const char *s) +{ + /* 16 bits */ + if (!strcmp_P(s, PSTR("cw_angle_limit"))) + return AA_CW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("ccw_angle_limit"))) + return AA_CCW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("max_torque"))) + return AA_MAX_TORQUE_L; + if (!strcmp_P(s, PSTR("down_calibration"))) + return AA_DOWN_CALIBRATION_L; + if (!strcmp_P(s, PSTR("up_calibration"))) + return AA_UP_CALIBRATION_L; + if (!strcmp_P(s, PSTR("torque_limit"))) + return AA_TORQUE_LIMIT_L; + if (!strcmp_P(s, PSTR("position"))) + return AA_PRESENT_POSITION_L; + if (!strcmp_P(s, PSTR("speed"))) + return AA_PRESENT_SPEED_L; + if (!strcmp_P(s, PSTR("load"))) + return AA_PRESENT_LOAD_L; + if (!strcmp_P(s, PSTR("moving_speed"))) + return AA_MOVING_SPEED_L; + if (!strcmp_P(s, PSTR("model"))) + return AA_MODEL_NUMBER_L; + if (!strcmp_P(s, PSTR("goal_pos"))) + return AA_GOAL_POSITION_L; + if (!strcmp_P(s, PSTR("punch"))) + return AA_PUNCH_L; + + /* 8 bits */ + if (!strcmp_P(s, PSTR("firmware"))) + return AA_FIRMWARE; + if (!strcmp_P(s, PSTR("id"))) + return AA_ID; + if (!strcmp_P(s, PSTR("baudrate"))) + return AA_BAUD_RATE; + if (!strcmp_P(s, PSTR("delay"))) + return AA_DELAY_TIME; + if (!strcmp_P(s, PSTR("high_lim_temp"))) + return AA_HIGHEST_LIMIT_TEMP; + if (!strcmp_P(s, PSTR("low_lim_volt"))) + return AA_LOWEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("high_lim_volt"))) + return AA_HIGHEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("status_return"))) + return AA_STATUS_RETURN_LEVEL; + if (!strcmp_P(s, PSTR("alarm_led"))) + return AA_ALARM_LED; + if (!strcmp_P(s, PSTR("alarm_shutdown"))) + return AA_ALARM_SHUTDOWN; + if (!strcmp_P(s, PSTR("torque_enable"))) + return AA_TORQUE_ENABLE; + if (!strcmp_P(s, PSTR("led"))) + return AA_LED; + if (!strcmp_P(s, PSTR("cw_comp_margin"))) + return AA_CW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("ccw_comp_margin"))) + return AA_CCW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("cw_comp_slope"))) + return AA_CW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("ccw_comp_slope"))) + return AA_CCW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("voltage"))) + return AA_PRESENT_VOLTAGE; + if (!strcmp_P(s, PSTR("temp"))) + return AA_PRESENT_TEMP; + if (!strcmp_P(s, PSTR("reginst"))) + return AA_PRESENT_REGINST; + if (!strcmp_P(s, PSTR("moving"))) + return AA_MOVING; + if (!strcmp_P(s, PSTR("lock"))) + return AA_LOCK; + + return 0; +} + +/**********************************************************/ +/* Ax12_Stress */ + +/* this structure is filled when cmd_ax12_stress is parsed successfully */ +struct cmd_ax12_stress_result { + fixed_string_t arg0; + uint8_t id; +}; + +/* function called when cmd_ax12_stress is parsed successfully */ +static void cmd_ax12_stress_parsed(void *parsed_result, void *data) +{ + struct cmd_ax12_stress_result *res = parsed_result; + int i, nb_errs = 0; + uint8_t val; + microseconds t = time_get_us2(); + + for (i=0; i<1000; i++) { + if (AX12_read_byte(&gen.ax12, res->id, AA_ID, &val) != 0) + nb_errs ++; + } + + printf_P(PSTR("%d errors / 1000\r\n"), nb_errs); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %d ms\r\n"), (int)t); +} + +prog_char str_ax12_stress_arg0[] = "ax12_stress"; +parse_pgm_token_string_t cmd_ax12_stress_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_ax12_stress_result, arg0, str_ax12_stress_arg0); +parse_pgm_token_num_t cmd_ax12_stress_id = TOKEN_NUM_INITIALIZER(struct cmd_ax12_stress_result, id, UINT8); + +prog_char help_ax12_stress[] = "Stress an AX12 with 1000 'read id' commands"; +parse_pgm_inst_t cmd_ax12_stress = { + .f = cmd_ax12_stress_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_ax12_stress, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_ax12_stress_arg0, + (prog_void *)&cmd_ax12_stress_id, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_baudrate is parsed successfully */ +struct cmd_baudrate_result { + fixed_string_t arg0; + uint32_t arg1; +}; + +/* function called when cmd_baudrate is parsed successfully */ +static void cmd_baudrate_parsed(void * parsed_result, void * data) +{ + struct cmd_baudrate_result *res = parsed_result; + struct uart_config c; + + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); + uart_getconf(1, &c); + c.baudrate = res->arg1; + uart_setconf(1, &c); + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); +} + +prog_char str_baudrate_arg0[] = "baudrate"; +parse_pgm_token_string_t cmd_baudrate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0, str_baudrate_arg0); +parse_pgm_token_num_t cmd_baudrate_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1, UINT32); + +prog_char help_baudrate[] = "Change ax12 baudrate"; +parse_pgm_inst_t cmd_baudrate = { + .f = cmd_baudrate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_baudrate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_baudrate_arg0, + (prog_void *)&cmd_baudrate_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Uint16 */ + + +/* this structure is filled when cmd_uint16_read is parsed successfully */ +struct cmd_uint16_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint16_t val; +}; + +/* function called when cmd_uint16_read is parsed successfully */ +static void cmd_uint16_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint16_t val; + uint8_t addr = addr_from_string(res->arg1); + ret = AX12_read_int(&gen.ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.4x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint16_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint16_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0); +prog_char str_uint16_arg1[] = "moving_speed#model#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#down_calibration#up_calibration#torque_limit#" + "position#speed#load#punch"; +parse_pgm_token_string_t cmd_uint16_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1); +parse_pgm_token_num_t cmd_uint16_num = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, num, UINT8); + +prog_char help_uint16_read[] = "Read uint16 value (type, num)"; +parse_pgm_inst_t cmd_uint16_read = { + .f = cmd_uint16_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0, + (prog_void *)&cmd_uint16_arg1, + (prog_void *)&cmd_uint16_num, + NULL, + }, +}; + +/* function called when cmd_uint16_write is parsed successfully */ +static void cmd_uint16_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint8_t addr = addr_from_string(res->arg1); + printf_P(PSTR("writing %s: %d [0x%.4x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_int(&gen.ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint16_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint16_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0_w); +prog_char str_uint16_arg1_w[] = "moving_speed#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#torque_limit#punch"; +parse_pgm_token_string_t cmd_uint16_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1_w); +parse_pgm_token_num_t cmd_uint16_val = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, val, UINT16); + +prog_char help_uint16_write[] = "Write uint16 value (write, num, val)"; +parse_pgm_inst_t cmd_uint16_write = { + .f = cmd_uint16_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0_w, + (prog_void *)&cmd_uint16_arg1_w, + (prog_void *)&cmd_uint16_num, + (prog_void *)&cmd_uint16_val, + NULL, + }, +}; + +/**********************************************************/ +/* Uint8 */ + + +/* this structure is filled when cmd_uint8_read is parsed successfully */ +struct cmd_uint8_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint8_t val; +}; + +/* function called when cmd_uint8_read is parsed successfully */ +static void cmd_uint8_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t ret; + uint8_t val; + uint8_t addr = addr_from_string(res->arg1); + + ret = AX12_read_byte(&gen.ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.2x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint8_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint8_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0); +prog_char str_uint8_arg1[] = "id#firmware#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "voltage#temp#reginst#moving#lock"; +parse_pgm_token_string_t cmd_uint8_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1); +parse_pgm_token_num_t cmd_uint8_num = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, num, UINT8); + +prog_char help_uint8_read[] = "Read uint8 value (type, num)"; +parse_pgm_inst_t cmd_uint8_read = { + .f = cmd_uint8_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0, + (prog_void *)&cmd_uint8_arg1, + (prog_void *)&cmd_uint8_num, + NULL, + }, +}; + +/* function called when cmd_uint8_write is parsed successfully */ +static void cmd_uint8_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t addr = addr_from_string(res->arg1); + uint8_t ret; + printf_P(PSTR("writing %s: %d [0x%.2x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_byte(&gen.ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint8_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint8_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0_w); +prog_char str_uint8_arg1_w[] = "id#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "reginst#lock"; +parse_pgm_token_string_t cmd_uint8_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1_w); +parse_pgm_token_num_t cmd_uint8_val = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, val, UINT8); + +prog_char help_uint8_write[] = "Write uint8 value (write, num, val)"; +parse_pgm_inst_t cmd_uint8_write = { + .f = cmd_uint8_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0_w, + (prog_void *)&cmd_uint8_arg1_w, + (prog_void *)&cmd_uint8_num, + (prog_void *)&cmd_uint8_val, + NULL, + }, +}; diff --git a/projects/microb2009/mainboard/commands_cs.c b/projects/microb2009/mainboard/commands_cs.c new file mode 100644 index 0000000..a39ab07 --- /dev/null +++ b/projects/microb2009/mainboard/commands_cs.c @@ -0,0 +1,677 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_cs.c,v 1.4 2009-05-02 10:08:09 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "cs.h" +#include "cmdline.h" + +struct csb_list { + const prog_char *name; + struct cs_block *csb; +}; + +prog_char csb_angle_str[] = "angle"; +prog_char csb_distance_str[] = "distance"; +struct csb_list csb_list[] = { + { .name = csb_angle_str, .csb = &mainboard.angle }, + { .name = csb_distance_str, .csb = &mainboard.distance }, +}; + +struct cmd_cs_result { + fixed_string_t cmdname; + fixed_string_t csname; +}; + +/* token to be used for all cs-related commands */ +prog_char str_csb_name[] = "angle#distance"; +parse_pgm_token_string_t cmd_csb_name_tok = TOKEN_STRING_INITIALIZER(struct cmd_cs_result, csname, str_csb_name); + +struct cs_block *cs_from_name(const char *name) +{ + int i; + + for (i=0; i<(sizeof(csb_list)/sizeof(*csb_list)); i++) { + if (!strcmp_P(name, csb_list[i].name)) + return csb_list[i].csb; + } + return NULL; +} + +/**********************************************************/ +/* Gains for control system */ + +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_result { + struct cmd_cs_result cs; + int16_t p; + int16_t i; + int16_t d; +}; + +/* function called when cmd_gain is parsed successfully */ +static void cmd_gain_parsed(void * parsed_result, void *show) +{ + struct cmd_gain_result *res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_gains(&csb->pid, res->p, res->i, res->d); + + printf_P(PSTR("%s %s %d %d %d\r\n"), + res->cs.cmdname, + res->cs.csname, + pid_get_gain_P(&csb->pid), + pid_get_gain_I(&csb->pid), + pid_get_gain_D(&csb->pid)); +} + +prog_char str_gain_arg0[] = "gain"; +parse_pgm_token_string_t cmd_gain_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, cs.cmdname, str_gain_arg0); +parse_pgm_token_num_t cmd_gain_p = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, p, INT16); +parse_pgm_token_num_t cmd_gain_i = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, i, INT16); +parse_pgm_token_num_t cmd_gain_d = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, d, INT16); + +prog_char help_gain[] = "Set gain values for PID"; +parse_pgm_inst_t cmd_gain = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_gain_p, + (prog_void *)&cmd_gain_i, + (prog_void *)&cmd_gain_d, + NULL, + }, +}; + +/* show */ +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_gain_show_arg[] = "show"; +parse_pgm_token_string_t cmd_gain_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_gain_show_result, show, str_gain_show_arg); + +prog_char help_gain_show[] = "Show gain values for PID"; +parse_pgm_inst_t cmd_gain_show = { + .f = cmd_gain_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_gain_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_gain_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Speeds for control system */ + +/* this structure is filled when cmd_speed is parsed successfully */ +struct cmd_speed_result { + struct cmd_cs_result cs; + uint16_t s; +}; + +/* function called when cmd_speed is parsed successfully */ +static void cmd_speed_parsed(void *parsed_result, void *show) +{ + struct cmd_speed_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + +#if notyet + if (!show) + ramp_set_vars(&csb->ramp, res->s, res->s); /* set speed */ + + printf_P(PSTR("%s %lu\r\n"), + res->cs.csname, + ext.r_b.var_pos); +#else + printf_P(PSTR("TODO\r\n")); +#endif +} + +prog_char str_speed_arg0[] = "speed"; +parse_pgm_token_string_t cmd_speed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, cs.cmdname, str_speed_arg0); +parse_pgm_token_num_t cmd_speed_s = TOKEN_NUM_INITIALIZER(struct cmd_speed_result, s, UINT16); + +prog_char help_speed[] = "Set speed values for ramp filter"; +parse_pgm_inst_t cmd_speed = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_speed_s, + NULL, + }, +}; + +/* show */ +struct cmd_speed_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_speed_show_arg[] = "show"; +parse_pgm_token_string_t cmd_speed_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_speed_show_result, show, str_speed_show_arg); + +prog_char help_speed_show[] = "Show speed values for ramp filter"; +parse_pgm_inst_t cmd_speed_show = { + .f = cmd_speed_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_speed_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_speed_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Derivate_Filters for control system */ + +/* this structure is filled when cmd_derivate_filter is parsed successfully */ +struct cmd_derivate_filter_result { + struct cmd_cs_result cs; + uint8_t size; +}; + +/* function called when cmd_derivate_filter is parsed successfully */ +static void cmd_derivate_filter_parsed(void *parsed_result, void *show) +{ + struct cmd_derivate_filter_result * res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_derivate_filter(&csb->pid, res->size); + + printf_P(PSTR("%s %s %u\r\n"), + res->cs.cmdname, + res->cs.csname, + pid_get_derivate_filter(&csb->pid)); +} + +prog_char str_derivate_filter_arg0[] = "derivate_filter"; +parse_pgm_token_string_t cmd_derivate_filter_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_derivate_filter_result, cs.cmdname, str_derivate_filter_arg0); +parse_pgm_token_num_t cmd_derivate_filter_size = TOKEN_NUM_INITIALIZER(struct cmd_derivate_filter_result, size, UINT32); + +prog_char help_derivate_filter[] = "Set derivate_filter values for PID (in, I, out)"; +parse_pgm_inst_t cmd_derivate_filter = { + .f = cmd_derivate_filter_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_derivate_filter, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_derivate_filter_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_derivate_filter_size, + NULL, + }, +}; + +/* show */ + +struct cmd_derivate_filter_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_derivate_filter_show_arg[] = "show"; +parse_pgm_token_string_t cmd_derivate_filter_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_derivate_filter_show_result, show, str_derivate_filter_show_arg); + +prog_char help_derivate_filter_show[] = "Show derivate_filter values for PID"; +parse_pgm_inst_t cmd_derivate_filter_show = { + .f = cmd_derivate_filter_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_derivate_filter_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_derivate_filter_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_derivate_filter_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Consign for control system */ + +/* this structure is filled when cmd_consign is parsed successfully */ +struct cmd_consign_result { + struct cmd_cs_result cs; + int32_t p; +}; + +/* function called when cmd_consign is parsed successfully */ +static void cmd_consign_parsed(void * parsed_result, void *data) +{ + struct cmd_consign_result * res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + cs_set_consign(&csb->cs, res->p); +} + +prog_char str_consign_arg0[] = "consign"; +parse_pgm_token_string_t cmd_consign_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_consign_result, cs.cmdname, str_consign_arg0); +parse_pgm_token_num_t cmd_consign_p = TOKEN_NUM_INITIALIZER(struct cmd_consign_result, p, INT32); + +prog_char help_consign[] = "Set consign value"; +parse_pgm_inst_t cmd_consign = { + .f = cmd_consign_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_consign, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_consign_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_consign_p, + NULL, + }, +}; + + +/**********************************************************/ +/* Maximums for control system */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_result { + struct cmd_cs_result cs; + uint32_t in; + uint32_t i; + uint32_t out; +}; + +/* function called when cmd_maximum is parsed successfully */ +static void cmd_maximum_parsed(void *parsed_result, void *show) +{ + struct cmd_maximum_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_maximums(&csb->pid, res->in, res->i, res->out); + + printf_P(PSTR("maximum %s %lu %lu %lu\r\n"), + res->cs.csname, + pid_get_max_in(&csb->pid), + pid_get_max_I(&csb->pid), + pid_get_max_out(&csb->pid)); +} + +prog_char str_maximum_arg0[] = "maximum"; +parse_pgm_token_string_t cmd_maximum_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, cs.cmdname, str_maximum_arg0); +parse_pgm_token_num_t cmd_maximum_in = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, in, UINT32); +parse_pgm_token_num_t cmd_maximum_i = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, i, UINT32); +parse_pgm_token_num_t cmd_maximum_out = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, out, UINT32); + +prog_char help_maximum[] = "Set maximum values for PID (in, I, out)"; +parse_pgm_inst_t cmd_maximum = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_maximum_in, + (prog_void *)&cmd_maximum_i, + (prog_void *)&cmd_maximum_out, + NULL, + }, +}; + +/* show */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; +prog_char str_maximum_show_arg[] = "show"; +parse_pgm_token_string_t cmd_maximum_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_maximum_show_result, show, str_maximum_show_arg); + +prog_char help_maximum_show[] = "Show maximum values for PID"; +parse_pgm_inst_t cmd_maximum_show = { + .f = cmd_maximum_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_maximum_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_maximum_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Quadramp for control system */ + +/* this structure is filled when cmd_quadramp is parsed successfully */ +struct cmd_quadramp_result { + struct cmd_cs_result cs; + uint32_t ap; + uint32_t an; + uint32_t sp; + uint32_t sn; +}; + +/* function called when cmd_quadramp is parsed successfully */ +static void cmd_quadramp_parsed(void *parsed_result, void *show) +{ + struct cmd_quadramp_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) { + quadramp_set_1st_order_vars(&csb->qr, res->sp, res->sn); + quadramp_set_2nd_order_vars(&csb->qr, res->ap, res->an); + } + + printf_P(PSTR("quadramp %s %ld %ld %ld %ld\r\n"), + res->cs.csname, + csb->qr.var_2nd_ord_pos, + csb->qr.var_2nd_ord_neg, + csb->qr.var_1st_ord_pos, + csb->qr.var_1st_ord_neg); +} + +prog_char str_quadramp_arg0[] = "quadramp"; +parse_pgm_token_string_t cmd_quadramp_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, cs.cmdname, str_quadramp_arg0); +parse_pgm_token_num_t cmd_quadramp_ap = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, ap, UINT32); +parse_pgm_token_num_t cmd_quadramp_an = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, an, UINT32); +parse_pgm_token_num_t cmd_quadramp_sp = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sp, UINT32); +parse_pgm_token_num_t cmd_quadramp_sn = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sn, UINT32); + +prog_char help_quadramp[] = "Set quadramp values (acc+, acc-, speed+, speed-)"; +parse_pgm_inst_t cmd_quadramp = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_quadramp_ap, + (prog_void *)&cmd_quadramp_an, + (prog_void *)&cmd_quadramp_sp, + (prog_void *)&cmd_quadramp_sn, + + NULL, + }, +}; + +/* show */ + +struct cmd_quadramp_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_quadramp_show_arg[] = "show"; +parse_pgm_token_string_t cmd_quadramp_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_show_result, show, str_quadramp_show_arg); + +prog_char help_quadramp_show[] = "Get quadramp values for control system"; +parse_pgm_inst_t cmd_quadramp_show = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_quadramp_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_quadramp_show_arg, + NULL, + }, +}; + + + +/**********************************************************/ +/* cs_status show for control system */ + +/* this structure is filled when cmd_cs_status is parsed successfully */ +struct cmd_cs_status_result { + struct cmd_cs_result cs; + fixed_string_t arg; +}; + +/* function called when cmd_cs_status is parsed successfully */ +static void cmd_cs_status_parsed(void *parsed_result, void *data) +{ + struct cmd_cs_status_result *res = parsed_result; + struct cs_block *csb; + uint8_t loop = 0; + uint8_t print_pid = 0, print_cs = 0; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + if (strcmp_P(res->arg, PSTR("on")) == 0) { + csb->on = 1; + printf_P(PSTR("%s is on\r\n"), res->cs.csname); + return; + } + else if (strcmp_P(res->arg, PSTR("off")) == 0) { + csb->on = 0; + printf_P(PSTR("%s is off\r\n"), res->cs.csname); + return; + } + else if (strcmp_P(res->arg, PSTR("show")) == 0) { + print_cs = 1; + } + else if (strcmp_P(res->arg, PSTR("loop_show")) == 0) { + loop = 1; + print_cs = 1; + } + else if (strcmp_P(res->arg, PSTR("pid_show")) == 0) { + print_pid = 1; + } + else if (strcmp_P(res->arg, PSTR("pid_loop_show")) == 0) { + print_pid = 1; + loop = 1; + } + + printf_P(PSTR("%s cs is %s\r\n"), res->cs.csname, csb->on ? "on":"off"); + do { + if (print_cs) + dump_cs(res->cs.csname, &csb->cs); + if (print_pid) + dump_pid(res->cs.csname, &csb->pid); + wait_ms(100); + } while(loop && !cmdline_keypressed()); +} + +prog_char str_cs_status_arg0[] = "cs_status"; +parse_pgm_token_string_t cmd_cs_status_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_cs_status_result, cs.cmdname, str_cs_status_arg0); +prog_char str_cs_status_arg[] = "pid_show#pid_loop_show#show#loop_show#on#off"; +parse_pgm_token_string_t cmd_cs_status_arg = TOKEN_STRING_INITIALIZER(struct cmd_cs_status_result, arg, str_cs_status_arg); + +prog_char help_cs_status[] = "Show cs status"; +parse_pgm_inst_t cmd_cs_status = { + .f = cmd_cs_status_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_cs_status, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_cs_status_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_cs_status_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Blocking_I for control system */ + +/* this structure is filled when cmd_blocking_i is parsed successfully */ +struct cmd_blocking_i_result { + struct cmd_cs_result cs; + int32_t k1; + int32_t k2; + uint32_t i; + uint16_t cpt; +}; + +/* function called when cmd_blocking_i is parsed successfully */ +static void cmd_blocking_i_parsed(void *parsed_result, void *show) +{ + struct cmd_blocking_i_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + bd_set_current_thresholds(&csb->bd, res->k1, res->k2, + res->i, res->cpt); + + printf_P(PSTR("%s %s %ld %ld %ld %d\r\n"), + res->cs.cmdname, + res->cs.csname, + csb->bd.k1, + csb->bd.k2, + csb->bd.i_thres, + csb->bd.cpt_thres); +} + +prog_char str_blocking_i_arg0[] = "blocking"; +parse_pgm_token_string_t cmd_blocking_i_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_blocking_i_result, cs.cmdname, str_blocking_i_arg0); +parse_pgm_token_num_t cmd_blocking_i_k1 = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, k1, INT32); +parse_pgm_token_num_t cmd_blocking_i_k2 = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, k2, INT32); +parse_pgm_token_num_t cmd_blocking_i_i = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, i, UINT32); +parse_pgm_token_num_t cmd_blocking_i_cpt = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, cpt, UINT16); + +prog_char help_blocking_i[] = "Set blocking detection values (k1, k2, i, cpt)"; +parse_pgm_inst_t cmd_blocking_i = { + .f = cmd_blocking_i_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_blocking_i, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_blocking_i_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_blocking_i_k1, + (prog_void *)&cmd_blocking_i_k2, + (prog_void *)&cmd_blocking_i_i, + (prog_void *)&cmd_blocking_i_cpt, + NULL, + }, +}; + +/* show */ + +struct cmd_blocking_i_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_blocking_i_show_arg[] = "show"; +parse_pgm_token_string_t cmd_blocking_i_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_blocking_i_show_result, show, str_blocking_i_show_arg); + +prog_char help_blocking_i_show[] = "Show blocking detection values"; +parse_pgm_inst_t cmd_blocking_i_show = { + .f = cmd_blocking_i_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_blocking_i_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_blocking_i_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_blocking_i_show_arg, + NULL, + }, +}; + + diff --git a/projects/microb2009/mainboard/commands_gen.c b/projects/microb2009/mainboard/commands_gen.c new file mode 100644 index 0000000..b20dcc8 --- /dev/null +++ b/projects/microb2009/mainboard/commands_gen.c @@ -0,0 +1,586 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_gen.c,v 1.8 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <encoders_spi.h> +#include <adc.h> + +#include <scheduler.h> +#include <scheduler_stats.h> +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include <diagnostic.h> + +#include "main.h" +#include "cmdline.h" +#include "sensor.h" + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(void * parsed_result, void * data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Bootloader */ + +/* this structure is filled when cmd_bootloader is parsed successfully */ +struct cmd_bootloader_result { + fixed_string_t arg0; +}; + +/* function called when cmd_bootloader is parsed successfully */ +static void cmd_bootloader_parsed(void *parsed_result, void *data) +{ + bootloader(); +} + +prog_char str_bootloader_arg0[] = "bootloader"; +parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0); + +prog_char help_bootloader[] = "Launch the bootloader"; +parse_pgm_inst_t cmd_bootloader = { + .f = cmd_bootloader_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_bootloader, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_bootloader_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Encoders tests */ + +/* this structure is filled when cmd_encoders is parsed successfully */ +struct cmd_encoders_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_encoders is parsed successfully */ +static void cmd_encoders_parsed(void *parsed_result, void *data) +{ + struct cmd_encoders_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("reset"))) { + encoders_spi_set_value((void *)0, 0); + encoders_spi_set_value((void *)1, 0); + encoders_spi_set_value((void *)2, 0); + encoders_spi_set_value((void *)3, 0); + return; + } + + /* show */ + while(!cmdline_keypressed()) { + printf_P(PSTR("% .8ld % .8ld % .8ld % .8ld\r\n"), + encoders_spi_get_value((void *)0), + encoders_spi_get_value((void *)1), + encoders_spi_get_value((void *)2), + encoders_spi_get_value((void *)3)); + wait_ms(100); + } +} + +prog_char str_encoders_arg0[] = "encoders"; +parse_pgm_token_string_t cmd_encoders_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg0, str_encoders_arg0); +prog_char str_encoders_arg1[] = "show#reset"; +parse_pgm_token_string_t cmd_encoders_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg1, str_encoders_arg1); + +prog_char help_encoders[] = "Show encoders values"; +parse_pgm_inst_t cmd_encoders = { + .f = cmd_encoders_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_encoders, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_encoders_arg0, + (prog_void *)&cmd_encoders_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Scheduler show */ + +/* this structure is filled when cmd_scheduler is parsed successfully */ +struct cmd_scheduler_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_scheduler is parsed successfully */ +static void cmd_scheduler_parsed(void *parsed_result, void *data) +{ + scheduler_dump_events(); + scheduler_stats_dump(); +} + +prog_char str_scheduler_arg0[] = "scheduler"; +parse_pgm_token_string_t cmd_scheduler_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg0, str_scheduler_arg0); +prog_char str_scheduler_arg1[] = "show"; +parse_pgm_token_string_t cmd_scheduler_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg1, str_scheduler_arg1); + +prog_char help_scheduler[] = "Show scheduler events"; +parse_pgm_inst_t cmd_scheduler = { + .f = cmd_scheduler_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scheduler, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scheduler_arg0, + (prog_void *)&cmd_scheduler_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pwms tests */ + +/* this structure is filled when cmd_pwm is parsed successfully */ +struct cmd_pwm_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; +}; + +/* function called when cmd_pwm is parsed successfully */ +static void cmd_pwm_parsed(void * parsed_result, void * data) +{ + void * pwm_ptr = NULL; + struct cmd_pwm_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("1(4A)"))) + pwm_ptr = &gen.pwm1_4A; + else if (!strcmp_P(res->arg1, PSTR("2(4B)"))) + pwm_ptr = &gen.pwm2_4B; + else if (!strcmp_P(res->arg1, PSTR("3(1A)"))) + pwm_ptr = &gen.pwm3_1A; + else if (!strcmp_P(res->arg1, PSTR("4(1B)"))) + pwm_ptr = &gen.pwm4_1B; + + else if (!strcmp_P(res->arg1, PSTR("s1(3C)"))) + pwm_ptr = &gen.servo1; + else if (!strcmp_P(res->arg1, PSTR("s2(5A)"))) + pwm_ptr = &gen.servo2; + else if (!strcmp_P(res->arg1, PSTR("s3(5B)"))) + pwm_ptr = &gen.servo3; + else if (!strcmp_P(res->arg1, PSTR("s3(5C)"))) + pwm_ptr = &gen.servo4; + + if (pwm_ptr) + pwm_ng_set(pwm_ptr, res->arg2); + + printf_P(PSTR("done\r\n")); +} + +prog_char str_pwm_arg0[] = "pwm"; +parse_pgm_token_string_t cmd_pwm_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg0, str_pwm_arg0); +prog_char str_pwm_arg1[] = "1(4A)#2(4B)#3(1A)#4(1B)#s1(3C)#s2(5A)#s3(5B)#s4(5C)"; +parse_pgm_token_string_t cmd_pwm_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg1, str_pwm_arg1); +parse_pgm_token_num_t cmd_pwm_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pwm_result, arg2, INT16); + +prog_char help_pwm[] = "Set pwm values [-4096 ; 4095]"; +parse_pgm_inst_t cmd_pwm = { + .f = cmd_pwm_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pwm, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pwm_arg0, + (prog_void *)&cmd_pwm_arg1, + (prog_void *)&cmd_pwm_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Adcs tests */ + +/* this structure is filled when cmd_adc is parsed successfully */ +struct cmd_adc_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_adc is parsed successfully */ +static void cmd_adc_parsed(void *parsed_result, void *data) +{ + struct cmd_adc_result *res = parsed_result; + uint8_t i, loop = 0; + + if (!strcmp_P(res->arg1, PSTR("loop_show"))) + loop = 1; + + do { + printf_P(PSTR("ADC values: ")); + for (i=0; i<ADC_MAX; i++) { + printf_P(PSTR("%.4d "), sensor_get_adc(i)); + } + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (loop && !cmdline_keypressed()); +} + +prog_char str_adc_arg0[] = "adc"; +parse_pgm_token_string_t cmd_adc_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_adc_result, arg0, str_adc_arg0); +prog_char str_adc_arg1[] = "show#loop_show"; +parse_pgm_token_string_t cmd_adc_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_adc_result, arg1, str_adc_arg1); + +prog_char help_adc[] = "Show adc values"; +parse_pgm_inst_t cmd_adc = { + .f = cmd_adc_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_adc, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_adc_arg0, + (prog_void *)&cmd_adc_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Sensors tests */ + +/* this structure is filled when cmd_sensor is parsed successfully */ +struct cmd_sensor_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_sensor is parsed successfully */ +static void cmd_sensor_parsed(void *parsed_result, void *data) +{ + struct cmd_sensor_result *res = parsed_result; + uint8_t i, loop = 0; + + if (!strcmp_P(res->arg1, PSTR("loop_show"))) + loop = 1; + + do { + printf_P(PSTR("SENSOR values: ")); + for (i=0; i<SENSOR_MAX; i++) { + printf_P(PSTR("%d "), !!sensor_get(i)); + } + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (loop && !cmdline_keypressed()); +} + +prog_char str_sensor_arg0[] = "sensor"; +parse_pgm_token_string_t cmd_sensor_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_sensor_result, arg0, str_sensor_arg0); +prog_char str_sensor_arg1[] = "show#loop_show"; +parse_pgm_token_string_t cmd_sensor_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_sensor_result, arg1, str_sensor_arg1); + +prog_char help_sensor[] = "Show sensor values"; +parse_pgm_inst_t cmd_sensor = { + .f = cmd_sensor_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sensor, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_sensor_arg0, + (prog_void *)&cmd_sensor_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Log */ + +/* this structure is filled when cmd_log is parsed successfully */ +struct cmd_log_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t arg2; + fixed_string_t arg3; +}; + +/* keep it sync with string choice */ +static const prog_char uart_log[] = "uart"; +static const prog_char rs_log[] = "rs"; +static const prog_char traj_log[] = "traj"; +static const prog_char i2c_log[] = "i2c"; +static const prog_char oa_log[] = "oa"; +static const prog_char strat_log[] = "strat"; +static const prog_char i2cproto_log[] = "i2cproto"; +static const prog_char sensor_log[] = "sensor"; +static const prog_char block_log[] = "bd"; +static const prog_char cs_log[] = "cs"; + +struct log_name_and_num { + const prog_char * name; + uint8_t num; +}; + +static const struct log_name_and_num log_name_and_num[] = { + { uart_log, E_UART }, + { rs_log, E_ROBOT_SYSTEM }, + { traj_log, E_TRAJECTORY }, + { i2c_log, E_I2C }, + { oa_log, E_OA }, + { strat_log, E_USER_STRAT }, + { i2cproto_log, E_USER_I2C_PROTO }, + { sensor_log, E_USER_SENSOR }, + { block_log, E_BLOCKING_DETECTION_MANAGER }, + { cs_log, E_USER_CS }, +}; + +static uint8_t +log_name2num(const char * s) +{ + uint8_t i; + + for (i=0; i<sizeof(log_name_and_num)/sizeof(struct log_name_and_num); i++) { + if (!strcmp_P(s, log_name_and_num[i].name)) { + return log_name_and_num[i].num; + } + } + return 0; +} + +const prog_char * +log_num2name(uint8_t num) +{ + uint8_t i; + + for (i=0; i<sizeof(log_name_and_num)/sizeof(struct log_name_and_num); i++) { + if (num == log_name_and_num[i].num) { + return log_name_and_num[i].name; + } + } + return NULL; +} + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_do_show(void) +{ + uint8_t i, empty=1; + const prog_char * name; + + printf_P(PSTR("log level is %d\r\n"), gen.log_level); + for (i=0; i<NB_LOGS; i++) { + name = log_num2name(gen.logs[i]); + if (name) { + printf_P(PSTR("log type %S is on\r\n"), name); + empty = 0; + } + } + if (empty) + printf_P(PSTR("no log configured\r\n"), gen.logs[i]); +} + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_parsed(void * parsed_result, void * data) +{ + struct cmd_log_result *res = (struct cmd_log_result *) parsed_result; + + if (!strcmp_P(res->arg1, PSTR("level"))) { + gen.log_level = res->arg2; + } + + /* else it is a show */ + cmd_log_do_show(); +} + +prog_char str_log_arg0[] = "log"; +parse_pgm_token_string_t cmd_log_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg0, str_log_arg0); +prog_char str_log_arg1[] = "level"; +parse_pgm_token_string_t cmd_log_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1); +parse_pgm_token_num_t cmd_log_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_log_result, arg2, INT32); + +prog_char help_log[] = "Set log options: level (0 -> 5)"; +parse_pgm_inst_t cmd_log = { + .f = cmd_log_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1, + (prog_void *)&cmd_log_arg2, + NULL, + }, +}; + +prog_char str_log_arg1_show[] = "show"; +parse_pgm_token_string_t cmd_log_arg1_show = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1_show); + +prog_char help_log_show[] = "Show configured logs"; +parse_pgm_inst_t cmd_log_show = { + .f = cmd_log_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1_show, + NULL, + }, +}; + +/* this structure is filled when cmd_log is parsed successfully */ +struct cmd_log_type_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_type_parsed(void * parsed_result, void * data) +{ + struct cmd_log_type_result *res = (struct cmd_log_type_result *) parsed_result; + uint8_t lognum; + uint8_t i; + + lognum = log_name2num(res->arg2); + if (lognum == 0) { + printf_P(PSTR("Cannot find log num\r\n")); + return; + } + + if (!strcmp_P(res->arg3, PSTR("on"))) { + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == lognum) { + printf_P(PSTR("Already on\r\n")); + return; + } + } + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == 0) { + gen.logs[i] = lognum; + break; + } + } + if (i==NB_LOGS) { + printf_P(PSTR("no more room\r\n")); + } + } + else if (!strcmp_P(res->arg3, PSTR("off"))) { + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == lognum) { + gen.logs[i] = 0; + break; + } + } + if (i==NB_LOGS) { + printf_P(PSTR("already off\r\n")); + } + } + cmd_log_do_show(); +} + +prog_char str_log_arg1_type[] = "type"; +parse_pgm_token_string_t cmd_log_arg1_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg1, str_log_arg1_type); +/* keep it sync with log_name_and_num above */ +prog_char str_log_arg2_type[] = "uart#rs#servo#traj#i2c#oa#strat#i2cproto#ext#sensor#bd#cs"; +parse_pgm_token_string_t cmd_log_arg2_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg2, str_log_arg2_type); +prog_char str_log_arg3[] = "on#off"; +parse_pgm_token_string_t cmd_log_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg3, str_log_arg3); + +prog_char help_log_type[] = "Set log type"; +parse_pgm_inst_t cmd_log_type = { + .f = cmd_log_type_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log_type, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1_type, + (prog_void *)&cmd_log_arg2_type, + (prog_void *)&cmd_log_arg3, + NULL, + }, +}; + + +/**********************************************************/ +/* Stack_Space */ + +/* this structure is filled when cmd_stack_space is parsed successfully */ +struct cmd_stack_space_result { + fixed_string_t arg0; +}; + +/* function called when cmd_stack_space is parsed successfully */ +static void cmd_stack_space_parsed(void *parsed_result, void *data) +{ + printf("res stack: %d\r\n", min_stack_space_available()); + +} + +prog_char str_stack_space_arg0[] = "stack_space"; +parse_pgm_token_string_t cmd_stack_space_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_stack_space_result, arg0, str_stack_space_arg0); + +prog_char help_stack_space[] = "Display remaining stack space"; +parse_pgm_inst_t cmd_stack_space = { + .f = cmd_stack_space_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_stack_space, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_stack_space_arg0, + NULL, + }, +}; diff --git a/projects/microb2009/mainboard/commands_mainboard.c b/projects/microb2009/mainboard/commands_mainboard.c new file mode 100644 index 0000000..b379dc1 --- /dev/null +++ b/projects/microb2009/mainboard/commands_mainboard.c @@ -0,0 +1,2154 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_mainboard.c,v 1.9 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> +#include <avr/eeprom.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> +#include <i2c.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "../common/i2c_commands.h" +#include "../common/eeprom_mapping.h" + +#include "main.h" +#include "sensor.h" +#include "cmdline.h" +#include "strat.h" +#include "strat_utils.h" +#include "strat_base.h" +#include "i2c_protocol.h" +#include "actuator.h" + +struct cmd_event_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + + +/* function called when cmd_event is parsed successfully */ +static void cmd_event_parsed(void *parsed_result, void *data) +{ + u08 bit=0; + + struct cmd_event_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("all"))) { + bit = DO_ENCODERS | DO_CS | DO_RS | DO_POS | + DO_BD | DO_TIMER | DO_POWER; + if (!strcmp_P(res->arg2, PSTR("on"))) + mainboard.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) + mainboard.flags &= bit; + else { /* show */ + printf_P(PSTR("encoders is %s\r\n"), + (DO_ENCODERS & mainboard.flags) ? "on":"off"); + printf_P(PSTR("cs is %s\r\n"), + (DO_CS & mainboard.flags) ? "on":"off"); + printf_P(PSTR("rs is %s\r\n"), + (DO_RS & mainboard.flags) ? "on":"off"); + printf_P(PSTR("pos is %s\r\n"), + (DO_POS & mainboard.flags) ? "on":"off"); + printf_P(PSTR("bd is %s\r\n"), + (DO_BD & mainboard.flags) ? "on":"off"); + printf_P(PSTR("timer is %s\r\n"), + (DO_TIMER & mainboard.flags) ? "on":"off"); + printf_P(PSTR("power is %s\r\n"), + (DO_POWER & mainboard.flags) ? "on":"off"); + } + return; + } + + if (!strcmp_P(res->arg1, PSTR("encoders"))) + bit = DO_ENCODERS; + else if (!strcmp_P(res->arg1, PSTR("cs"))) { + strat_hardstop(); + bit = DO_CS; + } + else if (!strcmp_P(res->arg1, PSTR("rs"))) + bit = DO_RS; + else if (!strcmp_P(res->arg1, PSTR("pos"))) + bit = DO_POS; + else if (!strcmp_P(res->arg1, PSTR("bd"))) + bit = DO_BD; + else if (!strcmp_P(res->arg1, PSTR("timer"))) { + time_reset(); + bit = DO_TIMER; + } + else if (!strcmp_P(res->arg1, PSTR("power"))) + bit = DO_POWER; + + if (!strcmp_P(res->arg2, PSTR("on"))) + mainboard.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) { + if (!strcmp_P(res->arg1, PSTR("cs"))) { + pwm_ng_set(LEFT_PWM, 0); + pwm_ng_set(RIGHT_PWM, 0); + } + mainboard.flags &= (~bit); + } + printf_P(PSTR("%s is %s\r\n"), res->arg1, + (bit & mainboard.flags) ? "on":"off"); +} + +prog_char str_event_arg0[] = "event"; +parse_pgm_token_string_t cmd_event_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg0, str_event_arg0); +prog_char str_event_arg1[] = "all#encoders#cs#rs#pos#bd#timer#power"; +parse_pgm_token_string_t cmd_event_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg1); +prog_char str_event_arg2[] = "on#off#show"; +parse_pgm_token_string_t cmd_event_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg2, str_event_arg2); + +prog_char help_event[] = "Enable/disable events"; +parse_pgm_inst_t cmd_event = { + .f = cmd_event_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_event, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_event_arg0, + (prog_void *)&cmd_event_arg1, + (prog_void *)&cmd_event_arg2, + NULL, + }, +}; + + +/**********************************************************/ +/* Spi_Test */ + +/* this structure is filled when cmd_spi_test is parsed successfully */ +struct cmd_spi_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_spi_test is parsed successfully */ +static void cmd_spi_test_parsed(void * parsed_result, void * data) +{ + uint16_t i = 0, ret = 0, ret2 = 0; + + if (mainboard.flags & DO_ENCODERS) { + printf_P(PSTR("Disable encoder event first\r\n")); + return; + } + + do { + spi_slave_select(0); + ret = spi_send_and_receive_byte(i); + ret2 = spi_send_and_receive_byte(i); + spi_slave_deselect(0); + + if ((i & 0x7ff) == 0) + printf_P(PSTR("Sent %.4x twice, received %x %x\r\n"), + i, ret, ret2); + + i++; + } while(!cmdline_keypressed()); +} + +prog_char str_spi_test_arg0[] = "spi_test"; +parse_pgm_token_string_t cmd_spi_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_spi_test_result, arg0, str_spi_test_arg0); + +prog_char help_spi_test[] = "Test the SPI"; +parse_pgm_inst_t cmd_spi_test = { + .f = cmd_spi_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_spi_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_spi_test_arg0, + NULL, + }, +}; + + + +/**********************************************************/ +/* Opponent tests */ + +/* this structure is filled when cmd_opponent is parsed successfully */ +struct cmd_opponent_result { + fixed_string_t arg0; + fixed_string_t arg1; + int32_t arg2; + int32_t arg3; +}; + +/* function called when cmd_opponent is parsed successfully */ +static void cmd_opponent_parsed(void *parsed_result, void *data) +{ + int16_t x,y,d,a; + + if (get_opponent_xyda(&x, &y, &d, &a)) + printf_P(PSTR("No opponent\r\n")); + else + printf_P(PSTR("x=%d y=%d, d=%d a=%d\r\n"), x, y, d, a); +} + +prog_char str_opponent_arg0[] = "opponent"; +parse_pgm_token_string_t cmd_opponent_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_opponent_result, arg0, str_opponent_arg0); +prog_char str_opponent_arg1[] = "show"; +parse_pgm_token_string_t cmd_opponent_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_opponent_result, arg1, str_opponent_arg1); + +prog_char help_opponent[] = "Show (x,y) opponent"; +parse_pgm_inst_t cmd_opponent = { + .f = cmd_opponent_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_opponent, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_opponent_arg0, + (prog_void *)&cmd_opponent_arg1, + NULL, + }, +}; + + +prog_char str_opponent_arg1_set[] = "set"; +parse_pgm_token_string_t cmd_opponent_arg1_set = TOKEN_STRING_INITIALIZER(struct cmd_opponent_result, arg1, str_opponent_arg1_set); +parse_pgm_token_num_t cmd_opponent_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_opponent_result, arg2, INT32); +parse_pgm_token_num_t cmd_opponent_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_opponent_result, arg3, INT32); + +prog_char help_opponent_set[] = "Set (x,y) opponent"; +parse_pgm_inst_t cmd_opponent_set = { + .f = cmd_opponent_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_opponent_set, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_opponent_arg0, + (prog_void *)&cmd_opponent_arg1_set, + (prog_void *)&cmd_opponent_arg2, + (prog_void *)&cmd_opponent_arg3, + NULL, + }, +}; + + +/**********************************************************/ +/* Start */ + +/* this structure is filled when cmd_start is parsed successfully */ +struct cmd_start_result { + fixed_string_t arg0; + fixed_string_t color; + fixed_string_t debug; +}; + +/* function called when cmd_start is parsed successfully */ +static void cmd_start_parsed(void *parsed_result, void *data) +{ + struct cmd_start_result *res = parsed_result; + uint8_t old_level = gen.log_level; + + gen.logs[NB_LOGS] = E_USER_STRAT; + if (!strcmp_P(res->debug, PSTR("debug"))) { + strat_infos.dump_enabled = 1; + gen.log_level = 5; + } + else { + strat_infos.dump_enabled = 0; + gen.log_level = 0; + } + + if (!strcmp_P(res->color, PSTR("red"))) { + mainboard.our_color = I2C_COLOR_RED; + i2c_set_color(I2C_MECHBOARD_ADDR, I2C_COLOR_RED); + i2c_set_color(I2C_SENSORBOARD_ADDR, I2C_COLOR_RED); + } + else if (!strcmp_P(res->color, PSTR("green"))) { + mainboard.our_color = I2C_COLOR_GREEN; + i2c_set_color(I2C_MECHBOARD_ADDR, I2C_COLOR_GREEN); + i2c_set_color(I2C_SENSORBOARD_ADDR, I2C_COLOR_GREEN); + } + + printf_P(PSTR("Check that lintel is loaded\r\n")); + while(!cmdline_keypressed()); + + printf_P(PSTR("Press a key when beacon ready\r\n")); + i2c_sensorboard_set_beacon(0); + while(!cmdline_keypressed()); + i2c_sensorboard_set_beacon(1); + + strat_start(); + + gen.logs[NB_LOGS] = 0; + gen.log_level = old_level; +} + +prog_char str_start_arg0[] = "start"; +parse_pgm_token_string_t cmd_start_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_start_result, arg0, str_start_arg0); +prog_char str_start_color[] = "green#red"; +parse_pgm_token_string_t cmd_start_color = TOKEN_STRING_INITIALIZER(struct cmd_start_result, color, str_start_color); +prog_char str_start_debug[] = "debug#match"; +parse_pgm_token_string_t cmd_start_debug = TOKEN_STRING_INITIALIZER(struct cmd_start_result, debug, str_start_debug); + +prog_char help_start[] = "Start the robot"; +parse_pgm_inst_t cmd_start = { + .f = cmd_start_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_start, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_start_arg0, + (prog_void *)&cmd_start_color, + (prog_void *)&cmd_start_debug, + NULL, + }, +}; + + + +/**********************************************************/ +/* Interact */ + +/* this structure is filled when cmd_interact is parsed successfully */ +struct cmd_interact_result { + fixed_string_t arg0; +}; + +static void print_cs(void) +{ + printf_P(PSTR("cons_d=% .8ld cons_a=% .8ld fil_d=% .8ld fil_a=% .8ld " + "err_d=% .8ld err_a=% .8ld out_d=% .8ld out_a=% .8ld\r\n"), + cs_get_consign(&mainboard.distance.cs), + cs_get_consign(&mainboard.angle.cs), + cs_get_filtered_consign(&mainboard.distance.cs), + cs_get_filtered_consign(&mainboard.angle.cs), + cs_get_error(&mainboard.distance.cs), + cs_get_error(&mainboard.angle.cs), + cs_get_out(&mainboard.distance.cs), + cs_get_out(&mainboard.angle.cs)); +} + +static void print_pos(void) +{ + printf_P(PSTR("x=% .8d y=% .8d a=% .8d\r\n"), + position_get_x_s16(&mainboard.pos), + position_get_y_s16(&mainboard.pos), + position_get_a_deg_s16(&mainboard.pos)); +} + +static void print_time(void) +{ + printf_P(PSTR("time %d\r\n"),time_get_s()); +} + + +static void print_sensors(void) +{ +#ifdef notyet + if (sensor_start_switch()) + printf_P(PSTR("Start switch | ")); + else + printf_P(PSTR(" | ")); + + if (IR_DISP_SENSOR()) + printf_P(PSTR("IR disp | ")); + else + printf_P(PSTR(" | ")); + + printf_P(PSTR("\r\n")); +#endif +} + +static void print_pid(void) +{ + printf_P(PSTR("P=% .8ld I=% .8ld D=% .8ld out=% .8ld | " + "P=% .8ld I=% .8ld D=% .8ld out=% .8ld\r\n"), + pid_get_value_in(&mainboard.distance.pid) * pid_get_gain_P(&mainboard.distance.pid), + pid_get_value_I(&mainboard.distance.pid) * pid_get_gain_I(&mainboard.distance.pid), + pid_get_value_D(&mainboard.distance.pid) * pid_get_gain_D(&mainboard.distance.pid), + pid_get_value_out(&mainboard.distance.pid), + pid_get_value_in(&mainboard.angle.pid) * pid_get_gain_P(&mainboard.angle.pid), + pid_get_value_I(&mainboard.angle.pid) * pid_get_gain_I(&mainboard.angle.pid), + pid_get_value_D(&mainboard.angle.pid) * pid_get_gain_D(&mainboard.angle.pid), + pid_get_value_out(&mainboard.angle.pid)); +} + +#define PRINT_POS (1<<0) +#define PRINT_PID (1<<1) +#define PRINT_CS (1<<2) +#define PRINT_SENSORS (1<<3) +#define PRINT_TIME (1<<4) +#define PRINT_BLOCKING (1<<5) + +static void cmd_interact_parsed(void * parsed_result, void * data) +{ + int c; + int8_t cmd; + uint8_t print = 0; + struct vt100 vt100; + + vt100_init(&vt100); + + printf_P(PSTR("Display debugs:\r\n" + " 1:pos\r\n" + " 2:pid\r\n" + " 3:cs\r\n" + " 4:sensors\r\n" + " 5:time\r\n" + /* " 6:blocking\r\n" */ + "Commands:\r\n" + " arrows:move\r\n" + " space:stop\r\n" + " q:quit\r\n")); + + /* stop motors */ + mainboard.flags &= (~DO_CS); + pwm_set_and_save(LEFT_PWM, 0); + pwm_set_and_save(RIGHT_PWM, 0); + + while(1) { + if (print & PRINT_POS) { + print_pos(); + } + + if (print & PRINT_PID) { + print_pid(); + } + + if (print & PRINT_CS) { + print_cs(); + } + + if (print & PRINT_SENSORS) { + print_sensors(); + } + + if (print & PRINT_TIME) { + print_time(); + } +/* if (print & PRINT_BLOCKING) { */ +/* printf_P(PSTR("%s %s blocking=%d\r\n"), */ +/* mainboard.blocking ? "BLOCK1":" ", */ +/* rs_is_blocked(&mainboard.rs) ? "BLOCK2":" ", */ +/* rs_get_blocking(&mainboard.rs)); */ +/* } */ + + c = cmdline_getchar(); + if (c == -1) { + wait_ms(10); + continue; + } + cmd = vt100_parser(&vt100, c); + if (cmd == -2) { + wait_ms(10); + continue; + } + + if (cmd == -1) { + switch(c) { + case '1': print ^= PRINT_POS; break; + case '2': print ^= PRINT_PID; break; + case '3': print ^= PRINT_CS; break; + case '4': print ^= PRINT_SENSORS; break; + case '5': print ^= PRINT_TIME; break; + case '6': print ^= PRINT_BLOCKING; break; + + case 'q': + if (mainboard.flags & DO_CS) + strat_hardstop(); + pwm_set_and_save(LEFT_PWM, 0); + pwm_set_and_save(RIGHT_PWM, 0); + return; + case ' ': + pwm_set_and_save(LEFT_PWM, 0); + pwm_set_and_save(RIGHT_PWM, 0); + break; + default: + break; + } + } + else { + switch(cmd) { + case KEY_UP_ARR: + pwm_set_and_save(LEFT_PWM, 1200); + pwm_set_and_save(RIGHT_PWM, 1200); + break; + case KEY_LEFT_ARR: + pwm_set_and_save(LEFT_PWM, -1200); + pwm_set_and_save(RIGHT_PWM, 1200); + break; + case KEY_DOWN_ARR: + pwm_set_and_save(LEFT_PWM, -1200); + pwm_set_and_save(RIGHT_PWM, -1200); + break; + case KEY_RIGHT_ARR: + pwm_set_and_save(LEFT_PWM, 1200); + pwm_set_and_save(RIGHT_PWM, -1200); + break; + } + } + wait_ms(10); + } +} + +prog_char str_interact_arg0[] = "interact"; +parse_pgm_token_string_t cmd_interact_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_interact_result, arg0, str_interact_arg0); + +prog_char help_interact[] = "Interactive mode"; +parse_pgm_inst_t cmd_interact = { + .f = cmd_interact_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_interact, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_interact_arg0, + NULL, + }, +}; + + +/**********************************************************/ +/* Color */ + +/* this structure is filled when cmd_color is parsed successfully */ +struct cmd_color_result { + fixed_string_t arg0; + fixed_string_t color; +}; + +/* function called when cmd_color is parsed successfully */ +static void cmd_color_parsed(void *parsed_result, void *data) +{ + struct cmd_color_result *res = (struct cmd_color_result *) parsed_result; + if (!strcmp_P(res->color, PSTR("red"))) { + mainboard.our_color = I2C_COLOR_RED; + i2c_set_color(I2C_MECHBOARD_ADDR, I2C_COLOR_RED); + i2c_set_color(I2C_SENSORBOARD_ADDR, I2C_COLOR_RED); + } + else if (!strcmp_P(res->color, PSTR("green"))) { + mainboard.our_color = I2C_COLOR_GREEN; + i2c_set_color(I2C_MECHBOARD_ADDR, I2C_COLOR_GREEN); + i2c_set_color(I2C_SENSORBOARD_ADDR, I2C_COLOR_GREEN); + } + printf_P(PSTR("Done\r\n")); +} + +prog_char str_color_arg0[] = "color"; +parse_pgm_token_string_t cmd_color_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_color_result, arg0, str_color_arg0); +prog_char str_color_color[] = "green#red"; +parse_pgm_token_string_t cmd_color_color = TOKEN_STRING_INITIALIZER(struct cmd_color_result, color, str_color_color); + +prog_char help_color[] = "Set our color"; +parse_pgm_inst_t cmd_color = { + .f = cmd_color_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_color, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_color_arg0, + (prog_void *)&cmd_color_color, + NULL, + }, +}; + + +/**********************************************************/ +/* Rs tests */ + +/* this structure is filled when cmd_rs is parsed successfully */ +struct cmd_rs_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_rs is parsed successfully */ +static void cmd_rs_parsed(void *parsed_result, void *data) +{ + // struct cmd_rs_result *res = parsed_result; + do { + printf_P(PSTR("angle cons=% .6ld in=% .6ld out=% .6ld / "), + cs_get_consign(&mainboard.angle.cs), + cs_get_filtered_feedback(&mainboard.angle.cs), + cs_get_out(&mainboard.angle.cs)); + printf_P(PSTR("distance cons=% .6ld in=% .6ld out=% .6ld / "), + cs_get_consign(&mainboard.distance.cs), + cs_get_filtered_feedback(&mainboard.distance.cs), + cs_get_out(&mainboard.distance.cs)); + printf_P(PSTR("l=% .4ld r=% .4ld\r\n"), mainboard.pwm_l, + mainboard.pwm_r); + wait_ms(100); + } while(!cmdline_keypressed()); +} + +prog_char str_rs_arg0[] = "rs"; +parse_pgm_token_string_t cmd_rs_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_rs_result, arg0, str_rs_arg0); +prog_char str_rs_arg1[] = "show"; +parse_pgm_token_string_t cmd_rs_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_rs_result, arg1, str_rs_arg1); + +prog_char help_rs[] = "Show rs (robot system) values"; +parse_pgm_inst_t cmd_rs = { + .f = cmd_rs_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_rs, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_rs_arg0, + (prog_void *)&cmd_rs_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* I2cdebug */ + +/* this structure is filled when cmd_i2cdebug is parsed successfully */ +struct cmd_i2cdebug_result { + fixed_string_t arg0; +}; + +/* function called when cmd_i2cdebug is parsed successfully */ +static void cmd_i2cdebug_parsed(void * parsed_result, void * data) +{ + i2c_debug(); + i2c_protocol_debug(); +} + +prog_char str_i2cdebug_arg0[] = "i2cdebug"; +parse_pgm_token_string_t cmd_i2cdebug_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_i2cdebug_result, arg0, str_i2cdebug_arg0); + +prog_char help_i2cdebug[] = "I2c debug infos"; +parse_pgm_inst_t cmd_i2cdebug = { + .f = cmd_i2cdebug_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_i2cdebug, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_i2cdebug_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Mechboard_Show */ + +/* this structure is filled when cmd_mechboard_show is parsed successfully */ +struct cmd_mechboard_show_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_mechboard_show is parsed successfully */ +static void cmd_mechboard_show_parsed(void * parsed_result, void * data) +{ + printf_P(PSTR("mode = %x\r\n"), mechboard.mode); + printf_P(PSTR("status = %x\r\n"), mechboard.status); + printf_P(PSTR("lintel_count = %d\r\n"), mechboard.lintel_count); + + printf_P(PSTR("column_count = %d\r\n"), get_column_count()); + printf_P(PSTR("left1=%d left2=%d right1=%d right2=%d\r\n"), + pump_left1_is_full(), pump_left2_is_full(), + pump_right1_is_full(), pump_right2_is_full()); + + printf_P(PSTR("pump_left1 = %d\r\n"), mechboard.pump_left1); + printf_P(PSTR("pump_left2 = %d\r\n"), mechboard.pump_left2); + printf_P(PSTR("pump_right1 = %d\r\n"), mechboard.pump_right1); + printf_P(PSTR("pump_right2 = %d\r\n"), mechboard.pump_right2); + + printf_P(PSTR("servo_lintel_left = %d\r\n"), mechboard.servo_lintel_left); + printf_P(PSTR("servo_lintel_right = %d\r\n"), mechboard.servo_lintel_right); + +} + +prog_char str_mechboard_show_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_mechboard_show_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_show_result, arg0, str_mechboard_show_arg0); +prog_char str_mechboard_show_arg1[] = "show"; +parse_pgm_token_string_t cmd_mechboard_show_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_show_result, arg1, str_mechboard_show_arg1); + +prog_char help_mechboard_show[] = "show mechboard status"; +parse_pgm_inst_t cmd_mechboard_show = { + .f = cmd_mechboard_show_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_mechboard_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_mechboard_show_arg0, + (prog_void *)&cmd_mechboard_show_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Mechboard_Setmode1 */ + +/* this structure is filled when cmd_mechboard_setmode1 is parsed successfully */ +struct cmd_mechboard_setmode1_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_mechboard_setmode1 is parsed successfully */ +static void cmd_mechboard_setmode1_parsed(void *parsed_result, void *data) +{ + struct cmd_mechboard_setmode1_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("init"))) + i2c_mechboard_mode_init(); + else if (!strcmp_P(res->arg1, PSTR("manual"))) + i2c_mechboard_mode_manual(); + else if (!strcmp_P(res->arg1, PSTR("pickup"))) + i2c_mechboard_mode_pickup(); + else if (!strcmp_P(res->arg1, PSTR("lazy_harvest"))) + i2c_mechboard_mode_lazy_harvest(); + else if (!strcmp_P(res->arg1, PSTR("harvest"))) + i2c_mechboard_mode_harvest(); + else if (!strcmp_P(res->arg1, PSTR("prepare_get_lintel"))) + i2c_mechboard_mode_prepare_get_lintel(); + else if (!strcmp_P(res->arg1, PSTR("get_lintel"))) + i2c_mechboard_mode_get_lintel(); + else if (!strcmp_P(res->arg1, PSTR("put_lintel"))) + i2c_mechboard_mode_put_lintel(); + else if (!strcmp_P(res->arg1, PSTR("init"))) + i2c_mechboard_mode_init(); + else if (!strcmp_P(res->arg1, PSTR("eject"))) + i2c_mechboard_mode_init(); + else if (!strcmp_P(res->arg1, PSTR("clear"))) + i2c_mechboard_mode_clear(); + else if (!strcmp_P(res->arg1, PSTR("loaded"))) + i2c_mechboard_mode_loaded(); + else if (!strcmp_P(res->arg1, PSTR("store"))) + i2c_mechboard_mode_store(); + else if (!strcmp_P(res->arg1, PSTR("manivelle"))) + i2c_mechboard_mode_manivelle(); + else if (!strcmp_P(res->arg1, PSTR("lazy_pickup"))) + i2c_mechboard_mode_lazy_pickup(); +} + +prog_char str_mechboard_setmode1_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_mechboard_setmode1_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode1_result, arg0, str_mechboard_setmode1_arg0); +prog_char str_mechboard_setmode1_arg1[] = "manivelle#init#manual#pickup#prepare_get_lintel#get_lintel#put_lintel1#eject#clear#harvest#lazy_harvest#store#lazy_pickup"; +parse_pgm_token_string_t cmd_mechboard_setmode1_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode1_result, arg1, str_mechboard_setmode1_arg1); + +prog_char help_mechboard_setmode1[] = "set mechboard mode (mode)"; +parse_pgm_inst_t cmd_mechboard_setmode1 = { + .f = cmd_mechboard_setmode1_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_mechboard_setmode1, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_mechboard_setmode1_arg0, + (prog_void *)&cmd_mechboard_setmode1_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Mechboard_Setmode2 */ + +/* this structure is filled when cmd_mechboard_setmode2 is parsed successfully */ +struct cmd_mechboard_setmode2_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_mechboard_setmode2 is parsed successfully */ +static void cmd_mechboard_setmode2_parsed(void * parsed_result, void * data) +{ + struct cmd_mechboard_setmode2_result *res = parsed_result; + uint8_t side = I2C_LEFT_SIDE; + + if (!strcmp_P(res->arg2, PSTR("left"))) + side = I2C_LEFT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("right"))) + side = I2C_RIGHT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("center"))) + side = I2C_CENTER_SIDE; + else if (!strcmp_P(res->arg2, PSTR("auto"))) + side = I2C_AUTO_SIDE; + + if (!strcmp_P(res->arg1, PSTR("prepare_pickup"))) + i2c_mechboard_mode_prepare_pickup(side); + else if (!strcmp_P(res->arg1, PSTR("push_temple_disc"))) + i2c_mechboard_mode_push_temple_disc(side); +} + +prog_char str_mechboard_setmode2_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_mechboard_setmode2_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode2_result, arg0, str_mechboard_setmode2_arg0); +prog_char str_mechboard_setmode2_arg1[] = "prepare_pickup#push_temple_disc"; +parse_pgm_token_string_t cmd_mechboard_setmode2_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode2_result, arg1, str_mechboard_setmode2_arg1); +prog_char str_mechboard_setmode2_arg2[] = "left#right#auto#center"; +parse_pgm_token_string_t cmd_mechboard_setmode2_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode2_result, arg2, str_mechboard_setmode2_arg2); + +prog_char help_mechboard_setmode2[] = "set mechboard mode (more, side)"; +parse_pgm_inst_t cmd_mechboard_setmode2 = { + .f = cmd_mechboard_setmode2_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_mechboard_setmode2, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_mechboard_setmode2_arg0, + (prog_void *)&cmd_mechboard_setmode2_arg1, + (prog_void *)&cmd_mechboard_setmode2_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Mechboard_Setmode3 */ + +/* this structure is filled when cmd_mechboard_setmode3 is parsed successfully */ +struct cmd_mechboard_setmode3_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t level; +}; + +/* function called when cmd_mechboard_setmode3 is parsed successfully */ +static void cmd_mechboard_setmode3_parsed(void *parsed_result, void *data) +{ + struct cmd_mechboard_setmode3_result *res = parsed_result; + if (!strcmp_P(res->arg1, PSTR("autobuild"))) + i2c_mechboard_mode_simple_autobuild(res->level); + else if (!strcmp_P(res->arg1, PSTR("prepare_build"))) + i2c_mechboard_mode_prepare_build_both(res->level); + else if (!strcmp_P(res->arg1, PSTR("prepare_inside"))) + i2c_mechboard_mode_prepare_inside_both(res->level); + else if (!strcmp_P(res->arg1, PSTR("push_temple"))) + i2c_mechboard_mode_push_temple(res->level); +} + +prog_char str_mechboard_setmode3_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_mechboard_setmode3_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode3_result, arg0, str_mechboard_setmode3_arg0); +prog_char str_mechboard_setmode3_arg1[] = "autobuild#prepare_build#prepare_inside#push_temple"; +parse_pgm_token_string_t cmd_mechboard_setmode3_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode3_result, arg1, str_mechboard_setmode3_arg1); +parse_pgm_token_num_t cmd_mechboard_setmode3_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode3_result, level, UINT8); + +prog_char help_mechboard_setmode3[] = "set mechboard mode (mode, level)"; +parse_pgm_inst_t cmd_mechboard_setmode3 = { + .f = cmd_mechboard_setmode3_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_mechboard_setmode3, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_mechboard_setmode3_arg0, + (prog_void *)&cmd_mechboard_setmode3_arg1, + (prog_void *)&cmd_mechboard_setmode3_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Mechboard_Setmode4 */ + +/* this structure is filled when cmd_mechboard_setmode4 is parsed successfully */ +struct cmd_mechboard_setmode4_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t level_l; + uint8_t count_l; + uint8_t dist_l; + uint8_t level_r; + uint8_t count_r; + uint8_t dist_r; + uint8_t do_lintel; +}; + +/* function called when cmd_mechboard_setmode4 is parsed successfully */ +static void cmd_mechboard_setmode4_parsed(void *parsed_result, void *data) +{ + struct cmd_mechboard_setmode4_result *res = parsed_result; + i2c_mechboard_mode_autobuild(res->level_l, res->count_l, res->dist_l, + res->level_r, res->count_r, res->dist_r, + res->do_lintel); +} + +prog_char str_mechboard_setmode4_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_mechboard_setmode4_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode4_result, arg0, str_mechboard_setmode4_arg0); +prog_char str_mechboard_setmode4_arg1[] = "autobuild"; +parse_pgm_token_string_t cmd_mechboard_setmode4_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode4_result, arg1, str_mechboard_setmode4_arg1); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, level_l, UINT8); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, count_l, UINT8); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, dist_l, UINT8); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg5 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, level_r, UINT8); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg6 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, count_r, UINT8); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg7 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, dist_r, UINT8); +parse_pgm_token_num_t cmd_mechboard_setmode4_arg8 = TOKEN_NUM_INITIALIZER(struct cmd_mechboard_setmode4_result, do_lintel, UINT8); + +prog_char help_mechboard_setmode4[] = "set mechboard mode (autobuild level_l count_l dist_l level_r count_r dist_r lintel)"; +parse_pgm_inst_t cmd_mechboard_setmode4 = { + .f = cmd_mechboard_setmode4_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_mechboard_setmode4, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_mechboard_setmode4_arg0, + (prog_void *)&cmd_mechboard_setmode4_arg1, + (prog_void *)&cmd_mechboard_setmode4_arg2, + (prog_void *)&cmd_mechboard_setmode4_arg3, + (prog_void *)&cmd_mechboard_setmode4_arg4, + (prog_void *)&cmd_mechboard_setmode4_arg5, + (prog_void *)&cmd_mechboard_setmode4_arg6, + (prog_void *)&cmd_mechboard_setmode4_arg7, + (prog_void *)&cmd_mechboard_setmode4_arg8, + NULL, + }, +}; + +/**********************************************************/ +/* Mechboard_Setmode5 */ + +/* this structure is filled when cmd_mechboard_setmode5 is parsed successfully */ +struct cmd_mechboard_setmode5_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_mechboard_setmode5 is parsed successfully */ +static void cmd_mechboard_setmode5_parsed(void *parsed_result, void * data) +{ + struct cmd_mechboard_setmode5_result *res = parsed_result; + uint8_t side = I2C_LEFT_SIDE, next_mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + + if (!strcmp_P(res->arg2, PSTR("left"))) + side = I2C_LEFT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("right"))) + side = I2C_RIGHT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("center"))) + side = I2C_CENTER_SIDE; + else if (!strcmp_P(res->arg2, PSTR("auto"))) + side = I2C_AUTO_SIDE; + + if (!strcmp_P(res->arg3, PSTR("harvest"))) + next_mode = I2C_MECHBOARD_MODE_HARVEST; + else if (!strcmp_P(res->arg3, PSTR("lazy_harvest"))) + next_mode = I2C_MECHBOARD_MODE_LAZY_HARVEST; + else if (!strcmp_P(res->arg3, PSTR("pickup"))) + next_mode = I2C_MECHBOARD_MODE_PICKUP; + else if (!strcmp_P(res->arg3, PSTR("clear"))) + next_mode = I2C_MECHBOARD_MODE_CLEAR; + else if (!strcmp_P(res->arg3, PSTR("store"))) + next_mode = I2C_MECHBOARD_MODE_STORE; + else if (!strcmp_P(res->arg3, PSTR("lazy_pickup"))) + next_mode = I2C_MECHBOARD_MODE_LAZY_PICKUP; + + if (!strcmp_P(res->arg1, PSTR("prepare_pickup"))) + i2c_mechboard_mode_prepare_pickup_next(side, next_mode); +} + +prog_char str_mechboard_setmode5_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_mechboard_setmode5_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode5_result, arg0, str_mechboard_setmode5_arg0); +prog_char str_mechboard_setmode5_arg1[] = "prepare_pickup"; +parse_pgm_token_string_t cmd_mechboard_setmode5_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode5_result, arg1, str_mechboard_setmode5_arg1); +prog_char str_mechboard_setmode5_arg2[] = "left#right#auto#center"; +parse_pgm_token_string_t cmd_mechboard_setmode5_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode5_result, arg2, str_mechboard_setmode5_arg2); +prog_char str_mechboard_setmode5_arg3[] = "harvest#pickup#store#lazy_harvest#lazy_pickup#clear"; +parse_pgm_token_string_t cmd_mechboard_setmode5_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_mechboard_setmode5_result, arg3, str_mechboard_setmode5_arg3); + +prog_char help_mechboard_setmode5[] = "set mechboard mode (more, side)"; +parse_pgm_inst_t cmd_mechboard_setmode5 = { + .f = cmd_mechboard_setmode5_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_mechboard_setmode5, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_mechboard_setmode5_arg0, + (prog_void *)&cmd_mechboard_setmode5_arg1, + (prog_void *)&cmd_mechboard_setmode5_arg2, + (prog_void *)&cmd_mechboard_setmode5_arg3, + NULL, + }, +}; + +/**********************************************************/ +/* pickup wheels */ + +/* this structure is filled when cmd_pickup_wheels is parsed successfully */ +struct cmd_pickup_wheels_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_pickup_wheels is parsed successfully */ +static void cmd_pickup_wheels_parsed(void *parsed_result, void *data) +{ + struct cmd_pickup_wheels_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("on"))) + pickup_wheels_on(); + else + pickup_wheels_off(); +} + +prog_char str_pickup_wheels_arg0[] = "pickup_wheels"; +parse_pgm_token_string_t cmd_pickup_wheels_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pickup_wheels_result, arg0, str_pickup_wheels_arg0); +prog_char str_pickup_wheels_arg1[] = "on#off"; +parse_pgm_token_string_t cmd_pickup_wheels_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pickup_wheels_result, arg1, str_pickup_wheels_arg1); + +prog_char help_pickup_wheels[] = "Enable/disable pickup wheels"; +parse_pgm_inst_t cmd_pickup_wheels = { + .f = cmd_pickup_wheels_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pickup_wheels, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pickup_wheels_arg0, + (prog_void *)&cmd_pickup_wheels_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Beacon_Start */ + +/* this structure is filled when cmd_beacon_start is parsed successfully */ +struct cmd_beacon_start_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_beacon_start is parsed successfully */ +static void cmd_beacon_start_parsed(void *parsed_result, void *data) +{ + struct cmd_beacon_start_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("start"))) + i2c_sensorboard_set_beacon(1); + else + i2c_sensorboard_set_beacon(0); +} + +prog_char str_beacon_start_arg0[] = "beacon"; +parse_pgm_token_string_t cmd_beacon_start_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_beacon_start_result, arg0, str_beacon_start_arg0); +prog_char str_beacon_start_arg1[] = "start#stop"; +parse_pgm_token_string_t cmd_beacon_start_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_beacon_start_result, arg1, str_beacon_start_arg1); + +prog_char help_beacon_start[] = "Beacon enabled/disable"; +parse_pgm_inst_t cmd_beacon_start = { + .f = cmd_beacon_start_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_beacon_start, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_beacon_start_arg0, + (prog_void *)&cmd_beacon_start_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pump_Current */ + +/* this structure is filled when cmd_pump_current is parsed successfully */ +struct cmd_pump_current_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_pump_current is parsed successfully */ +static void cmd_pump_current_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + printf_P(PSTR("l1=%d l2=%d r1=%d r2=%d\r\n"), + sensor_get_adc(ADC_CSENSE3), sensor_get_adc(ADC_CSENSE4), + mechboard.pump_right1_current, mechboard.pump_right2_current); +} + +prog_char str_pump_current_arg0[] = "pump_current"; +parse_pgm_token_string_t cmd_pump_current_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pump_current_result, arg0, str_pump_current_arg0); +prog_char str_pump_current_arg1[] = "show"; +parse_pgm_token_string_t cmd_pump_current_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pump_current_result, arg1, str_pump_current_arg1); + +prog_char help_pump_current[] = "dump pump current"; +parse_pgm_inst_t cmd_pump_current = { + .f = cmd_pump_current_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pump_current, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pump_current_arg0, + (prog_void *)&cmd_pump_current_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Build_Test */ + +/* this structure is filled when cmd_build_test is parsed successfully */ +struct cmd_build_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_build_test is parsed successfully */ +static void cmd_build_test_parsed(void *parsed_result, void *data) +{ + //struct cmd_build_test_result *res = parsed_result; + + printf_P(PSTR("lintel must be there\r\n")); + i2c_mechboard_mode_prepare_pickup_next(I2C_LEFT_SIDE, + I2C_MECHBOARD_MODE_HARVEST); + wait_ms(500); + + printf_P(PSTR("Insert 4 colums\r\n")); + while (get_column_count() != 4); + + i2c_mechboard_mode_prepare_build_both(0); + trajectory_d_rel(&mainboard.traj, 200); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + wait_ms(500); + + i2c_mechboard_mode_simple_autobuild(0); + wait_ms(100); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + trajectory_d_rel(&mainboard.traj, -200); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + i2c_mechboard_mode_prepare_pickup_next(I2C_LEFT_SIDE, + I2C_MECHBOARD_MODE_HARVEST); + + while (get_column_count() != 3); + + i2c_mechboard_mode_prepare_build_both(3); + trajectory_d_rel(&mainboard.traj, 200); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + wait_ms(500); + + i2c_mechboard_mode_autobuild(3, 1, I2C_AUTOBUILD_DEFAULT_DIST, + 3, 2,I2C_AUTOBUILD_DEFAULT_DIST, 0); + i2cproto_wait_update(); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + trajectory_d_rel(&mainboard.traj, -200); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + i2c_mechboard_mode_prepare_pickup(I2C_RIGHT_SIDE); + wait_ms(500); + + i2c_mechboard_mode_harvest(); + while (get_column_count() != 3); + + i2c_mechboard_mode_prepare_build_both(5); + trajectory_d_rel(&mainboard.traj, 200); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + wait_ms(1000); + + i2c_mechboard_mode_autobuild(4, 2, I2C_AUTOBUILD_DEFAULT_DIST, + 5, 1, I2C_AUTOBUILD_DEFAULT_DIST, 0); + i2cproto_wait_update(); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + trajectory_d_rel(&mainboard.traj, -200); +} + +prog_char str_build_test_arg0[] = "build_test"; +parse_pgm_token_string_t cmd_build_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_build_test_result, arg0, str_build_test_arg0); + +prog_char help_build_test[] = "Build_Test function"; +parse_pgm_inst_t cmd_build_test = { + .f = cmd_build_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_build_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_build_test_arg0, + NULL, + }, +}; + + +/**********************************************************/ +/* Column_Test */ + +/* this structure is filled when cmd_column_test is parsed successfully */ +struct cmd_column_test_result { + fixed_string_t arg0; + uint8_t level; + int16_t dist; + int8_t a1; + int8_t a2; + int8_t a3; + int16_t arm_dist; + int8_t nb_col; +}; + +/* function called when cmd_column_test is parsed successfully */ +static void cmd_column_test_parsed(void *parsed_result, void *data) +{ + struct cmd_column_test_result *res = parsed_result; + uint8_t level = res->level, debug = 0; + uint8_t c, push = 0; + + /* default conf */ + if (data) { + res->dist = 70; + res->a1 = -20; + res->a2 = 40; + res->a3 = -20; + res->arm_dist = 220; + res->nb_col = 2; + } + + if (!strcmp_P(res->arg0, PSTR("column_test_debug"))) + debug = 1; + if (!strcmp_P(res->arg0, PSTR("column_test_push"))) + push = 1; + + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_VERY_SLOW); + + /* Go to disc */ + + trajectory_d_rel(&mainboard.traj, 200); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + /* go back, insert colums */ + + trajectory_d_rel(&mainboard.traj, -200); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + + i2c_mechboard_mode_prepare_pickup_next(I2C_LEFT_SIDE, + I2C_MECHBOARD_MODE_HARVEST); + printf_P(PSTR("Insert 4 colums\r\n")); + while (get_column_count() != 4); + + /* build with left arm */ + + i2c_mechboard_mode_prepare_inside_both(level); + trajectory_d_rel(&mainboard.traj, 200-(res->dist)); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + + if (debug) + c = cmdline_getchar_wait(); + + trajectory_a_rel(&mainboard.traj, res->a1); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + + if (debug) + c = cmdline_getchar_wait(); + + i2c_mechboard_mode_prepare_build_select(level, -1); + time_wait_ms(200); + if (debug) + c = cmdline_getchar_wait(); + i2c_mechboard_mode_autobuild(level, res->nb_col, res->arm_dist, + 0, 0, res->arm_dist, 0); + while (get_mechboard_mode() != I2C_MECHBOARD_MODE_AUTOBUILD); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + if (debug) + c = cmdline_getchar_wait(); + i2c_mechboard_mode_prepare_inside_select(level+res->nb_col, -1); + + if (debug) + c = cmdline_getchar_wait(); + /* build with right arm */ + + trajectory_a_rel(&mainboard.traj, res->a2); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + + if (debug) + c = cmdline_getchar_wait(); + /* only ok for nb_col == 2 */ + if ((level + res->nb_col) >= 7) + i2c_mechboard_mode_prepare_build_select(-1, level + res->nb_col + 1); + else + i2c_mechboard_mode_prepare_build_select(-1, level + res->nb_col); + time_wait_ms(200); + if (debug) + c = cmdline_getchar_wait(); + i2c_mechboard_mode_autobuild(0, 0, res->arm_dist, + level + res->nb_col, res->nb_col, + res->arm_dist, 0); + while (get_mechboard_mode() != I2C_MECHBOARD_MODE_AUTOBUILD); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + + if (push) { + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple_disc(I2C_RIGHT_SIDE); + time_wait_ms(500); + trajectory_d_rel(&mainboard.traj, 100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + else if (level == 1 || level == 0) { + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple(level); + time_wait_ms(400); + strat_set_speed(200, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 120); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + if (debug) + c = cmdline_getchar_wait(); + i2c_mechboard_mode_prepare_inside_select(-1, level+res->nb_col*2); + + if (debug) + c = cmdline_getchar_wait(); + + trajectory_a_rel(&mainboard.traj, res->a3); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + + if (debug) + c = cmdline_getchar_wait(); + /* go back, insert colums */ + + trajectory_d_rel(&mainboard.traj, -100); + + return; +} + +prog_char str_column_test_arg0[] = "column_test#column_test_debug#column_test_push"; +parse_pgm_token_string_t cmd_column_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_column_test_result, arg0, str_column_test_arg0); +parse_pgm_token_num_t cmd_column_test_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, level, UINT8); + +prog_char help_column_test[] = "Column_Test function (level)"; +parse_pgm_inst_t cmd_column_test = { + .f = cmd_column_test_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_column_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_column_test_arg0, + (prog_void *)&cmd_column_test_arg1, + NULL, + }, +}; + +parse_pgm_token_num_t cmd_column_test_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, dist, INT16); +parse_pgm_token_num_t cmd_column_test_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, a1, INT8); +parse_pgm_token_num_t cmd_column_test_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, a2, INT8); +parse_pgm_token_num_t cmd_column_test_arg5 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, a3, INT8); +parse_pgm_token_num_t cmd_column_test_arg6 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, arm_dist, INT16); +parse_pgm_token_num_t cmd_column_test_arg7 = TOKEN_NUM_INITIALIZER(struct cmd_column_test_result, nb_col, INT8); + +prog_char help_column_test2[] = "Column_Test function (level, dist, a1, a2, a3, arm_dist, nb_col)"; +parse_pgm_inst_t cmd_column_test2 = { + .f = cmd_column_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_column_test2, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_column_test_arg0, + (prog_void *)&cmd_column_test_arg1, + (prog_void *)&cmd_column_test_arg2, + (prog_void *)&cmd_column_test_arg3, + (prog_void *)&cmd_column_test_arg4, + (prog_void *)&cmd_column_test_arg5, + (prog_void *)&cmd_column_test_arg6, + (prog_void *)&cmd_column_test_arg7, + NULL, + }, +}; + + +/**********************************************************/ +/* Pickup_Test */ + +/* this structure is filled when cmd_pickup_test is parsed successfully */ +struct cmd_pickup_test_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t dist; +}; + +/* return red or green sensor */ +#define COLOR_IR_SENSOR() \ + ({ \ + uint8_t __ret = 0; \ + if (side == I2C_RIGHT_SIDE) \ + __ret = sensor_get(S_DISP_RIGHT); \ + else \ + __ret = sensor_get(S_DISP_LEFT); \ + __ret; \ + }) \ +/* column dispensers */ +#define COL_SCAN_MARGIN 200 +/* distance between the wheel axis and the IR sensor */ + +/* function called when cmd_pickup_test is parsed successfully */ +static void cmd_pickup_test_parsed(void *parsed_result, void *data) +{ + uint8_t err, side, first_try = 1; + int8_t cols_count_before, cols_count_after, cols; + struct cmd_pickup_test_result *res = parsed_result; + int16_t pos1, pos2, pos; + microseconds us; + int16_t dist = res->dist; + uint8_t timeout = 0; + + if (!strcmp_P(res->arg1, PSTR("left"))) + side = I2C_LEFT_SIDE; + else + side = I2C_RIGHT_SIDE; + + i2c_mechboard_mode_prepare_pickup(I2C_AUTO_SIDE); + cols_count_before = get_column_count(); + position_set(&mainboard.pos, 0, 0, 0); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -1000); + err = WAIT_COND_OR_TRAJ_END(!COLOR_IR_SENSOR(), TRAJ_FLAGS_NO_NEAR); + if (err) /* we should not reach end */ + goto fail; + pos1 = position_get_x_s16(&mainboard.pos); + printf_P(PSTR("pos1 = %d\r\n"), pos1); + + err = WAIT_COND_OR_TRAJ_END(COLOR_IR_SENSOR(), TRAJ_FLAGS_NO_NEAR); + if (err) + goto fail; + pos2 = position_get_x_s16(&mainboard.pos); + printf_P(PSTR("pos2 = %d\r\n"), pos2); + + pos = ABS(pos1 - pos2); + printf_P(PSTR("pos = %d\r\n"), pos); + + trajectory_d_rel(&mainboard.traj, -dist + pos/2); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + if (side == I2C_LEFT_SIDE) + trajectory_a_rel(&mainboard.traj, 90); + else + trajectory_a_rel(&mainboard.traj, -90); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + pickup_wheels_on(); + retry: + if (first_try) + i2c_mechboard_mode_lazy_harvest(); + else + i2c_mechboard_mode_prepare_pickup(I2C_AUTO_SIDE); + first_try = 0; + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, 300); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST | END_NEAR); + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + err = strat_calib(600, TRAJ_FLAGS_SMALL_DIST); + + trajectory_d_rel(&mainboard.traj, -DIST_BACK_DISPENSER); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + goto fail; + + position_set(&mainboard.pos, 0, 0, 0); + if (get_mechboard_mode() == I2C_MECHBOARD_MODE_PREPARE_EJECT) { + strat_eject_col(90, 0); + goto retry; + } + + /* start to pickup with finger / arms */ + + printf_P(PSTR("%s pickup now\r\n"), __FUNCTION__); + i2c_mechboard_mode_pickup(); + WAIT_COND_OR_TIMEOUT(get_mechboard_mode() == + I2C_MECHBOARD_MODE_PICKUP, 100); + us = time_get_us2(); + cols = get_column_count(); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_PICKUP) { + if (get_column_count() != cols) { + cols = get_column_count(); + us = time_get_us2(); + } + if ((get_column_count() - cols_count_before) >= 4) { + printf_P(PSTR("%s no more cols in disp\r\n"), __FUNCTION__); + break; + } + /* 1 second timeout */ + if (time_get_us2() - us > 1500000L) { + printf_P(PSTR("%s timeout\r\n"), __FUNCTION__); + timeout = 1; + break; + } + } + + /* eject if we found a bad color column */ + + if (get_mechboard_mode() == I2C_MECHBOARD_MODE_PREPARE_EJECT) { + strat_eject_col(90, 0); + goto retry; + } + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -250); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST | END_NEAR); + + cols_count_after = get_column_count(); + cols = cols_count_after - cols_count_before; + DEBUG(E_USER_STRAT, "%s we got %d cols", __FUNCTION__, cols); + + pickup_wheels_off(); + i2c_mechboard_mode_clear(); + + wait_ms(1000); + return; + fail: + printf_P(PSTR("failed\r\n")); + strat_hardstop(); +} + +prog_char str_pickup_test_arg0[] = "pickup_test"; +parse_pgm_token_string_t cmd_pickup_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pickup_test_result, arg0, str_pickup_test_arg0); +prog_char str_pickup_test_arg1[] = "left#right"; +parse_pgm_token_string_t cmd_pickup_test_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pickup_test_result, arg1, str_pickup_test_arg1); +parse_pgm_token_num_t cmd_pickup_test_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pickup_test_result, dist, INT16); + +prog_char help_pickup_test[] = "Pickup_Test function"; +parse_pgm_inst_t cmd_pickup_test = { + .f = cmd_pickup_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pickup_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pickup_test_arg0, + (prog_void *)&cmd_pickup_test_arg1, + (prog_void *)&cmd_pickup_test_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Lintel_Test */ + +/* this structure is filled when cmd_lintel_test is parsed successfully */ +struct cmd_lintel_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_lintel_test is parsed successfully */ +static void cmd_lintel_test_parsed(void *parsed_result, void *data) +{ + uint8_t err, first_try = 1, right_ok, left_ok; + int16_t left_cur, right_cur; + + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(500); + retry: + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, 500); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err) && err != END_BLOCKING) + goto fail; + + i2c_mechboard_mode_get_lintel(); + time_wait_ms(500); + + left_cur = sensor_get_adc(ADC_CSENSE3); + left_ok = (left_cur > I2C_MECHBOARD_CURRENT_COLUMN); + right_cur = mechboard.pump_right1_current; + right_ok = (right_cur > I2C_MECHBOARD_CURRENT_COLUMN); + + printf_P(PSTR("left_ok=%d (%d), right_ok=%d (%d)\r\n"), + left_ok, left_cur, right_ok, right_cur); + if (first_try) { + if (!right_ok && !left_ok) { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + } + else if (right_ok && !left_ok) { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + strat_set_speed(500, 500); + trajectory_d_a_rel(&mainboard.traj, -150, 30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + trajectory_d_a_rel(&mainboard.traj, -140, -30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + first_try = 0; + goto retry; + } + else if (!right_ok && left_ok) { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + strat_set_speed(500, 500); + trajectory_d_a_rel(&mainboard.traj, -150, -30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + trajectory_d_a_rel(&mainboard.traj, -140, 30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + first_try = 0; + goto retry; + } + /* else, lintel is ok */ + else { + i2c_mechboard_mode_put_lintel(); + } + } + else { + if (right_ok && left_ok) { + /* lintel is ok */ + i2c_mechboard_mode_put_lintel(); + } + else { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + } + } + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -250); + err = wait_traj_end(TRAJ_FLAGS_STD); + return; + +fail: + printf_P(PSTR("fail\r\n")); + return; +} + +prog_char str_lintel_test_arg0[] = "lintel_test"; +parse_pgm_token_string_t cmd_lintel_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_lintel_test_result, arg0, str_lintel_test_arg0); + +prog_char help_lintel_test[] = "Lintel_Test function"; +parse_pgm_inst_t cmd_lintel_test = { + .f = cmd_lintel_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_lintel_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_lintel_test_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Scan_Test */ + +/* this structure is filled when cmd_scan_test is parsed successfully */ +struct cmd_scan_test_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t start_dist; + int16_t scan_dist; + int16_t scan_speed; + int16_t center_x; + int16_t center_y; + uint8_t level; +}; + +#define SCAN_MODE_CHECK_TEMPLE 0 +#define SCAN_MODE_SCAN_COL 1 +#define SCAN_MODE_SCAN_TEMPLE 2 +#define SCAN_MODE_TRAJ_ONLY 3 + +/* function called when cmd_scan_test is parsed successfully */ +static void cmd_scan_test_parsed(void *parsed_result, void *data) +{ + uint8_t err, mode=0, c; + int16_t pos1x, pos1y, dist; + struct cmd_scan_test_result *res = parsed_result; + int16_t back_mm = 0; + + int16_t ckpt_rel_x = 0, ckpt_rel_y = 0; + + double center_abs_x, center_abs_y; + double ckpt_rel_d, ckpt_rel_a; + double ckpt_abs_x, ckpt_abs_y; + + if (!strcmp_P(res->arg1, PSTR("traj_only"))) + mode = SCAN_MODE_TRAJ_ONLY; + else if (!strcmp_P(res->arg1, PSTR("check_temple"))) + mode = SCAN_MODE_CHECK_TEMPLE; + else if (!strcmp_P(res->arg1, PSTR("scan_col"))) + mode = SCAN_MODE_SCAN_COL; + else if (!strcmp_P(res->arg1, PSTR("scan_temple"))) + mode = SCAN_MODE_SCAN_TEMPLE; + + /* go to disc */ + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_VERY_SLOW); + trajectory_d_rel(&mainboard.traj, 400); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (err != END_BLOCKING) + return; + + /* save absolute position of disc */ + rel_da_to_abs_xy(265, 0, ¢er_abs_x, ¢er_abs_y); + + /* go back and prepare to scan */ + strat_set_speed(1000, 1000); + trajectory_d_a_rel(&mainboard.traj, -140, 130); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + return; + + /* prepare scanner arm */ + if (mode != SCAN_MODE_TRAJ_ONLY) + i2c_sensorboard_scanner_prepare(); + time_wait_ms(250); + + strat_set_speed(res->scan_speed, 1000); + + pos1x = position_get_x_s16(&mainboard.pos); + pos1y = position_get_y_s16(&mainboard.pos); + trajectory_d_rel(&mainboard.traj, -res->scan_dist); + + while (1) { + err = test_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (err != 0) + break; + + dist = distance_from_robot(pos1x, pos1y); + + if (dist > res->start_dist) + break; + + if (get_scanner_status() & I2C_SCAN_MAX_COLUMN) { + err = END_ERROR; + break; + } + } + + if (err) { + if (TRAJ_SUCCESS(err)) + err = END_ERROR; /* should not reach end */ + strat_hardstop(); + trajectory_goto_xy_abs(&mainboard.traj, pos1x, pos1y); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (mode != SCAN_MODE_TRAJ_ONLY) + i2c_sensorboard_scanner_stop(); + return; + } + + /* start the scanner */ + + if (mode != SCAN_MODE_TRAJ_ONLY) + i2c_sensorboard_scanner_start(); + + err = WAIT_COND_OR_TRAJ_END(get_scanner_status() & I2C_SCAN_MAX_COLUMN, + TRAJ_FLAGS_NO_NEAR); + if (err == 0) + err = END_ERROR; + if (!TRAJ_SUCCESS(err)) { + strat_hardstop(); + trajectory_goto_xy_abs(&mainboard.traj, pos1x, pos1y); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (mode != SCAN_MODE_TRAJ_ONLY) + i2c_sensorboard_scanner_stop(); + return; + } + + if (mode == SCAN_MODE_TRAJ_ONLY) + return; + + wait_scan_done(10000); + + i2c_sensorboard_scanner_stop(); + + if (mode == SCAN_MODE_CHECK_TEMPLE) { + i2c_sensorboard_scanner_algo_check(res->level, + res->center_x, res->center_y); + i2cproto_wait_update(); + wait_scan_done(10000); + scanner_dump_state(); + + if (sensorboard.dropzone_h == -1) { + printf_P(PSTR("-- try to build a temple\r\n")); + res->center_x = 15; + res->center_y = 13; + mode = SCAN_MODE_SCAN_TEMPLE; + } + } + + if (mode == SCAN_MODE_SCAN_TEMPLE) { + i2c_sensorboard_scanner_algo_temple(I2C_SCANNER_ZONE_DISC, + res->center_x, + res->center_y); + i2cproto_wait_update(); + wait_scan_done(10000); + scanner_dump_state(); + + if (sensorboard.dropzone_h == -1 || + strat_scan_get_checkpoint(mode, &ckpt_rel_x, + &ckpt_rel_y, &back_mm)) { + printf_P(PSTR("-- try to build a column\r\n")); + mode = SCAN_MODE_SCAN_COL; + } + } + + if (mode == SCAN_MODE_SCAN_COL) { + i2c_sensorboard_scanner_algo_column(I2C_SCANNER_ZONE_DISC, + res->center_x, res->center_y); + i2cproto_wait_update(); + wait_scan_done(10000); + scanner_dump_state(); + + if (sensorboard.dropzone_h == -1 || + strat_scan_get_checkpoint(mode, &ckpt_rel_x, + &ckpt_rel_y, &back_mm)) { + return; + } + } + + if (sensorboard.dropzone_h == -1) + return; + + if (mode == SCAN_MODE_CHECK_TEMPLE) { + ckpt_rel_x = 220; + ckpt_rel_y = 100; + } + + + printf_P(PSTR("rel xy for ckpt is %d,%d\r\n"), ckpt_rel_x, ckpt_rel_y); + + rel_xy_to_abs_xy(ckpt_rel_x, ckpt_rel_y, &ckpt_abs_x, &ckpt_abs_y); + abs_xy_to_rel_da(ckpt_abs_x, ckpt_abs_y, &ckpt_rel_d, &ckpt_rel_a); + + printf_P(PSTR("abs ckpt is %2.2f,%2.2f\r\n"), ckpt_abs_x, ckpt_abs_y); + + printf_P(PSTR("ok ? (y/n)\r\n")); + + c = cmdline_getchar_wait(); + + if (c != 'y') + return; + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + /* intermediate checkpoint for some positions */ + if ( (DEG(ckpt_rel_a) < 0 && DEG(ckpt_rel_a) > -90) ) { + trajectory_goto_xy_rel(&mainboard.traj, 200, 100); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + return; + } + + trajectory_goto_xy_abs(&mainboard.traj, ckpt_abs_x, ckpt_abs_y); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + return; + + trajectory_turnto_xy(&mainboard.traj, center_abs_x, center_abs_y); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + return; + + c = cmdline_getchar_wait(); + + pos1x = position_get_x_s16(&mainboard.pos); + pos1y = position_get_y_s16(&mainboard.pos); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 200); + err = WAIT_COND_OR_TRAJ_END(distance_from_robot(pos1x, pos1y) > 200, + TRAJ_FLAGS_SMALL_DIST); + if (err == 0) { + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_VERY_SLOW); + trajectory_d_rel(&mainboard.traj, 400); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + if (err != END_BLOCKING) + return; + + if (back_mm) { + trajectory_d_rel(&mainboard.traj, -back_mm); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } +} + +prog_char str_scan_test_arg0[] = "scan_test"; +parse_pgm_token_string_t cmd_scan_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scan_test_result, arg0, str_scan_test_arg0); +prog_char str_scan_test_arg1[] = "traj_only#scan_col#scan_temple"; +parse_pgm_token_string_t cmd_scan_test_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scan_test_result, arg1, str_scan_test_arg1); +parse_pgm_token_num_t cmd_scan_test_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_scan_test_result, start_dist, INT16); +parse_pgm_token_num_t cmd_scan_test_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_scan_test_result, scan_dist, INT16); +parse_pgm_token_num_t cmd_scan_test_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_scan_test_result, scan_speed, INT16); +parse_pgm_token_num_t cmd_scan_test_arg5 = TOKEN_NUM_INITIALIZER(struct cmd_scan_test_result, center_x, INT16); +parse_pgm_token_num_t cmd_scan_test_arg6 = TOKEN_NUM_INITIALIZER(struct cmd_scan_test_result, center_y, INT16); + +prog_char help_scan_test[] = "Scan_Test function (start_dist, scan_dist, speed_dist, centerx, centery)"; +parse_pgm_inst_t cmd_scan_test = { + .f = cmd_scan_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scan_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scan_test_arg0, + (prog_void *)&cmd_scan_test_arg1, + (prog_void *)&cmd_scan_test_arg2, + (prog_void *)&cmd_scan_test_arg3, + (prog_void *)&cmd_scan_test_arg4, + (prog_void *)&cmd_scan_test_arg5, + (prog_void *)&cmd_scan_test_arg6, + NULL, + }, +}; + +prog_char str_scan_test_arg1b[] = "check_temple"; +parse_pgm_token_string_t cmd_scan_test_arg1b = TOKEN_STRING_INITIALIZER(struct cmd_scan_test_result, arg1, str_scan_test_arg1b); +parse_pgm_token_num_t cmd_scan_test_arg7 = TOKEN_NUM_INITIALIZER(struct cmd_scan_test_result, level, UINT8); + +prog_char help_scan_test2[] = "Scan_Test function (start_dist, scan_dist, speed_dist, templex, templey, level)"; +parse_pgm_inst_t cmd_scan_test2 = { + .f = cmd_scan_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scan_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scan_test_arg0, + (prog_void *)&cmd_scan_test_arg1b, + (prog_void *)&cmd_scan_test_arg2, + (prog_void *)&cmd_scan_test_arg3, + (prog_void *)&cmd_scan_test_arg4, + (prog_void *)&cmd_scan_test_arg5, + (prog_void *)&cmd_scan_test_arg6, + (prog_void *)&cmd_scan_test_arg7, + NULL, + }, +}; + +/**********************************************************/ +/* Time_Monitor */ + +/* this structure is filled when cmd_time_monitor is parsed successfully */ +struct cmd_time_monitor_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_time_monitor is parsed successfully */ +static void cmd_time_monitor_parsed(void *parsed_result, void *data) +{ + struct cmd_time_monitor_result *res = parsed_result; + uint16_t seconds; + + if (!strcmp_P(res->arg1, PSTR("reset"))) { + eeprom_write_word(EEPROM_TIME_ADDRESS, 0); + } + seconds = eeprom_read_word(EEPROM_TIME_ADDRESS); + printf_P(PSTR("Running since %d mn %d\r\n"), seconds/60, seconds%60); +} + +prog_char str_time_monitor_arg0[] = "time_monitor"; +parse_pgm_token_string_t cmd_time_monitor_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_time_monitor_result, arg0, str_time_monitor_arg0); +prog_char str_time_monitor_arg1[] = "show#reset"; +parse_pgm_token_string_t cmd_time_monitor_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_time_monitor_result, arg1, str_time_monitor_arg1); + +prog_char help_time_monitor[] = "Show since how long we are running"; +parse_pgm_inst_t cmd_time_monitor = { + .f = cmd_time_monitor_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_time_monitor, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_time_monitor_arg0, + (prog_void *)&cmd_time_monitor_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Scanner */ + +/* this structure is filled when cmd_scanner is parsed successfully */ +struct cmd_scanner_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_scanner is parsed successfully */ +static void cmd_scanner_parsed(void *parsed_result, void *data) +{ + struct cmd_scanner_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("prepare"))) { + i2c_sensorboard_scanner_prepare(); + } + else if (!strcmp_P(res->arg1, PSTR("stop"))) { + i2c_sensorboard_scanner_stop(); + } + else if (!strcmp_P(res->arg1, PSTR("start"))) { + i2c_sensorboard_scanner_start(); + } + else if (!strcmp_P(res->arg1, PSTR("algo_col"))) { + i2c_sensorboard_scanner_algo_column(I2C_SCANNER_ZONE_DISC, + 15, 15); + } + else if (!strcmp_P(res->arg1, PSTR("algo_check"))) { + i2c_sensorboard_scanner_algo_check(2, 15, 15); // XXX + } + else if (!strcmp_P(res->arg1, PSTR("calib"))) { + i2c_sensorboard_scanner_calib(); + } + else if (!strcmp_P(res->arg1, PSTR("show"))) { + scanner_dump_state(); + } +} + +prog_char str_scanner_arg0[] = "scanner"; +parse_pgm_token_string_t cmd_scanner_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scanner_result, arg0, str_scanner_arg0); +prog_char str_scanner_arg1[] = "prepare#start#algo_col#algo_check#stop#show#calib"; +parse_pgm_token_string_t cmd_scanner_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scanner_result, arg1, str_scanner_arg1); + +prog_char help_scanner[] = "send commands to scanner"; +parse_pgm_inst_t cmd_scanner = { + .f = cmd_scanner_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scanner, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scanner_arg0, + (prog_void *)&cmd_scanner_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Build_Z1 */ + +/* this structure is filled when cmd_build_z1 is parsed successfully */ +struct cmd_build_z1_result { + fixed_string_t arg0; + uint8_t level; + int16_t d1; + int16_t d2; + int16_t d3; +}; + +/* function called when cmd_build_z1 is parsed successfully */ +static void cmd_build_z1_parsed(void *parsed_result, void *data) +{ + struct cmd_build_z1_result *res = parsed_result; + + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 400); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + trajectory_d_rel(&mainboard.traj, -200); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + i2c_mechboard_mode_prepare_pickup_next(I2C_LEFT_SIDE, + I2C_MECHBOARD_MODE_HARVEST); + + while (get_column_count() != 4); + + i2c_mechboard_mode_prepare_build_both(res->level); + time_wait_ms(500); + + trajectory_d_rel(&mainboard.traj, 400); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, -res->d1); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_autobuild(res->level, 2, I2C_AUTOBUILD_DEFAULT_DIST, + res->level, 2, I2C_AUTOBUILD_DEFAULT_DIST, + 1); + WAIT_COND_OR_TIMEOUT(get_mechboard_mode() == + I2C_MECHBOARD_MODE_AUTOBUILD, 100); + WAIT_COND_OR_TIMEOUT(get_mechboard_mode() != + I2C_MECHBOARD_MODE_AUTOBUILD, 10000); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, -res->d2); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple(1); + time_wait_ms(400); + strat_set_speed(200, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, res->d3); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); +} + +prog_char str_build_z1_arg0[] = "build_z1"; +parse_pgm_token_string_t cmd_build_z1_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_build_z1_result, arg0, str_build_z1_arg0); +parse_pgm_token_num_t cmd_build_z1_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_build_z1_result, level, UINT8); +parse_pgm_token_num_t cmd_build_z1_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_build_z1_result, d1, INT16); +parse_pgm_token_num_t cmd_build_z1_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_build_z1_result, d2, INT16); +parse_pgm_token_num_t cmd_build_z1_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_build_z1_result, d3, INT16); + +prog_char help_build_z1[] = "Build_Z1 function (level, d1, d2, d3)"; +parse_pgm_inst_t cmd_build_z1 = { + .f = cmd_build_z1_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_build_z1, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_build_z1_arg0, + (prog_void *)&cmd_build_z1_arg1, + (prog_void *)&cmd_build_z1_arg2, + (prog_void *)&cmd_build_z1_arg3, + (prog_void *)&cmd_build_z1_arg4, + NULL, + }, +}; + +#ifdef TEST_BEACON +/**********************************************************/ +/* Beacon_Opp_Dump */ + +/* this structure is filled when cmd_beacon_opp_dump is parsed successfully */ +struct cmd_beacon_opp_dump_result { + fixed_string_t arg0; +}; + +void beacon_dump_samples(void); + +/* function called when cmd_beacon_opp_dump is parsed successfully */ +static void cmd_beacon_opp_dump_parsed(void *parsed_result, void *data) +{ + beacon_dump_samples(); +} + +prog_char str_beacon_opp_dump_arg0[] = "beacon_opp_dump"; +parse_pgm_token_string_t cmd_beacon_opp_dump_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_beacon_opp_dump_result, arg0, str_beacon_opp_dump_arg0); + +prog_char help_beacon_opp_dump[] = "Dump beacon samples"; +parse_pgm_inst_t cmd_beacon_opp_dump = { + .f = cmd_beacon_opp_dump_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_beacon_opp_dump, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_beacon_opp_dump_arg0, + NULL, + }, +}; +#endif + +/**********************************************************/ +/* Test */ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_test_result { + fixed_string_t arg0; + int32_t radius; +}; +void circle_get_da_speed_from_radius(struct trajectory *traj, + double radius_mm, + double *speed_d, + double *speed_a); +/* function called when cmd_test is parsed successfully */ +static void cmd_test_parsed(void *parsed_result, void *data) +{ + struct cmd_test_result *res = parsed_result; + double d,a; + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + circle_get_da_speed_from_radius(&mainboard.traj, res->radius, &d, &a); + printf_P(PSTR("d=%2.2f a=%2.2f\r\n"), d, a); +} + +prog_char str_test_arg0[] = "test"; +parse_pgm_token_string_t cmd_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_test_result, arg0, str_test_arg0); +parse_pgm_token_num_t cmd_test_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_test_result, radius, INT32); + +prog_char help_test[] = "Test function"; +parse_pgm_inst_t cmd_test = { + .f = cmd_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_test_arg0, + (prog_void *)&cmd_test_arg1, + NULL, + }, +}; diff --git a/projects/microb2009/mainboard/commands_traj.c b/projects/microb2009/mainboard/commands_traj.c new file mode 100644 index 0000000..f3b38fd --- /dev/null +++ b/projects/microb2009/mainboard/commands_traj.c @@ -0,0 +1,1146 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_traj.c,v 1.8 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> +#include <encoders_spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "cs.h" +#include "cmdline.h" +#include "strat_utils.h" +#include "strat_base.h" +#include "strat_avoid.h" +#include "strat.h" +#include "../common/i2c_commands.h" +#include "i2c_protocol.h" + +/**********************************************************/ +/* Traj_Speeds for trajectory_manager */ + +/* this structure is filled when cmd_traj_speed is parsed successfully */ +struct cmd_traj_speed_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint16_t s; +}; + +/* function called when cmd_traj_speed is parsed successfully */ +static void cmd_traj_speed_parsed(void *parsed_result, void *data) +{ + struct cmd_traj_speed_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("angle"))) { + trajectory_set_speed(&mainboard.traj, mainboard.traj.d_speed, res->s); + } + else if (!strcmp_P(res->arg1, PSTR("distance"))) { + trajectory_set_speed(&mainboard.traj, res->s, mainboard.traj.a_speed); + } + /* else it is a "show" */ + + printf_P(PSTR("angle %u, distance %u\r\n"), + mainboard.traj.a_speed, + mainboard.traj.d_speed); +} + +prog_char str_traj_speed_arg0[] = "traj_speed"; +parse_pgm_token_string_t cmd_traj_speed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_traj_speed_result, arg0, str_traj_speed_arg0); +prog_char str_traj_speed_arg1[] = "angle#distance"; +parse_pgm_token_string_t cmd_traj_speed_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_traj_speed_result, arg1, str_traj_speed_arg1); +parse_pgm_token_num_t cmd_traj_speed_s = TOKEN_NUM_INITIALIZER(struct cmd_traj_speed_result, s, UINT16); + +prog_char help_traj_speed[] = "Set traj_speed values for trajectory manager"; +parse_pgm_inst_t cmd_traj_speed = { + .f = cmd_traj_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_traj_speed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_traj_speed_arg0, + (prog_void *)&cmd_traj_speed_arg1, + (prog_void *)&cmd_traj_speed_s, + NULL, + }, +}; + +/* show */ + +prog_char str_traj_speed_show_arg[] = "show"; +parse_pgm_token_string_t cmd_traj_speed_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_traj_speed_result, arg1, str_traj_speed_show_arg); + +prog_char help_traj_speed_show[] = "Show traj_speed values for trajectory manager"; +parse_pgm_inst_t cmd_traj_speed_show = { + .f = cmd_traj_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_traj_speed_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_traj_speed_arg0, + (prog_void *)&cmd_traj_speed_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* trajectory window configuration */ + +/* this structure is filled when cmd_trajectory is parsed successfully */ +struct cmd_trajectory_result { + fixed_string_t arg0; + fixed_string_t arg1; + float d_win; + float a_win; + float a_start; +}; + + +/* function called when cmd_trajectory is parsed successfully */ +static void cmd_trajectory_parsed(void * parsed_result, void * data) +{ + struct cmd_trajectory_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("set"))) { + trajectory_set_windows(&mainboard.traj, res->d_win, + res->a_win, res->a_start); + } + + printf_P(PSTR("trajectory %2.2f %2.2f %2.2f\r\n"), mainboard.traj.d_win, + DEG(mainboard.traj.a_win_rad), DEG(mainboard.traj.a_start_rad)); +} + +prog_char str_trajectory_arg0[] = "trajectory"; +parse_pgm_token_string_t cmd_trajectory_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_trajectory_result, arg0, str_trajectory_arg0); +prog_char str_trajectory_arg1[] = "set"; +parse_pgm_token_string_t cmd_trajectory_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_trajectory_result, arg1, str_trajectory_arg1); +parse_pgm_token_num_t cmd_trajectory_d = TOKEN_NUM_INITIALIZER(struct cmd_trajectory_result, d_win, FLOAT); +parse_pgm_token_num_t cmd_trajectory_a = TOKEN_NUM_INITIALIZER(struct cmd_trajectory_result, a_win, FLOAT); +parse_pgm_token_num_t cmd_trajectory_as = TOKEN_NUM_INITIALIZER(struct cmd_trajectory_result, a_start, FLOAT); + +prog_char help_trajectory[] = "Set trajectory windows (distance, angle, angle_start)"; +parse_pgm_inst_t cmd_trajectory = { + .f = cmd_trajectory_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_trajectory, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_trajectory_arg0, + (prog_void *)&cmd_trajectory_arg1, + (prog_void *)&cmd_trajectory_d, + (prog_void *)&cmd_trajectory_a, + (prog_void *)&cmd_trajectory_as, + NULL, + }, +}; + +/* show */ + +prog_char str_trajectory_show_arg[] = "show"; +parse_pgm_token_string_t cmd_trajectory_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_trajectory_result, arg1, str_trajectory_show_arg); + +prog_char help_trajectory_show[] = "Show trajectory window configuration"; +parse_pgm_inst_t cmd_trajectory_show = { + .f = cmd_trajectory_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_trajectory_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_trajectory_arg0, + (prog_void *)&cmd_trajectory_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* rs_gains configuration */ + +/* this structure is filled when cmd_rs_gains is parsed successfully */ +struct cmd_rs_gains_result { + fixed_string_t arg0; + fixed_string_t arg1; + float left; + float right; +}; + +/* function called when cmd_rs_gains is parsed successfully */ +static void cmd_rs_gains_parsed(void * parsed_result, void * data) +{ + struct cmd_rs_gains_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("set"))) { + rs_set_left_ext_encoder(&mainboard.rs, encoders_spi_get_value, + LEFT_ENCODER, res->left); // en augmentant on tourne à gauche + rs_set_right_ext_encoder(&mainboard.rs, encoders_spi_get_value, + RIGHT_ENCODER, res->right); //en augmentant on tourne à droite + } + printf_P(PSTR("rs_gains set ")); + f64_print(mainboard.rs.left_ext_gain); + printf_P(PSTR(" ")); + f64_print(mainboard.rs.right_ext_gain); + printf_P(PSTR("\r\n")); +} + +prog_char str_rs_gains_arg0[] = "rs_gains"; +parse_pgm_token_string_t cmd_rs_gains_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_rs_gains_result, arg0, str_rs_gains_arg0); +prog_char str_rs_gains_arg1[] = "set"; +parse_pgm_token_string_t cmd_rs_gains_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_rs_gains_result, arg1, str_rs_gains_arg1); +parse_pgm_token_num_t cmd_rs_gains_l = TOKEN_NUM_INITIALIZER(struct cmd_rs_gains_result, left, FLOAT); +parse_pgm_token_num_t cmd_rs_gains_r = TOKEN_NUM_INITIALIZER(struct cmd_rs_gains_result, right, FLOAT); + +prog_char help_rs_gains[] = "Set rs_gains (left, right)"; +parse_pgm_inst_t cmd_rs_gains = { + .f = cmd_rs_gains_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_rs_gains, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_rs_gains_arg0, + (prog_void *)&cmd_rs_gains_arg1, + (prog_void *)&cmd_rs_gains_l, + (prog_void *)&cmd_rs_gains_r, + NULL, + }, +}; + +/* show */ + +prog_char str_rs_gains_show_arg[] = "show"; +parse_pgm_token_string_t cmd_rs_gains_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_rs_gains_result, arg1, str_rs_gains_show_arg); + +prog_char help_rs_gains_show[] = "Show rs_gains"; +parse_pgm_inst_t cmd_rs_gains_show = { + .f = cmd_rs_gains_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_rs_gains_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_rs_gains_arg0, + (prog_void *)&cmd_rs_gains_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* track configuration */ + +/* this structure is filled when cmd_track is parsed successfully */ +struct cmd_track_result { + fixed_string_t arg0; + fixed_string_t arg1; + float val; +}; + +/* function called when cmd_track is parsed successfully */ +static void cmd_track_parsed(void * parsed_result, void * data) +{ + struct cmd_track_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("set"))) { + position_set_physical_params(&mainboard.pos, res->val, DIST_IMP_MM); + } + printf_P(PSTR("track set %f\r\n"), mainboard.pos.phys.track_mm); +} + +prog_char str_track_arg0[] = "track"; +parse_pgm_token_string_t cmd_track_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_track_result, arg0, str_track_arg0); +prog_char str_track_arg1[] = "set"; +parse_pgm_token_string_t cmd_track_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_track_result, arg1, str_track_arg1); +parse_pgm_token_num_t cmd_track_val = TOKEN_NUM_INITIALIZER(struct cmd_track_result, val, FLOAT); + +prog_char help_track[] = "Set track in mm"; +parse_pgm_inst_t cmd_track = { + .f = cmd_track_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_track, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_track_arg0, + (prog_void *)&cmd_track_arg1, + (prog_void *)&cmd_track_val, + NULL, + }, +}; + +/* show */ + +prog_char str_track_show_arg[] = "show"; +parse_pgm_token_string_t cmd_track_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_track_result, arg1, str_track_show_arg); + +prog_char help_track_show[] = "Show track"; +parse_pgm_inst_t cmd_track_show = { + .f = cmd_track_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_track_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_track_arg0, + (prog_void *)&cmd_track_show_arg, + NULL, + }, +}; + + + +/**********************************************************/ +/* Pt_Lists for testing traj */ + +#define PT_LIST_SIZE 10 +static struct xy_point pt_list[PT_LIST_SIZE]; +static uint16_t pt_list_len = 0; + +/* this structure is filled when cmd_pt_list is parsed successfully */ +struct cmd_pt_list_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint16_t arg2; + int16_t arg3; + int16_t arg4; +}; + +/* function called when cmd_pt_list is parsed successfully */ +static void cmd_pt_list_parsed(void * parsed_result, void * data) +{ + struct cmd_pt_list_result * res = parsed_result; + uint8_t i, why=0; + + if (!strcmp_P(res->arg1, PSTR("append"))) { + res->arg2 = pt_list_len; + } + + if (!strcmp_P(res->arg1, PSTR("insert")) || + !strcmp_P(res->arg1, PSTR("append"))) { + if (res->arg2 > pt_list_len) { + printf_P(PSTR("Index too large\r\n")); + return; + } + if (pt_list_len >= PT_LIST_SIZE) { + printf_P(PSTR("List is too large\r\n")); + return; + } + memmove(&pt_list[res->arg2+1], &pt_list[res->arg2], + PT_LIST_SIZE-1-res->arg2); + pt_list[res->arg2].x = res->arg3; + pt_list[res->arg2].y = res->arg4; + pt_list_len++; + } + else if (!strcmp_P(res->arg1, PSTR("del"))) { + if (pt_list_len <= 0) { + printf_P(PSTR("Error: list empty\r\n")); + return; + } + if (res->arg2 > pt_list_len) { + printf_P(PSTR("Index too large\r\n")); + return; + } + memmove(&pt_list[res->arg2], &pt_list[res->arg2+1], + (PT_LIST_SIZE-1-res->arg2)*sizeof(struct xy_point)); + pt_list_len--; + } + else if (!strcmp_P(res->arg1, PSTR("reset"))) { + pt_list_len = 0; + } + + /* else it is a "show" or a "start" */ + if (pt_list_len == 0) { + printf_P(PSTR("List empty\r\n")); + return; + } + for (i=0 ; i<pt_list_len ; i++) { + printf_P(PSTR("%d: x=%d y=%d\r\n"), i, pt_list[i].x, pt_list[i].y); + if (!strcmp_P(res->arg1, PSTR("start"))) { + trajectory_goto_xy_abs(&mainboard.traj, pt_list[i].x, pt_list[i].y); + why = wait_traj_end(0xFF); /* all */ + } + else if (!strcmp_P(res->arg1, PSTR("avoid_start"))) { + while (1) { + why = goto_and_avoid(pt_list[i].x, pt_list[i].y, 0xFF, 0xFF); + printf("next point\r\n"); + if (why != END_OBSTACLE) + break; + } + } + if (why & (~(END_TRAJ | END_NEAR))) + trajectory_stop(&mainboard.traj); + } +} + +prog_char str_pt_list_arg0[] = "pt_list"; +parse_pgm_token_string_t cmd_pt_list_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pt_list_result, arg0, str_pt_list_arg0); +prog_char str_pt_list_arg1[] = "insert"; +parse_pgm_token_string_t cmd_pt_list_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pt_list_result, arg1, str_pt_list_arg1); +parse_pgm_token_num_t cmd_pt_list_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pt_list_result, arg2, UINT16); +parse_pgm_token_num_t cmd_pt_list_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_pt_list_result, arg3, INT16); +parse_pgm_token_num_t cmd_pt_list_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_pt_list_result, arg4, INT16); + +prog_char help_pt_list[] = "Insert point in pt_list (idx,x,y)"; +parse_pgm_inst_t cmd_pt_list = { + .f = cmd_pt_list_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pt_list, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pt_list_arg0, + (prog_void *)&cmd_pt_list_arg1, + (prog_void *)&cmd_pt_list_arg2, + (prog_void *)&cmd_pt_list_arg3, + (prog_void *)&cmd_pt_list_arg4, + NULL, + }, +}; + +/* append */ + +prog_char str_pt_list_arg1_append[] = "append"; +parse_pgm_token_string_t cmd_pt_list_arg1_append = TOKEN_STRING_INITIALIZER(struct cmd_pt_list_result, arg1, str_pt_list_arg1_append); + +prog_char help_pt_list_append[] = "Append point in pt_list (x,y)"; +parse_pgm_inst_t cmd_pt_list_append = { + .f = cmd_pt_list_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pt_list_append, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pt_list_arg0, + (prog_void *)&cmd_pt_list_arg1_append, + (prog_void *)&cmd_pt_list_arg3, + (prog_void *)&cmd_pt_list_arg4, + NULL, + }, +}; + +/* del */ + +prog_char str_pt_list_del_arg[] = "del"; +parse_pgm_token_string_t cmd_pt_list_del_arg = TOKEN_STRING_INITIALIZER(struct cmd_pt_list_result, arg1, str_pt_list_del_arg); + +prog_char help_pt_list_del[] = "Del or insert point in pt_list (num)"; +parse_pgm_inst_t cmd_pt_list_del = { + .f = cmd_pt_list_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pt_list_del, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pt_list_arg0, + (prog_void *)&cmd_pt_list_del_arg, + (prog_void *)&cmd_pt_list_arg2, + NULL, + }, +}; +/* show */ + +prog_char str_pt_list_show_arg[] = "show#reset#start#avoid_start"; +parse_pgm_token_string_t cmd_pt_list_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_pt_list_result, arg1, str_pt_list_show_arg); + +prog_char help_pt_list_show[] = "Show, start or reset pt_list"; +parse_pgm_inst_t cmd_pt_list_show = { + .f = cmd_pt_list_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pt_list_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pt_list_arg0, + (prog_void *)&cmd_pt_list_show_arg, + NULL, + }, +}; + + + +/**********************************************************/ +/* Goto function */ + +/* this structure is filled when cmd_goto is parsed successfully */ +struct cmd_goto_result { + fixed_string_t arg0; + fixed_string_t arg1; + int32_t arg2; + int32_t arg3; + int32_t arg4; +}; + +/* function called when cmd_goto is parsed successfully */ +static void cmd_goto_parsed(void * parsed_result, void * data) +{ + struct cmd_goto_result * res = parsed_result; + uint8_t err; + microseconds t1, t2; + + interrupt_traj_reset(); + if (!strcmp_P(res->arg1, PSTR("a_rel"))) { + trajectory_a_rel(&mainboard.traj, res->arg2); + } + else if (!strcmp_P(res->arg1, PSTR("d_rel"))) { + trajectory_d_rel(&mainboard.traj, res->arg2); + } + else if (!strcmp_P(res->arg1, PSTR("a_abs"))) { + trajectory_a_abs(&mainboard.traj, res->arg2); + } + else if (!strcmp_P(res->arg1, PSTR("a_to_xy"))) { + trajectory_turnto_xy(&mainboard.traj, res->arg2, res->arg3); + } + else if (!strcmp_P(res->arg1, PSTR("a_behind_xy"))) { + trajectory_turnto_xy_behind(&mainboard.traj, res->arg2, res->arg3); + } + else if (!strcmp_P(res->arg1, PSTR("xy_rel"))) { + trajectory_goto_xy_rel(&mainboard.traj, res->arg2, res->arg3); + } + else if (!strcmp_P(res->arg1, PSTR("xy_abs"))) { + trajectory_goto_xy_abs(&mainboard.traj, res->arg2, res->arg3); + } + else if (!strcmp_P(res->arg1, PSTR("avoid"))) { + err = goto_and_avoid_forward(res->arg2, res->arg3, 0xFF, 0xFF); + if (err != END_TRAJ && err != END_NEAR) + strat_hardstop(); + } + else if (!strcmp_P(res->arg1, PSTR("avoid_bw"))) { + err = goto_and_avoid_backward(res->arg2, res->arg3, 0xFF, 0xFF); + if (err != END_TRAJ && err != END_NEAR) + strat_hardstop(); + } + else if (!strcmp_P(res->arg1, PSTR("xy_abs_fow"))) { + trajectory_goto_forward_xy_abs(&mainboard.traj, res->arg2, res->arg3); + } + else if (!strcmp_P(res->arg1, PSTR("xy_abs_back"))) { + trajectory_goto_backward_xy_abs(&mainboard.traj, res->arg2, res->arg3); + } + else if (!strcmp_P(res->arg1, PSTR("da_rel"))) { + trajectory_d_a_rel(&mainboard.traj, res->arg2, res->arg3); + } + t1 = time_get_us2(); + while ((err = test_traj_end(0xFF)) == 0) { + t2 = time_get_us2(); + if (t2 - t1 > 200000) { + dump_cs_debug("angle", &mainboard.angle.cs); + dump_cs_debug("distance", &mainboard.distance.cs); + t1 = t2; + } + } + if (err != END_TRAJ && err != END_NEAR) + strat_hardstop(); + printf_P(PSTR("returned %s\r\n"), get_err(err)); +} + +prog_char str_goto_arg0[] = "goto"; +parse_pgm_token_string_t cmd_goto_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_goto_result, arg0, str_goto_arg0); +prog_char str_goto_arg1_a[] = "d_rel#a_rel#a_abs"; +parse_pgm_token_string_t cmd_goto_arg1_a = TOKEN_STRING_INITIALIZER(struct cmd_goto_result, arg1, str_goto_arg1_a); +parse_pgm_token_num_t cmd_goto_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_goto_result, arg2, INT32); + +/* 1 params */ +prog_char help_goto1[] = "Change orientation of the mainboard"; +parse_pgm_inst_t cmd_goto1 = { + .f = cmd_goto_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_goto1, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_goto_arg0, + (prog_void *)&cmd_goto_arg1_a, + (prog_void *)&cmd_goto_arg2, + NULL, + }, +}; + +prog_char str_goto_arg1_b[] = "xy_rel#xy_abs#xy_abs_fow#xy_abs_back#da_rel#a_to_xy#avoid#avoid_bw#a_behind_xy"; +parse_pgm_token_string_t cmd_goto_arg1_b = TOKEN_STRING_INITIALIZER(struct cmd_goto_result, arg1, str_goto_arg1_b); +parse_pgm_token_num_t cmd_goto_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_goto_result, arg3, INT32); + +/* 2 params */ +prog_char help_goto2[] = "Go to a (x,y) or (d,a) position"; +parse_pgm_inst_t cmd_goto2 = { + .f = cmd_goto_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_goto2, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_goto_arg0, + (prog_void *)&cmd_goto_arg1_b, + (prog_void *)&cmd_goto_arg2, + (prog_void *)&cmd_goto_arg3, + NULL, + }, +}; + +/**********************************************************/ +/* Position tests */ + +/* this structure is filled when cmd_position is parsed successfully */ +struct cmd_position_result { + fixed_string_t arg0; + fixed_string_t arg1; + int32_t arg2; + int32_t arg3; + int32_t arg4; +}; + +#define AUTOPOS_SPEED_FAST 200 +static void auto_position(void) +{ + uint8_t err; + uint16_t old_spdd, old_spda; + + interrupt_traj_reset(); + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(AUTOPOS_SPEED_FAST, AUTOPOS_SPEED_FAST); + + trajectory_d_rel(&mainboard.traj, -300); + err = wait_traj_end(END_INTR|END_TRAJ|END_BLOCKING); + if (err == END_INTR) + goto intr; + wait_ms(100); + strat_reset_pos(ROBOT_LENGTH/2, 0, 0); + + trajectory_d_rel(&mainboard.traj, 120); + err = wait_traj_end(END_INTR|END_TRAJ); + if (err == END_INTR) + goto intr; + + trajectory_a_rel(&mainboard.traj, COLOR_A(90)); + err = wait_traj_end(END_INTR|END_TRAJ); + if (err == END_INTR) + goto intr; + + trajectory_d_rel(&mainboard.traj, -300); + err = wait_traj_end(END_INTR|END_TRAJ|END_BLOCKING); + if (err == END_INTR) + goto intr; + wait_ms(100); + strat_reset_pos(DO_NOT_SET_POS, COLOR_Y(ROBOT_LENGTH/2), + COLOR_A(90)); + + trajectory_d_rel(&mainboard.traj, 120); + err = wait_traj_end(END_INTR|END_TRAJ); + if (err == END_INTR) + goto intr; + wait_ms(100); + + trajectory_a_rel(&mainboard.traj, COLOR_A(-40)); + err = wait_traj_end(END_INTR|END_TRAJ); + if (err == END_INTR) + goto intr; + wait_ms(100); + + strat_set_speed(old_spdd, old_spda); + return; + +intr: + strat_hardstop(); + strat_set_speed(old_spdd, old_spda); +} + +/* function called when cmd_position is parsed successfully */ +static void cmd_position_parsed(void * parsed_result, void * data) +{ + struct cmd_position_result * res = parsed_result; + + /* display raw position values */ + if (!strcmp_P(res->arg1, PSTR("reset"))) { + position_set(&mainboard.pos, 0, 0, 0); + } + else if (!strcmp_P(res->arg1, PSTR("set"))) { + position_set(&mainboard.pos, res->arg2, res->arg3, res->arg4); + } + else if (!strcmp_P(res->arg1, PSTR("autoset_green"))) { + mainboard.our_color = I2C_COLOR_GREEN; + i2c_set_color(I2C_MECHBOARD_ADDR, I2C_COLOR_GREEN); + i2c_set_color(I2C_SENSORBOARD_ADDR, I2C_COLOR_GREEN); + auto_position(); + } + else if (!strcmp_P(res->arg1, PSTR("autoset_red"))) { + mainboard.our_color = I2C_COLOR_RED; + i2c_set_color(I2C_MECHBOARD_ADDR, I2C_COLOR_RED); + i2c_set_color(I2C_SENSORBOARD_ADDR, I2C_COLOR_RED); + auto_position(); + } + + /* else it's just a "show" */ + printf_P(PSTR("x=%.2f y=%.2f a=%.2f\r\n"), + position_get_x_double(&mainboard.pos), + position_get_y_double(&mainboard.pos), + DEG(position_get_a_rad_double(&mainboard.pos))); +} + +prog_char str_position_arg0[] = "position"; +parse_pgm_token_string_t cmd_position_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_position_result, arg0, str_position_arg0); +prog_char str_position_arg1[] = "show#reset#autoset_green#autoset_red"; +parse_pgm_token_string_t cmd_position_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_position_result, arg1, str_position_arg1); + +prog_char help_position[] = "Show/reset (x,y,a) position"; +parse_pgm_inst_t cmd_position = { + .f = cmd_position_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_position, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_position_arg0, + (prog_void *)&cmd_position_arg1, + NULL, + }, +}; + + +prog_char str_position_arg1_set[] = "set"; +parse_pgm_token_string_t cmd_position_arg1_set = TOKEN_STRING_INITIALIZER(struct cmd_position_result, arg1, str_position_arg1_set); +parse_pgm_token_num_t cmd_position_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_position_result, arg2, INT32); +parse_pgm_token_num_t cmd_position_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_position_result, arg3, INT32); +parse_pgm_token_num_t cmd_position_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_position_result, arg4, INT32); + +prog_char help_position_set[] = "Set (x,y,a) position"; +parse_pgm_inst_t cmd_position_set = { + .f = cmd_position_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_position_set, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_position_arg0, + (prog_void *)&cmd_position_arg1_set, + (prog_void *)&cmd_position_arg2, + (prog_void *)&cmd_position_arg3, + (prog_void *)&cmd_position_arg4, + NULL, + }, +}; + + +/**********************************************************/ +/* strat configuration */ + +/* this structure is filled when cmd_strat_infos is parsed successfully */ +struct cmd_strat_infos_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_strat_infos is parsed successfully */ +static void cmd_strat_infos_parsed(void *parsed_result, void *data) +{ + struct cmd_strat_infos_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("reset"))) { + strat_reset_infos(); + } + strat_infos.dump_enabled = 1; + strat_dump_infos(__FUNCTION__); +} + +prog_char str_strat_infos_arg0[] = "strat_infos"; +parse_pgm_token_string_t cmd_strat_infos_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_strat_infos_result, arg0, str_strat_infos_arg0); +prog_char str_strat_infos_arg1[] = "show#reset"; +parse_pgm_token_string_t cmd_strat_infos_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_strat_infos_result, arg1, str_strat_infos_arg1); + +prog_char help_strat_infos[] = "reset/show strat_infos"; +parse_pgm_inst_t cmd_strat_infos = { + .f = cmd_strat_infos_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_strat_infos, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_strat_infos_arg0, + (prog_void *)&cmd_strat_infos_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* strat configuration */ + +/* this structure is filled when cmd_strat_conf is parsed successfully */ +struct cmd_strat_conf_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_strat_conf is parsed successfully */ +static void cmd_strat_conf_parsed(void *parsed_result, void *data) +{ + struct cmd_strat_conf_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("base"))) { + strat_infos.conf.flags = 0; + strat_infos.conf.scan_our_min_time = 90; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 90; + strat_infos.conf.delay_between_opp_scan = 90; + } + else if (!strcmp_P(res->arg1, PSTR("big3"))) { + strat_infos.conf.flags = + STRAT_CONF_STORE_STATIC2 | + STRAT_CONF_BIG_3_TEMPLE; + strat_infos.conf.scan_our_min_time = 90; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 90; + strat_infos.conf.delay_between_opp_scan = 90; + } + else if (!strcmp_P(res->arg1, PSTR("base_check"))) { + strat_infos.conf.flags = 0; + strat_infos.conf.scan_our_min_time = 35; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 90; + strat_infos.conf.delay_between_opp_scan = 90; + } + else if (!strcmp_P(res->arg1, PSTR("big3_check"))) { + strat_infos.conf.flags = + STRAT_CONF_STORE_STATIC2 | + STRAT_CONF_BIG_3_TEMPLE; + strat_infos.conf.scan_our_min_time = 35; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 90; + strat_infos.conf.delay_between_opp_scan = 90; + } + else if (!strcmp_P(res->arg1, PSTR("offensive_early"))) { + strat_infos.conf.flags = + STRAT_CONF_TAKE_ONE_LINTEL | + STRAT_CONF_STORE_STATIC2 | + STRAT_CONF_EARLY_SCAN | + STRAT_CONF_PUSH_OPP_COLS; + strat_infos.conf.scan_our_min_time = 50; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 15; + strat_infos.conf.delay_between_opp_scan = 90; + strat_infos.conf.wait_opponent = 5; + } + else if (!strcmp_P(res->arg1, PSTR("offensive_late"))) { + strat_infos.conf.flags = STRAT_CONF_TAKE_ONE_LINTEL; + strat_infos.conf.scan_our_min_time = 90; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 30; + strat_infos.conf.delay_between_opp_scan = 90; + } + else if (!strcmp_P(res->arg1, PSTR("one_on_disc"))) { + strat_infos.conf.flags = + STRAT_CONF_ONLY_ONE_ON_DISC; + strat_infos.conf.scan_our_min_time = 90; + strat_infos.conf.delay_between_our_scan = 90; + strat_infos.conf.scan_opp_min_time = 90; + strat_infos.conf.delay_between_opp_scan = 90; + } + strat_infos.dump_enabled = 1; + strat_dump_conf(); +} + +prog_char str_strat_conf_arg0[] = "strat_conf"; +parse_pgm_token_string_t cmd_strat_conf_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf_result, arg0, str_strat_conf_arg0); +prog_char str_strat_conf_arg1[] = "show#base#big3#base_check#big3_check#offensive_early#offensive_late#one_on_disc"; +parse_pgm_token_string_t cmd_strat_conf_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf_result, arg1, str_strat_conf_arg1); + +prog_char help_strat_conf[] = "configure strat options"; +parse_pgm_inst_t cmd_strat_conf = { + .f = cmd_strat_conf_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_strat_conf, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_strat_conf_arg0, + (prog_void *)&cmd_strat_conf_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* strat configuration */ + +/* this structure is filled when cmd_strat_conf2 is parsed successfully */ +struct cmd_strat_conf2_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_strat_conf2 is parsed successfully */ +static void cmd_strat_conf2_parsed(void *parsed_result, void *data) +{ + struct cmd_strat_conf2_result *res = parsed_result; + uint8_t on, bit = 0; + + if (!strcmp_P(res->arg2, PSTR("on"))) + on = 1; + else + on = 0; + + if (!strcmp_P(res->arg1, PSTR("one_temple_on_disc"))) + bit = STRAT_CONF_ONLY_ONE_ON_DISC; + else if (!strcmp_P(res->arg1, PSTR("bypass_static2"))) + bit = STRAT_CONF_BYPASS_STATIC2; + else if (!strcmp_P(res->arg1, PSTR("take_one_lintel"))) + bit = STRAT_CONF_TAKE_ONE_LINTEL; + else if (!strcmp_P(res->arg1, PSTR("skip_when_check_fail"))) + bit = STRAT_CONF_TAKE_ONE_LINTEL; + else if (!strcmp_P(res->arg1, PSTR("store_static2"))) + bit = STRAT_CONF_STORE_STATIC2; + else if (!strcmp_P(res->arg1, PSTR("big3_temple"))) + bit = STRAT_CONF_BIG_3_TEMPLE; + else if (!strcmp_P(res->arg1, PSTR("early_opp_scan"))) + bit = STRAT_CONF_EARLY_SCAN; + else if (!strcmp_P(res->arg1, PSTR("push_opp_cols"))) + bit = STRAT_CONF_PUSH_OPP_COLS; + + if (on) + strat_infos.conf.flags |= bit; + else + strat_infos.conf.flags &= (~bit); + + strat_infos.dump_enabled = 1; + strat_dump_conf(); +} + +prog_char str_strat_conf2_arg0[] = "strat_conf"; +parse_pgm_token_string_t cmd_strat_conf2_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf2_result, arg0, str_strat_conf2_arg0); +prog_char str_strat_conf2_arg1[] = "push_opp_cols#one_temple_on_disc#bypass_static2#take_one_lintel#skip_when_check_fail#store_static2#big3_temple#early_opp_scan"; +parse_pgm_token_string_t cmd_strat_conf2_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf2_result, arg1, str_strat_conf2_arg1); +prog_char str_strat_conf2_arg2[] = "on#off"; +parse_pgm_token_string_t cmd_strat_conf2_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf2_result, arg2, str_strat_conf2_arg2); + + +prog_char help_strat_conf2[] = "configure strat options"; +parse_pgm_inst_t cmd_strat_conf2 = { + .f = cmd_strat_conf2_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_strat_conf2, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_strat_conf2_arg0, + (prog_void *)&cmd_strat_conf2_arg1, + (prog_void *)&cmd_strat_conf2_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* strat configuration */ + +/* this structure is filled when cmd_strat_conf3 is parsed successfully */ +struct cmd_strat_conf3_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t arg2; +}; + +/* function called when cmd_strat_conf3 is parsed successfully */ +static void cmd_strat_conf3_parsed(void *parsed_result, void *data) +{ + struct cmd_strat_conf3_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("scan_opponent_min_time"))) { + if (res->arg2 > 90) + res->arg2 = 90; + strat_infos.conf.scan_opp_min_time = res->arg2; + } + else if (!strcmp_P(res->arg1, PSTR("delay_between_opponent_scan"))) { + if (res->arg2 > 90) + res->arg2 = 90; + strat_infos.conf.delay_between_opp_scan = res->arg2; + } + else if (!strcmp_P(res->arg1, PSTR("scan_our_min_time"))) { + if (res->arg2 > 90) + res->arg2 = 90; + strat_infos.conf.scan_our_min_time = res->arg2; + } + else if (!strcmp_P(res->arg1, PSTR("delay_between_our_scan"))) { + if (res->arg2 > 90) + res->arg2 = 90; + strat_infos.conf.delay_between_our_scan = res->arg2; + } + else if (!strcmp_P(res->arg1, PSTR("wait_opponent"))) { + strat_infos.conf.wait_opponent = res->arg2; + } + else if (!strcmp_P(res->arg1, PSTR("lintel_min_time"))) { + strat_infos.conf.lintel_min_time = res->arg2; + } + strat_infos.dump_enabled = 1; + strat_dump_conf(); +} + +prog_char str_strat_conf3_arg0[] = "strat_conf"; +parse_pgm_token_string_t cmd_strat_conf3_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf3_result, arg0, str_strat_conf3_arg0); +prog_char str_strat_conf3_arg1[] = "lintel_min_time#scan_opponent_min_time#delay_between_opponent_scan#scan_our_min_time#delay_between_our_scan#wait_opponent"; +parse_pgm_token_string_t cmd_strat_conf3_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf3_result, arg1, str_strat_conf3_arg1); +parse_pgm_token_num_t cmd_strat_conf3_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_strat_conf3_result, arg2, UINT16); + +prog_char help_strat_conf3[] = "configure strat options"; +parse_pgm_inst_t cmd_strat_conf3 = { + .f = cmd_strat_conf3_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_strat_conf3, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_strat_conf3_arg0, + (prog_void *)&cmd_strat_conf3_arg1, + (prog_void *)&cmd_strat_conf3_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* strat configuration */ + +/* this structure is filled when cmd_strat_conf4 is parsed successfully */ +struct cmd_strat_conf4_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; +}; + +/* function called when cmd_strat_conf4 is parsed successfully */ +static void cmd_strat_conf4_parsed(void *parsed_result, void *data) +{ + struct cmd_strat_conf4_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("scan_opponent_angle"))) { + strat_infos.conf.scan_opp_angle = res->arg2; + } + strat_infos.dump_enabled = 1; + strat_dump_conf(); +} + +prog_char str_strat_conf4_arg0[] = "strat_conf"; +parse_pgm_token_string_t cmd_strat_conf4_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf4_result, arg0, str_strat_conf4_arg0); +prog_char str_strat_conf4_arg1[] = "scan_opponent_angle"; +parse_pgm_token_string_t cmd_strat_conf4_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_strat_conf4_result, arg1, str_strat_conf4_arg1); +parse_pgm_token_num_t cmd_strat_conf4_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_strat_conf4_result, arg2, UINT16); + +prog_char help_strat_conf4[] = "configure strat options"; +parse_pgm_inst_t cmd_strat_conf4 = { + .f = cmd_strat_conf4_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_strat_conf4, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_strat_conf4_arg0, + (prog_void *)&cmd_strat_conf4_arg1, + (prog_void *)&cmd_strat_conf4_arg2, + NULL, + }, +}; + + +/**********************************************************/ +/* Subtraj */ + +/* this structure is filled when cmd_subtraj is parsed successfully */ +struct cmd_subtraj_result { + fixed_string_t arg0; + fixed_string_t arg1; + int32_t arg2; + int32_t arg3; + int32_t arg4; + int32_t arg5; +}; + +/* function called when cmd_subtraj is parsed successfully */ +static void cmd_subtraj_parsed(void *parsed_result, void *data) +{ + struct cmd_subtraj_result *res = parsed_result; + uint8_t err = 0; + struct column_dispenser *disp; + + if (strcmp_P(res->arg1, PSTR("static")) == 0) { + err = strat_static_columns(res->arg2); + } + else if (strcmp_P(res->arg1, PSTR("static2")) == 0) { + strat_infos.s_cols.configuration = res->arg2; + switch (res->arg2) { + case 1: + position_set(&mainboard.pos, 1398, + COLOR_Y(1297), COLOR_A(-66)); + break; + case 2: + position_set(&mainboard.pos, 1232, + COLOR_Y(1051), COLOR_A(4)); + break; + case 3: + position_set(&mainboard.pos, 1232, + COLOR_Y(1043), COLOR_A(5)); + break; + case 4: + position_set(&mainboard.pos, 1346, + COLOR_Y(852), COLOR_A(57)); + break; + default: + return; + } + if (res->arg2 == 1 && res->arg3 == 1) { + strat_infos.s_cols.flags = STATIC_COL_LINE1_DONE; + } + if (res->arg2 == 1 && res->arg3 == 2) { + strat_infos.s_cols.flags = STATIC_COL_LINE2_DONE; + } + err = strat_static_columns_pass2(); + } + else if (strcmp_P(res->arg1, PSTR("lintel1")) == 0) { + err = strat_goto_lintel_disp(&strat_infos.l1); + } + else if (strcmp_P(res->arg1, PSTR("lintel2")) == 0) { + err = strat_goto_lintel_disp(&strat_infos.l2); + } + else if (strcmp_P(res->arg1, PSTR("coldisp1")) == 0) { + disp = &strat_infos.c1; + err = strat_goto_col_disp(&disp); + } + else if (strcmp_P(res->arg1, PSTR("coldisp2")) == 0) { + disp = &strat_infos.c2; + err = strat_goto_col_disp(&disp); + } + else if (strcmp_P(res->arg1, PSTR("coldisp3")) == 0) { + disp = &strat_infos.c3; + err = strat_goto_col_disp(&disp); + } + else if (strcmp_P(res->arg1, PSTR("disc")) == 0) { + if (res->arg2 == 0) { + printf_P(PSTR("bad level\r\n")); + return; + } + err = strat_goto_disc(res->arg2); + } + + printf_P(PSTR("substrat returned %s\r\n"), get_err(err)); + trajectory_hardstop(&mainboard.traj); +} + +prog_char str_subtraj_arg0[] = "subtraj"; +parse_pgm_token_string_t cmd_subtraj_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_subtraj_result, arg0, str_subtraj_arg0); +prog_char str_subtraj_arg1[] = "static#disc#lintel1#lintel2#coldisp1#coldisp2#coldisp3#static2"; +parse_pgm_token_string_t cmd_subtraj_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_subtraj_result, arg1, str_subtraj_arg1); +parse_pgm_token_num_t cmd_subtraj_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_subtraj_result, arg2, INT32); +parse_pgm_token_num_t cmd_subtraj_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_subtraj_result, arg3, INT32); +parse_pgm_token_num_t cmd_subtraj_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_subtraj_result, arg4, INT32); +parse_pgm_token_num_t cmd_subtraj_arg5 = TOKEN_NUM_INITIALIZER(struct cmd_subtraj_result, arg5, INT32); + +prog_char help_subtraj[] = "Test sub-trajectories (a,b,c,d: specific params)"; +parse_pgm_inst_t cmd_subtraj = { + .f = cmd_subtraj_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_subtraj, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_subtraj_arg0, + (prog_void *)&cmd_subtraj_arg1, + (prog_void *)&cmd_subtraj_arg2, + (prog_void *)&cmd_subtraj_arg3, + (prog_void *)&cmd_subtraj_arg4, + (prog_void *)&cmd_subtraj_arg5, + NULL, + }, +}; diff --git a/projects/microb2009/mainboard/cs.c b/projects/microb2009/mainboard/cs.c new file mode 100644 index 0000000..ec70f9a --- /dev/null +++ b/projects/microb2009/mainboard/cs.c @@ -0,0 +1,239 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cs.c,v 1.9 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> +#include <adc.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "main.h" +#include "strat.h" +#include "actuator.h" + +/* called every 5 ms */ +static void do_cs(void *dummy) +{ + static uint16_t cpt = 0; + static int32_t old_a = 0, old_d = 0; + + /* read encoders */ + if (mainboard.flags & DO_ENCODERS) { + encoders_spi_manage(NULL); + } + + /* XXX there is an issue which is probably related to avr-libc + * 1.6.2 (debian): this code using fixed_point lib does not + * work with it */ + /* robot system, conversion to angle,distance */ + if (mainboard.flags & DO_RS) { + int16_t a,d; + rs_update(&mainboard.rs); /* takes about 0.5 ms */ + /* process and store current speed */ + a = rs_get_angle(&mainboard.rs); + d = rs_get_distance(&mainboard.rs); + mainboard.speed_a = a - old_a; + mainboard.speed_d = d - old_d; + old_a = a; + old_d = d; + } + + /* control system */ + if (mainboard.flags & DO_CS) { + if (mainboard.angle.on) + cs_manage(&mainboard.angle.cs); + if (mainboard.distance.on) + cs_manage(&mainboard.distance.cs); + } + if ((cpt & 1) && (mainboard.flags & DO_POS)) { + /* about 1.5ms (worst case without centrifugal force + * compensation) */ + position_manage(&mainboard.pos); + } + if (mainboard.flags & DO_BD) { + bd_manage_from_cs(&mainboard.angle.bd, &mainboard.angle.cs); + bd_manage_from_cs(&mainboard.distance.bd, &mainboard.distance.cs); + } + if (mainboard.flags & DO_TIMER) { + uint8_t second; + /* the robot should stop correctly in the strat, but + * in some cases, we must force the stop from an + * interrupt */ + second = time_get_s(); + if (second >= MATCH_TIME + 2) { + pwm_ng_set(LEFT_PWM, 0); + pwm_ng_set(RIGHT_PWM, 0); + printf_P(PSTR("END OF TIME\r\n")); + while(1); + } + } + /* brakes */ + if (mainboard.flags & DO_POWER) + BRAKE_OFF(); + else + BRAKE_ON(); + cpt++; +} + +void dump_cs_debug(const char *name, struct cs *cs) +{ + DEBUG(E_USER_CS, "%s cons=% .5ld fcons=% .5ld err=% .5ld " + "in=% .5ld out=% .5ld", + name, cs_get_consign(cs), cs_get_filtered_consign(cs), + cs_get_error(cs), cs_get_filtered_feedback(cs), + cs_get_out(cs)); +} + +void dump_cs(const char *name, struct cs *cs) +{ + printf_P(PSTR("%s cons=% .5ld fcons=% .5ld err=% .5ld " + "in=% .5ld out=% .5ld\r\n"), + name, cs_get_consign(cs), cs_get_filtered_consign(cs), + cs_get_error(cs), cs_get_filtered_feedback(cs), + cs_get_out(cs)); +} + +void dump_pid(const char *name, struct pid_filter *pid) +{ + printf_P(PSTR("%s P=% .8ld I=% .8ld D=% .8ld out=% .8ld\r\n"), + name, + pid_get_value_in(pid) * pid_get_gain_P(pid), + pid_get_value_I(pid) * pid_get_gain_I(pid), + pid_get_value_D(pid) * pid_get_gain_D(pid), + pid_get_value_out(pid)); +} + +void microb_cs_init(void) +{ + /* ROBOT_SYSTEM */ + rs_init(&mainboard.rs); + rs_set_left_pwm(&mainboard.rs, pwm_set_and_save, LEFT_PWM); + rs_set_right_pwm(&mainboard.rs, pwm_set_and_save, RIGHT_PWM); + /* increase gain to decrease dist, increase left and it will turn more left */ + rs_set_left_ext_encoder(&mainboard.rs, encoders_spi_get_value, + LEFT_ENCODER, IMP_COEF * 1.0015); + rs_set_right_ext_encoder(&mainboard.rs, encoders_spi_get_value, + RIGHT_ENCODER, IMP_COEF * -1.006); + /* rs will use external encoders */ + rs_set_flags(&mainboard.rs, RS_USE_EXT); + + /* POSITION MANAGER */ + position_init(&mainboard.pos); + position_set_physical_params(&mainboard.pos, VIRTUAL_TRACK_MM, DIST_IMP_MM); + position_set_related_robot_system(&mainboard.pos, &mainboard.rs); + position_set_centrifugal_coef(&mainboard.pos, 0.000016); + position_use_ext(&mainboard.pos); + + /* TRAJECTORY MANAGER */ + trajectory_init(&mainboard.traj); + trajectory_set_cs(&mainboard.traj, &mainboard.distance.cs, + &mainboard.angle.cs); + trajectory_set_robot_params(&mainboard.traj, &mainboard.rs, &mainboard.pos); + trajectory_set_speed(&mainboard.traj, SPEED_DIST_FAST, SPEED_ANGLE_FAST); /* d, a */ + /* distance window, angle window, angle start */ + trajectory_set_windows(&mainboard.traj, 200., 5.0, 30.); + + /* ---- CS angle */ + /* PID */ + pid_init(&mainboard.angle.pid); + pid_set_gains(&mainboard.angle.pid, 500, 10, 7000); + pid_set_maximums(&mainboard.angle.pid, 0, 20000, 4095); + pid_set_out_shift(&mainboard.angle.pid, 10); + pid_set_derivate_filter(&mainboard.angle.pid, 4); + + /* QUADRAMP */ + quadramp_init(&mainboard.angle.qr); + quadramp_set_1st_order_vars(&mainboard.angle.qr, 2000, 2000); /* set speed */ + quadramp_set_2nd_order_vars(&mainboard.angle.qr, 13, 13); /* set accel */ + + /* CS */ + cs_init(&mainboard.angle.cs); + cs_set_consign_filter(&mainboard.angle.cs, quadramp_do_filter, &mainboard.angle.qr); + cs_set_correct_filter(&mainboard.angle.cs, pid_do_filter, &mainboard.angle.pid); + cs_set_process_in(&mainboard.angle.cs, rs_set_angle, &mainboard.rs); + cs_set_process_out(&mainboard.angle.cs, rs_get_angle, &mainboard.rs); + cs_set_consign(&mainboard.angle.cs, 0); + + /* Blocking detection */ + bd_init(&mainboard.angle.bd); + bd_set_speed_threshold(&mainboard.angle.bd, 80); + bd_set_current_thresholds(&mainboard.angle.bd, 500, 8000, 1000000, 50); + + /* ---- CS distance */ + /* PID */ + pid_init(&mainboard.distance.pid); + pid_set_gains(&mainboard.distance.pid, 500, 10, 7000); + pid_set_maximums(&mainboard.distance.pid, 0, 2000, 4095); + pid_set_out_shift(&mainboard.distance.pid, 10); + pid_set_derivate_filter(&mainboard.distance.pid, 6); + + /* QUADRAMP */ + quadramp_init(&mainboard.distance.qr); + quadramp_set_1st_order_vars(&mainboard.distance.qr, 2000, 2000); /* set speed */ + quadramp_set_2nd_order_vars(&mainboard.distance.qr, 17, 17); /* set accel */ + + /* CS */ + cs_init(&mainboard.distance.cs); + cs_set_consign_filter(&mainboard.distance.cs, quadramp_do_filter, &mainboard.distance.qr); + cs_set_correct_filter(&mainboard.distance.cs, pid_do_filter, &mainboard.distance.pid); + cs_set_process_in(&mainboard.distance.cs, rs_set_distance, &mainboard.rs); + cs_set_process_out(&mainboard.distance.cs, rs_get_distance, &mainboard.rs); + cs_set_consign(&mainboard.distance.cs, 0); + + /* Blocking detection */ + bd_init(&mainboard.distance.bd); + bd_set_speed_threshold(&mainboard.distance.bd, 60); + bd_set_current_thresholds(&mainboard.distance.bd, 500, 8000, 1000000, 50); + + /* set them on !! */ + mainboard.angle.on = 1; + mainboard.distance.on = 1; + + + scheduler_add_periodical_event_priority(do_cs, NULL, + 5000L / SCHEDULER_UNIT, + CS_PRIO); +} diff --git a/projects/microb2009/mainboard/cs.h b/projects/microb2009/mainboard/cs.h new file mode 100644 index 0000000..d3d1fa9 --- /dev/null +++ b/projects/microb2009/mainboard/cs.h @@ -0,0 +1,26 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cs.h,v 1.3 2009-03-29 18:42:41 zer0 Exp $ + * + */ + +void microb_cs_init(void); +void dump_cs(const char *name, struct cs *cs); +void dump_cs_debug(const char *name, struct cs *cs); +void dump_pid(const char *name, struct pid_filter *pid); diff --git a/projects/microb2009/mainboard/diagnostic_config.h b/projects/microb2009/mainboard/diagnostic_config.h new file mode 100644 index 0000000..9d9c3a5 --- /dev/null +++ b/projects/microb2009/mainboard/diagnostic_config.h @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.1 2009-02-27 22:23:37 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +/* undefine it to disable this functionnality */ +#define INTERRUPT_SHOW_PORT PORTA +#define INTERRUPT_SHOW_BIT 3 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#define DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/projects/microb2009/mainboard/encoders_spi_config.h b/projects/microb2009/mainboard/encoders_spi_config.h new file mode 100644 index 0000000..6528244 --- /dev/null +++ b/projects/microb2009/mainboard/encoders_spi_config.h @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_spi_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ +#ifndef _ENCODERS_SPI_CONFIG_H_ +#define _ENCODERS_SPI_CONFIG_H_ + +#define ENCODERS_SPI_NUMBER 4 +#define ENCODERS_SPI_SS_PORT SS_PORT /* PORTB on atmega2560 */ +#define ENCODERS_SPI_SS_BIT SS_BIT /* 0 on atmega2560 */ + +/* see spi configuration */ +#define ENCODERS_SPI_CLK_RATE SPI_CLK_RATE_16 +#define ENCODERS_SPI_FORMAT SPI_FORMAT_3 +#define ENCODERS_SPI_DATA_ORDER SPI_LSB_FIRST + +#endif diff --git a/projects/microb2009/mainboard/error_config.h b/projects/microb2009/mainboard/error_config.h new file mode 100644 index 0000000..7aad86a --- /dev/null +++ b/projects/microb2009/mainboard/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2009-02-27 22:23:37 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/mainboard/i2c_config.h b/projects/microb2009/mainboard/i2c_config.h new file mode 100644 index 0000000..1617810 --- /dev/null +++ b/projects/microb2009/mainboard/i2c_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.2 2009-03-05 23:01:32 zer0 Exp $ + * + */ + + +#define I2C_BITRATE 1 // divider dor i2c baudrate, see TWBR in doc +#define I2C_PRESCALER 3 // prescaler config, rate = 2^(n*2) + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 32 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 32 diff --git a/projects/microb2009/mainboard/i2c_protocol.c b/projects/microb2009/mainboard/i2c_protocol.c new file mode 100644 index 0000000..a503f6d --- /dev/null +++ b/projects/microb2009/mainboard/i2c_protocol.c @@ -0,0 +1,687 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.c,v 1.8 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <i2c.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "sensor.h" +#include "i2c_protocol.h" + +#define I2C_STATE_MAX 4 + +#define I2C_TIMEOUT 100 /* ms */ +#define I2C_MAX_ERRORS 40 + +static volatile uint8_t i2c_poll_num = 0; +static volatile uint8_t i2c_state = 0; +static volatile uint16_t i2c_errors = 0; + +#define OP_READY 0 /* no i2c op running */ +#define OP_POLL 1 /* a user command is running */ +#define OP_CMD 2 /* a polling (req / ans) is running */ + +static volatile uint8_t running_op = OP_READY; + +#define I2C_MAX_LOG 3 +static uint8_t error_log = 0; + +/* used for commands */ +uint8_t command_buf[I2C_SEND_BUFFER_SIZE]; +volatile int8_t command_dest=-1; +volatile uint8_t command_size=0; + +static int8_t i2c_req_mechboard_status(void); +static int8_t i2c_req_sensorboard_status(void); + +#define I2C_ERROR(args...) do { \ + if (error_log < I2C_MAX_LOG) { \ + ERROR(E_USER_I2C_PROTO, args); \ + error_log ++; \ + if (error_log == I2C_MAX_LOG) { \ + ERROR(E_USER_I2C_PROTO, \ + "i2c logs are now warnings"); \ + } \ + } \ + else \ + WARNING(E_USER_I2C_PROTO, args); \ + } while(0) + +void i2c_protocol_init(void) +{ +} + +void i2c_protocol_debug(void) +{ + printf_P(PSTR("I2C protocol debug infos:\r\n")); + printf_P(PSTR(" i2c_state=%d\r\n"), i2c_state); + printf_P(PSTR(" i2c_errors=%d\r\n"), i2c_errors); + printf_P(PSTR(" running_op=%d\r\n"), running_op); + printf_P(PSTR(" command_size=%d\r\n"), command_size); + printf_P(PSTR(" command_dest=%d\r\n"), command_dest); + printf_P(PSTR(" i2c_status=%x\r\n"), i2c_status()); +} + +static void i2cproto_next_state(uint8_t inc) +{ + i2c_state += inc; + if (i2c_state >= I2C_STATE_MAX) { + i2c_state = 0; + i2c_poll_num ++; + } +} + +void i2cproto_wait_update(void) +{ + uint8_t poll_num; + poll_num = i2c_poll_num; + WAIT_COND_OR_TIMEOUT((i2c_poll_num-poll_num) > 1, 150); +} + +/* called periodically : the goal of this 'thread' is to send requests + * and read answers on i2c slaves in the correct order. */ +void i2c_poll_slaves(void *dummy) +{ + uint8_t flags; + int8_t err; + static uint8_t a = 0; + + a++; + if (a & 0x4) + LED2_TOGGLE(); + + /* already running */ + IRQ_LOCK(flags); + if (running_op != OP_READY) { + IRQ_UNLOCK(flags); + return; + } + + /* if a command is ready to be sent, so send it */ + if (command_size) { + running_op = OP_CMD; + err = i2c_send(command_dest, command_buf, command_size, + I2C_CTRL_GENERIC); + if (err < 0) + goto error; + IRQ_UNLOCK(flags); + return; + } + + /* no command, so do the polling */ + running_op = OP_POLL; + + switch(i2c_state) { + + /* poll status of mechboard */ +#define I2C_REQ_MECHBOARD 0 + case I2C_REQ_MECHBOARD: + if ((err = i2c_req_mechboard_status())) + goto error; + break; + +#define I2C_ANS_MECHBOARD 1 + case I2C_ANS_MECHBOARD: + if ((err = i2c_recv(I2C_MECHBOARD_ADDR, + sizeof(struct i2c_ans_mechboard_status), + I2C_CTRL_GENERIC))) + goto error; + break; + + /* poll status of sensorboard */ +#define I2C_REQ_SENSORBOARD 2 + case I2C_REQ_SENSORBOARD: + if ((err = i2c_req_sensorboard_status())) + goto error; + break; + +#define I2C_ANS_SENSORBOARD 3 + case I2C_ANS_SENSORBOARD: + if ((err = i2c_recv(I2C_SENSORBOARD_ADDR, + sizeof(struct i2c_ans_sensorboard_status), + I2C_CTRL_GENERIC))) + goto error; + break; + + /* nothing, go to the first request */ + default: + i2c_state = 0; + running_op = OP_READY; + } + IRQ_UNLOCK(flags); + + return; + + error: + running_op = OP_READY; + IRQ_UNLOCK(flags); + i2c_errors++; + if (i2c_errors > I2C_MAX_ERRORS) { + I2C_ERROR("I2C send is_cmd=%d proto_state=%d " + "err=%d i2c_status=%x", !!command_size, i2c_state, err, i2c_status()); + i2c_reset(); + i2c_errors = 0; + } +} + +/* called when the xmit is finished */ +void i2c_sendevent(int8_t size) +{ + if (size > 0) { + if (running_op == OP_POLL) { + i2cproto_next_state(1); + } + else + command_size = 0; + } + else { + i2c_errors++; + NOTICE(E_USER_I2C_PROTO, "send error state=%d size=%d " + "op=%d", i2c_state, size, running_op); + if (i2c_errors > I2C_MAX_ERRORS) { + I2C_ERROR("I2C error, slave not ready"); + i2c_reset(); + i2c_errors = 0; + } + + if (running_op == OP_POLL) { + /* skip associated answer */ + i2cproto_next_state(2); + } + } + running_op = OP_READY; +} + +/* called rx event */ +void i2c_recvevent(uint8_t * buf, int8_t size) +{ + if (running_op == OP_POLL) + i2cproto_next_state(1); + + /* recv is only trigged after a poll */ + running_op = OP_READY; + + if (size < 0) { + goto error; + } + + switch (buf[0]) { + + case I2C_ANS_MECHBOARD_STATUS: { + struct i2c_ans_mechboard_status * ans = + (struct i2c_ans_mechboard_status *)buf; + + if (size != sizeof (*ans)) + goto error; + + /* status */ + mechboard.mode = ans->mode; + mechboard.status = ans->status; + mechboard.lintel_count = ans->lintel_count; + mechboard.column_flags = ans->column_flags; + /* pumps pwm */ + mechboard.pump_left1 = ans->pump_left1; + mechboard.pump_left2 = ans->pump_left2; + mechboard.pump_right1 = ans->pump_right1; + mechboard.pump_right2 = ans->pump_right2; + pwm_ng_set(LEFT_PUMP1_PWM, mechboard.pump_left1); + pwm_ng_set(LEFT_PUMP2_PWM, mechboard.pump_left2); + /* pumps current */ + mechboard.pump_right1_current = ans->pump_right1_current; + mechboard.pump_right2_current = ans->pump_right2_current; + /* servos */ + mechboard.servo_lintel_left = ans->servo_lintel_left; + mechboard.servo_lintel_right = ans->servo_lintel_right; + pwm_ng_set(&gen.servo2, mechboard.servo_lintel_right); + pwm_ng_set(&gen.servo3, mechboard.servo_lintel_left); + + break; + } + + case I2C_ANS_SENSORBOARD_STATUS: { + struct i2c_ans_sensorboard_status * ans = + (struct i2c_ans_sensorboard_status *)buf; + + if (size != sizeof (*ans)) + goto error; + sensorboard.status = ans->status; + sensorboard.opponent_x = ans->opponent_x; + sensorboard.opponent_y = ans->opponent_y; + sensorboard.opponent_a = ans->opponent_a; + sensorboard.opponent_d = ans->opponent_d; + + sensorboard.scan_status = ans->scan_status; + sensorboard.dropzone_h = ans->dropzone_h; + sensorboard.dropzone_x = ans->dropzone_x; + sensorboard.dropzone_y = ans->dropzone_y; + break; + } + + default: + break; + } + + return; + error: + i2c_errors++; + NOTICE(E_USER_I2C_PROTO, "recv error state=%d op=%d", + i2c_state, running_op); + if (i2c_errors > I2C_MAX_ERRORS) { + I2C_ERROR("I2C error, slave not ready"); + i2c_reset(); + i2c_errors = 0; + } +} + +void i2c_recvbyteevent(uint8_t hwstatus, uint8_t i, uint8_t c) +{ +} + + + +/* ******** ******** ******** ******** */ +/* commands */ +/* ******** ******** ******** ******** */ + + +static int8_t +i2c_send_command(uint8_t addr, uint8_t * buf, uint8_t size) +{ + uint8_t flags; + microseconds us = time_get_us2(); + + while ((time_get_us2() - us) < (I2C_TIMEOUT)*1000L) { + IRQ_LOCK(flags); + if (command_size == 0) { + memcpy(command_buf, buf, size); + command_size = size; + command_dest = addr; + IRQ_UNLOCK(flags); + return 0; + } + IRQ_UNLOCK(flags); + } + /* this should not happen... except if we are called from an + * interrupt context, but it's forbidden */ + I2C_ERROR("I2C command send failed"); + return -EBUSY; +} + +static int8_t i2c_req_mechboard_status(void) +{ + struct i2c_req_mechboard_status buf; + int8_t err; + + buf.hdr.cmd = I2C_REQ_MECHBOARD_STATUS; + buf.pump_left1_current = sensor_get_adc(ADC_CSENSE3); + buf.pump_left2_current = sensor_get_adc(ADC_CSENSE4); + err = i2c_send(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, + sizeof(buf), I2C_CTRL_GENERIC); + + return err; +} + +static int8_t i2c_req_sensorboard_status(void) +{ + struct i2c_req_sensorboard_status buf; + + buf.hdr.cmd = I2C_REQ_SENSORBOARD_STATUS; + /* robot position */ + buf.x = position_get_x_s16(&mainboard.pos); + buf.y = position_get_y_s16(&mainboard.pos); + buf.a = position_get_a_deg_s16(&mainboard.pos); + /* pickup wheels */ + buf.enable_pickup_wheels = mainboard.enable_pickup_wheels; + + return i2c_send(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, + sizeof(buf), I2C_CTRL_GENERIC); +} + +int8_t i2c_set_color(uint8_t addr, uint8_t color) +{ + struct i2c_cmd_generic_color buf; + + if (addr == I2C_SENSORBOARD_ADDR) + return 0; /* XXX disabled for now */ + buf.hdr.cmd = I2C_CMD_GENERIC_SET_COLOR; + buf.color = color; + return i2c_send_command(addr, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_led_control(uint8_t addr, uint8_t led, uint8_t state) +{ + struct i2c_cmd_led_control buf; + buf.hdr.cmd = I2C_CMD_GENERIC_LED_CONTROL; + buf.led_num = led; + buf.state = state; + return i2c_send_command(addr, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_manual(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_MANUAL; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_harvest(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_HARVEST; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_lazy_harvest(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_LAZY_HARVEST; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_pickup(uint8_t side) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + buf.prep_pickup.next_mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + buf.prep_pickup.side = side; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_push_temple_disc(uint8_t side) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PUSH_TEMPLE_DISC; + buf.prep_pickup.side = side; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_pickup_next(uint8_t side, uint8_t next_mode) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + buf.prep_pickup.next_mode = next_mode; + buf.prep_pickup.side = side; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_pickup(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PICKUP; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_eject(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_EJECT; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_manivelle(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_MANIVELLE; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_push_temple(uint8_t level) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PUSH_TEMPLE; + buf.push_temple.level = level; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf,sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_build_both(uint8_t level) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_BUILD; + buf.prep_build.level_l = level; + buf.prep_build.level_r = level; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_build_select(int8_t level_l, int8_t level_r) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_BUILD; + buf.prep_build.level_l = level_l; + buf.prep_build.level_r = level_r; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_inside_both(uint8_t level) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_INSIDE; + buf.prep_inside.level_l = level; + buf.prep_inside.level_r = level; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_inside_select(int8_t level_l, int8_t level_r) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_INSIDE; + buf.prep_inside.level_l = level_l; + buf.prep_inside.level_r = level_r; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_simple_autobuild(uint8_t level) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_AUTOBUILD; + buf.autobuild.level_left = level; + buf.autobuild.level_right = level; + buf.autobuild.count_left = 2; + buf.autobuild.count_right = 2; + buf.autobuild.do_lintel = 1; + buf.autobuild.distance_left = 210; + buf.autobuild.distance_right = 210; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_autobuild(uint8_t level_l, uint8_t count_l, + uint8_t dist_l, + uint8_t level_r, uint8_t count_r, + uint8_t dist_r, + uint8_t do_lintel) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_AUTOBUILD; + buf.autobuild.level_left = level_l; + buf.autobuild.level_right = level_r; + buf.autobuild.count_left = count_l; + buf.autobuild.count_right = count_r; + buf.autobuild.distance_left = dist_l; + buf.autobuild.distance_right = dist_r; + buf.autobuild.do_lintel = do_lintel; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_init(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_INIT; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_prepare_get_lintel(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PREPARE_GET_LINTEL; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_get_lintel(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_GET_LINTEL; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_put_lintel(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_PUT_LINTEL; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_clear(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_CLEAR; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_loaded(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_LOADED; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_store(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_STORE; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_mechboard_mode_lazy_pickup(void) +{ + struct i2c_cmd_mechboard_set_mode buf; + buf.hdr.cmd = I2C_CMD_MECHBOARD_SET_MODE; + buf.mode = I2C_MECHBOARD_MODE_LAZY_PICKUP; + return i2c_send_command(I2C_MECHBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_sensorboard_set_beacon(uint8_t enable) +{ + struct i2c_cmd_sensorboard_start_beacon buf; + buf.hdr.cmd = I2C_CMD_SENSORBOARD_SET_BEACON; + buf.enable = enable; + return i2c_send_command(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_sensorboard_scanner_set(uint8_t mode) +{ + struct i2c_cmd_sensorboard_scanner buf; + buf.hdr.cmd = I2C_CMD_SENSORBOARD_SET_SCANNER; + buf.mode = mode; + return i2c_send_command(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_sensorboard_scanner_calib(void) +{ + struct i2c_cmd_sensorboard_calib_scanner buf; + buf.hdr.cmd = I2C_CMD_SENSORBOARD_CALIB_SCANNER; + return i2c_send_command(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_sensorboard_scanner_algo_column(uint8_t zone, + int16_t x, int16_t y) +{ + struct i2c_cmd_sensorboard_scanner_algo buf; + buf.hdr.cmd = I2C_CMD_SENSORBOARD_SCANNER_ALGO; + buf.algo = I2C_SCANNER_ALGO_COLUMN_DROPZONE; + buf.drop_zone.working_zone = zone; + buf.drop_zone.center_x = x; + buf.drop_zone.center_y = y; + return i2c_send_command(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_sensorboard_scanner_algo_temple(uint8_t zone, + int16_t x, int16_t y) +{ + struct i2c_cmd_sensorboard_scanner_algo buf; + buf.hdr.cmd = I2C_CMD_SENSORBOARD_SCANNER_ALGO; + buf.algo = I2C_SCANNER_ALGO_TEMPLE_DROPZONE; + buf.drop_zone.working_zone = zone; + buf.drop_zone.center_x = x; + buf.drop_zone.center_y = y; + return i2c_send_command(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} + +int8_t i2c_sensorboard_scanner_algo_check(uint8_t level, + int16_t x, int16_t y) +{ + struct i2c_cmd_sensorboard_scanner_algo buf; + buf.hdr.cmd = I2C_CMD_SENSORBOARD_SCANNER_ALGO; + buf.algo = I2C_SCANNER_ALGO_CHECK_TEMPLE; + buf.check_temple.level = level; + buf.check_temple.temple_x = x; + buf.check_temple.temple_y = y; + return i2c_send_command(I2C_SENSORBOARD_ADDR, (uint8_t*)&buf, sizeof(buf)); +} diff --git a/projects/microb2009/mainboard/i2c_protocol.h b/projects/microb2009/mainboard/i2c_protocol.h new file mode 100644 index 0000000..0d40205 --- /dev/null +++ b/projects/microb2009/mainboard/i2c_protocol.h @@ -0,0 +1,92 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.h,v 1.6 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#ifndef _I2C_PROTOCOL_H_ +#define _I2C_PROTOCOL_H_ + +void i2c_protocol_init(void); +void i2c_protocol_debug(void); + +void i2cproto_wait_update(void); +void i2c_poll_slaves(void *dummy); + +void i2c_recvevent(uint8_t *buf, int8_t size); +void i2c_recvbyteevent(uint8_t hwstatus, uint8_t i, uint8_t c); +void i2c_sendevent(int8_t size); + +int8_t i2c_set_color(uint8_t addr, uint8_t color); +int8_t i2c_led_control(uint8_t addr, uint8_t led, uint8_t state); + +int8_t i2c_mechboard_mode_manual(void); +int8_t i2c_mechboard_mode_harvest(void); +int8_t i2c_mechboard_mode_lazy_harvest(void); +int8_t i2c_mechboard_mode_prepare_pickup(uint8_t side); +int8_t i2c_mechboard_mode_prepare_pickup_next(uint8_t side, uint8_t next_mode); +int8_t i2c_mechboard_mode_pickup(void); +int8_t i2c_mechboard_mode_eject(void); +int8_t i2c_mechboard_mode_lazy_pickup(void); + +int8_t i2c_mechboard_mode_prepare_build_both(uint8_t level); +int8_t i2c_mechboard_mode_prepare_build_select(int8_t level_l, int8_t level_r); +int8_t i2c_mechboard_mode_prepare_inside_both(uint8_t level); +int8_t i2c_mechboard_mode_prepare_inside_select(int8_t level_l, int8_t level_r); +int8_t i2c_mechboard_mode_simple_autobuild(uint8_t level); +int8_t i2c_mechboard_mode_autobuild(uint8_t level_l, uint8_t count_l, + uint8_t dist_l, + uint8_t level_r, uint8_t count_r, + uint8_t dist_r, + uint8_t do_lintel); +int8_t i2c_mechboard_mode_init(void); +int8_t i2c_mechboard_mode_eject(void); +int8_t i2c_mechboard_mode_prepare_get_lintel(void); +int8_t i2c_mechboard_mode_get_lintel(void); +int8_t i2c_mechboard_mode_put_lintel(void); +int8_t i2c_mechboard_mode_clear(void); +int8_t i2c_mechboard_mode_loaded(void); +int8_t i2c_mechboard_mode_store(void); +int8_t i2c_mechboard_mode_manivelle(void); +int8_t i2c_mechboard_mode_push_temple(uint8_t level); +int8_t i2c_mechboard_mode_push_temple_disc(uint8_t side); + +int8_t i2c_sensorboard_set_beacon(uint8_t enable); + +int8_t i2c_sensorboard_scanner_set(uint8_t mode); +static inline int8_t i2c_sensorboard_scanner_stop(void) { + return i2c_sensorboard_scanner_set(I2C_SENSORBOARD_SCANNER_STOP); +} +static inline int8_t i2c_sensorboard_scanner_start(void) { + return i2c_sensorboard_scanner_set(I2C_SENSORBOARD_SCANNER_START); +} +static inline int8_t i2c_sensorboard_scanner_prepare(void) { + return i2c_sensorboard_scanner_set(I2C_SENSORBOARD_SCANNER_PREPARE); +} + +int8_t i2c_sensorboard_scanner_calib(void); + +int8_t i2c_sensorboard_scanner_algo_column(uint8_t zone, + int16_t x, int16_t y); +int8_t i2c_sensorboard_scanner_algo_check(uint8_t level, + int16_t x, int16_t y); +int8_t i2c_sensorboard_scanner_algo_temple(uint8_t zone, + int16_t x, int16_t y); + + +#endif diff --git a/projects/microb2009/mainboard/main.c b/projects/microb2009/mainboard/main.c new file mode 100755 index 0000000..1b4d4b0 --- /dev/null +++ b/projects/microb2009/mainboard/main.c @@ -0,0 +1,295 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.10 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> +#include <avr/eeprom.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <i2c.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> +#include <adc.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "../common/eeprom_mapping.h" +#include "../common/i2c_commands.h" + +#include "main.h" +#include "ax12_user.h" +#include "strat.h" +#include "cmdline.h" +#include "sensor.h" +#include "actuator.h" +#include "cs.h" +#include "i2c_protocol.h" + +#if __AVR_LIBC_VERSION__ == 10602UL +#error "won't work with this version" +#endif + +/* 0 means "programmed" + * ---- with 16 Mhz quartz + * CKSEL 3-0 : 0111 + * SUT 1-0 : 10 + * CKDIV8 : 1 + * ---- bootloader + * BOOTZ 1-0 : 01 (4K bootloader) + * BOOTRST : 0 (reset on bootloader) + * ---- jtag + * jtagen : 0 + */ + +struct genboard gen; +struct mainboard mainboard; +struct mechboard mechboard; +struct sensorboard sensorboard; + +/***********************/ + +void bootloader(void) +{ +#define BOOTLOADER_ADDR 0x3f000 + if (pgm_read_byte_far(BOOTLOADER_ADDR) == 0xff) { + printf_P(PSTR("Bootloader is not present\r\n")); + return; + } + cli(); + BRAKE_ON(); + /* ... very specific :( */ + TIMSK0 = 0; + TIMSK1 = 0; + TIMSK2 = 0; + TIMSK3 = 0; + TIMSK4 = 0; + TIMSK5 = 0; + EIMSK = 0; + UCSR0B = 0; + UCSR1B = 0; + UCSR2B = 0; + UCSR3B = 0; + SPCR = 0; + TWCR = 0; + ACSR = 0; + ADCSRA = 0; + + EIND = 1; + __asm__ __volatile__ ("ldi r31,0xf8\n"); + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("eijmp\n"); + + /* never returns */ +} + +void do_time_monitor(void *dummy) +{ + uint16_t seconds; + seconds = eeprom_read_word(EEPROM_TIME_ADDRESS); + seconds ++; + eeprom_write_word(EEPROM_TIME_ADDRESS, seconds); +} + +void do_led_blink(void *dummy) +{ +#if 1 /* simple blink */ + LED1_TOGGLE(); +#endif +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + cpt++; + sei(); + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +int main(void) +{ + uint16_t seconds; + + /* brake */ + BRAKE_DDR(); + BRAKE_OFF(); + + /* CPLD reset on PG3 */ + DDRG |= 1<<3; + PORTG &= ~(1<<3); /* implicit */ + + /* LEDS */ + DDRJ |= 0x0c; + DDRL = 0xc0; + LED1_OFF(); + LED2_OFF(); + LED3_OFF(); + LED4_OFF(); + + memset(&gen, 0, sizeof(gen)); + memset(&mainboard, 0, sizeof(mainboard)); + mainboard.flags = DO_ENCODERS | DO_RS | + DO_POS | DO_POWER | DO_BD; + sensorboard.opponent_x = I2C_OPPONENT_NOT_THERE; + + /* UART */ + uart_init(); +#if CMDLINE_UART == 3 + fdevopen(uart3_dev_send, uart3_dev_recv); + uart_register_rx_event(3, emergency); +#elif CMDLINE_UART == 1 + fdevopen(uart1_dev_send, uart1_dev_recv); + uart_register_rx_event(1, emergency); +#else +# error not supported +#endif + + //eeprom_write_byte(EEPROM_MAGIC_ADDRESS, EEPROM_MAGIC_MAINBOARD); + /* check eeprom to avoid to run the bad program */ + if (eeprom_read_byte(EEPROM_MAGIC_ADDRESS) != + EEPROM_MAGIC_MAINBOARD) { + sei(); + printf_P(PSTR("Bad eeprom value\r\n")); + while(1); + } + + /* LOGS */ + error_register_emerg(mylog); + error_register_error(mylog); + error_register_warning(mylog); + error_register_notice(mylog); + error_register_debug(mylog); + + /* SPI + ENCODERS */ + encoders_spi_init(); /* this will also init spi hardware */ + + /* I2C */ + i2c_init(I2C_MODE_MASTER, I2C_MAINBOARD_ADDR); + i2c_protocol_init(); + i2c_register_recv_event(i2c_recvevent); + i2c_register_send_event(i2c_sendevent); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* PWM */ + PWM_NG_TIMER_16BITS_INIT(1, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_1); + PWM_NG_TIMER_16BITS_INIT(4, TIMER_16_MODE_PWM_10, + TIMER4_PRESCALER_DIV_1); + + PWM_NG_INIT16(&gen.pwm1_4A, 4, A, 10, PWM_NG_MODE_SIGNED | + PWM_NG_MODE_SIGN_INVERTED, &PORTD, 4); + PWM_NG_INIT16(&gen.pwm2_4B, 4, B, 10, PWM_NG_MODE_SIGNED | + PWM_NG_MODE_SIGN_INVERTED, &PORTD, 5); + PWM_NG_INIT16(&gen.pwm3_1A, 1, A, 10, PWM_NG_MODE_SIGNED, + &PORTD, 6); + PWM_NG_INIT16(&gen.pwm4_1B, 1, B, 10, PWM_NG_MODE_SIGNED, + &PORTD, 7); + + + /* servos */ + PWM_NG_TIMER_16BITS_INIT(3, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&gen.servo1, 3, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_TIMER_16BITS_INIT(5, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&gen.servo2, 5, A, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&gen.servo3, 5, B, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&gen.servo4, 5, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + pwm_ng_set(&gen.servo2, 290); /* right */ + pwm_ng_set(&gen.servo3, 400); /* left */ + /* 2 lintels 180, 485 */ + /* 1 lintel 155, 520 */ + + /* SCHEDULER */ + scheduler_init(); + + scheduler_add_periodical_event_priority(do_led_blink, NULL, + 100000L / SCHEDULER_UNIT, + LED_PRIO); + /* all cs management */ + microb_cs_init(); + + /* sensors, will also init hardware adc */ + sensor_init(); + + /* TIME */ + time_init(TIME_PRIO); + + /* start i2c slave polling */ + scheduler_add_periodical_event_priority(i2c_poll_slaves, NULL, + 8000L / SCHEDULER_UNIT, I2C_POLL_PRIO); + + /* strat */ + gen.logs[0] = E_USER_STRAT; + gen.log_level = 5; + strat_reset_infos(); + + /* strat-related event */ + scheduler_add_periodical_event_priority(strat_event, NULL, + 25000L / SCHEDULER_UNIT, + STRAT_PRIO); + + /* eeprom time monitor */ + scheduler_add_periodical_event_priority(do_time_monitor, NULL, + 1000000L / SCHEDULER_UNIT, + EEPROM_TIME_PRIO); + + sei(); + + printf_P(PSTR("\r\n")); + printf_P(PSTR("Respect et robustesse.\r\n")); + seconds = eeprom_read_word(EEPROM_TIME_ADDRESS); + printf_P(PSTR("Running since %d mn %d\r\n"), seconds/60, seconds%60); + cmdline_interact(); + + return 0; +} diff --git a/projects/microb2009/mainboard/main.h b/projects/microb2009/mainboard/main.h new file mode 100755 index 0000000..78fccc4 --- /dev/null +++ b/projects/microb2009/mainboard/main.h @@ -0,0 +1,227 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.h,v 1.10 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#define LED_TOGGLE(port, bit) do { \ + if (port & _BV(bit)) \ + port &= ~_BV(bit); \ + else \ + port |= _BV(bit); \ + } while(0) + +#define LED1_ON() sbi(PORTJ, 2) +#define LED1_OFF() cbi(PORTJ, 2) +#define LED1_TOGGLE() LED_TOGGLE(PORTJ, 2) + +#define LED2_ON() sbi(PORTL, 7) +#define LED2_OFF() cbi(PORTL, 7) +#define LED2_TOGGLE() LED_TOGGLE(PORTL, 7) + +#define LED3_ON() sbi(PORTJ, 3) +#define LED3_OFF() cbi(PORTJ, 3) +#define LED3_TOGGLE() LED_TOGGLE(PORTJ, 3) + +#define LED4_ON() sbi(PORTL, 6) +#define LED4_OFF() cbi(PORTL, 6) +#define LED4_TOGGLE() LED_TOGGLE(PORTL, 6) + +#define BRAKE_DDR() do { DDRJ |= 0xF0; } while(0) +#define BRAKE_ON() do { PORTJ |= 0xF0; } while(0) +#define BRAKE_OFF() do { PORTJ &= 0x0F; } while(0) + +/* only 90 seconds, don't forget it :) */ +#define MATCH_TIME 89 + +/* decrease track to decrease angle */ +#define EXT_TRACK_MM 302.0188 +#define VIRTUAL_TRACK_MM EXT_TRACK_MM + +#define ROBOT_LENGTH 320 +#define ROBOT_WIDTH 320 + +/* it is a 2048 imps -> 8192 because we see 1/4 period + * and diameter: 55mm -> perimeter 173mm + * 8192/173 -> 473 */ +/* increase it to go further */ +#define IMP_ENCODERS 2048 +#define WHEEL_DIAMETER_MM 55.0 +#define WHEEL_PERIM_MM (WHEEL_DIAMETER_MM * M_PI) +#define IMP_COEF 10. +#define DIST_IMP_MM (((IMP_ENCODERS*4) / WHEEL_PERIM_MM) * IMP_COEF) + +#define LEFT_ENCODER ((void *)1) +#define RIGHT_ENCODER ((void *)0) + +#define LEFT_PWM ((void *)&gen.pwm1_4A) +#define RIGHT_PWM ((void *)&gen.pwm2_4B) + +#define LEFT_PUMP1_PWM ((void *)&gen.pwm3_1A) +#define LEFT_PUMP2_PWM ((void *)&gen.pwm4_1B) + +/** ERROR NUMS */ +#define E_USER_STRAT 194 +#define E_USER_I2C_PROTO 195 +#define E_USER_SENSOR 196 +#define E_USER_CS 197 + +#define LED_PRIO 170 +#define TIME_PRIO 160 +#define ADC_PRIO 120 +#define CS_PRIO 100 +#define STRAT_PRIO 30 +#define I2C_POLL_PRIO 20 +#define EEPROM_TIME_PRIO 10 + +#define CS_PERIOD 5000L + +#define NB_LOGS 4 + +/* generic to all boards */ +struct genboard { + /* command line interface */ + struct rdline rdl; + char prompt[RDLINE_PROMPT_SIZE]; + + /* motors */ + struct pwm_ng pwm1_4A; + struct pwm_ng pwm2_4B; + struct pwm_ng pwm3_1A; + struct pwm_ng pwm4_1B; + + /* servos */ + struct pwm_ng servo1; + struct pwm_ng servo2; + struct pwm_ng servo3; + struct pwm_ng servo4; + + /* ax12 interface */ + AX12 ax12; + + /* log */ + uint8_t logs[NB_LOGS+1]; + uint8_t log_level; + uint8_t debug; +}; + +struct cs_block { + uint8_t on; + struct cs cs; + struct pid_filter pid; + struct quadramp_filter qr; + struct blocking_detection bd; +}; + +/* mainboard specific */ +struct mainboard { +#define DO_ENCODERS 1 +#define DO_CS 2 +#define DO_RS 4 +#define DO_POS 8 +#define DO_BD 16 +#define DO_TIMER 32 +#define DO_POWER 64 + uint8_t flags; /* misc flags */ + + /* control systems */ + struct cs_block angle; + struct cs_block distance; + + /* x,y positionning */ + struct robot_system rs; + struct robot_position pos; + struct trajectory traj; + + /* robot status */ + uint8_t our_color; + volatile int16_t speed_a; /* current angle speed */ + volatile int16_t speed_d; /* current dist speed */ + int32_t pwm_l; /* current left pwm */ + int32_t pwm_r; /* current right pwm */ + uint8_t enable_pickup_wheels; /* these PWM are on sensorboard */ + +}; + +/* state of mechboard, synchronized through i2c */ +struct mechboard { + uint8_t mode; + uint8_t status; + int8_t lintel_count; + uint8_t column_flags; + + /* pwm */ + int16_t pump_left1; + int16_t pump_right1; + int16_t pump_left2; + int16_t pump_right2; + + /* currents (for left arm, we can just read it on adc) */ + int16_t pump_right1_current; + int16_t pump_right2_current; + + /* pwm for lintel servos */ + uint16_t servo_lintel_left; + uint16_t servo_lintel_right; +}; + +/* state of sensorboard, synchronized through i2c */ +struct sensorboard { + uint8_t status; + /* opponent pos */ + int16_t opponent_x; + int16_t opponent_y; + int16_t opponent_a; + int16_t opponent_d; + + /* scanner */ +#define I2C_SCAN_DONE 1 + uint8_t scan_status; +#define I2C_COLUMN_NO_DROPZONE -1 + int8_t dropzone_h; + int16_t dropzone_x; + int16_t dropzone_y; +}; + +extern struct genboard gen; +extern struct mainboard mainboard; +extern struct mechboard mechboard; +extern struct sensorboard sensorboard; + +/* start the bootloader */ +void bootloader(void); + +#define WAIT_COND_OR_TIMEOUT(cond, timeout) \ +({ \ + microseconds __us = time_get_us2(); \ + uint8_t __ret = 1; \ + while(! (cond)) { \ + if (time_get_us2() - __us > (timeout)*1000L) {\ + __ret = 0; \ + break; \ + } \ + } \ + if (__ret) \ + DEBUG(E_USER_STRAT, "cond is true at line %d",\ + __LINE__); \ + else \ + DEBUG(E_USER_STRAT, "timeout at line %d", \ + __LINE__); \ + \ + __ret; \ +}) diff --git a/projects/microb2009/mainboard/obstacle_avoidance_config.h b/projects/microb2009/mainboard/obstacle_avoidance_config.h new file mode 100644 index 0000000..7306668 --- /dev/null +++ b/projects/microb2009/mainboard/obstacle_avoidance_config.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: obstacle_avoidance_config.h,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#define MAX_POLY 3 +#define MAX_PTS 12 +#define MAX_RAYS 150 +#define MAX_CHKPOINTS 7 diff --git a/projects/microb2009/mainboard/pid_config.h b/projects/microb2009/mainboard/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/projects/microb2009/mainboard/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/projects/microb2009/mainboard/rdline_config.h b/projects/microb2009/mainboard/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/mainboard/scheduler_config.h b/projects/microb2009/mainboard/scheduler_config.h new file mode 100755 index 0000000..daf5853 --- /dev/null +++ b/projects/microb2009/mainboard/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.2 2009-03-15 20:18:33 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 10 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/microb2009/mainboard/sensor.c b/projects/microb2009/mainboard/sensor.c new file mode 100644 index 0000000..6ecff35 --- /dev/null +++ b/projects/microb2009/mainboard/sensor.c @@ -0,0 +1,293 @@ +/* + * Copyright Droids Corporation (2009) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: sensor.c,v 1.8 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdlib.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <adc.h> +#include <scheduler.h> +#include <ax12.h> +#include <pwm_ng.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "main.h" +#include "sensor.h" + +/************ ADC */ + +struct adc_infos { + uint16_t config; + int16_t value; + int16_t prev_val; + int16_t (*filter)(struct adc_infos *, int16_t); +}; + +/* reach 90% of the value in 4 samples */ +int16_t rii_light(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + (int32_t)adc->prev_val / 2; + return adc->prev_val / 2; +} + +/* reach 90% of the value in 8 samples */ +int16_t rii_medium(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + ((int32_t)adc->prev_val * 3) / 4; + return adc->prev_val / 4; +} + +/* reach 90% of the value in 16 samples */ +int16_t rii_strong(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + ((int32_t)adc->prev_val * 7) / 8; + return adc->prev_val / 8; +} + + +#define ADC_CONF(x) ( ADC_REF_AVCC | ADC_MODE_INT | MUX_ADC##x ) + +/* define which ADC to poll, see in sensor.h */ +static struct adc_infos adc_infos[ADC_MAX] = { + [ADC_CSENSE1] = { .config = ADC_CONF(0), .filter = rii_medium }, + [ADC_CSENSE2] = { .config = ADC_CONF(1), .filter = rii_medium }, + [ADC_CSENSE3] = { .config = ADC_CONF(2), .filter = rii_medium }, + [ADC_CSENSE4] = { .config = ADC_CONF(3), .filter = rii_medium }, + [ADC_BATTERY1] = { .config = ADC_CONF(8), .filter = rii_strong }, + [ADC_BATTERY2] = { .config = ADC_CONF(9), .filter = rii_strong }, + + /* add adc on "cap" pins if needed */ +/* [ADC_CAP1] = { .config = ADC_CONF(10) }, */ +/* [ADC_CAP2] = { .config = ADC_CONF(11) }, */ +/* [ADC_CAP3] = { .config = ADC_CONF(12) }, */ +/* [ADC_CAP4] = { .config = ADC_CONF(13) }, */ +}; + +static void adc_event(int16_t result); + +/* called every 10 ms, see init below */ +static void do_adc(void *dummy) +{ + /* launch first conversion */ + adc_launch(adc_infos[0].config); +} + +static void adc_event(int16_t result) +{ + static uint8_t i = 0; + + /* filter value if needed */ + if (adc_infos[i].filter) + adc_infos[i].value = adc_infos[i].filter(&adc_infos[i], + result); + else + adc_infos[i].value = result; + + i ++; + if (i >= ADC_MAX) + i = 0; + else + adc_launch(adc_infos[i].config); +} + +int16_t sensor_get_adc(uint8_t i) +{ + int16_t tmp; + uint8_t flags; + + IRQ_LOCK(flags); + tmp = adc_infos[i].value; + IRQ_UNLOCK(flags); + return tmp; +} + +/************ boolean sensors */ + + +struct sensor_filter { + uint8_t filter; + uint8_t prev; + uint8_t thres_off; + uint8_t thres_on; + uint8_t cpt; + uint8_t invert; +}; + +/* pullup mapping: + * CAP 1,5,6,7,8 + */ +static struct sensor_filter sensor_filter[SENSOR_MAX] = { + [S_CAP1] = { 1, 0, 0, 1, 0, 0 }, /* 4 */ + [S_CAP2] = { 1, 0, 0, 1, 0, 0 }, /* 1 */ + [S_COLUMN_LEFT] = { 1, 0, 0, 1, 0, 1 }, /* 2 */ + [S_COLUMN_RIGHT] = { 1, 0, 0, 1, 0, 1 }, /* 3 */ + [S_START_SWITCH] = { 10, 0, 3, 7, 0, 0 }, /* 0 */ + [S_DISP_LEFT] = { 1, 0, 0, 1, 0, 1 }, /* 5 */ + [S_DISP_RIGHT] = { 1, 0, 0, 1, 0, 1 }, /* 6 */ + [S_CAP8] = { 1, 0, 0, 1, 0, 0 }, /* 7 */ + [S_RESERVED1] = { 10, 0, 3, 7, 0, 0 }, /* 8 */ + [S_RESERVED2] = { 10, 0, 3, 7, 0, 0 }, /* 9 */ + [S_RESERVED3] = { 1, 0, 0, 1, 0, 0 }, /* 10 */ + [S_RESERVED4] = { 1, 0, 0, 1, 0, 0 }, /* 11 */ + [S_RESERVED5] = { 1, 0, 0, 1, 0, 0 }, /* 12 */ + [S_RESERVED6] = { 1, 0, 0, 1, 0, 0 }, /* 13 */ + [S_RESERVED7] = { 1, 0, 0, 1, 0, 0 }, /* 14 */ + [S_RESERVED8] = { 1, 0, 0, 1, 0, 0 }, /* 15 */ +}; + +/* value of filtered sensors */ +static uint16_t sensor_filtered = 0; + +/* sensor mapping : + * 0-3: PORTK 2->5 (cap1 -> cap4) (adc10 -> adc13) + * 4-5: PORTL 0->1 (cap5 -> cap6) + * 6-7: PORTE 3->4 (cap7 -> cap8) + * 8-15: reserved + */ + +uint16_t sensor_get_all(void) +{ + uint16_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = sensor_filtered; + IRQ_UNLOCK(flags); + return tmp; +} + +uint8_t sensor_get(uint8_t i) +{ + uint16_t tmp = sensor_get_all(); + return (tmp & _BV(i)); +} + +/* get the physical value of pins */ +static uint16_t sensor_read(void) +{ + uint16_t tmp = 0; + tmp |= (uint16_t)((PINK & (_BV(2)|_BV(3)|_BV(4)|_BV(5))) >> 2) << 0; + tmp |= (uint16_t)((PINL & (_BV(0)|_BV(1))) >> 0) << 4; + tmp |= (uint16_t)((PINE & (_BV(3)|_BV(4))) >> 3) << 6; + /* add reserved sensors here */ + return tmp; +} + +/* called every 10 ms, see init below */ +static void do_boolean_sensors(void *dummy) +{ + uint8_t i; + uint8_t flags; + uint16_t sensor = sensor_read(); + uint16_t tmp = 0; + + for (i=0; i<SENSOR_MAX; i++) { + if ((1 << i) & sensor) { + if (sensor_filter[i].cpt < sensor_filter[i].filter) + sensor_filter[i].cpt++; + if (sensor_filter[i].cpt >= sensor_filter[i].thres_on) + sensor_filter[i].prev = 1; + } + else { + if (sensor_filter[i].cpt > 0) + sensor_filter[i].cpt--; + if (sensor_filter[i].cpt <= sensor_filter[i].thres_off) + sensor_filter[i].prev = 0; + } + + if (sensor_filter[i].prev) { + tmp |= (1UL << i); + } + } + IRQ_LOCK(flags); + sensor_filtered = tmp; + IRQ_UNLOCK(flags); +} + +/* virtual obstacle */ + +#define DISABLE_CPT_MAX 200 +static uint8_t disable = 0; /* used to disable obstacle detection + * during some time */ + +/* called every 10 ms */ +void +sensor_obstacle_update(void) +{ + if (disable > 0) { + disable --; + if (disable == 0) + DEBUG(E_USER_STRAT, "re-enable sensor"); + } +} + +void sensor_obstacle_disable(void) +{ + DEBUG(E_USER_STRAT, "disable sensor"); + disable = DISABLE_CPT_MAX; +} + +void sensor_obstacle_enable(void) +{ + disable = 0; +} + +uint8_t sensor_obstacle_is_disabled(void) +{ + return disable; +} + + +/************ global sensor init */ + +/* called every 10 ms, see init below */ +static void do_sensors(void *dummy) +{ + do_adc(NULL); + do_boolean_sensors(NULL); + sensor_obstacle_update(); +} + +void sensor_init(void) +{ + adc_init(); + adc_register_event(adc_event); + /* CS EVENT */ + scheduler_add_periodical_event_priority(do_sensors, NULL, + 10000L / SCHEDULER_UNIT, + ADC_PRIO); +} + diff --git a/projects/microb2009/mainboard/sensor.h b/projects/microb2009/mainboard/sensor.h new file mode 100644 index 0000000..0df5567 --- /dev/null +++ b/projects/microb2009/mainboard/sensor.h @@ -0,0 +1,62 @@ +/* + * Copyright Droids Corporation (2009) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: sensor.h,v 1.6 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +/* synchronize with sensor.c */ +#define ADC_CSENSE1 0 +#define ADC_CSENSE2 1 +#define ADC_CSENSE3 2 +#define ADC_CSENSE4 3 +#define ADC_BATTERY1 4 +#define ADC_BATTERY2 5 +#define ADC_MAX 6 + +/* synchronize with sensor.c */ +#define S_CAP1 0 +#define S_CAP2 1 +#define S_COLUMN_RIGHT 2 +#define S_COLUMN_LEFT 3 +#define S_START_SWITCH 4 +#define S_DISP_LEFT 5 +#define S_DISP_RIGHT 6 +#define S_CAP8 7 +#define S_RESERVED1 8 +#define S_RESERVED2 9 +#define S_RESERVED3 10 +#define S_RESERVED4 11 +#define S_RESERVED5 12 +#define S_RESERVED6 13 +#define S_RESERVED7 14 +#define S_RESERVED8 15 +#define SENSOR_MAX 16 + +void sensor_init(void); + +/* get filtered values for adc */ +int16_t sensor_get_adc(uint8_t i); + +/* get filtered values of boolean sensors */ +uint16_t sensor_get_all(void); +uint8_t sensor_get(uint8_t i); + +void sensor_obstacle_disable(void); +void sensor_obstacle_enable(void); +uint8_t sensor_obstacle_is_disabled(void); diff --git a/projects/microb2009/mainboard/spi_config.h b/projects/microb2009/mainboard/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/microb2009/mainboard/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/microb2009/mainboard/strat.c b/projects/microb2009/mainboard/strat.c new file mode 100644 index 0000000..3f54716 --- /dev/null +++ b/projects/microb2009/mainboard/strat.c @@ -0,0 +1,807 @@ +/* + * Copyright Droids, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat.c,v 1.6 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/queue.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <diagnostic.h> + +#include <rdline.h> +#include <parse.h> + +#include "../common/i2c_commands.h" +#include "i2c_protocol.h" +#include "main.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_utils.h" +#include "sensor.h" +#include "actuator.h" + +#define COL_DISP_MARGIN 400 /* stop 40 cm in front of dispenser */ +#define COL_SCAN_PRE_MARGIN 250 + + +#ifdef TEST_BEACON + +#define BEACON_MAX_SAMPLES 100 +struct beacon_sample { + int16_t posx; + int16_t posy; + int16_t posa; + int16_t oppx; + int16_t oppy; + uint8_t time; +}; + +static struct beacon_sample beacon_sample[BEACON_MAX_SAMPLES]; +static uint8_t beacon_prev_time = 0; +static uint8_t beacon_cur_idx = 0; + +static void beacon_update_samples(void) +{ + int16_t opp_a, opp_d, opp_x, opp_y; + int8_t err; + uint8_t time; + + time = time_get_s(); + + /* one sample per second max */ + if (time <= beacon_prev_time) + return; + /* limit max number of samples */ + if (beacon_cur_idx >= BEACON_MAX_SAMPLES) + return; + + memset(&beacon_sample[beacon_cur_idx], 0, sizeof(beacon_sample[beacon_cur_idx])); + beacon_prev_time = time; + beacon_sample[beacon_cur_idx].time = time; + + /* get opponent pos; if not found, just set struct to 0 */ + err = get_opponent_xyda(&opp_x, &opp_y, &opp_d, &opp_a); + if (err == -1) + return; + + beacon_sample[beacon_cur_idx].posx = position_get_x_s16(&mainboard.pos); + beacon_sample[beacon_cur_idx].posy = position_get_y_s16(&mainboard.pos); + beacon_sample[beacon_cur_idx].posa = position_get_a_deg_s16(&mainboard.pos); + beacon_sample[beacon_cur_idx].oppx = opp_x; + beacon_sample[beacon_cur_idx].oppy = opp_y; + beacon_cur_idx++; +} + +void beacon_dump_samples(void) +{ + uint16_t i; + + for (i=0; i<BEACON_MAX_SAMPLES; i++) { + printf_P(PSTR("%d: pos=(%d,%d,%d) opp=(%d,%d) time=%d\r\n"), + i, + beacon_sample[i].posx, + beacon_sample[i].posy, + beacon_sample[i].posa, + beacon_sample[i].oppx, + beacon_sample[i].oppy, + beacon_sample[i].time); + } +} +#endif + +struct strat_infos strat_infos = { + /* conf */ + .conf = { + .flags = 0, + /* scanner disabled by default */ + .scan_opp_min_time = 90, + .delay_between_opp_scan = 90, + .scan_our_min_time = 90, + .delay_between_our_scan = 90, + .wait_opponent = 0, + .lintel_min_time = 0, + .scan_opp_angle = -1, + }, + + /* static columns */ + .s_cols = { + .flags = 0, + .configuration = 0, + }, + + /* column dispensers ; be carreful, positions are + * color-dependent, so COLOR_Y() and COLOR_A() should be + * used. All angles here are _absolute_ */ + .c1 = { + .checkpoint_x = 2711 - COL_SCAN_PRE_MARGIN, + .checkpoint_y = AREA_Y - COL_DISP_MARGIN, + .scan_left = 0, + .scan_a = 180, + .eject_a = 180, + .recalib_x = 2711, + .recalib_y = AREA_Y - (ROBOT_LENGTH/2 + DIST_BACK_DISPENSER), + .pickup_a = 90, + .name = "col_disp1", + }, + .c2 = { + .checkpoint_x = AREA_X - COL_DISP_MARGIN, + .checkpoint_y = 800 - COL_SCAN_PRE_MARGIN, + .scan_left = 1, + .scan_a = -90, + .eject_a = -90, + .recalib_x = AREA_X - (ROBOT_LENGTH/2 + DIST_BACK_DISPENSER), + .recalib_y = 800, + .pickup_a = 0, + .name = "col_disp2", + }, + .c3 = { + .checkpoint_x = AREA_X-COL_DISP_MARGIN, + .checkpoint_y = 1300 + COL_SCAN_PRE_MARGIN, + .scan_a = 90, + .scan_left = 0, + .eject_a = -90, + .recalib_x = AREA_X - (ROBOT_LENGTH/2 + DIST_BACK_DISPENSER), + .recalib_y = 1300, + .pickup_a = 0, + .name = "col_disp3", + }, + + /* lintel dispensers */ + .l1 = { + .x = 912, /* XXX for red only */ + .name = "lin_disp1", + }, + .l2 = { + .x = 1312, /* XXX for red only */ + .name = "lin_disp2", + }, + + /* build zones */ + .zone_list = { +#define ZONE_DISC_NUM 0 + { + .flags = ZONE_F_VALID | ZONE_F_DISC, + .level = 2, + .checkpoint_x = 0, + .checkpoint_x = 0, + .name = "disc", + }, +#define ZONE_1A_NUM 1 + { + .flags = ZONE_F_VALID, + .level = 1, + .checkpoint_x = 1385, + .checkpoint_y = 1700, + .name = "z1a", + }, +#define ZONE_1B_NUM 2 + { + .flags = ZONE_F_VALID, + .level = 1, + .checkpoint_x = 1615, + .checkpoint_y = 1700, + .name = "z1b", + }, +#define ZONE_0B_NUM 3 + { + .flags = ZONE_F_VALID, + .level = 0, + .checkpoint_x = 2100, + .checkpoint_y = 1700, + .name = "z0b", + }, +#define ZONE_0A_NUM 4 + { + .flags = ZONE_F_VALID, + .level = 0, + .checkpoint_x = 900, + .checkpoint_y = 1700, + .name = "z0a", + }, + } +}; + +/*************************************************************/ + +/* INIT */ + +/*************************************************************/ + +void strat_set_bounding_box(void) +{ + if (get_color() == I2C_COLOR_RED) { + strat_infos.area_bbox.x1 = 300; + strat_infos.area_bbox.y1 = 200; + strat_infos.area_bbox.x2 = 2720; /* needed for c1 */ + strat_infos.area_bbox.y2 = 1800; + } + else { + strat_infos.area_bbox.x1 = 200; + strat_infos.area_bbox.y1 = 300; + strat_infos.area_bbox.x2 = 2720; /* needed for c1 */ + strat_infos.area_bbox.y2 = 1900; + } + + polygon_set_boundingbox(strat_infos.area_bbox.x1, + strat_infos.area_bbox.y1, + strat_infos.area_bbox.x2, + strat_infos.area_bbox.y2); +} + +/* called before each strat, and before the start switch */ +void strat_preinit(void) +{ + time_reset(); + interrupt_traj_reset(); + mainboard.flags = DO_ENCODERS | DO_CS | DO_RS | + DO_POS | DO_BD | DO_POWER; + + i2c_mechboard_mode_init(); + if (get_color() == I2C_COLOR_RED) + i2c_mechboard_mode_prepare_pickup(I2C_LEFT_SIDE); + else + i2c_mechboard_mode_prepare_pickup(I2C_RIGHT_SIDE); + + strat_dump_conf(); + strat_dump_infos(__FUNCTION__); +} + +void strat_dump_conf(void) +{ + if (!strat_infos.dump_enabled) + return; + + printf_P(PSTR("-- conf --\r\n")); + + printf_P(PSTR(" one build on disc: ")); + if (strat_infos.conf.flags & STRAT_CONF_ONLY_ONE_ON_DISC) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" bypass static2: ")); + if (strat_infos.conf.flags & STRAT_CONF_BYPASS_STATIC2) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" take one lintel: ")); + if (strat_infos.conf.flags & STRAT_CONF_TAKE_ONE_LINTEL) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" skip this temple when temple check fails: ")); + if (strat_infos.conf.flags & STRAT_CONF_SKIP_WHEN_CHECK_FAILS) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" store static2: ")); + if (strat_infos.conf.flags & STRAT_CONF_STORE_STATIC2) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" (big3) try to build a temple with 3 lintels: ")); + if (strat_infos.conf.flags & STRAT_CONF_BIG_3_TEMPLE) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" early opponent scan: ")); + if (strat_infos.conf.flags & STRAT_CONF_EARLY_SCAN) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" push opponent columns: ")); + if (strat_infos.conf.flags & STRAT_CONF_PUSH_OPP_COLS) + printf_P(PSTR("on\r\n")); + else + printf_P(PSTR("off\r\n")); + + printf_P(PSTR(" scan opponent min time: %d\r\n"), + strat_infos.conf.scan_opp_min_time); + printf_P(PSTR(" delay between oppnent scan: %d\r\n"), + strat_infos.conf.delay_between_opp_scan); + printf_P(PSTR(" scan our min time: %d\r\n"), + strat_infos.conf.scan_our_min_time); + printf_P(PSTR(" delay between our scan: %d\r\n"), + strat_infos.conf.delay_between_our_scan); + printf_P(PSTR(" wait opponent gone before scan: %d\r\n"), + strat_infos.conf.wait_opponent); + printf_P(PSTR(" lintel min time: %d\r\n"), + strat_infos.conf.lintel_min_time); + printf_P(PSTR(" scan_opp_angle: %d\r\n"), + strat_infos.conf.scan_opp_angle); +} + +void strat_dump_temple(struct temple *temple) +{ + if (!strat_infos.dump_enabled) + return; + + printf_P(PSTR(" temple %p (%s): "), temple, temple->zone->name); + + if (temple->flags & TEMPLE_F_MONOCOL) + printf_P(PSTR("MONOCOL ")); + else + printf_P(PSTR("BICOL ")); + + if (temple->flags & TEMPLE_F_ON_DISC) + printf_P(PSTR("ON_DISC ")); + else + printf_P(PSTR("ON_ZONE_0_1 ")); + + if (temple->flags & TEMPLE_F_OPPONENT) + printf_P(PSTR("OPPONENT ")); + else + printf_P(PSTR("OURS ")); + + if (temple->flags & TEMPLE_F_LINTEL) + printf_P(PSTR("LIN_ON_TOP ")); + else + printf_P(PSTR("COL_ON_TOP ")); + + printf_P(PSTR("\r\n")); + + printf_P(PSTR(" pos=(%d,%d,%d) ckpt=(%d,%d) ltime=%d\r\n"), + temple->x, temple->y, temple->a, + temple->checkpoint_x, temple->checkpoint_y, + temple->last_try_time); + printf_P(PSTR(" L: lev=%d da=%d,%d\r\n"), + temple->level_l, temple->dist_l, temple->angle_l); + printf_P(PSTR(" R: lev=%d da=%d,%d\r\n"), + temple->level_l, temple->dist_l, temple->angle_l); +} + +void strat_dump_zone(struct build_zone *zone) +{ + if (!strat_infos.dump_enabled) + return; + + printf_P(PSTR(" zone %s: "), zone->name); + + if (zone->flags & ZONE_F_DISC) + printf_P(PSTR("DISC ")); + else if (zone->flags & ZONE_F_ZONE1) + printf_P(PSTR("ZONE1 ")); + else if (zone->flags & ZONE_F_ZONE0) + printf_P(PSTR("ZONE0 ")); + + if (zone->flags & ZONE_F_BUSY) + printf_P(PSTR("BUSY ")); + else + printf_P(PSTR("FREE ")); + + printf_P(PSTR("\r\n")); + + printf_P(PSTR(" lev=%d ckpt=(%d,%d) ltime=%d\r\n"), + zone->level, + zone->checkpoint_x, zone->checkpoint_y, + zone->last_try_time); +} + +void strat_dump_static_cols(void) +{ + if (!strat_infos.dump_enabled) + return; + + printf_P(PSTR(" static cols: l0=%d l1=%d l2=%d\r\n"), + strat_infos.s_cols.flags & STATIC_COL_LINE0_DONE, + strat_infos.s_cols.flags & STATIC_COL_LINE1_DONE, + strat_infos.s_cols.flags & STATIC_COL_LINE2_DONE); +} + +void strat_dump_col_disp(void) +{ + if (!strat_infos.dump_enabled) + return; + + printf_P(PSTR(" c1 cnt=%d ltt=%d\r\n"), + strat_infos.c1.count, strat_infos.c1.last_try_time); + printf_P(PSTR(" c2 cnt=%d ltt=%d\r\n"), + strat_infos.c2.count, strat_infos.c2.last_try_time); + printf_P(PSTR(" c3 cnt=%d ltt=%d\r\n"), + strat_infos.c3.count, strat_infos.c3.last_try_time); +} + +void strat_dump_lin_disp(void) +{ + if (!strat_infos.dump_enabled) + return; + printf_P(PSTR(" l1 cnt=%d ltt=%d\r\n"), + strat_infos.l1.count, strat_infos.l1.last_try_time); + printf_P(PSTR(" l2 cnt=%d ltt=%d\r\n"), + strat_infos.l2.count, strat_infos.l2.last_try_time); + +} + +void strat_dump_all_temples(void) +{ + struct temple *temple; + uint8_t i; + + if (!strat_infos.dump_enabled) + return; + + for (i=0; i<MAX_TEMPLE; i++) { + temple = &strat_infos.temple_list[i]; + if (!(temple->flags & TEMPLE_F_VALID)) + continue; + strat_dump_temple(temple); + } +} + +void strat_dump_all_zones(void) +{ + struct build_zone *zone; + uint8_t i; + + if (!strat_infos.dump_enabled) + return; + + for (i=0; i<MAX_ZONE; i++) { + zone = &strat_infos.zone_list[i]; + if (!(zone->flags & ZONE_F_VALID)) + continue; + strat_dump_zone(zone); + } +} + +/* display current information about the state of the game */ +void strat_dump_infos(const char *caller) +{ + if (!strat_infos.dump_enabled) + return; + + printf_P(PSTR("%s() dump strat infos:\r\n"), caller); + strat_dump_static_cols(); + strat_dump_col_disp(); + strat_dump_lin_disp(); + strat_dump_all_temples(); + strat_dump_all_zones(); +} + +/* init current area state before a match. Dump update user conf + * here */ +void strat_reset_infos(void) +{ + uint8_t i; + + /* /!\ don't do a big memset() as there is static data */ + strat_infos.s_cols.flags = 0; + strat_infos.c1.count = 5; + strat_infos.c1.last_try_time = 0; + strat_infos.c2.count = 5; + strat_infos.c2.last_try_time = 0; + strat_infos.c3.count = 5; + strat_infos.c3.last_try_time = 0; + strat_infos.l1.count = 1; + strat_infos.l1.last_try_time = 0; + strat_infos.l2.count = 1; + strat_infos.l2.last_try_time = 0; + + strat_infos.taken_lintel = 0; + strat_infos.col_in_boobs = 0; + strat_infos.lazy_pickup_done = 0; + strat_infos.i2c_loaded_skipped = 0; + + memset(strat_infos.temple_list, 0, sizeof(strat_infos.temple_list)); + + for (i=0; i<MAX_ZONE; i++) + strat_infos.zone_list[i].flags = ZONE_F_VALID; + strat_infos.zone_list[ZONE_DISC_NUM].flags |= ZONE_F_DISC; + strat_infos.zone_list[ZONE_1A_NUM].flags |= ZONE_F_ZONE1; + strat_infos.zone_list[ZONE_1B_NUM].flags |= ZONE_F_ZONE1; + strat_infos.zone_list[ZONE_0A_NUM].flags |= ZONE_F_ZONE0; + strat_infos.zone_list[ZONE_0B_NUM].flags |= ZONE_F_ZONE0; + + strat_set_bounding_box(); + + /* set lintel position, depending on color */ + if (mainboard.our_color == I2C_COLOR_RED) { + strat_infos.l1.x = 912; + strat_infos.l2.x = 1312; + } + else { + strat_infos.l1.x = 888; + strat_infos.l2.x = 1288; + } +} + +/* call it just before launching the strat */ +void strat_init(void) +{ + pickup_wheels_on(); + strat_reset_infos(); + + /* we consider that the color is correctly set */ + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + time_reset(); + interrupt_traj_reset(); + + /* used in strat_base for END_TIMER */ + mainboard.flags = DO_ENCODERS | DO_CS | DO_RS | + DO_POS | DO_BD | DO_TIMER | DO_POWER; + +#ifdef TEST_BEACON + beacon_prev_time = 0; + beacon_cur_idx = 0; +#endif +} + + +/* call it after each strat */ +void strat_exit(void) +{ + uint8_t flags; + + pickup_wheels_off(); + mainboard.flags &= ~(DO_TIMER); + strat_hardstop(); + time_reset(); + wait_ms(1000); + IRQ_LOCK(flags); + mainboard.flags &= ~(DO_CS); + pwm_ng_set(LEFT_PWM, 0); + pwm_ng_set(RIGHT_PWM, 0); + IRQ_UNLOCK(flags); +} + +/* called periodically */ +void strat_event(void *dummy) +{ + /* limit speed when opponent is close */ + strat_limit_speed(); + +#ifdef TEST_BEACON + beacon_update_samples(); +#endif +} + +/* do static cols + first temples */ +static uint8_t strat_beginning(void) +{ + uint8_t err; + + /* don't limit the speed when opponent is near: it can change + * the radius of the curves */ + strat_limit_speed_disable(); + + err = strat_static_columns(0); + + strat_limit_speed_enable(); + + if (!TRAJ_SUCCESS(err)) + return err; + + /* go to disc to build the first temple */ + + /* XXX if opponent is near disc, go to zone1 */ + err = strat_goto_disc(2); + if (!TRAJ_SUCCESS(err)) + return err; + DEBUG(E_USER_STRAT, "disc reached"); + + /* can return END_ERROR or END_TIMER, should not happen + * here */ + err = strat_build_new_temple(&strat_infos.zone_list[0]); + if (!TRAJ_SUCCESS(err)) + return err; + + /* bypass static2 if specified */ + if (strat_infos.conf.flags & STRAT_CONF_BYPASS_STATIC2) { + err = strat_escape(&strat_infos.zone_list[0], TRAJ_FLAGS_STD); + return err; + } + + /* get the last 2 columns, and build them on previous temple */ + err = strat_static_columns_pass2(); + if (!TRAJ_SUCCESS(err)) + return err; + + /* early opponent scan, for offensive strategy */ + if (strat_infos.conf.flags & STRAT_CONF_EARLY_SCAN) { + err = strat_pickup_lintels(); + /* ignore code */ + + /* try to build on opponent (scan must be enabled) */ + err = strat_build_on_opponent_temple(); + /* ignore code */ + } + + return err; +} + +/* return true if we need to grab some more elements (lintel/cols) */ +uint8_t need_more_elements(void) +{ + if (time_get_s() <= 75) { + /* we have at least one col on each arm, build now */ + if ((get_column_count_left() >= 1) && + (get_column_count_right() >= 1)) + return 0; + } + else { + if (get_column_count()) + return 0; + } + return 1; +} + +/* dump state (every 5 s max) */ +#define DUMP_RATE_LIMIT(dump, last_print) \ + do { \ + if (time_get_s() - last_print > 5) { \ + dump(); \ + last_print = time_get_s(); \ + } \ + } while (0) + + +uint8_t strat_main(void) +{ + uint8_t err; + struct temple *temple = NULL; + struct build_zone *zone = NULL; + + uint8_t last_print_cols = 0; + uint8_t last_print_lin = 0; + uint8_t last_print_temple = 0; + uint8_t last_print_zone = 0; + + /* do static cols + first temple */ + err = strat_beginning(); + + /* skip error code */ + + while (1) { + + if (err == END_TIMER) { + DEBUG(E_USER_STRAT, "End of time"); + strat_exit(); + break; + } + + /* we have at least one col on each arm, build now */ + if (need_more_elements() == 0) { + + /* try to build on opponent, will return + * END_TRAJ without doing anything if + * disabled */ + err = strat_build_on_opponent_temple(); + if (!TRAJ_SUCCESS(err)) + continue; + if (need_more_elements()) + continue; + + /* try to scan and build on our temple, will + * return END_TRAJ without doing anything if + * disabled */ + err = strat_check_temple_and_build(); + if (!TRAJ_SUCCESS(err)) + continue; + if (need_more_elements()) + continue; + + /* Else, do a simple build, as before */ + + temple = strat_get_best_temple(); + + /* one valid temple found */ + if (temple) { + DUMP_RATE_LIMIT(strat_dump_all_temples, last_print_temple); + + err = strat_goto_temple(temple); + if (!TRAJ_SUCCESS(err)) + continue; + + /* can return END_ERROR or END_TIMER, + * should not happen here */ + err = strat_grow_temple(temple); + if (!TRAJ_SUCCESS(err)) + continue; + + err = strat_escape(temple->zone, TRAJ_FLAGS_STD); + if (!TRAJ_SUCCESS(err)) + continue; + + continue; + } + + zone = strat_get_best_zone(); + if (zone) { + DUMP_RATE_LIMIT(strat_dump_all_zones, last_print_zone); + + DEBUG(E_USER_STRAT, "goto zone %s", zone->name); + err = strat_goto_build_zone(zone, zone->level); + if (!TRAJ_SUCCESS(err)) + continue; + DEBUG(E_USER_STRAT, "zone reached"); + + /* no error code except END_ERROR, should not happen */ + err = strat_build_new_temple(zone); + + err = strat_escape(zone, TRAJ_FLAGS_STD); + if (!TRAJ_SUCCESS(err)) + continue; + + continue; + } + + /* XXX hey what can we do here... :'( */ + DEBUG(E_USER_STRAT, "panic :)"); + time_wait_ms(1000); + continue; + } + + /* else we need some elements (lintels, then columns) */ + else { + if (strat_infos.l1.count != 0 && strat_infos.l2.count != 0) + DUMP_RATE_LIMIT(strat_dump_lin_disp, last_print_lin); + + err = strat_pickup_lintels(); + /* can return an error code, but we have + * nothing to do because pickup_column() + * starts with a goto_and_avoid() */ + if (!TRAJ_SUCCESS(err)) + nop(); + + DUMP_RATE_LIMIT(strat_dump_col_disp, last_print_cols); + + err = strat_pickup_columns(); + if (!TRAJ_SUCCESS(err)) + nop(); /* nothing to do */ + + /* XXX check here that we have elements, or do + * something else */ + /* if we cannot take elements, try to build */ + } + } + return END_TRAJ; +} diff --git a/projects/microb2009/mainboard/strat.h b/projects/microb2009/mainboard/strat.h new file mode 100644 index 0000000..2b2b96a --- /dev/null +++ b/projects/microb2009/mainboard/strat.h @@ -0,0 +1,302 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat.h,v 1.7 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#ifndef _STRAT_H_ +#define _STRAT_H_ + +/* convert coords according to our color */ +#define COLOR_Y(y) ((mainboard.our_color==I2C_COLOR_RED)? (y) : (AREA_Y-(y))) +#define COLOR_A(a) ((mainboard.our_color==I2C_COLOR_RED)? (a) : (-a)) +#define COLOR_SIGN(x) ((mainboard.our_color==I2C_COLOR_RED)? (x) : (-x)) +#define COLOR_INVERT(x) ((mainboard.our_color==I2C_COLOR_RED)? (x) : (!x)) + +/* area */ +#define AREA_X 3000 +#define AREA_Y 2100 + +#define START_X 200 +#define START_Y COLOR_Y(200) +#define START_A COLOR_A(45) + +#define CENTER_X 1500 +#define CENTER_Y 1050 + +#define CORNER_X 3000 +#define CORNER_Y COLOR_Y(2100) + +/* + * /- line 0 + * | /- line 1 + * | | /- line 2 + * | | | + * +---C1--------------------------C1---+ + * | z0a z1 z0b | + * | . | + * | . | + * C3 0 1 2 ^ C3 + * y | 3 4 5 < > | + * C2 6 7 8 v C2 + * |------ 9 10 11 . ------| + * | | . | | + * | red | . |green| + * +-----+--L1--L2-------L2--L1---+-----+ + * x + */ + +/* static columns */ +#define LINE0_X 600 +#define LINE1_X 850 +#define LINE2_X 1100 + +#define COL0_X 600 +#define COL0_Y COLOR_Y(1175) +#define COL1_X 850 +#define COL1_Y COLOR_Y(1175) +#define COL2_X 1100 +#define COL2_Y COLOR_Y(1175) + +#define COL3_X 600 +#define COL3_Y COLOR_Y(975) +#define COL4_X 850 +#define COL4_Y COLOR_Y(975) +#define COL5_X 1100 +#define COL5_Y COLOR_Y(975) + +#define COL6_X 600 +#define COL6_Y COLOR_Y(775) +#define COL7_X 850 +#define COL7_Y COLOR_Y(775) +#define COL8_X 1100 +#define COL8_Y COLOR_Y(775) + +#define COL9_X 600 +#define COL9_Y COLOR_Y(575) +#define COL10_X 850 +#define COL10_Y COLOR_Y(575) +#define COL11_X 1100 +#define COL11_Y COLOR_Y(575) + +/* distance to go backward before pickup in dispenser */ +#define DIST_BACK_DISPENSER 35 + +/* diag of the pentagon (pentacle ?) */ +#define DISC_PENTA_DIAG 530 + +#define COL_DISP_MAX_TRIES 5 +#define LIN_DISP_MAX_TRIES 3 + +/* useful traj flags */ +#define TRAJ_SUCCESS(f) (f & (END_TRAJ|END_NEAR)) +#define TRAJ_FLAGS_STD (END_TRAJ|END_BLOCKING|END_NEAR|END_OBSTACLE|END_INTR|END_TIMER) +#define TRAJ_FLAGS_NO_TIMER (END_TRAJ|END_BLOCKING|END_NEAR|END_OBSTACLE|END_INTR) +#define TRAJ_FLAGS_NO_NEAR (END_TRAJ|END_BLOCKING|END_OBSTACLE|END_INTR|END_TIMER) +#define TRAJ_FLAGS_NO_NEAR_NO_TIMER (END_TRAJ|END_BLOCKING|END_OBSTACLE|END_INTR) +#define TRAJ_FLAGS_SMALL_DIST (END_TRAJ|END_BLOCKING|END_INTR) + +/* default speeds */ +#define SPEED_DIST_FAST 2500 +#define SPEED_ANGLE_FAST 2000 +#define SPEED_DIST_SLOW 1000 +#define SPEED_ANGLE_SLOW 1000 +#define SPEED_DIST_VERY_SLOW 400 +#define SPEED_ANGLE_VERY_SLOW 400 + +/* strat infos structures */ + +struct bbox { + int32_t x1; + int32_t y1; + int32_t x2; + int32_t y2; +}; + +struct conf { +#define STRAT_CONF_ONLY_ONE_ON_DISC 0x01 +#define STRAT_CONF_BYPASS_STATIC2 0x02 +#define STRAT_CONF_TAKE_ONE_LINTEL 0x04 +#define STRAT_CONF_SKIP_WHEN_CHECK_FAILS 0x08 +#define STRAT_CONF_STORE_STATIC2 0x10 +#define STRAT_CONF_BIG_3_TEMPLE 0x20 +#define STRAT_CONF_EARLY_SCAN 0x40 +#define STRAT_CONF_PUSH_OPP_COLS 0x80 + uint8_t flags; + uint8_t scan_opp_min_time; + uint8_t delay_between_opp_scan; + uint8_t scan_our_min_time; + uint8_t delay_between_our_scan; + uint8_t wait_opponent; + uint8_t lintel_min_time; + int16_t scan_opp_angle; +}; + +struct static_columns { +#define STATIC_COL_LINE0_DONE 0x01 +#define STATIC_COL_LINE1_DONE 0x02 +#define STATIC_COL_LINE2_DONE 0x04 + uint8_t flags; + uint8_t configuration; +}; + +struct column_dispenser { + int8_t count; + uint8_t last_try_time; + uint8_t scan_left; + int16_t checkpoint_x; + int16_t checkpoint_y; + int16_t scan_a; + int16_t eject_a; + int16_t pickup_a; + int16_t recalib_x; + int16_t recalib_y; + char *name; +}; + +struct lintel_dispenser { + int8_t count; + uint8_t last_try_time; + int16_t x; + char *name; +}; + +struct temple { +#define TEMPLE_F_VALID 0x01 /* structure is valid */ +#define TEMPLE_F_MONOCOL 0x02 /* temple has only one col */ +#define TEMPLE_F_ON_DISC 0x04 /* temple is on disc (else it's on other zone) */ +#define TEMPLE_F_OPPONENT 0x08 /* temple was originally built by opponent */ +#define TEMPLE_F_LINTEL 0x10 /* lintel on top (don't put another lintel) */ + + uint8_t flags; + /* position of the robot when we built it */ + int16_t x; + int16_t y; + int16_t a; + + /* position of the robot checkpoint */ + int16_t checkpoint_x; + int16_t checkpoint_y; + + /* position and level of each col */ + uint8_t level_l; + uint8_t dist_l; + uint8_t angle_l; + + uint8_t level_r; + uint8_t dist_r; + uint8_t angle_r; + +#define TEMPLE_DISABLE_TIME 5 + uint8_t last_try_time; + + struct build_zone *zone; +}; + +struct build_zone { +#define ZONE_F_VALID 0x01 /* zone is valid */ +#define ZONE_F_DISC 0x02 /* specific disc zone */ +#define ZONE_F_ZONE1 0x04 /* specific zone 1 */ +#define ZONE_F_ZONE0 0x08 /* specific zone 0 */ +#define ZONE_F_BUSY 0x10 /* this zone is busy */ + uint8_t flags; + uint8_t level; + int16_t checkpoint_x; + int16_t checkpoint_y; + +#define ZONE_DISABLE_TIME 5 + uint8_t last_try_time; + char *name; +}; + +#define MAX_TEMPLE 5 +#define MAX_ZONE 5 + +/* all infos related to strat */ +struct strat_infos { + uint8_t dump_enabled; + struct conf conf; + struct bbox area_bbox; + uint8_t taken_lintel; + uint8_t col_in_boobs; + uint8_t lazy_pickup_done; + uint8_t i2c_loaded_skipped; + struct static_columns s_cols; + struct column_dispenser c1; + struct column_dispenser c2; + struct column_dispenser c3; + struct lintel_dispenser l1; + struct lintel_dispenser l2; + struct build_zone zone_list[MAX_ZONE]; + struct temple temple_list[MAX_TEMPLE]; +}; +extern struct strat_infos strat_infos; + +/* in strat.c */ +void strat_dump_infos(const char *caller); /* show current known state + of area */ +void strat_dump_temple(struct temple *temple); +void strat_dump_conf(void); +void strat_reset_infos(void); /* reset current known state */ +void strat_preinit(void); +void strat_init(void); +void strat_exit(void); +void strat_dump_flags(void); +void strat_goto_near(int16_t x, int16_t y, uint16_t dist); +uint8_t strat_main(void); +void strat_event(void *dummy); + +/* in strat_static_columns.c */ +uint8_t strat_static_columns(uint8_t configuration); +uint8_t strat_static_columns_pass2(void); + +/* in strat_lintel.c */ +uint8_t strat_goto_lintel_disp(struct lintel_dispenser *disp); +uint8_t strat_pickup_lintels(void); + +/* in strat_column_disp.c */ +uint8_t strat_eject_col(int16_t eject_a, int16_t pickup_a); +uint8_t strat_pickup_columns(void); +uint8_t strat_goto_col_disp(struct column_dispenser **disp); + +/* in strat_building.c */ +uint8_t strat_goto_disc(int8_t level); +uint8_t strat_goto_build_zone(struct build_zone *build_zone, uint8_t level); +uint8_t strat_build_new_temple(struct build_zone *build_zone); +uint8_t strat_goto_temple(struct temple *temple); +uint8_t strat_grow_temple(struct temple *temple); +uint8_t strat_grow_temple_column(struct temple *temple); +struct temple *strat_get_best_temple(void); +struct temple *strat_get_our_temple_on_disc(uint8_t valid); +struct build_zone *strat_get_best_zone(void); +struct temple *strat_get_free_temple(void); + +/* in strat_scan.c */ +struct scan_disc_result; +void scanner_dump_state(void); +int8_t strat_scan_get_checkpoint(uint8_t mode, int16_t *ckpt_rel_x, + int16_t *ckpt_rel_y, int16_t *back_mm); +uint8_t strat_scan_disc(int16_t angle, uint8_t mode, + struct scan_disc_result *result); +uint8_t strat_goto_disc_angle(int16_t a_deg, int8_t level); +int16_t strat_get_temple_angle(struct temple *temple); +int16_t strat_temple_angle_to_scan_angle(int16_t temple_angle); +uint8_t strat_build_on_opponent_temple(void); +uint8_t strat_check_temple_and_build(void); + +#endif diff --git a/projects/microb2009/mainboard/strat_avoid.c b/projects/microb2009/mainboard/strat_avoid.c new file mode 100644 index 0000000..6e75dd0 --- /dev/null +++ b/projects/microb2009/mainboard/strat_avoid.c @@ -0,0 +1,535 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_avoid.c,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + +#include "main.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_utils.h" +#include "sensor.h" + +#define EDGE_NUMBER 5 +void set_rotated_pentagon(poly_t *pol, const point_t *robot_pt, + int16_t radius, int16_t x, int16_t y) +{ + + double c_a, s_a; + uint8_t i; + double px1, py1, px2, py2; + double a_rad; + + a_rad = atan2(y - robot_pt->y, x - robot_pt->x); + + /* generate pentagon */ + c_a = cos(-2*M_PI/EDGE_NUMBER); + s_a = sin(-2*M_PI/EDGE_NUMBER); + + /* + px1 = radius; + py1 = 0; + */ + px1 = radius * cos(a_rad + 2*M_PI/(2*EDGE_NUMBER)); + py1 = radius * sin(a_rad + 2*M_PI/(2*EDGE_NUMBER)); + + + for (i = 0; i < EDGE_NUMBER; i++){ + oa_poly_set_point(pol, x + px1, y + py1, i); + + px2 = px1*c_a + py1*s_a; + py2 = -px1*s_a + py1*c_a; + + px1 = px2; + py1 = py2; + } +} + +void set_rotated_poly(poly_t *pol, const point_t *robot_pt, + int16_t w, int16_t l, int16_t x, int16_t y) +{ + double tmp_x, tmp_y; + double a_rad; + + a_rad = atan2(y - robot_pt->y, x - robot_pt->x); + + DEBUG(E_USER_STRAT, "%s() x,y=%d,%d a_rad=%2.2f", + __FUNCTION__, x, y, a_rad); + + /* point 1 */ + tmp_x = w; + tmp_y = l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 0); + + /* point 2 */ + tmp_x = -w; + tmp_y = l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 1); + + /* point 3 */ + tmp_x = -w; + tmp_y = -l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 2); + + /* point 4 */ + tmp_x = w; + tmp_y = -l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 3); +} + +#define DISC_X CENTER_X +#define DISC_Y CENTER_Y + +void set_central_disc_poly(poly_t *pol, const point_t *robot_pt) +{ + set_rotated_pentagon(pol, robot_pt, DISC_PENTA_DIAG, + DISC_X, DISC_Y); +} + +#ifdef HOMOLOGATION +/* /!\ half size */ +#define O_WIDTH 400 +#define O_LENGTH 550 +#else +/* /!\ half size */ +#define O_WIDTH 360 +#define O_LENGTH 500 +#endif + +void set_opponent_poly(poly_t *pol, const point_t *robot_pt, int16_t w, int16_t l) +{ + int16_t x, y; + get_opponent_xy(&x, &y); + DEBUG(E_USER_STRAT, "oponent at: %d %d", x, y); + + /* place poly even if invalid, because it's -100 */ + set_rotated_poly(pol, robot_pt, w, l, x, y); +} + +/* don't care about polygons further than this distance for escape */ +#define ESCAPE_POLY_THRES 1000 + +/* don't reduce opp if opp is too far */ +#define REDUCE_POLY_THRES 600 + +/* has to be longer than any poly */ +#define ESCAPE_VECT_LEN 3000 + +/* + * Go in playground, loop until out of poly. The argument robot_pt is + * the pointer to the current position of the robot. + * Return 0 if there was nothing to do. + * Return 1 if we had to move. In this case, update the theorical + * position of the robot in robot_pt. + */ +static int8_t go_in_area(point_t *robot_pt) +{ + point_t poly_pts_area[4]; + poly_t poly_area; + point_t disc_pt, dst_pt; + + disc_pt.x = DISC_X; + disc_pt.y = DISC_Y; + + /* Go in playground */ + if (!is_in_boundingbox(robot_pt)){ + NOTICE(E_USER_STRAT, "not in playground %"PRIi32", %"PRIi32"", + robot_pt->x, robot_pt->y); + + poly_area.l = 4; + poly_area.pts = poly_pts_area; + poly_pts_area[0].x = strat_infos.area_bbox.x1; + poly_pts_area[0].y = strat_infos.area_bbox.y1; + + poly_pts_area[1].x = strat_infos.area_bbox.x2; + poly_pts_area[1].y = strat_infos.area_bbox.y1; + + poly_pts_area[2].x = strat_infos.area_bbox.x2; + poly_pts_area[2].y = strat_infos.area_bbox.y2; + + poly_pts_area[3].x = strat_infos.area_bbox.x1; + poly_pts_area[3].y = strat_infos.area_bbox.y2; + + is_crossing_poly(*robot_pt, disc_pt, &dst_pt, &poly_area); + NOTICE(E_USER_STRAT, "pt dst %"PRIi32", %"PRIi32"", dst_pt.x, dst_pt.y); + + strat_goto_xy_force(dst_pt.x, dst_pt.y); + + robot_pt->x = dst_pt.x; + robot_pt->y = dst_pt.y; + + NOTICE(E_USER_STRAT, "GOTO %"PRIi32",%"PRIi32"", + dst_pt.x, dst_pt.y); + + return 1; + } + + return 0; +} + + +/* + * Escape from polygons if needed. + * robot_pt is the current position of the robot, it will be + * updated. + */ +static int8_t escape_from_poly(point_t *robot_pt, + poly_t *pol_disc, + int16_t opp_x, int16_t opp_y, + int16_t opp_w, int16_t opp_l, + poly_t *pol_opp) +{ + uint8_t in_disc = 0, in_opp = 0; + double escape_dx = 0, escape_dy = 0; + double disc_dx = 0, disc_dy = 0; + double opp_dx = 0, opp_dy = 0; + double len; + point_t opp_pt, disc_pt, dst_pt; + point_t intersect_disc_pt, intersect_opp_pt; + + opp_pt.x = opp_x; + opp_pt.y = opp_y; + disc_pt.x = DISC_X; + disc_pt.y = DISC_Y; + + /* escape from other poly if necessary */ + if (is_in_poly(robot_pt, pol_disc) == 1) + in_disc = 1; + if (is_in_poly(robot_pt, pol_opp) == 1) + in_opp = 1; + + if (in_disc == 0 && in_opp == 0) { + NOTICE(E_USER_STRAT, "no need to escape"); + return 0; + } + + NOTICE(E_USER_STRAT, "in_disc=%d, in_opp=%d", in_disc, in_opp); + + /* process escape vector */ + + if (distance_between(robot_pt->x, robot_pt->y, DISC_X, DISC_Y) < ESCAPE_POLY_THRES) { + disc_dx = robot_pt->x - DISC_X; + disc_dy = robot_pt->y - DISC_Y; + NOTICE(E_USER_STRAT, " robot is near disc: vect=%2.2f,%2.2f", + disc_dx, disc_dy); + len = norm(disc_dx, disc_dy); + if (len != 0) { + disc_dx /= len; + disc_dy /= len; + } + else { + disc_dx = 1.0; + disc_dy = 0.0; + } + escape_dx += disc_dx; + escape_dy += disc_dy; + } + + if (distance_between(robot_pt->x, robot_pt->y, opp_x, opp_y) < ESCAPE_POLY_THRES) { + opp_dx = robot_pt->x - opp_x; + opp_dy = robot_pt->y - opp_y; + NOTICE(E_USER_STRAT, " robot is near opp: vect=%2.2f,%2.2f", + opp_dx, opp_dy); + len = norm(opp_dx, opp_dy); + if (len != 0) { + opp_dx /= len; + opp_dy /= len; + } + else { + opp_dx = 1.0; + opp_dy = 0.0; + } + escape_dx += opp_dx; + escape_dy += opp_dy; + } + + /* normalize escape vector */ + len = norm(escape_dx, escape_dy); + if (len != 0) { + escape_dx /= len; + escape_dy /= len; + } + else { + if (pol_disc != NULL) { + /* rotate 90° */ + escape_dx = disc_dy; + escape_dy = disc_dx; + } + else if (pol_opp != NULL) { + /* rotate 90° */ + escape_dx = opp_dy; + escape_dy = opp_dx; + } + else { /* should not happen */ + opp_dx = 1.0; + opp_dy = 0.0; + } + } + + NOTICE(E_USER_STRAT, " escape vect = %2.2f,%2.2f", + escape_dx, escape_dy); + + /* process the correct len of escape vector */ + + dst_pt.x = robot_pt->x + escape_dx * ESCAPE_VECT_LEN; + dst_pt.y = robot_pt->y + escape_dy * ESCAPE_VECT_LEN; + + NOTICE(E_USER_STRAT, "robot pt %"PRIi32" %"PRIi32, + robot_pt->x, robot_pt->y); + NOTICE(E_USER_STRAT, "dst point %"PRIi32",%"PRIi32, + dst_pt.x, dst_pt.y); + + if (in_disc) { + if (is_crossing_poly(*robot_pt, dst_pt, &intersect_disc_pt, + pol_disc) == 1) { + /* we add 2 mm to be sure we are out of th polygon */ + dst_pt.x = intersect_disc_pt.x + escape_dx * 2; + dst_pt.y = intersect_disc_pt.y + escape_dy * 2; + if (is_point_in_poly(pol_opp, dst_pt.x, dst_pt.y) != 1) { + + if (!is_in_boundingbox(&dst_pt)) + return -1; + + NOTICE(E_USER_STRAT, "GOTO %"PRIi32",%"PRIi32"", + dst_pt.x, dst_pt.y); + + strat_goto_xy_force(dst_pt.x, dst_pt.y); + + robot_pt->x = dst_pt.x; + robot_pt->y = dst_pt.y; + + return 0; + } + } + } + + if (in_opp) { + if (is_crossing_poly(*robot_pt, dst_pt, &intersect_opp_pt, + pol_opp) == 1) { + /* we add 2 cm to be sure we are out of th polygon */ + dst_pt.x = intersect_opp_pt.x + escape_dx * 2; + dst_pt.y = intersect_opp_pt.y + escape_dy * 2; + + if (is_point_in_poly(pol_disc, dst_pt.x, dst_pt.y) != 1) { + + if (!is_in_boundingbox(&dst_pt)) + return -1; + + NOTICE(E_USER_STRAT, "GOTO %"PRIi32",%"PRIi32"", + dst_pt.x, dst_pt.y); + + strat_goto_xy_force(dst_pt.x, dst_pt.y); + + robot_pt->x = dst_pt.x; + robot_pt->y = dst_pt.y; + + return 0; + } + } + } + + /* should not happen */ + return -1; +} + + +static int8_t __goto_and_avoid(int16_t x, int16_t y, + uint8_t flags_intermediate, + uint8_t flags_final, + uint8_t forward) +{ + int8_t len = -1, i; + point_t *p; + poly_t *pol_disc, *pol_opp; + int8_t ret; + int16_t opp_w, opp_l, opp_x, opp_y; + point_t p_dst, robot_pt; + + DEBUG(E_USER_STRAT, "%s(%d,%d) flags_i=%x flags_f=%x forw=%d", + __FUNCTION__, x, y, flags_intermediate, flags_final, forward); + + retry: + get_opponent_xy(&opp_x, &opp_y); + opp_w = O_WIDTH; + opp_l = O_LENGTH; + + robot_pt.x = position_get_x_s16(&mainboard.pos); + robot_pt.y = position_get_y_s16(&mainboard.pos); + + oa_init(); + pol_disc = oa_new_poly(5); + set_central_disc_poly(pol_disc, &robot_pt); + pol_opp = oa_new_poly(4); + set_opponent_poly(pol_opp, &robot_pt, O_WIDTH, O_LENGTH); + + /* If we are not in the limited area, try to go in it. */ + ret = go_in_area(&robot_pt); + + /* check that destination is valid */ + p_dst.x = x; + p_dst.y = y; + if (!is_in_boundingbox(&p_dst)) { + NOTICE(E_USER_STRAT, " dst is not in playground"); + return END_ERROR; + } + if (is_point_in_poly(pol_disc, x, y)) { + NOTICE(E_USER_STRAT, " dst is in disc"); + return END_ERROR; + } + if (is_point_in_poly(pol_opp, x, y)) { + NOTICE(E_USER_STRAT, " dst is in opp"); + return END_ERROR; + } + + /* now start to avoid */ + while (opp_w && opp_l) { + + /* robot_pt is not updated if it fails */ + ret = escape_from_poly(&robot_pt, + pol_disc, opp_x, opp_y, + opp_w, opp_l, pol_opp); + if (ret == 0) { + oa_reset(); + oa_start_end_points(robot_pt.x, robot_pt.y, x, y); + /* oa_dump(); */ + + len = oa_process(); + if (len >= 0) + break; + } + if (distance_between(robot_pt.x, robot_pt.y, opp_x, opp_y) < REDUCE_POLY_THRES ) { + if (opp_w == 0) + opp_l /= 2; + opp_w /= 2; + } + else { + NOTICE(E_USER_STRAT, "oa_process() returned %d", len); + return END_ERROR; + } + + NOTICE(E_USER_STRAT, "reducing opponent %d %d", opp_w, opp_l); + set_opponent_poly(pol_opp, &robot_pt, opp_w, opp_l); + } + + p = oa_get_path(); + for (i=0 ; i<len ; i++) { + DEBUG(E_USER_STRAT, "With avoidance %d: x=%"PRIi32" y=%"PRIi32"", i, p->x, p->y); + + if (forward) + trajectory_goto_forward_xy_abs(&mainboard.traj, p->x, p->y); + else + trajectory_goto_backward_xy_abs(&mainboard.traj, p->x, p->y); + + /* no END_NEAR for the last point */ + if (i == len - 1) + ret = wait_traj_end(flags_final); + else + ret = wait_traj_end(flags_intermediate); + + if (ret == END_BLOCKING) { + DEBUG(E_USER_STRAT, "Retry avoidance %s(%d,%d)", + __FUNCTION__, x, y); + goto retry; + } + else if (ret == END_OBSTACLE) { + /* brake and wait the speed to be slow */ + DEBUG(E_USER_STRAT, "Retry avoidance %s(%d,%d)", + __FUNCTION__, x, y); + goto retry; + } + /* else if it is not END_TRAJ or END_NEAR, return */ + else if (!TRAJ_SUCCESS(ret)) { + return ret; + } + p++; + } + + return END_TRAJ; +} + +/* go forward to a x,y point. use current speed for that */ +uint8_t goto_and_avoid_forward(int16_t x, int16_t y, uint8_t flags_intermediate, + uint8_t flags_final) +{ + return __goto_and_avoid(x, y, flags_intermediate, flags_final, 1); +} + +/* go backward to a x,y point. use current speed for that */ +uint8_t goto_and_avoid_backward(int16_t x, int16_t y, uint8_t flags_intermediate, + uint8_t flags_final) +{ + return __goto_and_avoid(x, y, flags_intermediate, flags_final, 0); +} + +/* go to a x,y point. prefer backward but go forward if the point is + * near and in front of us */ +uint8_t goto_and_avoid(int16_t x, int16_t y, uint8_t flags_intermediate, + uint8_t flags_final) +{ + double d,a; + abs_xy_to_rel_da(x, y, &d, &a); + + if (d < 300 && a < RAD(90) && a > RAD(-90)) + return __goto_and_avoid(x, y, flags_intermediate, + flags_final, 1); + else + return __goto_and_avoid(x, y, flags_intermediate, + flags_final, 0); +} diff --git a/projects/microb2009/mainboard/strat_avoid.h b/projects/microb2009/mainboard/strat_avoid.h new file mode 100644 index 0000000..0978fd7 --- /dev/null +++ b/projects/microb2009/mainboard/strat_avoid.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_avoid.h,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +void set_opponent_poly(poly_t *pol, int16_t w, int16_t l); +int8_t goto_and_avoid(int16_t x, int16_t y, uint8_t flags_intermediate, + uint8_t flags_final); +int8_t goto_and_avoid_backward(int16_t x, int16_t y, + uint8_t flags_intermediate, + uint8_t flags_final); +int8_t goto_and_avoid_forward(int16_t x, int16_t y, + uint8_t flags_intermediate, + uint8_t flags_final); diff --git a/projects/microb2009/mainboard/strat_base.c b/projects/microb2009/mainboard/strat_base.c new file mode 100644 index 0000000..21d526a --- /dev/null +++ b/projects/microb2009/mainboard/strat_base.c @@ -0,0 +1,512 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_base.c,v 1.8 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + +#include "../common/i2c_commands.h" + +#include "main.h" +#include "cmdline.h" +#include "strat_utils.h" +#include "strat_base.h" +#include "strat.h" +#include "sensor.h" +#include "i2c_protocol.h" + +/* true if we want to interrupt a trajectory */ +static uint8_t traj_intr=0; + +/* filled when a END_OBSTACLE is returned */ +struct opponent_obstacle opponent_obstacle; + +/* asked speed */ +static volatile int16_t strat_speed_a = SPEED_DIST_FAST; +static volatile int16_t strat_speed_d = SPEED_ANGLE_FAST; +static volatile uint16_t strat_limit_speed_a = 0; /* no limit */ +static volatile uint16_t strat_limit_speed_d = 0; + +static volatile uint8_t strat_limit_speed_enabled = 1; + + +/* Strings that match the end traj cause */ +/* /!\ keep it sync with stat_base.h */ +const char *err_tab []= { + "END_TRAJ", + "END_BLOCKING", + "END_NEAR", + "END_OBSTACLE", + "END_ERROR", + "END_INTR", + "END_TIMER", + "END_RESERVED", +}; + +/* return string from end traj type num */ +const char *get_err(uint8_t err) +{ + uint8_t i; + if (err == 0) + return "SUCCESS"; + for (i=0 ; i<8; i++) { + if (err & (1 <<i)) + return err_tab[i]; + } + return "END_UNKNOWN"; +} + +void strat_hardstop(void) +{ + trajectory_hardstop(&mainboard.traj); + pid_reset(&mainboard.angle.pid); + pid_reset(&mainboard.distance.pid); + bd_reset(&mainboard.angle.bd); + bd_reset(&mainboard.distance.bd); + + while ((ABS(mainboard.speed_d) > 200) || + (ABS(mainboard.speed_a) > 200)) + + trajectory_hardstop(&mainboard.traj); + pid_reset(&mainboard.angle.pid); + pid_reset(&mainboard.distance.pid); + bd_reset(&mainboard.angle.bd); + bd_reset(&mainboard.distance.bd); +} + +/* go to an x,y point without checking for obstacle or blocking. It + * should be used for very small dist only. Return END_TRAJ if we + * reach destination, or END_BLOCKING if the robot blocked more than 3 + * times. */ +uint8_t strat_goto_xy_force(int16_t x, int16_t y) +{ + uint8_t i, err; + +#ifdef HOMOLOGATION + int8_t serr; + uint8_t hardstop = 0; + microseconds us = time_get_us2(); + int16_t opp_a, opp_d, opp_x, opp_y; + + while (1) { + serr = get_opponent_xyda(&opp_x, &opp_y, + &opp_d, &opp_a); + if (serr == -1) + break; + if (opp_d < 600) + break; + if (hardstop == 0) { + strat_hardstop(); + hardstop = 1; + } + if ((time_get_us2() - us) > 3000000L) + break; + } +#endif + for (i=0; i<3; i++) { + trajectory_goto_xy_abs(&mainboard.traj, x, y); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (TRAJ_SUCCESS(err)) + return END_TRAJ; + if (err == END_BLOCKING) { + time_wait_ms(500); + strat_hardstop(); + } + } + return END_BLOCKING; +} + +/* reset position */ +void strat_reset_pos(int16_t x, int16_t y, int16_t a) +{ + int16_t posx = position_get_x_s16(&mainboard.pos); + int16_t posy = position_get_y_s16(&mainboard.pos); + int16_t posa = position_get_a_deg_s16(&mainboard.pos); + + if (x == DO_NOT_SET_POS) + x = posx; + if (y == DO_NOT_SET_POS) + y = posy; + if (a == DO_NOT_SET_POS) + a = posa; + + DEBUG(E_USER_STRAT, "reset pos (%s%s%s)", + x == DO_NOT_SET_POS ? "" : "x", + y == DO_NOT_SET_POS ? "" : "y", + a == DO_NOT_SET_POS ? "" : "a"); + position_set(&mainboard.pos, x, y, a); + DEBUG(E_USER_STRAT, "pos resetted", __FUNCTION__); +} + +/* + * decrease gain on angle PID, and go forward until we reach the + * border. + */ +uint8_t strat_calib(int16_t dist, uint8_t flags) +{ + int32_t p = pid_get_gain_P(&mainboard.angle.pid); + int32_t i = pid_get_gain_I(&mainboard.angle.pid); + int32_t d = pid_get_gain_D(&mainboard.angle.pid); + uint8_t err; + + pid_set_gains(&mainboard.angle.pid, 150, 0, 2000); + trajectory_d_rel(&mainboard.traj, dist); + err = wait_traj_end(flags); + pid_set_gains(&mainboard.angle.pid, p, i, d); + return err; +} + +/* escape from zone, and don't brake, so we can continue with another + * traj */ +uint8_t strat_escape(struct build_zone *zone, uint8_t flags) +{ + uint8_t err; + uint16_t old_spdd, old_spda; + + strat_get_speed(&old_spdd, &old_spda); + + err = WAIT_COND_OR_TIMEOUT(!opponent_is_behind(), 1000); + if (err == 0) { + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -150); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + strat_set_speed(old_spdd, old_spda); + return err; + } + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + if (zone->flags & ZONE_F_DISC) { + trajectory_d_rel(&mainboard.traj, -350); + err = WAIT_COND_OR_TRAJ_END(!robot_is_near_disc(), flags); + } + else { + trajectory_d_rel(&mainboard.traj, -300); + err = wait_traj_end(flags); + } + + strat_set_speed(old_spdd, old_spda); + if (err == 0) + return END_NEAR; + return err; +} + +static void strat_update_traj_speed(void) +{ + uint16_t d, a; + + d = strat_speed_d; + if (strat_limit_speed_d && d > strat_limit_speed_d) + d = strat_limit_speed_d; + a = strat_speed_a; + if (strat_limit_speed_a && a > strat_limit_speed_a) + a = strat_limit_speed_a; + + trajectory_set_speed(&mainboard.traj, d, a); +} + +void strat_set_speed(uint16_t d, uint16_t a) +{ + uint8_t flags; + IRQ_LOCK(flags); + strat_speed_d = d; + strat_speed_a = a; + strat_update_traj_speed(); + IRQ_UNLOCK(flags); +} + +void strat_get_speed(uint16_t *d, uint16_t *a) +{ + uint8_t flags; + IRQ_LOCK(flags); + *d = strat_speed_d; + *a = strat_speed_a; + IRQ_UNLOCK(flags); +} + +void strat_limit_speed_enable(void) +{ + strat_limit_speed_enabled = 1; +} + +void strat_limit_speed_disable(void) +{ + strat_limit_speed_enabled = 0; +} + +/* called periodically */ +void strat_limit_speed(void) +{ + uint16_t lim_d = 0, lim_a = 0; + int16_t opp_d, opp_a; + + if (strat_limit_speed_enabled == 0) + goto update; + + if (get_opponent_da(&opp_d, &opp_a) != 0) + goto update; + +#ifdef HOMOLOGATION + if (opp_d < 600) { + lim_d = 150; + lim_a = 200; + } +#else + if (opp_d < 500) { + if (mainboard.speed_d > 0 && (opp_a > 290 || opp_a < 70)) { + lim_d = SPEED_DIST_VERY_SLOW; + lim_a = SPEED_ANGLE_VERY_SLOW; + } + else if (mainboard.speed_d < 0 && (opp_a < 250 && opp_a > 110)) { + lim_d = SPEED_DIST_VERY_SLOW; + lim_a = SPEED_ANGLE_VERY_SLOW; + } + else { + lim_d = SPEED_DIST_SLOW; + lim_a = SPEED_ANGLE_VERY_SLOW; + } + } +#endif + else if (opp_d < 800) { + if (mainboard.speed_d > 0 && (opp_a > 290 || opp_a < 70)) { + lim_d = SPEED_DIST_SLOW; + lim_a = SPEED_ANGLE_SLOW; + } + else if (mainboard.speed_d < 0 && (opp_a < 250 && opp_a > 110)) { + lim_d = SPEED_DIST_SLOW; + lim_a = SPEED_ANGLE_SLOW; + } + } + + update: + if (lim_d != strat_limit_speed_d || + lim_a != strat_limit_speed_a) { + strat_limit_speed_d = lim_d; + strat_limit_speed_a = lim_a; + DEBUG(E_USER_STRAT, "new speed limit da=%d,%d", lim_d, lim_a); + strat_update_traj_speed(); + } +} + +/* start the strat */ +void strat_start(void) +{ + int8_t i; + uint8_t err; + + strat_preinit(); + + /* if start sw not plugged */ + if (sensor_get(S_START_SWITCH)) { + printf_P(PSTR("No start switch, press a key or plug it\r\n")); + + /* while start sw not plugged */ + while (sensor_get(S_START_SWITCH)) { + if (! cmdline_keypressed()) + continue; + + for (i=3; i>0; i--) { + printf_P(PSTR("%d\r\n"), i); + time_wait_ms(1000); + } + break; + } + } + + /* if start sw plugged */ + if (!sensor_get(S_START_SWITCH)) { + printf_P(PSTR("Ready, unplug start switch to start\r\n")); + /* while start sw plugged */ + while (!sensor_get(S_START_SWITCH)); + } + + strat_init(); + err = strat_main(); + NOTICE(E_USER_STRAT, "Finished !! returned %s", get_err(err)); + strat_exit(); +} + +/* return true if we have to brake due to an obstacle */ +uint8_t strat_obstacle(void) +{ + int16_t x_rel, y_rel; + int16_t opp_x, opp_y, opp_d, opp_a; + + /* too slow */ + if (ABS(mainboard.speed_d) < 150) + return 0; + + /* no opponent detected */ + if (get_opponent_xyda(&opp_x, &opp_y, + &opp_d, &opp_a)) + return 0; + + /* save obstacle position */ + opponent_obstacle.x = opp_x; + opponent_obstacle.y = opp_y; + opponent_obstacle.d = opp_d; + opponent_obstacle.a = opp_a; + + /* sensor are temporarily disabled */ + if (sensor_obstacle_is_disabled()) + return 0; + + /* relative position */ + x_rel = cos(RAD(opp_a)) * (double)opp_d; + y_rel = sin(RAD(opp_a)) * (double)opp_d; + + /* opponent too far */ + if (opp_d > 600) + return 0; + + /* opponent is in front of us */ + if (mainboard.speed_d > 0 && (opp_a > 325 || opp_a < 35)) { + DEBUG(E_USER_STRAT, "opponent front d=%d, a=%d " + "xrel=%d yrel=%d (speed_d=%d)", + opp_d, opp_a, x_rel, y_rel, mainboard.speed_d); + sensor_obstacle_disable(); + return 1; + } + /* opponent is behind us */ + if (mainboard.speed_d < 0 && (opp_a < 215 && opp_a > 145)) { + DEBUG(E_USER_STRAT, "opponent behind d=%d, a=%d xrel=%d yrel=%d", + opp_d, opp_a, x_rel, y_rel); + sensor_obstacle_disable(); + return 1; + } + + return 0; +} + +void interrupt_traj(void) +{ + traj_intr = 1; +} + +void interrupt_traj_reset(void) +{ + traj_intr = 0; +} + +uint8_t test_traj_end(uint8_t why) +{ + uint16_t cur_timer; + point_t robot_pt; + + robot_pt.x = position_get_x_s16(&mainboard.pos); + robot_pt.y = position_get_y_s16(&mainboard.pos); + + /* trigger an event at 3 sec before the end of the match if we + * have balls in the barrel */ + cur_timer = time_get_s(); + + if ((mainboard.flags & DO_TIMER) && (why & END_TIMER)) { + /* end of match */ + if (cur_timer >= MATCH_TIME) + return END_TIMER; + } + + if ((why & END_INTR) && traj_intr) { + interrupt_traj_reset(); + return END_INTR; + } + + if ((why & END_TRAJ) && trajectory_finished(&mainboard.traj)) + return END_TRAJ; + + /* we are near the destination point (depends on current + * speed) AND the robot is in the area bounding box. */ + if (why & END_NEAR) { + int16_t d_near = 100; + + if (mainboard.speed_d > 2000) + d_near = 150; + + if (trajectory_in_window(&mainboard.traj, d_near, RAD(5.0)) && + is_in_boundingbox(&robot_pt)) + return END_NEAR; + } + + if ((why & END_BLOCKING) && bd_get(&mainboard.angle.bd)) { + strat_hardstop(); + return END_BLOCKING; + } + + if ((why & END_BLOCKING) && bd_get(&mainboard.distance.bd)) { + strat_hardstop(); + return END_BLOCKING; + } + + if ((why & END_OBSTACLE) && strat_obstacle()) { + strat_hardstop(); + return END_OBSTACLE; + } + + return 0; +} + +uint8_t __wait_traj_end_debug(uint8_t why, uint16_t line) +{ + uint8_t ret = 0; + int16_t opp_x, opp_y, opp_d, opp_a; + + while (ret == 0) + ret = test_traj_end(why); + + if (ret == END_OBSTACLE) { + if (get_opponent_xyda(&opp_x, &opp_y, + &opp_d, &opp_a) == 0) + DEBUG(E_USER_STRAT, "Got %s at line %d" + " xy=(%d,%d) da=(%d,%d)", get_err(ret), + line, opp_x, opp_y, opp_d, opp_a); + } + else { + DEBUG(E_USER_STRAT, "Got %s at line %d", + get_err(ret), line); + } + return ret; +} diff --git a/projects/microb2009/mainboard/strat_base.h b/projects/microb2009/mainboard/strat_base.h new file mode 100644 index 0000000..27e1497 --- /dev/null +++ b/projects/microb2009/mainboard/strat_base.h @@ -0,0 +1,90 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_base.h,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +/* return values for strats and sub trajs */ +#define END_TRAJ 1 /* traj successful */ +#define END_BLOCKING 2 /* blocking during traj */ +#define END_NEAR 4 /* we are near destination */ +#define END_OBSTACLE 8 /* There is an obstacle in front of us */ +#define END_ERROR 16 /* Cannot do the command */ +#define END_INTR 32 /* interrupted by user */ +#define END_TIMER 64 /* we don't a lot of time */ +#define END_RESERVED 128 /* reserved */ + +/* only valid after a END_OBSTACLE */ +struct opponent_obstacle { + int16_t x; + int16_t y; + int16_t a; + int16_t d; +}; +extern struct opponent_obstacle opponent_obstacle; + +/* stop as fast as possible, without ramp */ +void strat_hardstop(void); + +#define DO_NOT_SET_POS -1000 +/* Reset position. If arg == DO_NOT_SET_POS, don't update value for + * it. */ +void strat_reset_pos(int16_t x, int16_t y, int16_t a); + +/* decrease gain on angle PID, and go forward until we reach the + * border. */ +uint8_t strat_calib(int16_t d, uint8_t flags); + +/* launch start procedure */ +void strat_start(void); + +/* go to an x,y point without checking for obstacle or blocking. It + * should be used for very small dist only. Return END_TRAJ if we + * reach destination, or END_BLOCKING if the robot blocked more than 3 + * times. */ +uint8_t strat_goto_xy_force(int16_t x, int16_t y); + +/* escape from disc polygon or another zone */ +struct build_zone; +uint8_t strat_escape(struct build_zone *zone, uint8_t flags); + +/* return true if we have to brake due to an obstacle */ +uint8_t strat_obstacle(void); + +/* set/get user strat speed */ +void strat_set_speed(uint16_t d, uint16_t a); +void strat_get_speed(uint16_t *d, uint16_t *a); + +/* when user type ctrl-c we can interrupt traj */ +void interrupt_traj(void); +void interrupt_traj_reset(void); + +/* limit speed when we are close of opponent */ +void strat_limit_speed_enable(void); +void strat_limit_speed_disable(void); +void strat_limit_speed(void); + +/* get name of traj error with its number */ +const char *get_err(uint8_t err); + +/* test trajectory end condition */ +uint8_t test_traj_end(uint8_t why); + +/* loop until test_traj_end() is true */ +#define wait_traj_end(why) __wait_traj_end_debug(why, __LINE__) +uint8_t __wait_traj_end_debug(uint8_t why, uint16_t line); diff --git a/projects/microb2009/mainboard/strat_building.c b/projects/microb2009/mainboard/strat_building.c new file mode 100644 index 0000000..9abdb5a --- /dev/null +++ b/projects/microb2009/mainboard/strat_building.c @@ -0,0 +1,907 @@ +/* + * Copyright Droids, Microb Technology (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_building.c,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/queue.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + + +#include "../common/i2c_commands.h" +#include "main.h" +#include "cmdline.h" +#include "i2c_protocol.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_utils.h" +#include "strat_avoid.h" +#include "sensor.h" + + +#define DISC_DIST_NEED_GOTO_AVOID 1000 +#define DISC_DIST_PREPARE_BUILD 700 +#define DISC_DIST_SLOW 500 + +#define ERROUT(e) do { \ + err = e; \ + goto end; \ + } while(0) + +static uint8_t is_ready_for_prepare_build(void) +{ + double d, a; + if (distance_from_robot(CENTER_X, CENTER_Y) > + DISC_DIST_PREPARE_BUILD) + return 0; + abs_xy_to_rel_da(CENTER_X, CENTER_Y, &d, &a); + if (a < RAD(-30)) + return 0; + if (a > RAD(30)) + return 0; + return 1; +} + +/* go to the nearest place on the disc. Also prepare the arms for + * building at the correct level. If level==-1, don't move the + * arms. */ +uint8_t strat_goto_disc(int8_t level) +{ + uint8_t err; + uint16_t old_spdd, old_spda; + double d, a, x, y; + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + /* workaround for some static cols configurations */ + if ((strat_infos.conf.flags & STRAT_CONF_EARLY_SCAN) == 0) { + if (time_get_s() > 15) + i2c_mechboard_mode_loaded(); + } + + /* if we are far from the disc, goto backward faster */ + abs_xy_to_rel_da(CENTER_X, CENTER_Y, &d, &a); + if (d > DISC_DIST_NEED_GOTO_AVOID) { + rel_da_to_abs_xy(d - DISC_DIST_PREPARE_BUILD, a, &x, &y); + err = goto_and_avoid(x, y, TRAJ_FLAGS_STD, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + } + +#ifdef HOMOLOGATION + { + int16_t opp_d, opp_a; + trajectory_turnto_xy(&mainboard.traj, + CENTER_X, CENTER_Y); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + + time_wait_ms(500); + + err = get_opponent_da(&opp_d, &opp_a); + if (err == 0 && opp_d < 600 && + (opp_a > 325 || opp_a < 35)) + return END_ERROR; + } +#endif + + trajectory_goto_forward_xy_abs(&mainboard.traj, + CENTER_X, CENTER_Y); + err = WAIT_COND_OR_TRAJ_END(is_ready_for_prepare_build(), + TRAJ_FLAGS_NO_NEAR); + + if (err == END_BLOCKING) + ERROUT(END_BLOCKING); + if (TRAJ_SUCCESS(err)) /* should not reach dest */ + ERROUT(END_ERROR); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + if (level != -1) + i2c_mechboard_mode_prepare_build_both(level); + + err = WAIT_COND_OR_TRAJ_END(distance_from_robot(CENTER_X, + CENTER_Y) < DISC_DIST_SLOW, + TRAJ_FLAGS_NO_NEAR); + + if (err == END_BLOCKING) + ERROUT(END_BLOCKING); + if (TRAJ_SUCCESS(err)) /* should not reach dest */ + ERROUT(END_ERROR); + + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_VERY_SLOW); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + if (err == END_BLOCKING) + ERROUT(END_TRAJ); + if (TRAJ_SUCCESS(err)) /* should not reach dest */ + ERROUT(END_ERROR); + + ERROUT(err); + end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* must be called from the checkpoint before zone 1. */ +static uint8_t strat_goto_build_zone1_near(uint8_t level) +{ + uint8_t err; + + /* turn to build zone */ + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + trajectory_a_abs(&mainboard.traj, COLOR_A(90)); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + return err; + + /* move forward to reach the build zone */ + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_SLOW); + i2c_mechboard_mode_prepare_build_both(level); + err = strat_calib(500, TRAJ_FLAGS_SMALL_DIST); + if (err == END_BLOCKING) { + err = END_TRAJ; + } + + DEBUG(E_USER_STRAT, "build zone reached"); + return err; +} + +/* must be called from the checkpoint before zone 0 */ +static uint8_t strat_goto_build_zone0_near(uint8_t level) +{ + uint8_t err; +#ifdef OLD_STYLE + int16_t cur_y, diff_y, dst_y; +#endif + + /* turn to build zone */ + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + trajectory_a_abs(&mainboard.traj, COLOR_A(90)); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + return err; + +#ifdef OLD_STYLE + cur_y = position_get_y_s16(&mainboard.pos); + dst_y = COLOR_Y(AREA_Y - (ROBOT_LENGTH/2) - 100); + diff_y = ABS(cur_y - dst_y); + + /* move forward to reach the build zone */ + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_SLOW); + i2c_mechboard_mode_prepare_build_both(level); + trajectory_d_rel(&mainboard.traj, diff_y); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (err == END_BLOCKING) { /* not very good for z0 but... */ + err = END_TRAJ; + } +#else + /* move forward to reach the build zone */ + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_SLOW); + i2c_mechboard_mode_prepare_build_both(level); + err = strat_calib(500, TRAJ_FLAGS_SMALL_DIST); + if (err == END_BLOCKING) { + err = END_TRAJ; + } +#endif + + DEBUG(E_USER_STRAT, "build zone reached"); + return err; +} + +/* Go to any build zone: disc, 1a or 1b. Doesn't work with zone 0 for + * now... */ +uint8_t strat_goto_build_zone(struct build_zone *zone, uint8_t level) +{ + uint8_t err = END_TRAJ; + uint16_t old_spdd, old_spda; + int16_t checkpoint_x, checkpoint_y; + int16_t errx; + + zone->last_try_time = time_get_s(); + + if (zone->flags & ZONE_F_DISC) + return strat_goto_disc(level); + + DEBUG(E_USER_STRAT, "goto build zone x=%d", zone->checkpoint_x); + + /* workaround for some static cols configurations */ + if (time_get_s() > 15) + i2c_mechboard_mode_loaded(); + + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + checkpoint_x = zone->checkpoint_x; + checkpoint_y = COLOR_Y(zone->checkpoint_y); + errx = position_get_x_s16(&mainboard.pos) - checkpoint_x; + + /* goto checkpoint if we are too far from it, or if error on x + * is too big. */ + if (distance_from_robot(checkpoint_x, checkpoint_y) > 300 || + ABS(errx) > 15) { + err = goto_and_avoid(checkpoint_x, checkpoint_y, + TRAJ_FLAGS_STD, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + } + + if (zone->flags & ZONE_F_ZONE1) + err = strat_goto_build_zone1_near(level); + else if (zone->flags & ZONE_F_ZONE0) + err = strat_goto_build_zone0_near(level); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* return a free temple structure */ +struct temple *strat_get_free_temple(void) +{ + uint8_t i; + + for (i=0; i<MAX_TEMPLE; i++) { + if (!(strat_infos.temple_list[i].flags & TEMPLE_F_VALID)) + return &strat_infos.temple_list[i]; + } + return NULL; +} + +uint8_t strat_can_build_on_temple(struct temple *temple) +{ + uint8_t col_l, col_r, max_col, lintel; + + col_l = get_column_count_left(); + col_r = get_column_count_right(); + max_col = (col_l > col_r ? col_l : col_r); + lintel = (get_lintel_count() > 0); + + if (strat_infos.conf.flags & STRAT_CONF_ONLY_ONE_ON_DISC) { + if ((temple->level_r > 5) && + (temple->flags & TEMPLE_F_ON_DISC)) + return 0; + } + + /* return symetric temples only */ + if (temple->level_l != temple->level_r) + return 0; + + if ((time_get_s() - temple->last_try_time) < TEMPLE_DISABLE_TIME) + return 0; + + /* we could do better to work on non-symetric temples */ + if (temple->level_l + max_col + lintel > 9) + return 0; + + if (temple->flags & TEMPLE_F_MONOCOL) + return 0; + + /* XXX don't allow to build on opponent temple. For that we + * must support the little back_mm. */ + if (temple->flags & TEMPLE_F_OPPONENT) + return 0; + + return 1; +} + + +/* return the best existing temple for building */ +struct temple *strat_get_best_temple(void) +{ + uint8_t i; + struct temple *best = NULL; + struct temple *temple = NULL; + + for (i=0; i<MAX_TEMPLE; i++) { + temple = &strat_infos.temple_list[i]; + + if (!(temple->flags & TEMPLE_F_VALID)) + continue; + + if (strat_can_build_on_temple(temple) == 0) + continue; + + if (best == NULL) { + best = temple; + continue; + } + + /* take the higher temple between 'best' and 'temple' */ + if (best->level_l < temple->level_l) + best = temple; + } + + DEBUG(E_USER_STRAT, "%s() return %p", __FUNCTION__, best); + return best; +} + +/* return the temple we built on the disc if any. If valid == 1, the + * temple must be buildable. */ +struct temple *strat_get_our_temple_on_disc(uint8_t valid) +{ + uint8_t i; + struct temple *temple = NULL; + + if (strat_infos.conf.flags & STRAT_CONF_ONLY_ONE_ON_DISC) { + return NULL; + } + + for (i=0; i<MAX_TEMPLE; i++) { + temple = &strat_infos.temple_list[i]; + + if (!(temple->flags & TEMPLE_F_VALID)) + continue; + + if (valid == 1 && strat_can_build_on_temple(temple) == 0) + continue; + + if (temple->flags & TEMPLE_F_ON_DISC) + return temple; + } + return NULL; +} + +#define COL_MAX(x,y) (((x)>(y)) ? (x) : (y)) + +#define TIME_FOR_LINTEL 3000L +#define TIME_FOR_BUILD 0L +#define TIME_FOR_COL 800L +#define TIME_MARGIN 2000L + +#define CHECKPOINT_DISC_DIST 380 +#define CHECKPOINT_OTHER_DIST 200 +/* Grow a temple. It will update temple list. */ +uint8_t strat_grow_temple(struct temple *temple) +{ + double checkpoint_x, checkpoint_y; + uint8_t add_level = 0; + uint8_t do_lintel = 1; + uint8_t col_l, col_r, col_max; + uint8_t err; + uint16_t timeout; + + /* XXX temple must be symetric */ + uint8_t level = temple->level_l; + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + + if (temple->level_l >= 9) + return END_ERROR; + + if ( (temple->zone->flags & ZONE_F_ZONE1) || + (temple->zone->flags & ZONE_F_ZONE0) ) { + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, -17); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + + col_l = get_column_count_left(); + col_r = get_column_count_right(); + + if (time_get_s() < 75) { + /* make temple symetric: if we have 1 col on left and 2 cols + * on right, only build one on both sides. */ + if (col_l > col_r) { + col_r = col_l; + do_lintel = 0; + } + if (col_r > col_l) { + col_r = col_l; + do_lintel = 0; + } + if (get_lintel_count() == 0) + do_lintel = 0; + } + else if (col_l != col_r) + do_lintel = 0; + + if (col_l == 0 || col_r == 0) { + if (temple->flags & TEMPLE_F_LINTEL) + do_lintel = 0; + } + + if (col_l == 0 && col_r == 0 && do_lintel == 0) { + DEBUG(E_USER_STRAT, "nothing to do"); + return END_ERROR; + } + + add_level = do_lintel + col_l; + while (level + add_level > 9) { + if (do_lintel) { + do_lintel = 0; + add_level = do_lintel + col_l; + continue; + } + /* we know col_r and col_l are > 0 */ + col_r--; + col_l--; + } + + col_max = COL_MAX(col_r, col_l); + + /* Reduce nb elts if we don't have time */ + timeout = (!!col_max) * TIME_FOR_BUILD; + timeout += col_max * TIME_FOR_COL; + timeout += do_lintel * TIME_FOR_LINTEL; + if ((timeout / 1000L) + time_get_s() > 89 && do_lintel) { + do_lintel = 0; + timeout -= TIME_FOR_LINTEL; + } + if ((timeout / 1000L) + time_get_s() > 89 && col_max) { + if (col_r > 0) + col_r--; + if (col_l > 0) + col_l--; + col_max--; + timeout -= TIME_FOR_COL; + } + + /* take a margin for timeout */ + timeout += (!!col_max) * TIME_MARGIN; + + if (col_l == 0 && col_r == 0 && do_lintel == 0) { + DEBUG(E_USER_STRAT, "nothing to do (2)"); + return END_ERROR; + } + + DEBUG(E_USER_STRAT, "Autobuild: left=%d,%d right=%d,%d lintel=%d", + level, col_l, level, col_r, do_lintel); + + i2c_mechboard_mode_autobuild(level, col_l, I2C_AUTOBUILD_DEFAULT_DIST, + level, col_r, I2C_AUTOBUILD_DEFAULT_DIST, + do_lintel); + WAIT_COND_OR_TIMEOUT(get_mechboard_mode() == + I2C_MECHBOARD_MODE_AUTOBUILD, 100); + err = WAIT_COND_OR_TIMEOUT(get_mechboard_mode() != + I2C_MECHBOARD_MODE_AUTOBUILD, timeout); + if (err == 0) { + DEBUG(E_USER_STRAT, "timeout building temple (timeout was %d)", timeout); + temple->flags = 0; /* remove temple from list */ + return END_TRAJ; + } + else + DEBUG(E_USER_STRAT, "temple built"); + + /* position of the robot when build the new temple */ + temple->x = position_get_x_s16(&mainboard.pos); + temple->y = position_get_y_s16(&mainboard.pos); + temple->a = position_get_a_deg_s16(&mainboard.pos); + + /* checkpoint is a bit behind us */ + if (temple->zone->flags & ZONE_F_DISC) { + rel_da_to_abs_xy(CHECKPOINT_DISC_DIST, M_PI, + &checkpoint_x, &checkpoint_y); + } + else { + rel_da_to_abs_xy(CHECKPOINT_OTHER_DIST, M_PI, + &checkpoint_x, &checkpoint_y); + } + temple->checkpoint_x = checkpoint_x; + temple->checkpoint_y = checkpoint_y; + + temple->level_l = level + add_level; + temple->dist_l = 0; + temple->angle_l = 0; + + temple->level_r = level + add_level; + temple->dist_r = 0; + temple->angle_r = 0; + + temple->flags = TEMPLE_F_VALID; + + if (distance_from_robot(CENTER_X, CENTER_Y) < 400) + temple->flags |= TEMPLE_F_ON_DISC; + + if (do_lintel) + temple->flags |= TEMPLE_F_LINTEL; + + /* we must push the temple */ + if ( ((temple->zone->flags & ZONE_F_ZONE1) || + (temple->zone->flags & ZONE_F_ZONE0)) && + level <= 1) { + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple(level); + time_wait_ms(400); + strat_set_speed(200, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + + /* Special case for big 3 */ + if (strat_infos.col_in_boobs) { + uint16_t old_spdd, old_spda; + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_SLOW); + DEBUG(E_USER_STRAT, "%s() big 3", __FUNCTION__); + strat_infos.col_in_boobs = 0; + trajectory_d_rel(&mainboard.traj, -120); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_prepare_pickup_next(I2C_AUTO_SIDE, + I2C_MECHBOARD_MODE_CLEAR); + WAIT_COND_OR_TIMEOUT(get_column_count() >= 2, 4000L); + i2c_mechboard_mode_prepare_build_both(level + add_level); + time_wait_ms(800); + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 120); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + err = strat_grow_temple(temple); + strat_set_speed(old_spdd, old_spda); + return err; + } + + return END_TRAJ; +} + +#define COL_BACK_DIST 70 +#define COL_ANGLE 20 +#define COL_ARM_DIST 220 + +#define COL_BACK_DIST_ZONE1 35 +#define COL_ARM_DIST_ZONE1 230 +#define COL_ANGLE_ZONE1 19 + +static uint8_t try_build_col(uint8_t l, uint8_t r, + uint8_t lp, uint8_t rp, + uint8_t lvl) +{ + uint8_t max_lvl = lvl + r + l; + + if (l == 0 && r == 0) + return 0; + if (lp - l == 2 && rp - r == 0) + return 0; + if (lp - l == 0 && rp - r == 2) + return 0; + if (max_lvl > 9) + return 0; + if (max_lvl == 9 && rp == 2 && r == 1) + return 0; + return max_lvl; +} + +/* Grow a temple by building a column on it. It will update temple + * list. */ +uint8_t strat_grow_temple_column(struct temple *temple) +{ + uint16_t old_spdd, old_spda; + double checkpoint_x, checkpoint_y; + uint8_t add_level = 0; + uint8_t col_l, col_r; + uint8_t col_l_before, col_r_before; + uint8_t err; + int16_t a_abs, a; + uint8_t level = temple->level_l; + uint8_t lvl_ok = 0, col_l_ok = 0, col_r_ok = 0; + uint8_t tmp_lvl; + int16_t col_arm_dist = COL_ARM_DIST; + int16_t col_back_dist = COL_BACK_DIST; + int16_t col_angle = COL_ANGLE; + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + + if (level >= 9) + return END_ERROR; + + strat_get_speed(&old_spdd, &old_spda); + + if ( (temple->zone->flags & ZONE_F_ZONE1) || + (temple->zone->flags & ZONE_F_ZONE0) ) { + if (level == 1) + col_arm_dist = COL_ARM_DIST_ZONE1; + col_back_dist = COL_BACK_DIST_ZONE1; + col_angle = COL_ANGLE_ZONE1; + } + + a_abs = position_get_a_deg_s16(&mainboard.pos); + + col_l_before = get_column_count_left(); + col_r_before = get_column_count_right(); + col_l = col_l_before; + col_r = col_r_before; + + /* check number of cols */ + for (col_l = 0; col_l < col_l_before + 1; col_l++) { + for (col_r = 0; col_r < col_r_before + 1; col_r++) { + tmp_lvl = try_build_col(col_l, col_r, + col_l_before, + col_r_before, level); + if (tmp_lvl > lvl_ok) { + lvl_ok = tmp_lvl; + col_l_ok = col_l; + col_r_ok = col_r; + } + } + } + + col_l = col_l_ok; + col_r = col_r_ok; + add_level = col_l + col_r; + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + + if (col_l == 0 && col_r == 0) + ERROUT(END_ERROR); + + DEBUG(E_USER_STRAT, "Build col: left=%d right=%d", + col_l, col_r); + + i2c_mechboard_mode_prepare_inside_both(level); + trajectory_d_rel(&mainboard.traj, -col_back_dist); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* build with left arm */ + if (col_l) { + a = a_abs - col_angle; + if (a < -180) + a += 360; + trajectory_a_abs(&mainboard.traj, a); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + if (time_get_s() > 88) + return END_TIMER; + + if (level >= 7 && get_column_count_left() == 2) + i2c_mechboard_mode_prepare_build_select(level+1, -1); + else + i2c_mechboard_mode_prepare_build_select(level, -1); + time_wait_ms(200); + i2c_mechboard_mode_autobuild(level, col_l, col_arm_dist, + 0, 0, col_arm_dist, 0); + while (get_mechboard_mode() != I2C_MECHBOARD_MODE_AUTOBUILD); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + if ((strat_infos.conf.flags & STRAT_CONF_PUSH_OPP_COLS) && + (col_r == 0) && + (temple->flags & TEMPLE_F_OPPONENT)) { + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple_disc(I2C_LEFT_SIDE); + time_wait_ms(500); + trajectory_d_rel(&mainboard.traj, 100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + else if ((level == 1 || level == 0) && (col_r == 0)) { + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple(level); + time_wait_ms(400); + strat_set_speed(200, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 120); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + + i2c_mechboard_mode_prepare_inside_select(level+col_l, -1); + } + + /* build with right arm */ + if (col_r) { + a = a_abs + col_angle; + if (a > 180) + a -= 360; + trajectory_a_abs(&mainboard.traj, a); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + if (time_get_s() > 88) + return END_TIMER; + + if ((level+col_l) >= 7 && get_column_count_right() == 2) + i2c_mechboard_mode_prepare_build_select(-1, level + col_l + 1); + else + i2c_mechboard_mode_prepare_build_select(-1, level + col_l); + time_wait_ms(200); + i2c_mechboard_mode_autobuild(0, 0, col_arm_dist, + level + col_l, col_r, + col_arm_dist, 0); + while (get_mechboard_mode() != I2C_MECHBOARD_MODE_AUTOBUILD); + while (get_mechboard_mode() == I2C_MECHBOARD_MODE_AUTOBUILD); + + if ((strat_infos.conf.flags & STRAT_CONF_PUSH_OPP_COLS) && + (temple->flags & TEMPLE_F_OPPONENT)) { + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple_disc(I2C_RIGHT_SIDE); + time_wait_ms(500); + trajectory_d_rel(&mainboard.traj, 100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + else if (level == 1 || level == 0) { + trajectory_d_rel(&mainboard.traj, -100); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + i2c_mechboard_mode_push_temple(level); + time_wait_ms(400); + strat_set_speed(200, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 120); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + + i2c_mechboard_mode_prepare_inside_select(-1, level + col_l + col_r); + + } + + trajectory_a_abs(&mainboard.traj, a_abs); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* position of the robot when build the new temple */ + temple->x = position_get_x_s16(&mainboard.pos); + temple->y = position_get_y_s16(&mainboard.pos); + temple->a = position_get_a_deg_s16(&mainboard.pos); + + /* checkpoint is a bit behind us */ + if (temple->zone->flags | ZONE_F_DISC) { + rel_da_to_abs_xy(CHECKPOINT_DISC_DIST, M_PI, + &checkpoint_x, &checkpoint_y); + } + else { + rel_da_to_abs_xy(CHECKPOINT_OTHER_DIST, M_PI, + &checkpoint_x, &checkpoint_y); + } + temple->checkpoint_x = checkpoint_x; + temple->checkpoint_y = checkpoint_y; + + temple->level_l = level + add_level; + temple->dist_l = 0; /* XXX */ + temple->angle_l = 0; + + temple->level_r = level + add_level; + temple->dist_r = 0; + temple->angle_r = 0; + + temple->flags = TEMPLE_F_VALID | TEMPLE_F_MONOCOL; + + if (distance_from_robot(CENTER_X, CENTER_Y) < 400) + temple->flags |= TEMPLE_F_ON_DISC; + + if ( (temple->zone->flags & ZONE_F_ZONE1) || + (temple->zone->flags & ZONE_F_ZONE0) ) { + + } + return END_TRAJ; + end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +uint8_t strat_build_new_temple(struct build_zone *zone) +{ + struct temple *temple; + uint8_t level = zone->level; + uint8_t err; + + /* create a dummy temple */ + temple = strat_get_free_temple(); + if (!temple) + return END_ERROR; + + memset(temple, 0, sizeof(*temple)); + temple->level_l = level; + temple->level_r = level; + temple->flags = TEMPLE_F_VALID | TEMPLE_F_LINTEL; + temple->zone = zone; + + zone->flags |= ZONE_F_BUSY; + + if (time_get_s() > 50 && time_get_s() < 85 && + get_lintel_count() == 0) + err = strat_grow_temple_column(temple); + else + err = strat_grow_temple(temple); + + if (!TRAJ_SUCCESS(err)) + temple->flags = 0; + return err; +} + +uint8_t strat_goto_temple(struct temple *temple) +{ + uint16_t old_spdd, old_spda; + uint8_t err; + + DEBUG(E_USER_STRAT, "goto temple %p checkpoint=%d,%d", + temple, temple->checkpoint_x, temple->checkpoint_y); + + temple->last_try_time = time_get_s(); + + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + i2c_mechboard_mode_loaded(); + + err = goto_and_avoid(temple->checkpoint_x, + temple->checkpoint_y, + TRAJ_FLAGS_STD, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + err = strat_goto_build_zone(temple->zone, temple->level_r); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + DEBUG(E_USER_STRAT, "zone reached"); + ERROUT(END_TRAJ); + + end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* return the best existing temple for building */ +struct build_zone *strat_get_best_zone(void) +{ + uint8_t i; + struct build_zone *zone = NULL; + + for (i=0; i<MAX_ZONE; i++) { + zone = &strat_infos.zone_list[i]; + + if (zone->flags & ZONE_F_BUSY) + continue; + if ((time_get_s() - zone->last_try_time) < ZONE_DISABLE_TIME) + continue; + + return zone; + } + return NULL; +} diff --git a/projects/microb2009/mainboard/strat_column_disp.c b/projects/microb2009/mainboard/strat_column_disp.c new file mode 100644 index 0000000..e0b481e --- /dev/null +++ b/projects/microb2009/mainboard/strat_column_disp.c @@ -0,0 +1,485 @@ +/* + * Copyright Droids, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_column_disp.c,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/queue.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "actuator.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_avoid.h" +#include "strat_utils.h" +#include "sensor.h" +#include "i2c_protocol.h" + +#define ERROUT(e) do { \ + err = e; \ + goto end; \ + } while(0) + +/* distance between the wheel axis and the IR sensor */ +#define IR_SHIFT_DISTANCE_RIGHT 85 +#define IR_SHIFT_DISTANCE_LEFT 95 + +/* return red or green sensor */ +#define COLOR_IR_SENSOR(left) \ + ({ \ + uint8_t __ret = 0; \ + if (left) \ + __ret = sensor_get(S_DISP_LEFT); \ + else \ + __ret = sensor_get(S_DISP_RIGHT); \ + \ + __ret; \ + }) \ + +/* eject one col, some error codes are ignored here: we want to be + * sure that the column is correctly ejected. */ +uint8_t strat_eject_col(int16_t eject_a, int16_t pickup_a) +{ + uint8_t err; + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -300); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + i2c_mechboard_mode_eject(); + time_wait_ms(600); + trajectory_a_abs(&mainboard.traj, eject_a); + + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST | END_NEAR); + i2c_mechboard_mode_clear(); + time_wait_ms(1000); + trajectory_a_abs(&mainboard.traj, pickup_a); + + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + return err; +} + +/* get columns from dispenser. Must be called when the robot is in + * front of the dispenser. */ +static uint8_t strat_pickup_col_disp(struct column_dispenser *disp) +{ + uint16_t old_spdd, old_spda; + int16_t recalib_x, recalib_y; + int16_t eject_a, pickup_a; + uint8_t err, timeout = 0; + int8_t cols_count_before, cols_count_after, cols; + microseconds us; + uint8_t first_try = 1; + uint8_t pickup_mode = I2C_MECHBOARD_MODE_PICKUP; + + /* XXX set lazy pickup mode */ + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + + strat_get_speed(&old_spdd, &old_spda); + + cols_count_before = get_column_count(); + pickup_a = COLOR_A(disp->pickup_a); + eject_a = COLOR_A(disp->eject_a); + recalib_x = disp->recalib_x; + recalib_y = COLOR_Y(disp->recalib_y); + + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + + /* turn to dispenser */ + i2c_mechboard_mode_prepare_pickup(I2C_AUTO_SIDE); + trajectory_a_abs(&mainboard.traj, pickup_a); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* go forward until blocking, then go back ~30mm */ + + pickup_wheels_on(); + retry: + if (time_get_s() > 86) { + DEBUG(E_USER_STRAT, "%s() too late...", __FUNCTION__); + return END_TIMER; + } + + if ((strat_infos.conf.flags & STRAT_CONF_BIG_3_TEMPLE) && + strat_infos.col_in_boobs == 0 && + strat_infos.lazy_pickup_done == 0) { + DEBUG(E_USER_STRAT, "%s() mode lazy", __FUNCTION__); + pickup_mode = I2C_MECHBOARD_MODE_LAZY_PICKUP; + strat_infos.col_in_boobs = 1; + strat_infos.lazy_pickup_done = 1; + } + else { + pickup_mode = I2C_MECHBOARD_MODE_PICKUP; + strat_infos.col_in_boobs = 0; + } + + if (first_try) + i2c_mechboard_mode_lazy_harvest(); + else + i2c_mechboard_mode_prepare_pickup(I2C_AUTO_SIDE); + first_try = 0; + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, 120); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + + err = strat_calib(600, TRAJ_FLAGS_SMALL_DIST); + + trajectory_d_rel(&mainboard.traj, -DIST_BACK_DISPENSER); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + if (get_mechboard_mode() == I2C_MECHBOARD_MODE_PREPARE_EJECT) { + strat_eject_col(eject_a, pickup_a); + goto retry; + } + + /* start to pickup with finger / arms */ + + DEBUG(E_USER_STRAT, "%s pickup now", __FUNCTION__); + + if (pickup_mode == I2C_MECHBOARD_MODE_PICKUP) + i2c_mechboard_mode_pickup(); + else + i2c_mechboard_mode_lazy_pickup(); + WAIT_COND_OR_TIMEOUT(get_mechboard_mode() == pickup_mode, 100); + us = time_get_us2(); + cols = get_column_count(); + while (get_mechboard_mode() == pickup_mode) { + if (get_column_count() != cols) { + cols = get_column_count(); + us = time_get_us2(); + } + if ((get_column_count() - cols_count_before) >= disp->count) { + DEBUG(E_USER_STRAT, "%s no more cols in disp", __FUNCTION__); + break; + } + /* 1 second timeout */ + if (time_get_us2() - us > 1000000L) { + DEBUG(E_USER_STRAT, "%s timeout", __FUNCTION__); + timeout = 1; + break; + } + } + + /* eject if we found a bad color column */ + + if (get_mechboard_mode() == I2C_MECHBOARD_MODE_PREPARE_EJECT) { + strat_eject_col(eject_a, pickup_a); + goto retry; + } + + /* only recalib if it was not a timeout or if we got at least + * 2 cols. */ + if (timeout == 0 || (get_column_count() - cols_count_before >= 2)) + strat_reset_pos(recalib_x, recalib_y, pickup_a); + else { + /* else just update x or y depending on disp */ + if (disp == &strat_infos.c1) + strat_reset_pos(recalib_x, DO_NOT_SET_POS, + DO_NOT_SET_POS); + else + strat_reset_pos(recalib_x, DO_NOT_SET_POS, + DO_NOT_SET_POS); + } + + /* go back */ + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -300); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST | END_NEAR); + + /* update dispenser count */ + + cols_count_after = get_column_count(); + cols = cols_count_after - cols_count_before; + if (cols > 0) { + DEBUG(E_USER_STRAT, "%s we got %d cols", __FUNCTION__, cols); + disp->count -= cols; + if (disp->count < 0) + disp->count = 0; + } + + pickup_wheels_off(); + if (pickup_mode == I2C_MECHBOARD_MODE_PICKUP) + i2c_mechboard_mode_clear(); + else + disp->count -= 2; + + ERROUT(END_TRAJ); + +end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* + * Go in front of a dispenser. It will update the dispenser if it is + * c2 or c3 if we detect that this dispenser does not exist. + */ +uint8_t strat_goto_col_disp(struct column_dispenser **pdisp) +{ + uint8_t err; + int16_t checkpoint_x, checkpoint_y; + int16_t scan_a; + uint16_t old_spdd, old_spda, scan_left; + int16_t pos1x, pos1y, pos2x, pos2y, pos, dist; + int16_t margin_col2, margin_col3; + struct column_dispenser *disp = *pdisp; + + if (disp->count <= 0) + return END_ERROR; + + if (disp->last_try_time >= time_get_s()) + return END_ERROR; + + disp->last_try_time = time_get_s(); + + strat_get_speed(&old_spdd, &old_spda); + + i2c_mechboard_mode_prepare_pickup_next(I2C_AUTO_SIDE, + I2C_MECHBOARD_MODE_CLEAR); + + /* set some useful variables */ + checkpoint_x = disp->checkpoint_x; + checkpoint_y = COLOR_Y(disp->checkpoint_y); + scan_a = COLOR_A(disp->scan_a); + scan_left = COLOR_INVERT(disp->scan_left); + + /* goto checkpoint */ + DEBUG(E_USER_STRAT, "%s(): goto %s (%d,%d) scan_left=%d", + __FUNCTION__, disp->name, checkpoint_x, + checkpoint_y, scan_left); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + +#if 0 + /* we have an intermediate checkpoint if we are on our + * side. If goto_and_avoid() returns END_ERROR, skip + * this checkpoint. */ + if (position_get_x_s16(&mainboard.pos) < 1500) { + err = goto_and_avoid(1000, COLOR_Y(1500), + TRAJ_FLAGS_STD, + TRAJ_FLAGS_STD); + if (!TRAJ_SUCCESS(err) && err != END_ERROR) + ERROUT(err); + } +#endif + /* go to checkpoint near the dispenser */ + err = goto_and_avoid(checkpoint_x, checkpoint_y, + TRAJ_FLAGS_STD, TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* turn to correct angle to prepare scanning */ + + trajectory_a_abs(&mainboard.traj, scan_a); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* scan now */ + + DEBUG(E_USER_STRAT, "%s(): scanning dispenser", __FUNCTION__); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -1000); + err = WAIT_COND_OR_TRAJ_END(!COLOR_IR_SENSOR(scan_left), + TRAJ_FLAGS_NO_NEAR); + if (err) /* we should not reach end */ + ERROUT(END_ERROR); + pos1x = position_get_x_s16(&mainboard.pos); + pos1y = position_get_y_s16(&mainboard.pos); + + err = WAIT_COND_OR_TRAJ_END(COLOR_IR_SENSOR(scan_left), + TRAJ_FLAGS_NO_NEAR); + if (err) + ERROUT(END_ERROR); + pos2x = position_get_x_s16(&mainboard.pos); + pos2y = position_get_y_s16(&mainboard.pos); + + dist = distance_between(pos1x, pos1y, pos2x, pos2y); + DEBUG(E_USER_STRAT, "%s(): scan done dist=%d", __FUNCTION__, dist); + + if (scan_left) + trajectory_d_rel(&mainboard.traj, -IR_SHIFT_DISTANCE_LEFT + dist/2); + else + trajectory_d_rel(&mainboard.traj, -IR_SHIFT_DISTANCE_RIGHT + dist/2); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + + if (disp == &strat_infos.c1) + ERROUT(END_TRAJ); + + /* mark c2 or c3 as empty... */ + if (strat_infos.c2.count == 0 || strat_infos.c3.count == 0) + ERROUT(END_TRAJ); + + pos = (pos2y + pos1y) / 2; + if (scan_a == 90) /* y is decreasing when scanning */ + pos -= 80; + else if (scan_a == -90) /* y is increasing when scanning */ + pos += 80; + + margin_col2 = ABS(pos - COLOR_Y(strat_infos.c2.recalib_y)); + margin_col3 = ABS(pos - COLOR_Y(strat_infos.c3.recalib_y)); + + if (margin_col3 > margin_col2) { + DEBUG(E_USER_STRAT, "%s(): delete disp c3 (scan_pos=%d)", __FUNCTION__, pos); + strat_infos.c3.count = 0; + *pdisp = &strat_infos.c2; + if (strat_infos.c3.last_try_time > strat_infos.c2.last_try_time) + strat_infos.c2.last_try_time = strat_infos.c3.last_try_time; + } + else { + DEBUG(E_USER_STRAT, "%s(): delete disp c2 (scan_pos=%d)", __FUNCTION__, pos); + strat_infos.c2.count = 0; + *pdisp = &strat_infos.c3; + if (strat_infos.c2.last_try_time > strat_infos.c3.last_try_time) + strat_infos.c3.last_try_time = strat_infos.c2.last_try_time; + } + ERROUT(END_TRAJ); + +end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* return the best dispenser between the 2 */ +static struct column_dispenser * +strat_disp_compare(struct column_dispenser *a, + struct column_dispenser *b) +{ + uint8_t want_cols = 4 - get_column_count(); + + DEBUG(E_USER_STRAT, "%s() want_cols=%d", __FUNCTION__, want_cols); + + /* an empty dispenser is not valid */ + if (a->count == 0) + return b; + if (b->count == 0) + return a; + + /* try to do a round robin: this is not optimal, but at least + * we will try another dispenser when one fails. */ + if (a->last_try_time < b->last_try_time) { + return a; + } + if (b->last_try_time < a->last_try_time) { + return b; + } + + /* take the one with the most columns */ + if (a->count >= want_cols && b->count < want_cols) + return a; + + /* take the one with the most columns */ + if (b->count >= want_cols && a->count < want_cols) + return b; + + /* the closer is the better */ + if (distance_from_robot(a->recalib_x, COLOR_Y(a->recalib_y)) < + distance_from_robot(b->recalib_x, COLOR_Y(b->recalib_y))) { + return a; + } + return b; +} + +/* choose the best dispenser */ +static struct column_dispenser *strat_get_best_col_disp(void) +{ + struct column_dispenser *disp; + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + + /* for the first call, use c3 */ + if (strat_infos.c1.last_try_time == 0 && + strat_infos.c2.last_try_time == 0 && + strat_infos.c3.last_try_time == 0) + return &strat_infos.c2; // XXX c3 + + DEBUG(E_USER_STRAT, "%s(): compare values", __FUNCTION__); + + /* else compare with standard conditions */ + disp = strat_disp_compare(&strat_infos.c1, &strat_infos.c2); + disp = strat_disp_compare(disp, &strat_infos.c3); + + if (disp->count == 0) + return NULL; + + return disp; +} + +/* choose the best dispenser, depending on disp count, distance, + * tries, ... and go pickup on it. */ +uint8_t strat_pickup_columns(void) +{ + struct column_dispenser *disp; + uint8_t err; + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + disp = strat_get_best_col_disp(); + + if (disp == NULL) { + DEBUG(E_USER_STRAT, "%s(): no col disp found", __FUNCTION__); + return END_ERROR; + } + + err = strat_goto_col_disp(&disp); + if (!TRAJ_SUCCESS(err)) + return err; + + err = strat_pickup_col_disp(disp); + if (!TRAJ_SUCCESS(err)) + return err; + + return END_TRAJ; +} diff --git a/projects/microb2009/mainboard/strat_lintel.c b/projects/microb2009/mainboard/strat_lintel.c new file mode 100644 index 0000000..72ab299 --- /dev/null +++ b/projects/microb2009/mainboard/strat_lintel.c @@ -0,0 +1,247 @@ +/* + * Copyright Droids, Microb Technology (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_lintel.c,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/queue.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_avoid.h" +#include "strat_utils.h" +#include "sensor.h" +#include "i2c_protocol.h" + +#define ERROUT(e) do { \ + err = e; \ + goto end; \ + } while(0) + +#define X_PRE_MARGIN 20 +#define X_POST_MARGIN 10 + +/* + * goto lintel disp. Return END_TRAJ if success or if there is nothing + * to do. Return END_ERROR if dest cannot be reached, else, it may + * return END_OBSTACLE or END_BLOCKING. + */ +uint8_t strat_goto_lintel_disp(struct lintel_dispenser *disp) +{ + uint8_t err, first_try = 1, right_ok, left_ok; + uint16_t old_spdd, old_spda; + int16_t left_cur, right_cur, a; + + if (disp->count == 0) + return END_ERROR; + + if (get_lintel_count() == 2) + return END_ERROR; + + if (disp->last_try_time >= time_get_s()) + return END_ERROR; + + disp->last_try_time = time_get_s(); + + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + DEBUG(E_USER_STRAT, "%s(): goto %s", __FUNCTION__, disp->name); + i2c_mechboard_mode_prepare_pickup(I2C_AUTO_SIDE); + + err = goto_and_avoid_backward(disp->x, COLOR_Y(400), + TRAJ_FLAGS_STD, TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + trajectory_a_abs(&mainboard.traj, COLOR_A(-90)); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + if (time_get_s() > 86) { + DEBUG(E_USER_STRAT, "%s() too late...", __FUNCTION__); + return END_TIMER; + } + + i2c_mechboard_mode_prepare_get_lintel(); + retry: + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_FAST); + err = strat_calib(500, TRAJ_FLAGS_SMALL_DIST); + if (err == END_BLOCKING) { + a = position_get_a_deg_s16(&mainboard.pos); + /* only reset pos if angle is not too different */ + if (ABS(a - COLOR_A(-90)) < 5) + strat_reset_pos(DO_NOT_SET_POS, + COLOR_Y(ROBOT_LENGTH/2), + COLOR_A(-90)); + } + else if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + i2c_mechboard_mode_get_lintel(); + time_wait_ms(500); + + left_cur = sensor_get_adc(ADC_CSENSE3); + left_ok = (left_cur > I2C_MECHBOARD_CURRENT_COLUMN); + right_cur = mechboard.pump_right1_current; + right_ok = (right_cur > I2C_MECHBOARD_CURRENT_COLUMN); + + DEBUG(E_USER_STRAT, "%s left_ok=%d (%d), right_ok=%d (%d)", __FUNCTION__, + left_ok, left_cur, right_ok, right_cur); + if (first_try) { + if (!right_ok && !left_ok) { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + } + /* XXX recalib x ? */ + else if (right_ok && !left_ok) { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + strat_set_speed(500, 500); + trajectory_d_a_rel(&mainboard.traj, -200, 30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + trajectory_d_a_rel(&mainboard.traj, 190, -30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + first_try = 0; + goto retry; + } + else if (!right_ok && left_ok) { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + strat_set_speed(500, 500); + trajectory_d_a_rel(&mainboard.traj, -200, -30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + trajectory_d_a_rel(&mainboard.traj, 190, 30); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + first_try = 0; + goto retry; + } + /* else, lintel is ok */ + else { + strat_infos.taken_lintel ++; + i2c_mechboard_mode_put_lintel(); + } + } + else { + if (right_ok && left_ok) { + /* lintel is ok */ + strat_infos.taken_lintel ++; + i2c_mechboard_mode_put_lintel(); + } + else { + i2c_mechboard_mode_prepare_get_lintel(); + time_wait_ms(300); + } + } + disp->count--; + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + trajectory_d_rel(&mainboard.traj, -250); + err = wait_traj_end(TRAJ_FLAGS_STD); + + ERROUT(err); + +end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* go pickup lintels on dispensers. Return END_TRAJ on success or if + + * there is nothing to do, else return the error status. */ +uint8_t strat_pickup_lintels(void) +{ + uint8_t err; + + if (get_column_count() != 0) + return END_ERROR; + + if (strat_infos.l1.count == 0 && strat_infos.l2.count == 0) + return END_TRAJ; + + /* skip if it's too early */ + if (time_get_s() < strat_infos.conf.lintel_min_time) + return END_TRAJ; + + /* skip next lintel if we want only one */ + if (strat_infos.conf.flags & STRAT_CONF_TAKE_ONE_LINTEL) { + if (strat_infos.taken_lintel) + return END_TRAJ; + } + + /* don't take lintel now if we already have one and if there + * is not much time */ + if (get_lintel_count() && time_get_s() > 75) + return END_TRAJ; + + /* take lintel 1 */ + err = strat_goto_lintel_disp(&strat_infos.l1); + if (!TRAJ_SUCCESS(err) && err != END_ERROR) + return err; + + /* skip next lintel if we want only one */ + if (strat_infos.conf.flags & STRAT_CONF_TAKE_ONE_LINTEL) { + if (strat_infos.taken_lintel) + return END_TRAJ; + } + + /* don't take lintel now if we already have one and if there + * is not much time */ + if (get_lintel_count() && time_get_s() > 75) + return END_TRAJ; + + /* take lintel 2 */ + err = strat_goto_lintel_disp(&strat_infos.l2); + if (!TRAJ_SUCCESS(err) && err != END_ERROR) + return err; + + return END_TRAJ; +} diff --git a/projects/microb2009/mainboard/strat_scan.c b/projects/microb2009/mainboard/strat_scan.c new file mode 100644 index 0000000..4140226 --- /dev/null +++ b/projects/microb2009/mainboard/strat_scan.c @@ -0,0 +1,689 @@ +/* + * Copyright Droids, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_scan.c,v 1.2 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/queue.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + + +#include "../common/i2c_commands.h" +#include "main.h" +#include "cmdline.h" +#include "i2c_protocol.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_utils.h" +#include "strat_avoid.h" +#include "sensor.h" + +#define ERROUT(e) do { \ + err = e; \ + goto end; \ + } while(0) + + +void scanner_dump_state(void) +{ + uint8_t status; + + printf_P(PSTR("scanner state:\r\n")); + status = sensorboard.scan_status; + + printf_P(PSTR(" status=%x: "), sensorboard.scan_status); + + if (status & I2C_SCAN_DONE) + printf_P(PSTR("DONE ")); + else + printf_P(PSTR("RUNNING ")); + if (status & I2C_SCAN_MAX_COLUMN) + printf_P(PSTR("OBSTACLE ")); + + printf_P(PSTR("\r\n")); + + if (sensorboard.dropzone_h == -1) { + printf_P(PSTR("No zone found\r\n")); + return; + } + + printf_P(PSTR(" column_h=%d\r\n"), sensorboard.dropzone_h); + printf_P(PSTR(" column_x=%d\r\n"), sensorboard.dropzone_x); + printf_P(PSTR(" column_y=%d\r\n"), sensorboard.dropzone_y); +} + +/* must be larger than the disc poly */ +#define CHECKPOINT_DIST 600 + +/* go to a specific angle on disc, if level == -1, don't move arms */ +uint8_t strat_goto_disc_angle(int16_t a_deg, int8_t level) +{ + uint8_t err; + uint16_t old_spdd, old_spda; + double x, y; + uint8_t need_clear = 0; + + DEBUG(E_USER_STRAT, "%s(a_deg=%d, level=%d)", __FUNCTION__, + a_deg, level); + + strat_get_speed(&old_spdd, &old_spda); + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + /* workaround for some static cols configurations */ + if ((strat_infos.conf.flags & STRAT_CONF_EARLY_SCAN) == 0) { + if (time_get_s() > 15) + i2c_mechboard_mode_loaded(); + } + /* another workaround for offensive configuration */ + else { + if (strat_infos.i2c_loaded_skipped == 0) { + DEBUG(E_USER_STRAT, "%s() need clear"); + strat_infos.i2c_loaded_skipped = 1; + i2c_mechboard_mode_prepare_pickup_next(I2C_AUTO_SIDE, + I2C_MECHBOARD_MODE_CLEAR); + need_clear = 1; + } + else + i2c_mechboard_mode_loaded(); + } + + + /* calculate the checkpoint */ + x = CHECKPOINT_DIST; + y = 0; + rotate(&x, &y, RAD(a_deg)); + x += CENTER_X; + y += CENTER_Y; + + err = goto_and_avoid(x, y, TRAJ_FLAGS_STD, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* early offensive conf only */ + if (need_clear) { + err = WAIT_COND_OR_TIMEOUT(get_column_count() == 2, + 3000L); + DEBUG(E_USER_STRAT, "%s() offensive: err=%d", err); + if (err == 0) /* timeout */ + return END_ERROR; + } + err = strat_goto_disc(level); + + end: + strat_set_speed(old_spdd, old_spda); + return err; + +} + +/* only valid for temple on disc */ +int16_t strat_get_temple_angle(struct temple *temple) +{ + int16_t x, y; + double a; + + x = temple->x; + y = temple->y; + x -= CENTER_X; + y -= CENTER_Y; + a = atan2(y, x); + return DEG(a); +} + +#define SCAN_ANGLE_OFFSET (-40) +int16_t strat_temple_angle_to_scan_angle(int16_t temple_angle) +{ + return temple_angle + SCAN_ANGLE_OFFSET; +} + +/* start to scan after this distance */ +#define DIST_START_SCAN 50 + +/* scan during this distance (includes DIST_START_SCAN) */ +#define DIST_SCAN 430 + +/* speed of the scan */ +#define SPEED_SCAN 450 + +/* from scanner point of view */ +#define DISC_CENTER_X 15 +#define DISC_CENTER_Y 13 + +/* distance of the checkpoint */ +#define CKPT_DST 550. + +/* to convert in robot coordinates */ +#define SIDE_OFFSET (ROBOT_WIDTH/2) +#define DIST_OFFSET (DIST_SCAN - DIST_START_SCAN) + +/* center of the disc in robot coordinates */ +#define CENTER_X_SCANNER 166 +#define CENTER_Y_SCANNER 174 + +/* center of the disc in scanner millimeters coordinates */ +#define CENTER_X_SCANNER2 120 +#define CENTER_Y_SCANNER2 155 + +/* structure filled by strat_scan_disc() */ +struct scan_disc_result { +#define SCAN_FAILED 0 +#define SCAN_VALID 1 + uint8_t status; + +#define SCAN_ACTION_BUILD_TEMPLE 0 +#define SCAN_ACTION_BUILD_COL 1 + uint8_t action; + + uint8_t level; +}; + +#define SCAN_MODE_CHECK_TEMPLE 0 +#define SCAN_MODE_SCAN_COL 1 +#define SCAN_MODE_SCAN_TEMPLE 2 + +int8_t strat_scan_get_checkpoint(uint8_t mode, int16_t *ckpt_rel_x, + int16_t *ckpt_rel_y, int16_t *back_mm) +{ + int16_t center_rel_x, center_rel_y; + int16_t col_rel_x, col_rel_y; + int16_t col_vect_x, col_vect_y; + double col_vect_norm; + int16_t ckpt_vect_x, ckpt_vect_y; + + /* do some filtering */ + if (mode == SCAN_MODE_SCAN_TEMPLE && + sensorboard.dropzone_x > CENTER_X_SCANNER) { + DEBUG(E_USER_STRAT, "x too big"); + return -1; + } + + /* process relative pos from robot point of view */ + center_rel_x = DIST_OFFSET - CENTER_Y_SCANNER; + center_rel_y = -(SIDE_OFFSET + CENTER_X_SCANNER); + + col_rel_x = DIST_OFFSET - sensorboard.dropzone_y; + col_rel_y = -(SIDE_OFFSET + sensorboard.dropzone_x); + DEBUG(E_USER_STRAT, "col_rel = %d,%d", col_rel_x, col_rel_y); + + /* vector from center to column */ + col_vect_x = col_rel_x - center_rel_x; + col_vect_y = col_rel_y - center_rel_y; + col_vect_norm = norm(col_vect_x, col_vect_y); + + /* vector from center to ckpt */ + ckpt_vect_x = (double)(col_vect_x) * CKPT_DST / col_vect_norm; + ckpt_vect_y = (double)(col_vect_y) * CKPT_DST / col_vect_norm; + + /* rel pos of ckpt */ + *ckpt_rel_x = center_rel_x + ckpt_vect_x; + *ckpt_rel_y = center_rel_y + ckpt_vect_y; + + /* do some filtering */ + if (col_vect_norm > 150 || col_vect_norm < 30) { + DEBUG(E_USER_STRAT, "bad norm"); + return -1; + } + + if (mode == SCAN_MODE_SCAN_TEMPLE) { + if (col_vect_norm > 50) { + *back_mm = ABS(col_vect_norm-50); + } + } + return 0; +} + +/* + * scan the disc: return END_TRAJ on success (and status in result is + * set to SCAN_VALID). In this case, all the scan_disc_result + * structure is filled with appropriate parameters. mode can be + * 'check' or 'scan_col'. Note that if we do a check_temple, the level + * field in structure must be filled first by the caller. + */ +uint8_t strat_scan_disc(int16_t angle, uint8_t mode, + struct scan_disc_result *result) +{ + uint16_t old_spdd, old_spda; + uint8_t err, stop_scanner = 0; + uint8_t original_mode = mode; + int16_t pos1x, pos1y, dist; + int16_t back_mm = 0; + + int16_t ckpt_rel_x = 0, ckpt_rel_y = 0; + + double center_abs_x, center_abs_y; + double ckpt_rel_d, ckpt_rel_a; + double ckpt_abs_x, ckpt_abs_y; + + /* mark status as failed for now */ + result->status = SCAN_FAILED; + + DEBUG(E_USER_STRAT, "%s(angle=%d)", __FUNCTION__, angle); + + strat_get_speed(&old_spdd, &old_spda); + + /* go on disc */ + err = strat_goto_disc_angle(angle, -1); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* wait opponent before scanning */ + if (strat_infos.conf.wait_opponent > 0) { + int16_t opp_x, opp_y, opp_d, opp_a; + int8_t err; + microseconds us; + + us = time_get_us2(); + while ((err = get_opponent_xyda(&opp_x, &opp_y, + &opp_d, &opp_a)) == 0) { + if (opp_d > 600) + break; + if (opp_a < 180) + break; + + if (time_get_us2() - us >= (uint32_t)strat_infos.conf.wait_opponent * 1000000L) + return END_ERROR; + } + } + + /* save absolute position of disc */ + rel_da_to_abs_xy(265, 0, ¢er_abs_x, ¢er_abs_y); + + strat_limit_speed_disable(); + + /* go back and prepare to scan */ + strat_set_speed(1000, 1000); + trajectory_d_a_rel(&mainboard.traj, -140, 130); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + /* XXX check that opp is not behind us */ + + /* prepare scanner */ + + stop_scanner = 1; + i2c_sensorboard_scanner_prepare(); + time_wait_ms(250); /* XXX to remove ? */ + + strat_set_speed(SPEED_SCAN, 1000); + + pos1x = position_get_x_s16(&mainboard.pos); + pos1y = position_get_y_s16(&mainboard.pos); + trajectory_d_rel(&mainboard.traj, -DIST_SCAN); + + while (1) { + err = test_traj_end(TRAJ_FLAGS_SMALL_DIST); + if (err != 0) + break; + + dist = distance_from_robot(pos1x, pos1y); + + if (dist > DIST_START_SCAN) + break; + + if (get_scanner_status() & I2C_SCAN_MAX_COLUMN) { + err = END_ERROR; + break; + } + } + + if (err) { + if (TRAJ_SUCCESS(err)) + err = END_ERROR; /* should not reach end */ + strat_hardstop(); + trajectory_goto_xy_abs(&mainboard.traj, pos1x, pos1y); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + ERROUT(err); + } + + /* start the scanner */ + + i2c_sensorboard_scanner_start(); + + err = WAIT_COND_OR_TRAJ_END(get_scanner_status() & I2C_SCAN_MAX_COLUMN, + TRAJ_FLAGS_NO_NEAR); + if (err == 0) + err = END_ERROR; + if (!TRAJ_SUCCESS(err)) { + strat_hardstop(); + trajectory_goto_xy_abs(&mainboard.traj, pos1x, pos1y); + wait_traj_end(TRAJ_FLAGS_NO_NEAR); + ERROUT(err); + } + + wait_scan_done(1000); + + i2c_sensorboard_scanner_stop(); + stop_scanner = 0; + + if (mode == SCAN_MODE_CHECK_TEMPLE) { + i2c_sensorboard_scanner_algo_check(result->level, + CENTER_X_SCANNER2, + CENTER_Y_SCANNER2); + i2cproto_wait_update(); + wait_scan_done(1000); + scanner_dump_state(); + + if (sensorboard.dropzone_h == -1 && + !(strat_infos.conf.flags & STRAT_CONF_SKIP_WHEN_CHECK_FAILS)) { + DEBUG(E_USER_STRAT, "-- try to build a temple"); + mode = SCAN_MODE_SCAN_TEMPLE; + } + else { + result->action = SCAN_ACTION_BUILD_TEMPLE; + /* level is already set by caller */ + } + } + + if (mode == SCAN_MODE_SCAN_TEMPLE) { + i2c_sensorboard_scanner_algo_temple(I2C_SCANNER_ZONE_DISC, + DISC_CENTER_X, + DISC_CENTER_Y); + i2cproto_wait_update(); + wait_scan_done(1000); + scanner_dump_state(); + + if (sensorboard.dropzone_h == -1 || + strat_scan_get_checkpoint(mode, &ckpt_rel_x, + &ckpt_rel_y, &back_mm)) { + if (original_mode != SCAN_MODE_CHECK_TEMPLE) { + DEBUG(E_USER_STRAT, "-- try to build a column"); + mode = SCAN_MODE_SCAN_COL; + } + else { + DEBUG(E_USER_STRAT, "-- check failed"); + } + } + else { + result->action = SCAN_ACTION_BUILD_TEMPLE; + result->level = sensorboard.dropzone_h; + } + } + + if (mode == SCAN_MODE_SCAN_COL) { + i2c_sensorboard_scanner_algo_column(I2C_SCANNER_ZONE_DISC, + DISC_CENTER_X, + DISC_CENTER_Y); + i2cproto_wait_update(); + wait_scan_done(1000); + scanner_dump_state(); + + if (sensorboard.dropzone_h == -1 || + strat_scan_get_checkpoint(mode, &ckpt_rel_x, + &ckpt_rel_y, &back_mm)) { + ERROUT(END_ERROR); + } + else { + result->action = SCAN_ACTION_BUILD_COL; + result->level = sensorboard.dropzone_h; + } + } + + if (sensorboard.dropzone_h == -1) { + ERROUT(END_ERROR); + } + + if (mode == SCAN_MODE_CHECK_TEMPLE) { + ckpt_rel_x = 220; + ckpt_rel_y = 100; + } + + DEBUG(E_USER_STRAT, "rel xy for ckpt is %d,%d", ckpt_rel_x, ckpt_rel_y); + + rel_xy_to_abs_xy(ckpt_rel_x, ckpt_rel_y, &ckpt_abs_x, &ckpt_abs_y); + abs_xy_to_rel_da(ckpt_abs_x, ckpt_abs_y, &ckpt_rel_d, &ckpt_rel_a); + + DEBUG(E_USER_STRAT, "abs ckpt is %2.2f,%2.2f", ckpt_abs_x, ckpt_abs_y); + + strat_set_speed(SPEED_DIST_FAST, SPEED_ANGLE_FAST); + + /* intermediate checkpoint for some positions */ + if ( (DEG(ckpt_rel_a) < 0 && DEG(ckpt_rel_a) > -90) ) { + trajectory_goto_xy_rel(&mainboard.traj, 200, 100); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + } + + trajectory_goto_xy_abs(&mainboard.traj, ckpt_abs_x, ckpt_abs_y); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + if (result->action == SCAN_ACTION_BUILD_TEMPLE) { + i2c_mechboard_mode_prepare_build_both(result->level); + } + + trajectory_turnto_xy(&mainboard.traj, center_abs_x, center_abs_y); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + pos1x = position_get_x_s16(&mainboard.pos); + pos1y = position_get_y_s16(&mainboard.pos); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_SLOW); + trajectory_d_rel(&mainboard.traj, 400); + err = WAIT_COND_OR_TRAJ_END(distance_from_robot(pos1x, pos1y) > 200, + TRAJ_FLAGS_SMALL_DIST); + if (err == 0) { + strat_set_speed(SPEED_DIST_VERY_SLOW, SPEED_ANGLE_VERY_SLOW); + trajectory_d_rel(&mainboard.traj, 400); + err = wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + if (TRAJ_SUCCESS(err)) + err = END_ERROR; /* should not reach end */ + if (err != END_BLOCKING && !TRAJ_SUCCESS(err)) + ERROUT(err); + + if (back_mm) { + trajectory_d_rel(&mainboard.traj, -back_mm); + wait_traj_end(TRAJ_FLAGS_SMALL_DIST); + } + + result->status = SCAN_VALID; + + strat_limit_speed_enable(); + return END_TRAJ; + + end: + if (stop_scanner) + i2c_sensorboard_scanner_stop(); + strat_limit_speed_enable(); + strat_set_speed(old_spdd, old_spda); + return err; + +} + +/* do action according to scanner result. temple argument can be NULL + * if it's a new one (from opponent) or it can be our previous + * temple. */ +uint8_t strat_scan_do_action(struct scan_disc_result *scan_result, + struct temple *temple, struct build_zone *zone) +{ + uint8_t err; + + /* remove the temple from the list */ + if (scan_result->status != SCAN_VALID) + return END_ERROR; + + if (temple) { + /* we were scanning a temple, remove it */ + if (scan_result->level != temple->level_l) { + temple->flags = 0; + temple = NULL; + } + } + + if (temple == NULL) { + temple = strat_get_free_temple(); + if (temple == NULL) + return END_ERROR; + memset(temple, 0, sizeof(*temple)); + temple->level_l = scan_result->level; + temple->level_r = scan_result->level; + temple->flags = TEMPLE_F_OPPONENT | + TEMPLE_F_VALID | TEMPLE_F_LINTEL; + temple->zone = zone; + } + zone->flags |= ZONE_F_BUSY; + + switch (scan_result->action) { + + case SCAN_ACTION_BUILD_COL: + err = strat_grow_temple_column(temple); + break; + + case SCAN_ACTION_BUILD_TEMPLE: + err = strat_grow_temple(temple); + break; + default: + err = END_TRAJ; + break; + } + if (!TRAJ_SUCCESS(err)) + temple->flags = 0; + return err; +} + +uint8_t strat_build_on_opponent_temple(void) +{ + struct temple *temple; + uint8_t err; + struct scan_disc_result scan_result; + int16_t temple_angle; + + if (time_get_s() < strat_infos.conf.scan_opp_min_time) + return END_TRAJ; + + strat_infos.conf.scan_opp_min_time = + time_get_s() + strat_infos.conf.delay_between_opp_scan; + + /* scan on disc only */ + if (strat_infos.conf.scan_opp_angle == -1) { + temple = strat_get_our_temple_on_disc(0); + + /* scan the opposite of our temple if we found + * one on disc */ + if (temple) { + temple_angle = strat_get_temple_angle(temple); + temple_angle += 180; + if (temple_angle > 180) + temple_angle -= 360; + } + /* else scan at 0 deg (opponent side) */ + else { + temple_angle = 0; + } + } + else { + /* user specified scan position */ + temple_angle = strat_infos.conf.delay_between_opp_scan; + if (temple_angle > 180) + temple_angle -= 360; + } + temple_angle = strat_temple_angle_to_scan_angle(temple_angle); + + + err = strat_scan_disc(temple_angle, SCAN_MODE_SCAN_TEMPLE, + &scan_result); + if (!TRAJ_SUCCESS(err)) + return err; + + /* XXX on disc only */ + err = strat_scan_do_action(&scan_result, NULL, + &strat_infos.zone_list[0]); + + if (!TRAJ_SUCCESS(err)) + return err; + + err = strat_escape(&strat_infos.zone_list[0], TRAJ_FLAGS_STD); + return err; +} + +uint8_t strat_check_temple_and_build(void) +{ + struct temple *temple; + uint8_t err; + struct scan_disc_result scan_result; + int16_t temple_angle; + + if (time_get_s() < strat_infos.conf.scan_our_min_time) + return END_TRAJ; + strat_infos.conf.scan_our_min_time = + time_get_s() + strat_infos.conf.delay_between_our_scan; + + /* on disc only, symetric only */ + temple = strat_get_our_temple_on_disc(1); + if (temple == NULL) + return END_TRAJ; + + temple_angle = strat_get_temple_angle(temple); + temple_angle = strat_temple_angle_to_scan_angle(temple_angle); + + scan_result.level = temple->level_l; + err = strat_scan_disc(temple_angle, SCAN_MODE_CHECK_TEMPLE, + &scan_result); + if (scan_result.status != SCAN_VALID) { + temple->flags = 0; + temple = NULL; + } + /* no column after a temple check */ + else if (scan_result.action == SCAN_ACTION_BUILD_COL && + time_get_s() < 70) + err = END_ERROR; + if (!TRAJ_SUCCESS(err)) + return err; + + err = strat_scan_do_action(&scan_result, temple, + temple->zone); + if (!TRAJ_SUCCESS(err)) + return err; + + err = strat_escape(&strat_infos.zone_list[0], TRAJ_FLAGS_STD); + return err; +} diff --git a/projects/microb2009/mainboard/strat_static_columns.c b/projects/microb2009/mainboard/strat_static_columns.c new file mode 100644 index 0000000..7af6043 --- /dev/null +++ b/projects/microb2009/mainboard/strat_static_columns.c @@ -0,0 +1,416 @@ +/* + * Copyright Droids, Microb Technology (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_static_columns.c,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/queue.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "strat.h" +#include "strat_base.h" +#include "strat_utils.h" +#include "strat_avoid.h" +#include "sensor.h" +#include "i2c_protocol.h" + +#define ERROUT(e) do { \ + err = e; \ + goto end; \ + } while(0) + +#define BIG_DIST 5000 + +/* + * must be called from start area. + * get 4 static columns and build a temple on the disc + */ +uint8_t strat_static_columns(uint8_t configuration) +{ + uint8_t err; + uint8_t col1_present = 0, col4_present = 0; + uint16_t old_spdd, old_spda; + + DEBUG(E_USER_STRAT, "%s(%d)", __FUNCTION__, configuration); + + strat_get_speed(&old_spdd, &old_spda); + + /* calibrate scanner */ + i2c_sensorboard_scanner_calib(); + + i2c_mechboard_mode_harvest(); + + /* go straight. total distance is less than 5 meters */ + strat_set_speed(1000, 1000); + trajectory_d_rel(&mainboard.traj, BIG_DIST); + + /* when y > 50, break */ + err = WAIT_COND_OR_TRAJ_END(y_is_more_than(500), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + + /* turn to 90° abs while going forward */ + DEBUG(E_USER_STRAT, "turn now"); + strat_set_speed(1000, 350); + trajectory_only_a_abs(&mainboard.traj, COLOR_A(90)); + + /* when y > 100, check the presence of column 4 */ + err = WAIT_COND_OR_TRAJ_END(y_is_more_than(1000), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + if (get_color() == I2C_COLOR_RED && sensor_get(S_COLUMN_RIGHT)) + col4_present = 1; + if (get_color() == I2C_COLOR_GREEN && sensor_get(S_COLUMN_LEFT)) + col4_present = 1; + + /* when y > 120, check the presence of column 1 */ + err = WAIT_COND_OR_TRAJ_END(y_is_more_than(1200), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + if (get_color() == I2C_COLOR_RED && sensor_get(S_COLUMN_RIGHT)) + col1_present = 1; + if (get_color() == I2C_COLOR_GREEN && sensor_get(S_COLUMN_LEFT)) + col1_present = 1; + + /* when y > 130, break */ + err = WAIT_COND_OR_TRAJ_END(y_is_more_than(1300), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + + strat_infos.s_cols.flags |= STATIC_COL_LINE0_DONE; + + DEBUG(E_USER_STRAT, "col4=%d col1=%d", col4_present, col1_present); + DEBUG(E_USER_STRAT, "have %d cols", get_column_count()); + + if (configuration == 0) { + if (get_column_count() > 2) { + configuration = 1; + if (col4_present || col1_present) { + strat_infos.s_cols.flags |= + STATIC_COL_LINE2_DONE; + } + else { + strat_infos.s_cols.flags |= + STATIC_COL_LINE1_DONE; + } + } + + /* only 2 colums on the first line */ + else { + /* all other colums are on line 1 */ + if (col4_present && col1_present) { + configuration = 2; + strat_infos.s_cols.flags |= + STATIC_COL_LINE2_DONE; + } + + /* only 2 columns on line 1, so there are also + * 2 on line 2 */ + else if (col4_present || col1_present) { + configuration = 4; + strat_infos.s_cols.flags |= + STATIC_COL_LINE2_DONE; + } + + /* all other columns are on line 2 */ + else { + configuration = 3; + strat_infos.s_cols.flags |= + STATIC_COL_LINE1_DONE; + } + } + } + + strat_infos.s_cols.configuration = configuration; + DEBUG(E_USER_STRAT, "use configuration %d", configuration); + + if (configuration == 1) { + /* we already got 4 columns, go to the disc directly */ + + strat_set_speed(1500, 900); + trajectory_only_a_abs(&mainboard.traj, COLOR_A(0)); + err = WAIT_COND_OR_TRAJ_END(x_is_more_than(1100), TRAJ_FLAGS_STD); + + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + } + else if (configuration == 2 /* go from line 0 to line 1 */) { + strat_set_speed(800, 1000); + /* relative is needed here */ + trajectory_only_a_rel(&mainboard.traj, COLOR_A(-180)); + err = WAIT_COND_OR_TRAJ_END(!y_is_more_than(1300), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + strat_set_speed(1000, 600); + err = WAIT_COND_OR_TRAJ_END(!y_is_more_than(1100), + TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + } + else if (configuration == 3 /* go from line 0 to line 2 and there is 4 columns + on line 2*/) { + strat_set_speed(1000, 600); + /* relative is needed here */ + trajectory_only_a_rel(&mainboard.traj, COLOR_A(-180)); + err = WAIT_COND_OR_TRAJ_END(!y_is_more_than(1110), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + } + else if (configuration == 4 /* go from line 0 to line 2 and there is 2 columns + on line 2 */) { + strat_set_speed(1000, 600); + /* relative is needed here */ + trajectory_only_a_rel(&mainboard.traj, COLOR_A(-180)); + err = WAIT_COND_OR_TRAJ_END(!y_is_more_than(600), TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + } + else { + trajectory_stop(&mainboard.traj); + } + + ERROUT(END_TRAJ); + + end: + strat_set_speed(old_spdd, old_spda); + return err; +} + +/* + * get last 2 columns + * must be called after the first temple building + */ +uint8_t strat_static_columns_pass2(void) +{ + uint16_t old_spdd, old_spda; + uint8_t side, err, next_mode; + + DEBUG(E_USER_STRAT, "%s()", __FUNCTION__); + + strat_get_speed(&old_spdd, &old_spda); + + if (get_color() == I2C_COLOR_RED) + side = I2C_RIGHT_SIDE; + else + side = I2C_LEFT_SIDE; + + if (strat_infos.conf.flags & STRAT_CONF_STORE_STATIC2) + next_mode = I2C_MECHBOARD_MODE_STORE; + else + next_mode = I2C_MECHBOARD_MODE_HARVEST; + + switch (strat_infos.s_cols.configuration) { + + /* configuration 1: 4 cols on line 0 */ + case 1: + if (strat_infos.s_cols.flags & STATIC_COL_LINE1_DONE) { + /* go on line 2 */ + + strat_set_speed(2000, 700); + trajectory_d_a_rel(&mainboard.traj, -450, COLOR_A(35)); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + i2c_mechboard_mode_prepare_pickup_next(side, + next_mode); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + trajectory_goto_forward_xy_abs(&mainboard.traj, + LINE2_X, + COLOR_Y(400)); + err = WAIT_COND_OR_TRAJ_END(get_column_count() == 2, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + } + else { + /* go on line 1 */ + strat_set_speed(2000, 700); + trajectory_d_a_rel(&mainboard.traj, -650, COLOR_A(55)); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + i2c_mechboard_mode_prepare_pickup_next(side, + next_mode); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + + err = goto_and_avoid_forward(LINE1_X, + COLOR_Y(400), + TRAJ_FLAGS_NO_NEAR, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + } + + ERROUT(END_TRAJ); + break; + + /* configuration 2: 2 cols on line 0, + all other colums are on line 1 */ + case 2: + /* go on line 1 */ + strat_set_speed(2000, 700); + trajectory_d_a_rel(&mainboard.traj, -410, COLOR_A(-20)); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + i2c_mechboard_mode_prepare_pickup_next(side, + next_mode); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + + err = goto_and_avoid_forward(COL10_X, COLOR_Y(400), + TRAJ_FLAGS_NO_NEAR, + TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + ERROUT(END_TRAJ); + break; + + /* configuration 3: 2 cols on line 0, + all other colums are on line 2 */ + case 3: + /* go on line 2 */ + strat_set_speed(2000, 700); + trajectory_d_a_rel(&mainboard.traj, -150, COLOR_A(-30)); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + i2c_mechboard_mode_prepare_pickup_next(side, + next_mode); + + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + + trajectory_goto_forward_xy_abs(&mainboard.traj, + LINE2_X, + COLOR_Y(400)); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + ERROUT(END_TRAJ); + break; + + /* configuration 4: 2 cols on line 0, + 2 on line 1, 2 on line 2 */ + case 4: + /* go on line 1 */ + strat_set_speed(600, 2000); + trajectory_d_a_rel(&mainboard.traj, -BIG_DIST, + COLOR_A(-135)); + err = WAIT_COND_OR_TRAJ_END(y_is_more_than(900), + TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + + DEBUG(E_USER_STRAT, "%s():%d", __FUNCTION__, __LINE__); + i2c_mechboard_mode_prepare_pickup_next(side, + next_mode); + + strat_set_speed(2000, 2000); + trajectory_d_rel(&mainboard.traj, -BIG_DIST); + err = WAIT_COND_OR_TRAJ_END(y_is_more_than(1100), + TRAJ_FLAGS_STD); + if (TRAJ_SUCCESS(err)) /* we should not reach end */ + ERROUT(END_ERROR); + else if (err) + ERROUT(err); + + DEBUG(E_USER_STRAT, "%s():%d", __FUNCTION__, __LINE__); + trajectory_d_a_rel(&mainboard.traj, -600, COLOR_A(40)); + err = wait_traj_end(TRAJ_FLAGS_NO_NEAR); + if (!TRAJ_SUCCESS(err)) + ERROUT(err); + + DEBUG(E_USER_STRAT, "%s():%d", __FUNCTION__, __LINE__); + strat_set_speed(SPEED_DIST_SLOW, SPEED_ANGLE_FAST); + err = goto_and_avoid_forward(LINE1_X, + COLOR_Y(400), + TRAJ_FLAGS_NO_NEAR, + TRAJ_FLAGS_NO_NEAR); + ERROUT(END_TRAJ); + break; + + default: + break; + } + + /* should not reach this point */ + ERROUT(END_ERROR); + + end: + strat_set_speed(old_spdd, old_spda); + return err; +} diff --git a/projects/microb2009/mainboard/strat_utils.c b/projects/microb2009/mainboard/strat_utils.c new file mode 100644 index 0000000..81a12d6 --- /dev/null +++ b/projects/microb2009/mainboard/strat_utils.c @@ -0,0 +1,413 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_utils.c,v 1.7 2009-11-08 17:24:33 zer0 Exp $ + * + */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <trajectory_manager.h> +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> +#include <blocking_detection_manager.h> +#include <robot_system.h> +#include <position_manager.h> + +#include <rdline.h> +#include <parse.h> + +#include "../common/i2c_commands.h" + +#include "main.h" +#include "strat_utils.h" +#include "strat.h" +#include "sensor.h" +#include "i2c_protocol.h" + +/* return the distance between two points */ +int16_t distance_between(int16_t x1, int16_t y1, int16_t x2, int16_t y2) +{ + int32_t x,y; + x = (x2-x1); + x = x*x; + y = (y2-y1); + y = y*y; + return sqrt(x+y); +} + +/* return the distance to a point in the area */ +int16_t distance_from_robot(int16_t x, int16_t y) +{ + return distance_between(position_get_x_s16(&mainboard.pos), + position_get_y_s16(&mainboard.pos), x, y); +} + +/** do a modulo 360 -> [-180,+180], knowing that 'a' is in [-3*180,+3*180] */ +int16_t simple_modulo_360(int16_t a) +{ + if (a < -180) { + a += 360; + } + else if (a > 180) { + a -= 360; + } + return a; +} + +/** do a modulo 2.pi -> [-Pi,+Pi], knowing that 'a' is in [-3Pi,+3Pi] */ +double simple_modulo_2pi(double a) +{ + if (a < -M_PI) { + a += M_2PI; + } + else if (a > M_PI) { + a -= M_2PI; + } + return a; +} + +/* return the distance to a point in the area */ +int16_t angle_abs_to_rel(int16_t a_abs) +{ + return simple_modulo_360(a_abs - position_get_a_deg_s16(&mainboard.pos)); +} + +void rel_da_to_abs_xy(double d_rel, double a_rel_rad, + double *x_abs, double *y_abs) +{ + double x = position_get_x_double(&mainboard.pos); + double y = position_get_y_double(&mainboard.pos); + double a = position_get_a_rad_double(&mainboard.pos); + + *x_abs = x + d_rel*cos(a+a_rel_rad); + *y_abs = y + d_rel*sin(a+a_rel_rad); +} + +double norm(double x, double y) +{ + return sqrt(x*x + y*y); +} + +void rel_xy_to_abs_xy(double x_rel, double y_rel, + double *x_abs, double *y_abs) +{ + double d_rel, a_rel; + d_rel = norm(x_rel, y_rel); + a_rel = atan2(y_rel, x_rel); + rel_da_to_abs_xy(d_rel, a_rel, x_abs, y_abs); +} + +/* return an angle between -pi and pi */ +void abs_xy_to_rel_da(double x_abs, double y_abs, + double *d_rel, double *a_rel_rad) +{ + double x = position_get_x_double(&mainboard.pos); + double y = position_get_y_double(&mainboard.pos); + double a = position_get_a_rad_double(&mainboard.pos); + + *a_rel_rad = atan2(y_abs - y, x_abs - x) - a; + if (*a_rel_rad < -M_PI) { + *a_rel_rad += M_2PI; + } + else if (*a_rel_rad > M_PI) { + *a_rel_rad -= M_2PI; + } + *d_rel = norm(x_abs-x, y_abs-y); +} + +void rotate(double *x, double *y, double rot) +{ + double l, a; + + l = norm(*x, *y); + a = atan2(*y, *x); + + a += rot; + *x = l * cos(a); + *y = l * sin(a); +} + +/* return true if the point is in area */ +uint8_t is_in_area(int16_t x, int16_t y, int16_t margin) +{ + if (x < margin) + return 0; + if (x > (AREA_X - margin)) + return 0; + if (y < margin) + return 0; + if (y > (AREA_Y - margin)) + return 0; + return 1; +} + + +/* return true if the point is in area */ +uint8_t robot_is_in_area(int16_t margin) +{ + return is_in_area(position_get_x_s16(&mainboard.pos), + position_get_y_s16(&mainboard.pos), + margin); +} + +/* return true if we are near the disc */ +uint8_t robot_is_near_disc(void) +{ + if (distance_from_robot(CENTER_X, CENTER_Y) < DISC_PENTA_DIAG) + return 1; + return 0; +} + +/* return 1 or 0 depending on which side of a line (y=cste) is the + * robot. works in red or green color. */ +uint8_t y_is_more_than(int16_t y) +{ + int16_t posy; + + posy = position_get_y_s16(&mainboard.pos); + if (mainboard.our_color == I2C_COLOR_RED) { + if (posy > y) + return 1; + else + return 0; + } + else { + if (posy < (AREA_Y-y)) + return 1; + else + return 0; + } +} + +/* return 1 or 0 depending on which side of a line (x=cste) is the + * robot. works in red or green color. */ +uint8_t x_is_more_than(int16_t x) +{ + int16_t posx; + + posx = position_get_x_s16(&mainboard.pos); + if (posx > x) + return 1; + else + return 0; +} + +int16_t sin_table[] = { + 0, + 3211, + 6392, + 9512, + 12539, + 15446, + 18204, + 20787, + 23170, + 25330, + 27245, + 28898, + 30273, + 31357, + 32138, + 32610, + 32767, +}; + +int16_t fast_sin(int16_t deg) +{ + deg %= 360; + + if (deg < 0) + deg += 360; + + if (deg < 90) + return sin_table[(deg*16)/90]; + else if (deg < 180) + return sin_table[((180-deg)*16)/90]; + else if (deg < 270) + return -sin_table[((deg-180)*16)/90]; + else + return -sin_table[((360-deg)*16)/90]; +} + +int16_t fast_cos(int16_t deg) +{ + return fast_sin(90+deg); +} + + +/* get the color of our robot */ +uint8_t get_color(void) +{ + return mainboard.our_color; +} + +/* get the color of the opponent robot */ +uint8_t get_opponent_color(void) +{ + if (mainboard.our_color == I2C_COLOR_RED) + return I2C_COLOR_GREEN; + else + return I2C_COLOR_RED; +} + +/* get the xy pos of the opponent robot */ +int8_t get_opponent_xy(int16_t *x, int16_t *y) +{ + uint8_t flags; + IRQ_LOCK(flags); + *x = sensorboard.opponent_x; + *y = sensorboard.opponent_y; + IRQ_UNLOCK(flags); + if (*x == I2C_OPPONENT_NOT_THERE) + return -1; + return 0; +} + +/* get the da pos of the opponent robot */ +int8_t get_opponent_da(int16_t *d, int16_t *a) +{ + uint8_t flags; + int16_t x_tmp; + IRQ_LOCK(flags); + x_tmp = sensorboard.opponent_x; + *d = sensorboard.opponent_d; + *a = sensorboard.opponent_a; + IRQ_UNLOCK(flags); + if (x_tmp == I2C_OPPONENT_NOT_THERE) + return -1; + return 0; +} + +/* get the da pos of the opponent robot */ +int8_t get_opponent_xyda(int16_t *x, int16_t *y, int16_t *d, int16_t *a) +{ + uint8_t flags; + IRQ_LOCK(flags); + *x = sensorboard.opponent_x; + *y = sensorboard.opponent_y; + *d = sensorboard.opponent_d; + *a = sensorboard.opponent_a; + IRQ_UNLOCK(flags); + if (*x == I2C_OPPONENT_NOT_THERE) + return -1; + return 0; +} + +uint8_t pump_left1_is_full(void) +{ + return !!( (mechboard.column_flags & I2C_MECHBOARD_COLUMN_L1) && + (sensor_get_adc(ADC_CSENSE3) > I2C_MECHBOARD_CURRENT_COLUMN)); +} + +uint8_t pump_left2_is_full(void) +{ + return !!( (mechboard.column_flags & I2C_MECHBOARD_COLUMN_L2) && + (sensor_get_adc(ADC_CSENSE4) > I2C_MECHBOARD_CURRENT_COLUMN)); +} + +uint8_t pump_right1_is_full(void) +{ + return !!( (mechboard.column_flags & I2C_MECHBOARD_COLUMN_R1) && + (mechboard.pump_right1_current > I2C_MECHBOARD_CURRENT_COLUMN)); +} + +uint8_t pump_right2_is_full(void) +{ + return !!( (mechboard.column_flags & I2C_MECHBOARD_COLUMN_R2) && + (mechboard.pump_right2_current > I2C_MECHBOARD_CURRENT_COLUMN)); +} + +/* number of column owned by the robot */ +uint8_t get_column_count_left(void) +{ + uint8_t ret = 0; + ret += pump_left1_is_full(); + ret += pump_left2_is_full(); + return ret; +} + +/* number of column owned by the robot */ +uint8_t get_column_count_right(void) +{ + uint8_t ret = 0; + ret += pump_right1_is_full(); + ret += pump_right2_is_full(); + return ret; +} + +/* number of column owned by the robot */ +uint8_t get_column_count(void) +{ + uint8_t ret = 0; + ret += pump_left1_is_full(); + ret += pump_left2_is_full(); + ret += pump_right1_is_full(); + ret += pump_right2_is_full(); + return ret; +} + +uint8_t get_lintel_count(void) +{ + return mechboard.lintel_count; +} + +uint8_t get_mechboard_mode(void) +{ + return mechboard.mode; +} + +uint8_t get_scanner_status(void) +{ + return sensorboard.scan_status; +} + +/* return 0 if timeout, or 1 if cond is true */ +uint8_t wait_scan_done(uint16_t timeout) +{ + uint8_t err; + err = WAIT_COND_OR_TIMEOUT(get_scanner_status() & I2C_SCAN_DONE, timeout); + return err; +} + +uint8_t opponent_is_behind(void) +{ + int8_t opp_there; + int16_t opp_d, opp_a; + + opp_there = get_opponent_da(&opp_d, &opp_a); + if (opp_there && (opp_a < 215 && opp_a > 145) && opp_d < 600) + return 1; + return 0; +} diff --git a/projects/microb2009/mainboard/strat_utils.h b/projects/microb2009/mainboard/strat_utils.h new file mode 100644 index 0000000..986b601 --- /dev/null +++ b/projects/microb2009/mainboard/strat_utils.h @@ -0,0 +1,76 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: strat_utils.h,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + */ + + +#define DEG(x) (((double)(x)) * (180.0 / M_PI)) +#define RAD(x) (((double)(x)) * (M_PI / 180.0)) +#define M_2PI (2*M_PI) + +struct xy_point { + int16_t x; + int16_t y; +}; + +/* wait traj end flag or cond. return 0 if cond become true, else + * return the traj flag */ +#define WAIT_COND_OR_TRAJ_END(cond, mask) \ + ({ \ + uint8_t __err = 0; \ + while ( (! (cond)) && (__err == 0)) { \ + __err = test_traj_end(TRAJ_FLAGS_NO_NEAR); \ + } \ + __err; \ + }) \ + +int16_t distance_between(int16_t x1, int16_t y1, int16_t x2, int16_t y2); +int16_t distance_from_robot(int16_t x, int16_t y); +int16_t simple_modulo_360(int16_t a); +double simple_modulo_2pi(double a); +int16_t angle_abs_to_rel(int16_t a_abs); +void rel_da_to_abs_xy(double d_rel, double a_rel_rad, double *x_abs, double *y_abs); +double norm(double x, double y); +void rel_xy_to_abs_xy(double x_rel, double y_rel, double *x_abs, double *y_abs); +void abs_xy_to_rel_da(double x_abs, double y_abs, double *d_rel, double *a_rel_rad); +void rotate(double *x, double *y, double rot); +uint8_t is_in_area(int16_t x, int16_t y, int16_t margin); +uint8_t robot_is_in_area(int16_t margin); +uint8_t robot_is_near_disc(void); +uint8_t y_is_more_than(int16_t y); +uint8_t x_is_more_than(int16_t x); +int16_t fast_sin(int16_t deg); +int16_t fast_cos(int16_t deg); +uint8_t get_color(void); +uint8_t get_opponent_color(void); +int8_t get_opponent_xy(int16_t *x, int16_t *y); +int8_t get_opponent_da(int16_t *d, int16_t *a); +int8_t get_opponent_xyda(int16_t *x, int16_t *y, int16_t *d, int16_t *a); +uint8_t get_column_count(void); +uint8_t get_column_count_right(void); +uint8_t get_column_count_left(void); +uint8_t get_lintel_count(void); +uint8_t get_mechboard_mode(void); +uint8_t pump_left1_is_full(void); +uint8_t pump_left2_is_full(void); +uint8_t pump_right1_is_full(void); +uint8_t pump_right2_is_full(void); +uint8_t get_scanner_status(void); +uint8_t wait_scan_done(uint16_t timeout); +uint8_t opponent_is_behind(void); diff --git a/projects/microb2009/mainboard/time_config.h b/projects/microb2009/mainboard/time_config.h new file mode 100755 index 0000000..14db608 --- /dev/null +++ b/projects/microb2009/mainboard/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 25000l diff --git a/projects/microb2009/mainboard/timer_config.h b/projects/microb2009/mainboard/timer_config.h new file mode 100755 index 0000000..47d9f18 --- /dev/null +++ b/projects/microb2009/mainboard/timer_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 diff --git a/projects/microb2009/mainboard/uart_config.h b/projects/microb2009/mainboard/uart_config.h new file mode 100644 index 0000000..514d1e9 --- /dev/null +++ b/projects/microb2009/mainboard/uart_config.h @@ -0,0 +1,94 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.5 2009-11-08 17:24:33 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART1 definitions + */ + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 64 +#define UART1_TX_FIFO_SIZE 127 +#define UART1_NBITS 8 + +#define UART1_PARITY UART_PARTITY_NONE + +#define UART1_STOP_BIT UART_STOP_BITS_1 + + +/* + * UART3 definitions + */ + +/* compile uart3 fonctions, undefine it to pass compilation */ +#define UART3_COMPILE + +/* enable uart3 if == 1, disable if == 0 */ +#define UART3_ENABLED 1 + +/* enable uart3 interrupts if == 1, disable if == 0 */ +#define UART3_INTERRUPT_ENABLED 1 + +#define UART3_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART3_USE_DOUBLE_SPEED 1 + +#define UART3_RX_FIFO_SIZE 64 +#define UART3_TX_FIFO_SIZE 64 +#define UART3_NBITS 8 + +#define UART3_PARITY UART_PARTITY_NONE + +#define UART3_STOP_BIT UART_STOP_BITS_1 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/projects/microb2009/mechboard/.config b/projects/microb2009/mechboard/.config new file mode 100644 index 0000000..fd14974 --- /dev/null +++ b/projects/microb2009/mechboard/.config @@ -0,0 +1,279 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_MCU_ATMEGA2560=y +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_ADVANCED_PRINTF=y +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_GEOMETRY is not set +# CONFIG_MODULE_GEOMETRY_CREATE_CONFIG is not set +CONFIG_MODULE_SCHEDULER=y +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +CONFIG_MODULE_TIME=y +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +CONFIG_MODULE_I2C=y +CONFIG_MODULE_I2C_MASTER=y +# CONFIG_MODULE_I2C_MULTIMASTER is not set +CONFIG_MODULE_I2C_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +CONFIG_MODULE_PWM_NG=y +CONFIG_MODULE_ADC=y +CONFIG_MODULE_ADC_CREATE_CONFIG=y + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +CONFIG_MODULE_AX12=y +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +CONFIG_MODULE_ENCODERS_SPI=y +CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG=y + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +CONFIG_MODULE_BLOCKING_DETECTION_MANAGER=y +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +CONFIG_MODULE_PID=y +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +CONFIG_MODULE_DIAGNOSTIC=y +CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG=y +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/projects/microb2009/mechboard/CVS/Entries b/projects/microb2009/mechboard/CVS/Entries new file mode 100644 index 0000000..d020cb8 --- /dev/null +++ b/projects/microb2009/mechboard/CVS/Entries @@ -0,0 +1,41 @@ +/.config/1.2/Wed May 27 20:04:07 2009// +/Makefile/1.4/Fri Apr 24 19:30:41 2009// +/actuator.c/1.4/Fri Apr 24 19:30:41 2009// +/actuator.h/1.6/Sun Nov 8 17:25:00 2009// +/adc_config.h/1.1/Thu Mar 5 22:52:36 2009// +/arm_highlevel.c/1.4/Sun Nov 8 17:25:00 2009// +/arm_highlevel.h/1.4/Sun Nov 8 17:25:00 2009// +/arm_xy.c/1.5/Sun Nov 8 17:25:00 2009// +/arm_xy.h/1.4/Sun Nov 8 17:25:00 2009// +/ax12_config.h/1.1/Thu Mar 5 22:52:36 2009// +/ax12_user.c/1.4/Fri Apr 24 19:30:42 2009// +/ax12_user.h/1.3/Tue Apr 7 20:03:48 2009// +/cmdline.c/1.3/Fri Apr 24 19:30:42 2009// +/cmdline.h/1.4/Sun Nov 8 17:25:00 2009// +/commands.c/1.6/Sun Nov 8 17:25:00 2009// +/commands_ax12.c/1.3/Fri Apr 24 19:30:42 2009// +/commands_cs.c/1.2/Tue Apr 7 20:03:48 2009// +/commands_gen.c/1.5/Sun Nov 8 17:25:00 2009// +/commands_mechboard.c/1.6/Sun Nov 8 17:25:00 2009// +/cs.c/1.4/Fri Apr 24 19:30:42 2009// +/cs.h/1.1/Thu Mar 5 22:52:35 2009// +/diagnostic_config.h/1.1/Thu Mar 5 22:52:35 2009// +/encoders_spi_config.h/1.1/Thu Mar 5 22:52:35 2009// +/error_config.h/1.1/Thu Mar 5 22:52:35 2009// +/i2c_config.h/1.1/Thu Mar 5 22:52:35 2009// +/i2c_protocol.c/1.6/Sun Nov 8 17:25:00 2009// +/i2c_protocol.h/1.1/Thu Mar 5 22:52:35 2009// +/main.c/1.6/Sun Nov 8 17:25:00 2009// +/main.h/1.6/Sun Nov 8 17:25:00 2009// +/pid_config.h/1.1/Thu Mar 5 22:52:35 2009// +/rdline_config.h/1.1/Thu Mar 5 22:52:35 2009// +/scheduler_config.h/1.2/Tue Apr 7 20:03:48 2009// +/sensor.c/1.6/Sun Nov 8 17:25:00 2009// +/sensor.h/1.4/Fri Apr 24 19:30:42 2009// +/spi_config.h/1.1/Thu Mar 5 22:52:35 2009// +/state.c/1.5/Sun Nov 8 17:25:00 2009// +/state.h/1.5/Sun Nov 8 17:25:00 2009// +/time_config.h/1.3/Tue Apr 7 20:03:48 2009// +/timer_config.h/1.1/Thu Mar 5 22:52:35 2009// +/uart_config.h/1.5/Sun Nov 8 17:25:00 2009// +D diff --git a/projects/microb2009/mechboard/CVS/Repository b/projects/microb2009/mechboard/CVS/Repository new file mode 100644 index 0000000..b144ba8 --- /dev/null +++ b/projects/microb2009/mechboard/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/mechboard diff --git a/projects/microb2009/mechboard/CVS/Root b/projects/microb2009/mechboard/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/mechboard/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/mechboard/CVS/Template b/projects/microb2009/mechboard/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/mechboard/Makefile b/projects/microb2009/mechboard/Makefile new file mode 100644 index 0000000..34efb9f --- /dev/null +++ b/projects/microb2009/mechboard/Makefile @@ -0,0 +1,35 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../.. +# VALUE, absolute or relative path : example ../.. # + +CFLAGS += -Werror -Wextra +LDFLAGS = -T ../common/avr6.x + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c cmdline.c commands_ax12.c commands_gen.c +SRC += commands_cs.c commands_mechboard.c commands.c +SRC += i2c_protocol.c sensor.c actuator.c cs.c +SRC += arm_xy.c state.c ax12_user.c arm_highlevel.c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +AVRDUDE_DELAY=50 + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/mechboard/actuator.c b/projects/microb2009/mechboard/actuator.c new file mode 100644 index 0000000..a36a70c --- /dev/null +++ b/projects/microb2009/mechboard/actuator.c @@ -0,0 +1,163 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: actuator.c,v 1.4 2009-04-24 19:30:41 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> + +#include "../common/i2c_commands.h" +#include "actuator.h" +#include "ax12_user.h" +#include "main.h" + +#define FINGER_DEBUG(args...) DEBUG(E_USER_FINGER, args) +#define FINGER_NOTICE(args...) NOTICE(E_USER_FINGER, args) +#define FINGER_ERROR(args...) ERROR(E_USER_FINGER, args) + +struct finger { + int8_t event; + uint16_t destination; +}; + +struct finger finger; + +static void finger_goto_cb(void *); + +/* schedule a single event for the finger */ +static void finger_schedule_event(struct finger *finger) +{ + uint8_t flags; + int8_t ret; + + IRQ_LOCK(flags); + ret = scheduler_add_event(SCHEDULER_SINGLE, + (void *)finger_goto_cb, + finger, 1, ARM_PRIO); + if (ret == -1) { + IRQ_UNLOCK(flags); + FINGER_ERROR("Cannot load finger event"); + return; + } + finger->event = ret; + IRQ_UNLOCK(flags); +} + +static void finger_goto_cb(void *data) +{ + uint8_t flags; + struct finger *finger = data; + uint16_t position; + + IRQ_LOCK(flags); + finger->event = -1; + position = finger->destination; + IRQ_UNLOCK(flags); + FINGER_DEBUG("goto_cb %d", position); + ax12_user_write_int(&gen.ax12, FINGER_AX12, + AA_GOAL_POSITION_L, position); +} + +/* load an event that will move the ax12 for us */ +void finger_goto(uint16_t position) +{ + uint8_t flags; + FINGER_NOTICE("goto %d", position); + + IRQ_LOCK(flags); + finger.destination = position; + if (finger.event != -1) { + IRQ_UNLOCK(flags); + return; /* nothing to do, event already scheduled */ + } + IRQ_UNLOCK(flags); + finger_schedule_event(&finger); +} + +static void finger_init(void) +{ + finger.event = -1; + finger.destination = 0; + /* XXX set pos ? */ +} + +uint16_t finger_get_goal_pos(void) +{ + return finger.destination; +} + +uint8_t finger_get_side(void) +{ + if (finger.destination <= FINGER_CENTER) + return I2C_LEFT_SIDE; + return I2C_RIGHT_SIDE; +} + +/**********/ + +#define SERVO_LEFT_OUT 400 +#define SERVO_LEFT_1LIN 520 +#define SERVO_LEFT_2LIN 485 +#define SERVO_RIGHT_OUT 290 +#define SERVO_RIGHT_1LIN 155 +#define SERVO_RIGHT_2LIN 180 + +void servo_lintel_out(void) +{ + mechboard.servo_lintel_left = SERVO_LEFT_OUT; + mechboard.servo_lintel_right = SERVO_RIGHT_OUT; +} + +void servo_lintel_1lin(void) +{ + mechboard.servo_lintel_left = SERVO_LEFT_1LIN; + mechboard.servo_lintel_right = SERVO_RIGHT_1LIN; +} + +void servo_lintel_2lin(void) +{ + mechboard.servo_lintel_left = SERVO_LEFT_2LIN; + mechboard.servo_lintel_right = SERVO_RIGHT_2LIN; +} + +/**********/ + +void actuator_init(void) +{ + finger_init(); + servo_lintel_out(); +} diff --git a/projects/microb2009/mechboard/actuator.h b/projects/microb2009/mechboard/actuator.h new file mode 100644 index 0000000..c55f564 --- /dev/null +++ b/projects/microb2009/mechboard/actuator.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: actuator.h,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#define FINGER_RIGHT 666 +#define FINGER_RIGHT_RELAX 621 +#define FINGER_CENTER_RIGHT 491 +#define FINGER_CENTER 490 +#define FINGER_CENTER_LEFT 489 +#define FINGER_LEFT 340 +#define FINGER_LEFT_RELAX 385 + +void finger_goto(uint16_t position); +uint16_t finger_get_goal_pos(void); +uint8_t finger_get_side(void); + +void servo_lintel_out(void); +void servo_lintel_1lin(void); +void servo_lintel_2lin(void); + +void actuator_init(void); + diff --git a/projects/microb2009/mechboard/adc_config.h b/projects/microb2009/mechboard/adc_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/mechboard/arm_highlevel.c b/projects/microb2009/mechboard/arm_highlevel.c new file mode 100644 index 0000000..abda4d4 --- /dev/null +++ b/projects/microb2009/mechboard/arm_highlevel.c @@ -0,0 +1,644 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: arm_highlevel.c,v 1.4 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/pgmspace.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "arm_xy.h" +#include "arm_highlevel.h" + +#define WRIST_ANGLE_PUMP1 -2 /* in degree */ +#define WRIST_ANGLE_PUMP2 103 /* in degree */ + +struct arm *arm_num2ptr(uint8_t arm_num) +{ + switch (arm_num) { + case ARM_LEFT_NUM: + return &left_arm; + case ARM_RIGHT_NUM: + return &right_arm; + default: + return NULL; + } +} + +#define ARM_MAX_H 110 +#define ARM_STRAIGHT_D 254 +#define ARM_STRAIGHT_H 0 + +void arm_goto_straight(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_STRAIGHT_D, ARM_STRAIGHT_H, angle); +} + +/* position to get a column */ +#define ARM_GET_D 60 +#define ARM_GET_H -140 + +void arm_goto_get_column(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_GET_D, ARM_GET_H, angle); +} + +/* position to get a column */ +#define ARM_PREPARE_D 62 +#define ARM_PREPARE_H -133 + +void arm_goto_prepare_get(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_PREPARE_D, ARM_PREPARE_H, angle); +} + +#define ARM_INTERMEDIATE_D (65) +#define ARM_INTERMEDIATE_H (-115) + +void arm_goto_intermediate_get(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_INTERMEDIATE_D, ARM_INTERMEDIATE_H, angle); +} + +/* used in prepare pickup */ +#define ARM_INTERMEDIATE_FRONT_D (90) +#define ARM_INTERMEDIATE_FRONT_H (-105) + +void arm_goto_intermediate_front_get(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_INTERMEDIATE_FRONT_D, + ARM_INTERMEDIATE_FRONT_H, angle); +} + +/* ****** */ + +#define ARM_PREPARE_EJECT_D (70) +#define ARM_PREPARE_EJECT_H (-50) + +void arm_goto_prepare_eject(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_PREPARE_EJECT_D, ARM_PREPARE_EJECT_H, angle); +} + +#define ARM_EJECT_D (200) +#define ARM_EJECT_H (30) + +void arm_goto_eject(uint8_t arm_num, uint8_t pump_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + arm_do_xy(arm, ARM_EJECT_D, ARM_EJECT_H, angle); +} + +/* ****** */ + +#define ARM_PREPARE_GET_LINTEL_INSIDE1_D 90 +#define ARM_PREPARE_GET_LINTEL_INSIDE1_H -75 +#define ARM_PREPARE_GET_LINTEL_INSIDE1_A -30 +void arm_goto_prepare_get_lintel_inside1(void) +{ + arm_do_xy(&left_arm, ARM_PREPARE_GET_LINTEL_INSIDE1_D, + ARM_PREPARE_GET_LINTEL_INSIDE1_H, + ARM_PREPARE_GET_LINTEL_INSIDE1_A); + arm_do_xy(&right_arm, ARM_PREPARE_GET_LINTEL_INSIDE1_D, + ARM_PREPARE_GET_LINTEL_INSIDE1_H, + ARM_PREPARE_GET_LINTEL_INSIDE1_A); +} + +#define ARM_PREPARE_GET_LINTEL_INSIDE2_D 30 +#define ARM_PREPARE_GET_LINTEL_INSIDE2_H -75 +#define ARM_PREPARE_GET_LINTEL_INSIDE2_A -30 +void arm_goto_prepare_get_lintel_inside2(uint8_t lintel_count) +{ + uint16_t d; + d = ARM_PREPARE_GET_LINTEL_INSIDE2_D; + if (lintel_count == 2) + d += 34; + arm_do_xy(&left_arm, d, + ARM_PREPARE_GET_LINTEL_INSIDE2_H, + ARM_PREPARE_GET_LINTEL_INSIDE2_A); + arm_do_xy(&right_arm, d, + ARM_PREPARE_GET_LINTEL_INSIDE2_H, + ARM_PREPARE_GET_LINTEL_INSIDE2_A); +} + +#define ARM_GET_LINTEL_INSIDE_D 10 +#define ARM_GET_LINTEL_INSIDE_H -75 +#define ARM_GET_LINTEL_INSIDE_A -30 +void arm_goto_get_lintel_inside(uint8_t lintel_count) +{ + uint16_t d; + d = ARM_GET_LINTEL_INSIDE_D; + if (lintel_count == 2) + d += 34; + arm_do_xy(&left_arm, d, + ARM_GET_LINTEL_INSIDE_H, + ARM_GET_LINTEL_INSIDE_A); + arm_do_xy(&right_arm, d, + ARM_GET_LINTEL_INSIDE_H, + ARM_GET_LINTEL_INSIDE_A); +} + +#define ARM_PREPARE_BUILD_LINTEL1_D 30 +#define ARM_PREPARE_BUILD_LINTEL1_H -50 +#define ARM_PREPARE_BUILD_LINTEL1_A -30 +void arm_goto_prepare_build_lintel1(void) +{ + arm_do_xy(&left_arm, ARM_PREPARE_BUILD_LINTEL1_D, + ARM_PREPARE_BUILD_LINTEL1_H, + ARM_PREPARE_BUILD_LINTEL1_A); + arm_do_xy(&right_arm, ARM_PREPARE_BUILD_LINTEL1_D, + ARM_PREPARE_BUILD_LINTEL1_H, + ARM_PREPARE_BUILD_LINTEL1_A); +} + +#define ARM_PREPARE_BUILD_LINTEL2_D 80 +#define ARM_PREPARE_BUILD_LINTEL2_H -110 +#define ARM_PREPARE_BUILD_LINTEL2_A 60 +void arm_goto_prepare_build_lintel2(uint8_t level) +{ + int16_t h; + if (level < 3) + level = 3; + h = (int16_t)level * 30 + ARM_PREPARE_BUILD_LINTEL2_H; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(&left_arm, ARM_PREPARE_BUILD_LINTEL2_D, + h, ARM_PREPARE_BUILD_LINTEL2_A); + arm_do_xy(&right_arm, ARM_PREPARE_BUILD_LINTEL2_D, + h, ARM_PREPARE_BUILD_LINTEL2_A); +} + +#define ARM_PREPARE_BUILD_LINTEL3_D 205 +#define ARM_PREPARE_BUILD_LINTEL3_H -100 +#define ARM_PREPARE_BUILD_LINTEL3_A 50 +void arm_goto_prepare_build_lintel3(uint8_t level) +{ + int16_t h; + if (level < 2) + level = 2; + h = (int16_t)level * 30 + ARM_PREPARE_BUILD_LINTEL3_H; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(&left_arm, ARM_PREPARE_BUILD_LINTEL3_D, + h, ARM_PREPARE_BUILD_LINTEL3_A); + arm_do_xy(&right_arm, ARM_PREPARE_BUILD_LINTEL3_D, + h, ARM_PREPARE_BUILD_LINTEL3_A); +} + +#define ARM_BUILD_LINTEL_D 205 +#define ARM_BUILD_LINTEL_H -128 +#define ARM_BUILD_LINTEL_A 50 +void arm_goto_build_lintel(uint8_t level) +{ + int16_t h; + h = (int16_t)level * 30 + ARM_BUILD_LINTEL_H; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(&left_arm, ARM_BUILD_LINTEL_D, + h, ARM_BUILD_LINTEL_A); + arm_do_xy(&right_arm, ARM_BUILD_LINTEL_D, + h, ARM_BUILD_LINTEL_A); +} + +/* ****** */ + +#define ARM_PREPARE_GET_LINTEL_DISP_D 190 +#define ARM_PREPARE_GET_LINTEL_DISP_H -40 +#define ARM_PREPARE_GET_LINTEL_DISP_A 50 +void arm_goto_prepare_get_lintel_disp(void) +{ + arm_do_xy(&left_arm, ARM_PREPARE_GET_LINTEL_DISP_D, + ARM_PREPARE_GET_LINTEL_DISP_H, + ARM_PREPARE_GET_LINTEL_DISP_A); + arm_do_xy(&right_arm, ARM_PREPARE_GET_LINTEL_DISP_D, + ARM_PREPARE_GET_LINTEL_DISP_H, + ARM_PREPARE_GET_LINTEL_DISP_A); +} + +#define ARM_GET_LINTEL_DISP_D 190 +#define ARM_GET_LINTEL_DISP_H -70 +#define ARM_GET_LINTEL_DISP_A 40 +void arm_goto_get_lintel_disp(void) +{ + arm_do_xy(&left_arm, ARM_GET_LINTEL_DISP_D, + ARM_GET_LINTEL_DISP_H, + ARM_GET_LINTEL_DISP_A); + arm_do_xy(&right_arm, ARM_GET_LINTEL_DISP_D, + ARM_GET_LINTEL_DISP_H, + ARM_GET_LINTEL_DISP_A); +} + +#define ARM_PREPARE_PUT_LINTEL_DISP_D 130 +#define ARM_PREPARE_PUT_LINTEL_DISP_H 0 +#define ARM_PREPARE_PUT_LINTEL_DISP_A 0 +void arm_goto_prepare_put_lintel(void) +{ + arm_do_xy(&left_arm, ARM_PREPARE_PUT_LINTEL_DISP_D, + ARM_PREPARE_PUT_LINTEL_DISP_H, + ARM_PREPARE_PUT_LINTEL_DISP_A); + arm_do_xy(&right_arm, ARM_PREPARE_PUT_LINTEL_DISP_D, + ARM_PREPARE_PUT_LINTEL_DISP_H, + ARM_PREPARE_PUT_LINTEL_DISP_A); +} + +#define ARM_PUT_LINTEL_DISP_D 30 +#define ARM_PUT_LINTEL_DISP_H -60 +#define ARM_PUT_LINTEL_DISP_A -30 +void arm_goto_put_lintel(uint8_t lintel_count) +{ + arm_do_xy(&left_arm, + ARM_PUT_LINTEL_DISP_D + lintel_count * 30, + ARM_PUT_LINTEL_DISP_H, + ARM_PUT_LINTEL_DISP_A); + arm_do_xy(&right_arm, + ARM_PUT_LINTEL_DISP_D + lintel_count * 30, + ARM_PUT_LINTEL_DISP_H, + ARM_PUT_LINTEL_DISP_A); +} + +/* ****** */ + + +#define ARM_LOADED_D 100 +#define ARM_LOADED_H 0 + +void arm_goto_loaded(uint8_t arm_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + arm_do_xy(arm, ARM_LOADED_D, ARM_LOADED_H, WRIST_ANGLE_PUMP2); +} + + +/* for columns */ +#define ARM_PREPARE_BUILD_INSIDE_D 90 +#define ARM_PREPARE_BUILD_INSIDE_H -45 + +void arm_goto_prepare_build_inside(uint8_t arm_num, uint8_t pump_num, uint8_t level) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + int16_t h; + if (level < 2) + level = 2; + h = (int16_t)level * 30 + ARM_PREPARE_BUILD_INSIDE_H; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(arm, ARM_PREPARE_BUILD_INSIDE_D, h, angle); +} + +#define ARM_PREPARE_AUTOBUILD_INSIDE_D 90 +#define ARM_PREPARE_AUTOBUILD_INSIDE_H -70 + +void arm_goto_prepare_autobuild_inside(uint8_t arm_num, uint8_t pump_num, uint8_t level) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + int16_t h; + if (level < 2) + level = 2; + h = (int16_t)level * 30 + ARM_PREPARE_AUTOBUILD_INSIDE_H; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(arm, ARM_PREPARE_AUTOBUILD_INSIDE_D, h, angle); +} + +#define ARM_PREPARE_AUTOBUILD_OUTSIDE_D 210 /* not used, see dist below */ +#define ARM_PREPARE_AUTOBUILD_OUTSIDE_H_P1 (-110) +#define ARM_PREPARE_AUTOBUILD_OUTSIDE_H_P2 (-90) + +void arm_goto_prepare_autobuild_outside(uint8_t arm_num, uint8_t pump_num, + uint8_t level, uint8_t dist) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + int16_t h; + if (pump_num == PUMP_LEFT1_NUM || pump_num == PUMP_RIGHT1_NUM) + h = (int16_t)level * 30 + ARM_PREPARE_AUTOBUILD_OUTSIDE_H_P1; + else + h = (int16_t)level * 30 + ARM_PREPARE_AUTOBUILD_OUTSIDE_H_P2; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(arm, dist, h, angle); +} + +#define ARM_AUTOBUILD_D_P1 208 /* not used, see dist below */ +#define ARM_AUTOBUILD_D_P2 210 /* not used, see dist below */ +#define ARM_AUTOBUILD_D_P1_OFFSET (-2) +#define ARM_AUTOBUILD_D_P2_OFFSET (0) +#define ARM_AUTOBUILD_H_P1 (-133) +#define ARM_AUTOBUILD_H_P2 (-130) + +void arm_goto_autobuild(uint8_t arm_num, uint8_t pump_num, + uint8_t level, uint8_t dist) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t angle = pump_num2angle(pump_num); + int16_t h; + if (pump_num == PUMP_LEFT1_NUM || pump_num == PUMP_RIGHT1_NUM) { + h = (int16_t)level * 30 + ARM_AUTOBUILD_H_P1; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(arm, dist + ARM_AUTOBUILD_D_P1_OFFSET, h, angle); + } + else { + h = (int16_t)level * 30 + ARM_AUTOBUILD_H_P2; + if (h > ARM_MAX_H) + h = ARM_MAX_H; + arm_do_xy(arm, dist + ARM_AUTOBUILD_D_P2_OFFSET, h, angle); + } +} + +#define ARM_PUSH_TEMPLE_D 170 +#define ARM_PUSH_TEMPLE_H -165 + +void arm_goto_push_temple(uint8_t arm_num, uint8_t level) +{ + struct arm *arm = arm_num2ptr(arm_num); + int16_t h = ARM_PUSH_TEMPLE_H; + + /* level can be 0 or 1 */ + if (level) + h += 30; + arm_do_xy(arm, ARM_PUSH_TEMPLE_D, h, WRIST_ANGLE_PUMP1); +} + +#define ARM_PREPARE_PUSH_TEMPLE_D 120 +#define ARM_PREPARE_PUSH_TEMPLE_H -60 + +void arm_goto_prepare_push_temple(uint8_t arm_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + arm_do_xy(arm, ARM_PREPARE_PUSH_TEMPLE_D, + ARM_PREPARE_PUSH_TEMPLE_H, WRIST_ANGLE_PUMP1); +} + +#define ARM_PUSH_TEMPLE_DISC_D1 215 +#define ARM_PUSH_TEMPLE_DISC_H1 -100 +#define ARM_PUSH_TEMPLE_DISC_D2 190 +#define ARM_PUSH_TEMPLE_DISC_H2 -65 + +void arm_goto_push_temple_disc(uint8_t arm_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + int8_t pump_num; + + pump_num = arm_get_busy_pump(arm_num); + if (pump_num == -1) + arm_do_xy(arm, ARM_PUSH_TEMPLE_DISC_D1, + ARM_PUSH_TEMPLE_DISC_H1, WRIST_ANGLE_PUMP1); + else + arm_do_xy(arm, ARM_PUSH_TEMPLE_DISC_D2, + ARM_PUSH_TEMPLE_DISC_H2, WRIST_ANGLE_PUMP1); +} + +#define ARM_PREPARE_PUSH_TEMPLE_DISC_D 100 +#define ARM_PREPARE_PUSH_TEMPLE_DISC_H -80 + +void arm_goto_prepare_push_temple_disc(uint8_t arm_num) +{ + struct arm *arm = arm_num2ptr(arm_num); + arm_do_xy(arm, ARM_PREPARE_PUSH_TEMPLE_DISC_D, + ARM_PREPARE_PUSH_TEMPLE_DISC_H, WRIST_ANGLE_PUMP1); +} + +void arm_prepare_free_pumps(void) +{ + int8_t pump_num; + + pump_num = arm_get_free_pump(ARM_LEFT_NUM); + if (pump_num != -1) + arm_goto_prepare_get(ARM_LEFT_NUM, pump_num); + pump_num = arm_get_free_pump(ARM_RIGHT_NUM); + if (pump_num != -1) + arm_goto_prepare_get(ARM_RIGHT_NUM, pump_num); +} + + +/* return the id of a free pump on this arm */ +int8_t arm_get_free_pump(uint8_t arm_num) +{ + switch (arm_num) { + case ARM_LEFT_NUM: + if (pump_is_free(PUMP_LEFT1_NUM) && + pump_is_free(PUMP_LEFT2_NUM)) + return PUMP_LEFT1_NUM; + else if (pump_is_free(PUMP_LEFT2_NUM)) + return PUMP_LEFT2_NUM; + return -1; + case ARM_RIGHT_NUM: + if (pump_is_free(PUMP_RIGHT1_NUM) && + pump_is_free(PUMP_RIGHT2_NUM)) + return PUMP_RIGHT1_NUM; + else if (pump_is_free(PUMP_RIGHT2_NUM)) + return PUMP_RIGHT2_NUM; + return -1; + default: + return -1; + } +} + +/* return the id of a busy pump on this arm */ +int8_t arm_get_busy_pump(uint8_t arm_num) +{ + switch (arm_num) { + case ARM_LEFT_NUM: + if (pump_is_busy(PUMP_LEFT2_NUM)) + return PUMP_LEFT2_NUM; + else if (pump_is_busy(PUMP_LEFT1_NUM)) + return PUMP_LEFT1_NUM; + return -1; + case ARM_RIGHT_NUM: + if (pump_is_busy(PUMP_RIGHT2_NUM)) + return PUMP_RIGHT2_NUM; + else if (pump_is_busy(PUMP_RIGHT1_NUM)) + return PUMP_RIGHT1_NUM; + return -1; + default: + return -1; + } +} + +uint8_t arm_wait_both(uint8_t mask) +{ + uint8_t ret; + ret = arm_wait_traj_end(&left_arm, mask); + if (ret != ARM_TRAJ_END && ret != ARM_TRAJ_NEAR) + return ret; + return arm_wait_traj_end(&right_arm, mask); +} + +uint8_t arm_wait_select(uint8_t left, uint8_t right, uint8_t mask) +{ + if (left && right) + return arm_wait_both(mask); + if (left) + return arm_wait_traj_end(&left_arm, mask); + if (right) + return arm_wait_traj_end(&right_arm, mask); + return ARM_TRAJ_END; +} + +/*********************/ + +int16_t *pump_num2ptr(uint8_t pump_num) +{ + switch (pump_num) { + case PUMP_LEFT1_NUM: + return &mechboard.pump_left1; + case PUMP_RIGHT1_NUM: + return &mechboard.pump_right1; + case PUMP_LEFT2_NUM: + return &mechboard.pump_left2; + case PUMP_RIGHT2_NUM: + return &mechboard.pump_right2; + default: + return NULL; + } +} + +void pump_set(uint8_t pump_num, int16_t val) +{ + int16_t *pump_ptr = pump_num2ptr(pump_num); + + *pump_ptr = val; + + switch (pump_num) { + case PUMP_RIGHT1_NUM: + pwm_ng_set(RIGHT_PUMP1_PWM, val); + break; + case PUMP_RIGHT2_NUM: + pwm_ng_set(RIGHT_PUMP2_PWM, val); + break; + + /* no pwm, it's remote */ + case PUMP_LEFT1_NUM: + case PUMP_LEFT2_NUM: + default: + break; + } +} + +int16_t pump_num2angle(uint8_t pump_num) +{ + switch (pump_num) { + case PUMP_LEFT1_NUM: + case PUMP_RIGHT1_NUM: + return WRIST_ANGLE_PUMP1; + case PUMP_LEFT2_NUM: + case PUMP_RIGHT2_NUM: + return WRIST_ANGLE_PUMP2; + default: + return 0; + } +} + +void pump_mark_busy(uint8_t pump_num) +{ + switch (pump_num) { + case PUMP_LEFT1_NUM: + mechboard.column_flags |= I2C_MECHBOARD_COLUMN_L1; + break; + case PUMP_RIGHT1_NUM: + mechboard.column_flags |= I2C_MECHBOARD_COLUMN_R1; + break; + case PUMP_LEFT2_NUM: + mechboard.column_flags |= I2C_MECHBOARD_COLUMN_L2; + break; + case PUMP_RIGHT2_NUM: + mechboard.column_flags |= I2C_MECHBOARD_COLUMN_R2; + break; + default: + break; + } + +} + +void pump_mark_free(uint8_t pump_num) +{ + switch (pump_num) { + case PUMP_LEFT1_NUM: + mechboard.column_flags &= (~I2C_MECHBOARD_COLUMN_L1); + break; + case PUMP_RIGHT1_NUM: + mechboard.column_flags &= (~I2C_MECHBOARD_COLUMN_R1); + break; + case PUMP_LEFT2_NUM: + mechboard.column_flags &= (~I2C_MECHBOARD_COLUMN_L2); + break; + case PUMP_RIGHT2_NUM: + mechboard.column_flags &= (~I2C_MECHBOARD_COLUMN_R2); + break; + default: + break; + } + +} + +uint8_t pump_is_free(uint8_t pump_num) +{ + switch (pump_num) { + case PUMP_LEFT1_NUM: + return !(mechboard.column_flags & I2C_MECHBOARD_COLUMN_L1); + case PUMP_RIGHT1_NUM: + return !(mechboard.column_flags & I2C_MECHBOARD_COLUMN_R1); + case PUMP_LEFT2_NUM: + return !(mechboard.column_flags & I2C_MECHBOARD_COLUMN_L2); + case PUMP_RIGHT2_NUM: + return !(mechboard.column_flags & I2C_MECHBOARD_COLUMN_R2); + default: + return 0; + } +} + +uint8_t pump_is_busy(uint8_t pump_num) +{ + return !pump_is_free(pump_num); +} diff --git a/projects/microb2009/mechboard/arm_highlevel.h b/projects/microb2009/mechboard/arm_highlevel.h new file mode 100644 index 0000000..eaf3ae2 --- /dev/null +++ b/projects/microb2009/mechboard/arm_highlevel.h @@ -0,0 +1,84 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: arm_highlevel.h,v 1.4 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#define ARM_LEFT_NUM 0 +#define ARM_RIGHT_NUM 1 + +#define PUMP_LEFT1_NUM 0 +#define PUMP_RIGHT1_NUM 1 +#define PUMP_LEFT2_NUM 2 +#define PUMP_RIGHT2_NUM 3 + +struct arm *arm_num2ptr(uint8_t arm_num); + +void arm_goto_straight(uint8_t arm_num, uint8_t pump_num); +void arm_goto_get_column(uint8_t arm_num, uint8_t pump_num); +void arm_goto_prepare_get(uint8_t arm_num, uint8_t pump_num); +void arm_goto_intermediate_get(uint8_t arm_num, uint8_t pump_num); +void arm_goto_intermediate_front_get(uint8_t arm_num, uint8_t pump_num); +void arm_goto_prepare_eject(uint8_t arm_num, uint8_t pump_num); +void arm_goto_eject(uint8_t arm_num, uint8_t pump_num); +void arm_goto_loaded(uint8_t arm_num); +void arm_goto_prepare_build_inside(uint8_t arm_num, uint8_t pump_num, + uint8_t level); +void arm_goto_prepare_autobuild_inside(uint8_t arm_num, uint8_t pump_num, + uint8_t level); +void arm_goto_prepare_autobuild_outside(uint8_t arm_num, uint8_t pump_num, + uint8_t level, uint8_t dist); +void arm_goto_autobuild(uint8_t arm_num, uint8_t pump_num, + uint8_t level, uint8_t dist); + +void arm_goto_prepare_get_lintel_inside1(void); +void arm_goto_prepare_get_lintel_inside2(uint8_t lintel_count); +void arm_goto_get_lintel_inside(uint8_t lintel_count); +void arm_goto_prepare_build_lintel1(void); +void arm_goto_prepare_build_lintel2(uint8_t level); +void arm_goto_prepare_build_lintel3(uint8_t level); +void arm_goto_build_lintel(uint8_t level); + +void arm_goto_prepare_get_lintel_disp(void); +void arm_goto_get_lintel_disp(void); + +void arm_goto_prepare_put_lintel(void); +void arm_goto_put_lintel(uint8_t lintel_count); +void arm_goto_prepare_push_temple(uint8_t arm_num); +void arm_goto_push_temple(uint8_t arm_num, uint8_t level); +void arm_goto_prepare_push_temple_disc(uint8_t arm_num); +void arm_goto_push_temple_disc(uint8_t arm_num); + +void arm_prepare_free_pumps(void); +uint8_t arm_wait_both(uint8_t mask); +uint8_t arm_wait_select(uint8_t left, uint8_t right, uint8_t mask); + +/* return the id of the free pump for the arm, or return -1 */ +int8_t arm_get_free_pump(uint8_t arm_num); +int8_t arm_get_busy_pump(uint8_t arm_num); + +#define PUMP_ON 3400 +#define PUMP_OFF 0 +#define PUMP_REVERSE -3400 + +void pump_set(uint8_t pump_num, int16_t val); +int16_t pump_num2angle(uint8_t pump_num); +void pump_mark_busy(uint8_t pump_num); +void pump_mark_free(uint8_t pump_num); +uint8_t pump_is_free(uint8_t pump_num); +uint8_t pump_is_busy(uint8_t pump_num); diff --git a/projects/microb2009/mechboard/arm_xy.c b/projects/microb2009/mechboard/arm_xy.c new file mode 100644 index 0000000..2690844 --- /dev/null +++ b/projects/microb2009/mechboard/arm_xy.c @@ -0,0 +1,809 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: arm_xy.c,v 1.5 2009-11-08 17:25:00 zer0 Exp $ + * + * Fabrice DESCLAUX <serpilliere@droids-corp.org> + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <math.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/pgmspace.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> + +#include "main.h" +#include "cmdline.h" +#include "arm_xy.h" +#include "ax12_user.h" + +#define ARM_DEBUG(args...) DEBUG(E_USER_ARM, args) +#define ARM_NOTICE(args...) NOTICE(E_USER_ARM, args) +#define ARM_ERROR(args...) ERROR(E_USER_ARM, args) + +#define DEG(x) (((double)(x)) * (180.0 / M_PI)) +#define RAD(x) (((double)(x)) * (M_PI / 180.0)) +#define M_2PI (2*M_PI) + +/* physical location/dimensions of arm */ +#define ARM_S_LEN 124. +#define ARM_E_LEN 130. + +/* timeout after 1 second if position is not reached */ +#define ARM_GLOBAL_TIMEOUT 1000000L + +/* timeout 100ms after position is reached if not in window */ +#define ARM_WINDOW_TIMEOUT 200000L + +/* default (template) period, but real one is variable */ +#define ARM_PERIOD 50000L +#define ARM_MAX_DIST 40L + +/* we pos reached, check arm in window every period */ +#define ARM_SURVEY_PERIOD 25000UL /* in us */ + +/* number of steps/s */ +#define ARM_AX12_MAX_SPEED (800L) + +/* Maximum number of steps in one ARM_PERIOD */ +#define ARM_MAX_E (((ARM_AX12_MAX_SPEED*ARM_PERIOD)/1000000L)) +/* 4000 steps/CS => 800step/ms */ +#define ARM_MAX_S ((800L*ARM_PERIOD)/1000L) + + +/* window limits in ax12/cs unit */ +#define ARM_SHOULDER_WINDOW_POS 250 +#define ARM_ELBOW_WINDOW_POS 8 +#define ARM_ELBOW_WINDOW_SPEED 100 +#define ARM_WRIST_WINDOW_POS 8 +#define ARM_WRIST_WINDOW_SPEED 100 + +/* default and max speeds */ +#define SHOULDER_DEFAULT_SPEED 800 +#define ELBOW_DEFAULT_SPEED 0x3ff +#define SHOULDER_MAX_SPEED 10000 +#define ELBOW_MAX_SPEED 0x3ff + +/* window status flags */ +#define SHOULDER_NOT_IN_WIN 1 +#define ELBOW_NOT_IN_WIN 2 +#define WRIST_NOT_IN_WIN 4 + +static void wrist_angle_deg2robot_l(double wrist_deg, double *wrist_out); +static void angle_rad2robot_l(double shoulder_rad, double elbow_rad, + double *shoulder_robot, double *elbow_robot); +static void angle_robot2rad_l(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad); +static void wrist_angle_deg2robot_r(double wrist_deg, double *wrist_out); +static void angle_rad2robot_r(double shoulder_rad, double elbow_rad, + double *shoulder_robot, double *elbow_robot); +static void angle_robot2rad_r(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad); + +static void arm_schedule_event(struct arm *arm, uint32_t time); + +struct arm left_arm = { + .config = { + .wrist_angle_deg2robot = wrist_angle_deg2robot_l, + .angle_rad2robot = angle_rad2robot_l, + .angle_robot2rad = angle_robot2rad_l, + .elbow_ax12 = L_ELBOW_AX12, + .wrist_ax12 = L_WRIST_AX12, + }, +}; + +struct arm right_arm = { + .config = { + .wrist_angle_deg2robot = wrist_angle_deg2robot_r, + .angle_rad2robot = angle_rad2robot_r, + .angle_robot2rad = angle_robot2rad_r, + .elbow_ax12 = R_ELBOW_AX12, + .wrist_ax12 = R_WRIST_AX12, + }, +}; + +/* process shoulder + elbow angles from height and distance */ +int8_t cart2angle(int32_t h_int, int32_t d_int, double *alpha, double *beta) +{ + double h, d, l; + double elbow, shoulder; + + d = d_int; + h = h_int; + l = sqrt(d*d + h*h); + if (l > (ARM_S_LEN + ARM_E_LEN)) + return -1; + + elbow = -acos((d*d + h*h - ARM_E_LEN*ARM_E_LEN - + ARM_S_LEN*ARM_S_LEN) / (2*ARM_S_LEN*ARM_E_LEN)); + shoulder = atan2(h,d) - atan2(ARM_E_LEN*sin(elbow), + ARM_S_LEN+ARM_E_LEN*cos(elbow)); + + *alpha = shoulder; + *beta = elbow; + + return 0; +} + + +/* process height and distance from shoulder + elbow angles */ +void angle2cart(double alpha, double beta, int32_t *h, int32_t *d) +{ + double tmp_a; + int32_t tmp_h, tmp_d; + + tmp_h = ARM_S_LEN * sin(alpha); + tmp_d = ARM_S_LEN * cos(alpha); + + tmp_a = alpha+beta; + *h = tmp_h + ARM_E_LEN * sin(tmp_a); + *d = tmp_d + ARM_E_LEN * cos(tmp_a); +} + +/*** left arm */ + +#define ARM_LEFT_S_OFFSET -1150. +#define ARM_LEFT_E_OFFSET 476. +#define ARM_LEFT_W_OFFSET 90. + +static void wrist_angle_deg2robot_l(double wrist_deg, double *wrist_out) +{ + *wrist_out = -wrist_deg * 3.41 + ARM_LEFT_W_OFFSET; +} + +/* convert an angle in radian into a robot-specific unit + * for shoulder and elbow for LEFT ARM*/ +static void angle_rad2robot_l(double shoulder_rad, double elbow_rad, + double *shoulder_robot, double *elbow_robot) +{ + *shoulder_robot = shoulder_rad * 4 * 66 * 512. / (2*M_PI) + ARM_LEFT_S_OFFSET; + *elbow_robot = -elbow_rad * 3.41 * 360. / (2*M_PI) + ARM_LEFT_E_OFFSET; +} + +/* convert a robot-specific unit into an angle in radian + * for shoulder and elbow for LEFT ARM */ +static void angle_robot2rad_l(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad) +{ + *shoulder_rad = ((shoulder_robot - ARM_LEFT_S_OFFSET) * (2*M_PI))/(4 * 66 * 512.); + *elbow_rad = -((elbow_robot - ARM_LEFT_E_OFFSET) * (2*M_PI))/(3.41 * 360.); +} + +/*** right arm */ + +#define ARM_RIGHT_S_OFFSET 1150. +#define ARM_RIGHT_E_OFFSET 673. +#define ARM_RIGHT_W_OFFSET 935. + +static void wrist_angle_deg2robot_r(double wrist_deg, double *wrist_out) +{ + *wrist_out = wrist_deg * 3.41 + ARM_RIGHT_W_OFFSET; +} + +/* convert an angle in radian into a robot-specific unit + * for shoulder and elbow */ +static void angle_rad2robot_r(double shoulder_rad, double elbow_rad, + double *shoulder_robot, double *elbow_robot) +{ + *shoulder_robot = -shoulder_rad * 4 * 66 * 512. / (2*M_PI) + ARM_RIGHT_S_OFFSET; + *elbow_robot = elbow_rad * 3.41 * 360. / (2*M_PI) + ARM_RIGHT_E_OFFSET; +} + +/* convert a robot-specific unit into an angle in radian + * for shoulder and elbow */ +static void angle_robot2rad_r(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad) +{ + *shoulder_rad = -((shoulder_robot - ARM_RIGHT_S_OFFSET) * (2*M_PI))/(4 * 66 * 512.); + *elbow_rad = ((elbow_robot - ARM_RIGHT_E_OFFSET) * (2*M_PI))/(3.41 * 360.); +} + + +/* + * Fill the arm_status structure according to request. + * + * return: + * 0 => success + * < 0 => error + */ +static int8_t arm_do_step(struct arm *arm) +{ + const struct arm_config *conf = &arm->config; + const struct arm_request *req = &arm->req; + struct arm_status *status = &arm->status; + + int8_t ret; + int32_t diff_h, diff_d; /* position delta in steps */ + int32_t next_h, next_d; /* next position in steps */ + int32_t l; /* distance between cur pos and next pos */ + + double as_cur_rad, ae_cur_rad; /* current angle in rad */ + double as_next_rad, ae_next_rad; /* next angle in rad */ + double as_cur, ae_cur; /* current angle in angle_steps */ + double as_next, ae_next; /* next angle in angle_steps */ + + int32_t as_diff, ae_diff; /* angle delta in angle_steps */ + int32_t s_speed, e_speed; /* elbow/shoulder speed in angle_steps */ + + double as_coef, ae_coef; + + /* process diff between final request and current pos */ + diff_h = req->h_mm - status->h_mm; + diff_d = req->d_mm - status->d_mm; + ARM_NOTICE("goal:d=%ld,h=%ld cur:d=%ld,h=%ld diff:d=%ld,h=%ld", + req->d_mm, req->h_mm, status->d_mm, status->h_mm, + diff_d, diff_h); + + /* if distance to next point is too large, saturate it */ + l = sqrt(diff_h*diff_h + diff_d*diff_d); + if (l > ARM_MAX_DIST) { + diff_h = diff_h * ARM_MAX_DIST / l; + diff_d = diff_d * ARM_MAX_DIST / l; + } + ARM_NOTICE("l=%ld ; after max dist: diff:d=%ld,h=%ld", l, diff_d, diff_h); + + /* process next position */ + next_h = status->h_mm + diff_h; + next_d = status->d_mm + diff_d; + ARM_DEBUG("next:d=%ld,h=%ld", next_d, next_h); + + /* calculate the current angle of arm in radian */ + ret = cart2angle(status->h_mm, status->d_mm, &as_cur_rad, &ae_cur_rad); + if (ret) + return ret; + ARM_DEBUG("as_cur_rad=%f ae_cur_rad=%f", as_cur_rad, ae_cur_rad); + + /* calculate the next angle of arm in radian */ + ret = cart2angle(next_h, next_d, &as_next_rad, &ae_next_rad); + if (ret) + return ret; + ARM_DEBUG("as_next_rad=%f ae_next_rad=%f", as_next_rad, ae_next_rad); + + /* convert radian in angle_steps */ + conf->angle_rad2robot(as_cur_rad, ae_cur_rad, + &as_cur, &ae_cur); + ARM_DEBUG("as_cur=%f ae_cur=%f", as_cur, ae_cur); + conf->angle_rad2robot(as_next_rad, ae_next_rad, + &as_next, &ae_next); + ARM_DEBUG("as_next=%f ae_next=%f", as_next, ae_next); + + /* process angle delta in angle_steps */ + as_diff = as_next - as_cur; + ae_diff = ae_next - ae_cur; + ARM_DEBUG("as_diff=%ld ae_diff=%ld", as_diff, ae_diff); + + /* update position status */ + status->h_mm = next_h; + status->d_mm = next_d; + status->shoulder_angle_steps = as_next; + status->elbow_angle_steps = ae_next; + status->shoulder_angle_rad = as_next_rad; + status->elbow_angle_rad = ae_next_rad; + + /* we reached destination, nothing to do */ + if (as_diff == 0 && ae_diff == 0) { + status->shoulder_speed = SHOULDER_DEFAULT_SPEED; + status->elbow_speed = ELBOW_DEFAULT_SPEED; + status->next_update_time = 0; + ARM_NOTICE("reaching end"); + return 0; + } + + /* test if one actuator is already in position */ + if (as_diff == 0) { + ARM_DEBUG("shoulder reached destination"); + ae_coef = (double)ARM_MAX_E / (double)ae_diff; + status->next_update_time = ARM_PERIOD * ABS(ae_coef); + e_speed = ABS(ae_coef) * ABS(ae_diff); + s_speed = ARM_MAX_S; + } + else if (ae_diff == 0) { + ARM_DEBUG("elbow reached destination"); + as_coef = (double)ARM_MAX_S / (double)as_diff; + status->next_update_time = ARM_PERIOD / ABS(as_coef); + e_speed = ARM_MAX_E; + s_speed = ABS(as_coef) * ABS(as_diff); + } + + else { + as_coef = (double)ARM_MAX_S / (double)as_diff; + ae_coef = (double)ARM_MAX_E / (double)ae_diff; + + ARM_DEBUG("as_coef=%f ae_coef=%f", as_coef, ae_coef); + + /* if elbow is limitating */ + if (ABS(as_coef) >= ABS(ae_coef)) { + ARM_DEBUG("elbow limit"); + status->next_update_time = ARM_PERIOD / ABS(ae_coef); + s_speed = ABS(ae_coef) * ABS(as_diff); + e_speed = ABS(ae_coef) * ABS(ae_diff); + } + /* else, shoulder is limitating */ + else { + ARM_DEBUG("shoulder limit"); + status->next_update_time = ARM_PERIOD / ABS(as_coef); + s_speed = ABS(as_coef) * ABS(as_diff); + e_speed = ABS(as_coef) * ABS(ae_diff); + } + } + + ARM_NOTICE("next update: %ld", status->next_update_time); + + /* convert speed in specific unit */ + status->shoulder_speed = (s_speed * CS_PERIOD) / ARM_PERIOD; + status->elbow_speed = (e_speed * 0x3ff) / ARM_MAX_E; + + ARM_DEBUG("speeds: s=%ld e=%ld", status->shoulder_speed, status->elbow_speed); + + /* avoid limits */ + if (status->shoulder_speed == 0) + status->shoulder_speed = 1; + if (status->elbow_speed == 0) + status->elbow_speed = 1; + if (status->shoulder_speed >= SHOULDER_MAX_SPEED) + status->shoulder_speed = SHOULDER_MAX_SPEED; + if (status->elbow_speed >= ELBOW_MAX_SPEED) + status->elbow_speed = ELBOW_MAX_SPEED; + + ARM_DEBUG("speeds (sat): s=%ld e=%ld", status->shoulder_speed, status->elbow_speed); + + return 0; +} + +static void arm_delete_event(struct arm *arm) +{ + if (arm->status.event == -1) + return; + ARM_DEBUG("Delete arm event"); + scheduler_del_event(arm->status.event); + arm->status.event = -1; +} + +/* write values to ax12 + cs */ +static void arm_apply(struct arm *arm) +{ + struct cs_block *csb = arm->config.csb; + const struct arm_status *st = &arm->status; + + ARM_DEBUG("arm_apply"); + + if (arm->config.simulate) + return; + + /* set speed and pos of shoulder */ + quadramp_set_1st_order_vars(&csb->qr, + st->shoulder_speed, + st->shoulder_speed); + cs_set_consign(&csb->cs, st->shoulder_angle_steps); + + /* set speed and position of elbow */ + ax12_user_write_int(&gen.ax12, arm->config.elbow_ax12, + AA_MOVING_SPEED_L, st->elbow_speed); + ax12_user_write_int(&gen.ax12, arm->config.elbow_ax12, + AA_GOAL_POSITION_L, st->elbow_angle_steps); +} + +/* return true if one of the mask condition is true */ +uint8_t arm_test_traj_end(struct arm *arm, uint8_t mask) +{ + if ((mask & ARM_TRAJ_END) && (arm->status.state & ARM_FLAG_IN_WINDOW)) + return ARM_TRAJ_END; + + if ((mask & ARM_TRAJ_NEAR) && (arm->status.state & ARM_FLAG_LAST_STEP)) + return ARM_TRAJ_NEAR; + + if ((mask & ARM_TRAJ_TIMEOUT) && (arm->status.state & ARM_FLAG_TIMEOUT)) + return ARM_TRAJ_TIMEOUT; + + if ((mask & ARM_TRAJ_ERROR) && (arm->status.state & ARM_FLAG_ERROR)) + return ARM_TRAJ_ERROR; + + return 0; +} + +uint8_t arm_wait_traj_end(struct arm *arm, uint8_t mask) +{ + uint8_t ret; + while(1) { + ret = arm_test_traj_end(arm, mask); + if (ret) + return ret; + } +} + +/* return true if one of the mask condition is true */ +uint8_t arm_in_window(struct arm *arm, uint8_t *status) +{ + int8_t err; +/* uint16_t spd; */ + int16_t pos; + int32_t cs_err; + + *status = 0; + + if (arm->config.simulate) + return 1; + + /* shoulder, just check position */ + cs_err = cs_get_error(&arm->config.csb->cs); + if (ABS(cs_err) > ARM_SHOULDER_WINDOW_POS) + *status |= SHOULDER_NOT_IN_WIN; + +#if 0 + /* check elbow speed */ + err = ax12_user_read_int(&gen.ax12, arm->config.elbow_ax12, + AA_PRESENT_SPEED_L, &spd); + if (err) + goto fail; + if (spd > ARM_ELBOW_WINDOW_SPEED) + return 0; + + /* check wrist speed */ + err = ax12_user_read_int(&gen.ax12, arm->config.wrist_ax12, + AA_PRESENT_SPEED_L, &spd); + if (err) + goto fail; + if (spd > ARM_WRIST_WINDOW_SPEED) + return 0; +#endif + /* check elbow pos */ + err = ax12_user_read_int(&gen.ax12, arm->config.elbow_ax12, + AA_PRESENT_POSITION_L, (uint16_t *)&pos); + if (err) + goto fail; + if (ABS(arm->status.elbow_angle_steps - pos) > ARM_ELBOW_WINDOW_POS) + *status |= ELBOW_NOT_IN_WIN; + + /* check wrist pos */ + err = ax12_user_read_int(&gen.ax12, arm->config.wrist_ax12, + AA_PRESENT_POSITION_L, (uint16_t *)&pos); + if (err) + goto fail; + if (ABS(arm->status.wrist_angle_steps - pos) > ARM_WRIST_WINDOW_POS) + *status |= WRIST_NOT_IN_WIN; + + if (*status) + return 0; + + ARM_NOTICE("arm is in window (%ld us after reach pos)", + time_get_us2() - arm->status.pos_reached_time); + return 1; /* ok, we are in window */ + + fail: + return 0; +} + +/* process wrist pos and apply it. it's done only once. */ +static int8_t arm_set_wrist(struct arm *arm) +{ + int8_t err; + int32_t as_deg, ae_deg, aw_deg; + uint16_t wrist_out_u16; + double wrist_out, as_rad, ae_rad; + int16_t pos; + uint32_t diff_time; + + /* calculate the destination angle of arm in radian */ + err = cart2angle(arm->req.h_mm, arm->req.d_mm, + &as_rad, &ae_rad); + if (err) + return -1; + + /* calc angle destination */ + as_deg = DEG(as_rad); + ae_deg = DEG(ae_rad); + ARM_DEBUG("as_dest_deg=%d ae_dest_deg=%d", as_deg, ae_deg); + aw_deg = as_deg + ae_deg - arm->req.w_deg; + arm->config.wrist_angle_deg2robot(aw_deg, &wrist_out); + wrist_out_u16 = wrist_out; + + ARM_DEBUG("set wrist to %ld degrees (%d steps)", aw_deg, + wrist_out_u16); + + /* process the theorical reach time for the wrist */ + if (arm->config.simulate) { + pos = arm->status.wrist_angle_steps; + } + else { + err = ax12_user_read_int(&gen.ax12, arm->config.wrist_ax12, + AA_PRESENT_POSITION_L, (uint16_t *)&pos); + if (err) + pos = arm->status.wrist_angle_steps; + } + /* 600 is the number of steps/s */ + diff_time = (ABS((int16_t)wrist_out_u16 - pos) * 1000000L) / 600; + arm->status.wrist_reach_time = arm->status.start_time + diff_time; + ARM_DEBUG("wrist reach time is %ld (diff=%ld)", + arm->status.wrist_reach_time, diff_time); + + /* update current position to destination */ + arm->status.wrist_angle_steps = wrist_out_u16; + + if (arm->config.simulate) + return 0; + + /* send it to ax12 */ + ax12_user_write_int(&gen.ax12, arm->config.wrist_ax12, + AA_GOAL_POSITION_L, wrist_out_u16); + return 0; +} + +/* event callback */ +static void arm_do_xy_cb(struct arm *arm) +{ + uint8_t win_status; + + arm->status.event = -1; + + /* if consign haven't reach destination */ + if ((arm->status.state & ARM_FLAG_LAST_STEP) == 0) { + if (arm_do_step(arm)) + arm->status.state |= ARM_FLAG_ERROR; + + /* it's the first call for the traj */ + if (arm->status.state == ARM_STATE_INIT) { + arm->status.state |= ARM_FLAG_MOVING; + if (arm_set_wrist(arm)) + arm->status.state |= ARM_FLAG_ERROR; + } + + /* we have more steps to do */ + if (arm->status.next_update_time == 0) { + arm->status.state &= ~ARM_FLAG_MOVING; + arm->status.state |= ARM_FLAG_LAST_STEP; + arm->status.pos_reached_time = time_get_us2(); + } + arm_apply(arm); + } + /* last step is reached, we can check that arm is in window */ + else if ((arm->status.state & ARM_FLAG_IN_WINDOW) == 0) { + if (arm_in_window(arm, &win_status)) + arm->status.state |= ARM_FLAG_IN_WINDOW; + + /* check for window arm timeout */ + else { + microseconds t; + int32_t diff1, diff2; + t = time_get_us2(); + diff1 = t - arm->status.pos_reached_time; + diff2 = t - arm->status.wrist_reach_time; + if (diff1 > ARM_WINDOW_TIMEOUT && + diff2 > ARM_WINDOW_TIMEOUT) { + ARM_NOTICE("win timeout at %ld win_status=%x", + t, win_status); + arm->status.state |= ARM_FLAG_TIMEOUT; + } + } + } + + /* check for global arm timeout */ + if ((time_get_us2() - arm->status.start_time) > ARM_GLOBAL_TIMEOUT) { + ARM_NOTICE("global timeout at %ld", time_get_us2()); + arm->status.state |= ARM_FLAG_TIMEOUT; + } + + /* reload event if needed */ + if ((arm->status.state & ARM_FLAG_FINISHED) == ARM_FLAG_FINISHED) { + ARM_NOTICE("arm traj finished"); + return; /* no more event, position reached */ + } + if (arm->status.state & (ARM_FLAG_ERROR|ARM_FLAG_TIMEOUT)) { + ARM_NOTICE("error or timeout"); + return; /* no more event */ + } + else if (arm->status.state & ARM_FLAG_LAST_STEP) { + /* theorical position is reached, but reload an event + * for position survey (window), every 25ms */ + arm_schedule_event(arm, ARM_SURVEY_PERIOD); + } + else { + /* reload event for next position step */ + arm_schedule_event(arm, arm->status.next_update_time); + } +} + +/* schedule a single event for this arm */ +static void arm_schedule_event(struct arm *arm, uint32_t time) +{ + uint8_t flags; + int8_t ret; + + arm_delete_event(arm); + if (time < SCHEDULER_UNIT) + time = SCHEDULER_UNIT; + IRQ_LOCK(flags); + ret = scheduler_add_event(SCHEDULER_SINGLE, + (void *)arm_do_xy_cb, + arm, time/SCHEDULER_UNIT, ARM_PRIO); + if (ret == -1) { + IRQ_UNLOCK(flags); + ARM_ERROR("Cannot load arm event"); + return; + } + arm->status.event = ret; + IRQ_UNLOCK(flags); +} + +int8_t arm_do_xy(struct arm *arm, int16_t d_mm, int16_t h_mm, int16_t w_deg) +{ + ARM_NOTICE("arm_do_xy: d_mm=%d h_mm=%d w_deg=%d", d_mm, h_mm, w_deg); + + /* remove previous event if any */ + arm_delete_event(arm); + + /* init mandatory params */ + arm->req.d_mm = d_mm; + arm->req.h_mm = h_mm; + arm->req.w_deg = w_deg; + arm->status.start_time = time_get_us2(); + arm->status.state = ARM_STATE_INIT; + + /* all the job will be done asynchronously now */ + arm_schedule_event(arm, 0); + return 0; +} + +void arm_dump(struct arm *arm) +{ + printf_P(PSTR("config: simulate=%d\r\n"), + arm->config.simulate); + printf_P(PSTR("req: d_mm=%ld h_mm=%ld w_deg=%ld\r\n"), + arm->req.d_mm, arm->req.h_mm, arm->req.w_deg); + printf_P(PSTR("status: ")); + if (arm->status.state == ARM_STATE_INIT) + printf_P(PSTR("ARM_STATE_INIT ")); + if (arm->status.state & ARM_FLAG_MOVING) + printf_P(PSTR("ARM_FLAG_MOVING ")); + if (arm->status.state & ARM_FLAG_LAST_STEP) + printf_P(PSTR("ARM_FLAG_LAST_STEP ")); + if (arm->status.state & ARM_FLAG_IN_WINDOW) + printf_P(PSTR("ARM_FLAG_IN_WINDOW ")); + if (arm->status.state & ARM_FLAG_ERROR) + printf_P(PSTR("ARM_FLAG_ERROR ")); + if (arm->status.state & ARM_FLAG_TIMEOUT) + printf_P(PSTR("ARM_FLAG_TIMEOUT ")); + printf_P(PSTR("\r\n")); + + printf_P(PSTR(" d_mm=%ld h_mm=%ld goal_w_steps=%d\r\n"), + arm->status.d_mm, arm->status.h_mm, arm->status.wrist_angle_steps); + printf_P(PSTR(" cur_shl_steps=%ld cur_elb_steps=%ld\r\n"), + arm->status.shoulder_angle_steps, arm->status.elbow_angle_steps); + printf_P(PSTR(" cur_shl_rad=%f cur_elb_rad=%f\r\n"), + arm->status.shoulder_angle_rad, arm->status.elbow_angle_rad); + printf_P(PSTR(" cur_shl_deg=%f cur_elb_deg=%f\r\n"), + DEG(arm->status.shoulder_angle_rad), DEG(arm->status.elbow_angle_rad)); + printf_P(PSTR(" event=%d next_update_time=%ld\r\n"), + arm->status.event, arm->status.next_update_time); + printf_P(PSTR(" start_time=%ld pos_reached_time=%ld wrist_reach_time=%ld\r\n"), + arm->status.start_time, arm->status.pos_reached_time, + arm->status.wrist_reach_time); +} + +#define CALIB_ANGLE (RAD(-93.)) + +void arm_calibrate(void) +{ + double shoulder, elbow; + + pwm_ng_set(LEFT_ARM_PWM, 500); + pwm_ng_set(RIGHT_ARM_PWM, -500); + wait_ms(200); + + pwm_ng_set(LEFT_ARM_PWM, 300); + pwm_ng_set(RIGHT_ARM_PWM, -300); + wait_ms(700); + + printf_P(PSTR("Init arm, please wait...")); + ax12_user_write_int(&gen.ax12, AX12_BROADCAST_ID, AA_TORQUE_ENABLE, 0x1); + ax12_user_write_int(&gen.ax12, AX12_BROADCAST_ID, AA_ALARM_SHUTDOWN, 0x04); + + angle_rad2robot_r(0, CALIB_ANGLE, &shoulder, &elbow); + ax12_user_write_int(&gen.ax12, R_ELBOW_AX12, AA_GOAL_POSITION_L, elbow); + ax12_user_write_int(&gen.ax12, R_WRIST_AX12, AA_GOAL_POSITION_L, 628); + + angle_rad2robot_l(0, CALIB_ANGLE, &shoulder, &elbow); + ax12_user_write_int(&gen.ax12, L_ELBOW_AX12, AA_GOAL_POSITION_L, elbow); + ax12_user_write_int(&gen.ax12, L_WRIST_AX12, AA_GOAL_POSITION_L, 394); + pwm_ng_set(LEFT_ARM_PWM, -100); + pwm_ng_set(RIGHT_ARM_PWM, 100); + + wait_ms(2000); + + cs_set_consign(&mechboard.left_arm.cs, 0); + cs_set_consign(&mechboard.right_arm.cs, 0); + encoders_spi_set_value(LEFT_ARM_ENCODER, 0); + encoders_spi_set_value(RIGHT_ARM_ENCODER, 0); + + printf_P(PSTR("ok\r\n")); +} + +/* init arm config */ +void arm_init(void) +{ + uint32_t shoulder_robot; + uint16_t elbow_robot, wrist_robot; + double shoulder_rad, elbow_rad; + int32_t h, d; + uint8_t err = 0; + + memset(&left_arm.status, 0, sizeof(left_arm.status)); + memset(&right_arm.status, 0, sizeof(right_arm.status)); + left_arm.status.event = -1; + right_arm.status.event = -1; + + arm_calibrate(); + + /* set des slopes XXX */ + + /* set maximum moving speeds */ + err |= ax12_user_write_int(&gen.ax12, L_ELBOW_AX12, AA_MOVING_SPEED_L, 0x3ff); + err |= ax12_user_write_int(&gen.ax12, L_WRIST_AX12, AA_MOVING_SPEED_L, 0x3ff); + err |= ax12_user_write_int(&gen.ax12, R_ELBOW_AX12, AA_MOVING_SPEED_L, 0x3ff); + err |= ax12_user_write_int(&gen.ax12, R_WRIST_AX12, AA_MOVING_SPEED_L, 0x3ff); + + /* left arm init */ + shoulder_robot = encoders_spi_get_value(LEFT_ARM_ENCODER); + err |= ax12_user_read_int(&gen.ax12, L_ELBOW_AX12, AA_PRESENT_POSITION_L, &elbow_robot); + err |= ax12_user_read_int(&gen.ax12, L_WRIST_AX12, AA_PRESENT_POSITION_L, &wrist_robot); + + angle_robot2rad_l(shoulder_robot, elbow_robot, + &shoulder_rad, &elbow_rad); + angle2cart(shoulder_rad, elbow_rad, &h, &d); + printf_P(PSTR("left arm: h:%ld d:%ld w:%d\r\n"), h, d, wrist_robot); + left_arm.status.h_mm = h; + left_arm.status.d_mm = d; + left_arm.status.wrist_angle_steps = wrist_robot; + left_arm.status.state = ARM_FLAG_FINISHED; + left_arm.config.csb = &mechboard.left_arm; + + /* left arm init */ + shoulder_robot = encoders_spi_get_value(RIGHT_ARM_ENCODER); + err |= ax12_user_read_int(&gen.ax12, R_ELBOW_AX12, AA_PRESENT_POSITION_L, &elbow_robot); + err |= ax12_user_read_int(&gen.ax12, R_WRIST_AX12, AA_PRESENT_POSITION_L, &wrist_robot); + + angle_robot2rad_r(shoulder_robot, elbow_robot, + &shoulder_rad, &elbow_rad); + angle2cart(shoulder_rad, elbow_rad, &h, &d); + printf_P(PSTR("right arm: h:%ld d:%ld w:%d\r\n"), h, d, wrist_robot); + right_arm.status.h_mm = h; + right_arm.status.d_mm = d; + right_arm.status.wrist_angle_steps = wrist_robot; + right_arm.status.state = ARM_FLAG_FINISHED; + right_arm.config.csb = &mechboard.right_arm; + + if (err) + ARM_ERROR("ARM INIT ERROR"); +} diff --git a/projects/microb2009/mechboard/arm_xy.h b/projects/microb2009/mechboard/arm_xy.h new file mode 100644 index 0000000..3b1407f --- /dev/null +++ b/projects/microb2009/mechboard/arm_xy.h @@ -0,0 +1,123 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: arm_xy.h,v 1.4 2009-11-08 17:25:00 zer0 Exp $ + * + * Fabrice DESCLAUX <serpilliere@droids-corp.org> + * Olivier MATZ <zer0@droids-corp.org> + */ + +/* all static configuration for an arm */ +struct arm_config { + void (*wrist_angle_deg2robot)(double wrist_edg, + double *wrist_out); + + void (*angle_rad2robot)(double shoulder_deg, double elbow_deg, + double *shoulder_out, double *elbow_out); + + void (*angle_robot2rad)(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad); + + /* ax12 identifiers */ + int8_t elbow_ax12; + int8_t wrist_ax12; + + /* related control system */ + struct cs_block *csb; + + /* if true, don't apply to ax12 / cs */ + uint8_t simulate; +}; + +/* request for a final position, in mm */ +struct arm_request { + int32_t h_mm; + int32_t d_mm; + int32_t w_deg; +}; + +/* returned by arm_test_traj_end() */ +#define ARM_TRAJ_END 0x01 +#define ARM_TRAJ_NEAR 0x02 +#define ARM_TRAJ_TIMEOUT 0x04 +#define ARM_TRAJ_ERROR 0x08 + +#define ARM_TRAJ_ALL (ARM_TRAJ_END|ARM_TRAJ_TIMEOUT|ARM_TRAJ_ERROR) +#define ARM_TRAJ_ALL_NEAR (ARM_TRAJ_END|ARM_TRAJ_NEAR|ARM_TRAJ_TIMEOUT|ARM_TRAJ_ERROR) +#define ARM_TRAJ_END_NEAR (ARM_TRAJ_END|ARM_TRAJ_NEAR) + +#define ARM_STATE_INIT 0 +#define ARM_FLAG_MOVING 0x01 /* arm is currently moving */ +#define ARM_FLAG_LAST_STEP 0x02 /* no more step is needed */ +#define ARM_FLAG_IN_WINDOW 0x04 /* arm speed and pos are ok */ +#define ARM_FLAG_TIMEOUT 0x08 /* too much time too reach pos */ +#define ARM_FLAG_ERROR 0x10 /* error */ +#define ARM_FLAG_FINISHED (ARM_FLAG_LAST_STEP | ARM_FLAG_IN_WINDOW) + +/* Describes the current position of the arm. Mainly filled by + * arm_do_step(), arm_set_wrist(), arm_do_xy_cb(), ... */ +struct arm_status { + /* current position */ + int32_t h_mm; + int32_t d_mm; + + /* wrist goal position (set once at init) */ + int16_t wrist_angle_steps; + + /* current angles in steps */ + int32_t elbow_angle_steps; + int32_t shoulder_angle_steps; + + /* current angles in radian */ + double elbow_angle_rad; + double shoulder_angle_rad; + + /* time before next update */ + uint32_t next_update_time; + + /* what speed to be applied, in specific speed unit */ + uint32_t shoulder_speed; + uint32_t elbow_speed; + + volatile int8_t state; /* see list of flags above */ + int8_t event; /* scheduler event, -1 if not running */ + + microseconds start_time; /* when we started that command */ + microseconds wrist_reach_time; /* when the wrist should reach dest */ + microseconds pos_reached_time; /* when last step is sent */ +}; + +struct arm { + struct arm_config config; + struct arm_status status; + struct arm_request req; +}; + +extern struct arm left_arm; +extern struct arm right_arm; + +uint8_t arm_test_traj_end(struct arm *arm, uint8_t mask); +uint8_t arm_wait_traj_end(struct arm *arm, uint8_t mask); + +/* do a specific move to distance, height. This function _must_ be + * called from a context with a prio < ARM_PRIO to avoid any race + * condition. */ +int8_t arm_do_xy(struct arm *arm, int16_t d_mm, int16_t h_mm, int16_t w_deg); + +void arm_dump(struct arm *arm); +void arm_calibrate(void); +void arm_init(void); diff --git a/projects/microb2009/mechboard/ax12_config.h b/projects/microb2009/mechboard/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/projects/microb2009/mechboard/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/projects/microb2009/mechboard/ax12_user.c b/projects/microb2009/mechboard/ax12_user.c new file mode 100644 index 0000000..9000bbd --- /dev/null +++ b/projects/microb2009/mechboard/ax12_user.c @@ -0,0 +1,305 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12_user.c,v 1.4 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/list.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <i2c.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "ax12_user.h" + +#define AX12_ERROR(args...) ERROR(E_USER_AX12, args) +#define AX12_NOTICE(args...) NOTICE(E_USER_AX12, args) +#define AX12_MAX_TRIES 3 + +/* + * Cmdline interface for AX12. Use the PC to command a daisy-chain of + * AX12 actuators with a nice command line interface. + * + * The circuit should be as following: + * + * |----------| + * | uart3|------->--- PC (baudrate=57600) + * | |-------<--- + * | atmega128| + * | | + * | uart0|---->---+-- AX12 (baudrate 115200) + * | |----<---| + * |----------| + * + * Note that RX and TX pins of UART1 are connected together to provide + * a half-duplex UART emulation. + * + */ + +#define UCSRxB UCSR0B +#define AX12_TIMEOUT 15000L /* in us */ + +static uint32_t ax12_stats_ops = 0; /* total ops */ +static uint32_t ax12_stats_fails = 0; /* number of fails */ +static uint32_t ax12_stats_drops = 0; /* number of drops (3 fails) */ +static uint32_t ax12_dropped_logs = 0; /* error messages that were not displayed */ +static microseconds t_prev_msg = 0; + +/********************************* AX12 commands */ + +/* + * We use synchronous access (not interrupt driven) to the hardware + * UART, because we have to be sure that the transmission/reception is + * really finished when we return from the functions. + * + * We don't use the CM-5 circuit as described in the AX12 + * documentation, we simply connect TX and RX and use TXEN + RXEN + + * DDR to manage the port directions. + */ + +static volatile uint8_t ax12_state = AX12_STATE_READ; +extern volatile struct cirbuf g_tx_fifo[]; /* uart fifo */ +static volatile uint8_t ax12_nsent = 0; + +/* Called by ax12 module to send a character on serial line. Count the + * number of transmitted bytes. It will be used in ax12_recv_char() to + * drop the bytes that we transmitted. */ +static int8_t ax12_send_char(uint8_t c) +{ + uart_send(UART_AX12_NUM, c); + ax12_nsent++; + return 0; +} + +/* for atmega256 */ +#ifndef TXEN +#define TXEN TXEN0 +#endif + +/* called by uart module when the character has been written in + * UDR. It does not mean that the byte is physically transmitted. */ +static void ax12_send_callback(__attribute__((unused)) char c) +{ + if (ax12_state == AX12_STATE_READ) { + /* disable TX when last byte is pushed. */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[UART_AX12_NUM])) + UCSRxB &= ~(1<<TXEN); + } +} + +/* Called by ax12 module when we want to receive a char. Note that we + * also receive the bytes we sent ! So we need to drop them. */ +static int16_t ax12_recv_char(void) +{ + microseconds t = time_get_us2(); + int c; + while (1) { + c = uart_recv_nowait(UART_AX12_NUM); + if (c != -1) { + if (ax12_nsent == 0) + return c; + ax12_nsent --; + } + + /* 5 ms timeout */ + if ((time_get_us2() - t) > AX12_TIMEOUT) + return -1; + } + return c; +} + +/* called by ax12 module when we want to switch serial line. As we + * work in interruption mode, this function can be called to switch + * back in read mode even if the bytes are not really transmitted on + * the line. That's why in this case we do nothing, we will fall back + * in read mode in any case when xmit is finished -- see in + * ax12_send_callback() -- */ +static void ax12_switch_uart(uint8_t state) +{ + uint8_t flags; + + if (state == AX12_STATE_WRITE) { + IRQ_LOCK(flags); + ax12_nsent=0; + while (uart_recv_nowait(UART_AX12_NUM) != -1); + UCSRxB |= (1<<TXEN); + ax12_state = AX12_STATE_WRITE; + IRQ_UNLOCK(flags); + } + else { + IRQ_LOCK(flags); + if (CIRBUF_IS_EMPTY(&g_tx_fifo[UART_AX12_NUM])) + UCSRxB &= ~(1<<TXEN); + ax12_state = AX12_STATE_READ; + IRQ_UNLOCK(flags); + } +} + +/* ----- */ + +/* log rate limit */ +static void ax12_print_error(uint8_t err, uint16_t line) +{ + microseconds t2; + + /* no more than 1 log per sec */ + t2 = time_get_us2(); + + if (t2 - t_prev_msg < 1000000L) { + ax12_dropped_logs++; + return; + } + AX12_ERROR("AX12 error %x at line %d (%ld messages dropped)", + err, line, ax12_dropped_logs); + ax12_dropped_logs = 0; + t_prev_msg = t2; +} + +uint8_t __ax12_user_write_byte(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint8_t data, uint16_t line) +{ + uint8_t err, i; + + ax12_stats_ops++; + + for (i=0; i<AX12_MAX_TRIES ; i++) { + err = AX12_write_byte(ax12, id, address, data); + if (err == 0) + break; + wait_ms(2); /* BAD HACK XXX */ + ax12_stats_fails++; + } + if (err == 0) + return 0; + + ax12_print_error(err, line); + ax12_stats_drops++; + return err; +} + +uint8_t __ax12_user_write_int(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t data, uint16_t line) +{ + uint8_t err, i; + + ax12_stats_ops++; + + for (i=0; i<AX12_MAX_TRIES ; i++) { + err = AX12_write_int(ax12, id, address, data); + if (err == 0) + break; + wait_ms(2); /* BAD HACK XXX */ + ax12_stats_fails++; + } + if (err == 0) + return 0; + + ax12_print_error(err, line); + ax12_stats_drops++; + return err; +} + +uint8_t __ax12_user_read_byte(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint8_t *val, uint16_t line) +{ + uint8_t err, i; + + ax12_stats_ops++; + + for (i=0; i<AX12_MAX_TRIES ; i++) { + err = AX12_read_byte(ax12, id, address, val); + if (err == 0) + break; + wait_ms(2); /* BAD HACK XXX */ + ax12_stats_fails++; + } + if (err == 0) { + /* XXX hack for broadcast */ + if (id == AX12_BROADCAST_ID) + wait_ms(1); + return 0; + } + + ax12_print_error(err, line); + ax12_stats_drops++; + return err; +} + +uint8_t __ax12_user_read_int(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t *val, uint16_t line) +{ + uint8_t err, i; + + ax12_stats_ops++; + + for (i=0; i<AX12_MAX_TRIES ; i++) { + err = AX12_read_int(ax12, id, address, val); + if (err == 0) + break; + wait_ms(2); /* BAD HACK XXX */ + ax12_stats_fails++; + } + if (err == 0) { + /* XXX hack for broadcast */ + if (id == AX12_BROADCAST_ID) + wait_ms(1); + return 0; + } + + ax12_print_error(err, line); + ax12_stats_drops++; + return err; +} + +void ax12_dump_stats(void) +{ + printf_P(PSTR("AX12 stats:\r\n")); + printf_P(PSTR(" total ops: %ld\r\n"), ax12_stats_ops); + printf_P(PSTR(" total fails: %ld\r\n"), ax12_stats_fails); + printf_P(PSTR(" total drops: %ld\r\n"), ax12_stats_drops); + printf_P(PSTR(" logs dropped since last message: %ld\r\n"), ax12_dropped_logs); +} + +void ax12_user_init(void) +{ + /* AX12 */ + AX12_init(&gen.ax12); + AX12_set_hardware_send(&gen.ax12, ax12_send_char); + AX12_set_hardware_recv(&gen.ax12, ax12_recv_char); + AX12_set_hardware_switch(&gen.ax12, ax12_switch_uart); + uart_register_tx_event(UART_AX12_NUM, ax12_send_callback); + t_prev_msg = time_get_us2(); +} diff --git a/projects/microb2009/mechboard/ax12_user.h b/projects/microb2009/mechboard/ax12_user.h new file mode 100644 index 0000000..bbd7283 --- /dev/null +++ b/projects/microb2009/mechboard/ax12_user.h @@ -0,0 +1,76 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12_user.h,v 1.3 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +/* This is the ax12 user interface. It initializes the aversive AX12 + * module so that it works in background, using interrupt driver uart. + * + * Be carreful, a call to AX12 module is synchronous and uses + * interruptions, so interrupts must be enabled. On the other side, a + * call _must not_ interrupt another one. That's why all calls to the + * module are done either in init() functions or in a scheduler event + * with prio=ARM_PRIO. + */ + +/* XXX do a safe_ax12() function that will retry once or twice if we + * see some problems. */ + +#define UART_AX12_NUM 0 + +void ax12_user_init(void); + +void ax12_dump_stats(void); + +#define ax12_user_write_byte(ax12, id, addr, data) \ + __ax12_user_write_byte(ax12, id, addr, data, __LINE__) + +#define ax12_user_write_int(ax12, id, addr, data) \ + __ax12_user_write_int(ax12, id, addr, data, __LINE__) + +#define ax12_user_read_byte(ax12, id, addr, data) \ + __ax12_user_read_byte(ax12, id, addr, data, __LINE__) + +#define ax12_user_read_int(ax12, id, addr, data) \ + __ax12_user_read_int(ax12, id, addr, data, __LINE__) + +/** @brief Write byte in AX-12 memory + * @return Error code from AX-12 (0 means okay) */ +uint8_t __ax12_user_write_byte(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint8_t data, uint16_t line); + +/** @brief Write integer (2 bytes) in AX-12 memory + * @return Error code from AX-12 (0 means okay) + * + * address : data low + * address+1 : data high + */ +uint8_t __ax12_user_write_int(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t data, uint16_t line); + +/** @brief Read byte from AX-12 memory + * @return Error code from AX-12 (0 means okay) */ +uint8_t __ax12_user_read_byte(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint8_t *val, uint16_t line); + +/** @brief Write integer (2 bytes) from AX-12 memory + * @return Error code from AX-12 (0 means okay) */ +uint8_t __ax12_user_read_int(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t *val, uint16_t line); diff --git a/projects/microb2009/mechboard/cmdline.c b/projects/microb2009/mechboard/cmdline.c new file mode 100644 index 0000000..f784b35 --- /dev/null +++ b/projects/microb2009/mechboard/cmdline.c @@ -0,0 +1,149 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cmdline.c,v 1.3 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <parse.h> +#include <rdline.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include "main.h" +#include "cmdline.h" + + +/******** See in commands.c for the list of commands. */ +extern parse_pgm_ctx_t main_ctx[]; + +static void write_char(char c) +{ + uart_send(CMDLINE_UART, c); +} + +static void +valid_buffer(const char *buf, __attribute__((unused)) uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char *buf, char *dstbuf, uint8_t dstsize, + int16_t *state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + + +/* sending "pop" on cmdline uart resets the robot */ +void emergency(char c) +{ + static uint8_t i = 0; + + if ((i == 0 && c == 'p') || + (i == 1 && c == 'o') || + (i == 2 && c == 'p')) + i++; + else if ( !(i == 1 && c == 'p') ) + i = 0; + if (i == 3) + reset(); +} + +/* log function, add a command to configure + * it dynamically */ +void mylog(struct error * e, ...) +{ + va_list ap; + u16 stream_flags = stdout->flags; + uint8_t i; + time_h tv; + + if (e->severity > ERROR_SEVERITY_ERROR) { + if (gen.log_level < e->severity) + return; + + for (i=0; i<NB_LOGS+1; i++) + if (gen.logs[i] == e->err_num) + break; + if (i == NB_LOGS+1) + return; + } + + va_start(ap, e); + tv = time_get_time(); + printf_P(PSTR("%ld.%.3ld: "), tv.s, (tv.us/1000UL)); + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR("\r\n")); + va_end(ap); + stdout->flags = stream_flags; +} + +int cmdline_interact(void) +{ + const char *history, *buffer; + int8_t ret, same = 0; + int16_t c; + + rdline_init(&gen.rdl, write_char, valid_buffer, complete_buffer); + snprintf(gen.prompt, sizeof(gen.prompt), "mechboard > "); + rdline_newline(&gen.rdl, gen.prompt); + + while (1) { + c = uart_recv_nowait(CMDLINE_UART); + if (c == -1) + continue; + ret = rdline_char_in(&gen.rdl, c); + if (ret != 2 && ret != 0) { + buffer = rdline_get_buffer(&gen.rdl); + history = rdline_get_history_item(&gen.rdl, 0); + if (history) { + same = !memcmp(buffer, history, strlen(history)) && + buffer[strlen(history)] == '\n'; + } + else + same = 0; + if (strlen(buffer) > 1 && !same) + rdline_add_history(&gen.rdl, buffer); + rdline_newline(&gen.rdl, gen.prompt); + } + } + + return 0; +} diff --git a/projects/microb2009/mechboard/cmdline.h b/projects/microb2009/mechboard/cmdline.h new file mode 100644 index 0000000..e5bb569 --- /dev/null +++ b/projects/microb2009/mechboard/cmdline.h @@ -0,0 +1,40 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cmdline.h,v 1.4 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#define CMDLINE_UART 1 + +/* uart rx callback for reset() */ +void emergency(char c); + +/* log function */ +void mylog(struct error * e, ...); + +/* launch cmdline */ +int cmdline_interact(void); + +static inline uint8_t cmdline_keypressed(void) { + return (uart_recv_nowait(CMDLINE_UART) != -1); +} + +static inline int16_t cmdline_getchar(void) { + return uart_recv_nowait(CMDLINE_UART); +} diff --git a/projects/microb2009/mechboard/commands.c b/projects/microb2009/mechboard/commands.c new file mode 100644 index 0000000..1c2186d --- /dev/null +++ b/projects/microb2009/mechboard/commands.c @@ -0,0 +1,150 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdlib.h> +#include <aversive/pgmspace.h> +#include <parse.h> + +/* commands_gen.c */ +extern parse_pgm_inst_t cmd_reset; +extern parse_pgm_inst_t cmd_bootloader; +extern parse_pgm_inst_t cmd_encoders; +extern parse_pgm_inst_t cmd_pwm; +extern parse_pgm_inst_t cmd_adc; +extern parse_pgm_inst_t cmd_sensor; +extern parse_pgm_inst_t cmd_log; +extern parse_pgm_inst_t cmd_log_show; +extern parse_pgm_inst_t cmd_log_type; +extern parse_pgm_inst_t cmd_stack_space; +extern parse_pgm_inst_t cmd_scheduler; + +/* commands_ax12.c */ +extern parse_pgm_inst_t cmd_baudrate; +extern parse_pgm_inst_t cmd_uint16_read; +extern parse_pgm_inst_t cmd_uint16_write; +extern parse_pgm_inst_t cmd_uint8_read; +extern parse_pgm_inst_t cmd_uint8_write; +extern parse_pgm_inst_t cmd_ax12_stress; +extern parse_pgm_inst_t cmd_ax12_dump_stats; + +/* commands_cs.c */ +extern parse_pgm_inst_t cmd_gain; +extern parse_pgm_inst_t cmd_gain_show; +extern parse_pgm_inst_t cmd_speed; +extern parse_pgm_inst_t cmd_speed_show; +extern parse_pgm_inst_t cmd_derivate_filter; +extern parse_pgm_inst_t cmd_derivate_filter_show; +extern parse_pgm_inst_t cmd_consign; +extern parse_pgm_inst_t cmd_maximum; +extern parse_pgm_inst_t cmd_maximum_show; +extern parse_pgm_inst_t cmd_quadramp; +extern parse_pgm_inst_t cmd_quadramp_show; +extern parse_pgm_inst_t cmd_cs_status; +extern parse_pgm_inst_t cmd_blocking_i; +extern parse_pgm_inst_t cmd_blocking_i_show; + +/* commands_mechboard.c */ +extern parse_pgm_inst_t cmd_event; +extern parse_pgm_inst_t cmd_color; +extern parse_pgm_inst_t cmd_arm_show; +extern parse_pgm_inst_t cmd_arm_goto; +extern parse_pgm_inst_t cmd_arm_goto_fixed; +extern parse_pgm_inst_t cmd_arm_simulate; +extern parse_pgm_inst_t cmd_finger; +extern parse_pgm_inst_t cmd_pump; +extern parse_pgm_inst_t cmd_state1; +extern parse_pgm_inst_t cmd_state2; +extern parse_pgm_inst_t cmd_state3; +extern parse_pgm_inst_t cmd_state4; +extern parse_pgm_inst_t cmd_state5; +extern parse_pgm_inst_t cmd_state_debug; +extern parse_pgm_inst_t cmd_state_machine; +extern parse_pgm_inst_t cmd_servo_lintel; +extern parse_pgm_inst_t cmd_pump_current; +extern parse_pgm_inst_t cmd_manivelle; +extern parse_pgm_inst_t cmd_test; + + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + + /* commands_gen.c */ + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_bootloader, + (parse_pgm_inst_t *)&cmd_encoders, + (parse_pgm_inst_t *)&cmd_pwm, + (parse_pgm_inst_t *)&cmd_adc, + (parse_pgm_inst_t *)&cmd_sensor, + (parse_pgm_inst_t *)&cmd_log, + (parse_pgm_inst_t *)&cmd_log_show, + (parse_pgm_inst_t *)&cmd_log_type, + (parse_pgm_inst_t *)&cmd_stack_space, + (parse_pgm_inst_t *)&cmd_scheduler, + + /* commands_ax12.c */ + (parse_pgm_inst_t *)&cmd_baudrate, + (parse_pgm_inst_t *)&cmd_uint16_read, + (parse_pgm_inst_t *)&cmd_uint16_write, + (parse_pgm_inst_t *)&cmd_uint8_read, + (parse_pgm_inst_t *)&cmd_uint8_write, + (parse_pgm_inst_t *)&cmd_ax12_stress, + (parse_pgm_inst_t *)&cmd_ax12_dump_stats, + + /* commands_cs.c */ + (parse_pgm_inst_t *)&cmd_gain, + (parse_pgm_inst_t *)&cmd_gain_show, + (parse_pgm_inst_t *)&cmd_speed, + (parse_pgm_inst_t *)&cmd_speed_show, + (parse_pgm_inst_t *)&cmd_consign, + (parse_pgm_inst_t *)&cmd_derivate_filter, + (parse_pgm_inst_t *)&cmd_derivate_filter_show, + (parse_pgm_inst_t *)&cmd_maximum, + (parse_pgm_inst_t *)&cmd_maximum_show, + (parse_pgm_inst_t *)&cmd_quadramp, + (parse_pgm_inst_t *)&cmd_quadramp_show, + (parse_pgm_inst_t *)&cmd_cs_status, + (parse_pgm_inst_t *)&cmd_blocking_i, + (parse_pgm_inst_t *)&cmd_blocking_i_show, + + /* commands_mechboard.c */ + (parse_pgm_inst_t *)&cmd_event, + (parse_pgm_inst_t *)&cmd_color, + (parse_pgm_inst_t *)&cmd_arm_show, + (parse_pgm_inst_t *)&cmd_arm_goto, + (parse_pgm_inst_t *)&cmd_arm_goto_fixed, + (parse_pgm_inst_t *)&cmd_arm_simulate, + (parse_pgm_inst_t *)&cmd_finger, + (parse_pgm_inst_t *)&cmd_pump, + (parse_pgm_inst_t *)&cmd_state1, + (parse_pgm_inst_t *)&cmd_state2, + (parse_pgm_inst_t *)&cmd_state3, + (parse_pgm_inst_t *)&cmd_state4, + (parse_pgm_inst_t *)&cmd_state5, + (parse_pgm_inst_t *)&cmd_state_debug, + (parse_pgm_inst_t *)&cmd_state_machine, + (parse_pgm_inst_t *)&cmd_servo_lintel, + (parse_pgm_inst_t *)&cmd_pump_current, + (parse_pgm_inst_t *)&cmd_manivelle, + (parse_pgm_inst_t *)&cmd_test, + + NULL, +}; diff --git a/projects/microb2009/mechboard/commands_ax12.c b/projects/microb2009/mechboard/commands_ax12.c new file mode 100644 index 0000000..b052944 --- /dev/null +++ b/projects/microb2009/mechboard/commands_ax12.c @@ -0,0 +1,427 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_ax12.c,v 1.3 2009-04-24 19:30:42 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "ax12_user.h" + +uint8_t addr_from_string(const char *s) +{ + /* 16 bits */ + if (!strcmp_P(s, PSTR("cw_angle_limit"))) + return AA_CW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("ccw_angle_limit"))) + return AA_CCW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("max_torque"))) + return AA_MAX_TORQUE_L; + if (!strcmp_P(s, PSTR("down_calibration"))) + return AA_DOWN_CALIBRATION_L; + if (!strcmp_P(s, PSTR("up_calibration"))) + return AA_UP_CALIBRATION_L; + if (!strcmp_P(s, PSTR("torque_limit"))) + return AA_TORQUE_LIMIT_L; + if (!strcmp_P(s, PSTR("position"))) + return AA_PRESENT_POSITION_L; + if (!strcmp_P(s, PSTR("speed"))) + return AA_PRESENT_SPEED_L; + if (!strcmp_P(s, PSTR("load"))) + return AA_PRESENT_LOAD_L; + if (!strcmp_P(s, PSTR("moving_speed"))) + return AA_MOVING_SPEED_L; + if (!strcmp_P(s, PSTR("model"))) + return AA_MODEL_NUMBER_L; + if (!strcmp_P(s, PSTR("goal_pos"))) + return AA_GOAL_POSITION_L; + if (!strcmp_P(s, PSTR("punch"))) + return AA_PUNCH_L; + + /* 8 bits */ + if (!strcmp_P(s, PSTR("firmware"))) + return AA_FIRMWARE; + if (!strcmp_P(s, PSTR("id"))) + return AA_ID; + if (!strcmp_P(s, PSTR("baudrate"))) + return AA_BAUD_RATE; + if (!strcmp_P(s, PSTR("delay"))) + return AA_DELAY_TIME; + if (!strcmp_P(s, PSTR("high_lim_temp"))) + return AA_HIGHEST_LIMIT_TEMP; + if (!strcmp_P(s, PSTR("low_lim_volt"))) + return AA_LOWEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("high_lim_volt"))) + return AA_HIGHEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("status_return"))) + return AA_STATUS_RETURN_LEVEL; + if (!strcmp_P(s, PSTR("alarm_led"))) + return AA_ALARM_LED; + if (!strcmp_P(s, PSTR("alarm_shutdown"))) + return AA_ALARM_SHUTDOWN; + if (!strcmp_P(s, PSTR("torque_enable"))) + return AA_TORQUE_ENABLE; + if (!strcmp_P(s, PSTR("led"))) + return AA_LED; + if (!strcmp_P(s, PSTR("cw_comp_margin"))) + return AA_CW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("ccw_comp_margin"))) + return AA_CCW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("cw_comp_slope"))) + return AA_CW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("ccw_comp_slope"))) + return AA_CCW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("voltage"))) + return AA_PRESENT_VOLTAGE; + if (!strcmp_P(s, PSTR("temp"))) + return AA_PRESENT_TEMP; + if (!strcmp_P(s, PSTR("reginst"))) + return AA_PRESENT_REGINST; + if (!strcmp_P(s, PSTR("moving"))) + return AA_MOVING; + if (!strcmp_P(s, PSTR("lock"))) + return AA_LOCK; + + return 0; +} + +/**********************************************************/ +/* Ax12_Stress */ + +/* this structure is filled when cmd_ax12_stress is parsed successfully */ +struct cmd_ax12_stress_result { + fixed_string_t arg0; + uint8_t id; +}; + +/* function called when cmd_ax12_stress is parsed successfully */ +static void cmd_ax12_stress_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_ax12_stress_result *res = parsed_result; + int i, nb_errs, id; + uint8_t val; + microseconds t; + + t = time_get_us2(); + nb_errs = 0; + for (i=0; i<1000; i++) { + if (AX12_read_byte(&gen.ax12, res->id, AA_ID, &val) != 0) + nb_errs ++; + } + + printf_P(PSTR("%d errors / 1000\r\n"), nb_errs); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %d ms\r\n"), (int)t); + + t = time_get_us2(); + nb_errs = 0; + for (i=0; i<1000; i++) { + if (AX12_write_int(&gen.ax12, res->id, AA_GOAL_POSITION_L, 500)) + nb_errs ++; + } + + printf_P(PSTR("%d errors / 1000\r\n"), nb_errs); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %d ms\r\n"), (int)t); + + /* test 5 servos */ + t = time_get_us2(); + nb_errs = 0; + id = 1; + for (i=0; i<100; i++) { + if (AX12_write_int(&gen.ax12, id, AA_GOAL_POSITION_L, 500)) + nb_errs ++; + id ++; + if (id > 5) + id = 1; + } + + printf_P(PSTR("%d errors / 100\r\n"), nb_errs); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %d ms\r\n"), (int)t); + + +} + +prog_char str_ax12_stress_arg0[] = "ax12_stress"; +parse_pgm_token_string_t cmd_ax12_stress_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_ax12_stress_result, arg0, str_ax12_stress_arg0); +parse_pgm_token_num_t cmd_ax12_stress_id = TOKEN_NUM_INITIALIZER(struct cmd_ax12_stress_result, id, UINT8); + +prog_char help_ax12_stress[] = "Stress an AX12 with 1000 'read id' commands (id)"; +parse_pgm_inst_t cmd_ax12_stress = { + .f = cmd_ax12_stress_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_ax12_stress, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_ax12_stress_arg0, + (prog_void *)&cmd_ax12_stress_id, + NULL, + }, +}; + +/**********************************************************/ +/* Ax12_Dump_Stats */ + +/* this structure is filled when cmd_ax12_dump_stats is parsed successfully */ +struct cmd_ax12_dump_stats_result { + fixed_string_t arg0; +}; + +/* function called when cmd_ax12_dump_stats is parsed successfully */ +static void cmd_ax12_dump_stats_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + ax12_dump_stats(); +} + +prog_char str_ax12_dump_stats_arg0[] = "ax12_dump_stats"; +parse_pgm_token_string_t cmd_ax12_dump_stats_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_ax12_dump_stats_result, arg0, str_ax12_dump_stats_arg0); + +prog_char help_ax12_dump_stats[] = "Dump AX12 stats"; +parse_pgm_inst_t cmd_ax12_dump_stats = { + .f = cmd_ax12_dump_stats_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_ax12_dump_stats, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_ax12_dump_stats_arg0, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_baudrate is parsed successfully */ +struct cmd_baudrate_result { + fixed_string_t arg0; + uint32_t arg1; +}; + +/* function called when cmd_baudrate is parsed successfully */ +static void cmd_baudrate_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_baudrate_result *res = parsed_result; + struct uart_config c; + + uart_getconf(UART_AX12_NUM, &c); + c.baudrate = res->arg1; + uart_setconf(UART_AX12_NUM, &c); +} + +prog_char str_baudrate_arg0[] = "baudrate"; +parse_pgm_token_string_t cmd_baudrate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0, str_baudrate_arg0); +parse_pgm_token_num_t cmd_baudrate_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1, UINT32); + +prog_char help_baudrate[] = "Change ax12 baudrate"; +parse_pgm_inst_t cmd_baudrate = { + .f = cmd_baudrate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_baudrate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_baudrate_arg0, + (prog_void *)&cmd_baudrate_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Uint16 */ + + +/* this structure is filled when cmd_uint16_read is parsed successfully */ +struct cmd_uint16_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint16_t val; +}; + +/* function called when cmd_uint16_read is parsed successfully */ +static void cmd_uint16_read_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint16_t val; + uint8_t addr = addr_from_string(res->arg1); + ret = ax12_user_read_int(&gen.ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.4x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint16_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint16_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0); +prog_char str_uint16_arg1[] = "moving_speed#model#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#down_calibration#up_calibration#torque_limit#" + "position#speed#load#punch"; +parse_pgm_token_string_t cmd_uint16_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1); +parse_pgm_token_num_t cmd_uint16_num = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, num, UINT8); + +prog_char help_uint16_read[] = "Read uint16 value (type, num)"; +parse_pgm_inst_t cmd_uint16_read = { + .f = cmd_uint16_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0, + (prog_void *)&cmd_uint16_arg1, + (prog_void *)&cmd_uint16_num, + NULL, + }, +}; + +/* function called when cmd_uint16_write is parsed successfully */ +static void cmd_uint16_write_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint8_t addr = addr_from_string(res->arg1); + printf_P(PSTR("writing %s: %d [0x%.4x]\r\n"), res->arg1, + res->val, res->val); + ret = ax12_user_write_int(&gen.ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint16_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint16_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0_w); +prog_char str_uint16_arg1_w[] = "moving_speed#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#torque_limit#punch"; +parse_pgm_token_string_t cmd_uint16_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1_w); +parse_pgm_token_num_t cmd_uint16_val = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, val, UINT16); + +prog_char help_uint16_write[] = "Write uint16 value (write, num, val)"; +parse_pgm_inst_t cmd_uint16_write = { + .f = cmd_uint16_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0_w, + (prog_void *)&cmd_uint16_arg1_w, + (prog_void *)&cmd_uint16_num, + (prog_void *)&cmd_uint16_val, + NULL, + }, +}; + +/**********************************************************/ +/* Uint8 */ + + +/* this structure is filled when cmd_uint8_read is parsed successfully */ +struct cmd_uint8_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint8_t val; +}; + +/* function called when cmd_uint8_read is parsed successfully */ +static void cmd_uint8_read_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t ret; + uint8_t val; + uint8_t addr = addr_from_string(res->arg1); + + ret = ax12_user_read_byte(&gen.ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.2x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint8_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint8_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0); +prog_char str_uint8_arg1[] = "id#firmware#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "voltage#temp#reginst#moving#lock"; +parse_pgm_token_string_t cmd_uint8_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1); +parse_pgm_token_num_t cmd_uint8_num = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, num, UINT8); + +prog_char help_uint8_read[] = "Read uint8 value (type, num)"; +parse_pgm_inst_t cmd_uint8_read = { + .f = cmd_uint8_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0, + (prog_void *)&cmd_uint8_arg1, + (prog_void *)&cmd_uint8_num, + NULL, + }, +}; + +/* function called when cmd_uint8_write is parsed successfully */ +static void cmd_uint8_write_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t addr = addr_from_string(res->arg1); + uint8_t ret; + printf_P(PSTR("writing %s: %d [0x%.2x]\r\n"), res->arg1, + res->val, res->val); + ret = ax12_user_write_byte(&gen.ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint8_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint8_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0_w); +prog_char str_uint8_arg1_w[] = "id#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "reginst#lock"; +parse_pgm_token_string_t cmd_uint8_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1_w); +parse_pgm_token_num_t cmd_uint8_val = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, val, UINT8); + +prog_char help_uint8_write[] = "Write uint8 value (write, num, val)"; +parse_pgm_inst_t cmd_uint8_write = { + .f = cmd_uint8_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0_w, + (prog_void *)&cmd_uint8_arg1_w, + (prog_void *)&cmd_uint8_num, + (prog_void *)&cmd_uint8_val, + NULL, + }, +}; diff --git a/projects/microb2009/mechboard/commands_cs.c b/projects/microb2009/mechboard/commands_cs.c new file mode 100644 index 0000000..c2937f5 --- /dev/null +++ b/projects/microb2009/mechboard/commands_cs.c @@ -0,0 +1,670 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_cs.c,v 1.2 2009-04-07 20:03:48 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "cs.h" +#include "cmdline.h" + +struct csb_list { + const prog_char *name; + struct cs_block *csb; +}; + +prog_char csb_left_arm_str[] = "left_arm"; +prog_char csb_right_arm_str[] = "right_arm"; +struct csb_list csb_list[] = { + { .name = csb_left_arm_str, .csb = &mechboard.left_arm }, + { .name = csb_right_arm_str, .csb = &mechboard.right_arm }, +}; + +struct cmd_cs_result { + fixed_string_t cmdname; + fixed_string_t csname; +}; + +/* token to be used for all cs-related commands */ +prog_char str_csb_name[] = "left_arm#right_arm"; +parse_pgm_token_string_t cmd_csb_name_tok = TOKEN_STRING_INITIALIZER(struct cmd_cs_result, csname, str_csb_name); + +struct cs_block *cs_from_name(const char *name) +{ + unsigned int i; + + for (i=0; i<(sizeof(csb_list)/sizeof(*csb_list)); i++) { + if (!strcmp_P(name, csb_list[i].name)) + return csb_list[i].csb; + } + return NULL; +} + +/**********************************************************/ +/* Gains for control system */ + +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_result { + struct cmd_cs_result cs; + int16_t p; + int16_t i; + int16_t d; +}; + +/* function called when cmd_gain is parsed successfully */ +static void cmd_gain_parsed(void * parsed_result, void *show) +{ + struct cmd_gain_result *res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_gains(&csb->pid, res->p, res->i, res->d); + + printf_P(PSTR("%s %s %d %d %d\r\n"), + res->cs.cmdname, + res->cs.csname, + pid_get_gain_P(&csb->pid), + pid_get_gain_I(&csb->pid), + pid_get_gain_D(&csb->pid)); +} + +prog_char str_gain_arg0[] = "gain"; +parse_pgm_token_string_t cmd_gain_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, cs.cmdname, str_gain_arg0); +parse_pgm_token_num_t cmd_gain_p = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, p, INT16); +parse_pgm_token_num_t cmd_gain_i = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, i, INT16); +parse_pgm_token_num_t cmd_gain_d = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, d, INT16); + +prog_char help_gain[] = "Set gain values for PID"; +parse_pgm_inst_t cmd_gain = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_gain_p, + (prog_void *)&cmd_gain_i, + (prog_void *)&cmd_gain_d, + NULL, + }, +}; + +/* show */ +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_gain_show_arg[] = "show"; +parse_pgm_token_string_t cmd_gain_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_gain_show_result, show, str_gain_show_arg); + +prog_char help_gain_show[] = "Show gain values for PID"; +parse_pgm_inst_t cmd_gain_show = { + .f = cmd_gain_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_gain_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_gain_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Speeds for control system */ + +/* this structure is filled when cmd_speed is parsed successfully */ +struct cmd_speed_result { + struct cmd_cs_result cs; + uint16_t s; +}; + +/* function called when cmd_speed is parsed successfully */ +static void cmd_speed_parsed(void *parsed_result, __attribute__((unused)) void *show) +{ + struct cmd_speed_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + +#if notyet + if (!show) + ramp_set_vars(&csb->ramp, res->s, res->s); /* set speed */ + + printf_P(PSTR("%s %lu\r\n"), + res->cs.csname, + ext.r_b.var_pos); +#else + printf_P(PSTR("TODO\r\n")); +#endif +} + +prog_char str_speed_arg0[] = "speed"; +parse_pgm_token_string_t cmd_speed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, cs.cmdname, str_speed_arg0); +parse_pgm_token_num_t cmd_speed_s = TOKEN_NUM_INITIALIZER(struct cmd_speed_result, s, UINT16); + +prog_char help_speed[] = "Set speed values for ramp filter"; +parse_pgm_inst_t cmd_speed = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_speed_s, + NULL, + }, +}; + +/* show */ +struct cmd_speed_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_speed_show_arg[] = "show"; +parse_pgm_token_string_t cmd_speed_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_speed_show_result, show, str_speed_show_arg); + +prog_char help_speed_show[] = "Show speed values for ramp filter"; +parse_pgm_inst_t cmd_speed_show = { + .f = cmd_speed_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_speed_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_speed_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Derivate_Filters for control system */ + +/* this structure is filled when cmd_derivate_filter is parsed successfully */ +struct cmd_derivate_filter_result { + struct cmd_cs_result cs; + uint8_t size; +}; + +/* function called when cmd_derivate_filter is parsed successfully */ +static void cmd_derivate_filter_parsed(void *parsed_result, void *show) +{ + struct cmd_derivate_filter_result * res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_derivate_filter(&csb->pid, res->size); + + printf_P(PSTR("%s %s %u\r\n"), + res->cs.cmdname, + res->cs.csname, + pid_get_derivate_filter(&csb->pid)); +} + +prog_char str_derivate_filter_arg0[] = "derivate_filter"; +parse_pgm_token_string_t cmd_derivate_filter_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_derivate_filter_result, cs.cmdname, str_derivate_filter_arg0); +parse_pgm_token_num_t cmd_derivate_filter_size = TOKEN_NUM_INITIALIZER(struct cmd_derivate_filter_result, size, UINT32); + +prog_char help_derivate_filter[] = "Set derivate_filter values for PID (in, I, out)"; +parse_pgm_inst_t cmd_derivate_filter = { + .f = cmd_derivate_filter_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_derivate_filter, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_derivate_filter_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_derivate_filter_size, + NULL, + }, +}; + +/* show */ + +struct cmd_derivate_filter_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_derivate_filter_show_arg[] = "show"; +parse_pgm_token_string_t cmd_derivate_filter_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_derivate_filter_show_result, show, str_derivate_filter_show_arg); + +prog_char help_derivate_filter_show[] = "Show derivate_filter values for PID"; +parse_pgm_inst_t cmd_derivate_filter_show = { + .f = cmd_derivate_filter_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_derivate_filter_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_derivate_filter_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_derivate_filter_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Consign for control system */ + +/* this structure is filled when cmd_consign is parsed successfully */ +struct cmd_consign_result { + struct cmd_cs_result cs; + int32_t p; +}; + +/* function called when cmd_consign is parsed successfully */ +static void cmd_consign_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_consign_result * res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + cs_set_consign(&csb->cs, res->p); +} + +prog_char str_consign_arg0[] = "consign"; +parse_pgm_token_string_t cmd_consign_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_consign_result, cs.cmdname, str_consign_arg0); +parse_pgm_token_num_t cmd_consign_p = TOKEN_NUM_INITIALIZER(struct cmd_consign_result, p, INT32); + +prog_char help_consign[] = "Set consign value"; +parse_pgm_inst_t cmd_consign = { + .f = cmd_consign_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_consign, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_consign_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_consign_p, + NULL, + }, +}; + + +/**********************************************************/ +/* Maximums for control system */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_result { + struct cmd_cs_result cs; + uint32_t in; + uint32_t i; + uint32_t out; +}; + +/* function called when cmd_maximum is parsed successfully */ +static void cmd_maximum_parsed(void *parsed_result, void *show) +{ + struct cmd_maximum_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_maximums(&csb->pid, res->in, res->i, res->out); + + printf_P(PSTR("maximum %s %lu %lu %lu\r\n"), + res->cs.csname, + pid_get_max_in(&csb->pid), + pid_get_max_I(&csb->pid), + pid_get_max_out(&csb->pid)); +} + +prog_char str_maximum_arg0[] = "maximum"; +parse_pgm_token_string_t cmd_maximum_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, cs.cmdname, str_maximum_arg0); +parse_pgm_token_num_t cmd_maximum_in = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, in, UINT32); +parse_pgm_token_num_t cmd_maximum_i = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, i, UINT32); +parse_pgm_token_num_t cmd_maximum_out = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, out, UINT32); + +prog_char help_maximum[] = "Set maximum values for PID (in, I, out)"; +parse_pgm_inst_t cmd_maximum = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_maximum_in, + (prog_void *)&cmd_maximum_i, + (prog_void *)&cmd_maximum_out, + NULL, + }, +}; + +/* show */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; +prog_char str_maximum_show_arg[] = "show"; +parse_pgm_token_string_t cmd_maximum_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_maximum_show_result, show, str_maximum_show_arg); + +prog_char help_maximum_show[] = "Show maximum values for PID"; +parse_pgm_inst_t cmd_maximum_show = { + .f = cmd_maximum_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_maximum_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_maximum_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Quadramp for control system */ + +/* this structure is filled when cmd_quadramp is parsed successfully */ +struct cmd_quadramp_result { + struct cmd_cs_result cs; + uint32_t ap; + uint32_t an; + uint32_t sp; + uint32_t sn; +}; + +/* function called when cmd_quadramp is parsed successfully */ +static void cmd_quadramp_parsed(void *parsed_result, void *show) +{ + struct cmd_quadramp_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) { + quadramp_set_1st_order_vars(&csb->qr, res->sp, res->sn); + quadramp_set_2nd_order_vars(&csb->qr, res->ap, res->an); + } + + printf_P(PSTR("quadramp %s %ld %ld %ld %ld\r\n"), + res->cs.csname, + csb->qr.var_2nd_ord_pos, + csb->qr.var_2nd_ord_neg, + csb->qr.var_1st_ord_pos, + csb->qr.var_1st_ord_neg); +} + +prog_char str_quadramp_arg0[] = "quadramp"; +parse_pgm_token_string_t cmd_quadramp_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, cs.cmdname, str_quadramp_arg0); +parse_pgm_token_num_t cmd_quadramp_ap = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, ap, UINT32); +parse_pgm_token_num_t cmd_quadramp_an = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, an, UINT32); +parse_pgm_token_num_t cmd_quadramp_sp = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sp, UINT32); +parse_pgm_token_num_t cmd_quadramp_sn = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sn, UINT32); + +prog_char help_quadramp[] = "Set quadramp values (acc+, acc-, speed+, speed-)"; +parse_pgm_inst_t cmd_quadramp = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_quadramp_ap, + (prog_void *)&cmd_quadramp_an, + (prog_void *)&cmd_quadramp_sp, + (prog_void *)&cmd_quadramp_sn, + + NULL, + }, +}; + +/* show */ + +struct cmd_quadramp_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_quadramp_show_arg[] = "show"; +parse_pgm_token_string_t cmd_quadramp_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_show_result, show, str_quadramp_show_arg); + +prog_char help_quadramp_show[] = "Get quadramp values for control system"; +parse_pgm_inst_t cmd_quadramp_show = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_quadramp_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_quadramp_show_arg, + NULL, + }, +}; + + + +/**********************************************************/ +/* cs_status show for control system */ + +/* this structure is filled when cmd_cs_status is parsed successfully */ +struct cmd_cs_status_result { + struct cmd_cs_result cs; + fixed_string_t arg; +}; + +/* function called when cmd_cs_status is parsed successfully */ +static void cmd_cs_status_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_cs_status_result *res = parsed_result; + struct cs_block *csb; + uint8_t loop = 0; + uint8_t print_pid = 0, print_cs = 0; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + if (strcmp_P(res->arg, PSTR("on")) == 0) { + csb->on = 1; + printf_P(PSTR("%s is on\r\n"), res->cs.csname); + return; + } + else if (strcmp_P(res->arg, PSTR("off")) == 0) { + csb->on = 0; + printf_P(PSTR("%s is off\r\n"), res->cs.csname); + return; + } + else if (strcmp_P(res->arg, PSTR("show")) == 0) { + print_cs = 1; + } + else if (strcmp_P(res->arg, PSTR("loop_show")) == 0) { + loop = 1; + print_cs = 1; + } + else if (strcmp_P(res->arg, PSTR("pid_show")) == 0) { + print_pid = 1; + } + else if (strcmp_P(res->arg, PSTR("pid_loop_show")) == 0) { + print_pid = 1; + loop = 1; + } + + printf_P(PSTR("%s cs is %s\r\n"), res->cs.csname, csb->on ? "on":"off"); + do { + if (print_cs) + dump_cs(res->cs.csname, &csb->cs); + if (print_pid) + dump_pid(res->cs.csname, &csb->pid); + wait_ms(100); + } while(loop && !cmdline_keypressed()); +} + +prog_char str_cs_status_arg0[] = "cs_status"; +parse_pgm_token_string_t cmd_cs_status_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_cs_status_result, cs.cmdname, str_cs_status_arg0); +prog_char str_cs_status_arg[] = "pid_show#pid_loop_show#show#loop_show#on#off"; +parse_pgm_token_string_t cmd_cs_status_arg = TOKEN_STRING_INITIALIZER(struct cmd_cs_status_result, arg, str_cs_status_arg); + +prog_char help_cs_status[] = "Show cs status"; +parse_pgm_inst_t cmd_cs_status = { + .f = cmd_cs_status_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_cs_status, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_cs_status_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_cs_status_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Blocking_I for control system */ + +/* this structure is filled when cmd_blocking_i is parsed successfully */ +struct cmd_blocking_i_result { + struct cmd_cs_result cs; + int32_t k1; + int32_t k2; + uint32_t i; + uint16_t cpt; +}; + +/* function called when cmd_blocking_i is parsed successfully */ +static void cmd_blocking_i_parsed(void *parsed_result, void *show) +{ + struct cmd_blocking_i_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + bd_set_current_thresholds(&csb->bd, res->k1, res->k2, + res->i, res->cpt); + + printf_P(PSTR("%s %s %ld %ld %ld %d\r\n"), + res->cs.cmdname, + res->cs.csname, + csb->bd.k1, + csb->bd.k2, + csb->bd.i_thres, + csb->bd.cpt_thres); +} + +prog_char str_blocking_i_arg0[] = "blocking"; +parse_pgm_token_string_t cmd_blocking_i_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_blocking_i_result, cs.cmdname, str_blocking_i_arg0); +parse_pgm_token_num_t cmd_blocking_i_k1 = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, k1, INT32); +parse_pgm_token_num_t cmd_blocking_i_k2 = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, k2, INT32); +parse_pgm_token_num_t cmd_blocking_i_i = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, i, UINT32); +parse_pgm_token_num_t cmd_blocking_i_cpt = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, cpt, UINT16); + +prog_char help_blocking_i[] = "Set blocking detection values (k1, k2, i, cpt)"; +parse_pgm_inst_t cmd_blocking_i = { + .f = cmd_blocking_i_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_blocking_i, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_blocking_i_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_blocking_i_k1, + (prog_void *)&cmd_blocking_i_k2, + (prog_void *)&cmd_blocking_i_i, + (prog_void *)&cmd_blocking_i_cpt, + NULL, + }, +}; + +/* show */ + +struct cmd_blocking_i_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_blocking_i_show_arg[] = "show"; +parse_pgm_token_string_t cmd_blocking_i_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_blocking_i_show_result, show, str_blocking_i_show_arg); + +prog_char help_blocking_i_show[] = "Show blocking detection values"; +parse_pgm_inst_t cmd_blocking_i_show = { + .f = cmd_blocking_i_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_blocking_i_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_blocking_i_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_blocking_i_show_arg, + NULL, + }, +}; + + diff --git a/projects/microb2009/mechboard/commands_gen.c b/projects/microb2009/mechboard/commands_gen.c new file mode 100644 index 0000000..6517ea0 --- /dev/null +++ b/projects/microb2009/mechboard/commands_gen.c @@ -0,0 +1,579 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_gen.c,v 1.5 2009-11-08 17:25:00 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <encoders_spi.h> +#include <adc.h> + +#include <scheduler.h> +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include <diagnostic.h> + +#include "main.h" +#include "cmdline.h" +#include "sensor.h" + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Bootloader */ + +/* this structure is filled when cmd_bootloader is parsed successfully */ +struct cmd_bootloader_result { + fixed_string_t arg0; +}; + +/* function called when cmd_bootloader is parsed successfully */ +static void cmd_bootloader_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + bootloader(); +} + +prog_char str_bootloader_arg0[] = "bootloader"; +parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0); + +prog_char help_bootloader[] = "Launch the bootloader"; +parse_pgm_inst_t cmd_bootloader = { + .f = cmd_bootloader_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_bootloader, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_bootloader_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Encoders tests */ + +/* this structure is filled when cmd_encoders is parsed successfully */ +struct cmd_encoders_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_encoders is parsed successfully */ +static void cmd_encoders_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_encoders_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("reset"))) { + encoders_spi_set_value((void *)0, 0); + encoders_spi_set_value((void *)1, 0); + encoders_spi_set_value((void *)2, 0); + encoders_spi_set_value((void *)3, 0); + return; + } + + /* show */ + while(!cmdline_keypressed()) { + printf_P(PSTR("% .8ld % .8ld % .8ld % .8ld\r\n"), + encoders_spi_get_value((void *)0), + encoders_spi_get_value((void *)1), + encoders_spi_get_value((void *)2), + encoders_spi_get_value((void *)3)); + wait_ms(100); + } +} + +prog_char str_encoders_arg0[] = "encoders"; +parse_pgm_token_string_t cmd_encoders_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg0, str_encoders_arg0); +prog_char str_encoders_arg1[] = "show#reset"; +parse_pgm_token_string_t cmd_encoders_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg1, str_encoders_arg1); + +prog_char help_encoders[] = "Show encoders values"; +parse_pgm_inst_t cmd_encoders = { + .f = cmd_encoders_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_encoders, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_encoders_arg0, + (prog_void *)&cmd_encoders_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Scheduler show */ + +/* this structure is filled when cmd_scheduler is parsed successfully */ +struct cmd_scheduler_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_scheduler is parsed successfully */ +static void cmd_scheduler_parsed( __attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + scheduler_dump_events(); +} + +prog_char str_scheduler_arg0[] = "scheduler"; +parse_pgm_token_string_t cmd_scheduler_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg0, str_scheduler_arg0); +prog_char str_scheduler_arg1[] = "show"; +parse_pgm_token_string_t cmd_scheduler_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg1, str_scheduler_arg1); + +prog_char help_scheduler[] = "Show scheduler events"; +parse_pgm_inst_t cmd_scheduler = { + .f = cmd_scheduler_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scheduler, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scheduler_arg0, + (prog_void *)&cmd_scheduler_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pwms tests */ + +/* this structure is filled when cmd_pwm is parsed successfully */ +struct cmd_pwm_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; +}; + +/* function called when cmd_pwm is parsed successfully */ +static void cmd_pwm_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + void * pwm_ptr = NULL; + struct cmd_pwm_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("1(4A)"))) + pwm_ptr = &gen.pwm1_4A; + else if (!strcmp_P(res->arg1, PSTR("2(4B)"))) + pwm_ptr = &gen.pwm2_4B; + else if (!strcmp_P(res->arg1, PSTR("3(1A)"))) + pwm_ptr = &gen.pwm3_1A; + else if (!strcmp_P(res->arg1, PSTR("4(1B)"))) + pwm_ptr = &gen.pwm4_1B; + + else if (!strcmp_P(res->arg1, PSTR("s1(3C)"))) + pwm_ptr = &gen.servo1; + else if (!strcmp_P(res->arg1, PSTR("s2(5A)"))) + pwm_ptr = &gen.servo2; + else if (!strcmp_P(res->arg1, PSTR("s3(5B)"))) + pwm_ptr = &gen.servo3; + else if (!strcmp_P(res->arg1, PSTR("s3(5C)"))) + pwm_ptr = &gen.servo4; + + if (pwm_ptr) + pwm_ng_set(pwm_ptr, res->arg2); + + printf_P(PSTR("done\r\n")); +} + +prog_char str_pwm_arg0[] = "pwm"; +parse_pgm_token_string_t cmd_pwm_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg0, str_pwm_arg0); +prog_char str_pwm_arg1[] = "1(4A)#2(4B)#3(1A)#4(1B)#s1(3C)#s2(5A)#s3(5B)#s4(5C)"; +parse_pgm_token_string_t cmd_pwm_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg1, str_pwm_arg1); +parse_pgm_token_num_t cmd_pwm_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pwm_result, arg2, INT16); + +prog_char help_pwm[] = "Set pwm values [-4096 ; 4095]"; +parse_pgm_inst_t cmd_pwm = { + .f = cmd_pwm_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pwm, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pwm_arg0, + (prog_void *)&cmd_pwm_arg1, + (prog_void *)&cmd_pwm_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Adcs tests */ + +/* this structure is filled when cmd_adc is parsed successfully */ +struct cmd_adc_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_adc is parsed successfully */ +static void cmd_adc_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_adc_result *res = parsed_result; + uint8_t i, loop = 0; + + if (!strcmp_P(res->arg1, PSTR("loop_show"))) + loop = 1; + + do { + printf_P(PSTR("ADC values: ")); + for (i=0; i<ADC_MAX; i++) { + printf_P(PSTR("%.4d "), sensor_get_adc(i)); + } + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (loop && !cmdline_keypressed()); +} + +prog_char str_adc_arg0[] = "adc"; +parse_pgm_token_string_t cmd_adc_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_adc_result, arg0, str_adc_arg0); +prog_char str_adc_arg1[] = "show#loop_show"; +parse_pgm_token_string_t cmd_adc_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_adc_result, arg1, str_adc_arg1); + +prog_char help_adc[] = "Show adc values"; +parse_pgm_inst_t cmd_adc = { + .f = cmd_adc_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_adc, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_adc_arg0, + (prog_void *)&cmd_adc_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Sensors tests */ + +/* this structure is filled when cmd_sensor is parsed successfully */ +struct cmd_sensor_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_sensor is parsed successfully */ +static void cmd_sensor_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_sensor_result *res = parsed_result; + uint8_t i, loop = 0; + + if (!strcmp_P(res->arg1, PSTR("loop_show"))) + loop = 1; + + do { + printf_P(PSTR("SENSOR values: ")); + for (i=0; i<SENSOR_MAX; i++) { + printf_P(PSTR("%d "), !!sensor_get(i)); + } + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (loop && !cmdline_keypressed()); +} + +prog_char str_sensor_arg0[] = "sensor"; +parse_pgm_token_string_t cmd_sensor_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_sensor_result, arg0, str_sensor_arg0); +prog_char str_sensor_arg1[] = "show#loop_show"; +parse_pgm_token_string_t cmd_sensor_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_sensor_result, arg1, str_sensor_arg1); + +prog_char help_sensor[] = "Show sensor values"; +parse_pgm_inst_t cmd_sensor = { + .f = cmd_sensor_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sensor, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_sensor_arg0, + (prog_void *)&cmd_sensor_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Log */ + +/* this structure is filled when cmd_log is parsed successfully */ +struct cmd_log_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t arg2; + fixed_string_t arg3; +}; + +/* keep it sync with string choice */ +static const prog_char uart_log[] = "uart"; +static const prog_char i2c_log[] = "i2c"; +static const prog_char i2cproto_log[] = "i2cproto"; +static const prog_char sensor_log[] = "sensor"; +static const prog_char block_log[] = "bd"; +static const prog_char arm_log[] = "arm"; +static const prog_char finger_log[] = "finger"; +static const prog_char state_log[] = "state"; +static const prog_char ax12_log[] = "ax12"; + +struct log_name_and_num { + const prog_char * name; + uint8_t num; +}; + +static const struct log_name_and_num log_name_and_num[] = { + { uart_log, E_UART }, + { i2c_log, E_I2C }, + { i2cproto_log, E_USER_I2C_PROTO }, + { sensor_log, E_USER_SENSOR }, + { block_log, E_BLOCKING_DETECTION_MANAGER }, + { arm_log, E_USER_ARM }, + { finger_log, E_USER_FINGER }, + { state_log, E_USER_ST_MACH }, + { ax12_log, E_USER_AX12 }, +}; + +static uint8_t +log_name2num(const char * s) +{ + uint8_t i; + + for (i=0; i<sizeof(log_name_and_num)/sizeof(struct log_name_and_num); i++) { + if (!strcmp_P(s, log_name_and_num[i].name)) { + return log_name_and_num[i].num; + } + } + return 0; +} + +const prog_char * +log_num2name(uint8_t num) +{ + uint8_t i; + + for (i=0; i<sizeof(log_name_and_num)/sizeof(struct log_name_and_num); i++) { + if (num == log_name_and_num[i].num) { + return log_name_and_num[i].name; + } + } + return NULL; +} + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_do_show(void) +{ + uint8_t i, empty=1; + const prog_char * name; + + printf_P(PSTR("log level is %d\r\n"), gen.log_level); + for (i=0; i<NB_LOGS; i++) { + name = log_num2name(gen.logs[i]); + if (name) { + printf_P(PSTR("log type %S is on\r\n"), name); + empty = 0; + } + } + if (empty) + printf_P(PSTR("no log configured\r\n"), gen.logs[i]); +} + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_log_result *res = (struct cmd_log_result *) parsed_result; + + if (!strcmp_P(res->arg1, PSTR("level"))) { + gen.log_level = res->arg2; + } + + /* else it is a show */ + cmd_log_do_show(); +} + +prog_char str_log_arg0[] = "log"; +parse_pgm_token_string_t cmd_log_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg0, str_log_arg0); +prog_char str_log_arg1[] = "level"; +parse_pgm_token_string_t cmd_log_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1); +parse_pgm_token_num_t cmd_log_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_log_result, arg2, INT32); + +prog_char help_log[] = "Set log options: level (0 -> 5)"; +parse_pgm_inst_t cmd_log = { + .f = cmd_log_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1, + (prog_void *)&cmd_log_arg2, + NULL, + }, +}; + +prog_char str_log_arg1_show[] = "show"; +parse_pgm_token_string_t cmd_log_arg1_show = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1_show); + +prog_char help_log_show[] = "Show configured logs"; +parse_pgm_inst_t cmd_log_show = { + .f = cmd_log_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1_show, + NULL, + }, +}; + +/* this structure is filled when cmd_log is parsed successfully */ +struct cmd_log_type_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_type_parsed(void * parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_log_type_result *res = (struct cmd_log_type_result *) parsed_result; + uint8_t lognum; + uint8_t i; + + lognum = log_name2num(res->arg2); + if (lognum == 0) { + printf_P(PSTR("Cannot find log num\r\n")); + return; + } + + if (!strcmp_P(res->arg3, PSTR("on"))) { + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == lognum) { + printf_P(PSTR("Already on\r\n")); + return; + } + } + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == 0) { + gen.logs[i] = lognum; + break; + } + } + if (i==NB_LOGS) { + printf_P(PSTR("no more room\r\n")); + } + } + else if (!strcmp_P(res->arg3, PSTR("off"))) { + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == lognum) { + gen.logs[i] = 0; + break; + } + } + if (i==NB_LOGS) { + printf_P(PSTR("already off\r\n")); + } + } + cmd_log_do_show(); +} + +prog_char str_log_arg1_type[] = "type"; +parse_pgm_token_string_t cmd_log_arg1_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg1, str_log_arg1_type); +/* keep it sync with log_name_and_num above */ +prog_char str_log_arg2_type[] = "uart#i2c#i2cproto#sensor#bd#arm#finger#state#ax12"; +parse_pgm_token_string_t cmd_log_arg2_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg2, str_log_arg2_type); +prog_char str_log_arg3[] = "on#off"; +parse_pgm_token_string_t cmd_log_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg3, str_log_arg3); + +prog_char help_log_type[] = "Set log type"; +parse_pgm_inst_t cmd_log_type = { + .f = cmd_log_type_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log_type, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1_type, + (prog_void *)&cmd_log_arg2_type, + (prog_void *)&cmd_log_arg3, + NULL, + }, +}; + + +/**********************************************************/ +/* Stack_Space */ + +/* this structure is filled when cmd_stack_space is parsed successfully */ +struct cmd_stack_space_result { + fixed_string_t arg0; +}; + +/* function called when cmd_stack_space is parsed successfully */ +static void cmd_stack_space_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + printf("res stack: %d\r\n", min_stack_space_available()); + +} + +prog_char str_stack_space_arg0[] = "stack_space"; +parse_pgm_token_string_t cmd_stack_space_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_stack_space_result, arg0, str_stack_space_arg0); + +prog_char help_stack_space[] = "Display remaining stack space"; +parse_pgm_inst_t cmd_stack_space = { + .f = cmd_stack_space_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_stack_space, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_stack_space_arg0, + NULL, + }, +}; diff --git a/projects/microb2009/mechboard/commands_mechboard.c b/projects/microb2009/mechboard/commands_mechboard.c new file mode 100644 index 0000000..2790618 --- /dev/null +++ b/projects/microb2009/mechboard/commands_mechboard.c @@ -0,0 +1,1033 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_mechboard.c,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "sensor.h" +#include "cmdline.h" +#include "state.h" +#include "i2c_protocol.h" +#include "actuator.h" +#include "arm_xy.h" +#include "arm_highlevel.h" +#include "actuator.h" + +extern uint16_t state_debug; + +struct cmd_event_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + + +/* function called when cmd_event is parsed successfully */ +static void cmd_event_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + u08 bit=0; + + struct cmd_event_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("all"))) { + bit = DO_ENCODERS | DO_CS | DO_BD | DO_POWER; + if (!strcmp_P(res->arg2, PSTR("on"))) + mechboard.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) + mechboard.flags &= bit; + else { /* show */ + printf_P(PSTR("encoders is %s\r\n"), + (DO_ENCODERS & mechboard.flags) ? "on":"off"); + printf_P(PSTR("cs is %s\r\n"), + (DO_CS & mechboard.flags) ? "on":"off"); + printf_P(PSTR("bd is %s\r\n"), + (DO_BD & mechboard.flags) ? "on":"off"); + printf_P(PSTR("power is %s\r\n"), + (DO_POWER & mechboard.flags) ? "on":"off"); + } + return; + } + + if (!strcmp_P(res->arg1, PSTR("encoders"))) + bit = DO_ENCODERS; + else if (!strcmp_P(res->arg1, PSTR("cs"))) { + if (!strcmp_P(res->arg2, PSTR("on"))) + arm_calibrate(); + bit = DO_CS; + } + else if (!strcmp_P(res->arg1, PSTR("bd"))) + bit = DO_BD; + else if (!strcmp_P(res->arg1, PSTR("power"))) + bit = DO_POWER; + + + if (!strcmp_P(res->arg2, PSTR("on"))) + mechboard.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) { + if (!strcmp_P(res->arg1, PSTR("cs"))) { + pwm_ng_set(LEFT_ARM_PWM, 0); + pwm_ng_set(RIGHT_ARM_PWM, 0); + } + mechboard.flags &= (~bit); + } + printf_P(PSTR("%s is %s\r\n"), res->arg1, + (bit & mechboard.flags) ? "on":"off"); +} + +prog_char str_event_arg0[] = "event"; +parse_pgm_token_string_t cmd_event_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg0, str_event_arg0); +prog_char str_event_arg1[] = "all#encoders#cs#bd#power"; +parse_pgm_token_string_t cmd_event_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg1); +prog_char str_event_arg2[] = "on#off#show"; +parse_pgm_token_string_t cmd_event_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg2, str_event_arg2); + +prog_char help_event[] = "Enable/disable events"; +parse_pgm_inst_t cmd_event = { + .f = cmd_event_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_event, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_event_arg0, + (prog_void *)&cmd_event_arg1, + (prog_void *)&cmd_event_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Color */ + +/* this structure is filled when cmd_color is parsed successfully */ +struct cmd_color_result { + fixed_string_t arg0; + fixed_string_t color; +}; + +/* function called when cmd_color is parsed successfully */ +static void cmd_color_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_color_result *res = (struct cmd_color_result *) parsed_result; + if (!strcmp_P(res->color, PSTR("red"))) { + mechboard.our_color = I2C_COLOR_RED; + } + else if (!strcmp_P(res->color, PSTR("green"))) { + mechboard.our_color = I2C_COLOR_GREEN; + } + printf_P(PSTR("Done\r\n")); +} + +prog_char str_color_arg0[] = "color"; +parse_pgm_token_string_t cmd_color_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_color_result, arg0, str_color_arg0); +prog_char str_color_color[] = "green#red"; +parse_pgm_token_string_t cmd_color_color = TOKEN_STRING_INITIALIZER(struct cmd_color_result, color, str_color_color); + +prog_char help_color[] = "Set our color"; +parse_pgm_inst_t cmd_color = { + .f = cmd_color_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_color, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_color_arg0, + (prog_void *)&cmd_color_color, + NULL, + }, +}; + +/**********************************************************/ +/* arm_show */ + +/* this structure is filled when cmd_arm_show is parsed successfully */ +struct cmd_arm_show_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_arm_show is parsed successfully */ +static void cmd_arm_show_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_arm_show_result *res = parsed_result; + + if (strcmp_P(res->arg1, PSTR("left")) == 0) + arm_dump(&left_arm); + else if (strcmp_P(res->arg1, PSTR("right")) == 0) + arm_dump(&right_arm); + else { + arm_dump(&left_arm); + arm_dump(&right_arm); + } +} + +prog_char str_arm_show_arg0[] = "arm"; +parse_pgm_token_string_t cmd_arm_show_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_show_result, arg0, str_arm_show_arg0); +prog_char str_arm_show_arg1[] = "left#right#both"; +parse_pgm_token_string_t cmd_arm_show_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_arm_show_result, arg1, str_arm_show_arg1); +prog_char str_arm_show_arg2[] = "show"; +parse_pgm_token_string_t cmd_arm_show_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_arm_show_result, arg2, str_arm_show_arg2); + +prog_char help_arm_show[] = "Show arm status"; +parse_pgm_inst_t cmd_arm_show = { + .f = cmd_arm_show_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_show_arg0, + (prog_void *)&cmd_arm_show_arg1, + (prog_void *)&cmd_arm_show_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* arm_goto */ + +/* this structure is filled when cmd_arm_goto is parsed successfully */ +struct cmd_arm_goto_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; + int16_t arg3; + int16_t arg4; +}; + +/* function called when cmd_arm_goto is parsed successfully */ +static void cmd_arm_goto_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_arm_goto_result *res = parsed_result; + uint8_t err; + + if (strcmp_P(res->arg1, PSTR("left")) == 0) { + arm_do_xy(&left_arm, res->arg2, res->arg3, res->arg4); + err = arm_wait_traj_end(&left_arm, ARM_TRAJ_ALL); + if (err != ARM_TRAJ_END) + printf_P(PSTR("err %x\r\n"), err); + } + else if (strcmp_P(res->arg1, PSTR("right")) == 0) { + arm_do_xy(&right_arm, res->arg2, res->arg3, res->arg4); + err = arm_wait_traj_end(&right_arm, ARM_TRAJ_ALL); + if (err != ARM_TRAJ_END) + printf_P(PSTR("err %x\r\n"), err); + } + else { + arm_do_xy(&left_arm, res->arg2, res->arg3, res->arg4); + arm_do_xy(&right_arm, res->arg2, res->arg3, res->arg4); + err = arm_wait_traj_end(&left_arm, ARM_TRAJ_ALL); + if (err != ARM_TRAJ_END) + printf_P(PSTR("left err %x\r\n"), err); + err = arm_wait_traj_end(&right_arm, ARM_TRAJ_ALL); + if (err != ARM_TRAJ_END) + printf_P(PSTR("right err %x\r\n"), err); + } +} + +prog_char str_arm_goto_arg0[] = "arm"; +parse_pgm_token_string_t cmd_arm_goto_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_result, arg0, str_arm_goto_arg0); +prog_char str_arm_goto_arg1[] = "left#right#both"; +parse_pgm_token_string_t cmd_arm_goto_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_result, arg1, str_arm_goto_arg1); +parse_pgm_token_num_t cmd_arm_goto_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg2, INT16); +parse_pgm_token_num_t cmd_arm_goto_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg3, INT16); +parse_pgm_token_num_t cmd_arm_goto_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg4, INT16); + +prog_char help_arm_goto[] = "Arm goto d_mm,h_mm,w_deg"; +parse_pgm_inst_t cmd_arm_goto = { + .f = cmd_arm_goto_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_goto, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_goto_arg0, + (prog_void *)&cmd_arm_goto_arg1, + (prog_void *)&cmd_arm_goto_arg2, + (prog_void *)&cmd_arm_goto_arg3, + (prog_void *)&cmd_arm_goto_arg4, + NULL, + }, +}; + +/**********************************************************/ +/* arm_goto_fixed */ + +/* this structure is filled when cmd_arm_goto_fixed is parsed successfully */ +struct cmd_arm_goto_fixed_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_arm_goto_fixed is parsed successfully */ +static void cmd_arm_goto_fixed_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_arm_goto_fixed_result *res = parsed_result; + void (*f)(uint8_t, uint8_t) = NULL; + uint8_t err, pump_num = 0; + + if (strcmp_P(res->arg2, PSTR("prepare")) == 0) + f = arm_goto_prepare_get; + else if (strcmp_P(res->arg2, PSTR("get")) == 0) + f = arm_goto_get_column; + else if (strcmp_P(res->arg2, PSTR("inter")) == 0) + f = arm_goto_intermediate_get; + else if (strcmp_P(res->arg2, PSTR("inter")) == 0) + f = arm_goto_straight; + + if (f == NULL) + return; + + /* no matter if it's left or right here */ + if (strcmp_P(res->arg3, PSTR("p1")) == 0) + pump_num = PUMP_LEFT1_NUM; + if (strcmp_P(res->arg3, PSTR("p2")) == 0) + pump_num = PUMP_LEFT2_NUM; + + /* /!\ strcmp() inverted logic do handle "both" case */ + if (strcmp_P(res->arg1, PSTR("right"))) + f(ARM_LEFT_NUM, pump_num); + if (strcmp_P(res->arg1, PSTR("left"))) + f(ARM_RIGHT_NUM, pump_num); + + if (strcmp_P(res->arg1, PSTR("right"))) { + err = arm_wait_traj_end(&left_arm, ARM_TRAJ_ALL); + if (err != ARM_TRAJ_END) + printf_P(PSTR("left err %x\r\n"), err); + } + if (strcmp_P(res->arg1, PSTR("left"))) { + err = arm_wait_traj_end(&right_arm, ARM_TRAJ_ALL); + if (err != ARM_TRAJ_END) + printf_P(PSTR("right err %x\r\n"), err); + } +} + +prog_char str_arm_goto_fixed_arg0[] = "arm"; +parse_pgm_token_string_t cmd_arm_goto_fixed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_fixed_result, arg0, str_arm_goto_fixed_arg0); +prog_char str_arm_goto_fixed_arg1[] = "left#right#both"; +parse_pgm_token_string_t cmd_arm_goto_fixed_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_fixed_result, arg1, str_arm_goto_fixed_arg1); +prog_char str_arm_goto_fixed_arg2[] = "prepare#get#inter#straight"; +parse_pgm_token_string_t cmd_arm_goto_fixed_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_fixed_result, arg2, str_arm_goto_fixed_arg2); +prog_char str_arm_goto_fixed_arg3[] = "p1#p2"; +parse_pgm_token_string_t cmd_arm_goto_fixed_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_fixed_result, arg3, str_arm_goto_fixed_arg3); + +prog_char help_arm_goto_fixed[] = "Goto fixed positions"; +parse_pgm_inst_t cmd_arm_goto_fixed = { + .f = cmd_arm_goto_fixed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_goto_fixed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_goto_fixed_arg0, + (prog_void *)&cmd_arm_goto_fixed_arg1, + (prog_void *)&cmd_arm_goto_fixed_arg2, + (prog_void *)&cmd_arm_goto_fixed_arg3, + NULL, + }, +}; + +/**********************************************************/ +/* arm_simulate */ + +/* this structure is filled when cmd_arm_simulate is parsed successfully */ +struct cmd_arm_simulate_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_arm_simulate is parsed successfully */ +static void cmd_arm_simulate_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_arm_simulate_result *res = parsed_result; + uint8_t val; + + if (strcmp_P(res->arg2, PSTR("simulate")) == 0) + val = 1; + else + val = 0; + + if (strcmp_P(res->arg1, PSTR("left")) == 0) + left_arm.config.simulate = 1; + else if (strcmp_P(res->arg1, PSTR("right")) == 0) + right_arm.config.simulate = 1; + else { + left_arm.config.simulate = 1; + right_arm.config.simulate = 1; + } +} + +prog_char str_arm_simulate_arg0[] = "arm"; +parse_pgm_token_string_t cmd_arm_simulate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_simulate_result, arg0, str_arm_simulate_arg0); +prog_char str_arm_simulate_arg1[] = "left#right#both"; +parse_pgm_token_string_t cmd_arm_simulate_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_arm_simulate_result, arg1, str_arm_simulate_arg1); +prog_char str_arm_simulate_arg2[] = "simulate#real"; +parse_pgm_token_string_t cmd_arm_simulate_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_arm_simulate_result, arg2, str_arm_simulate_arg2); + +prog_char help_arm_simulate[] = "Simulation or real for arm"; +parse_pgm_inst_t cmd_arm_simulate = { + .f = cmd_arm_simulate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_simulate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_simulate_arg0, + (prog_void *)&cmd_arm_simulate_arg1, + (prog_void *)&cmd_arm_simulate_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* finger */ + +/* this structure is filled when cmd_finger is parsed successfully */ +struct cmd_finger_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_finger is parsed successfully */ +static void cmd_finger_parsed(void *parsed_result, __attribute__((unused)) void *data) +{ + struct cmd_finger_result *res = parsed_result; + uint16_t dest = 0; + + if (strcmp_P(res->arg1, PSTR("left")) == 0) + dest = FINGER_LEFT; + else if (strcmp_P(res->arg1, PSTR("right")) == 0) + dest = FINGER_RIGHT; + else if (strcmp_P(res->arg1, PSTR("center")) == 0) + dest = FINGER_CENTER; + finger_goto(dest); +} + +prog_char str_finger_arg0[] = "finger"; +parse_pgm_token_string_t cmd_finger_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_finger_result, arg0, str_finger_arg0); +prog_char str_finger_arg1[] = "left#right#center"; +parse_pgm_token_string_t cmd_finger_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_finger_result, arg1, str_finger_arg1); + +prog_char help_finger[] = "Move finger"; +parse_pgm_inst_t cmd_finger = { + .f = cmd_finger_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_finger, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_finger_arg0, + (prog_void *)&cmd_finger_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* pump */ + +/* this structure is filled when cmd_pump is parsed successfully */ +struct cmd_pump_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_pump is parsed successfully */ +static void cmd_pump_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_pump_result *res = parsed_result; + int8_t pump_num = 0; + int16_t val = 0; + + if (strcmp_P(res->arg1, PSTR("left1")) == 0) + pump_num = PUMP_LEFT1_NUM; + else if (strcmp_P(res->arg1, PSTR("right1")) == 0) + pump_num = PUMP_RIGHT1_NUM; + else if (strcmp_P(res->arg1, PSTR("left2")) == 0) + pump_num = PUMP_LEFT2_NUM; + else if (strcmp_P(res->arg1, PSTR("right2")) == 0) + pump_num = PUMP_RIGHT2_NUM; + + if (strcmp_P(res->arg2, PSTR("on")) == 0) + val = PUMP_ON; + else if (strcmp_P(res->arg2, PSTR("off")) == 0) + val = PUMP_OFF; + else if (strcmp_P(res->arg2, PSTR("reverse")) == 0) + val = PUMP_REVERSE; + + pump_set(pump_num, val); +} + +prog_char str_pump_arg0[] = "pump"; +parse_pgm_token_string_t cmd_pump_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pump_result, arg0, str_pump_arg0); +prog_char str_pump_arg1[] = "left1#left2#right1#right2"; +parse_pgm_token_string_t cmd_pump_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pump_result, arg1, str_pump_arg1); +prog_char str_pump_arg2[] = "on#off#reverse"; +parse_pgm_token_string_t cmd_pump_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_pump_result, arg2, str_pump_arg2); + +prog_char help_pump[] = "activate pump"; +parse_pgm_inst_t cmd_pump = { + .f = cmd_pump_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pump, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pump_arg0, + (prog_void *)&cmd_pump_arg1, + (prog_void *)&cmd_pump_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* State1 */ + +/* this structure is filled when cmd_state1 is parsed successfully */ +struct cmd_state1_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_state1 is parsed successfully */ +static void cmd_state1_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_state1_result *res = parsed_result; + struct i2c_cmd_mechboard_set_mode command; + + if (!strcmp_P(res->arg1, PSTR("init"))) { + state_init(); + return; + } + + if (!strcmp_P(res->arg1, PSTR("manual"))) + command.mode = I2C_MECHBOARD_MODE_MANUAL; + else if (!strcmp_P(res->arg1, PSTR("harvest"))) + command.mode = I2C_MECHBOARD_MODE_HARVEST; + else if (!strcmp_P(res->arg1, PSTR("lazy_harvest"))) + command.mode = I2C_MECHBOARD_MODE_LAZY_HARVEST; + else if (!strcmp_P(res->arg1, PSTR("pickup"))) + command.mode = I2C_MECHBOARD_MODE_PICKUP; + else if (!strcmp_P(res->arg1, PSTR("prepare_get_lintel"))) + command.mode = I2C_MECHBOARD_MODE_PREPARE_GET_LINTEL; + else if (!strcmp_P(res->arg1, PSTR("get_lintel"))) + command.mode = I2C_MECHBOARD_MODE_GET_LINTEL; + else if (!strcmp_P(res->arg1, PSTR("put_lintel"))) + command.mode = I2C_MECHBOARD_MODE_PUT_LINTEL; + else if (!strcmp_P(res->arg1, PSTR("clear"))) + command.mode = I2C_MECHBOARD_MODE_CLEAR; + else if (!strcmp_P(res->arg1, PSTR("loaded"))) + command.mode = I2C_MECHBOARD_MODE_LOADED; + else if (!strcmp_P(res->arg1, PSTR("store"))) + command.mode = I2C_MECHBOARD_MODE_STORE; + else if (!strcmp_P(res->arg1, PSTR("lazy_pickup"))) + command.mode = I2C_MECHBOARD_MODE_LAZY_PICKUP; + state_set_mode(&command); +} + +prog_char str_state1_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_state1_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state1_result, arg0, str_state1_arg0); +prog_char str_state1_arg1[] = "init#manual#pickup#prepare_get_lintel#get_lintel#put_lintel#clear#lazy_harvest#harvest#loaded#store#lazy_pickup"; +parse_pgm_token_string_t cmd_state1_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_state1_result, arg1, str_state1_arg1); + +prog_char help_state1[] = "set mechboard mode"; +parse_pgm_inst_t cmd_state1 = { + .f = cmd_state1_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state1, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state1_arg0, + (prog_void *)&cmd_state1_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* State2 */ + +/* this structure is filled when cmd_state2 is parsed successfully */ +struct cmd_state2_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_state2 is parsed successfully */ +static void cmd_state2_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_state2_result *res = parsed_result; + struct i2c_cmd_mechboard_set_mode command; + uint8_t side; + + if (!strcmp_P(res->arg2, PSTR("left"))) + side = I2C_LEFT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("right"))) + side = I2C_RIGHT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("center"))) + side = I2C_CENTER_SIDE; + else + side = I2C_AUTO_SIDE; + + if (!strcmp_P(res->arg1, PSTR("prepare_pickup"))) { + command.mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + command.prep_pickup.side = side; + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + } + else if (!strcmp_P(res->arg1, PSTR("push_temple_disc"))) { + command.mode = I2C_MECHBOARD_MODE_PUSH_TEMPLE_DISC; + command.push_temple_disc.side = side; + } + + + state_set_mode(&command); +} + +prog_char str_state2_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_state2_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state2_result, arg0, str_state2_arg0); +prog_char str_state2_arg1[] = "prepare_pickup#push_temple_disc"; +parse_pgm_token_string_t cmd_state2_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_state2_result, arg1, str_state2_arg1); +prog_char str_state2_arg2[] = "left#right#auto#center"; +parse_pgm_token_string_t cmd_state2_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_state2_result, arg2, str_state2_arg2); + +prog_char help_state2[] = "set mechboard mode"; +parse_pgm_inst_t cmd_state2 = { + .f = cmd_state2_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state2, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state2_arg0, + (prog_void *)&cmd_state2_arg1, + (prog_void *)&cmd_state2_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* State3 */ + +/* this structure is filled when cmd_state3 is parsed successfully */ +struct cmd_state3_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t level; +}; + +/* function called when cmd_state3 is parsed successfully */ +static void cmd_state3_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_state3_result *res = parsed_result; + struct i2c_cmd_mechboard_set_mode command; + + if (!strcmp_P(res->arg1, PSTR("prepare_build"))) { + command.mode = I2C_MECHBOARD_MODE_PREPARE_BUILD; + command.prep_build.level_l = res->level; + command.prep_build.level_r = res->level; + } + else if (!strcmp_P(res->arg1, PSTR("prepare_inside"))) { + command.mode = I2C_MECHBOARD_MODE_PREPARE_INSIDE; + command.prep_inside.level_l = res->level; + command.prep_inside.level_r = res->level; + } + else if (!strcmp_P(res->arg1, PSTR("autobuild"))) { + command.mode = I2C_MECHBOARD_MODE_AUTOBUILD; + command.autobuild.level_left = res->level; + command.autobuild.level_right = res->level; + command.autobuild.count_left = 2; + command.autobuild.count_right = 2; + command.autobuild.distance_left = I2C_AUTOBUILD_DEFAULT_DIST; + command.autobuild.distance_right = I2C_AUTOBUILD_DEFAULT_DIST; + command.autobuild.do_lintel = 1; + } + else if (!strcmp_P(res->arg1, PSTR("push_temple"))) { + command.mode = I2C_MECHBOARD_MODE_PUSH_TEMPLE; + command.push_temple.level = res->level; + } + state_set_mode(&command); +} + +prog_char str_state3_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_state3_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state3_result, arg0, str_state3_arg0); +prog_char str_state3_arg1[] = "prepare_build#autobuild#prepare_inside"; +parse_pgm_token_string_t cmd_state3_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_state3_result, arg1, str_state3_arg1); +parse_pgm_token_num_t cmd_state3_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_state3_result, level, UINT8); + +prog_char help_state3[] = "set mechboard mode"; +parse_pgm_inst_t cmd_state3 = { + .f = cmd_state3_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state3, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state3_arg0, + (prog_void *)&cmd_state3_arg1, + (prog_void *)&cmd_state3_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* State4 */ + +/* this structure is filled when cmd_state4 is parsed successfully */ +struct cmd_state4_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t level_l; + uint8_t count_l; + uint8_t dist_l; + uint8_t level_r; + uint8_t count_r; + uint8_t dist_r; + uint8_t do_lintel; +}; + +/* function called when cmd_state4 is parsed successfully */ +static void cmd_state4_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_state4_result *res = parsed_result; + struct i2c_cmd_mechboard_set_mode command; + + if (!strcmp_P(res->arg1, PSTR("autobuild"))) { + command.mode = I2C_MECHBOARD_MODE_AUTOBUILD; + command.autobuild.distance_left = res->dist_l; + command.autobuild.distance_right = res->dist_r; + command.autobuild.level_left = res->level_l; + command.autobuild.level_right = res->level_r; + command.autobuild.count_left = res->count_l; + command.autobuild.count_right = res->count_r; + command.autobuild.do_lintel = res->do_lintel; + } + state_set_mode(&command); +} + +prog_char str_state4_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_state4_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state4_result, arg0, str_state4_arg0); +prog_char str_state4_arg1[] = "autobuild"; +parse_pgm_token_string_t cmd_state4_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_state4_result, arg1, str_state4_arg1); +parse_pgm_token_num_t cmd_state4_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, level_l, UINT8); +parse_pgm_token_num_t cmd_state4_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, count_l, UINT8); +parse_pgm_token_num_t cmd_state4_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, dist_l, UINT8); +parse_pgm_token_num_t cmd_state4_arg5 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, level_r, UINT8); +parse_pgm_token_num_t cmd_state4_arg6 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, count_r, UINT8); +parse_pgm_token_num_t cmd_state4_arg7 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, dist_r, UINT8); +parse_pgm_token_num_t cmd_state4_arg8 = TOKEN_NUM_INITIALIZER(struct cmd_state4_result, do_lintel, UINT8); + +prog_char help_state4[] = "set mechboard mode (autobuild level_l count_l dist_l level_r count_r dist_r lintel)"; +parse_pgm_inst_t cmd_state4 = { + .f = cmd_state4_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state4, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state4_arg0, + (prog_void *)&cmd_state4_arg1, + (prog_void *)&cmd_state4_arg2, + (prog_void *)&cmd_state4_arg3, + (prog_void *)&cmd_state4_arg4, + (prog_void *)&cmd_state4_arg5, + (prog_void *)&cmd_state4_arg6, + (prog_void *)&cmd_state4_arg7, + (prog_void *)&cmd_state4_arg8, + NULL, + }, +}; + +/**********************************************************/ +/* State5 */ + +/* this structure is filled when cmd_state5 is parsed successfully */ +struct cmd_state5_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_state5 is parsed successfully */ +static void cmd_state5_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_state5_result *res = parsed_result; + struct i2c_cmd_mechboard_set_mode command; + uint8_t side; + + if (!strcmp_P(res->arg2, PSTR("left"))) + side = I2C_LEFT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("right"))) + side = I2C_RIGHT_SIDE; + else if (!strcmp_P(res->arg2, PSTR("center"))) + side = I2C_CENTER_SIDE; + else + side = I2C_AUTO_SIDE; + + command.mode = I2C_MECHBOARD_MODE_PREPARE_PICKUP; + command.prep_pickup.side = side; + + if (!strcmp_P(res->arg3, PSTR("harvest"))) + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_HARVEST; + else if (!strcmp_P(res->arg3, PSTR("lazy_harvest"))) + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_LAZY_HARVEST; + else if (!strcmp_P(res->arg3, PSTR("pickup"))) + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_PICKUP; + else if (!strcmp_P(res->arg3, PSTR("clear"))) + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_CLEAR; + else if (!strcmp_P(res->arg3, PSTR("store"))) + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_STORE; + else if (!strcmp_P(res->arg3, PSTR("lazy_pickup"))) + command.prep_pickup.next_mode = I2C_MECHBOARD_MODE_LAZY_PICKUP; + + state_set_mode(&command); +} + +prog_char str_state5_arg0[] = "mechboard"; +parse_pgm_token_string_t cmd_state5_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state5_result, arg0, str_state5_arg0); +prog_char str_state5_arg1[] = "prepare_pickup"; +parse_pgm_token_string_t cmd_state5_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_state5_result, arg1, str_state5_arg1); +prog_char str_state5_arg2[] = "left#right#auto#center"; +parse_pgm_token_string_t cmd_state5_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_state5_result, arg2, str_state5_arg2); +prog_char str_state5_arg3[] = "harvest#pickup#store#lazy_harvest#lazy_pickup#clear"; +parse_pgm_token_string_t cmd_state5_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_state5_result, arg3, str_state5_arg3); + +prog_char help_state5[] = "set mechboard mode 2"; +parse_pgm_inst_t cmd_state5 = { + .f = cmd_state5_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state5, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state5_arg0, + (prog_void *)&cmd_state5_arg1, + (prog_void *)&cmd_state5_arg2, + (prog_void *)&cmd_state5_arg3, + NULL, + }, +}; + +/**********************************************************/ +/* State_Machine */ + +/* this structure is filled when cmd_state_machine is parsed successfully */ +struct cmd_state_machine_result { + fixed_string_t arg0; +}; + +/* function called when cmd_state_machine is parsed successfully */ +static void cmd_state_machine_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + state_machine(); +} + +prog_char str_state_machine_arg0[] = "state_machine"; +parse_pgm_token_string_t cmd_state_machine_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state_machine_result, arg0, str_state_machine_arg0); + +prog_char help_state_machine[] = "launch state machine"; +parse_pgm_inst_t cmd_state_machine = { + .f = cmd_state_machine_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state_machine, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state_machine_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* State_Debug */ + +/* this structure is filled when cmd_state_debug is parsed successfully */ +struct cmd_state_debug_result { + fixed_string_t arg0; + uint8_t on; +}; + +/* function called when cmd_state_debug is parsed successfully */ +static void cmd_state_debug_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_state_debug_result *res = parsed_result; + state_debug = res->on; +} + +prog_char str_state_debug_arg0[] = "state_debug"; +parse_pgm_token_string_t cmd_state_debug_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_state_debug_result, arg0, str_state_debug_arg0); +parse_pgm_token_num_t cmd_state_debug_on = TOKEN_NUM_INITIALIZER(struct cmd_state_debug_result, on, UINT8); + +prog_char help_state_debug[] = "Set debug timer for state machine"; +parse_pgm_inst_t cmd_state_debug = { + .f = cmd_state_debug_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_state_debug, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_state_debug_arg0, + (prog_void *)&cmd_state_debug_on, + NULL, + }, +}; + +/**********************************************************/ +/* Servo_Lintel */ + +/* this structure is filled when cmd_servo_lintel is parsed successfully */ +struct cmd_servo_lintel_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_servo_lintel is parsed successfully */ +static void cmd_servo_lintel_parsed(void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_servo_lintel_result *res = parsed_result; + if (!strcmp_P(res->arg1, PSTR("out"))) + servo_lintel_out(); + else if (!strcmp_P(res->arg1, PSTR("1lin"))) + servo_lintel_1lin(); + else if (!strcmp_P(res->arg1, PSTR("2lin"))) + servo_lintel_2lin(); + +} + +prog_char str_servo_lintel_arg0[] = "servo_lintel"; +parse_pgm_token_string_t cmd_servo_lintel_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_servo_lintel_result, arg0, str_servo_lintel_arg0); +prog_char str_servo_lintel_arg1[] = "out#1lin#2lin"; +parse_pgm_token_string_t cmd_servo_lintel_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_servo_lintel_result, arg1, str_servo_lintel_arg1); + +prog_char help_servo_lintel[] = "Servo_Lintel function"; +parse_pgm_inst_t cmd_servo_lintel = { + .f = cmd_servo_lintel_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_servo_lintel, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_servo_lintel_arg0, + (prog_void *)&cmd_servo_lintel_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pump_Current */ + +/* this structure is filled when cmd_pump_current is parsed successfully */ +struct cmd_pump_current_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_pump_current is parsed successfully */ +static void cmd_pump_current_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + printf_P(PSTR("l1=%d l2=%d r1=%d r2=%d\r\n"), + mechboard.pump_left1_current, mechboard.pump_left2_current, + sensor_get_adc(ADC_CSENSE3), sensor_get_adc(ADC_CSENSE4)); +} + +prog_char str_pump_current_arg0[] = "pump_current"; +parse_pgm_token_string_t cmd_pump_current_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pump_current_result, arg0, str_pump_current_arg0); +prog_char str_pump_current_arg1[] = "show"; +parse_pgm_token_string_t cmd_pump_current_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pump_current_result, arg1, str_pump_current_arg1); + +prog_char help_pump_current[] = "dump pump current"; +parse_pgm_inst_t cmd_pump_current = { + .f = cmd_pump_current_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pump_current, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pump_current_arg0, + (prog_void *)&cmd_pump_current_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Manivelle */ + +/* this structure is filled when cmd_manivelle is parsed successfully */ +struct cmd_manivelle_result { + fixed_string_t arg0; + uint8_t step; +}; + +/* function called when cmd_manivelle is parsed successfully */ +static void cmd_manivelle_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ + struct cmd_manivelle_result *res = parsed_result; + state_manivelle(res->step); +} + +prog_char str_manivelle_arg0[] = "manivelle"; +parse_pgm_token_string_t cmd_manivelle_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_manivelle_result, arg0, str_manivelle_arg0); +parse_pgm_token_num_t cmd_manivelle_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_manivelle_result, step, UINT8); + +prog_char help_manivelle[] = "Manivelle function"; +parse_pgm_inst_t cmd_manivelle = { + .f = cmd_manivelle_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_manivelle, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_manivelle_arg0, + (prog_void *)&cmd_manivelle_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Test */ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_test is parsed successfully */ +static void cmd_test_parsed(__attribute__((unused)) void *parsed_result, + __attribute__((unused)) void *data) +{ +} + +prog_char str_test_arg0[] = "test"; +parse_pgm_token_string_t cmd_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_test_result, arg0, str_test_arg0); + +prog_char help_test[] = "Test function"; +parse_pgm_inst_t cmd_test = { + .f = cmd_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_test_arg0, + NULL, + }, +}; diff --git a/projects/microb2009/mechboard/cs.c b/projects/microb2009/mechboard/cs.c new file mode 100644 index 0000000..29a2cab --- /dev/null +++ b/projects/microb2009/mechboard/cs.c @@ -0,0 +1,163 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cs.c,v 1.4 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> +#include <adc.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "main.h" +#include "actuator.h" + +/* called every 5 ms */ +static void do_cs(__attribute__((unused)) void *dummy) +{ + /* read encoders */ + if (mechboard.flags & DO_ENCODERS) { + encoders_spi_manage(NULL); + } + /* control system */ + if (mechboard.flags & DO_CS) { + if (mechboard.left_arm.on) + cs_manage(&mechboard.left_arm.cs); + if (mechboard.right_arm.on) + cs_manage(&mechboard.right_arm.cs); + } + if (mechboard.flags & DO_BD) { + bd_manage_from_cs(&mechboard.left_arm.bd, &mechboard.left_arm.cs); + bd_manage_from_cs(&mechboard.right_arm.bd, &mechboard.right_arm.cs); + } + if (mechboard.flags & DO_POWER) + BRAKE_OFF(); + else + BRAKE_ON(); +} + +void dump_cs_debug(const char *name, struct cs *cs) +{ + DEBUG(E_USER_CS, "%s cons=% .5ld fcons=% .5ld err=% .5ld " + "in=% .5ld out=% .5ld", + name, cs_get_consign(cs), cs_get_filtered_consign(cs), + cs_get_error(cs), cs_get_filtered_feedback(cs), + cs_get_out(cs)); +} + +void dump_cs(const char *name, struct cs *cs) +{ + printf_P(PSTR("%s cons=% .5ld fcons=% .5ld err=% .5ld " + "in=% .5ld out=% .5ld\r\n"), + name, cs_get_consign(cs), cs_get_filtered_consign(cs), + cs_get_error(cs), cs_get_filtered_feedback(cs), + cs_get_out(cs)); +} + +void dump_pid(const char *name, struct pid_filter *pid) +{ + printf_P(PSTR("%s P=% .8ld I=% .8ld D=% .8ld out=% .8ld\r\n"), + name, + pid_get_value_in(pid) * pid_get_gain_P(pid), + pid_get_value_I(pid) * pid_get_gain_I(pid), + pid_get_value_D(pid) * pid_get_gain_D(pid), + pid_get_value_out(pid)); +} + +void microb_cs_init(void) +{ + /* ---- CS left_arm */ + /* PID */ + pid_init(&mechboard.left_arm.pid); + pid_set_gains(&mechboard.left_arm.pid, 500, 40, 5000); + pid_set_maximums(&mechboard.left_arm.pid, 0, 5000, 2400); /* max is 12 V */ + pid_set_out_shift(&mechboard.left_arm.pid, 10); + pid_set_derivate_filter(&mechboard.left_arm.pid, 4); + + /* QUADRAMP */ + quadramp_init(&mechboard.left_arm.qr); + quadramp_set_1st_order_vars(&mechboard.left_arm.qr, 2000, 2000); /* set speed */ + quadramp_set_2nd_order_vars(&mechboard.left_arm.qr, 20, 20); /* set accel */ + + /* CS */ + cs_init(&mechboard.left_arm.cs); + cs_set_consign_filter(&mechboard.left_arm.cs, quadramp_do_filter, &mechboard.left_arm.qr); + cs_set_correct_filter(&mechboard.left_arm.cs, pid_do_filter, &mechboard.left_arm.pid); + cs_set_process_in(&mechboard.left_arm.cs, pwm_ng_set, LEFT_ARM_PWM); + cs_set_process_out(&mechboard.left_arm.cs, encoders_spi_get_value, LEFT_ARM_ENCODER); + cs_set_consign(&mechboard.left_arm.cs, 0); + + /* Blocking detection */ + bd_init(&mechboard.left_arm.bd); + bd_set_speed_threshold(&mechboard.left_arm.bd, 150); + bd_set_current_thresholds(&mechboard.left_arm.bd, 500, 8000, 1000000, 40); + + /* ---- CS right_arm */ + /* PID */ + pid_init(&mechboard.right_arm.pid); + pid_set_gains(&mechboard.right_arm.pid, 500, 40, 5000); + pid_set_maximums(&mechboard.right_arm.pid, 0, 5000, 2400); /* max is 12 V */ + pid_set_out_shift(&mechboard.right_arm.pid, 10); + pid_set_derivate_filter(&mechboard.right_arm.pid, 6); + + /* QUADRAMP */ + quadramp_init(&mechboard.right_arm.qr); + quadramp_set_1st_order_vars(&mechboard.right_arm.qr, 1000, 1000); /* set speed */ + quadramp_set_2nd_order_vars(&mechboard.right_arm.qr, 20, 20); /* set accel */ + + /* CS */ + cs_init(&mechboard.right_arm.cs); + cs_set_consign_filter(&mechboard.right_arm.cs, quadramp_do_filter, &mechboard.right_arm.qr); + cs_set_correct_filter(&mechboard.right_arm.cs, pid_do_filter, &mechboard.right_arm.pid); + cs_set_process_in(&mechboard.right_arm.cs, pwm_ng_set, RIGHT_ARM_PWM); + cs_set_process_out(&mechboard.right_arm.cs, encoders_spi_get_value, RIGHT_ARM_ENCODER); + cs_set_consign(&mechboard.right_arm.cs, 0); + + /* Blocking detection */ + bd_init(&mechboard.right_arm.bd); + bd_set_speed_threshold(&mechboard.right_arm.bd, 150); + bd_set_current_thresholds(&mechboard.right_arm.bd, 500, 8000, 1000000, 40); + + /* set them on !! */ + mechboard.left_arm.on = 1; + mechboard.right_arm.on = 1; + + + scheduler_add_periodical_event_priority(do_cs, NULL, + CS_PERIOD / SCHEDULER_UNIT, + CS_PRIO); +} diff --git a/projects/microb2009/mechboard/cs.h b/projects/microb2009/mechboard/cs.h new file mode 100644 index 0000000..5b3be83 --- /dev/null +++ b/projects/microb2009/mechboard/cs.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cs.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ + +void microb_cs_init(void); +void dump_cs(const char *name, struct cs *cs); +void dump_pid(const char *name, struct pid_filter *pid); diff --git a/projects/microb2009/mechboard/diagnostic_config.h b/projects/microb2009/mechboard/diagnostic_config.h new file mode 100644 index 0000000..7302bfa --- /dev/null +++ b/projects/microb2009/mechboard/diagnostic_config.h @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +/* undefine it to disable this functionnality */ +#define INTERRUPT_SHOW_PORT PORTA +#define INTERRUPT_SHOW_BIT 3 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#define DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/projects/microb2009/mechboard/encoders_spi_config.h b/projects/microb2009/mechboard/encoders_spi_config.h new file mode 100644 index 0000000..e71e662 --- /dev/null +++ b/projects/microb2009/mechboard/encoders_spi_config.h @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_spi_config.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ +#ifndef _ENCODERS_SPI_CONFIG_H_ +#define _ENCODERS_SPI_CONFIG_H_ + +#define ENCODERS_SPI_NUMBER 4 +#define ENCODERS_SPI_SS_PORT SS_PORT /* PORTB on atmega2560 */ +#define ENCODERS_SPI_SS_BIT SS_BIT /* 0 on atmega2560 */ + +/* see spi configuration */ +#define ENCODERS_SPI_CLK_RATE SPI_CLK_RATE_16 +#define ENCODERS_SPI_FORMAT SPI_FORMAT_3 +#define ENCODERS_SPI_DATA_ORDER SPI_LSB_FIRST + +#endif diff --git a/projects/microb2009/mechboard/error_config.h b/projects/microb2009/mechboard/error_config.h new file mode 100644 index 0000000..2df45d0 --- /dev/null +++ b/projects/microb2009/mechboard/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/mechboard/i2c_config.h b/projects/microb2009/mechboard/i2c_config.h new file mode 100644 index 0000000..93ce0ec --- /dev/null +++ b/projects/microb2009/mechboard/i2c_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ + + +#define I2C_BITRATE 1 // divider dor i2c baudrate, see TWBR in doc +#define I2C_PRESCALER 3 // prescaler config, rate = 2^(n*2) + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 32 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 32 diff --git a/projects/microb2009/mechboard/i2c_protocol.c b/projects/microb2009/mechboard/i2c_protocol.c new file mode 100644 index 0000000..902207b --- /dev/null +++ b/projects/microb2009/mechboard/i2c_protocol.c @@ -0,0 +1,211 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.c,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#include <string.h> + +#include <aversive.h> +#include <aversive/list.h> +#include <aversive/error.h> + +#include <i2c.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "sensor.h" +#include "state.h" + +void i2c_protocol_init(void) +{ +} + +/*** LED CONTROL ***/ +void i2c_led_control(uint8_t l, uint8_t state) +{ + switch(l) { + case 1: + state? LED1_ON():LED1_OFF(); + break; + case 2: + state? LED2_ON():LED2_OFF(); + break; + case 3: + state? LED3_ON():LED3_OFF(); + break; + case 4: + state? LED4_ON():LED4_OFF(); + break; + default: + break; + } +} + +#ifdef notyet +static void i2c_test(uint16_t val) +{ + static uint16_t prev=0; + + if ( (val-prev) != 1 ) { + WARNING(E_USER_I2C_PROTO, "Dupplicated msg %d", val); + } + prev = val; + ext.nb_test_cmd ++; +} +#endif + +static void i2c_send_status(void) +{ + struct i2c_ans_mechboard_status ans; + i2c_flush(); + ans.hdr.cmd = I2C_ANS_MECHBOARD_STATUS; + + /* status */ + ans.mode = state_get_mode(); + ans.status = mechboard.status; + + ans.lintel_count = mechboard.lintel_count; + ans.column_flags = mechboard.column_flags; + /* pumps pwm */ + ans.pump_left1 = mechboard.pump_left1; + ans.pump_right1 = mechboard.pump_right1; + ans.pump_left2 = mechboard.pump_left2; + ans.pump_right2 = mechboard.pump_right2; + /* pumps current */ + ans.pump_right1_current = sensor_get_adc(ADC_CSENSE3); + ans.pump_right2_current = sensor_get_adc(ADC_CSENSE4); + /* servos */ + ans.servo_lintel_left = mechboard.servo_lintel_left; + ans.servo_lintel_right = mechboard.servo_lintel_right; + + i2c_send(I2C_ADD_MASTER, (uint8_t *) &ans, + sizeof(ans), I2C_CTRL_GENERIC); +} + +static int8_t i2c_set_mode(struct i2c_cmd_mechboard_set_mode *cmd) +{ + state_set_mode(cmd); + return 0; +} + +void i2c_recvevent(uint8_t * buf, int8_t size) +{ + void *void_cmd = buf; + + static uint8_t a = 0; + + a++; + if (a & 0x10) + LED2_TOGGLE(); + + if (size <= 0) { + goto error; + } + + switch (buf[0]) { + + /* Commands (no answer needed) */ + case I2C_CMD_GENERIC_LED_CONTROL: + { + struct i2c_cmd_led_control *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + i2c_led_control(cmd->led_num, cmd->state); + break; + } + + case I2C_CMD_MECHBOARD_SET_MODE: + { + struct i2c_cmd_mechboard_set_mode *cmd = void_cmd; + if (size != sizeof(struct i2c_cmd_mechboard_set_mode)) + goto error; + i2c_set_mode(cmd); + break; + } + + case I2C_CMD_GENERIC_SET_COLOR: + { + struct i2c_cmd_generic_color *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + mechboard.our_color = cmd->color; + break; + } + +#ifdef notyet + case I2C_CMD_EXTENSION_TEST: + { + struct i2c_cmd_extension_test *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + i2c_test(cmd->val); + break; + } +#endif + + /* Add other commands here ...*/ + + + case I2C_REQ_MECHBOARD_STATUS: + { + struct i2c_req_mechboard_status *cmd = void_cmd; + if (size != sizeof (struct i2c_req_mechboard_status)) + goto error; + + mechboard.pump_left1_current = cmd->pump_left1_current; + mechboard.pump_left2_current = cmd->pump_left2_current; + i2c_send_status(); + break; + } + + default: + goto error; + } + + error: + /* log error on a led ? */ + return; +} + +void i2c_recvbyteevent(__attribute__((unused)) uint8_t hwstatus, + __attribute__((unused)) uint8_t i, + __attribute__((unused)) int8_t c) +{ +} + +void i2c_sendevent(__attribute__((unused)) int8_t size) +{ +} + + diff --git a/projects/microb2009/mechboard/i2c_protocol.h b/projects/microb2009/mechboard/i2c_protocol.h new file mode 100644 index 0000000..7f022ef --- /dev/null +++ b/projects/microb2009/mechboard/i2c_protocol.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ + +#include <aversive.h> + +void i2c_protocol_init(void); + +void i2c_recvevent(uint8_t * buf, int8_t size); +void i2c_recvbyteevent(uint8_t hwstatus, uint8_t i, uint8_t c); +void i2c_sendevent(int8_t size); + +int debug_send(char c, FILE* f); diff --git a/projects/microb2009/mechboard/main.c b/projects/microb2009/mechboard/main.c new file mode 100755 index 0000000..27c0138 --- /dev/null +++ b/projects/microb2009/mechboard/main.c @@ -0,0 +1,269 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> +#include <avr/eeprom.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <i2c.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> +#include <adc.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "../common/eeprom_mapping.h" +#include "../common/i2c_commands.h" + +#include "main.h" +#include "ax12_user.h" +#include "cmdline.h" +#include "sensor.h" +#include "state.h" +#include "actuator.h" +#include "arm_xy.h" +#include "cs.h" +#include "i2c_protocol.h" + +/* 0 means "programmed" + * ---- with 16 Mhz quartz + * CKSEL 3-0 : 0111 + * SUT 1-0 : 10 + * CKDIV8 : 1 + * ---- bootloader + * BOOTZ 1-0 : 01 (4K bootloader) + * BOOTRST : 0 (reset on bootloader) + * ---- jtag + * jtagen : 0 + */ + +struct genboard gen; +struct mechboard mechboard; + +/***********************/ + +void bootloader(void) +{ +#define BOOTLOADER_ADDR 0x3f000 + if (pgm_read_byte_far(BOOTLOADER_ADDR) == 0xff) { + printf_P(PSTR("Bootloader is not present\r\n")); + return; + } + cli(); + BRAKE_ON(); + /* ... very specific :( */ + TIMSK0 = 0; + TIMSK1 = 0; + TIMSK2 = 0; + TIMSK3 = 0; + TIMSK4 = 0; + TIMSK5 = 0; + EIMSK = 0; + UCSR0B = 0; + UCSR1B = 0; + UCSR2B = 0; + UCSR3B = 0; + SPCR = 0; + TWCR = 0; + ACSR = 0; + ADCSRA = 0; + + EIND = 1; + __asm__ __volatile__ ("ldi r31,0xf8\n"); + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("eijmp\n"); + + /* never returns */ +} + +void do_led_blink(__attribute__((unused)) void *dummy) +{ +#if 1 /* simple blink */ + static uint8_t a=0; + + if(a) + LED1_ON(); + else + LED1_OFF(); + + a = !a; +#endif +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + cpt++; + sei(); + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +int main(void) +{ + /* brake */ + BRAKE_ON(); + BRAKE_DDR(); + + /* CPLD reset on PG3 */ + DDRG |= 1<<3; + PORTG &= ~(1<<3); /* implicit */ + + /* LEDS */ + DDRJ |= 0x0c; + DDRL = 0xc0; + LED1_OFF(); + memset(&gen, 0, sizeof(gen)); + memset(&mechboard, 0, sizeof(mechboard)); + /* cs is enabled after arm_calibrate() */ + mechboard.flags = DO_ENCODERS | DO_POWER; // DO_BD + + /* UART */ + uart_init(); +#if CMDLINE_UART == 3 + fdevopen(uart3_dev_send, uart3_dev_recv); + uart_register_rx_event(3, emergency); +#elif CMDLINE_UART == 1 + fdevopen(uart1_dev_send, uart1_dev_recv); + uart_register_rx_event(1, emergency); +#else +# error not supported +#endif + + //eeprom_write_byte(EEPROM_MAGIC_ADDRESS, EEPROM_MAGIC_MECHBOARD); + /* check eeprom to avoid to run the bad program */ + if (eeprom_read_byte(EEPROM_MAGIC_ADDRESS) != + EEPROM_MAGIC_MECHBOARD) { + sei(); + printf_P(PSTR("Bad eeprom value\r\n")); + while(1); + } + + /* LOGS */ + error_register_emerg(mylog); + error_register_error(mylog); + error_register_warning(mylog); + error_register_notice(mylog); + error_register_debug(mylog); + + /* SPI + ENCODERS */ + encoders_spi_init(); /* this will also init spi hardware */ + + /* I2C */ + i2c_protocol_init(); + i2c_init(I2C_MODE_SLAVE, I2C_MECHBOARD_ADDR); + i2c_register_recv_event(i2c_recvevent); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* PWM */ + PWM_NG_TIMER_16BITS_INIT(1, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_1); + PWM_NG_TIMER_16BITS_INIT(4, TIMER_16_MODE_PWM_10, + TIMER4_PRESCALER_DIV_1); + + PWM_NG_INIT16(&gen.pwm1_4A, 4, A, 10, PWM_NG_MODE_SIGNED, + &PORTD, 4); + PWM_NG_INIT16(&gen.pwm2_4B, 4, B, 10, PWM_NG_MODE_SIGNED, + &PORTD, 5); + PWM_NG_INIT16(&gen.pwm3_1A, 1, A, 10, PWM_NG_MODE_SIGNED | + PWM_NG_MODE_SIGN_INVERTED, + &PORTD, 6); + PWM_NG_INIT16(&gen.pwm4_1B, 1, B, 10, PWM_NG_MODE_SIGNED | + PWM_NG_MODE_SIGN_INVERTED, + &PORTD, 7); + + + /* servos */ + PWM_NG_TIMER_16BITS_INIT(3, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&gen.servo1, 3, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_TIMER_16BITS_INIT(5, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&gen.servo2, 5, A, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&gen.servo3, 5, B, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&gen.servo4, 5, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + + /* SCHEDULER */ + scheduler_init(); + + scheduler_add_periodical_event_priority(do_led_blink, NULL, + 100000L / SCHEDULER_UNIT, + LED_PRIO); + /* all cs management */ + microb_cs_init(); + + /* sensors, will also init hardware adc */ + sensor_init(); + + /* TIME */ + time_init(TIME_PRIO); + + /* ax12 */ + ax12_user_init(); + + sei(); + + /* finger + other actuators */ + actuator_init(); + + state_init(); + + printf_P(PSTR("\r\n")); + printf_P(PSTR("Dass das Gluck deinen Haus setzt.\r\n")); + + /* arm management */ + gen.logs[0] = E_USER_ST_MACH; + gen.log_level = 5; + arm_init(); + mechboard.flags |= DO_CS; + arm_do_xy(&left_arm, 60, -80, 0); + arm_do_xy(&right_arm, 60, -80, 0); + + state_machine(); + cmdline_interact(); + + return 0; +} diff --git a/projects/microb2009/mechboard/main.h b/projects/microb2009/mechboard/main.h new file mode 100755 index 0000000..5422f6c --- /dev/null +++ b/projects/microb2009/mechboard/main.h @@ -0,0 +1,174 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.h,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#define LED_TOGGLE(port, bit) do { \ + if (port & _BV(bit)) \ + port &= ~_BV(bit); \ + else \ + port |= _BV(bit); \ + } while(0) + +#define LED1_ON() sbi(PORTJ, 2) +#define LED1_OFF() cbi(PORTJ, 2) +#define LED1_TOGGLE() LED_TOGGLE(PORTJ, 2) + +#define LED2_ON() sbi(PORTL, 7) +#define LED2_OFF() cbi(PORTL, 7) +#define LED2_TOGGLE() LED_TOGGLE(PORTL, 7) + +#define LED3_ON() sbi(PORTJ, 3) +#define LED3_OFF() cbi(PORTJ, 3) +#define LED3_TOGGLE() LED_TOGGLE(PORTJ, 3) + +#define LED4_ON() sbi(PORTL, 6) +#define LED4_OFF() cbi(PORTL, 6) +#define LED4_TOGGLE() LED_TOGGLE(PORTL, 6) + +#define BRAKE_DDR() do { DDRJ |= 0xF0; } while(0) +#define BRAKE_ON() do { PORTJ |= 0xF0; } while(0) +#define BRAKE_OFF() do { PORTJ &= 0x0F; } while(0) + +#define LEFT_ARM_ENCODER ((void *)0) +#define RIGHT_ARM_ENCODER ((void *)1) + +#define LEFT_ARM_PWM ((void *)&gen.pwm1_4A) +#define RIGHT_ARM_PWM ((void *)&gen.pwm2_4B) + +#define RIGHT_PUMP1_PWM ((void *)&gen.pwm3_1A) +#define RIGHT_PUMP2_PWM ((void *)&gen.pwm4_1B) + +#define R_ELBOW_AX12 1 +#define R_WRIST_AX12 2 +#define L_ELBOW_AX12 4 +#define L_WRIST_AX12 3 +#define FINGER_AX12 5 + +/** ERROR NUMS */ +#define E_USER_I2C_PROTO 195 +#define E_USER_SENSOR 196 +#define E_USER_ARM 197 +#define E_USER_FINGER 198 +#define E_USER_ST_MACH 199 +#define E_USER_CS 200 +#define E_USER_AX12 201 + +#define LED_PRIO 170 +#define TIME_PRIO 160 +#define ADC_PRIO 120 +#define CS_PRIO 100 +#define ARM_PRIO 50 +#define I2C_POLL_PRIO 20 + +#define CS_PERIOD 5000L + +#define NB_LOGS 4 + +/* generic to all boards */ +struct genboard { + /* command line interface */ + struct rdline rdl; + char prompt[RDLINE_PROMPT_SIZE]; + + /* motors */ + struct pwm_ng pwm1_4A; + struct pwm_ng pwm2_4B; + struct pwm_ng pwm3_1A; + struct pwm_ng pwm4_1B; + + /* servos */ + struct pwm_ng servo1; + struct pwm_ng servo2; + struct pwm_ng servo3; + struct pwm_ng servo4; + + /* ax12 interface */ + AX12 ax12; + + /* log */ + uint8_t logs[NB_LOGS+1]; + uint8_t log_level; + uint8_t debug; +}; + +struct cs_block { + uint8_t on; + struct cs cs; + struct pid_filter pid; + struct quadramp_filter qr; + struct blocking_detection bd; +}; + +/* mechboard specific */ +struct mechboard { +#define DO_ENCODERS 1 +#define DO_CS 2 +#define DO_BD 4 +#define DO_POWER 8 + uint8_t flags; /* misc flags */ + + /* control systems */ + struct cs_block left_arm; + struct cs_block right_arm; + + /* robot status */ + uint8_t our_color; + volatile uint8_t lintel_count; + volatile uint8_t column_flags; + volatile uint8_t status; + + /* local pumps */ + int16_t pump_right1; + int16_t pump_right2; + /* remote pump (on mainboard) */ + int16_t pump_left1; + int16_t pump_left2; + + /* remote pump current */ + int16_t pump_left1_current; + int16_t pump_left2_current; + + uint16_t servo_lintel_left; + uint16_t servo_lintel_right; + +}; + +extern struct genboard gen; +extern struct mechboard mechboard; + +/* start the bootloader */ +void bootloader(void); + +#define DEG(x) (((double)(x)) * (180.0 / M_PI)) +#define RAD(x) (((double)(x)) * (M_PI / 180.0)) +#define M_2PI (2*M_PI) + +#define WAIT_COND_OR_TIMEOUT(cond, timeout) \ +({ \ + microseconds __us = time_get_us2(); \ + uint8_t __ret = 1; \ + while(! (cond)) { \ + if (time_get_us2() - __us > (timeout)*1000L) {\ + __ret = 0; \ + break; \ + } \ + } \ + __ret; \ +}) diff --git a/projects/microb2009/mechboard/pid_config.h b/projects/microb2009/mechboard/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/projects/microb2009/mechboard/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/projects/microb2009/mechboard/rdline_config.h b/projects/microb2009/mechboard/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/mechboard/scheduler_config.h b/projects/microb2009/mechboard/scheduler_config.h new file mode 100755 index 0000000..98690be --- /dev/null +++ b/projects/microb2009/mechboard/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.2 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 9 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/microb2009/mechboard/sensor.c b/projects/microb2009/mechboard/sensor.c new file mode 100644 index 0000000..a80201f --- /dev/null +++ b/projects/microb2009/mechboard/sensor.c @@ -0,0 +1,254 @@ +/* + * Copyright Droids Corporation (2009) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: sensor.c,v 1.6 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#include <stdlib.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <adc.h> +#include <scheduler.h> +#include <ax12.h> +#include <pwm_ng.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "main.h" +#include "sensor.h" + +/************ ADC */ + +struct adc_infos { + uint16_t config; + int16_t value; + int16_t prev_val; + int16_t (*filter)(struct adc_infos *, int16_t); +}; + +/* reach 90% of the value in 4 samples */ +int16_t rii_light(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + (int32_t)adc->prev_val / 2; + return adc->prev_val / 2; +} + +/* reach 90% of the value in 8 samples */ +int16_t rii_medium(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + ((int32_t)adc->prev_val * 3) / 4; + return adc->prev_val / 4; +} + +/* reach 90% of the value in 16 samples */ +int16_t rii_strong(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + ((int32_t)adc->prev_val * 7) / 8; + return adc->prev_val / 8; +} + + +#define ADC_CONF(x) ( ADC_REF_AVCC | ADC_MODE_INT | MUX_ADC##x ) + +/* define which ADC to poll, see in sensor.h */ +static struct adc_infos adc_infos[ADC_MAX] = { + [ADC_CSENSE1] = { .config = ADC_CONF(0), .filter = rii_medium }, + [ADC_CSENSE2] = { .config = ADC_CONF(1), .filter = rii_medium }, + [ADC_CSENSE3] = { .config = ADC_CONF(2), .filter = rii_medium }, + [ADC_CSENSE4] = { .config = ADC_CONF(3), .filter = rii_medium }, + + /* add adc on "cap" pins if needed */ +/* [ADC_CAP1] = { .config = ADC_CONF(10) }, */ +/* [ADC_CAP2] = { .config = ADC_CONF(11) }, */ +/* [ADC_CAP3] = { .config = ADC_CONF(12) }, */ +/* [ADC_CAP4] = { .config = ADC_CONF(13) }, */ +}; + +static void adc_event(int16_t result); + +/* called every 10 ms, see init below */ +static void do_adc(__attribute__((unused)) void *dummy) +{ + /* launch first conversion */ + adc_launch(adc_infos[0].config); +} + +static void adc_event(int16_t result) +{ + static uint8_t i = 0; + + /* filter value if needed */ + if (adc_infos[i].filter) + adc_infos[i].value = adc_infos[i].filter(&adc_infos[i], + result); + else + adc_infos[i].value = result; + + i ++; + if (i >= ADC_MAX) + i = 0; + else + adc_launch(adc_infos[i].config); +} + +int16_t sensor_get_adc(uint8_t i) +{ + int16_t tmp; + uint8_t flags; + + IRQ_LOCK(flags); + tmp = adc_infos[i].value; + IRQ_UNLOCK(flags); + return tmp; +} + +/************ boolean sensors */ + + +struct sensor_filter { + uint8_t filter; + uint8_t prev; + uint8_t thres_off; + uint8_t thres_on; + uint8_t cpt; + uint8_t invert; +}; + +/* pullup mapping: + * CAP 1,5,6,7,8 + */ +static struct sensor_filter sensor_filter[SENSOR_MAX] = { + [S_CAP1] = { 10, 0, 3, 7, 0, 0 }, /* 0 */ + [S_FRONT] = { 5, 0, 4, 1, 0, 0 }, /* 1 */ + [S_CAP3] = { 10, 0, 3, 7, 0, 0 }, /* 2 */ + [S_CAP4] = { 1, 0, 0, 1, 0, 0 }, /* 3 */ + [S_COL_LEFT] = { 5, 0, 4, 1, 0, 1 }, /* 4 */ + [S_LEFT] = { 5, 0, 4, 1, 0, 1 }, /* 5 */ + [S_RIGHT] = { 5, 0, 4, 1, 0, 1 }, /* 6 */ + [S_COL_RIGHT] = { 5, 0, 4, 1, 0, 1 }, /* 7 */ + [S_RESERVED1] = { 10, 0, 3, 7, 0, 0 }, /* 8 */ + [S_RESERVED2] = { 10, 0, 3, 7, 0, 0 }, /* 9 */ + [S_RESERVED3] = { 1, 0, 0, 1, 0, 0 }, /* 10 */ + [S_RESERVED4] = { 1, 0, 0, 1, 0, 0 }, /* 11 */ + [S_RESERVED5] = { 1, 0, 0, 1, 0, 0 }, /* 12 */ + [S_RESERVED6] = { 1, 0, 0, 1, 0, 0 }, /* 13 */ + [S_RESERVED7] = { 1, 0, 0, 1, 0, 0 }, /* 14 */ + [S_RESERVED8] = { 1, 0, 0, 1, 0, 0 }, /* 15 */ +}; + +/* value of filtered sensors */ +static uint16_t sensor_filtered = 0; + +/* sensor mapping : + * 0-3: PORTK 2->5 (cap1 -> cap4) (adc10 -> adc13) + * 4-5: PORTL 0->1 (cap5 -> cap6) + * 6-7: PORTE 3->4 (cap7 -> cap8) + * 8-15: reserved + */ + +uint16_t sensor_get_all(void) +{ + uint16_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = sensor_filtered; + IRQ_UNLOCK(flags); + return tmp; +} + +uint8_t sensor_get(uint8_t i) +{ + uint16_t tmp = sensor_get_all(); + return !!(tmp & _BV(i)); +} + +/* get the physical value of pins */ +static uint16_t sensor_read(void) +{ + uint16_t tmp = 0; + tmp |= (uint16_t)((PINK & (_BV(2)|_BV(3)|_BV(4)|_BV(5))) >> 2) << 0; + tmp |= (uint16_t)((PINL & (_BV(0)|_BV(1))) >> 0) << 4; + tmp |= (uint16_t)((PINE & (_BV(3)|_BV(4))) >> 3) << 6; + /* add reserved sensors here */ + return tmp; +} + +/* called every 10 ms, see init below */ +static void do_boolean_sensors(__attribute__((unused)) void *dummy) +{ + uint8_t i; + uint8_t flags; + uint16_t sensor = sensor_read(); + uint16_t tmp = 0; + + for (i=0; i<SENSOR_MAX; i++) { + if ((1 << i) & sensor) { + if (sensor_filter[i].cpt < sensor_filter[i].filter) + sensor_filter[i].cpt++; + if (sensor_filter[i].cpt >= sensor_filter[i].thres_on) + sensor_filter[i].prev = 1; + } + else { + if (sensor_filter[i].cpt > 0) + sensor_filter[i].cpt--; + if (sensor_filter[i].cpt <= sensor_filter[i].thres_off) + sensor_filter[i].prev = 0; + } + + if (sensor_filter[i].prev && !sensor_filter[i].invert) { + tmp |= (1UL << i); + } + else if (!sensor_filter[i].prev && sensor_filter[i].invert) { + tmp |= (1UL << i); + } + } + IRQ_LOCK(flags); + sensor_filtered = tmp; + IRQ_UNLOCK(flags); +} + + + +/************ global sensor init */ + +/* called every 10 ms, see init below */ +static void do_sensors(__attribute__((unused)) void *dummy) +{ + do_adc(NULL); + do_boolean_sensors(NULL); +} + +void sensor_init(void) +{ + adc_init(); + adc_register_event(adc_event); + /* CS EVENT */ + scheduler_add_periodical_event_priority(do_sensors, NULL, + 10000L / SCHEDULER_UNIT, + ADC_PRIO); +} + diff --git a/projects/microb2009/mechboard/sensor.h b/projects/microb2009/mechboard/sensor.h new file mode 100644 index 0000000..27460db --- /dev/null +++ b/projects/microb2009/mechboard/sensor.h @@ -0,0 +1,56 @@ +/* + * Copyright Droids Corporation (2009) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: sensor.h,v 1.4 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +/* synchronize with sensor.c */ +#define ADC_CSENSE1 0 +#define ADC_CSENSE2 1 +#define ADC_CSENSE3 2 +#define ADC_CSENSE4 3 +#define ADC_MAX 4 + +/* synchronize with sensor.c */ +#define S_CAP1 0 +#define S_FRONT 1 +#define S_CAP3 2 +#define S_CAP4 3 +#define S_COL_LEFT 4 +#define S_LEFT 5 +#define S_RIGHT 6 +#define S_COL_RIGHT 7 +#define S_RESERVED1 8 +#define S_RESERVED2 9 +#define S_RESERVED3 10 +#define S_RESERVED4 11 +#define S_RESERVED5 12 +#define S_RESERVED6 13 +#define S_RESERVED7 14 +#define S_RESERVED8 15 +#define SENSOR_MAX 16 + +void sensor_init(void); + +/* get filtered values for adc */ +int16_t sensor_get_adc(uint8_t i); + +/* get filtered values of boolean sensors */ +uint16_t sensor_get_all(void); +uint8_t sensor_get(uint8_t i); diff --git a/projects/microb2009/mechboard/spi_config.h b/projects/microb2009/mechboard/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/microb2009/mechboard/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/microb2009/mechboard/state.c b/projects/microb2009/mechboard/state.c new file mode 100644 index 0000000..10af0f2 --- /dev/null +++ b/projects/microb2009/mechboard/state.c @@ -0,0 +1,1407 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: state.c,v 1.5 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#include <math.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <vt100.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "cmdline.h" +#include "sensor.h" +#include "actuator.h" +#include "arm_xy.h" +#include "arm_highlevel.h" +#include "state.h" + +#define STMCH_DEBUG(args...) DEBUG(E_USER_ST_MACH, args) +#define STMCH_NOTICE(args...) NOTICE(E_USER_ST_MACH, args) +#define STMCH_ERROR(args...) ERROR(E_USER_ST_MACH, args) + +/* shorter aliases for this file */ +#define MANUAL I2C_MECHBOARD_MODE_MANUAL +#define HARVEST I2C_MECHBOARD_MODE_HARVEST +#define PREPARE_PICKUP I2C_MECHBOARD_MODE_PREPARE_PICKUP +#define PICKUP I2C_MECHBOARD_MODE_PICKUP +#define PREPARE_BUILD I2C_MECHBOARD_MODE_PREPARE_BUILD +#define AUTOBUILD I2C_MECHBOARD_MODE_AUTOBUILD +#define WAIT I2C_MECHBOARD_MODE_WAIT +#define INIT I2C_MECHBOARD_MODE_INIT +#define PREPARE_GET_LINTEL I2C_MECHBOARD_MODE_PREPARE_GET_LINTEL +#define GET_LINTEL I2C_MECHBOARD_MODE_GET_LINTEL +#define PUT_LINTEL I2C_MECHBOARD_MODE_PUT_LINTEL +#define PREPARE_EJECT I2C_MECHBOARD_MODE_PREPARE_EJECT +#define EJECT I2C_MECHBOARD_MODE_EJECT +#define CLEAR I2C_MECHBOARD_MODE_CLEAR +#define LAZY_HARVEST I2C_MECHBOARD_MODE_LAZY_HARVEST +#define LOADED I2C_MECHBOARD_MODE_LOADED +#define PREPARE_INSIDE I2C_MECHBOARD_MODE_PREPARE_INSIDE +#define STORE I2C_MECHBOARD_MODE_STORE +#define LAZY_PICKUP I2C_MECHBOARD_MODE_LAZY_PICKUP +#define MANIVELLE I2C_MECHBOARD_MODE_MANIVELLE +#define PUSH_TEMPLE I2C_MECHBOARD_MODE_PUSH_TEMPLE +#define PUSH_TEMPLE_DISC I2C_MECHBOARD_MODE_PUSH_TEMPLE_DISC +#define EXIT I2C_MECHBOARD_MODE_EXIT + +static void state_do_eject(uint8_t arm_num, uint8_t pump_num, uint8_t old_mode); + +static struct i2c_cmd_mechboard_set_mode mainboard_command; +static struct vt100 local_vt100; +static volatile uint8_t prev_state; +static uint8_t pickup_side; +static volatile uint8_t changed = 0; + +uint8_t state_debug = 0; + +void state_dump_sensors(void) +{ + uint16_t tmp = sensor_get_all(); + prog_char *front = PSTR("no_front"); + prog_char *left = PSTR("no_left"); + prog_char *right = PSTR("no_right"); + + if (tmp & _BV(S_FRONT)) + front = PSTR("FRONT"); + if (tmp & _BV(S_LEFT)) { + if (tmp & _BV(S_COL_LEFT)) + left = PSTR("LEFT(red)"); + else + left = PSTR("LEFT(green)"); + } + if (tmp & _BV(S_RIGHT)) { + if (tmp & _BV(S_COL_RIGHT)) + right = PSTR("RIGHT(red)"); + else + right = PSTR("RIGHT(green)"); + } + + STMCH_DEBUG("sensors = %S %S %S", front, left, right); +} + +/* return 1 if column is there */ +uint8_t arm_get_sensor(uint8_t arm_num) +{ + if (arm_num == ARM_LEFT_NUM) { + return sensor_get(S_LEFT); + } + else if (arm_num == ARM_RIGHT_NUM) { + return sensor_get(S_RIGHT); + } + return 0; +} + +/* return 0 if color is correct, else return -1 */ +int8_t arm_get_color_sensor(uint8_t arm_num) +{ + uint8_t col = 0; + if (arm_num == ARM_LEFT_NUM) { + col = sensor_get(S_COL_LEFT); + } + else if (arm_num == ARM_RIGHT_NUM) { + col = sensor_get(S_COL_RIGHT); + } + + /* if col != 0, column is red */ + if (col) { + if (mechboard.our_color == I2C_COLOR_RED) + return 0; + return -1; + } + else { + if (mechboard.our_color == I2C_COLOR_GREEN) + return 0; + return -1; + } +} + +void state_debug_wait_key_pressed(void) +{ + if (!state_debug) + return; + printf_P(PSTR("press a key\r\n")); + while(!cmdline_keypressed()); +} + +/* set a new state, return 0 on success */ +int8_t state_set_mode(struct i2c_cmd_mechboard_set_mode *cmd) +{ + changed = 1; + prev_state = mainboard_command.mode; + memcpy(&mainboard_command, cmd, sizeof(mainboard_command)); + STMCH_DEBUG("%s mode=%d", __FUNCTION__, mainboard_command.mode); + return 0; +} + +/* check that state is the one in parameter and that state did not + * changed */ +uint8_t state_check(uint8_t mode) +{ + int16_t c; + if (mode != mainboard_command.mode) + return 0; + + if (changed) + return 0; + + /* force quit when CTRL-C is typed */ + c = cmdline_getchar(); + if (c == -1) + return 1; + if (vt100_parser(&local_vt100, c) == KEY_CTRL_C) { + mainboard_command.mode = EXIT; + return 0; + } + return 1; +} + +uint8_t state_get_mode(void) +{ + return mainboard_command.mode; +} + +void pump_reset_all(void) +{ + uint8_t i; + for (i=0; i<4; i++) { + pump_set(i, PUMP_OFF); + pump_mark_free(i); + } +} + +void pump_check_all(void) +{ + if (pump_is_busy(PUMP_LEFT1_NUM) && + mechboard.pump_left1_current < I2C_MECHBOARD_CURRENT_COLUMN) { + STMCH_DEBUG("Mark l1 as free"); + pump_mark_free(PUMP_LEFT1_NUM); + pump_set(PUMP_LEFT1_NUM, PUMP_OFF); + } + + if (pump_is_busy(PUMP_LEFT2_NUM) && + mechboard.pump_left2_current < I2C_MECHBOARD_CURRENT_COLUMN) { + STMCH_DEBUG("Mark l2 as free"); + pump_mark_free(PUMP_LEFT2_NUM); + pump_set(PUMP_LEFT2_NUM, PUMP_OFF); + } + + if (pump_is_busy(PUMP_RIGHT1_NUM) && + sensor_get_adc(ADC_CSENSE3) < I2C_MECHBOARD_CURRENT_COLUMN) { + STMCH_DEBUG("Mark r1 as free"); + pump_mark_free(PUMP_RIGHT1_NUM); + pump_set(PUMP_RIGHT1_NUM, PUMP_OFF); + } + + if (pump_is_busy(PUMP_RIGHT2_NUM) && + sensor_get_adc(ADC_CSENSE4) < I2C_MECHBOARD_CURRENT_COLUMN) { + STMCH_DEBUG("Mark r2 as free"); + pump_mark_free(PUMP_RIGHT2_NUM); + pump_set(PUMP_RIGHT2_NUM, PUMP_OFF); + } +} + +uint8_t get_free_pump_count(void) +{ + uint8_t i, free_pump_count = 0; + for (i=0; i<4; i++) { + if (pump_is_free(i)) + free_pump_count++; + } + return free_pump_count; +} + +/* move finger if we are not in lazy harvest */ +void state_finger_goto(uint8_t mode, uint16_t position) +{ + if (mode == LAZY_HARVEST) + return; + finger_goto(position); +} + +void state_manivelle(int16_t step_deg) +{ + double add_h = 0.; + double add_d = 160.; + double l = 70.; + double step = RAD(step_deg); + microseconds us; + double al = RAD(0); + double ar = RAD(180); + + time_wait_ms(500); + + us = time_get_us2(); + while (1) { + al += step; + ar += step; + arm_do_xy(&left_arm, add_d+l*sin(al), add_h+l*cos(al), 10); + arm_do_xy(&right_arm, add_d+l*sin(ar), add_h+l*cos(ar), 10); + time_wait_ms(25); + if (time_get_us2() - us > (4000L * 1000L)) + break; + } +} + +static void state_do_manivelle(void) +{ + if (!state_check(MANIVELLE)) + return; + state_manivelle(30); + while (state_check(MANIVELLE)); +} + +/* common function for pickup/harvest */ +static void state_pickup_or_harvest(uint8_t mode) +{ + int8_t arm_num, pump_num; + int8_t other_arm_num, other_pump_num; + struct arm *arm; + microseconds us; + uint8_t flags, bad_color = 0, have_2cols = 0; + + pump_check_all(); + + /* get arm num */ + if (pickup_side == I2C_LEFT_SIDE) { + arm_num = ARM_LEFT_NUM; + other_arm_num = ARM_RIGHT_NUM; + } + else { + arm_num = ARM_RIGHT_NUM; + other_arm_num = ARM_LEFT_NUM; + } + + pump_num = arm_get_free_pump(arm_num); + other_pump_num = arm_get_free_pump(other_arm_num); + + /* pump is not free... skip to other arm */ + if (mode == HARVEST && pump_num == -1) { + STMCH_DEBUG("%s no free pump", __FUNCTION__); + if (arm_num == ARM_RIGHT_NUM) { + state_finger_goto(mode, FINGER_CENTER_RIGHT); + pickup_side = I2C_LEFT_SIDE; + } + else { + state_finger_goto(mode, FINGER_CENTER_LEFT); + pickup_side = I2C_RIGHT_SIDE; + } + return; + } + else if (mode == PICKUP && pump_num == -1) { + /* or exit when we are in pickup mode */ + IRQ_LOCK(flags); + if (mainboard_command.mode == mode) + mainboard_command.mode = WAIT; + IRQ_UNLOCK(flags); + } + + us = time_get_us2(); + /* wait front sensor */ + if (mode == HARVEST || mode == LAZY_HARVEST) { + STMCH_DEBUG("%s wait front", __FUNCTION__); + + while (1) { + if (sensor_get(S_FRONT)) + break; + if (state_check(mode) == 0) + return; + /* wait 500ms before reading other + sensors */ + if (time_get_us2() - us < (500 * 1000L)) + continue; + if (arm_get_sensor(arm_num)) + break; + if (arm_get_sensor(other_arm_num)) { + uint8_t tmp; + tmp = arm_num; + arm_num = other_arm_num; + other_arm_num = tmp; + pump_num = arm_get_free_pump(arm_num); + other_pump_num = arm_get_free_pump(other_arm_num); + if (other_pump_num == -1) + return; // XXX + break; + } + } + } + + + STMCH_DEBUG("%s arm_num=%d pump_num=%d", + __FUNCTION__, arm_num, pump_num); + + /* when ready, move finger */ + if (arm_num == ARM_RIGHT_NUM) + state_finger_goto(mode, FINGER_RIGHT); + else + state_finger_goto(mode, FINGER_LEFT); + + state_debug_wait_key_pressed(); + + + arm = arm_num2ptr(arm_num); + + /* prepare arm, should be already done */ + arm_goto_prepare_get(arm_num, pump_num); + while (arm_test_traj_end(arm, ARM_TRAJ_ALL) && + state_check(mode)); + + STMCH_DEBUG("%s arm pos ok", __FUNCTION__); + + state_debug_wait_key_pressed(); + + /* wait to see the column on the sensor */ + us = time_get_us2(); + while (1) { + if (arm_get_sensor(arm_num)) + break; + if (state_check(mode) == 0) + return; + if (mode == PICKUP) /* no timeout in pickup */ + continue; + /* 500ms timeout in harvest, go back */ + if (time_get_us2() - us > 500*1000L) { + STMCH_DEBUG("%s timeout", __FUNCTION__); + + if (arm_num == ARM_RIGHT_NUM) + state_finger_goto(mode, FINGER_LEFT); + else + state_finger_goto(mode, FINGER_RIGHT); + + if (sensor_get(S_FRONT)) + time_wait_ms(500); + + pump_set(pump_num, PUMP_OFF); + return; + } + } + + state_dump_sensors(); + + pump_set(pump_num, PUMP_ON); + /* bad color */ + if (arm_get_color_sensor(arm_num) == -1) { + bad_color = 1; + STMCH_DEBUG("%s prepare eject", __FUNCTION__); + mainboard_command.mode = PREPARE_EJECT; + state_do_eject(arm_num, pump_num, mode); + return; + } + + STMCH_DEBUG("%s sensor ok", __FUNCTION__); + + /* by the way, prepare the other arm */ + if (other_pump_num != -1) + arm_goto_prepare_get(other_arm_num, other_pump_num); + + /* get the column */ + arm_goto_get_column(arm_num, pump_num); + + us = time_get_us2(); + while (1) { + /* wait 50 ms */ + if (time_get_us2() - us > 50*1000L) + break; + if (mode != HARVEST) + continue; + /* if we still see the front sensor, it's because + * there are 2 columns instead of one or because there + * is another column, so send the arm on other + * side. */ + if (sensor_get(S_FRONT) && have_2cols == 0) { + STMCH_DEBUG("%s 2 columns, release finger", __FUNCTION__); + have_2cols = 1; + if (finger_get_side() == I2C_LEFT_SIDE) + state_finger_goto(mode, FINGER_RIGHT); + else + state_finger_goto(mode, FINGER_LEFT); + } + } + + if (mode == HARVEST && have_2cols == 0) { + /* just release a bit of effort */ + if (finger_get_side() == I2C_LEFT_SIDE) { + state_finger_goto(mode, FINGER_LEFT_RELAX); + } + else { + state_finger_goto(mode, FINGER_RIGHT_RELAX); + } + } + else if (mode == PICKUP) { + /* no free pump on other arm */ + if (other_pump_num == -1) { + if (finger_get_side() == I2C_LEFT_SIDE) { + state_finger_goto(mode, FINGER_LEFT_RELAX); + } + else { + state_finger_goto(mode, FINGER_RIGHT_RELAX); + } + } + /* else send finger on the other side */ + else { + if (finger_get_side() == I2C_LEFT_SIDE) { + state_finger_goto(mode, FINGER_RIGHT); + } + else { + state_finger_goto(mode, FINGER_LEFT); + } + } + } + + us = time_get_us2(); + while (1) { + /* wait 100 ms */ + if (time_get_us2() - us > 100*1000L) + break; + if (mode != HARVEST) + continue; + /* if we still see the front sensor, it's because + * there are 2 columns instead of one or because there + * is another column, so send the arm on other + * side. */ + if (sensor_get(S_FRONT) && have_2cols == 0) { + STMCH_DEBUG("%s 2 columns, release finger", __FUNCTION__); + have_2cols = 1; + if (finger_get_side() == I2C_LEFT_SIDE) + state_finger_goto(mode, FINGER_RIGHT); + else + state_finger_goto(mode, FINGER_LEFT); + } + } + + /* consider the column as taken */ + pump_mark_busy(pump_num); + + state_debug_wait_key_pressed(); + + arm_goto_intermediate_get(arm_num, pump_num); + arm_wait_traj_end(arm, ARM_TRAJ_ALL_NEAR); + + /* prepare next */ + pump_num = arm_get_free_pump(arm_num); + if (pump_num == -1) + arm_goto_loaded(arm_num); + else + arm_goto_intermediate_get(arm_num, pump_num); + + state_debug_wait_key_pressed(); + + /* switch to wait state */ + if (get_free_pump_count() == 0) { + IRQ_LOCK(flags); + if (mainboard_command.mode == mode) + mainboard_command.mode = WAIT; + IRQ_UNLOCK(flags); + } + + /* next pickup/harvest will be on the other side */ + if (pickup_side == I2C_LEFT_SIDE) + pickup_side = I2C_RIGHT_SIDE; + else + pickup_side = I2C_LEFT_SIDE; +} + + +/* manual mode, arm position is sent from mainboard */ +static void state_do_manual(void) +{ + if (!state_check(MANUAL)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + while (state_check(MANUAL)); +} + +/* wait mode */ +static void state_do_wait(void) +{ + if (!state_check(WAIT)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + while (state_check(WAIT)); +} + +/* init mode */ +static void state_do_init(void) +{ + if (!state_check(INIT)) + return; + state_init(); + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + while (state_check(INIT)); +} + +/* harvest columns elts from area */ +static void state_do_harvest(void) +{ + if (!state_check(HARVEST)) + return; + + if (get_free_pump_count() == 0) { + mainboard_command.mode = WAIT; + return; + } + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + state_pickup_or_harvest(HARVEST); +} + +/* harvest columns elts from area without moving finger */ +static void state_do_lazy_harvest(void) +{ + if (!state_check(LAZY_HARVEST)) + return; + + if (get_free_pump_count() == 0) { + mainboard_command.mode = WAIT; + return; + } + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + state_pickup_or_harvest(LAZY_HARVEST); +} + +/* eject a column. always called from pickup mode. */ +static void state_do_eject(uint8_t arm_num, uint8_t pump_num, uint8_t old_mode) +{ + struct arm *arm; + arm = arm_num2ptr(arm_num); + + if (finger_get_side() == I2C_LEFT_SIDE) { + state_finger_goto(old_mode, FINGER_LEFT_RELAX); + } + else { + state_finger_goto(old_mode, FINGER_RIGHT_RELAX); + } + + /* wait mainboard to eject */ + while (state_check(PREPARE_EJECT)); + + if (finger_get_side() == I2C_LEFT_SIDE) { + state_finger_goto(old_mode, FINGER_CENTER_LEFT); + } + else { + state_finger_goto(old_mode, FINGER_CENTER_RIGHT); + } + + arm_goto_get_column(arm_num, pump_num); + arm_wait_traj_end(arm, ARM_TRAJ_ALL); + time_wait_ms(150); + + state_debug_wait_key_pressed(); + + arm_goto_prepare_eject(arm_num, pump_num); + arm_wait_traj_end(arm, ARM_TRAJ_ALL); + + state_debug_wait_key_pressed(); + + if (finger_get_side() == I2C_LEFT_SIDE) { + state_finger_goto(old_mode, FINGER_LEFT_RELAX); + } + else { + state_finger_goto(old_mode, FINGER_RIGHT_RELAX); + } + + state_debug_wait_key_pressed(); + + time_wait_ms(300); + arm_goto_eject(arm_num, pump_num); + time_wait_ms(200); + pump_set(pump_num, PUMP_REVERSE); + arm_wait_traj_end(arm, ARM_TRAJ_ALL); + + arm_goto_intermediate_get(arm_num, pump_num); + pump_set(pump_num, PUMP_OFF); +} + + +/* prepare pickup in a dispenser, or harvest */ +static void state_do_prepare_pickup(void) +{ + uint8_t left_count = 0, right_count = 0; + int8_t pump_l, pump_r; + + if (!state_check(PREPARE_PICKUP)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + pump_check_all(); + + pump_l = arm_get_free_pump(ARM_LEFT_NUM); + if (pump_l == -1) { + arm_goto_loaded(ARM_LEFT_NUM); + } + else { + arm_goto_intermediate_front_get(ARM_LEFT_NUM, pump_l); + } + + pump_r = arm_get_free_pump(ARM_RIGHT_NUM); + if (pump_r == -1) { + arm_goto_loaded(ARM_RIGHT_NUM); + } + else { + arm_goto_intermediate_front_get(ARM_RIGHT_NUM, pump_r); + } + + arm_wait_both(ARM_TRAJ_ALL); + + if (pump_l != -1) + arm_goto_prepare_get(ARM_LEFT_NUM, pump_l); + if (pump_r != -1) + arm_goto_prepare_get(ARM_RIGHT_NUM, pump_r); + + if (mainboard_command.prep_pickup.side == I2C_AUTO_SIDE) { + left_count += pump_is_busy(PUMP_LEFT1_NUM); + left_count += pump_is_busy(PUMP_LEFT2_NUM); + right_count += pump_is_busy(PUMP_RIGHT1_NUM); + right_count += pump_is_busy(PUMP_RIGHT2_NUM); + if (left_count < right_count) + finger_goto(FINGER_RIGHT); + else + finger_goto(FINGER_LEFT); + } + else if (mainboard_command.prep_pickup.side == I2C_LEFT_SIDE) + finger_goto(FINGER_LEFT); + else if (mainboard_command.prep_pickup.side == I2C_RIGHT_SIDE) + finger_goto(FINGER_RIGHT); + else if (mainboard_command.prep_pickup.side == I2C_CENTER_SIDE) + finger_goto(FINGER_CENTER_LEFT); + + /* try to know on which side we have to pickup */ + if (finger_get_side() == I2C_RIGHT_SIDE) { + pickup_side = I2C_LEFT_SIDE; + } + else { + pickup_side = I2C_RIGHT_SIDE; + } + + arm_prepare_free_pumps(); + + mainboard_command.mode = mainboard_command.prep_pickup.next_mode; + + while (state_check(PREPARE_PICKUP)); +} + +/* clear pickup zone, will switch to harvest if needed */ +static void state_do_clear(void) +{ + uint8_t flags, err; + + if (!state_check(CLEAR)) + return; + + if (get_free_pump_count() == 0) { + mainboard_command.mode = WAIT; + return; + } + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + finger_goto(FINGER_LEFT); + err = WAIT_COND_OR_TIMEOUT(sensor_get(S_LEFT), 500); + if (err) { + IRQ_LOCK(flags); + if (mainboard_command.mode == CLEAR) + mainboard_command.mode = I2C_MECHBOARD_MODE_HARVEST; + IRQ_UNLOCK(flags); + pickup_side = I2C_LEFT_SIDE; + return; + } + + finger_goto(FINGER_RIGHT); + err = WAIT_COND_OR_TIMEOUT(sensor_get(S_RIGHT), 500); + if (err) { + IRQ_LOCK(flags); + if (mainboard_command.mode == CLEAR) + mainboard_command.mode = I2C_MECHBOARD_MODE_HARVEST; + IRQ_UNLOCK(flags); + pickup_side = I2C_RIGHT_SIDE; + return; + } + + IRQ_LOCK(flags); + if (mainboard_command.mode == CLEAR) + mainboard_command.mode = I2C_MECHBOARD_MODE_HARVEST; + IRQ_UNLOCK(flags); +} + +/* do a lazy pickup */ +static void state_do_lazy_pickup(void) +{ + int8_t flags, arm_num, pump_num; + uint32_t us; + + if (!state_check(LAZY_PICKUP)) + return; + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + if (arm_get_sensor(ARM_LEFT_NUM) && + arm_get_sensor(ARM_RIGHT_NUM)) { + IRQ_LOCK(flags); + if (mainboard_command.mode == LAZY_PICKUP) { + mainboard_command.mode = WAIT; + } + IRQ_UNLOCK(flags); + return; + } + + if (finger_get_side() == I2C_RIGHT_SIDE) { + finger_goto(FINGER_LEFT); + arm_num = ARM_LEFT_NUM; + } + else { + finger_goto(FINGER_RIGHT); + arm_num = ARM_RIGHT_NUM; + } + + us = time_get_us2(); + while(1) { + if (state_check(LAZY_PICKUP) == 0) + return; + if (arm_get_sensor(arm_num)) + break; + if (time_get_us2() - us > 500*1000L) { + if (finger_get_side() == I2C_RIGHT_SIDE) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + return; + } + } + + if (arm_get_color_sensor(arm_num) == -1) { + pump_num = arm_get_free_pump(arm_num); + if (pump_num == -1) + return; /* XXX */ + pump_set(pump_num, PUMP_ON); + STMCH_DEBUG("%s prepare eject", __FUNCTION__); + mainboard_command.mode = PREPARE_EJECT; + state_do_eject(arm_num, pump_num, LAZY_PICKUP); + } +} + +/* pickup from a dispenser automatically */ +static void state_do_pickup(void) +{ + if (!state_check(PICKUP)) + return; + + if (get_free_pump_count() == 0) { + mainboard_command.mode = WAIT; + return; + } + + /* XXX check that finger is at correct place */ + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + state_pickup_or_harvest(PICKUP); +} + +/* store columns without using arms */ +static void state_do_store(void) +{ + int8_t arm_num; + int8_t other_arm_num; + microseconds us; + + if (!state_check(STORE)) + return; + + if (get_free_pump_count() == 0) { + mainboard_command.mode = WAIT; + return; + } + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + /* get arm num */ + if (pickup_side == I2C_LEFT_SIDE) { + arm_num = ARM_LEFT_NUM; + other_arm_num = ARM_RIGHT_NUM; + } + else { + arm_num = ARM_RIGHT_NUM; + other_arm_num = ARM_LEFT_NUM; + } + + while (1) { + if (sensor_get(S_FRONT)) + break; + if (state_check(STORE) == 0) + return; + } + + /* when ready, move finger */ + if (arm_num == ARM_RIGHT_NUM) + finger_goto(FINGER_RIGHT); + else + finger_goto(FINGER_LEFT); + + /* wait to see the column on the sensor */ + us = time_get_us2(); + while (1) { + if (arm_get_sensor(arm_num)) + break; + if (state_check(STORE) == 0) + return; + /* 500ms timeout in harvest, go back */ + if (time_get_us2() - us > 500*1000L) { + STMCH_DEBUG("%s timeout", __FUNCTION__); + + if (arm_num == ARM_RIGHT_NUM) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + return; + } + } + + if (arm_get_sensor(arm_num) && arm_get_sensor(other_arm_num)) { + STMCH_DEBUG("%s full", __FUNCTION__); + while (state_check(STORE)); + return; + } + + /* next store will be on the other side */ + if (pickup_side == I2C_LEFT_SIDE) + pickup_side = I2C_RIGHT_SIDE; + else + pickup_side = I2C_LEFT_SIDE; +} + +/* prepare the building of a temple */ +static void state_do_prepare_build(void) +{ + int8_t pump_num, level; + if (!state_check(PREPARE_BUILD)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + pump_check_all(); + + if (finger_get_side() == I2C_LEFT_SIDE) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + + pump_num = arm_get_busy_pump(ARM_LEFT_NUM); + level = mainboard_command.prep_build.level_l; + if (pump_num != -1 && level != -1) + arm_goto_prepare_autobuild_outside(ARM_LEFT_NUM, pump_num, + level, I2C_AUTOBUILD_DEFAULT_DIST); + + pump_num = arm_get_busy_pump(ARM_RIGHT_NUM); + level = mainboard_command.prep_build.level_r; + if (pump_num != -1 && level != -1) + arm_goto_prepare_autobuild_outside(ARM_RIGHT_NUM, pump_num, + level, I2C_AUTOBUILD_DEFAULT_DIST); + + while (state_check(PREPARE_BUILD)); +} + +/* prepare the building of a temple */ +static void state_do_push_temple(void) +{ + uint8_t level; + + level = mainboard_command.push_temple.level; + + if (!state_check(PUSH_TEMPLE)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + if (finger_get_side() == I2C_LEFT_SIDE) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + + arm_goto_prepare_push_temple(ARM_LEFT_NUM); + arm_goto_prepare_push_temple(ARM_RIGHT_NUM); + arm_wait_both(ARM_TRAJ_ALL); + + arm_goto_push_temple(ARM_LEFT_NUM, level); + arm_goto_push_temple(ARM_RIGHT_NUM, level); + + while (state_check(PUSH_TEMPLE)); +} + +/* prepare the building of a temple */ +static void state_do_push_temple_disc(void) +{ + uint8_t side; + struct arm *arm; + + if (!state_check(PUSH_TEMPLE_DISC)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + side = mainboard_command.push_temple_disc.side; + + if (side == I2C_LEFT_SIDE) { + arm = arm_num2ptr(ARM_LEFT_NUM); + arm_goto_prepare_push_temple_disc(ARM_LEFT_NUM); + arm_wait_traj_end(arm, ARM_TRAJ_ALL); + arm_goto_push_temple_disc(ARM_LEFT_NUM); + } + else { + arm = arm_num2ptr(ARM_RIGHT_NUM); + arm_goto_prepare_push_temple_disc(ARM_RIGHT_NUM); + arm_wait_traj_end(arm, ARM_TRAJ_ALL); + arm_goto_push_temple_disc(ARM_RIGHT_NUM); + } + + while (state_check(PUSH_TEMPLE_DISC)); +} + +/* prepare the building of a temple (mainly for columns) */ +static void state_do_prepare_inside(void) +{ + int8_t pump_num, level_l, level_r; + if (!state_check(PREPARE_INSIDE)) + return; + + level_l = mainboard_command.prep_inside.level_l; + level_r = mainboard_command.prep_inside.level_r; + STMCH_DEBUG("%s mode=%d level_l=%d, level_r=%d", __FUNCTION__, + state_get_mode(), level_l, level_r); + + pump_check_all(); + + if (finger_get_side() == I2C_LEFT_SIDE) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + + pump_num = arm_get_busy_pump(ARM_LEFT_NUM); + if (pump_num == -1) + pump_num = PUMP_LEFT1_NUM; + if (level_l != -1) + arm_goto_prepare_build_inside(ARM_LEFT_NUM, pump_num, + level_l); + + pump_num = arm_get_busy_pump(ARM_RIGHT_NUM); + if (pump_num == -1) + pump_num = PUMP_RIGHT1_NUM; + if (level_r != -1) + arm_goto_prepare_build_inside(ARM_RIGHT_NUM, pump_num, + level_r); + + while (state_check(PREPARE_INSIDE)); +} + +/* moving position */ +static void state_do_loaded(void) +{ + if (!state_check(LOADED)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + pump_check_all(); + + if (finger_get_side() == I2C_LEFT_SIDE) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + + arm_goto_loaded(ARM_LEFT_NUM); + arm_goto_loaded(ARM_RIGHT_NUM); + + while (state_check(LOADED)); +} + +static void state_do_build_lintel(uint8_t level) +{ + STMCH_DEBUG("%s() level=%d have_lintel=%d", + __FUNCTION__, level, mechboard.lintel_count); + + servo_lintel_out(); + + arm_goto_prepare_get_lintel_inside1(); + arm_wait_both(ARM_TRAJ_ALL); + state_debug_wait_key_pressed(); + + pump_set(PUMP_LEFT1_NUM, PUMP_REVERSE); + pump_set(PUMP_RIGHT1_NUM, PUMP_REVERSE); + arm_goto_prepare_get_lintel_inside2(mechboard.lintel_count); + arm_wait_both(ARM_TRAJ_ALL); + state_debug_wait_key_pressed(); + + arm_goto_get_lintel_inside(mechboard.lintel_count); + arm_wait_both(ARM_TRAJ_ALL); + state_debug_wait_key_pressed(); + + time_wait_ms(150); + arm_goto_prepare_build_lintel1(); + arm_wait_both(ARM_TRAJ_ALL); + state_debug_wait_key_pressed(); + + arm_goto_prepare_build_lintel2(level); + arm_wait_both(ARM_TRAJ_ALL); + state_debug_wait_key_pressed(); + + arm_goto_prepare_build_lintel3(level); + arm_wait_both(ARM_TRAJ_ALL); + state_debug_wait_key_pressed(); + + if (mechboard.lintel_count == 1) + servo_lintel_1lin(); + else + servo_lintel_2lin(); + + arm_goto_build_lintel(level); + arm_wait_both(ARM_TRAJ_ALL); + time_wait_ms(170); + pump_set(PUMP_LEFT1_NUM, PUMP_ON); + time_wait_ms(50); /* right arm a bit after */ + pump_set(PUMP_RIGHT1_NUM, PUMP_ON); + time_wait_ms(130); + pump_set(PUMP_LEFT1_NUM, PUMP_OFF); + pump_set(PUMP_RIGHT1_NUM, PUMP_OFF); + + mechboard.lintel_count --; +} + +/* Build one level of column. If pump_r or pump_l is -1, don't build + * with this arm. */ +static void state_do_build_column(uint8_t level_l, int8_t pump_l, + uint8_t dist_l, + uint8_t level_r, int8_t pump_r, + uint8_t dist_r) +{ + STMCH_DEBUG("%s() level_l=%d pump_l=%d level_r=%d pump_r=%d", + __FUNCTION__, level_l, pump_l, level_r, pump_r); + + /* nothing to do */ + if (pump_l == -1 && pump_r == -1) + return; + + /* go above the selected level */ + if (pump_l != -1) + arm_goto_prepare_autobuild_outside(ARM_LEFT_NUM, pump_l, level_l, dist_l); + if (pump_r != -1) + arm_goto_prepare_autobuild_outside(ARM_RIGHT_NUM, pump_r, level_r, dist_r); + STMCH_DEBUG("l=%d r=%d", arm_test_traj_end(&left_arm, ARM_TRAJ_ALL), + arm_test_traj_end(&right_arm, ARM_TRAJ_ALL)); + arm_wait_select(pump_l != -1, pump_r != -1, ARM_TRAJ_ALL); + STMCH_DEBUG("l=%d r=%d", arm_test_traj_end(&left_arm, ARM_TRAJ_ALL), + arm_test_traj_end(&right_arm, ARM_TRAJ_ALL)); + + state_debug_wait_key_pressed(); + + /* drop columns of P2 */ + if (pump_l != -1) + arm_goto_autobuild(ARM_LEFT_NUM, pump_l, level_l, dist_l); + if (pump_r != -1) + arm_goto_autobuild(ARM_RIGHT_NUM, pump_r, level_r, dist_r); + arm_wait_select(pump_l != -1, pump_r != -1, ARM_TRAJ_ALL); + + state_debug_wait_key_pressed(); + + time_wait_ms(150); + if (pump_l != -1) + pump_set(pump_l, PUMP_REVERSE); + if (pump_r != -1) + pump_set(pump_r, PUMP_REVERSE); + time_wait_ms(150); + if (pump_l != -1) { + pump_set(pump_l, PUMP_OFF); + pump_mark_free(pump_l); + } + if (pump_r != -1) { + pump_set(pump_r, PUMP_OFF); + pump_mark_free(pump_r); + } + + state_debug_wait_key_pressed(); +} + +/* autobuild columns elts from area */ +/* check level to avoid bad things ? */ +/* check if enough cols ? */ +static void state_do_autobuild(void) +{ + int8_t pump_l, pump_r; + /* copy command into local data */ + int8_t level_l = mainboard_command.autobuild.level_left; + int8_t level_r = mainboard_command.autobuild.level_right; + uint8_t count_l = mainboard_command.autobuild.count_left; + uint8_t count_r = mainboard_command.autobuild.count_right; + uint8_t dist_l = mainboard_command.autobuild.distance_left; + uint8_t dist_r = mainboard_command.autobuild.distance_right; + uint8_t do_lintel = mainboard_command.autobuild.do_lintel; + int8_t max_level = level_l; + + + if (!state_check(AUTOBUILD)) + return; + + STMCH_DEBUG("%s mode=%d do_lintel=%d", __FUNCTION__, + state_get_mode(), do_lintel); + STMCH_DEBUG(" left: level=%d count=%d", level_l, count_l); + STMCH_DEBUG(" right: level=%d count=%d", level_r, count_r); + + /* + * build the first level of column if needed + */ + + /* don't build with this arm if no pump or if we don't ask to */ + pump_l = arm_get_busy_pump(ARM_LEFT_NUM); + if (count_l == 0) + pump_l = -1; + pump_r = arm_get_busy_pump(ARM_RIGHT_NUM); + if (count_r == 0) + pump_r = -1; + + if (pump_l == -1 && pump_r == -1) + goto lintel_only; + + state_do_build_column(level_l, pump_l, dist_l, + level_r, pump_r, dist_r); + + /* one level up */ + if (pump_l != -1) { + count_l --; + level_l ++; + max_level = level_l; + } + if (pump_r != -1) { + count_r --; + level_r ++; + if (level_r > max_level) + max_level = level_r; + } + + /* + * build the second level of column if needed + */ + + /* don't build with this arm if no pump or if we don't ask to */ + pump_l = arm_get_busy_pump(ARM_LEFT_NUM); + if (count_l == 0) + pump_l = -1; + pump_r = arm_get_busy_pump(ARM_RIGHT_NUM); + if (count_r == 0) + pump_r = -1; + + state_do_build_column(level_l, pump_l, dist_l, + level_r, pump_r, dist_r); + + /* one level up */ + if (pump_l != -1) { + count_l --; + level_l ++; + max_level = level_l; + } + if (pump_r != -1) { + count_r --; + level_r ++; + if (level_r > max_level) + max_level = level_r; + } + + state_debug_wait_key_pressed(); + + if (mechboard.lintel_count != 0 && do_lintel != 0) { + arm_goto_prepare_autobuild_outside(ARM_LEFT_NUM, + PUMP_LEFT1_NUM, + max_level, + I2C_AUTOBUILD_DEFAULT_DIST); + arm_goto_prepare_autobuild_outside(ARM_RIGHT_NUM, + PUMP_RIGHT1_NUM, + max_level, + I2C_AUTOBUILD_DEFAULT_DIST); + arm_wait_both(ARM_TRAJ_ALL_NEAR); + state_debug_wait_key_pressed(); + + arm_goto_prepare_autobuild_inside(ARM_LEFT_NUM, + PUMP_LEFT1_NUM, + max_level); + arm_goto_prepare_autobuild_inside(ARM_RIGHT_NUM, + PUMP_RIGHT1_NUM, + max_level); + arm_wait_both(ARM_TRAJ_ALL_NEAR); + state_debug_wait_key_pressed(); + } + + lintel_only: + if (mechboard.lintel_count == 0 || do_lintel == 0) { + mainboard_command.mode = WAIT; + return; + } + + state_do_build_lintel(max_level); + mainboard_command.mode = WAIT; +} + +/* prepare to get the lintel */ +static void state_do_prepare_get_lintel(void) +{ + if (!state_check(PREPARE_GET_LINTEL)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + arm_goto_prepare_get_lintel_disp(); + arm_wait_both(ARM_TRAJ_ALL); + + pump_set(PUMP_LEFT1_NUM, PUMP_OFF); + pump_set(PUMP_RIGHT1_NUM, PUMP_OFF); + + /* go fully left or right */ + if (finger_get_side() == I2C_LEFT_SIDE) + finger_goto(FINGER_LEFT); + else + finger_goto(FINGER_RIGHT); + + while (state_check(PREPARE_GET_LINTEL)); +} + +/* get the lintel from the dispenser */ +static void state_do_get_lintel(void) +{ + if (!state_check(GET_LINTEL)) + return; + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + + pump_set(PUMP_LEFT1_NUM, PUMP_REVERSE); + pump_set(PUMP_RIGHT1_NUM, PUMP_REVERSE); + + arm_goto_get_lintel_disp(); + arm_wait_both(ARM_TRAJ_ALL_NEAR); + + time_wait_ms(200); + + STMCH_DEBUG("%s left1=%d left2=%d", __FUNCTION__, + mechboard.pump_left1_current, + sensor_get_adc(ADC_CSENSE3)); + + while (state_check(GET_LINTEL)); + + /* mainboard asked to release lintel, so release pump first */ + if (state_get_mode() == PREPARE_GET_LINTEL) { + pump_set(PUMP_LEFT1_NUM, PUMP_ON); + pump_set(PUMP_RIGHT1_NUM, PUMP_ON); + time_wait_ms(200); + pump_set(PUMP_LEFT1_NUM, PUMP_OFF); + pump_set(PUMP_RIGHT1_NUM, PUMP_OFF); + } +} + +/* put the lintel inside the robot */ +static void state_do_put_lintel(void) +{ + uint8_t prev_lin_count; + + if (!state_check(PUT_LINTEL)) + return; + + STMCH_DEBUG("%s mode=%d", __FUNCTION__, state_get_mode()); + prev_lin_count = mechboard.lintel_count; + mechboard.lintel_count ++; + + arm_goto_prepare_get_lintel_disp(); + arm_wait_both(ARM_TRAJ_ALL); + + servo_lintel_out(); + + arm_goto_prepare_put_lintel(); + arm_wait_both(ARM_TRAJ_ALL_NEAR); + + arm_goto_put_lintel(prev_lin_count); + arm_wait_both(ARM_TRAJ_ALL); + + pump_set(PUMP_LEFT1_NUM, PUMP_ON); + pump_set(PUMP_RIGHT1_NUM, PUMP_ON); + + if (mechboard.lintel_count == 1) + servo_lintel_1lin(); + else + servo_lintel_2lin(); + + time_wait_ms(300); + + pump_set(PUMP_LEFT1_NUM, PUMP_OFF); + pump_set(PUMP_RIGHT1_NUM, PUMP_OFF); + + arm_goto_prepare_put_lintel(); + arm_wait_both(ARM_TRAJ_ALL_NEAR); + + while (state_check(PUT_LINTEL)); +} + +/* main state machine */ +void state_machine(void) +{ + while (state_get_mode() != EXIT) { + changed = 0; + state_do_init(); + state_do_manual(); + state_do_harvest(); + state_do_lazy_harvest(); + state_do_prepare_pickup(); + state_do_pickup(); + state_do_prepare_inside(); + state_do_prepare_build(); + state_do_autobuild(); + state_do_prepare_get_lintel(); + state_do_get_lintel(); + state_do_put_lintel(); + state_do_loaded(); + state_do_clear(); + state_do_lazy_pickup(); + state_do_wait(); + state_do_store(); + state_do_manivelle(); + state_do_push_temple(); + state_do_push_temple_disc(); + } +} + +void state_init(void) +{ + vt100_init(&local_vt100); + mainboard_command.mode = WAIT; + pump_reset_all(); + mechboard.lintel_count = 1; + mechboard.column_flags = 0; + servo_lintel_1lin(); + finger_goto(FINGER_LEFT); +} diff --git a/projects/microb2009/mechboard/state.h b/projects/microb2009/mechboard/state.h new file mode 100644 index 0000000..0b49890 --- /dev/null +++ b/projects/microb2009/mechboard/state.h @@ -0,0 +1,40 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: state.h,v 1.5 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +#ifndef _STATE_H_ +#define _STATE_H_ + +extern volatile uint8_t lintel_count; + +void state_manivelle(int16_t step_deg); + +/* set a new state, return 0 on success */ +int8_t state_set_mode(struct i2c_cmd_mechboard_set_mode *cmd); + +/* get current state */ +uint8_t state_get_mode(void); + +/* launch state machine */ +void state_machine(void); + +void state_init(void); + +#endif diff --git a/projects/microb2009/mechboard/time_config.h b/projects/microb2009/mechboard/time_config.h new file mode 100755 index 0000000..6a1e4c5 --- /dev/null +++ b/projects/microb2009/mechboard/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.3 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 1000l diff --git a/projects/microb2009/mechboard/timer_config.h b/projects/microb2009/mechboard/timer_config.h new file mode 100755 index 0000000..bbfad76 --- /dev/null +++ b/projects/microb2009/mechboard/timer_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1 2009-03-05 22:52:35 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 diff --git a/projects/microb2009/mechboard/uart_config.h b/projects/microb2009/mechboard/uart_config.h new file mode 100644 index 0000000..a54811e --- /dev/null +++ b/projects/microb2009/mechboard/uart_config.h @@ -0,0 +1,67 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.5 2009-11-08 17:25:00 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE +#define UART0_ENABLED 1 +#define UART0_INTERRUPT_ENABLED 1 +#define UART0_BAUDRATE 57600 +//#define UART0_BAUDRATE 1000000 +#define UART0_USE_DOUBLE_SPEED 1 +#define UART0_RX_FIFO_SIZE 32 +#define UART0_TX_FIFO_SIZE 32 +#define UART0_NBITS 8 +#define UART0_PARITY UART_PARTITY_NONE +#define UART0_STOP_BIT UART_STOP_BITS_2 + +#define UART1_COMPILE +#define UART1_ENABLED 1 +#define UART1_INTERRUPT_ENABLED 1 +#define UART1_BAUDRATE 57600 +#define UART1_USE_DOUBLE_SPEED 1 +#define UART1_RX_FIFO_SIZE 128 +#define UART1_TX_FIFO_SIZE 128 +#define UART1_NBITS 8 +#define UART1_PARITY UART_PARTITY_NONE +#define UART1_STOP_BIT UART_STOP_BITS_1 + +#define UART3_COMPILE +#define UART3_ENABLED 1 +#define UART3_INTERRUPT_ENABLED 1 +#define UART3_BAUDRATE 57600 +#define UART3_USE_DOUBLE_SPEED 1 +#define UART3_RX_FIFO_SIZE 128 +#define UART3_TX_FIFO_SIZE 128 +#define UART3_NBITS 8 +#define UART3_PARITY UART_PARTITY_NONE +#define UART3_STOP_BIT UART_STOP_BITS_1 + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/projects/microb2009/microb_cmd/CVS/Entries b/projects/microb2009/microb_cmd/CVS/Entries new file mode 100644 index 0000000..dc75348 --- /dev/null +++ b/projects/microb2009/microb_cmd/CVS/Entries @@ -0,0 +1,2 @@ +/microbcmd.py/1.7/Wed May 27 20:04:07 2009// +D diff --git a/projects/microb2009/microb_cmd/CVS/Repository b/projects/microb2009/microb_cmd/CVS/Repository new file mode 100644 index 0000000..eb58ebd --- /dev/null +++ b/projects/microb2009/microb_cmd/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/microb_cmd diff --git a/projects/microb2009/microb_cmd/CVS/Root b/projects/microb2009/microb_cmd/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/microb_cmd/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/microb_cmd/CVS/Template b/projects/microb2009/microb_cmd/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/microb_cmd/microbcmd.py b/projects/microb2009/microb_cmd/microbcmd.py new file mode 100755 index 0000000..5080927 --- /dev/null +++ b/projects/microb2009/microb_cmd/microbcmd.py @@ -0,0 +1,929 @@ +#! /usr/bin/env python + +import os,sys,termios,atexit +import serial +from select import select +import cmd +#import pylab +from matplotlib import pylab +from math import * + +import numpy +import shlex +import time +import math +import warnings +warnings.filterwarnings("ignore","tempnam",RuntimeWarning, __name__) + +import logging +log = logging.getLogger("MicrobShell") +_handler = logging.StreamHandler() +_handler.setFormatter(logging.Formatter("%(levelname)s: %(message)s")) +log.addHandler(_handler) +log.setLevel(1) + +MICROB_PATH=os.path.dirname(sys.argv[0]) + +SPM_PAGE_SIZE = 256 + +def crc_ccitt_update (crc, data): + """crc argument is the previous value of 16 bits crc (the initial + value is 0xffff). 'data' is the 8 bits value added to crc. The + function returns the new crc value.""" + + data ^= (crc & 0xff) + data ^= (data << 4) + data &= 0xff + + ret = (data << 8) & 0xffff + ret |= ((crc >> 8) & 0xff) + ret ^= ((data >> 4) & 0xff) + ret ^= ((data << 3) & 0xffff) + return ret + +def do_crc(buf): + i = 0 + crc = 0xffff + sum = 0 + while i < len(buf): + crc = crc_ccitt_update(crc, ord(buf[i])) + sum += ord(buf[i]) + i += 1 + return (crc << 16) + (sum & 0xffff) + +def prog_page(ser, addr, buf): + """program a page from buf at addr""" + + # switch in program mode + ser.flushInput() + ser.write('p') + + # send address + s = ser.readline() + if not s.endswith("addr?\r\n"): + print "failed (don't match addr)" + return -1 + ser.write("%x\n"%addr) + s = ser.readline() + if not s.startswith("ok"): + print "failed" + return -1 + + # fill page with buf data + page = [ '\xff' ] * SPM_PAGE_SIZE + i = 0 + while i < SPM_PAGE_SIZE and i < len(buf): + page[i] = buf[i] + i += 1 + + # send data + i = 0 + while i < SPM_PAGE_SIZE: + c = page[i] + ser.write(c) + i += 1 + + sys.stdout.write(".") + sys.stdout.flush() + + # compare crc + avr_crc = int(ser.readline()[0:8], 16) + + crc = do_crc(page) + if crc != avr_crc: + print "failed: bad crc %x %x"%(crc, avr_crc) + ser.write('n') + return -1 + + ser.write('y') + s = ser.readline() + if not s.startswith("OK"): + print "failed" + return -1 + return 0 + +def read32(ser, addr): + """read a 32 bits value at addr""" + + # switch in program mode + ser.flushInput() + ser.write('d') + + # send address + s = ser.readline() + if not s.endswith("addr?\r\n"): + print "failed (don't match addr)" + return -1 + ser.write("%x\n"%addr) + s = ser.readline() + return int(s) + +def check_crc(ser, buf, offset, size): + """Process the crc of buf, ask for a crc of the flash, and check + that value is correct""" + if size <= 0: + return 0 + + # go in CRC mode + ser.flushInput() + ser.write('c') + + # send addr + s = ser.readline() + if not s.endswith("addr?\r\n"): + print "failed <%s>"%s + return -1 + ser.write("%x\n"%offset) + + # send size + s = ser.readline() + if not s.startswith("size?"): + print "failed" + return -1 + ser.write("%x\n"%size) + + # compare CRC + crc = do_crc(buf[offset:offset+size]) + avr_crc = int(ser.readline()[0:8], 16) + if crc != avr_crc: + return -1 + return 0 + +class SerialLogger: + def __init__(self, ser, filein, fileout=None): + self.ser = ser + self.filein = filein + self.fin = open(filein, "a", 0) + if fileout: + self.fileout = fileout + self.fout = open(fileout, "a", 0) + else: + self.fileout = filein + self.fout = self.fin + def fileno(self): + return self.ser.fileno() + def read(self, *args): + res = self.ser.read(*args) + self.fin.write(res) + return res + def write(self, s): + self.fout.write(s) + self.ser.write(s) + + + + + +""" +fig = figure() + +ax = subplot(111) + + +X = 45. +Y = -10. +l1 = 9. +l2 = 21.13 +l3 = 47.14 + +l_mirror = 249. +h_mirror = 13. + + +def ang2_a_mirror(b): + x2 = X+l1*math.cos(b) + y2 = Y+l1*math.sin(b) + + A = (l3**2+x2**2+y2**2-l2**2)/(2*l3) + + DELTA = -(A**2-x2**2-y2**2) + B = +math.sqrt(DELTA) + + D = x2**2+y2**2 + + c_a = (x2*A+y2*B)/D + s_a = -(x2*B-y2*A)/D + + a = math.atan2(s_a, c_a) + return x2, y2, c_a, s_a, a + + +def ang2_H_L(l_telemetre, c_a, s_a, a): + d = h_mirror*c_a/s_a + H = (l_telemetre - l_mirror - d)*math.sin(2*a) + L = l_mirror + d + H/math.tan(2*a) + return H, L + +all_p = [] +for b in xrange(0, 360, 20): + b = b*2*math.pi / 360. + + x2, y2, c_a, s_a, a = ang2_a_mirror(b) + x1 = l3*c_a + y1 = l3*s_a + + px = [0, x1, x2, X] + py = [0, y1, y2, Y] + + all_p+=[px, py] + + print math.sqrt((x2-x1)**2+(y2-y1)**2) + + H, L = ang2_H_L(400., c_a, s_a, a) + print H, L + +ax.plot(*all_p) + +show() + +""" + + + + +class Interp(cmd.Cmd): + prompt = "Microb> " + def __init__(self, tty, baudrate=57600): + cmd.Cmd.__init__(self) + self.ser = serial.Serial(tty,baudrate=baudrate) + self.escape = "\x01" # C-a + self.quitraw = "\x02" # C-b + self.serial_logging = False + self.default_in_log_file = "/tmp/microb.in.log" + self.default_out_log_file = "/tmp/microb.out.log" + + def do_quit(self, args): + return True + + def do_log(self, args): + """Activate serial logs. + log <filename> logs input and output to <filename> + log <filein> <fileout> logs input to <filein> and output to <fileout> + log logs to /tmp/microb.log or the last used file""" + + if self.serial_logging: + log.error("Already logging to %s and %s" % (self.ser.filein, + self.ser.fileout)) + else: + self.serial_logging = True + files = [os.path.expanduser(x) for x in args.split()] + if len(files) == 0: + files = [self.default_in_log_file, self.default_out_log_file] + elif len(files) == 1: + self.default_in_log_file = files[0] + self.default_out_log_file = None + elif len(files) == 2: + self.default_in_log_file = files[0] + self.default_out_log_file = files[1] + else: + print "Can't parse arguments" + + self.ser = SerialLogger(self.ser, *files) + log.info("Starting serial logging to %s and %s" % (self.ser.filein, + self.ser.fileout)) + + + def do_unlog(self, args): + if self.serial_logging: + log.info("Stopping serial logging to %s and %s" % (self.ser.filein, + self.ser.fileout)) + self.ser = self.ser.ser + self.serial_logging = False + else: + log.error("No log to stop") + + + def do_raw(self, args): + "Switch to RAW mode" + stdin = os.open("/dev/stdin",os.O_RDONLY) + stdout = os.open("/dev/stdout",os.O_WRONLY) + + stdin_termios = termios.tcgetattr(stdin) + raw_termios = stdin_termios[:] + + try: + log.info("Switching to RAW mode") + + # iflag + raw_termios[0] &= ~(termios.IGNBRK | termios.BRKINT | + termios.PARMRK | termios.ISTRIP | + termios.INLCR | termios.IGNCR | + termios.ICRNL | termios.IXON) + # oflag + raw_termios[1] &= ~termios.OPOST; + # cflag + raw_termios[2] &= ~(termios.CSIZE | termios.PARENB); + raw_termios[2] |= termios.CS8; + # lflag + raw_termios[3] &= ~(termios.ECHO | termios.ECHONL | + termios.ICANON | termios.ISIG | + termios.IEXTEN); + + termios.tcsetattr(stdin, termios.TCSADRAIN, raw_termios) + + mode = "normal" + while True: + ins,outs,errs=select([stdin,self.ser],[],[]) + for x in ins: + if x == stdin: + c = os.read(stdin,1) + if mode == "escape": + mode =="normal" + if c == self.escape: + self.ser.write(self.escape) + elif c == self.quitraw: + return + else: + self.ser.write(self.escape) + self.ser.write(c) + else: + if c == self.escape: + mode = "escape" + else: + self.ser.write(c) + elif x == self.ser: + os.write(stdout,self.ser.read()) + finally: + termios.tcsetattr(stdin, termios.TCSADRAIN, stdin_termios) + log.info("Back to normal mode") + + + def do_arm_x(self, args): + fsdf + my_h = 100 + my_r = 220 + my_ang = 90 + + self.ser.write("armxy %d %d %d\n"%(my_h, -my_r, my_ang)) + time.sleep(1) + + for i in xrange(-my_r, my_r, 25): + self.ser.write("armxy %d %d %d\n"%(my_h, i, my_ang)) + self.ser.flushInput() + + time.sleep(0.03) + + def do_arm_y(self, args): + my_x = 80 + my_r = 145 + my_ang = 0 + self.ser.write("armxy %d %d %d\n"%(-my_r, my_x, my_ang)) + time.sleep(1) + + for i in xrange(-my_r, my_r, 25): + self.ser.write("armxy %d %d %d\n"%(i, my_x, my_ang)) + self.ser.flushInput() + + time.sleep(0.03) + + def do_arm_circ(self, args): + add_h = 120 + add_d = 120 + l = 70 + for i in xrange(0, 360, 10): + x = l*math.cos(i*math.pi/180) + y = l*math.sin(i*math.pi/180) + + + self.ser.write("armxy %d %d 90\n"%(x+add_h, y+add_d)) + self.ser.flushInput() + + time.sleep(0.05) + + def do_arm_init(self, args): + self.arm_h = 130 + self.arm_v = 130 + self.mov_max = 20 + + self.ser.write("armxy %d %d\n"%(self.arm_h, self.arm_v)) + + def arm_py_goto(self, h, v, a): + """ + dh, dv = h-self.arm_h, v-self.arm_v + d = math.sqrt(dh**2 + dv**2) + + old_h = self.arm_h + old_v = self.arm_v + + mov_todo = int(d/self.mov_max) + for i in xrange(1, mov_todo): + p_h = dh*i/mov_todo + p_v = dv*i/mov_todo + + new_h = old_h+p_h + new_v = old_v+p_v + + self.ser.write("armxy %d %d %d\n"%(new_h, new_v, a)) + self.ser.flushInput() + self.arm_h = new_h + self.arm_v = new_v + + time.sleep(0.04) + + self.ser.write("armxy %d %d %d\n"%(h, v, a)) + self.ser.flushInput() + """ + + self.ser.write("armxy %d %d %d\n"%(h, v, a)) + self.ser.flushInput() + + time.sleep(0.2) + + + + def do_arm_tt(self, args): + for i in xrange(2): + self.arm_py_goto(80, 80, 200) + self.arm_py_goto(80, 200, 200) + self.arm_py_goto(200, 200, 200) + self.arm_py_goto(200, 80, 200) + + def do_arm_harve(self, args): + angl1 = 1 + angl2 = 100 + my_time = 0.03 + self.arm_py_goto(130,130,angl1) + self.arm_py_goto(-150,60,angl1) + time.sleep(0.1) + + self.ser.write("pwm 1B -3000\n") + self.ser.flushInput() + time.sleep(0.2) + + self.arm_py_goto(-120,60,angl1) + time.sleep(2) + self.arm_py_goto(-120,60,angl2) + time.sleep(2) + self.arm_py_goto(-150,60,angl2) + self.ser.write("pwm 3C -3000\n") + self.ser.flushInput() + time.sleep(0.2) + self.arm_py_goto(-130,60,angl2) + self.arm_py_goto(0,160,angl2) + + #middle point + self.arm_py_goto(-40,200,angl2) + + h = -150 + d = 210 + + self.arm_py_goto(h,d,angl2) + time.sleep(.3) + self.ser.write("pwm 3C 3000\n") + time.sleep(0.1) + self.arm_py_goto(h+60,d,angl2) + time.sleep(0.1) + + self.arm_py_goto(h+60,d,angl1) + time.sleep(0.3) + self.arm_py_goto(h+40,d,angl1) + time.sleep(0.3) + self.arm_py_goto(h+30,d,angl1) + time.sleep(0.3) + self.ser.write("pwm 1B 3000\n") + time.sleep(0.1) + self.arm_py_goto(h+70,d,angl1) + + self.ser.write("pwm 1B 0\n") + self.ser.write("pwm 3C 0\n") + + self.arm_py_goto(130,130,angl2) + + + + def update_graph(self, val): + freq = self.sfreq.val + self.theta_max = freq*math.pi*2.0 + self.theta = pylab.arange(0.0, self.theta_max, self.theta_max/len(self.r)) + self.theta = self.theta[:len(self.r)] + + self.myplot.set_xdata(self.theta) + draw() + """ + def do_graph(self, args): + self.ser.write("pwm 1A 2000\n") + time.sleep(0.5) + print "sampling..." + self.ser.write("sample start\n") + while True: + l = self.ser.readline() + if "dump end" in l: + break + #time.sleep(2) + self.ser.write("pwm 1A 0\n") + l = self.ser.readline() + l = self.ser.readline() + + print "dumping..." + self.ser.write("sample dump\n") + vals = [] + while True: + l = self.ser.readline() + if l[0] in ['s', 'c', 'a']: + continue + if l[0] in ['e']: + break + tokens = [x for x in shlex.shlex(l)] + v = int(tokens[0]) + #v = min(v, 150) + vals.append(v) + vals.reverse() + print "total vals:", len(vals) + + pylab.subplot(111, polar = True) + self.r = vals + valinit = 5.38 + #theta_max = 4.8*2.3*pi + self.theta_max =valinit*pylab.pi + self.theta = pylab.arange(0.0, self.theta_max, self.theta_max/len(self.r)) + + self.myplot, = pylab.plot(self.theta, self.r) + + #slide bar + axfreq = pylab.axes([0.25, 0.1, 0.65, 0.03]) + self.sfreq = pylab.Slider(axfreq, "Freq", 1, 20, valinit = valinit) + self.sfreq.on_changed(self.update_graph) + + pylab.show() + """ + + + def do_dump(self, args): + + t = [x for x in shlex.shlex(args)] + + t.reverse() + do_img = False + + #send speed,debug=off + #self.ser.write("scan_params 500 0\n") + #send algo 1 wrkazone 1 cx 15 cy 15 + self.ser.write("scan_img 1 1 15 15\n") + + print t + while len(t): + x = t.pop() + if x == 'img': + do_img = True + + print "dumping..." + self.ser.write("sample dump 0 0 400 0\n") + + + + while True: + l = self.ser.readline() + + if "start dumping" in l: + tokens = [x for x in shlex.shlex(l)] + num_rows = int(tokens[-1]) + print "num row: ", num_rows + break + print l.strip() + #scan_stop = time.time() + #print "total time:", scan_stop-scan_start + + + vals = [] + while True: + l = self.ser.readline() + + if l[0] in ['s', 'c', 'a']: + continue + if l[0] in ['e']: + break + tokens = [x for x in shlex.shlex(l)] + v = int(tokens[0]) + #v = min(v, 150) + vals.append(v) + + + #vals.reverse() + print "total vals:", len(vals) + valinit = 5 + + #num_rows = int(600/valinit) + #num_cols = int(valinit) + num_rows_orig = num_rows + num_rows *= 1 + num_cols = len(vals)/num_rows + + data = [] + pt_num = 0 + my_min = None + my_max = None + + print "dim", num_rows, num_cols + print "sav img to pgm" + fimg = open("dump.pgm", "wb") + fimg.write("P5\n#toto\n%d %d\n255\n"%(num_rows, num_cols)) + for i in xrange(num_cols): + data.append([]) + #data[-1].append(0.0) + + for j in xrange(num_rows): + if vals[pt_num]>0x10: + p = 0 + else: + p=vals[pt_num] * 0x20 + if (p>0xFF): + p = 0xFF + + fimg.write(chr(p)) + if my_min == None or my_min>p: + my_min = p + if p!=255 and (my_max == None or my_max<p): + my_max = p + if p >= 205: + p = 0 + p/=1. + + + + data[-1].append(p) + pt_num+=1 + #data[-1].append(1.) + fimg.close() + print my_min, my_max + #print data + data = numpy.array(data) + + if do_img: + ax = pylab.subplot(111) + ax.imshow(data) + + + #pylab.subplot(111, polar = True) + self.r = vals + #theta_max = 4.8*2.3*pi + self.theta_max =valinit*pylab.pi + self.theta = pylab.arange(0.0, self.theta_max, self.theta_max/len(self.r)) + + """ + tmp = [] + for x in data: + tmp+=list(x) + self.myplot, = pylab.plot(tmp) + + + """ + if not do_img : + tmpx = [] + tmpy = [] + for x in data: + tmpy+=list(x) + tmpx+=range(len(x)) + self.myplot, = pylab.plot(tmpx, tmpy) + + + #slide bar + #axfreq = pylab.axes([0.25, 0.1, 0.65, 0.03]) + #self.sfreq = pylab.Slider(axfreq, "Freq", 1, 20, valinit = valinit) + #self.sfreq.on_changed(self.update_graph) + + pylab.show() + + + def do_scan_params(self, args): + t = [x for x in shlex.shlex(args)] + + if len(t)!=2: + return + t = [int(x) for x in t] + self.ser.write("scan_params %d %d\n"%tuple(t)) + + def do_graph(self, args): + t = [x for x in shlex.shlex(args)] + + t.reverse() + do_img = False + + #send speed,debug=off + #self.ser.write("scan_params 500 0\n") + #send algo 1 wrkazone 1 cx 15 cy 15 + self.ser.write("scan_img 1 1 15 15\n") + + print t + while len(t): + x = t.pop() + if x == 'img': + do_img = True + + + scan_start = time.time() + print "sampling..." + + self.ser.write("scan_do\n") + + flog = open('log.txt', 'w') + + while True: + l = self.ser.readline() + flog.write(l) + + if "dump end" in l: + break + flog.close() + + #time.sleep(2) + #self.ser.write("pwm 1A 0\n") + #l = self.ser.readline() + #l = self.ser.readline() + + + print "dumping..." + self.ser.write("sample dump 0 0 400 0\n") + + + + while True: + l = self.ser.readline() + + if "start dumping" in l: + tokens = [x for x in shlex.shlex(l)] + num_rows = int(tokens[-1]) + print "num row: ", num_rows + break + print l.strip() + scan_stop = time.time() + print "total time:", scan_stop-scan_start + + + vals = [] + while True: + l = self.ser.readline() + + if l[0] in ['s', 'c', 'a']: + continue + if l[0] in ['e']: + break + tokens = [x for x in shlex.shlex(l)] + v = int(tokens[0]) + #v = min(v, 150) + vals.append(v) + + + #vals.reverse() + print "total vals:", len(vals) + valinit = 5 + + #num_rows = int(600/valinit) + #num_cols = int(valinit) + num_rows_orig = num_rows + num_rows *= 1 + num_cols = len(vals)/num_rows + + data = [] + pt_num = 0 + my_min = None + my_max = None + + print "dim", num_rows, num_cols + print "sav img to pgm" + fimg = open("dump.pgm", "wb") + fimg.write("P5\n#toto\n%d %d\n255\n"%(num_rows, num_cols)) + for i in xrange(num_cols): + data.append([]) + #data[-1].append(0.0) + + for j in xrange(num_rows): + if vals[pt_num]>0x10: + p = 0 + else: + p=vals[pt_num] * 0x20 + if (p>0xFF): + p = 0xFF + + fimg.write(chr(p)) + if my_min == None or my_min>p: + my_min = p + if p!=255 and (my_max == None or my_max<p): + my_max = p + if p >= 205: + p = 0 + p/=1. + + + + data[-1].append(p) + pt_num+=1 + #data[-1].append(1.) + fimg.close() + print my_min, my_max + #print data + data = numpy.array(data) + + if do_img: + ax = pylab.subplot(111) + ax.imshow(data) + + + #pylab.subplot(111, polar = True) + self.r = vals + #theta_max = 4.8*2.3*pi + self.theta_max =valinit*pylab.pi + self.theta = pylab.arange(0.0, self.theta_max, self.theta_max/len(self.r)) + + """ + tmp = [] + for x in data: + tmp+=list(x) + self.myplot, = pylab.plot(tmp) + + + """ + if not do_img : + tmpx = [] + tmpy = [] + for x in data: + tmpy+=list(x) + tmpx+=range(len(x)) + self.myplot, = pylab.plot(tmpx, tmpy) + + + #slide bar + #axfreq = pylab.axes([0.25, 0.1, 0.65, 0.03]) + #self.sfreq = pylab.Slider(axfreq, "Freq", 1, 20, valinit = valinit) + #self.sfreq.on_changed(self.update_graph) + + pylab.show() + + + def bootloader(self, filename, boardnum): + self.ser.write("\n") + time.sleep(0.4) + self.ser.write("bootloader\n") + time.sleep(0.4) + self.ser.write("\n") + + print "start programming" + self.ser.flushInput() + f = open(filename) + buf = f.read() + addr = 0 + while addr < len(buf): + time.sleep(0.1) + if check_crc(self.ser, buf, addr, SPM_PAGE_SIZE) == 0: + sys.stdout.write("*") + sys.stdout.flush() + elif prog_page(self.ser, addr, + buf[addr:addr+SPM_PAGE_SIZE]) != 0: + return + addr += SPM_PAGE_SIZE + if check_crc(self.ser, buf, 0, len(buf)): + print "crc failed" + return + print "Done." + self.ser.write("x") + self.do_raw("") + + def do_bootloader(self, args): + self.bootloader(args, 0) + + def do_mainboard(self, args): + filename = os.path.join(MICROB_PATH, "../mainboard/main.bin") + self.bootloader(filename, 1) + + def do_mechboard(self, args): + filename = os.path.join(MICROB_PATH, "../mechboard/main.bin") + self.bootloader(filename, 2) + + def do_sensorboard(self, args): + filename = os.path.join(MICROB_PATH, "../sensorboard/main.bin") + self.bootloader(filename, 3) + + def do_toto(self, args): + for i in range(10): + time.sleep(1) + self.ser.write("pwm s3(3C) 200\n") + time.sleep(1) + self.ser.write("pwm s3(3C) 250\n") + +if __name__ == "__main__": + try: + import readline,atexit + except ImportError: + pass + else: + histfile = os.path.join(os.environ["HOME"], ".microb_history") + atexit.register(readline.write_history_file, histfile) + try: + readline.read_history_file(histfile) + except IOError: + pass + + device = "/dev/ttyS0" + if len(sys.argv) > 1: + device = sys.argv[1] + interp = Interp(device) + while 1: + try: + interp.cmdloop() + except KeyboardInterrupt: + print + except Exception,e: + l = str(e).strip() + if l: + log.exception("%s" % l.splitlines()[-1]) + continue + break diff --git a/projects/microb2009/sensorboard/.config b/projects/microb2009/sensorboard/.config new file mode 100644 index 0000000..bc9e293 --- /dev/null +++ b/projects/microb2009/sensorboard/.config @@ -0,0 +1,279 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_MCU_ATMEGA2560=y +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_ADVANCED_PRINTF=y +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_GEOMETRY=y +CONFIG_MODULE_SCHEDULER=y +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +CONFIG_MODULE_TIME=y +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +CONFIG_MODULE_I2C=y +CONFIG_MODULE_I2C_MASTER=y +# CONFIG_MODULE_I2C_MULTIMASTER is not set +CONFIG_MODULE_I2C_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +CONFIG_MODULE_PWM_NG=y +CONFIG_MODULE_ADC=y +CONFIG_MODULE_ADC_CREATE_CONFIG=y + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +CONFIG_MODULE_AX12=y +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +CONFIG_MODULE_ENCODERS_SPI=y +CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG=y + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +CONFIG_MODULE_BLOCKING_DETECTION_MANAGER=y +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +CONFIG_MODULE_PID=y +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +CONFIG_MODULE_DIAGNOSTIC=y +CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG=y +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/projects/microb2009/sensorboard/CVS/Entries b/projects/microb2009/sensorboard/CVS/Entries new file mode 100644 index 0000000..fdc3cf5 --- /dev/null +++ b/projects/microb2009/sensorboard/CVS/Entries @@ -0,0 +1,43 @@ +/.config/1.3/Wed May 27 20:04:07 2009// +/Makefile/1.4/Wed May 27 20:04:07 2009// +/actuator.c/1.2/Fri Apr 24 19:30:42 2009// +/actuator.h/1.2/Fri Apr 24 19:30:42 2009// +/adc_config.h/1.1/Sun Mar 29 18:44:54 2009// +/ax12_config.h/1.1/Sun Mar 29 18:44:54 2009// +/ax12_user.c/1.2/Tue Apr 7 20:03:48 2009// +/ax12_user.h/1.2/Tue Apr 7 20:03:48 2009// +/beacon.c/1.3/Wed May 27 20:04:07 2009// +/beacon.h/1.2/Wed May 27 20:04:07 2009// +/cmdline.c/1.2/Tue Apr 7 20:03:48 2009// +/cmdline.h/1.2/Wed May 27 20:04:07 2009// +/commands.c/1.2/Wed May 27 20:04:07 2009// +/commands_ax12.c/1.1/Sun Mar 29 18:44:54 2009// +/commands_cs.c/1.1/Sun Mar 29 18:44:54 2009// +/commands_gen.c/1.4/Wed May 27 20:04:07 2009// +/commands_scan.c/1.1/Wed May 27 20:04:07 2009// +/commands_sensorboard.c/1.2/Fri Apr 24 19:30:42 2009// +/cs.c/1.4/Wed May 27 20:04:07 2009// +/cs.h/1.1/Sun Mar 29 18:44:54 2009// +/diagnostic_config.h/1.1/Sun Mar 29 18:44:54 2009// +/encoders_spi_config.h/1.1/Sun Mar 29 18:44:54 2009// +/error_config.h/1.1/Sun Mar 29 18:44:54 2009// +/gen_scan_tab.c/1.1/Wed May 27 20:04:07 2009// +/i2c_config.h/1.1/Sun Mar 29 18:44:54 2009// +/i2c_protocol.c/1.3/Wed May 27 20:04:07 2009// +/i2c_protocol.h/1.1/Sun Mar 29 18:44:54 2009// +/img_processing.c/1.1/Wed May 27 20:04:07 2009// +/img_processing.h/1.1/Wed May 27 20:04:07 2009// +/main.c/1.4/Wed May 27 20:04:07 2009// +/main.h/1.4/Wed May 27 20:04:07 2009// +/pid_config.h/1.1/Sun Mar 29 18:44:54 2009// +/rdline_config.h/1.1/Sun Mar 29 18:44:54 2009// +/scanner.c/1.1/Wed May 27 20:04:07 2009// +/scanner.h/1.1/Wed May 27 20:04:07 2009// +/scheduler_config.h/1.2/Wed May 27 20:04:07 2009// +/sensor.c/1.3/Wed May 27 20:04:07 2009// +/sensor.h/1.1/Sun Mar 29 18:44:54 2009// +/spi_config.h/1.1/Sun Mar 29 18:44:54 2009// +/time_config.h/1.1/Sun Mar 29 18:44:54 2009// +/timer_config.h/1.1/Sun Mar 29 18:44:54 2009// +/uart_config.h/1.3/Wed May 27 20:04:07 2009// +D diff --git a/projects/microb2009/sensorboard/CVS/Repository b/projects/microb2009/sensorboard/CVS/Repository new file mode 100644 index 0000000..e37e757 --- /dev/null +++ b/projects/microb2009/sensorboard/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/sensorboard diff --git a/projects/microb2009/sensorboard/CVS/Root b/projects/microb2009/sensorboard/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/sensorboard/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/sensorboard/CVS/Template b/projects/microb2009/sensorboard/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/sensorboard/Makefile b/projects/microb2009/sensorboard/Makefile new file mode 100644 index 0000000..3013479 --- /dev/null +++ b/projects/microb2009/sensorboard/Makefile @@ -0,0 +1,46 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../.. +# VALUE, absolute or relative path : example ../.. # + +CFLAGS += -Werror +LDFLAGS = -T ../common/avr6.x + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c cmdline.c commands_ax12.c commands_gen.c +SRC += commands_cs.c commands_sensorboard.c commands.c commands_scan.c +SRC += i2c_protocol.c sensor.c actuator.c cs.c ax12_user.c +SRC += beacon.c +SRC += img_processing.c +SRC += scanner.c + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +scan_h_l.h: + @gcc gen_scan_tab.c -o gen_scan_tab -lm; \ + if ./gen_scan_tab > /dev/null 2>&1; then \ + echo ok; \ + else \ + echo nok; \ + fi + +AVRDUDE_DELAY=50 + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/sensorboard/actuator.c b/projects/microb2009/sensorboard/actuator.c new file mode 100644 index 0000000..2895c5a --- /dev/null +++ b/projects/microb2009/sensorboard/actuator.c @@ -0,0 +1,61 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: actuator.c,v 1.2 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> + +#include "main.h" + +#define PICKUP_WHEEL_L_ON 2000 +#define PICKUP_WHEEL_R_ON -2000 +#define PICKUP_WHEEL_L_OFF 0 +#define PICKUP_WHEEL_R_OFF 0 + +void pickup_wheels_on(void) +{ + pwm_ng_set(PICKUP_WHEEL_L_PWM, PICKUP_WHEEL_L_ON); + pwm_ng_set(PICKUP_WHEEL_R_PWM, PICKUP_WHEEL_R_ON); +} + +void pickup_wheels_off(void) +{ + pwm_ng_set(PICKUP_WHEEL_L_PWM, PICKUP_WHEEL_L_OFF); + pwm_ng_set(PICKUP_WHEEL_R_PWM, PICKUP_WHEEL_R_OFF); +} + diff --git a/projects/microb2009/sensorboard/actuator.h b/projects/microb2009/sensorboard/actuator.h new file mode 100644 index 0000000..a1a535d --- /dev/null +++ b/projects/microb2009/sensorboard/actuator.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: actuator.h,v 1.2 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +void pickup_wheels_on(void); +void pickup_wheels_off(void); + + diff --git a/projects/microb2009/sensorboard/adc_config.h b/projects/microb2009/sensorboard/adc_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/sensorboard/ax12_config.h b/projects/microb2009/sensorboard/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/projects/microb2009/sensorboard/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/projects/microb2009/sensorboard/ax12_user.c b/projects/microb2009/sensorboard/ax12_user.c new file mode 100644 index 0000000..231495e --- /dev/null +++ b/projects/microb2009/sensorboard/ax12_user.c @@ -0,0 +1,169 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12_user.c,v 1.2 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +#include <aversive.h> +#include <aversive/list.h> +#include <aversive/error.h> + +#include <i2c.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" + +/* + * Cmdline interface for AX12. Use the PC to command a daisy-chain of + * AX12 actuators with a nice command line interface. + * + * The circuit should be as following: + * + * |----------| + * | uart3|------->--- PC (baudrate=57600) + * | |-------<--- + * | atmega128| + * | | + * | uart0|---->---+-- AX12 (baudrate 115200) + * | |----<---| + * |----------| + * + * Note that RX and TX pins of UART1 are connected together to provide + * a half-duplex UART emulation. + * + */ + +#define UART_AX12_NUM 0 +#define UCSRxB UCSR0B +#define AX12_TIMEOUT 5000UL /* in us */ + +/********************************* AX12 commands */ + +/* + * We use synchronous access (not interrupt driven) to the hardware + * UART, because we have to be sure that the transmission/reception is + * really finished when we return from the functions. + * + * We don't use the CM-5 circuit as described in the AX12 + * documentation, we simply connect TX and RX and use TXEN + RXEN + + * DDR to manage the port directions. + */ + +static volatile uint8_t ax12_state = AX12_STATE_READ; +extern volatile struct cirbuf g_tx_fifo[]; /* uart fifo */ +static volatile uint8_t ax12_nsent = 0; + +/* Called by ax12 module to send a character on serial line. Count the + * number of transmitted bytes. It will be used in ax12_recv_char() to + * drop the bytes that we transmitted. */ +static int8_t ax12_send_char(uint8_t c) +{ + uart_send(UART_AX12_NUM, c); + ax12_nsent++; + return 0; +} + +/* for atmega256 */ +#ifndef TXEN +#define TXEN TXEN0 +#endif + +/* called by uart module when the character has been written in + * UDR. It does not mean that the byte is physically transmitted. */ +static void ax12_send_callback(char c) +{ + if (ax12_state == AX12_STATE_READ) { + /* disable TX when last byte is pushed. */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[UART_AX12_NUM])) + UCSRxB &= ~(1<<TXEN); + } +} + +/* Called by ax12 module when we want to receive a char. Note that we + * also receive the bytes we sent ! So we need to drop them. */ +static int16_t ax12_recv_char(void) +{ + microseconds t = time_get_us2(); + int c; + while (1) { + c = uart_recv_nowait(UART_AX12_NUM); + if (c != -1) { + if (ax12_nsent == 0) + return c; + ax12_nsent --; + } + + /* 5 ms timeout */ + if ((time_get_us2() - t) > AX12_TIMEOUT) + return -1; + } + return c; +} + +/* called by ax12 module when we want to switch serial line. As we + * work in interruption mode, this function can be called to switch + * back in read mode even if the bytes are not really transmitted on + * the line. That's why in this case we do nothing, we will fall back + * in read mode in any case when xmit is finished -- see in + * ax12_send_callback() -- */ +static void ax12_switch_uart(uint8_t state) +{ + uint8_t flags; + + if (state == AX12_STATE_WRITE) { + IRQ_LOCK(flags); + ax12_nsent=0; + while (uart_recv_nowait(UART_AX12_NUM) != -1); + UCSRxB |= (1<<TXEN); + ax12_state = AX12_STATE_WRITE; + IRQ_UNLOCK(flags); + } + else { + IRQ_LOCK(flags); + if (CIRBUF_IS_EMPTY(&g_tx_fifo[UART_AX12_NUM])) + UCSRxB &= ~(1<<TXEN); + ax12_state = AX12_STATE_READ; + IRQ_UNLOCK(flags); + } +} + + +void ax12_user_init(void) +{ + /* AX12 */ + AX12_init(&gen.ax12); + AX12_set_hardware_send(&gen.ax12, ax12_send_char); + AX12_set_hardware_recv(&gen.ax12, ax12_recv_char); + AX12_set_hardware_switch(&gen.ax12, ax12_switch_uart); + uart_register_tx_event(UART_AX12_NUM, ax12_send_callback); +} diff --git a/projects/microb2009/sensorboard/ax12_user.h b/projects/microb2009/sensorboard/ax12_user.h new file mode 100644 index 0000000..4091709 --- /dev/null +++ b/projects/microb2009/sensorboard/ax12_user.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: ax12_user.h,v 1.2 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +/* This is the ax12 user interface. It initializes the aversive AX12 + * module so that it works in background, using interrupt driver uart. + * + * Be carreful, a call to AX12 module is synchronous and uses + * interruptions, so interrupts must be enabled. On the other side, a + * call _must not_ interrupt another one. That's why all calls to the + * module are done either in init() functions or in a scheduler event + * with prio=ARM_PRIO. + */ + +/* XXX do a safe_ax12() function that will retry once or twice if we + * see some problems. */ + +void ax12_user_init(void); diff --git a/projects/microb2009/sensorboard/beacon.c b/projects/microb2009/sensorboard/beacon.c new file mode 100755 index 0000000..34f1686 --- /dev/null +++ b/projects/microb2009/sensorboard/beacon.c @@ -0,0 +1,397 @@ + +#include <stdio.h> +#include <string.h> +#include <math.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <uart.h> +#include <i2c.h> +#include <ax12.h> +#include <parse.h> +#include <rdline.h> +#include <pwm_ng.h> +#include <encoders_spi.h> +#include <timer.h> +#include <scheduler.h> +#include <pid.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <adc.h> +#include <spi.h> + +#include <blocking_detection_manager.h> + +#include "sensor.h" + +#include "../common/i2c_commands.h" +#include "main.h" +#include "beacon.h" + +struct beacon beacon; + +#define BEACON_PWM_VALUE 1000 +#define IR_SENSOR() (!!(PINK&(1<<2))) +#define MODULO_TIMER (1023L) +#define COEFF_TIMER (2) +#define COEFF_MULT (100L) +#define COEFF_MULT2 (1000L) +#define BEACON_SIZE (9) +#define BEACON_MAX_SAMPLE (3) + +#define OPPONENT_POS_X (11) +#define OPPONENT_POS_Y (22) + +#define BEACON_DEBUG(args...) DEBUG(E_USER_BEACON, args) +#define BEACON_NOTICE(args...) NOTICE(E_USER_BEACON, args) +#define BEACON_ERROR(args...) ERROR(E_USER_BEACON, args) + +static volatile int32_t rising = -1; +static volatile int32_t falling = -1; + +static int32_t get_dist(float size); +static int32_t get_angle(int32_t middle, int32_t ref); + +static int32_t pos_ref = 0; +static int32_t invalid_count = 0; + +static volatile int32_t beacon_speed; +static volatile int32_t beacon_save_count = 0; +static volatile int32_t beacon_prev_save_count = 0; +static volatile int32_t count = 0; +static volatile int32_t count_diff_rising = 0; +static volatile int32_t count_diff_falling = 0; +static int32_t beacon_coeff = 0; + +static volatile int8_t valid_beacon = 0; + +static volatile int32_t beacon_pos; + +//static int32_t beacon_sample_size[BEACON_MAX_SAMPLE]; + +int32_t encoders_spi_get_value_beacon(void *number) +{ + int32_t ret; + + ret = encoders_spi_get_value(number); + return ret*4; +} + + +void encoders_spi_set_value_beacon(void * number, int32_t v) +{ + encoders_spi_set_value(number, v/4); +} + +int32_t encoders_spi_update_beacon_speed(void * number) +{ + int32_t ret; + uint8_t flags; + + IRQ_LOCK(flags); + ret = encoders_spi_get_value_beacon(number); + beacon_speed = ret - beacon_pos; + beacon_pos = ret; + beacon_prev_save_count = beacon_save_count; + beacon_save_count = TCNT3; + IRQ_UNLOCK(flags); + + beacon_coeff = COEFF_TIMER * COEFF_MULT;//beacon_speed * COEFF_MULT / ((beacon_prev_save_count - beacon_save_count + MODULO_TIMER + 1)&MODULO_TIMER); + + return beacon_speed; +} + + +void beacon_init(void) +{ + //int8_t i; + + beacon_reset_pos(); + pos_ref = encoders_spi_get_value_beacon(BEACON_ENCODER); + + memset(&beacon, 0, sizeof(struct beacon)); + beacon.opponent_x = I2C_OPPONENT_NOT_THERE; + + beacon_speed = 0; + + /*for(i=0;i<BEACON_MAX_SAMPLE;i++) + beacon_sample_size[i] = 0;*/ + + /* set external interrupt (any edge) */ + PCMSK2 = (1<<PCINT18); + PCICR = (1<<PCIE2); + + +} + +void beacon_calibre_pos(void) +{ + sensorboard.flags &= ~DO_CS; + + /* init beacon pos */ + pwm_ng_set(BEACON_PWM, 100); + + /* find rising edge of the mirror*/ + wait_ms(100); + while (sensor_get(BEACON_POS_SENSOR)); + wait_ms(100); + while (!sensor_get(BEACON_POS_SENSOR)); + + pwm_ng_set(BEACON_PWM, 0); + + + beacon_reset_pos(); + pid_reset(&sensorboard.beacon.pid); + encoders_spi_set_value_beacon(BEACON_ENCODER, BEACON_OFFSET_CALIBRE); + + cs_set_consign(&sensorboard.beacon.cs, 0); + + sensorboard.flags |= DO_CS; +} + +void beacon_start(void) +{ + beacon_reset_pos(); + sensorboard.beacon.on = 1; + cs_set_consign(&sensorboard.beacon.cs, 600); +} + +void beacon_stop(void) +{ + sensorboard.beacon.on = 0; + pwm_ng_set(BEACON_PWM, 0); +} + +void beacon_reset_pos(void) +{ + pwm_ng_set(BEACON_PWM, 0); + encoders_spi_set_value(BEACON_ENCODER, 0); +} + + + +int32_t encoders_spi_get_beacon_speed(void * dummy) +{ + return beacon_speed; +} + + +//port K bit 2 +/* motor speed (top tour) */ +SIGNAL(SIG_PIN_CHANGE2) +{ + uint8_t flags; + + /* rising edge */ + if ( IR_SENSOR()) { + IRQ_LOCK(flags); + count = TCNT3; + rising = beacon_pos; + count_diff_rising = (count - beacon_save_count + MODULO_TIMER + 1)&MODULO_TIMER; + valid_beacon = 0; + IRQ_UNLOCK(flags); + + } + /* falling edge */ + else { + IRQ_LOCK(flags); + count = TCNT3; + falling = beacon_pos; + count_diff_falling = (count - beacon_save_count + MODULO_TIMER + 1)&MODULO_TIMER; + valid_beacon = 1; + IRQ_UNLOCK(flags); + } +} + +void beacon_calc(void *dummy) +{ + static uint8_t a=0; + static int32_t local_rising, local_falling; + static int32_t middle; + static float size = 0; + int32_t local_angle; + int32_t local_dist; + + int32_t local_count_diff_rising ; + int32_t local_count_diff_falling ; + int32_t local_beacon_coeff; + + int32_t result_x=0; + int32_t result_y=0; + int32_t temp=0; + int32_t edge=0; + //int32_t total_size=0; + + uint8_t flags; + //uint8_t i; + int8_t local_valid; + + if(a) + LED4_ON(); + else + LED4_OFF(); + + a = !a; + + if (falling == -1){ + /* 0.5 second timeout */ + if (invalid_count < 25) + invalid_count++; + else { + IRQ_LOCK(flags); + beacon.opponent_x = I2C_OPPONENT_NOT_THERE; + IRQ_UNLOCK(flags); + } + return; + } + + invalid_count = 0; + IRQ_LOCK(flags); + local_valid = valid_beacon; + local_count_diff_rising = count_diff_rising; + local_count_diff_falling = count_diff_falling ; + local_rising = rising; + local_falling = falling; + local_beacon_coeff = beacon_coeff; + IRQ_UNLOCK(flags); + + if (local_valid){ + invalid_count = 0; + //BEACON_DEBUG("rising= %ld\t",local_rising); + //BEACON_DEBUG("falling= %ld\r\n",local_falling); + + /* recalculate number of pulse by adding the value of the counter, then put value back into motor's round range */ + local_rising = ((local_rising + (local_count_diff_rising * local_beacon_coeff) / COEFF_MULT)) %(BEACON_STEP_TOUR); + local_falling = ((local_falling + (local_count_diff_falling * local_beacon_coeff) / COEFF_MULT)) %(BEACON_STEP_TOUR); + + //BEACON_DEBUG("rising1= %ld\t",local_rising); + //BEACON_DEBUG("falling1= %ld\r\n",local_falling); + + //BEACON_DEBUG("count diff rising= %ld\t",local_count_diff_rising); + //BEACON_DEBUG("count diff falling= %ld\r\n",local_count_diff_falling); + + /* if around 360 deg, rising > falling, so invert both and recalculate size and middle */ + if(local_falling < local_rising){ + temp = local_rising; + local_rising = local_falling; + local_falling = temp; + size = BEACON_STEP_TOUR - local_falling + local_rising; + middle = (local_falling + ((int32_t)(size)/2) + BEACON_STEP_TOUR) %(BEACON_STEP_TOUR); + edge = local_falling; + } + /* else rising > falling */ + else{ + size = local_falling - local_rising; + middle = local_rising + (size / 2); + edge = local_rising; + } + + //for(i=BEACON_MAX_SAMPLE-1;i>0;i--){ + // beacon_sample_size[i] = beacon_sample_size[i-1]; + // total_size += beacon_sample_size[i]; + //} + //beacon_sample_size[0] = size; + //total_size += size; + //total_size /= BEACON_MAX_SAMPLE; + + //BEACON_DEBUG("rising2= %ld\t",local_rising); + //BEACON_DEBUG("falling2= %ld\r\n",local_falling); + /* BEACON_DEBUG("size= %ld %ld\t",size, total_size); */ + BEACON_DEBUG("size= %f\r\n",size); + //BEACON_DEBUG("middle= %ld\r\n",middle); + + local_angle = get_angle(middle,0); + BEACON_NOTICE("opponent angle= %ld\t",local_angle); + + local_dist = get_dist(size); + BEACON_NOTICE("opponent dist= %ld\r\n",local_dist); + + beacon_angle_dist_to_x_y(local_angle, local_dist, &result_x, &result_y); + + IRQ_LOCK(flags); + beacon.opponent_x = result_x; + beacon.opponent_y = result_y; + beacon.opponent_angle = local_angle; + beacon.opponent_dist = local_dist; + /* for I2C test */ + //beacon.opponent_x = OPPONENT_POS_X; + //beacon.opponent_y = OPPONENT_POS_Y; + IRQ_UNLOCK(flags); + + BEACON_NOTICE("opponent x= %ld\t",beacon.opponent_x); + BEACON_NOTICE("opponent y= %ld\r\n\n",beacon.opponent_y); + } + else { + BEACON_NOTICE("non valid\r\n\n"); + } + + falling = -1; +} + +static int32_t get_dist(float size) +{ + int32_t dist=0; + //int32_t alpha=0; + + //alpha = (size*2*M_PI*COEFF_MULT2); + //dist = ((2*BEACON_SIZE*BEACON_STEP_TOUR*COEFF_MULT2)/alpha)/2; + + /* function found by measuring points up to 80cm */ + //dist = ((size - 600)*(size - 600)) / 2400 +28; + + /* new function */ + /* dist = a0 + a1*x + a2*x² + a3x³ */ + dist = 1157.3 + (1.4146*size) + (-0.013508*size*size) + (0.00001488*size*size*size); + + return dist; + +} + +static int32_t get_angle(int32_t middle, int32_t ref) +{ + int32_t ret_angle; + + ret_angle = (middle - ref) * 360 / BEACON_STEP_TOUR; + + if(ret_angle > 360) + ret_angle -= 360; + + return ret_angle; +} + +void beacon_angle_dist_to_x_y(int32_t angle, int32_t dist, int32_t *x, int32_t *y) +{ + uint8_t flags; + + int32_t local_x; + int32_t local_y; + int32_t x_opponent; + int32_t y_opponent; + int32_t local_robot_angle; + + IRQ_LOCK(flags); + local_x = beacon.robot_x; + local_y = beacon.robot_y; + local_robot_angle = beacon.robot_angle; + IRQ_UNLOCK(flags); + + if (local_robot_angle < 0) + local_robot_angle += 360; + + x_opponent = cos((local_robot_angle + angle)* 2 * M_PI / 360)* dist; + y_opponent = sin((local_robot_angle + angle)* 2 * M_PI / 360)* dist; + + //BEACON_DEBUG("x_op= %ld\t",x_opponent); + //BEACON_DEBUG("y_op= %ld\r\n",y_opponent); + //BEACON_NOTICE("robot_x= %ld\t",local_x); + //BEACON_NOTICE("robot_y= %ld\t",local_y); + //BEACON_NOTICE("robot_angle= %ld\r\n",local_robot_angle); + + *x = local_x + x_opponent; + *y = local_y + y_opponent; + +} diff --git a/projects/microb2009/sensorboard/beacon.h b/projects/microb2009/sensorboard/beacon.h new file mode 100755 index 0000000..21d7dd5 --- /dev/null +++ b/projects/microb2009/sensorboard/beacon.h @@ -0,0 +1,58 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: beacon.h,v 1.2 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +struct beacon { + int32_t beacon_speed; + + int32_t opponent_angle; + int32_t opponent_dist; + int32_t prev_opponent_angle; + int32_t prev_opponent_dist; + int32_t robot_x; + int32_t robot_y; + int32_t robot_angle; + int32_t opponent_x; + int32_t opponent_y; +}; + +/* real encoder value: 3531.75 so, multiple by 4 to have round + * value */ +#define BEACON_STEP_TOUR (14127L) +#define BEACON_OFFSET_CALIBRE 40 + +extern struct beacon beacon; + +void beacon_dump(void); +void beacon_init(void); +void beacon_calibre_pos(void); +void beacon_start(void); +void beacon_stop(void); +void beacon_calc(void *dummy); +void beacon_angle_dist_to_x_y(int32_t angle, int32_t dist, int32_t *x, int32_t *y); + +void beacon_reset_pos(void); +void beacon_set_consign(int32_t val); + +int32_t encoders_spi_get_beacon_speed(void *dummy); +int32_t encoders_spi_update_beacon_speed(void *number); +int32_t encoders_spi_get_value_beacon(void *number); + + diff --git a/projects/microb2009/sensorboard/cmdline.c b/projects/microb2009/sensorboard/cmdline.c new file mode 100644 index 0000000..ceb3efe --- /dev/null +++ b/projects/microb2009/sensorboard/cmdline.c @@ -0,0 +1,149 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cmdline.c,v 1.2 2009-04-07 20:03:48 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <parse.h> +#include <rdline.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include "main.h" +#include "cmdline.h" + + +/******** See in commands.c for the list of commands. */ +extern parse_pgm_ctx_t main_ctx[]; + +static void write_char(char c) +{ + uart_send(CMDLINE_UART, c); +} + +static void +valid_buffer(const char *buf, uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char *buf, char *dstbuf, uint8_t dstsize, + int16_t *state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + + +/* sending "pop" on cmdline uart resets the robot */ +void emergency(char c) +{ + static uint8_t i = 0; + + if ((i == 0 && c == 'p') || + (i == 1 && c == 'o') || + (i == 2 && c == 'p')) + i++; + else if ( !(i == 1 && c == 'p') ) + i = 0; + if (i == 3) + reset(); +} + +/* log function, add a command to configure + * it dynamically */ +void mylog(struct error * e, ...) +{ + va_list ap; + u16 stream_flags = stdout->flags; + uint8_t i; + time_h tv; + + if (e->severity > ERROR_SEVERITY_ERROR) { + if (gen.log_level < e->severity) + return; + + for (i=0; i<NB_LOGS+1; i++) + if (gen.logs[i] == e->err_num) + break; + if (i == NB_LOGS+1) + return; + } + + va_start(ap, e); + tv = time_get_time(); + printf_P(PSTR("%ld.%.3ld: "), tv.s, (tv.us/1000UL)); + vfprintf_P(stdout, e->text, ap); + printf_P(PSTR("\r\n")); + va_end(ap); + stdout->flags = stream_flags; +} + +int cmdline_interact(void) +{ + const char *history, *buffer; + int8_t ret, same = 0; + int16_t c; + + rdline_init(&gen.rdl, write_char, valid_buffer, complete_buffer); + snprintf(gen.prompt, sizeof(gen.prompt), "sensorboard > "); + rdline_newline(&gen.rdl, gen.prompt); + + while (1) { + c = uart_recv_nowait(CMDLINE_UART); + if (c == -1) + continue; + ret = rdline_char_in(&gen.rdl, c); + if (ret != 2 && ret != 0) { + buffer = rdline_get_buffer(&gen.rdl); + history = rdline_get_history_item(&gen.rdl, 0); + if (history) { + same = !memcmp(buffer, history, strlen(history)) && + buffer[strlen(history)] == '\n'; + } + else + same = 0; + if (strlen(buffer) > 1 && !same) + rdline_add_history(&gen.rdl, buffer); + rdline_newline(&gen.rdl, gen.prompt); + } + } + + return 0; +} diff --git a/projects/microb2009/sensorboard/cmdline.h b/projects/microb2009/sensorboard/cmdline.h new file mode 100644 index 0000000..57dfa49 --- /dev/null +++ b/projects/microb2009/sensorboard/cmdline.h @@ -0,0 +1,40 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cmdline.h,v 1.2 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#define CMDLINE_UART 1 + +/* uart rx callback for reset() */ +void emergency(char c); + +/* log function */ +void mylog(struct error * e, ...); + +/* launch cmdline */ +int cmdline_interact(void); + +static inline uint8_t cmdline_keypressed(void) { + return (uart_recv_nowait(CMDLINE_UART) != -1); +} + +static inline uint8_t cmdline_getchar(void) { + return uart_recv_nowait(CMDLINE_UART); +} diff --git a/projects/microb2009/sensorboard/commands.c b/projects/microb2009/sensorboard/commands.c new file mode 100644 index 0000000..539c96d --- /dev/null +++ b/projects/microb2009/sensorboard/commands.c @@ -0,0 +1,128 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.2 2009-05-27 20:04:07 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdlib.h> +#include <aversive/pgmspace.h> +#include <parse.h> + +/* commands_gen.c */ +extern parse_pgm_inst_t cmd_reset; +extern parse_pgm_inst_t cmd_bootloader; +extern parse_pgm_inst_t cmd_encoders; +extern parse_pgm_inst_t cmd_pwm; +extern parse_pgm_inst_t cmd_adc; +extern parse_pgm_inst_t cmd_sensor; +extern parse_pgm_inst_t cmd_log; +extern parse_pgm_inst_t cmd_log_show; +extern parse_pgm_inst_t cmd_log_type; +extern parse_pgm_inst_t cmd_stack_space; +extern parse_pgm_inst_t cmd_scheduler; + +/* commands_ax12.c */ +extern parse_pgm_inst_t cmd_baudrate; +extern parse_pgm_inst_t cmd_uint16_read; +extern parse_pgm_inst_t cmd_uint16_write; +extern parse_pgm_inst_t cmd_uint8_read; +extern parse_pgm_inst_t cmd_uint8_write; + +/* commands_cs.c */ +extern parse_pgm_inst_t cmd_gain; +extern parse_pgm_inst_t cmd_gain_show; +extern parse_pgm_inst_t cmd_speed; +extern parse_pgm_inst_t cmd_speed_show; +extern parse_pgm_inst_t cmd_derivate_filter; +extern parse_pgm_inst_t cmd_derivate_filter_show; +extern parse_pgm_inst_t cmd_consign; +extern parse_pgm_inst_t cmd_maximum; +extern parse_pgm_inst_t cmd_maximum_show; +extern parse_pgm_inst_t cmd_quadramp; +extern parse_pgm_inst_t cmd_quadramp_show; +extern parse_pgm_inst_t cmd_cs_status; +extern parse_pgm_inst_t cmd_blocking_i; +extern parse_pgm_inst_t cmd_blocking_i_show; + +/* commands_sensorboard.c */ +extern parse_pgm_inst_t cmd_event; +extern parse_pgm_inst_t cmd_test; + +/* commands_scan.c */ +extern parse_pgm_inst_t cmd_sample; +extern parse_pgm_inst_t cmd_sadc; +extern parse_pgm_inst_t cmd_scan_params; +extern parse_pgm_inst_t cmd_scan_calibre; +extern parse_pgm_inst_t cmd_scan_do; +extern parse_pgm_inst_t cmd_scan_img; + + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + + /* commands_gen.c */ + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_bootloader, + (parse_pgm_inst_t *)&cmd_encoders, + (parse_pgm_inst_t *)&cmd_pwm, + (parse_pgm_inst_t *)&cmd_adc, + (parse_pgm_inst_t *)&cmd_sensor, + (parse_pgm_inst_t *)&cmd_log, + (parse_pgm_inst_t *)&cmd_log_show, + (parse_pgm_inst_t *)&cmd_log_type, + (parse_pgm_inst_t *)&cmd_stack_space, + (parse_pgm_inst_t *)&cmd_scheduler, + + /* commands_ax12.c */ + (parse_pgm_inst_t *)&cmd_baudrate, + (parse_pgm_inst_t *)&cmd_uint16_read, + (parse_pgm_inst_t *)&cmd_uint16_write, + (parse_pgm_inst_t *)&cmd_uint8_read, + (parse_pgm_inst_t *)&cmd_uint8_write, + + /* commands_cs.c */ + (parse_pgm_inst_t *)&cmd_gain, + (parse_pgm_inst_t *)&cmd_gain_show, + (parse_pgm_inst_t *)&cmd_speed, + (parse_pgm_inst_t *)&cmd_speed_show, + (parse_pgm_inst_t *)&cmd_consign, + (parse_pgm_inst_t *)&cmd_derivate_filter, + (parse_pgm_inst_t *)&cmd_derivate_filter_show, + (parse_pgm_inst_t *)&cmd_maximum, + (parse_pgm_inst_t *)&cmd_maximum_show, + (parse_pgm_inst_t *)&cmd_quadramp, + (parse_pgm_inst_t *)&cmd_quadramp_show, + (parse_pgm_inst_t *)&cmd_cs_status, + (parse_pgm_inst_t *)&cmd_blocking_i, + (parse_pgm_inst_t *)&cmd_blocking_i_show, + + /* commands_sensorboard.c */ + (parse_pgm_inst_t *)&cmd_event, + (parse_pgm_inst_t *)&cmd_test, + + /* commands_scan.c */ + (parse_pgm_inst_t *)&cmd_sample, + (parse_pgm_inst_t *)&cmd_sadc, + (parse_pgm_inst_t *)&cmd_scan_params, + (parse_pgm_inst_t *)&cmd_scan_calibre, + (parse_pgm_inst_t *)&cmd_scan_do, + (parse_pgm_inst_t *)&cmd_scan_img, + + NULL, +}; diff --git a/projects/microb2009/sensorboard/commands_ax12.c b/projects/microb2009/sensorboard/commands_ax12.c new file mode 100644 index 0000000..771fb30 --- /dev/null +++ b/projects/microb2009/sensorboard/commands_ax12.c @@ -0,0 +1,368 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_ax12.c,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" + +uint8_t addr_from_string(const char *s) +{ + /* 16 bits */ + if (!strcmp_P(s, PSTR("cw_angle_limit"))) + return AA_CW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("ccw_angle_limit"))) + return AA_CCW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("max_torque"))) + return AA_MAX_TORQUE_L; + if (!strcmp_P(s, PSTR("down_calibration"))) + return AA_DOWN_CALIBRATION_L; + if (!strcmp_P(s, PSTR("up_calibration"))) + return AA_UP_CALIBRATION_L; + if (!strcmp_P(s, PSTR("torque_limit"))) + return AA_TORQUE_LIMIT_L; + if (!strcmp_P(s, PSTR("position"))) + return AA_PRESENT_POSITION_L; + if (!strcmp_P(s, PSTR("speed"))) + return AA_PRESENT_SPEED_L; + if (!strcmp_P(s, PSTR("load"))) + return AA_PRESENT_LOAD_L; + if (!strcmp_P(s, PSTR("moving_speed"))) + return AA_MOVING_SPEED_L; + if (!strcmp_P(s, PSTR("model"))) + return AA_MODEL_NUMBER_L; + if (!strcmp_P(s, PSTR("goal_pos"))) + return AA_GOAL_POSITION_L; + if (!strcmp_P(s, PSTR("punch"))) + return AA_PUNCH_L; + + /* 8 bits */ + if (!strcmp_P(s, PSTR("firmware"))) + return AA_FIRMWARE; + if (!strcmp_P(s, PSTR("id"))) + return AA_ID; + if (!strcmp_P(s, PSTR("baudrate"))) + return AA_BAUD_RATE; + if (!strcmp_P(s, PSTR("delay"))) + return AA_DELAY_TIME; + if (!strcmp_P(s, PSTR("high_lim_temp"))) + return AA_HIGHEST_LIMIT_TEMP; + if (!strcmp_P(s, PSTR("low_lim_volt"))) + return AA_LOWEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("high_lim_volt"))) + return AA_HIGHEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("status_return"))) + return AA_STATUS_RETURN_LEVEL; + if (!strcmp_P(s, PSTR("alarm_led"))) + return AA_ALARM_LED; + if (!strcmp_P(s, PSTR("alarm_shutdown"))) + return AA_ALARM_SHUTDOWN; + if (!strcmp_P(s, PSTR("torque_enable"))) + return AA_TORQUE_ENABLE; + if (!strcmp_P(s, PSTR("led"))) + return AA_LED; + if (!strcmp_P(s, PSTR("cw_comp_margin"))) + return AA_CW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("ccw_comp_margin"))) + return AA_CCW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("cw_comp_slope"))) + return AA_CW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("ccw_comp_slope"))) + return AA_CCW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("voltage"))) + return AA_PRESENT_VOLTAGE; + if (!strcmp_P(s, PSTR("temp"))) + return AA_PRESENT_TEMP; + if (!strcmp_P(s, PSTR("reginst"))) + return AA_PRESENT_REGINST; + if (!strcmp_P(s, PSTR("moving"))) + return AA_MOVING; + if (!strcmp_P(s, PSTR("lock"))) + return AA_LOCK; + + return 0; +} + +/**********************************************************/ +/* Ax12_Stress */ + +/* this structure is filled when cmd_ax12_stress is parsed successfully */ +struct cmd_ax12_stress_result { + fixed_string_t arg0; + uint8_t id; +}; + +/* function called when cmd_ax12_stress is parsed successfully */ +static void cmd_ax12_stress_parsed(void *parsed_result, void *data) +{ + struct cmd_ax12_stress_result *res = parsed_result; + int i, nb_errs = 0; + uint8_t val; + microseconds t = time_get_us2(); + + for (i=0; i<1000; i++) { + if (AX12_read_byte(&gen.ax12, res->id, AA_ID, &val) != 0) + nb_errs ++; + } + + printf_P(PSTR("%d errors / 1000\r\n"), nb_errs); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %d ms\r\n"), (int)t); +} + +prog_char str_ax12_stress_arg0[] = "ax12_stress"; +parse_pgm_token_string_t cmd_ax12_stress_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_ax12_stress_result, arg0, str_ax12_stress_arg0); +parse_pgm_token_num_t cmd_ax12_stress_id = TOKEN_NUM_INITIALIZER(struct cmd_ax12_stress_result, id, UINT8); + +prog_char help_ax12_stress[] = "Stress an AX12 with 1000 'read id' commands"; +parse_pgm_inst_t cmd_ax12_stress = { + .f = cmd_ax12_stress_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_ax12_stress, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_ax12_stress_arg0, + (prog_void *)&cmd_ax12_stress_id, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_baudrate is parsed successfully */ +struct cmd_baudrate_result { + fixed_string_t arg0; + uint32_t arg1; +}; + +/* function called when cmd_baudrate is parsed successfully */ +static void cmd_baudrate_parsed(void * parsed_result, void * data) +{ + struct cmd_baudrate_result *res = parsed_result; + struct uart_config c; + + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); + uart_getconf(1, &c); + c.baudrate = res->arg1; + uart_setconf(1, &c); + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); +} + +prog_char str_baudrate_arg0[] = "baudrate"; +parse_pgm_token_string_t cmd_baudrate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0, str_baudrate_arg0); +parse_pgm_token_num_t cmd_baudrate_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1, UINT32); + +prog_char help_baudrate[] = "Change ax12 baudrate"; +parse_pgm_inst_t cmd_baudrate = { + .f = cmd_baudrate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_baudrate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_baudrate_arg0, + (prog_void *)&cmd_baudrate_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Uint16 */ + + +/* this structure is filled when cmd_uint16_read is parsed successfully */ +struct cmd_uint16_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint16_t val; +}; + +/* function called when cmd_uint16_read is parsed successfully */ +static void cmd_uint16_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint16_t val; + uint8_t addr = addr_from_string(res->arg1); + ret = AX12_read_int(&gen.ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.4x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint16_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint16_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0); +prog_char str_uint16_arg1[] = "moving_speed#model#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#down_calibration#up_calibration#torque_limit#" + "position#speed#load#punch"; +parse_pgm_token_string_t cmd_uint16_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1); +parse_pgm_token_num_t cmd_uint16_num = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, num, UINT8); + +prog_char help_uint16_read[] = "Read uint16 value (type, num)"; +parse_pgm_inst_t cmd_uint16_read = { + .f = cmd_uint16_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0, + (prog_void *)&cmd_uint16_arg1, + (prog_void *)&cmd_uint16_num, + NULL, + }, +}; + +/* function called when cmd_uint16_write is parsed successfully */ +static void cmd_uint16_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint8_t addr = addr_from_string(res->arg1); + printf_P(PSTR("writing %s: %d [0x%.4x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_int(&gen.ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint16_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint16_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0_w); +prog_char str_uint16_arg1_w[] = "moving_speed#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#torque_limit#punch"; +parse_pgm_token_string_t cmd_uint16_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1_w); +parse_pgm_token_num_t cmd_uint16_val = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, val, UINT16); + +prog_char help_uint16_write[] = "Write uint16 value (write, num, val)"; +parse_pgm_inst_t cmd_uint16_write = { + .f = cmd_uint16_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0_w, + (prog_void *)&cmd_uint16_arg1_w, + (prog_void *)&cmd_uint16_num, + (prog_void *)&cmd_uint16_val, + NULL, + }, +}; + +/**********************************************************/ +/* Uint8 */ + + +/* this structure is filled when cmd_uint8_read is parsed successfully */ +struct cmd_uint8_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint8_t val; +}; + +/* function called when cmd_uint8_read is parsed successfully */ +static void cmd_uint8_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t ret; + uint8_t val; + uint8_t addr = addr_from_string(res->arg1); + + ret = AX12_read_byte(&gen.ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.2x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint8_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint8_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0); +prog_char str_uint8_arg1[] = "id#firmware#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "voltage#temp#reginst#moving#lock"; +parse_pgm_token_string_t cmd_uint8_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1); +parse_pgm_token_num_t cmd_uint8_num = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, num, UINT8); + +prog_char help_uint8_read[] = "Read uint8 value (type, num)"; +parse_pgm_inst_t cmd_uint8_read = { + .f = cmd_uint8_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0, + (prog_void *)&cmd_uint8_arg1, + (prog_void *)&cmd_uint8_num, + NULL, + }, +}; + +/* function called when cmd_uint8_write is parsed successfully */ +static void cmd_uint8_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t addr = addr_from_string(res->arg1); + uint8_t ret; + printf_P(PSTR("writing %s: %d [0x%.2x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_byte(&gen.ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint8_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint8_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0_w); +prog_char str_uint8_arg1_w[] = "id#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "reginst#lock"; +parse_pgm_token_string_t cmd_uint8_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1_w); +parse_pgm_token_num_t cmd_uint8_val = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, val, UINT8); + +prog_char help_uint8_write[] = "Write uint8 value (write, num, val)"; +parse_pgm_inst_t cmd_uint8_write = { + .f = cmd_uint8_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0_w, + (prog_void *)&cmd_uint8_arg1_w, + (prog_void *)&cmd_uint8_num, + (prog_void *)&cmd_uint8_val, + NULL, + }, +}; diff --git a/projects/microb2009/sensorboard/commands_cs.c b/projects/microb2009/sensorboard/commands_cs.c new file mode 100644 index 0000000..690922a --- /dev/null +++ b/projects/microb2009/sensorboard/commands_cs.c @@ -0,0 +1,670 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_cs.c,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "cs.h" +#include "cmdline.h" + +struct csb_list { + const prog_char *name; + struct cs_block *csb; +}; + +prog_char csb_beacon_str[] = "beacon"; +prog_char csb_scanner_str[] = "scanner"; +struct csb_list csb_list[] = { + { .name = csb_beacon_str, .csb = &sensorboard.beacon }, + { .name = csb_scanner_str, .csb = &sensorboard.scanner }, +}; + +struct cmd_cs_result { + fixed_string_t cmdname; + fixed_string_t csname; +}; + +/* token to be used for all cs-related commands */ +prog_char str_csb_name[] = "beacon#scanner"; +parse_pgm_token_string_t cmd_csb_name_tok = TOKEN_STRING_INITIALIZER(struct cmd_cs_result, csname, str_csb_name); + +struct cs_block *cs_from_name(const char *name) +{ + int i; + + for (i=0; i<(sizeof(csb_list)/sizeof(*csb_list)); i++) { + if (!strcmp_P(name, csb_list[i].name)) + return csb_list[i].csb; + } + return NULL; +} + +/**********************************************************/ +/* Gains for control system */ + +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_result { + struct cmd_cs_result cs; + int16_t p; + int16_t i; + int16_t d; +}; + +/* function called when cmd_gain is parsed successfully */ +static void cmd_gain_parsed(void * parsed_result, void *show) +{ + struct cmd_gain_result *res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_gains(&csb->pid, res->p, res->i, res->d); + + printf_P(PSTR("%s %s %d %d %d\r\n"), + res->cs.cmdname, + res->cs.csname, + pid_get_gain_P(&csb->pid), + pid_get_gain_I(&csb->pid), + pid_get_gain_D(&csb->pid)); +} + +prog_char str_gain_arg0[] = "gain"; +parse_pgm_token_string_t cmd_gain_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, cs.cmdname, str_gain_arg0); +parse_pgm_token_num_t cmd_gain_p = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, p, INT16); +parse_pgm_token_num_t cmd_gain_i = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, i, INT16); +parse_pgm_token_num_t cmd_gain_d = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, d, INT16); + +prog_char help_gain[] = "Set gain values for PID"; +parse_pgm_inst_t cmd_gain = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_gain_p, + (prog_void *)&cmd_gain_i, + (prog_void *)&cmd_gain_d, + NULL, + }, +}; + +/* show */ +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_gain_show_arg[] = "show"; +parse_pgm_token_string_t cmd_gain_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_gain_show_result, show, str_gain_show_arg); + +prog_char help_gain_show[] = "Show gain values for PID"; +parse_pgm_inst_t cmd_gain_show = { + .f = cmd_gain_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_gain_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_gain_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Speeds for control system */ + +/* this structure is filled when cmd_speed is parsed successfully */ +struct cmd_speed_result { + struct cmd_cs_result cs; + uint16_t s; +}; + +/* function called when cmd_speed is parsed successfully */ +static void cmd_speed_parsed(void *parsed_result, void *show) +{ + struct cmd_speed_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + +#if notyet + if (!show) + ramp_set_vars(&csb->ramp, res->s, res->s); /* set speed */ + + printf_P(PSTR("%s %lu\r\n"), + res->cs.csname, + ext.r_b.var_pos); +#else + printf_P(PSTR("TODO\r\n")); +#endif +} + +prog_char str_speed_arg0[] = "speed"; +parse_pgm_token_string_t cmd_speed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, cs.cmdname, str_speed_arg0); +parse_pgm_token_num_t cmd_speed_s = TOKEN_NUM_INITIALIZER(struct cmd_speed_result, s, UINT16); + +prog_char help_speed[] = "Set speed values for ramp filter"; +parse_pgm_inst_t cmd_speed = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_speed_s, + NULL, + }, +}; + +/* show */ +struct cmd_speed_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_speed_show_arg[] = "show"; +parse_pgm_token_string_t cmd_speed_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_speed_show_result, show, str_speed_show_arg); + +prog_char help_speed_show[] = "Show speed values for ramp filter"; +parse_pgm_inst_t cmd_speed_show = { + .f = cmd_speed_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_speed_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_speed_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Derivate_Filters for control system */ + +/* this structure is filled when cmd_derivate_filter is parsed successfully */ +struct cmd_derivate_filter_result { + struct cmd_cs_result cs; + uint8_t size; +}; + +/* function called when cmd_derivate_filter is parsed successfully */ +static void cmd_derivate_filter_parsed(void *parsed_result, void *show) +{ + struct cmd_derivate_filter_result * res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_derivate_filter(&csb->pid, res->size); + + printf_P(PSTR("%s %s %u\r\n"), + res->cs.cmdname, + res->cs.csname, + pid_get_derivate_filter(&csb->pid)); +} + +prog_char str_derivate_filter_arg0[] = "derivate_filter"; +parse_pgm_token_string_t cmd_derivate_filter_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_derivate_filter_result, cs.cmdname, str_derivate_filter_arg0); +parse_pgm_token_num_t cmd_derivate_filter_size = TOKEN_NUM_INITIALIZER(struct cmd_derivate_filter_result, size, UINT32); + +prog_char help_derivate_filter[] = "Set derivate_filter values for PID (in, I, out)"; +parse_pgm_inst_t cmd_derivate_filter = { + .f = cmd_derivate_filter_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_derivate_filter, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_derivate_filter_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_derivate_filter_size, + NULL, + }, +}; + +/* show */ + +struct cmd_derivate_filter_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_derivate_filter_show_arg[] = "show"; +parse_pgm_token_string_t cmd_derivate_filter_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_derivate_filter_show_result, show, str_derivate_filter_show_arg); + +prog_char help_derivate_filter_show[] = "Show derivate_filter values for PID"; +parse_pgm_inst_t cmd_derivate_filter_show = { + .f = cmd_derivate_filter_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_derivate_filter_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_derivate_filter_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_derivate_filter_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Consign for control system */ + +/* this structure is filled when cmd_consign is parsed successfully */ +struct cmd_consign_result { + struct cmd_cs_result cs; + int32_t p; +}; + +/* function called when cmd_consign is parsed successfully */ +static void cmd_consign_parsed(void * parsed_result, void *data) +{ + struct cmd_consign_result * res = parsed_result; + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + cs_set_consign(&csb->cs, res->p); +} + +prog_char str_consign_arg0[] = "consign"; +parse_pgm_token_string_t cmd_consign_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_consign_result, cs.cmdname, str_consign_arg0); +parse_pgm_token_num_t cmd_consign_p = TOKEN_NUM_INITIALIZER(struct cmd_consign_result, p, INT32); + +prog_char help_consign[] = "Set consign value"; +parse_pgm_inst_t cmd_consign = { + .f = cmd_consign_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_consign, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_consign_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_consign_p, + NULL, + }, +}; + + +/**********************************************************/ +/* Maximums for control system */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_result { + struct cmd_cs_result cs; + uint32_t in; + uint32_t i; + uint32_t out; +}; + +/* function called when cmd_maximum is parsed successfully */ +static void cmd_maximum_parsed(void *parsed_result, void *show) +{ + struct cmd_maximum_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + pid_set_maximums(&csb->pid, res->in, res->i, res->out); + + printf_P(PSTR("maximum %s %lu %lu %lu\r\n"), + res->cs.csname, + pid_get_max_in(&csb->pid), + pid_get_max_I(&csb->pid), + pid_get_max_out(&csb->pid)); +} + +prog_char str_maximum_arg0[] = "maximum"; +parse_pgm_token_string_t cmd_maximum_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, cs.cmdname, str_maximum_arg0); +parse_pgm_token_num_t cmd_maximum_in = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, in, UINT32); +parse_pgm_token_num_t cmd_maximum_i = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, i, UINT32); +parse_pgm_token_num_t cmd_maximum_out = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, out, UINT32); + +prog_char help_maximum[] = "Set maximum values for PID (in, I, out)"; +parse_pgm_inst_t cmd_maximum = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_maximum_in, + (prog_void *)&cmd_maximum_i, + (prog_void *)&cmd_maximum_out, + NULL, + }, +}; + +/* show */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; +prog_char str_maximum_show_arg[] = "show"; +parse_pgm_token_string_t cmd_maximum_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_maximum_show_result, show, str_maximum_show_arg); + +prog_char help_maximum_show[] = "Show maximum values for PID"; +parse_pgm_inst_t cmd_maximum_show = { + .f = cmd_maximum_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_maximum_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_maximum_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Quadramp for control system */ + +/* this structure is filled when cmd_quadramp is parsed successfully */ +struct cmd_quadramp_result { + struct cmd_cs_result cs; + uint32_t ap; + uint32_t an; + uint32_t sp; + uint32_t sn; +}; + +/* function called when cmd_quadramp is parsed successfully */ +static void cmd_quadramp_parsed(void *parsed_result, void *show) +{ + struct cmd_quadramp_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) { + quadramp_set_1st_order_vars(&csb->qr, res->sp, res->sn); + quadramp_set_2nd_order_vars(&csb->qr, res->ap, res->an); + } + + printf_P(PSTR("quadramp %s %ld %ld %ld %ld\r\n"), + res->cs.csname, + csb->qr.var_2nd_ord_pos, + csb->qr.var_2nd_ord_neg, + csb->qr.var_1st_ord_pos, + csb->qr.var_1st_ord_neg); +} + +prog_char str_quadramp_arg0[] = "quadramp"; +parse_pgm_token_string_t cmd_quadramp_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, cs.cmdname, str_quadramp_arg0); +parse_pgm_token_num_t cmd_quadramp_ap = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, ap, UINT32); +parse_pgm_token_num_t cmd_quadramp_an = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, an, UINT32); +parse_pgm_token_num_t cmd_quadramp_sp = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sp, UINT32); +parse_pgm_token_num_t cmd_quadramp_sn = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sn, UINT32); + +prog_char help_quadramp[] = "Set quadramp values (acc+, acc-, speed+, speed-)"; +parse_pgm_inst_t cmd_quadramp = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_quadramp_ap, + (prog_void *)&cmd_quadramp_an, + (prog_void *)&cmd_quadramp_sp, + (prog_void *)&cmd_quadramp_sn, + + NULL, + }, +}; + +/* show */ + +struct cmd_quadramp_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_quadramp_show_arg[] = "show"; +parse_pgm_token_string_t cmd_quadramp_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_show_result, show, str_quadramp_show_arg); + +prog_char help_quadramp_show[] = "Get quadramp values for control system"; +parse_pgm_inst_t cmd_quadramp_show = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_quadramp_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_quadramp_show_arg, + NULL, + }, +}; + + + +/**********************************************************/ +/* cs_status show for control system */ + +/* this structure is filled when cmd_cs_status is parsed successfully */ +struct cmd_cs_status_result { + struct cmd_cs_result cs; + fixed_string_t arg; +}; + +/* function called when cmd_cs_status is parsed successfully */ +static void cmd_cs_status_parsed(void *parsed_result, void *data) +{ + struct cmd_cs_status_result *res = parsed_result; + struct cs_block *csb; + uint8_t loop = 0; + uint8_t print_pid = 0, print_cs = 0; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + if (strcmp_P(res->arg, PSTR("on")) == 0) { + csb->on = 1; + printf_P(PSTR("%s is on\r\n"), res->cs.csname); + return; + } + else if (strcmp_P(res->arg, PSTR("off")) == 0) { + csb->on = 0; + printf_P(PSTR("%s is off\r\n"), res->cs.csname); + return; + } + else if (strcmp_P(res->arg, PSTR("show")) == 0) { + print_cs = 1; + } + else if (strcmp_P(res->arg, PSTR("loop_show")) == 0) { + loop = 1; + print_cs = 1; + } + else if (strcmp_P(res->arg, PSTR("pid_show")) == 0) { + print_pid = 1; + } + else if (strcmp_P(res->arg, PSTR("pid_loop_show")) == 0) { + print_pid = 1; + loop = 1; + } + + printf_P(PSTR("%s cs is %s\r\n"), res->cs.csname, csb->on ? "on":"off"); + do { + if (print_cs) + dump_cs(res->cs.csname, &csb->cs); + if (print_pid) + dump_pid(res->cs.csname, &csb->pid); + wait_ms(100); + } while(loop && !cmdline_keypressed()); +} + +prog_char str_cs_status_arg0[] = "cs_status"; +parse_pgm_token_string_t cmd_cs_status_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_cs_status_result, cs.cmdname, str_cs_status_arg0); +prog_char str_cs_status_arg[] = "pid_show#pid_loop_show#show#loop_show#on#off"; +parse_pgm_token_string_t cmd_cs_status_arg = TOKEN_STRING_INITIALIZER(struct cmd_cs_status_result, arg, str_cs_status_arg); + +prog_char help_cs_status[] = "Show cs status"; +parse_pgm_inst_t cmd_cs_status = { + .f = cmd_cs_status_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_cs_status, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_cs_status_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_cs_status_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Blocking_I for control system */ + +/* this structure is filled when cmd_blocking_i is parsed successfully */ +struct cmd_blocking_i_result { + struct cmd_cs_result cs; + int32_t k1; + int32_t k2; + uint32_t i; + uint16_t cpt; +}; + +/* function called when cmd_blocking_i is parsed successfully */ +static void cmd_blocking_i_parsed(void *parsed_result, void *show) +{ + struct cmd_blocking_i_result * res = parsed_result; + + struct cs_block *csb; + + csb = cs_from_name(res->cs.csname); + if (csb == NULL) { + printf_P(PSTR("null csb\r\n")); + return; + } + + if (!show) + bd_set_current_thresholds(&csb->bd, res->k1, res->k2, + res->i, res->cpt); + + printf_P(PSTR("%s %s %ld %ld %ld %d\r\n"), + res->cs.cmdname, + res->cs.csname, + csb->bd.k1, + csb->bd.k2, + csb->bd.i_thres, + csb->bd.cpt_thres); +} + +prog_char str_blocking_i_arg0[] = "blocking"; +parse_pgm_token_string_t cmd_blocking_i_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_blocking_i_result, cs.cmdname, str_blocking_i_arg0); +parse_pgm_token_num_t cmd_blocking_i_k1 = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, k1, INT32); +parse_pgm_token_num_t cmd_blocking_i_k2 = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, k2, INT32); +parse_pgm_token_num_t cmd_blocking_i_i = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, i, UINT32); +parse_pgm_token_num_t cmd_blocking_i_cpt = TOKEN_NUM_INITIALIZER(struct cmd_blocking_i_result, cpt, UINT16); + +prog_char help_blocking_i[] = "Set blocking detection values (k1, k2, i, cpt)"; +parse_pgm_inst_t cmd_blocking_i = { + .f = cmd_blocking_i_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_blocking_i, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_blocking_i_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_blocking_i_k1, + (prog_void *)&cmd_blocking_i_k2, + (prog_void *)&cmd_blocking_i_i, + (prog_void *)&cmd_blocking_i_cpt, + NULL, + }, +}; + +/* show */ + +struct cmd_blocking_i_show_result { + struct cmd_cs_result cs; + fixed_string_t show; +}; + +prog_char str_blocking_i_show_arg[] = "show"; +parse_pgm_token_string_t cmd_blocking_i_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_blocking_i_show_result, show, str_blocking_i_show_arg); + +prog_char help_blocking_i_show[] = "Show blocking detection values"; +parse_pgm_inst_t cmd_blocking_i_show = { + .f = cmd_blocking_i_parsed, /* function to call */ + .data = (void *)1, /* 2nd arg of func */ + .help_str = help_blocking_i_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_blocking_i_arg0, + (prog_void *)&cmd_csb_name_tok, + (prog_void *)&cmd_blocking_i_show_arg, + NULL, + }, +}; + + diff --git a/projects/microb2009/sensorboard/commands_gen.c b/projects/microb2009/sensorboard/commands_gen.c new file mode 100644 index 0000000..9f7cdd6 --- /dev/null +++ b/projects/microb2009/sensorboard/commands_gen.c @@ -0,0 +1,573 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_gen.c,v 1.4 2009-05-27 20:04:07 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <encoders_spi.h> +#include <adc.h> + +#include <scheduler.h> +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include <diagnostic.h> + +#include "main.h" +#include "cmdline.h" +#include "sensor.h" + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(void * parsed_result, void * data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Bootloader */ + +/* this structure is filled when cmd_bootloader is parsed successfully */ +struct cmd_bootloader_result { + fixed_string_t arg0; +}; + +/* function called when cmd_bootloader is parsed successfully */ +static void cmd_bootloader_parsed(void *parsed_result, void *data) +{ + bootloader(); +} + +prog_char str_bootloader_arg0[] = "bootloader"; +parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0); + +prog_char help_bootloader[] = "Launch the bootloader"; +parse_pgm_inst_t cmd_bootloader = { + .f = cmd_bootloader_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_bootloader, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_bootloader_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Encoders tests */ + +/* this structure is filled when cmd_encoders is parsed successfully */ +struct cmd_encoders_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_encoders is parsed successfully */ +static void cmd_encoders_parsed(void *parsed_result, void *data) +{ + struct cmd_encoders_result *res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("reset"))) { + encoders_spi_set_value((void *)0, 0); + encoders_spi_set_value((void *)1, 0); + encoders_spi_set_value((void *)2, 0); + encoders_spi_set_value((void *)3, 0); + return; + } + + /* show */ + while(!cmdline_keypressed()) { + printf_P(PSTR("% .8ld % .8ld % .8ld % .8ld\r\n"), + encoders_spi_get_value((void *)0), + encoders_spi_get_value((void *)1), + encoders_spi_get_value((void *)2), + encoders_spi_get_value((void *)3)); + wait_ms(100); + } +} + +prog_char str_encoders_arg0[] = "encoders"; +parse_pgm_token_string_t cmd_encoders_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg0, str_encoders_arg0); +prog_char str_encoders_arg1[] = "show#reset"; +parse_pgm_token_string_t cmd_encoders_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg1, str_encoders_arg1); + +prog_char help_encoders[] = "Show encoders values"; +parse_pgm_inst_t cmd_encoders = { + .f = cmd_encoders_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_encoders, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_encoders_arg0, + (prog_void *)&cmd_encoders_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Scheduler show */ + +/* this structure is filled when cmd_scheduler is parsed successfully */ +struct cmd_scheduler_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_scheduler is parsed successfully */ +static void cmd_scheduler_parsed(void *parsed_result, void *data) +{ + scheduler_dump_events(); +} + +prog_char str_scheduler_arg0[] = "scheduler"; +parse_pgm_token_string_t cmd_scheduler_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg0, str_scheduler_arg0); +prog_char str_scheduler_arg1[] = "show"; +parse_pgm_token_string_t cmd_scheduler_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg1, str_scheduler_arg1); + +prog_char help_scheduler[] = "Show scheduler events"; +parse_pgm_inst_t cmd_scheduler = { + .f = cmd_scheduler_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scheduler, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scheduler_arg0, + (prog_void *)&cmd_scheduler_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pwms tests */ + +/* this structure is filled when cmd_pwm is parsed successfully */ +struct cmd_pwm_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; +}; + +/* function called when cmd_pwm is parsed successfully */ +static void cmd_pwm_parsed(void * parsed_result, void * data) +{ + void * pwm_ptr = NULL; + struct cmd_pwm_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("1(4A)"))) + pwm_ptr = &gen.pwm1_4A; + else if (!strcmp_P(res->arg1, PSTR("2(4B)"))) + pwm_ptr = &gen.pwm2_4B; + else if (!strcmp_P(res->arg1, PSTR("3(1A)"))) + pwm_ptr = &gen.pwm3_1A; + else if (!strcmp_P(res->arg1, PSTR("4(1B)"))) + pwm_ptr = &gen.pwm4_1B; + + else if (!strcmp_P(res->arg1, PSTR("s1(3C)"))) + pwm_ptr = &gen.servo1; + else if (!strcmp_P(res->arg1, PSTR("s2(5A)"))) + pwm_ptr = &gen.servo2; + else if (!strcmp_P(res->arg1, PSTR("s3(5B)"))) + pwm_ptr = &gen.servo3; + else if (!strcmp_P(res->arg1, PSTR("s3(5C)"))) + pwm_ptr = &gen.servo4; + + if (pwm_ptr) + pwm_ng_set(pwm_ptr, res->arg2); + + printf_P(PSTR("done\r\n")); +} + +prog_char str_pwm_arg0[] = "pwm"; +parse_pgm_token_string_t cmd_pwm_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg0, str_pwm_arg0); +prog_char str_pwm_arg1[] = "1(4A)#2(4B)#3(1A)#4(1B)#s1(3C)#s2(5A)#s3(5B)#s4(5C)"; +parse_pgm_token_string_t cmd_pwm_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg1, str_pwm_arg1); +parse_pgm_token_num_t cmd_pwm_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pwm_result, arg2, INT16); + +prog_char help_pwm[] = "Set pwm values [-4096 ; 4095]"; +parse_pgm_inst_t cmd_pwm = { + .f = cmd_pwm_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pwm, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pwm_arg0, + (prog_void *)&cmd_pwm_arg1, + (prog_void *)&cmd_pwm_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Adcs tests */ + +/* this structure is filled when cmd_adc is parsed successfully */ +struct cmd_adc_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_adc is parsed successfully */ +static void cmd_adc_parsed(void *parsed_result, void *data) +{ + struct cmd_adc_result *res = parsed_result; + uint8_t i, loop = 0; + + if (!strcmp_P(res->arg1, PSTR("loop_show"))) + loop = 1; + + do { + printf_P(PSTR("ADC values: ")); + for (i=0; i<ADC_MAX; i++) { + printf_P(PSTR("%.4d "), sensor_get_adc(i)); + } + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (loop && !cmdline_keypressed()); +} + +prog_char str_adc_arg0[] = "adc"; +parse_pgm_token_string_t cmd_adc_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_adc_result, arg0, str_adc_arg0); +prog_char str_adc_arg1[] = "show#loop_show"; +parse_pgm_token_string_t cmd_adc_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_adc_result, arg1, str_adc_arg1); + +prog_char help_adc[] = "Show adc values"; +parse_pgm_inst_t cmd_adc = { + .f = cmd_adc_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_adc, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_adc_arg0, + (prog_void *)&cmd_adc_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Sensors tests */ + +/* this structure is filled when cmd_sensor is parsed successfully */ +struct cmd_sensor_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_sensor is parsed successfully */ +static void cmd_sensor_parsed(void *parsed_result, void *data) +{ + struct cmd_sensor_result *res = parsed_result; + uint8_t i, loop = 0; + + if (!strcmp_P(res->arg1, PSTR("loop_show"))) + loop = 1; + + do { + printf_P(PSTR("SENSOR values: ")); + for (i=0; i<SENSOR_MAX; i++) { + printf_P(PSTR("%d "), !!sensor_get(i)); + } + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (loop && !cmdline_keypressed()); +} + +prog_char str_sensor_arg0[] = "sensor"; +parse_pgm_token_string_t cmd_sensor_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_sensor_result, arg0, str_sensor_arg0); +prog_char str_sensor_arg1[] = "show#loop_show"; +parse_pgm_token_string_t cmd_sensor_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_sensor_result, arg1, str_sensor_arg1); + +prog_char help_sensor[] = "Show sensor values"; +parse_pgm_inst_t cmd_sensor = { + .f = cmd_sensor_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sensor, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_sensor_arg0, + (prog_void *)&cmd_sensor_arg1, + NULL, + }, +}; + + +/**********************************************************/ +/* Log */ + +/* this structure is filled when cmd_log is parsed successfully */ +struct cmd_log_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t arg2; + fixed_string_t arg3; +}; + +/* keep it sync with string choice */ +static const prog_char uart_log[] = "uart"; +static const prog_char i2c_log[] = "i2c"; +static const prog_char i2cproto_log[] = "i2cproto"; +static const prog_char sensor_log[] = "sensor"; +static const prog_char block_log[] = "bd"; +static const prog_char beacon_log[] = "beacon"; +static const prog_char scanner_log[] = "scanner"; +static const prog_char imgprocess_log[] = "imgprocess"; + +struct log_name_and_num { + const prog_char * name; + uint8_t num; +}; + +static const struct log_name_and_num log_name_and_num[] = { + { uart_log, E_UART }, + { i2c_log, E_I2C }, + { i2cproto_log, E_USER_I2C_PROTO }, + { sensor_log, E_USER_SENSOR }, + { block_log, E_BLOCKING_DETECTION_MANAGER }, + { beacon_log, E_USER_BEACON }, + { scanner_log, E_USER_SCANNER }, + { imgprocess_log, E_USER_IMGPROCESS }, +}; + +static uint8_t +log_name2num(const char * s) +{ + uint8_t i; + + for (i=0; i<sizeof(log_name_and_num)/sizeof(struct log_name_and_num); i++) { + if (!strcmp_P(s, log_name_and_num[i].name)) { + return log_name_and_num[i].num; + } + } + return 0; +} + +const prog_char * +log_num2name(uint8_t num) +{ + uint8_t i; + + for (i=0; i<sizeof(log_name_and_num)/sizeof(struct log_name_and_num); i++) { + if (num == log_name_and_num[i].num) { + return log_name_and_num[i].name; + } + } + return NULL; +} + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_do_show(void) +{ + uint8_t i, empty=1; + const prog_char * name; + + printf_P(PSTR("log level is %d\r\n"), gen.log_level); + for (i=0; i<NB_LOGS; i++) { + name = log_num2name(gen.logs[i]); + if (name) { + printf_P(PSTR("log type %S is on\r\n"), name); + empty = 0; + } + } + if (empty) + printf_P(PSTR("no log configured\r\n"), gen.logs[i]); +} + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_parsed(void * parsed_result, void * data) +{ + struct cmd_log_result *res = (struct cmd_log_result *) parsed_result; + + if (!strcmp_P(res->arg1, PSTR("level"))) { + gen.log_level = res->arg2; + } + + /* else it is a show */ + cmd_log_do_show(); +} + +prog_char str_log_arg0[] = "log"; +parse_pgm_token_string_t cmd_log_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg0, str_log_arg0); +prog_char str_log_arg1[] = "level"; +parse_pgm_token_string_t cmd_log_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1); +parse_pgm_token_num_t cmd_log_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_log_result, arg2, INT32); + +prog_char help_log[] = "Set log options: level (0 -> 5)"; +parse_pgm_inst_t cmd_log = { + .f = cmd_log_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1, + (prog_void *)&cmd_log_arg2, + NULL, + }, +}; + +prog_char str_log_arg1_show[] = "show"; +parse_pgm_token_string_t cmd_log_arg1_show = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1_show); + +prog_char help_log_show[] = "Show configured logs"; +parse_pgm_inst_t cmd_log_show = { + .f = cmd_log_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1_show, + NULL, + }, +}; + +/* this structure is filled when cmd_log is parsed successfully */ +struct cmd_log_type_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_log is parsed successfully */ +static void cmd_log_type_parsed(void * parsed_result, void * data) +{ + struct cmd_log_type_result *res = (struct cmd_log_type_result *) parsed_result; + uint8_t lognum; + uint8_t i; + + lognum = log_name2num(res->arg2); + if (lognum == 0) { + printf_P(PSTR("Cannot find log num\r\n")); + return; + } + + if (!strcmp_P(res->arg3, PSTR("on"))) { + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == lognum) { + printf_P(PSTR("Already on\r\n")); + return; + } + } + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == 0) { + gen.logs[i] = lognum; + break; + } + } + if (i==NB_LOGS) { + printf_P(PSTR("no more room\r\n")); + } + } + else if (!strcmp_P(res->arg3, PSTR("off"))) { + for (i=0; i<NB_LOGS; i++) { + if (gen.logs[i] == lognum) { + gen.logs[i] = 0; + break; + } + } + if (i==NB_LOGS) { + printf_P(PSTR("already off\r\n")); + } + } + cmd_log_do_show(); +} + +prog_char str_log_arg1_type[] = "type"; +parse_pgm_token_string_t cmd_log_arg1_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg1, str_log_arg1_type); +/* keep it sync with log_name_and_num above */ +prog_char str_log_arg2_type[] = "uart#i2c#i2cproto#sensor#bd#beacon#scanner#imgprocess"; +parse_pgm_token_string_t cmd_log_arg2_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg2, str_log_arg2_type); +prog_char str_log_arg3[] = "on#off"; +parse_pgm_token_string_t cmd_log_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg3, str_log_arg3); + +prog_char help_log_type[] = "Set log type"; +parse_pgm_inst_t cmd_log_type = { + .f = cmd_log_type_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_log_type, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_log_arg0, + (prog_void *)&cmd_log_arg1_type, + (prog_void *)&cmd_log_arg2_type, + (prog_void *)&cmd_log_arg3, + NULL, + }, +}; + + +/**********************************************************/ +/* Stack_Space */ + +/* this structure is filled when cmd_stack_space is parsed successfully */ +struct cmd_stack_space_result { + fixed_string_t arg0; +}; + +/* function called when cmd_stack_space is parsed successfully */ +static void cmd_stack_space_parsed(void *parsed_result, void *data) +{ + printf("res stack: %d\r\n", min_stack_space_available()); + +} + +prog_char str_stack_space_arg0[] = "stack_space"; +parse_pgm_token_string_t cmd_stack_space_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_stack_space_result, arg0, str_stack_space_arg0); + +prog_char help_stack_space[] = "Display remaining stack space"; +parse_pgm_inst_t cmd_stack_space = { + .f = cmd_stack_space_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_stack_space, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_stack_space_arg0, + NULL, + }, +}; diff --git a/projects/microb2009/sensorboard/commands_scan.c b/projects/microb2009/sensorboard/commands_scan.c new file mode 100644 index 0000000..e252298 --- /dev/null +++ b/projects/microb2009/sensorboard/commands_scan.c @@ -0,0 +1,401 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_scan.c,v 1.1 2009-05-27 20:04:07 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> +#include <time.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include <adc.h> + +#include <math.h> + +#include "main.h" +#include "cmdline.h" +#include "../common/i2c_commands.h" +#include "i2c_protocol.h" +#include "actuator.h" + +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> + +#include "img_processing.h" +#include "scanner.h" + + + +/**********************************************************/ +/* sample ADC */ +/* +extern uint16_t sample_i; +extern float scan_offset_a; +extern float scan_offset_b; +*/ +extern struct scan_params scan_params; + +//extern uint16_t sample_tab[MAX_SAMPLE]; +/* this structure is filled when cmd_sample is parsed successfully */ +struct cmd_sample_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint16_t offset_b; + float offset_a; + uint16_t dump_speed; + uint8_t filter; +}; + +extern int32_t pos_start_scan; +/* function called when cmd_sample is parsed successfully */ + +#define MAX_OBJECTS 10 +Object_bb sac_obj[MAX_OBJECTS]; +static void cmd_sample_parsed(void * parsed_result, void * data) +{ + struct cmd_sample_result * res = parsed_result; + uint16_t i; + + printf_P(PSTR("cmd sample called\r\n")); + printf_P(PSTR("arg %s %d\r\n"), res->arg1, res->offset_b); + + quadramp_set_1st_order_vars(&sensorboard.scanner.qr, res->dump_speed, res->dump_speed); /* set speed */ + + + scan_params.offset_b = (((float)res->offset_b)*M_PI/180.); + scan_params.offset_a = (((float)res->offset_a)*M_PI/180.); + scan_params.filter = res->filter; + + if (!strcmp_P(res->arg1, PSTR("start"))) { + scan_params.sample_i = MAX_SAMPLE; + scan_params.pos_start_scan = encoders_spi_get_value_scanner(SCANNER_ENC); + //printf_P(PSTR("start scan at pos %ld\r\n"), scan_params.pos_start_scan); + + memset(scan_params.sample_tab, 0xff, MAX_SAMPLE*sizeof(uint8_t)); + + + cs_set_consign(&sensorboard.scanner.cs, scan_params.pos_start_scan+SCANNER_STEP_TOUR*200L); + //printf_P(PSTR("scan dst %ld\r\n"), scan_params.pos_start_scan+SCANNER_STEP_TOUR*200L); + + scan_params.last_col_n = 0; + scan_params.last_row_n = 0; + scan_params.last_sample = 0; + + } + else if (!strcmp_P(res->arg1, PSTR("dump"))) { + printf_P(PSTR("start object detection\r\n")); + for (i=0;i<MAX_OBJECTS;i++){ + sac_obj[i].x_min = 0; + sac_obj[i].x_max = 0; + sac_obj[i].y_min = 0; + sac_obj[i].y_max = 0; + } + + //parcour_img(sample_tab, PIX_PER_SCAN, MAX_SAMPLE/PIX_PER_SCAN, sac_obj, MAX_OBJECTS); + /* + process_img(scan_params.sample_tab, PIX_PER_SCAN, MAX_SAMPLE/PIX_PER_SCAN, + 4, 1, + 0, 15, 15, + 1); + */ + + for (i=0;i<MAX_OBJECTS;i++){ + printf_P(PSTR("obj: %d %d %d %d\r\n"), + sac_obj[i].x_min, + sac_obj[i].y_min, + sac_obj[i].x_max, + sac_obj[i].y_max); + } + + printf_P(PSTR("start dumping %ld\r\n"), PIX_PER_SCAN); + + for (i=0;i<MAX_SAMPLE;i++) + printf_P(PSTR("%d\r\n"),scan_params.sample_tab[i]); + + printf_P(PSTR("end dumping (pos: %ld)\r\n"), + encoders_spi_get_value_scanner((void *)SCANNER_ENC)); + } + +} + +prog_char str_sample_arg0[] = "sample"; +parse_pgm_token_string_t cmd_sample_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_sample_result, arg0, str_sample_arg0); +prog_char str_sample_arg1[] = "start#dump"; +parse_pgm_token_string_t cmd_sample_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_sample_result, arg1, str_sample_arg1); +parse_pgm_token_num_t cmd_sample_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_sample_result, offset_b, UINT16); +parse_pgm_token_num_t cmd_sample_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_sample_result, offset_a, FLOAT); +parse_pgm_token_num_t cmd_sample_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_sample_result, dump_speed, UINT16); +parse_pgm_token_num_t cmd_sample_arg5 = TOKEN_NUM_INITIALIZER(struct cmd_sample_result, filter, UINT8); + +prog_char help_sample[] = "Sample func off_a_mot, off_a_angl, dump_speed"; +parse_pgm_inst_t cmd_sample = { + .f = cmd_sample_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sample, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_sample_arg0, + (prog_void *)&cmd_sample_arg1, + (prog_void *)&cmd_sample_arg2, + (prog_void *)&cmd_sample_arg3, + (prog_void *)&cmd_sample_arg4, + (prog_void *)&cmd_sample_arg5, + NULL, + }, +}; + + + + +/**********************************************************/ +/* sadc tests */ + +/* this structure is filled when cmd_sadc is parsed successfully */ +struct cmd_sadc_result { + fixed_string_t arg0; +}; + +/* function called when cmd_sadc is parsed successfully */ +static void cmd_sadc_parsed(void *parsed_result, void *data) +{ + + printf_P(PSTR("Scan ADC values:\r\n")); + do { + printf_P(PSTR("%.4d "), adc_get_value( ADC_REF_AVCC | MUX_ADC13 )); + printf_P(PSTR("\r\n")); + wait_ms(100); + } while (!cmdline_keypressed()); +} + +prog_char str_sadc_arg0[] = "sadc"; +parse_pgm_token_string_t cmd_sadc_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_sadc_result, arg0, str_sadc_arg0); + +prog_char help_sadc[] = "Show sadc values"; +parse_pgm_inst_t cmd_sadc = { + .f = cmd_sadc_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sadc, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_sadc_arg0, + NULL, + }, +}; + + + + +/**********************************************************/ +/* set scanner params */ + +/* this structure is filled when cmd_scan_params is parsed successfully */ +struct cmd_scan_params_result { + fixed_string_t arg0; + int speed; + uint8_t debug; +}; + +/* function called when cmd_scan_params is parsed successfully */ +static void cmd_scan_params_parsed(void * parsed_result, void * data) +{ + struct cmd_scan_params_result * res = parsed_result; + + scan_params.speed = res->speed; + scan_params.debug = res->debug; + +} + +prog_char str_scan_params_arg0[] = "scan_params"; +parse_pgm_token_string_t cmd_scan_params_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scan_params_result, arg0, str_scan_params_arg0); +parse_pgm_token_num_t cmd_scan_params_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_scan_params_result, speed, INT16); +parse_pgm_token_num_t cmd_scan_params_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_scan_params_result, debug, UINT8); + +prog_char help_scan_params[] = "Set scanner params (speed, debug)"; +parse_pgm_inst_t cmd_scan_params = { + .f = cmd_scan_params_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sample, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scan_params_arg0, + (prog_void *)&cmd_scan_params_arg1, + (prog_void *)&cmd_scan_params_arg2, + NULL, + }, +}; + + + +/**********************************************************/ +/* set scanner calibration */ + +/* this structure is filled when cmd_scan_calibre is parsed successfully */ +struct cmd_scan_calibre_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_scan_calibre is parsed successfully */ +static void cmd_scan_calibre_parsed(void * parsed_result, void * data) +{ + struct cmd_scan_calibre_result * res = parsed_result; + + printf_P(PSTR("Starting scanner autocalibration\r\n")); + + + if (!strcmp_P(res->arg1, PSTR("mirror"))) { + scanner_calibre_mirror(); + } + else{ + scanner_calibre_laser(); + } +} + +prog_char str_scan_calibre_arg0[] = "scan_calibre"; + +prog_char str_scan_calibre_what_arg1[] = "mirror#laser"; +parse_pgm_token_string_t cmd_scan_calibre_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scan_calibre_result, arg0, str_scan_calibre_arg0); +parse_pgm_token_string_t cmd_scan_calibre_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scan_calibre_result, arg1, str_scan_calibre_what_arg1); + + +prog_char help_scan_calibre[] = "Scanner auto calibration (mirror|laser)"; +parse_pgm_inst_t cmd_scan_calibre = { + .f = cmd_scan_calibre_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scan_calibre, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scan_calibre_arg0, + (prog_void *)&cmd_scan_calibre_arg1, + NULL, + }, +}; + + + +/**********************************************************/ +/* start scan */ + +/* this structure is filled when cmd_scan_do is parsed successfully */ +struct cmd_scan_do_result { + fixed_string_t arg0; +}; + +/* function called when cmd_scan_do is parsed successfully */ +static void cmd_scan_do_parsed(void * parsed_result, void * data) +{ + printf_P(PSTR("Starting scan\r\n")); + scanner_scan_autonomous(); +} + +prog_char str_scan_do_arg0[] = "scan_do"; +parse_pgm_token_string_t cmd_scan_do_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scan_do_result, arg0, str_scan_do_arg0); + +prog_char help_scan_do[] = "Scan zone"; +parse_pgm_inst_t cmd_scan_do = { + .f = cmd_scan_do_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scan_do, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scan_do_arg0, + NULL, + }, +}; + + + + +/**********************************************************/ +/* set scanner img params */ + +/* this structure is filled when cmd_scan_img is parsed successfully */ +struct cmd_scan_img_result { + fixed_string_t arg0; + uint8_t algo; + uint8_t h; + int16_t x; + int16_t y; + +}; + +/* function called when cmd_scan_img is parsed successfully */ +static void cmd_scan_img_parsed(void * parsed_result, void * data) +{ + struct cmd_scan_img_result * res = parsed_result; + + scan_params.algo = res->algo; + if (res->algo == I2C_SCANNER_ALGO_COLUMN_DROPZONE) { + scan_params.drop_zone.working_zone = res->h; + scan_params.drop_zone.center_x = res->x; + scan_params.drop_zone.center_y = res->y; + } else if (res->algo == I2C_SCANNER_ALGO_CHECK_TEMPLE) { + scan_params.check_temple.level = res->h; + scan_params.check_temple.temple_x = res->x; + scan_params.check_temple.temple_y = res->y; + } else if (res->algo == I2C_SCANNER_ALGO_TEMPLE_DROPZONE) { + scan_params.drop_zone.working_zone = res->h; + scan_params.drop_zone.center_x = res->x; + scan_params.drop_zone.center_y = res->y; + } + + + +} + +prog_char str_scan_img_arg0[] = "scan_img"; +parse_pgm_token_string_t cmd_scan_img_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scan_img_result, arg0, str_scan_img_arg0); +parse_pgm_token_num_t cmd_scan_img_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_scan_img_result, algo, UINT8); +parse_pgm_token_num_t cmd_scan_img_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_scan_img_result, h, UINT8); +parse_pgm_token_num_t cmd_scan_img_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_scan_img_result, x, INT16); +parse_pgm_token_num_t cmd_scan_img_arg4 = TOKEN_NUM_INITIALIZER(struct cmd_scan_img_result, y, INT16); + + +prog_char help_scan_img[] = "Set scanner img processing params (algo, H, x, y)"; +parse_pgm_inst_t cmd_scan_img = { + .f = cmd_scan_img_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_scan_img, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_scan_img_arg0, + (prog_void *)&cmd_scan_img_arg1, + (prog_void *)&cmd_scan_img_arg2, + (prog_void *)&cmd_scan_img_arg3, + (prog_void *)&cmd_scan_img_arg4, + NULL, + }, +}; + + diff --git a/projects/microb2009/sensorboard/commands_sensorboard.c b/projects/microb2009/sensorboard/commands_sensorboard.c new file mode 100644 index 0000000..9b90bd1 --- /dev/null +++ b/projects/microb2009/sensorboard/commands_sensorboard.c @@ -0,0 +1,197 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands_sensorboard.c,v 1.2 2009-04-24 19:30:42 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "main.h" +#include "cmdline.h" +#include "../common/i2c_commands.h" +#include "i2c_protocol.h" +#include "actuator.h" + +struct cmd_event_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + + +/* function called when cmd_event is parsed successfully */ +static void cmd_event_parsed(void *parsed_result, void *data) +{ + u08 bit=0; + + struct cmd_event_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("all"))) { + bit = DO_ENCODERS | DO_CS | DO_BD | DO_POWER; + if (!strcmp_P(res->arg2, PSTR("on"))) + sensorboard.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) + sensorboard.flags &= bit; + else { /* show */ + printf_P(PSTR("encoders is %s\r\n"), + (DO_ENCODERS & sensorboard.flags) ? "on":"off"); + printf_P(PSTR("cs is %s\r\n"), + (DO_CS & sensorboard.flags) ? "on":"off"); + printf_P(PSTR("bd is %s\r\n"), + (DO_BD & sensorboard.flags) ? "on":"off"); + printf_P(PSTR("power is %s\r\n"), + (DO_POWER & sensorboard.flags) ? "on":"off"); + } + return; + } + + if (!strcmp_P(res->arg1, PSTR("encoders"))) + bit = DO_ENCODERS; + else if (!strcmp_P(res->arg1, PSTR("cs"))) { + //strat_hardstop(); + bit = DO_CS; + } + else if (!strcmp_P(res->arg1, PSTR("bd"))) + bit = DO_BD; + else if (!strcmp_P(res->arg1, PSTR("power"))) + bit = DO_POWER; + + + if (!strcmp_P(res->arg2, PSTR("on"))) + sensorboard.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) { + if (!strcmp_P(res->arg1, PSTR("cs"))) { + pwm_ng_set(BEACON_PWM, 0); + pwm_ng_set(SCANNER_PWM, 0); + } + sensorboard.flags &= (~bit); + } + printf_P(PSTR("%s is %s\r\n"), res->arg1, + (bit & sensorboard.flags) ? "on":"off"); +} + +prog_char str_event_arg0[] = "event"; +parse_pgm_token_string_t cmd_event_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg0, str_event_arg0); +prog_char str_event_arg1[] = "all#encoders#cs#bd#power"; +parse_pgm_token_string_t cmd_event_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg1); +prog_char str_event_arg2[] = "on#off#show"; +parse_pgm_token_string_t cmd_event_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg2, str_event_arg2); + +prog_char help_event[] = "Enable/disable events"; +parse_pgm_inst_t cmd_event = { + .f = cmd_event_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_event, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_event_arg0, + (prog_void *)&cmd_event_arg1, + (prog_void *)&cmd_event_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Color */ + +/* this structure is filled when cmd_color is parsed successfully */ +struct cmd_color_result { + fixed_string_t arg0; + fixed_string_t color; +}; + +/* function called when cmd_color is parsed successfully */ +static void cmd_color_parsed(void *parsed_result, void *data) +{ + struct cmd_color_result *res = (struct cmd_color_result *) parsed_result; + if (!strcmp_P(res->color, PSTR("red"))) { + sensorboard.our_color = I2C_COLOR_RED; + } + else if (!strcmp_P(res->color, PSTR("green"))) { + sensorboard.our_color = I2C_COLOR_GREEN; + } + printf_P(PSTR("Done\r\n")); +} + +prog_char str_color_arg0[] = "color"; +parse_pgm_token_string_t cmd_color_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_color_result, arg0, str_color_arg0); +prog_char str_color_color[] = "green#red"; +parse_pgm_token_string_t cmd_color_color = TOKEN_STRING_INITIALIZER(struct cmd_color_result, color, str_color_color); + +prog_char help_color[] = "Set our color"; +parse_pgm_inst_t cmd_color = { + .f = cmd_color_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_color, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_color_arg0, + (prog_void *)&cmd_color_color, + NULL, + }, +}; + + +/**********************************************************/ +/* Test */ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_test is parsed successfully */ +static void cmd_test_parsed(void *parsed_result, void *data) +{ + //struct cmd_test_result *res = parsed_result; + +} + +prog_char str_test_arg0[] = "test"; +parse_pgm_token_string_t cmd_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_test_result, arg0, str_test_arg0); + +prog_char help_test[] = "Test function"; +parse_pgm_inst_t cmd_test = { + .f = cmd_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_test_arg0, + NULL, + }, +}; diff --git a/projects/microb2009/sensorboard/cs.c b/projects/microb2009/sensorboard/cs.c new file mode 100644 index 0000000..010b49e --- /dev/null +++ b/projects/microb2009/sensorboard/cs.c @@ -0,0 +1,145 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cs.c,v 1.4 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <spi.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> +#include <adc.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "main.h" +#include "beacon.h" +#include "scanner.h" +#include "actuator.h" + +/* called every 5 ms */ +static void do_cs(void *dummy) +{ + /* read encoders */ + if (sensorboard.flags & DO_ENCODERS) { + encoders_spi_manage(NULL); + } + /* control system */ + if (sensorboard.flags & DO_CS) { + if (sensorboard.beacon.on) + cs_manage(&sensorboard.beacon.cs); + if (sensorboard.scanner.on) + cs_manage(&sensorboard.scanner.cs); + } + if (sensorboard.flags & DO_BD) { + bd_manage_from_cs(&sensorboard.beacon.bd, &sensorboard.beacon.cs); + bd_manage_from_cs(&sensorboard.scanner.bd, &sensorboard.scanner.cs); + } + if (sensorboard.flags & DO_POWER) + BRAKE_OFF(); + else + BRAKE_ON(); +} + +void dump_cs(const char *name, struct cs *cs) +{ + printf_P(PSTR("%s cons=% .5ld fcons=% .5ld err=% .5ld " + "in=% .5ld out=% .5ld\r\n"), + name, cs_get_consign(cs), cs_get_filtered_consign(cs), + cs_get_error(cs), cs_get_filtered_feedback(cs), + cs_get_out(cs)); +} + +void dump_pid(const char *name, struct pid_filter *pid) +{ + printf_P(PSTR("%s P=% .8ld I=% .8ld D=% .8ld out=% .8ld\r\n"), + name, + pid_get_value_in(pid) * pid_get_gain_P(pid), + pid_get_value_I(pid) * pid_get_gain_I(pid), + pid_get_value_D(pid) * pid_get_gain_D(pid), + pid_get_value_out(pid)); +} + +void microb_cs_init(void) +{ + /* ---- CS beacon */ + /* PID */ + pid_init(&sensorboard.beacon.pid); + pid_set_gains(&sensorboard.beacon.pid, 80, 80, 250); + pid_set_maximums(&sensorboard.beacon.pid, 0, 10000, 2000); + pid_set_out_shift(&sensorboard.beacon.pid, 6); + pid_set_derivate_filter(&sensorboard.beacon.pid, 6); + + /* CS */ + cs_init(&sensorboard.beacon.cs); + cs_set_correct_filter(&sensorboard.beacon.cs, pid_do_filter, &sensorboard.beacon.pid); + cs_set_process_in(&sensorboard.beacon.cs, pwm_ng_set, BEACON_PWM); + cs_set_process_out(&sensorboard.beacon.cs, encoders_spi_update_beacon_speed, BEACON_ENCODER); + cs_set_consign(&sensorboard.beacon.cs, 0); + + /* ---- CS scanner */ + /* PID */ + pid_init(&sensorboard.scanner.pid); + pid_set_gains(&sensorboard.scanner.pid, 200, 5, 250); + pid_set_maximums(&sensorboard.scanner.pid, 0, 10000, 2047); + pid_set_out_shift(&sensorboard.scanner.pid, 6); + pid_set_derivate_filter(&sensorboard.scanner.pid, 6); + + /* QUADRAMP */ + quadramp_init(&sensorboard.scanner.qr); + quadramp_set_1st_order_vars(&sensorboard.scanner.qr, 200, 200); /* set speed */ + quadramp_set_2nd_order_vars(&sensorboard.scanner.qr, 20, 20); /* set accel */ + + /* CS */ + cs_init(&sensorboard.scanner.cs); + cs_set_consign_filter(&sensorboard.scanner.cs, quadramp_do_filter, &sensorboard.scanner.qr); + cs_set_correct_filter(&sensorboard.scanner.cs, pid_do_filter, &sensorboard.scanner.pid); + cs_set_process_in(&sensorboard.scanner.cs, pwm_ng_set, SCANNER_PWM); + cs_set_process_out(&sensorboard.scanner.cs, encoders_spi_update_scanner, SCANNER_ENCODER); + cs_set_consign(&sensorboard.scanner.cs, 0); + + /* Blocking detection */ + bd_init(&sensorboard.scanner.bd); + bd_set_speed_threshold(&sensorboard.scanner.bd, 150); + bd_set_current_thresholds(&sensorboard.scanner.bd, 500, 8000, 1000000, 40); + + /* set them on !! */ + sensorboard.beacon.on = 0; + sensorboard.scanner.on = 1; + + + scheduler_add_periodical_event_priority(do_cs, NULL, + 5000L / SCHEDULER_UNIT, + CS_PRIO); +} diff --git a/projects/microb2009/sensorboard/cs.h b/projects/microb2009/sensorboard/cs.h new file mode 100644 index 0000000..fe50c80 --- /dev/null +++ b/projects/microb2009/sensorboard/cs.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: cs.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +void microb_cs_init(void); +void dump_cs(const char *name, struct cs *cs); +void dump_pid(const char *name, struct pid_filter *pid); diff --git a/projects/microb2009/sensorboard/diagnostic_config.h b/projects/microb2009/sensorboard/diagnostic_config.h new file mode 100644 index 0000000..e4ebb75 --- /dev/null +++ b/projects/microb2009/sensorboard/diagnostic_config.h @@ -0,0 +1,44 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: diagnostic_config.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +#ifndef _DEBUG_CONFIG_ +#define _DEBUG_CONFIG_ 1.0 // version + + +/** port line definition for the show_int_loop() function */ +/* undefine it to disable this functionnality */ +#define INTERRUPT_SHOW_PORT PORTA +#define INTERRUPT_SHOW_BIT 3 + + + +/** memory mark for the min_stack_space_available() function + the ram is filled with this value after a reset ! */ +#define MARK 0x55 + +/** the mark is inserted in whole RAM if this is enabled + (could lead to problems if you need to hold values through a reset...) + so it's better to disable it. + stack counting is not affected */ +//#define DIAG_FILL_ENTIRE_RAM + + +#endif //_DEBUG_CONFIG_ diff --git a/projects/microb2009/sensorboard/encoders_spi_config.h b/projects/microb2009/sensorboard/encoders_spi_config.h new file mode 100644 index 0000000..6a4a68b --- /dev/null +++ b/projects/microb2009/sensorboard/encoders_spi_config.h @@ -0,0 +1,33 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_spi_config.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ +#ifndef _ENCODERS_SPI_CONFIG_H_ +#define _ENCODERS_SPI_CONFIG_H_ + +#define ENCODERS_SPI_NUMBER 4 +#define ENCODERS_SPI_SS_PORT SS_PORT /* PORTB on atmega2560 */ +#define ENCODERS_SPI_SS_BIT SS_BIT /* 0 on atmega2560 */ + +/* see spi configuration */ +#define ENCODERS_SPI_CLK_RATE SPI_CLK_RATE_16 +#define ENCODERS_SPI_FORMAT SPI_FORMAT_3 +#define ENCODERS_SPI_DATA_ORDER SPI_LSB_FIRST + +#endif diff --git a/projects/microb2009/sensorboard/error_config.h b/projects/microb2009/sensorboard/error_config.h new file mode 100644 index 0000000..15ca2fc --- /dev/null +++ b/projects/microb2009/sensorboard/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/sensorboard/gen_scan_tab.c b/projects/microb2009/sensorboard/gen_scan_tab.c new file mode 100644 index 0000000..7b94bfd --- /dev/null +++ b/projects/microb2009/sensorboard/gen_scan_tab.c @@ -0,0 +1,680 @@ +#include <stdio.h> +#include <stdlib.h> +#include <math.h> +#include <inttypes.h> + +#include <stdint.h> + + +#include "scanner.h" + +#define ADC_REF_AVCC 0 +#define MUX_ADC13 0 + + + +double TELEMETRE_A = TELEMETRE_A_INIT; +double TELEMETRE_B = TELEMETRE_B_INIT; + + +#define printf_P printf +#define PSTR(a) (a) +int32_t motor_angle = 0; +int32_t scan_dist = 0; + + +int32_t H_fin, L_fin; +double L, H; + +#define nop() + +#define ABS(val) ({ \ + __typeof(val) __val = (val); \ + if (__val < 0) \ + __val = - __val; \ + __val; \ + }) + +struct scan_params scan_params; + +int32_t encoders_spi_get_value_scanner_interpolation(void *a) +{ + return motor_angle; +} + + +int16_t adc_get_value(uint8_t a) +{ + return scan_dist; +} + + + +/* get motor angle in radian; return mirror angle in radian, cos a sin a */ +void ang2_a_mirror(double b, double * c_a, double* s_a, double* a) +{ + double x2, y2; + double A, DELTA, B, D; + + b+=scan_params.offset_b; + x2 = X + l1*cos(b); + y2 = Y + l1*sin(b); + + A = (l3*l3 + x2*x2 + y2*y2 - l2*l2)/(2*l3); + + DELTA = -(A*A - x2*x2 - y2*y2); + B = sqrt(DELTA); + + D = x2*x2 + y2*y2; + + *c_a = (x2*A + y2*B)/D; + *s_a = -(x2*B - y2*A)/D; + + *a = atan2(*s_a, *c_a); + + *a += scan_params.offset_a; + // *s_a = sin(*a); + // *c_a = cos(*a); + +} + +/* get telemeter dist , cos a, sin a, a and return H, L of scanned point */ +void ang2_H_L(double l_telemetre, double c_a, double s_a, double a, double *H, double *L) +{ + double d; + d = h_mirror*c_a/s_a; + *H = (l_telemetre - l_mirror - d)*sin(2*a); + *L = l_mirror + d + *H/tan(2*a); + + //*H+= 8*sin(a-scan_params.offset_a); +} + + + +//int32_t last_col_n; +//int32_t last_row_n; +//uint8_t last_sample; + +//uint8_t h_limit[] = {40, 53, 66, 78, 94, 111, 123}; +//uint8_t h_limit[] = {37, 48, 61, 72, 94, 111, 123}; + +/* last high is dummy, to deal higher columns */ +//uint8_t h_limit[] = {68, 79, 93, 107, 121, 138, 155, 170, 250}; + + +//uint8_t h_limit[] = {60, 72, 85, 98, 112, 129, 250}; + +//uint8_t h_limit[] = {80, 97, 118, 134, 145, 160, 250}; + + +//uint8_t h_limit[] = {79, 94, 108, 117, 129, 144, 250}; + +uint8_t h_limit[] = {83, 95, 108, 120, 135, 147, 164, 250}; +#define H_MARGIN (-6) + +#define cs_set_consign(a, b) + + + +void do_scan(void * dummy) +{ + + unsigned int i; + int16_t a; + int32_t row_n; + int32_t col_n; + + + int32_t tour_pos; + int32_t pos, last_pos; + int32_t pos_tmp ; + int32_t mot_pos; + double dist; + uint8_t min_sample; + + double b, c_a, s_a, /*H, L,*/ m_a; + // int32_t H_fin; + + + //printf("scan\n"); + if (scan_params.sample_i==0) + return; + + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); +#if 0 + if (scan_params.sample_i==1){ + printf_P(PSTR("dump end enc %ld %d \r\n"), mot_pos, PIX_PER_SCAN); + //scanner.flags &= (~CS_ON); + + + + /* stop scan at cur pos + 10 round */ + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + mot_pos = SCANNER_STEP_TOUR * ((mot_pos/SCANNER_STEP_TOUR) + 1) ; + + printf_P(PSTR("set to %ld \r\n"), mot_pos); + + cs_set_consign(&sensorboard.scanner.cs, mot_pos); + //pwm_ng_set(SCANNER_MOT_PWM, 0); + + + } + + mot_pos-= scan_params.pos_start_scan; +#endif + a = adc_get_value( ADC_REF_AVCC | MUX_ADC13 ); + + + //dist = (a-TELEMETRE_B)/TELEMETRE_A; + //dist = TELEMETRE_A * a +TELEMETRE_B; + dist = telemetre_to_cm(a); + + //printf_P(PSTR("enc val = %ld\r\n"), encoders_microb_get_value((void *)SCANNER_ENC)); + + + //sample_tab[MAX_SAMPLE-sample_i] = a>0x1ff?0x1FF:a; + //sample_tab[MAX_SAMPLE-sample_i] |= PINF&2?0x200:0; + + + row_n = (mot_pos)/(SCANNER_STEP_TOUR/2); +#if 0 + /* separe scan forward/backword */ + if (row_n%2){ + row_n/=2; + } + else{ + row_n/=2; + row_n+=30; + } +#endif + + tour_pos = (mot_pos)%(SCANNER_STEP_TOUR); + + b = (2.*M_PI)*(double)tour_pos/(double)(SCANNER_STEP_TOUR); + + ang2_a_mirror(b, &c_a, &s_a, &m_a); + ang2_H_L(dist, c_a, s_a, m_a, &H, &L); + + + if (H >0){ + printf("zarb H\n"); + H = 0; + } + + if (dist> SCAN_MAX_DIST){ + H = 0; + L = 0; + } + + H = H;//m_a*180/M_PI; + L = L;//(L-100)*PIX_PER_SCAN; + + //printf_P(PSTR("polling : ADC0 = %i %f\r\n"),a, dist); + //printf_P(PSTR("%f %f %2.2f %f\r\n"), H, L, m_a*180./M_PI, dist); + + + //printf_P(PSTR("dist, b, a: %2.2f %2.2f %2.2f\r\n"), dist, b*180/M_PI, m_a*180/M_PI); + + H=(H+SCAN_H_MAX)*SCAN_H_COEF; + L-=SCAN_L_MIN; + + + /* XXX may never append */ + if (L<0) + L=0; + + + /* first filter => pixel modulo level */ +#define H_BASE 10 +#define H_MUL 14 + H_fin = H;//+SCAN_H_MAX; + //H_fin = ((H_fin-H_BASE)/H_MUL)*H_MUL + H_BASE; + + if (scan_params.filter){ + H_fin = 11; // default is level 11 + for (i=0;i<sizeof(h_limit)/sizeof(uint8_t);i++){ + if (H < h_limit[i]+H_MARGIN){ + H_fin = i; + break; + } + } + } + + L_fin = L; + //printf_P(PSTR("%f %f\r\n"), dist, m_a*180/M_PI); + //printf_P(PSTR("%f %f\r\n"), m_a*180/M_PI, b*180/M_PI); + + //printf_P(PSTR("%d %f\r\n"), a, b*180/M_PI); + //printf_P(PSTR("%f %f %f\r\n"), H, m_a*180/M_PI, offset_b); + + //printf_P(PSTR("a, tpos: %d %d \r\n"), a, tour_pos); + + + //printf_P(PSTR("%f %f\r\n"), H, L); + + + /* + if (row_n%2){ + //tour_pos = ((SCANNER_STEP_TOUR/2)-tour_pos); + tour_pos = (tour_pos*PIX_PER_SCAN)/(SCANNER_STEP_TOUR); + } + else{ + tour_pos = ((SCANNER_STEP_TOUR-tour_pos)*PIX_PER_SCAN)/(SCANNER_STEP_TOUR); + } + */ + col_n = (PIX_PER_SCAN*L)/(SCAN_L_MAX-SCAN_L_MIN); + if (col_n>PIX_PER_SCAN) + printf("BUG!!! RECALC MAX L\r\n"); + + //col_n = (PIX_PER_SCAN+col_n -5)%PIX_PER_SCAN; + + //pos = (row_n*SCANNER_STEP_TOUR + tour_pos)/STEP_PER_POS; + //pos= row_n*PIX_PER_SCAN+tour_pos; + //last_pos= last_row_n*PIX_PER_SCAN+last_tour_pos; + + + + pos= row_n*PIX_PER_SCAN+col_n; + last_pos= scan_params.last_row_n*PIX_PER_SCAN+scan_params.last_col_n; + + //printf_P(PSTR("%ld %ld %ld %ld\r\n"), row_n, col_n, pos, H_fin); + + //a-=0x100; + a-=200; + //a/=10; + + if (0<= pos && pos <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos] = a>0xff?0xFF:a; + //sample_tab[(int)L] = H ; + scan_params.sample_tab[pos] = H_fin; + nop(); + if ((scan_params.last_row_n == row_n) && ABS(last_pos-pos)>1){ + /* we have a hole, pad it with minimal hight */ + if (H_fin>scan_params.last_sample) + min_sample = scan_params.last_sample; + else + min_sample = H_fin; + + //printf("(%ld, %ld) (%ld %ld)\r\n", last_col_n, last_row_n, col_n, row_n); + + /* fill grow, avoid erasing curent pos */ + if (pos > last_pos){ + pos_tmp = last_pos; + last_pos = pos; + //printf("loop1 on (%ld, %ld) %ld\r\n", pos_tmp, last_pos, last_pos-pos_tmp); + + } + else{ + pos_tmp = pos+1; + //printf("loop1 on (%ld, %ld) %ld\r\n", pos_tmp, last_pos, last_pos-pos_tmp); + } + + + for (;pos_tmp< last_pos;pos_tmp++){ + if (0< pos_tmp && pos_tmp <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos_tmp] = min_sample; + nop(); + + } + + + } + + scan_params.last_row_n = row_n; + scan_params.last_col_n = col_n; + scan_params.last_sample = H_fin; + + + //printf("pos : %ld\r\n", pos); + //sample_tab[sample_i] = a>0x1ff?0x1FF:a; + + //sample_ok_tab[MAX_SAMPLE-sample_i] = PORTF&2; + + /* + if (((pos <MAX_SAMPLE)) && (tour_pos<=(SCANNER_STEP_TOUR/2))) + sample_tab[pos] = 0xffff; + */ + scan_params.sample_i--; +} + + +#define my_offset_a (0*M_PI/180) +#define my_offset_b (34*M_PI/180) + +//#define my_offset_a (40*M_PI/180) +//#define my_offset_b (-5*M_PI/180) + + + +/* + *2 cause we don't known exactly limits + at computation time +*/ +lookup_h_l array_h_l[DIM_DIST*2][DIM_ANGLE*2]; + + + +#define pgm_read_word_near(a) (*((uint16_t*)(a))) + + +void do_scan_quick(void * dummy) +{ + + int i, j; + int16_t a; + int32_t row_n; + int32_t col_n; + + + int32_t tour_pos; + int32_t pos, last_pos; + int32_t pos_tmp ; + int32_t mot_pos; + uint8_t min_sample; + //double H, L; + //int32_t H_fin, L_fin; + + + union{ + uint16_t u16; + lookup_h_l h_l; + }val; + if (scan_params.sample_i==0) + return; + + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + if (scan_params.sample_i==1){ + printf_P(PSTR("dump end enc %ld %d \r\n"), mot_pos, PIX_PER_SCAN); + //scanner.flags &= (~CS_ON); + + + + /* stop scan at cur pos + 10 round */ + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + mot_pos = SCANNER_STEP_TOUR * ((mot_pos/SCANNER_STEP_TOUR) + 1) ; + + printf_P(PSTR("set to %ld \r\n"), mot_pos); + + cs_set_consign(&sensorboard.scanner.cs, mot_pos); + //pwm_ng_set(SCANNER_MOT_PWM, 0); + + + } + + mot_pos-= scan_params.pos_start_scan; + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC13 ); + + + tour_pos = (mot_pos)%(SCANNER_STEP_TOUR); + + + if (scan_params.offset_a != 0) + printf_P(PSTR("%ld %d \r\n"), tour_pos, a); + + /* lookup in precomputed array */ + + + j = (DIM_DIST * (telemetre_to_cm(a)-TELEMETRE_MIN_CM))/(TELEMETRE_MAX_CM - TELEMETRE_MIN_CM); + i = (DIM_ANGLE * tour_pos)/STEP_PER_ROUND; + + + if (j<0) + j=0; + if (j>=DIM_DIST) + j = DIM_DIST-1; + + if (i>=DIM_ANGLE) + i = DIM_ANGLE-1; + + + val.u16 = pgm_read_word_near(&array_h_l[j][i]); + + + //val.u16 = pgm_read_word_near(&array_h_l[(a-TELEMETRE_MIN)/DIST_STEP][mot_pos/ANGLE_STEP]); + //val.u16 = pgm_read_word_near(&array_h_l[a][tp]); + H = val.h_l.h; + L = val.h_l.l; + /* + val.u16 = pgm_read_word_near(&array_h_l[(a-TELEMETRE_MIN)/DIST_STEP][mot_pos/ANGLE_STEP]); + + H = val.h_l.h; + L = val.h_l.l; + */ + H_fin = H; + L_fin = L; + + + + col_n = (PIX_PER_SCAN*L)/(SCAN_L_MAX-SCAN_L_MIN); + if (col_n>PIX_PER_SCAN) + printf("BUG!!! RECALC MAX L\r\n"); + + //col_n = (PIX_PER_SCAN+col_n -5)%PIX_PER_SCAN; + + //pos = (row_n*SCANNER_STEP_TOUR + tour_pos)/STEP_PER_POS; + //pos= row_n*PIX_PER_SCAN+tour_pos; + //last_pos= last_row_n*PIX_PER_SCAN+last_tour_pos; + + row_n = (mot_pos)/(SCANNER_STEP_TOUR/2); + + + pos= row_n*PIX_PER_SCAN+col_n; + last_pos= scan_params.last_row_n*PIX_PER_SCAN+scan_params.last_col_n; + + //printf_P(PSTR("%ld %ld %ld %ld\r\n"), row_n, col_n, pos, H_fin); + + //a-=0x100; + a-=200; + //a/=10; + + if (0<= pos && pos <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos] = a>0xff?0xFF:a; + //sample_tab[(int)L] = H ; + scan_params.sample_tab[pos] = H_fin; + nop(); + if ((scan_params.last_row_n == row_n) && ABS(last_pos-pos)>1){ + /* we have a hole, pad it with minimal hight */ + if (H_fin>scan_params.last_sample) + min_sample = scan_params.last_sample; + else + min_sample = H_fin; + + //printf("(%ld, %ld) (%ld %ld)\r\n", last_col_n, last_row_n, col_n, row_n); + + /* fill grow, avoid erasing curent pos */ + if (pos > last_pos){ + pos_tmp = last_pos; + last_pos = pos; + //printf("loop1 on (%ld, %ld) %ld\r\n", pos_tmp, last_pos, last_pos-pos_tmp); + + } + else{ + pos_tmp = pos+1; + //printf("loop1 on (%ld, %ld) %ld\r\n", pos_tmp, last_pos, last_pos-pos_tmp); + } + + + for (;pos_tmp< last_pos;pos_tmp++){ + if (0< pos_tmp && pos_tmp <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos_tmp] = min_sample; + nop(); + + } + + + } + + scan_params.last_row_n = row_n; + scan_params.last_col_n = col_n; + scan_params.last_sample = H_fin; + + + //printf("pos : %ld\r\n", pos); + //sample_tab[sample_i] = a>0x1ff?0x1FF:a; + + //sample_ok_tab[MAX_SAMPLE-sample_i] = PORTF&2; + + /* + if (((pos <MAX_SAMPLE)) && (tour_pos<=(SCANNER_STEP_TOUR/2))) + sample_tab[pos] = 0xffff; + */ + scan_params.sample_i--; +} + + +int main(int argc, char** argv) +{ + union{ + uint16_t u16; + lookup_h_l h_l; + }val; + + int i, j; + FILE* f, *fin, *f_header; + + unsigned char line[1000]; + unsigned int a, b; + unsigned int dist_max, angle_max; + + scan_params.filter = 1; + + + + f = fopen("oo", "w"); + + + TELEMETRE_B = 23.50; + + scan_params.offset_a = my_offset_a; + scan_params.offset_b = my_offset_b; + + + + + + /*precompute H & L array */ + for (j = 0, scan_dist = TELEMETRE_MIN; scan_dist< TELEMETRE_MAX; j++, scan_dist+=DIST_STEP){ + + for (i = 0, motor_angle = 0; motor_angle < STEP_PER_ROUND; i++, motor_angle+=ANGLE_STEP){ + scan_params.sample_i = 100; + scan_params.pos_start_scan = 0; + //printf("%d\n", i); + do_scan(0); + //printf("mangle, dist, h, l: %d %d, (%d, %2.2f)\n", motor_angle, scan_dist, H_fin, L); + //fprintf(f, "mangle, dist, h, l: %d %d, (%d, %2.2f)\n", motor_angle, scan_dist, H_fin, L); + /* + j = (scan_dist - TELEMETRE_MIN)/DIST_STEP; + i = motor_angle/ANGLE_STEP; + //printf("%d %d (%d %d) (%d %d %d = %d)\n", i, j, motor_angle, ANGLE_STEP, scan_dist, TELEMETRE_MIN, DIST_STEP, (scan_dist - TELEMETRE_MIN)/DIST_STEP); + array_h_l[j][i].h = H_fin; + array_h_l[j][i].l = L_fin; + */ + j = (DIM_DIST * (telemetre_to_cm(scan_dist)-TELEMETRE_MIN_CM))/(TELEMETRE_MAX_CM - TELEMETRE_MIN_CM); + i = (DIM_ANGLE * motor_angle)/STEP_PER_ROUND; + array_h_l[j][i].h = H_fin; + array_h_l[j][i].l = L_fin; + + } + } + + + scan_params.filter = 0; + if (argc>1 && !strcmp(argv[1], "1")) + scan_params.filter = 1; + + + printf("max i max j %d %d \n", i, j); + dist_max = j; + angle_max = i; + + f_header = fopen("scan_h_l.h", "w"); + fprintf(f_header, "PROGMEM lookup_h_l array_h_l[%d][%d] = {\n", dist_max, angle_max); + for (j = 0, scan_dist = 0; j<dist_max; j++, scan_dist+=DIST_STEP){ + fprintf(f_header, "{\n"); + + for (i = 0, motor_angle = 0; i < angle_max; i++, motor_angle+=ANGLE_STEP){ + fprintf(f_header, "{ .h = %d, .l = %d }, ", array_h_l[j][i].h, array_h_l[j][i].l); + + } + fprintf(f_header, "},\n"); + } + fprintf(f_header, "};\n", DIM_DIST, DIM_ANGLE); + + fclose(f_header); + + + + printf("IIIIIIIIIIII %d %d\n", array_h_l[38][152].h, array_h_l[38][152].l); + val.u16 = pgm_read_word_near(&array_h_l[38][152]); + printf("IIIIIIIIIIII %d %d\n", val.h_l.h, val.h_l.l); + + motor_angle = 9000; + scan_dist = 388; + + for (motor_angle = 0; motor_angle<14000; motor_angle+=100){ + for (scan_dist = TELEMETRE_MIN; scan_dist<300; scan_dist+=10){ + scan_params.sample_i = 100; + scan_params.pos_start_scan = 0; + + do_scan(0); + + + //printf("m s %d %d\n", motor_angle, scan_dist); + //printf("R %d %d\n", H_fin, L_fin); + + val.u16 = pgm_read_word_near(&array_h_l[(scan_dist-TELEMETRE_MIN)/DIST_STEP][motor_angle/ANGLE_STEP]); + //printf("Q %d %d\n\n", val.h_l.h, val.h_l.l); + + if (val.h_l.h != H_fin || val.h_l.l != L_fin) + printf("BUG BUG\n"); + } + } + + fin = fopen("out", "r"); + while(fgets(line, sizeof(line), fin)){ + scan_params.sample_i = 100; + scan_params.pos_start_scan = 0; + + //printf("[%s]\n", line); + sscanf(line, "%d %d\n", &a, &b); + //printf("%d %d\n", a, b); + motor_angle = a; + scan_dist = b; + do_scan_quick(0); + /* + j = (DIM_DIST * (telemetre_to_cm(scan_dist)-TELEMETRE_MIN_CM))/(TELEMETRE_MAX_CM - TELEMETRE_MIN_CM); + i = (DIM_ANGLE * motor_angle)/STEP_PER_ROUND; + + val.u16 = pgm_read_word_near(&array_h_l[j][i]); + H_fin = val.h_l.h; + L_fin = val.h_l.l; + */ + + printf("Q %d %d\n", H_fin, L_fin); + + do_scan(0); + + printf("R %d %d\n", H_fin, L_fin); + + fprintf(f, "mangle, dist, h, l: %d %d, (%d, %d)\n", motor_angle, scan_dist, H_fin, L_fin); + + } + fclose(fin); + + fclose(f); + + return; + /* + for (j = 0, scan_dist = 0; j<DIM_DIST; j++, scan_dist+=DIST_STEP){ + for (i = 0, motor_angle = 0; i < DIM_ANGLE; i++, motor_angle+=ANGLE_STEP){ + do_scan(0); + printf("%d %d, (%d, %2.2f)\n", motor_angle, scan_dist, H_fin, L); + + } + + } + */ + + +} diff --git a/projects/microb2009/sensorboard/i2c_config.h b/projects/microb2009/sensorboard/i2c_config.h new file mode 100644 index 0000000..ebc0678 --- /dev/null +++ b/projects/microb2009/sensorboard/i2c_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + + +#define I2C_BITRATE 1 // divider dor i2c baudrate, see TWBR in doc +#define I2C_PRESCALER 3 // prescaler config, rate = 2^(n*2) + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 32 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 32 diff --git a/projects/microb2009/sensorboard/i2c_protocol.c b/projects/microb2009/sensorboard/i2c_protocol.c new file mode 100644 index 0000000..c349e55 --- /dev/null +++ b/projects/microb2009/sensorboard/i2c_protocol.c @@ -0,0 +1,256 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.c,v 1.3 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#include <string.h> + +#include <aversive.h> +#include <aversive/list.h> +#include <aversive/error.h> + +#include <scheduler.h> + +#include <i2c.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <time.h> +#include <spi.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <rdline.h> +#include <parse.h> +#include <parse_string.h> +#include <parse_num.h> + +#include "../common/i2c_commands.h" +#include "main.h" +#include "actuator.h" +#include "beacon.h" +#include "scanner.h" + +void i2c_protocol_init(void) +{ +} + +/*** LED CONTROL ***/ +void i2c_led_control(uint8_t l, uint8_t state) +{ + switch(l) { + case 1: + state? LED1_ON():LED1_OFF(); + break; + case 2: + state? LED2_ON():LED2_OFF(); + break; + default: + break; + } +} + +void i2c_send_status(void) +{ + struct i2c_ans_sensorboard_status ans; + i2c_flush(); + ans.hdr.cmd = I2C_ANS_SENSORBOARD_STATUS; + ans.status = 0x55; /* XXX */ + ans.opponent_x = beacon.opponent_x; + ans.opponent_y = beacon.opponent_y; + ans.opponent_a = beacon.opponent_angle; + ans.opponent_d = beacon.opponent_dist; + + ans.scan_status = 0; + ans.scan_status |= scan_params.working ? 0 : I2C_SCAN_DONE; + ans.scan_status |= scan_params.max_column_detected ? I2C_SCAN_MAX_COLUMN : 0; + + + ans.dropzone_x = scan_params.dropzone_x; + ans.dropzone_y = scan_params.dropzone_y; + ans.dropzone_h = scan_params.dropzone_h; + + i2c_send(I2C_ADD_MASTER, (uint8_t *) &ans, + sizeof(ans), I2C_CTRL_GENERIC); +} + + +void i2c_scanner_calibre_laser(void* dummy) +{ + scanner_calibre_laser(); +} + +void i2c_scanner_end_process(void* dummy) +{ + scanner_end_process(); +} + +void i2c_recvevent(uint8_t * buf, int8_t size) +{ + void *void_cmd = buf; + static uint8_t a=0; + a=!a; + if (a) + LED2_ON(); + else + LED2_OFF(); + + if (size <= 0) { + goto error; + } + + switch (buf[0]) { + + /* Commands (no answer needed) */ + case I2C_CMD_GENERIC_LED_CONTROL: + { + struct i2c_cmd_led_control *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + i2c_led_control(cmd->led_num, cmd->state); + break; + } + + case I2C_CMD_GENERIC_SET_COLOR: + { + struct i2c_cmd_generic_color *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + sensorboard.our_color = cmd->color; + break; + } + + case I2C_CMD_SENSORBOARD_SET_BEACON: + { + struct i2c_cmd_sensorboard_start_beacon *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + + if (cmd->enable) + beacon_start(); + else + beacon_stop(); + + break; + } + + case I2C_CMD_SENSORBOARD_SET_SCANNER: + { + struct i2c_cmd_sensorboard_scanner *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + + scanner_set_mode(cmd->mode); + break; + + } + + + case I2C_CMD_SENSORBOARD_SCANNER_ALGO: + { + struct i2c_cmd_sensorboard_scanner_algo *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + + scan_params.algo = cmd->algo; + + if (cmd->algo == I2C_SCANNER_ALGO_COLUMN_DROPZONE){ + scan_params.drop_zone.working_zone = cmd->drop_zone.working_zone; + scan_params.drop_zone.center_x = cmd->drop_zone.center_x; + scan_params.drop_zone.center_y = cmd->drop_zone.center_y; + } + else if (cmd->algo == I2C_SCANNER_ALGO_CHECK_TEMPLE) { + scan_params.check_temple.level = cmd->check_temple.level; + scan_params.check_temple.temple_x = cmd->check_temple.temple_x; + scan_params.check_temple.temple_y = cmd->check_temple.temple_y; + } + else if (cmd->algo == I2C_SCANNER_ALGO_TEMPLE_DROPZONE){ + scan_params.drop_zone.working_zone = cmd->drop_zone.working_zone; + scan_params.drop_zone.center_x = cmd->drop_zone.center_x; + scan_params.drop_zone.center_y = cmd->drop_zone.center_y; + } + else{ + /* new command */ + } + + scan_params.working = 1; + scheduler_add_single_event_priority(i2c_scanner_end_process, NULL, + 1, + CS_PRIO-1); + break; + + } + + case I2C_CMD_SENSORBOARD_CALIB_SCANNER: + { + struct i2c_cmd_sensorboard_calib_scanner *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + + scheduler_add_single_event_priority(i2c_scanner_calibre_laser, NULL, + 1, + CS_PRIO-1); + break; + } + + + + /* Add other commands here ...*/ + + + case I2C_REQ_SENSORBOARD_STATUS: + { + struct i2c_req_sensorboard_status *cmd = void_cmd; + if (size != sizeof (*cmd)) + goto error; + + beacon.robot_x = cmd->x; + beacon.robot_y = cmd->y; + beacon.robot_angle = cmd->a; + + if (cmd->enable_pickup_wheels) + pickup_wheels_on(); + else + pickup_wheels_off(); + + i2c_send_status(); + break; + } + + default: + goto error; + } + + error: + /* log error on a led ? */ + return; +} + +void i2c_recvbyteevent(uint8_t hwstatus, uint8_t i, uint8_t c) +{ +} + +void i2c_sendevent(int8_t size) +{ +} + + diff --git a/projects/microb2009/sensorboard/i2c_protocol.h b/projects/microb2009/sensorboard/i2c_protocol.h new file mode 100644 index 0000000..6fcac74 --- /dev/null +++ b/projects/microb2009/sensorboard/i2c_protocol.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +#include <aversive.h> + +void i2c_protocol_init(void); + +void i2c_recvevent(uint8_t * buf, int8_t size); +void i2c_recvbyteevent(uint8_t hwstatus, uint8_t i, uint8_t c); +void i2c_sendevent(int8_t size); + +int debug_send(char c, FILE* f); diff --git a/projects/microb2009/sensorboard/img_processing.c b/projects/microb2009/sensorboard/img_processing.c new file mode 100644 index 0000000..d030478 --- /dev/null +++ b/projects/microb2009/sensorboard/img_processing.c @@ -0,0 +1,1619 @@ +#include <stdio.h> +#include <string.h> +#include <inttypes.h> + +#include <aversive/pgmspace.h> +#include <aversive/error.h> + +#include <stdint.h> + +#include <stdio.h> +#include <stdlib.h> +#include <math.h> + +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> + +#include "img_processing.h" + + +#define debug_printf(fmt, ...) printf_P(PSTR(fmt), ##__VA_ARGS__) + +#ifndef HOST_VERSION + +#include <aversive.h> +#include <pwm_ng.h> +#include <pid.h> +#include <time.h> +#include <quadramp.h> +#include <blocking_detection_manager.h> +#include <rdline.h> + +#include <control_system_manager.h> +#include <adc.h> +#include <spi.h> +#include <ax12.h> + +#include "main.h" + +#define IMG_DEBUG(args...) DEBUG(E_USER_IMGPROCESS, args) +#define IMG_NOTICE(args...) NOTICE(E_USER_IMGPROCESS, args) +#define IMG_ERROR(args...) ERROR(E_USER_IMGPROCESS, args) + +#else + +#define IMG_DEBUG(args...) debug_printf(args) +#define IMG_NOTICE(args...) debug_printf(args) +#define IMG_ERROR(args...) debug_printf(args) + +#endif + + + + +#define OBJECT_MINIMUM_DEMI_PERIMETER (2*3) +/* store object in pool if never seen + * returns: + * 1 if new object + * 0 if already known + */ +int store_obj(Object_bb* tab_o, int total, Object_bb*o) +{ + uint8_t i; + + if (o->x_max - o->x_min + o->y_max - o->y_min < OBJECT_MINIMUM_DEMI_PERIMETER) + return 0; + + for (i=0;i<total;i++){ + if (!memcmp(&tab_o[i], o, sizeof(Object_bb))) + return 0; + + if (tab_o[i].x_min==0 && tab_o[i].x_max==0 && + tab_o[i].y_min==0 && tab_o[i].y_max==0){ + memcpy(&tab_o[i], o, sizeof(Object_bb)); + return 1; + } + + } + return 0; +} + +/* step around object of given color and compute its bounding box */ +void object_find_bounding_box(unsigned char* data, + int16_t x_in, int16_t y_in, + int16_t start_x, int16_t start_y, + int16_t color, int16_t color_w,Object_bb* o) +{ + int16_t pos_x = start_x; + int16_t pos_y = start_y; + int16_t start =0; + int16_t len = 0; + int16_t count_stand = 0; + + vect_t v, vi; + + + v.x = 1; + v.y = 0; + + vi = v; + + o->x_max = 0; + o->y_max = 0; + o->x_min = x_in; + o->y_min = y_in; + + + while(1){ + if (pos_x == start_x && pos_y == start_y){ + count_stand++; + if (count_stand>4) + break; + if( v.x == vi.x && v.y == vi.y && start) + break; + } + + if (pos_x<o->x_min) + o->x_min = pos_x; + if (pos_y<o->y_min) + o->y_min = pos_y; + if (pos_x>o->x_max) + o->x_max = pos_x; + if (pos_y>o->y_max) + o->y_max = pos_y; + + /* is next pixel is good color */ + if (data[(pos_y+v.y)*x_in + pos_x+v.x] != color){ + pos_x = pos_x+v.x; + pos_y = pos_y+v.y; + len++; + vect_rot_retro(&v); + start = 1; + continue; + } + vect_rot_trigo(&v); + } + + o->len = len; +} + + + + + +/* step around object of given color and computes its polygon */ +void object_find_poly(unsigned char* data, + int16_t x_in, int16_t y_in, + int16_t start_x, int16_t start_y, + int16_t color, int16_t color_w, Object_poly* o) +{ + int16_t pos_x = start_x; + int16_t pos_y = start_y; + int16_t start =0; + int16_t len = 0; + int16_t count_stand = 0; + uint16_t pt_step, pt_num; + vect_t v, vi; + + v.x = 1; + v.y = 0; + + vi = v; + + pt_step = o->len/POLY_MAX_PTS + 1; + + pt_num = 0; + + while(1){ + if (pos_x == start_x && pos_y == start_y){ + count_stand++; + if (count_stand>4) + break; + if( v.x == vi.x && v.y == vi.y && start) + break; + } + + /* is next pixel is good color */ + if (data[(pos_y+v.y)*x_in + pos_x+v.x] != color){ + pos_x = pos_x+v.x; + pos_y = pos_y+v.y; + len++; + + if (len >pt_num*pt_step){ + o->pts[pt_num].x = pos_x; + o->pts[pt_num].y = pos_y; + pt_num+=1; + if (pt_num>=POLY_MAX_PTS) + break; + } + + vect_rot_retro(&v); + start = 1; + continue; + } + vect_rot_trigo(&v); + } + + o->pts_num = pt_num; + +} + +#define PT_LEFT 0 +#define PT_RIGHT 2 +#define PT_TOP 1 +#define PT_DOWN 3 + +/* return most left/right/top/down pts indexes of given polygon */ +void object_find_extrem_points_index(Object_poly* o, + unsigned int *pts) +{ + unsigned int i; + for (i=0;i<4;i++) + pts[i] = 0; + + + for (i=1;i<o->pts_num;i++){ + if (o->pts[i].x < o->pts[pts[PT_LEFT]].x) + pts[PT_LEFT] = i; + if (o->pts[i].x > o->pts[pts[PT_RIGHT]].x) + pts[PT_RIGHT] = i; + if (o->pts[i].y < o->pts[pts[PT_TOP]].y) + pts[PT_TOP] = i; + if (o->pts[i].y > o->pts[pts[PT_DOWN]].y) + pts[PT_DOWN] = i; + } + +} + + +#define NUM_CALIPERS 4 +/* for debug purpose: display a vector on image */ +void draw_pt_vect(unsigned char *buf, int16_t x_in, int16_t y_in, + vect_t *v, point_t p) +{ + unsigned int i; + float n; + int16_t x, y; + float coef=1.0; + + if (!v->x && !v->y) + return; + + n = vect_norm(v); + coef = 1/n; + for (i=0;i<5;i++){ + x = p.x; + y = p.y; + + x+=(float)((v->x)*(float)i*(float)coef); + y+=(float)((v->y)*(float)i*(float)coef); + if ((x== p.x) && (y == p.y)) + buf[y*x_in+x] = 0x0; + else + buf[y*x_in+x] = 0x0; + } + +} + +#define CAL_X 3 +#define CAL_Y 0 + + +/* compute minimum rectangle area including the given convex polygon */ +void object_poly_get_min_ar(Object_poly *o, unsigned int *pts_index_out, + vect_t *v_out, vect_t *r1, vect_t*r2) +{ + vect_t calipers[NUM_CALIPERS]; + vect_t edges[NUM_CALIPERS]; + + unsigned int i; + unsigned int calipers_pts_index[NUM_CALIPERS]; + float angles[NUM_CALIPERS]; + float min_angle; + float total_rot_angle = 0; + int caliper_result_index; + + vect_t res1, res2; + float ps, n1, n2, caliper_n; + + float aera_tmp; + /* XXX hack sould be max*/ + float aera_min=0x100000; + + object_find_extrem_points_index(o, calipers_pts_index); + + calipers[0].x = 0; + calipers[0].y = 1; + + calipers[1].x = -1; + calipers[1].y = 0; + + calipers[2].x = 0; + calipers[2].y = -1; + + calipers[3].x = 1; + calipers[3].y = 0; + + + while (total_rot_angle <= M_PI/2){ + + for (i=0;i<NUM_CALIPERS;i++){ + /* compute polygon edge vector */ + edges[i].x = o->pts[(calipers_pts_index[i] + 1)%o->pts_num].x - + o->pts[calipers_pts_index[i]].x; + edges[i].y = o->pts[(calipers_pts_index[i] + 1)%o->pts_num].y - + o->pts[calipers_pts_index[i]].y; + + /* compute angle between caliper and polygon edge */ + angles[i] = vect_get_angle(&edges[i], &calipers[i]); + } + + /* find min angle */ + min_angle = angles[0]; + caliper_result_index = 0; + for (i=1;i<NUM_CALIPERS;i++){ + if (angles[i]<min_angle){ + min_angle = angles[i]; + caliper_result_index = i; + } + } + + /* rotate calipers */ + calipers[caliper_result_index] = edges[caliper_result_index]; + + for (i=caliper_result_index; i<caliper_result_index + o->pts_num; i++){ + calipers[(i+1) % NUM_CALIPERS] = calipers[i % NUM_CALIPERS]; + vect_rot_trigo(&calipers[(i+1) % NUM_CALIPERS]); + } + + /* update calipers point */ + for (i=0;i<NUM_CALIPERS;i++){ + if (angles[i]==min_angle) + calipers_pts_index[i] = (calipers_pts_index[i] + 1) % o->pts_num; + } + + res1.x = o->pts[calipers_pts_index[2]].x - o->pts[calipers_pts_index[0]].x; + res1.y = o->pts[calipers_pts_index[2]].y - o->pts[calipers_pts_index[0]].y; + + res2.x = o->pts[calipers_pts_index[3]].x - o->pts[calipers_pts_index[1]].x; + res2.y = o->pts[calipers_pts_index[3]].y - o->pts[calipers_pts_index[1]].y; + + ps = vect_pscal(&res1, &calipers[CAL_X]); + n1 = vect_norm(&res1); + caliper_n = vect_norm(&calipers[CAL_X]); + caliper_n*=caliper_n; + + res1 = calipers[CAL_X]; + + res1.x *= ps/(caliper_n); + res1.y *= ps/(caliper_n); + + + ps = vect_pscal(&res2, &calipers[CAL_Y]); + n1 = vect_norm(&res2); + + res2 = calipers[CAL_Y]; + + res2.x *= ps/(caliper_n); + res2.y *= ps/(caliper_n); + + n1 = vect_norm(&res1); + n2 = vect_norm(&res2); + + aera_tmp = n1*n2; + + if (aera_min >aera_tmp){ + aera_min = aera_tmp; + for (i=0;i<NUM_CALIPERS;i++){ + pts_index_out[i] = calipers_pts_index[i]; + } + *v_out = calipers[0]; + *r1 = res1; + *r2 = res2; + + } + total_rot_angle+=min_angle; + } + + return; +} + +#define COEF_CALIP 1 +/* transform caliper to rectangle coordinates */ +int object_poly_caliper_to_rectangle(Object_poly *o, + unsigned int *pts_index_out, vect_t* caliper, + vect_t *r1, vect_t*r2, point_t *p) +{ + line_t l1, l2; + vect_t caliper_tmp; + int ret, i; + double mp_x, mp_y; + point_t p_int1;//, p_int2; + + point_t p1, p2; + + caliper_tmp = *caliper; + + //IMG_DEBUG("cal: %" PRIi32 " %" PRIi32 "", caliper_tmp.x, caliper_tmp.y); + + mp_x = 0; + mp_y = 0; + + /* to be precise, calc 4 intersection of 4 calipers */ + for (i=0;i<NUM_CALIPERS;i++){ + p1.x = o->pts[pts_index_out[i]].x; + p1.y = o->pts[pts_index_out[i]].y; + + p2.x = p1.x+COEF_CALIP*caliper_tmp.x; + p2.y = p1.y+COEF_CALIP*caliper_tmp.y; + + pts2line(&p1, &p2, &l1); + + vect_rot_trigo(&caliper_tmp); + + p1.x = o->pts[pts_index_out[(i+1)%NUM_CALIPERS]].x; + p1.y = o->pts[pts_index_out[(i+1)%NUM_CALIPERS]].y; + + p2.x = p1.x+COEF_CALIP*caliper_tmp.x; + p2.y = p1.y+COEF_CALIP*caliper_tmp.y; + + pts2line(&p1, &p2, &l2); + + ret = intersect_line(&l1, &l2, &p_int1); + if (ret!=1) + return 0; + //IMG_DEBUG("int1 (%d): %" PRIi32 " %" PRIi32 " ", ret, p_int1.x, p_int1.y); + + mp_x+=p_int1.x; + mp_y+=p_int1.y; + + } + + + + p->x = lround(mp_x/NUM_CALIPERS); + p->y = lround(mp_y/NUM_CALIPERS); + + + return 1; + +} + +#define OBJECT_DIM 5 +/* split zone in many column's sized area */ +int split_rectangle(point_t *p, vect_t *r1, vect_t* r2, uint8_t max_zone, zone* zones, uint8_t color) +{ + int n1, n2; + int i, j; + int index=0; + int r1_s, r2_s; + point_t ptmp; + + + n1 = vect_norm(r1); + n2 = vect_norm(r2); + + r1_s = n1/OBJECT_DIM; + r2_s = n2/OBJECT_DIM; + + if (!r1_s || ! r2_s) + return 0; + + ptmp.x = p->x - r1->x/2 - r2->x/2 + (r1->x/(r1_s*2))+(r2->x/(r2_s*2)); + ptmp.y = p->y - r1->y/2 - r2->y/2 + (r1->y/(r1_s*2))+(r2->y/(r2_s*2)); + + for(i=0;i<r1_s;i++){ + for(j=0;j<r2_s;j++){ + zones[index].p.x = ptmp.x + (i*r1->x)/r1_s+(j*r2->x)/r2_s; + zones[index].p.y = ptmp.y + (i*r1->y)/r1_s+(j*r2->y)/r2_s; + zones[index].h = color; + zones[index].valid = 1; + + index++; + if (index>=max_zone) + return index; + + + } + } + + return index; +} + +#define OBJECT_SEMI_DIM (OBJECT_DIM/2) +#define MIN_SURFACE_PERCENT 50 +#define HIGHER_MAX_PIXEL 5 + + +int zone_has_enought_pixels(unsigned char* data, int16_t x_in, int16_t y_in, zone* z) +{ + int x, y; + uint16_t count, total_pix, higher_pixels; + + count = 0; + total_pix=0; + higher_pixels = 0; + + for (x = -OBJECT_SEMI_DIM; + (x <= OBJECT_SEMI_DIM) && (higher_pixels < HIGHER_MAX_PIXEL); + x++){ + for (y = -OBJECT_SEMI_DIM; + (y <= OBJECT_SEMI_DIM) && (higher_pixels < HIGHER_MAX_PIXEL); + y++){ + total_pix++; + if (data[x_in * (y + z->p.y) + x + z->p.x] == z->h) + count++; + + if (data[x_in * (y + z->p.y) + x + z->p.x] > z->h) + higher_pixels++; + + } + + } + + IMG_DEBUG("has enougth pixel (h: %d x %"PRIi32": y:%"PRIi32") total: %d/%d (tt: %d, hmax: %d)", z->h, z->p.x, z->p.y, + count, (total_pix * MIN_SURFACE_PERCENT) / 100, total_pix, higher_pixels); + + if ((count > (total_pix * MIN_SURFACE_PERCENT) / 100) && + (higher_pixels <HIGHER_MAX_PIXEL)) + return 1; + + return 0; +} + +int zone_filter_min_surface(unsigned char* data, int16_t x_in, int16_t y_in, + uint8_t color, unsigned int zones_num, zone* p) +{ + int i; + + for (i = 0; i < zones_num ; i++){ + if (zone_has_enought_pixels(data, x_in, y_in, &p[i])) + continue; + + p[i].valid = 0; + } + + IMG_NOTICE("num zone after min surf: %d", zones_num); + + return zones_num; + +} + +/* center is 15 cm radius*/ +#define CENTER_RADIUS 15 + +/* the complete column must be in the drop zone*/ +#define CENTER_MAX_DIST (15-3) + +/* the column must not be too close from center*/ +#define CENTER_MIN_DIST (8) + +int zone_filter_center(unsigned int zones_num, zone* p, int16_t center_x, int16_t center_y, int tweak_min_margin) +{ + int i; + vect_t v; + + for (i = 0; i < zones_num; i++){ + + v.x = p[i].p.x - center_x; + v.y = p[i].p.y - center_y; + IMG_DEBUG("square dist to center %"PRIi32" (%d %d)", + v.x*v.x + v.y*v.y, (CENTER_MIN_DIST+tweak_min_margin) * (CENTER_MIN_DIST+tweak_min_margin), CENTER_MAX_DIST * CENTER_MAX_DIST); + + if (v.x*v.x + v.y*v.y < CENTER_MAX_DIST * CENTER_MAX_DIST && + v.x*v.x + v.y*v.y > (CENTER_MIN_DIST+tweak_min_margin) * (CENTER_MIN_DIST+tweak_min_margin)) + continue; + + p[i].valid = 0; + + } + + return zones_num; +} + +#define MAX_DIST_TO_ZONE 2 + +unsigned int zone_filter_zone_rect(unsigned int zones_num, zone* p, int16_t center_x, int16_t center_y , uint8_t working_zone) +{ + int i; + + for (i = 0; i < zones_num; i++){ + + IMG_DEBUG("rct x:%"PRIi32" y:%"PRIi32" (centerx: %d)",p[i].p.x , p[i].p.y, center_x); + + if ((p[i].p.x > center_x - MAX_DIST_TO_ZONE) && (p[i].h > working_zone)) + continue; + + p[i].valid = 0; + } + + return zones_num; +} + + +/* delete point to render polygon convex */ +int object_poly_to_convex(Object_poly *o) +{ + unsigned int i, j; + vect_t v, w; + int16_t z; + unsigned int del_pts_num = 0; + + for (i=0;i<o->pts_num;){ + v.x = o->pts[(i + o->pts_num - 1)%o->pts_num].x - o->pts[i].x; + v.y = o->pts[(i + o->pts_num - 1)%o->pts_num].y - o->pts[i].y; + + w.x = o->pts[(i+1)%o->pts_num].x - o->pts[i].x; + w.y = o->pts[(i+1)%o->pts_num].y - o->pts[i].y; + + z = vect_pvect(&v, &w); + if (z>0){ + i+=1; + continue; + } + + /* found a convex angle (or colinear points) */ + for (j = i; j < o->pts_num-1; j++){ + o->pts[j] = o->pts[j+1]; + } + if (i!=0) + i-=1; + o->pts_num--; + del_pts_num++; + } + + return del_pts_num; +} + + + + + +#define DEFAULT_COLOR 255 +/* scan all image and find objects*/ +unsigned char *parcour_img(unsigned char* data, int16_t x_in, int16_t y_in, + Object_bb *sac_obj, Object_poly *sac_obj_poly, int16_t max_obj) +{ + int16_t i, obj_num; + + uint8_t in_color=0; + int16_t etat; + + Object_bb o; + int ret; + + obj_num = 0; + /* + first, delete borders + */ + for (i=0;i<x_in;i++){ + data[i] = 0; + data[(y_in - 1) * x_in + i] = 0; + } + + for (i=0;i<y_in;i++){ + data[i * x_in] = 0; + data[i * x_in + x_in - 1] = 0; + } + + + + etat = 0; + /* + 0 look for color (object or edge) + 1 look for edge end + */ + + for (i=1;i<x_in*y_in;i++){ + switch(etat){ + case 0: + //we are in the dark + switch(data[i]){ + case 0: + //look for in dark + break; + /* + case 1: + case 2: + case 0x15: + case 0x24: + */ + default: + in_color = data[i]; + etat = 1; + // we found an object + object_find_bounding_box(data, x_in, y_in, (i-1)%x_in, (i-1)/x_in, data[i], 255, &o); + + ret = store_obj(sac_obj, max_obj, &o); + /* if new object, process rotating calipers */ + if (ret){ + sac_obj_poly[obj_num].len = o.len; + object_find_poly(data, x_in, y_in, + (i-1)%x_in, (i-1)/x_in, + data[i], 255, &sac_obj_poly[obj_num]); + IMG_DEBUG("%d",sac_obj_poly[obj_num].pts_num); + object_poly_to_convex(&sac_obj_poly[obj_num]); + /* + for (j=0;j<sac_obj_poly[obj_num].pts_num;j++){ + data[sac_obj_poly[obj_num].pts[j].y*x_in + sac_obj_poly[obj_num].pts[j].x] = 8; + }*/ + sac_obj_poly[obj_num].color = data[i]; + obj_num++; + } + + break; + + case DEFAULT_COLOR: + //we must out of color + break; + } + break; + + case 1: + if (data[i] != in_color){ + i--; + etat = 0; + } + /* + we are in a color and want to go out of it + */ + break; + + } + + + + } + + + return data; + + +} +/* space between twin tower is 13 pixels*/ +#define SPACE_INTER_TWIN_TOWER (13) + +#define SPACE_INTER_TWIN_TOWER_TOLERENCE 3 + + + +/* find best twin tower for each zone */ +void find_twin_tower(uint8_t zones_num, zone* zones, int8_t sisters[MAX_ZONES][MAX_SISTER_PER_ZONE], + int16_t center_x, int16_t center_y) +{ + + uint8_t i, j; + uint8_t z_n; + int n1, n2; + unsigned int z1, z2, z3; + //int32_t scal1, scal2; + vect_t v, v1, v2; + line_t l; + point_t p; + unsigned int good_zone; + double dist, dist2; + unsigned int current_sister; + + /* init dummy sisters */ + for (i = 0; i < zones_num; i++) + for (j = 0; j < MAX_SISTER_PER_ZONE; j++) + sisters[i][j] = -1; + + + + for (z_n = 0; z_n < zones_num; z_n++){ + if (!zones[z_n].valid) + continue; + + current_sister = 0; + + for (i = 0; i < zones_num; i++){ + + + /* we already have max sisters */ + if (current_sister >= MAX_SISTER_PER_ZONE) + break; + + + if (!zones[i].valid) + continue; + + + if (i == z_n) + continue; + + /* twin tower must have same high */ + if (zones[i].h != zones[z_n].h) + continue; + + IMG_DEBUG("test sisters (%"PRIi32" %"PRIi32") (%"PRIi32" %"PRIi32")", + zones[z_n].p.x, zones[z_n].p.y, + zones[i].p.x, zones[i].p.y); + + + dist = sqrt( (zones[i].p.x - zones[z_n].p.x) * (zones[i].p.x - zones[z_n].p.x) + + (zones[i].p.y - zones[z_n].p.y) * (zones[i].p.y - zones[z_n].p.y) ); + + + IMG_DEBUG("sister space is %2.2f may be near %d", dist, SPACE_INTER_TWIN_TOWER); + + /* + twin tower must be close/far enought to drop lintel + */ + if (ABS(dist - SPACE_INTER_TWIN_TOWER) > SPACE_INTER_TWIN_TOWER_TOLERENCE) + continue; + + + pts2line(&zones[i].p, &zones[z_n].p, &l); + + /* + test the paralelism of the temple: + zone may be on same distance from center + */ + + + v1.x = zones[z_n].p.x - center_x; + v1.y = zones[z_n].p.y - center_y; + + dist = vect_norm(&v1); + + v2.x = zones[i].p.x - center_x; + v2.y = zones[i].p.y - center_y; + + dist2 = vect_norm(&v2); + + IMG_DEBUG("zone dist %2.2f %2.2f", dist, dist2); + if (ABS(dist-dist2) > 3){ + IMG_DEBUG("bad parallelism %2.2f", ABS(dist-dist2)); + continue; + } + + + + + /* no other aligned tower to avoid dropping on a lintel + * (3 aligned zone may mean lintel) + */ + + good_zone = 1; + + for (j = 0; j < zones_num; j++){ + if (j==i ||j == z_n) + continue; + + /* if third zone, but lower */ + if (zones[j].h <= zones[i].h) + continue; + + /* + check distance from dropping zone to + line formed by twin towers + */ + + proj_pt_line(&zones[j].p, &l, &p); + + + /* test if projected point is in the segement */ + + + v.x = zones[z_n].p.x - zones[i].p.x; + v.y = zones[z_n].p.y - zones[i].p.y; + + v1.x = p.x - zones[i].p.x; + v1.y = p.y - zones[i].p.y; + + n1 = vect_pscal_sign(&v, &v1); + + v.x = -v.x; + v.y = -v.y; + + v1.x = p.x - zones[z_n].p.x; + v1.y = p.y - zones[z_n].p.y; + + + n2 =vect_pscal_sign(&v, &v1); + + v.x = p.x - zones[j].p.x; + v.y = p.y - zones[j].p.y; + + dist = vect_norm(&v); + IMG_DEBUG("dist pt h %d n: (%d %d) (%"PRIi32" %"PRIi32") to line %2.2f", zones[j].h, n1, n2, zones[j].p.x, zones[j].p.y, dist); + + + if ((n1>=0 && n2>=0) && dist < OBJECT_DIM+2.){ + good_zone = 0; + break; + } + + + /* test if zone is far from points*/ + + v1.x = zones[j].p.x - zones[z_n].p.x; + v1.y = zones[j].p.y - zones[z_n].p.y; + + dist = vect_norm(&v1); + IMG_DEBUG("dist pt to z1 %2.2f", dist); + + if (dist < OBJECT_DIM){ + good_zone = 0; + break; + } + + v2.x = zones[j].p.x - zones[i].p.x; + v2.y = zones[j].p.y - zones[i].p.y; + + + dist = vect_norm(&v2); + IMG_DEBUG("dist pt to z2 %2.2f", dist); + + if (dist < OBJECT_DIM){ + good_zone = 0; + break; + } + + + + z1 = i; + z2 = z_n; + z3 = j; + + + + + + /* + XXX may be a lintel on lintel !! + */ + + } + + if (!good_zone) + continue; + + IMG_DEBUG("sisters ok (%"PRIi32" %"PRIi32") (%"PRIi32" %"PRIi32")", + zones[z_n].p.x, zones[z_n].p.y, + zones[i].p.x, zones[i].p.y); + + + sisters[z_n][current_sister] = i; + current_sister++; + } + } +} + +/* test if a higher zone is too close */ +int test_close_zone(uint8_t zones_num, zone* zones, unsigned int z_n) +{ + uint8_t i; + vect_t v; + double dist; + + for (i = 0; i < zones_num; i++){ + if (i == z_n) + continue; + if (zones[i].h <= zones[z_n].h) + continue; + + v.x = zones[i].p.x - zones[z_n].p.x; + v.y = zones[i].p.y - zones[z_n].p.y; + + dist = vect_norm(&v); + //IMG_DEBUG("dist pt to pt %2.2f", dist); + + if (dist < OBJECT_DIM){ + return 1; + } + + } + + return 0; +} + +#define MAX_COLUMN 4 +#define MAX_LINTEL 2 + +drop_column_zone drop_c[MAX_COLUMN]; +drop_lintel_zone drop_l[MAX_LINTEL]; + + +void reset_drop_zone(void) +{ + memset(drop_c, 0, sizeof(drop_c)); + memset(drop_l, 0, sizeof(drop_l)); + +} + + +void display_drop_zones(uint8_t n_columns, uint8_t n_lintels, zone* zones) +{ + unsigned int i; + + for (i=0;i<n_columns;i++) + IMG_NOTICE("c %d:(h:%d) (%"PRIi32" %"PRIi32") valid=%d", + i, drop_c[i].h, + zones[drop_c[i].z].p.x, zones[drop_c[i].z].p.y, + drop_c[i].valid); + + for (i=0;i<n_lintels;i++) + IMG_NOTICE("l %d:(h:%d) (%"PRIi32" %"PRIi32") " + "(%"PRIi32" %"PRIi32") valid=%d", + i, drop_l[i].h, + zones[drop_l[i].z1].p.x, zones[drop_l[i].z1].p.y, + zones[drop_l[i].z2].p.x, zones[drop_l[i].z2].p.y, drop_l[i].valid); + +} + +#define MY_MAX(a, b) ((a)>(b)?(a):(b)) + + +#if 0 +#define MAX_DROP_HIGH 8 + + +/* + recursive function to maximize points during object + dropping, given lintel/column number + working zone may be 1, 2 or 3 + */ +unsigned int solve_objects_dropping(unsigned int points, unsigned int points_max, + uint8_t n_columns, uint8_t n_lintels, + uint8_t zones_num, zone* zones, int8_t sisters[MAX_ZONES][MAX_SISTER_PER_ZONE], uint8_t working_zone) +{ + + uint8_t i, j; + unsigned int points_calc; + //unsigned int points_added = 0; + int sister; + int ret; + + + /* if no more objects, return points */ + if (n_columns == 0 && n_lintels == 0) + return MY_MAX(points, points_max); + + /* start by putting columns if so */ + for (i = 0; i < zones_num; i++){ + if (zones[i].h >= MAX_DROP_HIGH) + continue; + + if (n_columns){ + + ret = test_close_zone(zones_num, zones, i); + if (ret) + continue; + + zones[i].h++; + points_calc = solve_objects_dropping(points + zones[i].h, points_max, + n_columns - 1, n_lintels, + zones_num, zones, sisters, working_zone); + + if (points_calc > points_max){ + points_max = points_calc; + drop_c[n_columns - 1].z = i; + drop_c[n_columns - 1].h = zones[i].h; + drop_c[n_columns - 1].valid = 1; + + } + zones[i].h--; + } + /* we must depose all columns before dropping lintels */ + else if (n_lintels){ + + /* dont drop lintel on ground */ + if (zones[i].h <= working_zone) + continue; + + /* XXX todo need get second zone near selected one */ + //ret = find_twin_tower(zones_num, zones, i, &sister); + + for (j = 0; j < MAX_SISTER_PER_ZONE; j++){ + sister = sisters[i][j]; + if (sister == -1) + break; + if (zones[i].h != zones[sister].h){ + sister = -1; + } + + } + + if (sister == -1) + continue; + //IMG_DEBUG("sister found: %d %d (h=%d %p)", i, sister, zones[i].h, &zones[i].h); + + zones[i].h++; + zones[sister].h++; + + + points_calc = solve_objects_dropping(points + zones[i].h * 3, points_max, + n_columns, n_lintels - 1, + zones_num, zones, sisters, working_zone); + + if (points_calc > points_max){ + points_max = points_calc; + + drop_l[n_lintels - 1].z1 = i; + drop_l[n_lintels - 1].z2 = sister; + drop_l[n_lintels - 1].h = zones[i].h; + drop_l[n_lintels - 1].valid = 1; + + } + + + zones[sister].h--; + zones[i].h--; + } + } + + return MY_MAX(points, points_max); +} +#endif + + +/* */ +int find_column_dropzone(uint8_t zones_num, zone* zones) +{ + uint8_t i; + + uint8_t z_n = 0; + + if (zones_num <= 0) + return -1; + + for (i = 0; i < zones_num; i++){ + if (!zones[i].valid) + continue; + if (zones[i].h > zones[z_n].h) + z_n = i; + } + + + /* + now, chose dropzone closest to robot + meaning little x, big y + so maximise y-x + */ + for (i = 0; i < zones_num; i++){ + if (zones[i].h != zones[z_n].h) + continue; + if (!zones[i].valid) + continue; + if (zones[i].p.y - zones[i].p.x > zones[z_n].p.y - zones[z_n].p.x) + z_n = i; + } + + + + return z_n; +} + + + +uint8_t color2h(uint8_t color) +{ + return (0x100-color)/0x20; +} + +uint8_t h2color(uint8_t color) +{ + return color*0x20; +} + + +#define NUM_ZONE_GENERATE 8 +#define DIST_ZONE_GEN 9 + +/* + remove zone at ground level, and generate zones on + a circle at X cm from center + */ +unsigned int generate_center_ground_zones(unsigned char* data, int16_t x_in, int16_t y_in, + zone * zones, unsigned int zones_num, uint8_t max_zones, int16_t center_x, int16_t center_y) +{ + double c_a, s_a; + uint8_t i, j; + double px1, py1, px2, py2; + + + /* first del zone at level 2 */ + for (i = 0; i < zones_num; ){ + if (zones[i].h!=2){ + i++; + continue; + } + + for (j = i; j < zones_num-1; j++) + zones[j] = zones[j+1]; + + zones_num--; + + } + + /* generate zones around circle */ + + c_a = cos(2*M_PI/NUM_ZONE_GENERATE); + s_a = sin(2*M_PI/NUM_ZONE_GENERATE); + + px1 = DIST_ZONE_GEN; + py1 = 0; + + for (i = 0; i < NUM_ZONE_GENERATE; i++){ + + zones[zones_num].p.x = center_x + px1; + zones[zones_num].p.y = center_y + py1; + zones[zones_num].h = 2; + zones[zones_num].valid = 1; + + + px2 = px1*c_a + py1*s_a; + py2 = -px1*s_a + py1*c_a; + + px1 = px2; + py1 = py2; + + /* skip zone if it is not in img */ + if (zones[zones_num].p.x < 0 || zones[zones_num].p.y < 0 || + zones[zones_num].p.x >= x_in || zones[zones_num].p.y > y_in) + continue; + + /* skip zone if not enougth pixels */ + if (!zone_has_enought_pixels(data, x_in, y_in, &zones[zones_num])) + continue; + + zones_num++; + if (zones_num >= max_zones) + break; + + } + + return zones_num; + + +} + + +/* + remove zone at ground level, and generate zones on + a line at X cm from robot + */ +unsigned int generate_rectangle_ground_zones(unsigned char* data, int16_t x_in, int16_t y_in, + zone * zones, unsigned int zones_num, uint8_t max_zones, int16_t center_x, int16_t center_y, + uint8_t working_zone) +{ + uint8_t i, j; + uint8_t y; + + /* first del zone at level i */ + for (i = 0; i < zones_num; ){ + if (zones[i].h != working_zone ){ + i++; + continue; + } + + for (j = i; j < zones_num-1; j++) + zones[j] = zones[j+1]; + + zones_num--; + } + + + /* generate zones on a line */ + for (y = OBJECT_DIM; y < y_in; y+=OBJECT_DIM){ + + zones[zones_num].p.x = center_x; + zones[zones_num].p.y = y; + zones[zones_num].h = working_zone ; + zones[zones_num].valid = 1; + + if (!zone_has_enought_pixels(data, x_in, y_in, &zones[zones_num])) + continue; + zones_num++; + + if (zones_num >= max_zones) + break; + + } + return zones_num; + +} + + +#define MAX_DECAL_LINE 5 +#define ENOUGHT_ZONE_PIXEL 2 + +void recal_img_y(unsigned char* buffer, int16_t x_in, int16_t y_in, + uint8_t working_zone) +{ + uint8_t i, j; + uint8_t cpt; + + /* recal img only for central zone */ + if (working_zone !=2) + return; + + for (i = 0; i < MAX_DECAL_LINE; i++){ + cpt = 0; + for (j = 0; j < x_in; j++){ + if (buffer[i*x_in + j] ==2) + cpt++; + } + + if (cpt >= ENOUGHT_ZONE_PIXEL) + break; + } + + memmove(buffer, &buffer[i * x_in], x_in * y_in - i*x_in); + memset(&buffer[x_in * y_in - i * x_in], 0, i*x_in); +} + + +#define MAX_OBJECTS 20 + +#define MAX_ZONES_PER_OBJECT 20 + + +uint8_t g_zone_num; +zone g_all_zones[MAX_ZONES]; + +uint8_t process_img(unsigned char *buffer, int16_t x_in, int16_t y_in, + zone * all_zones, uint8_t max_zones) +{ + + int ret; + int i, j; + + zone zones[MAX_ZONES_PER_OBJECT]; + + vect_t caliper; + unsigned int pts_cal[4]; + point_t ptmp; + vect_t r1, r2; + int zone_len; + + + uint8_t zone_num = 0; + + Object_bb sac_obj[MAX_OBJECTS]; + Object_poly sac_obj_poly[MAX_OBJECTS]; + + + + /* + XXX fix: only decal for working zone 2/(1?) + but we dont have info yet + */ + recal_img_y(buffer, x_in, y_in, 2); + + memset(sac_obj, 0, sizeof(sac_obj)); + memset(sac_obj_poly, 0, sizeof(sac_obj_poly)); + + + /* first, find polygons*/ + parcour_img(buffer, x_in, y_in, sac_obj, sac_obj_poly, MAX_OBJECTS); + + /* enclose each poygon in the min area polygon + then, split each rectangle in dropping zone + */ + for (i=0;i<MAX_OBJECTS;i++){ + + if (!sac_obj_poly[i].pts_num) + continue; + + IMG_DEBUG("obj: %d %d %d %d %d", + i, + sac_obj[i].x_min, + sac_obj[i].y_min, + sac_obj[i].x_max, + sac_obj[i].y_max); + + //IMG_DEBUG("poly pts_num: %d", sac_obj_poly[i].pts_num); + + object_poly_get_min_ar(&sac_obj_poly[i], &pts_cal[0], &caliper, &r1, &r2); + + ret = object_poly_caliper_to_rectangle(&sac_obj_poly[i], &pts_cal[0], &caliper, + &r1, &r2, &ptmp); + + if (!ret) + continue; + + /* + IMG_DEBUG("r: (%3"PRIi32" %3"PRIi32") " + "(%3"PRIi32" %3"PRIi32")", + r1.x, r1.y, r2.x, r2.y); + IMG_DEBUG("intersection: %"PRIi32" %"PRIi32"", + ptmp.x, ptmp.y); + */ + + zone_len = split_rectangle(&ptmp, &r1, &r2, + MAX_ZONES_PER_OBJECT, &zones[0], sac_obj_poly[i].color); + //IMG_DEBUG("split ok %d", zone_len); + + zone_len = zone_filter_min_surface(buffer, x_in, y_in, + sac_obj_poly[i].color, + zone_len, &zones[0]); + + for (j = 0; j < zone_len && zone_num < max_zones; zone_num++, j++) + all_zones[zone_num] = zones[j]; + + } + + + IMG_NOTICE("num zones end: %d", zone_num); + + return zone_num; +} + + +void process_img_to_zone(unsigned char *buffer, int16_t x_in, int16_t y_in) +{ + g_zone_num = process_img(buffer, x_in, y_in, + g_all_zones, MAX_ZONES); +} + +uint8_t filter_zones(unsigned char *buffer, int16_t x_in, int16_t y_in, + zone * all_zones, uint8_t zone_num, uint8_t max_zones, + uint8_t working_zone, int16_t center_x, int16_t center_y, + int tweak_min_margin) +{ + uint8_t i; + + /* first valid all zones */ + for (i = 0; i < zone_num; i++){ + all_zones[i].valid = 1; + + /* filter zone lower thatn working zone */ + if (all_zones[i].h < working_zone) + all_zones[i].valid = 0; + } + + + /* + generate correct zone at ground level + (depending on working zone) + */ + if (working_zone == 2) + zone_num = generate_center_ground_zones(buffer, x_in, y_in, + all_zones, zone_num, max_zones, center_x, center_y); + else + zone_num = generate_rectangle_ground_zones(buffer, x_in, y_in, + all_zones, zone_num, max_zones, center_x, center_y, + working_zone); + + /* filter zone position, depending on workingzone */ + if (working_zone == 2) + zone_num = zone_filter_center(zone_num, all_zones, center_x, center_y, tweak_min_margin); + else + zone_num = zone_filter_zone_rect(zone_num, all_zones, center_x, center_y , working_zone); + + + + /* display zones (debug purpose) */ + + for (i = 0; i < zone_num; i++){ + //buffer[all_zones[i].p.y*x_in+all_zones[i].p.x] = 0x3; + IMG_NOTICE("h:%d (v:%d) x:%"PRIi32" y:%"PRIi32"", all_zones[i].h, all_zones[i].valid, all_zones[i].p.x, all_zones[i].p.y); + + } + + IMG_NOTICE("num zones: %d", zone_num); + + + + + return zone_num; +} + + +/* + return -1 if not column dropzone is found + return column hight if found +*/ +int8_t get_column_dropzone(unsigned char *buffer, int16_t x_in, int16_t y_in, + uint8_t working_zone, int16_t center_x, int16_t center_y, + int16_t * dropzone_x, int16_t * dropzone_y) +{ + uint8_t zone_num; + int c_drop_zone; + + + + zone_num = filter_zones(buffer, x_in, y_in, + g_all_zones, g_zone_num, MAX_ZONES, + working_zone, center_x, center_y, + 0); + + c_drop_zone = find_column_dropzone(zone_num, g_all_zones); + + if (c_drop_zone<0) + return -1; + + *dropzone_x = g_all_zones[c_drop_zone].p.x; + *dropzone_y = g_all_zones[c_drop_zone].p.y; + + *dropzone_x = (*dropzone_x) * PIXEL2CM; + *dropzone_y = (*dropzone_y) * PIXEL2CM + 30; + + return g_all_zones[c_drop_zone].h; +} + +#define ROBOT_SEMI_INTERCOLUMN_SPACE 75 + +uint8_t is_temple_there(unsigned char * buffer, int16_t x_in, int16_t y_in, + uint8_t h, int16_t center_x, int16_t center_y) +{ + zone z; + int ret; + int i; + + + IMG_NOTICE("test z (mm) : x:%d y:%d", center_x, center_y); + IMG_NOTICE("test z:(pix): x:%d y:%d", (int)(center_x/ PIXEL2CM), (int)(center_y/ PIXEL2CM)); + + + z.p.x = center_x / PIXEL2CM; + z.p.y = (center_y - ROBOT_SEMI_INTERCOLUMN_SPACE) / PIXEL2CM ; + z.h = h; + z.valid = 1; + ret = zone_has_enought_pixels(buffer, x_in, y_in, &z); + IMG_NOTICE("test z1: %d", ret); + + if (!ret) + return 0; + + z.p.x = center_x / PIXEL2CM; + z.p.y = (center_y + ROBOT_SEMI_INTERCOLUMN_SPACE)/ PIXEL2CM; + z.h = h; + z.valid = 1; + ret = zone_has_enought_pixels(buffer, x_in, y_in, &z); + IMG_NOTICE("test z2: %d", ret); + if (!ret) + return 0; + + + /* + if middle zone is less or egual to tested temple + */ + z.p.x = center_x / PIXEL2CM; + z.p.y = center_y / PIXEL2CM; + + for (i = h; i > 0; i--){ + z.h = i; + z.valid = 1; + ret = zone_has_enought_pixels(buffer, x_in, y_in, &z); + IMG_NOTICE("test z3:(h=%d) %d", i, ret); + + if (ret) + return 1; + } + + return 0; + +} + + +int8_t find_temple_dropzone(unsigned char *buffer, int16_t x_in, int16_t y_in, + uint8_t working_zone, int16_t center_x, int16_t center_y, + int16_t * dropzone_x, int16_t * dropzone_y) +{ + uint8_t zone_num; + int8_t sisters[MAX_ZONES][MAX_SISTER_PER_ZONE]; + int8_t z_n = -1; + uint8_t i, j; + + + /* find all drop zone */ + zone_num = filter_zones(buffer, x_in, y_in, + g_all_zones, g_zone_num, MAX_ZONES, + working_zone, center_x, center_y, + -2); + + /* precompute possible twin towers */ + find_twin_tower(zone_num, g_all_zones, sisters, center_x, center_y); + + + for (i=0; i< zone_num; i++){ + IMG_DEBUG("all sisters: %d", i); + for (j=0;j<MAX_SISTER_PER_ZONE;j++){ + IMG_DEBUG("s: %d", sisters[i][j]); + } + } + + /* only use first sister of each zone */ + for (i=0; i< zone_num; i++){ + + /* if zone doesn't have twin tower */ + if (sisters[i][0] == -1) + continue; + + if (!g_all_zones[i].valid) + continue; + + if (z_n == -1){ + z_n = i; + continue; + } + + /* if we found higher twin tower */ + if (g_all_zones[z_n].h > g_all_zones[i].h) + continue; + + z_n = i; + } + + IMG_NOTICE("twin tower found :z_n=%d", z_n); + if (z_n == -1) + return -1; + + IMG_NOTICE("(%"PRIi32" %"PRIi32") (%"PRIi32" %"PRIi32")", + g_all_zones[z_n].p.x, g_all_zones[z_n].p.y, + g_all_zones[sisters[z_n][0]].p.x, g_all_zones[sisters[z_n][0]].p.y); + + + *dropzone_x = ((double)(g_all_zones[z_n].p.x + g_all_zones[sisters[z_n][0]].p.x)*PIXEL2CM ) / 2; + *dropzone_y = ((double)(g_all_zones[z_n].p.y + g_all_zones[sisters[z_n][0]].p.y)*PIXEL2CM ) / 2 + 30; + + + return g_all_zones[z_n].h; + +} + diff --git a/projects/microb2009/sensorboard/img_processing.h b/projects/microb2009/sensorboard/img_processing.h new file mode 100644 index 0000000..4c06237 --- /dev/null +++ b/projects/microb2009/sensorboard/img_processing.h @@ -0,0 +1,111 @@ + + + +typedef struct _Object_bb +{ + uint8_t x_min; + uint8_t x_max; + uint8_t y_min; + uint8_t y_max; + uint16_t len; +}Object_bb; + +#define POLY_MAX_PTS 12 +typedef struct _Object_poly +{ + uint16_t pixels_perim; + uint16_t pts_num; + point_t pts[POLY_MAX_PTS]; + uint16_t len; + uint8_t color; +}Object_poly; + + +typedef struct _zone +{ + point_t p; + uint8_t h:7; + uint8_t valid:1; +}zone; + + +typedef struct _drop_column_zone +{ + uint8_t valid; + uint8_t z; + uint8_t h; +}drop_column_zone; + +typedef struct _drop_lintel_zone +{ + uint8_t valid; + uint8_t z1; + uint8_t h; + uint8_t z2; +}drop_lintel_zone; + + + + +#define MAX_ZONES 30 + +#define MAX_SISTER_PER_ZONE 1 + + + +unsigned char *parcour_img(unsigned char* data, int16_t x_in, int16_t y_in, Object_bb *sac_obj, Object_poly *sac_obj_poly, int16_t max_obj); + +float vect_get_angle(vect_t*v, vect_t* w); + +void object_poly_get_min_ar(Object_poly *o, unsigned int *pts_index_out, vect_t *v_out, vect_t *r1, vect_t*r2); + +void draw_pt_vect(unsigned char *buf, int16_t x_in, int16_t y_in, vect_t *v, point_t p); + +void vect_rot_trigo(vect_t* v); + +int object_poly_caliper_to_rectangle(Object_poly *o, + unsigned int *pts_index_out, vect_t* caliper, + vect_t *r1, vect_t*r2, point_t *p); + +int split_rectangle(point_t *p, vect_t *r1, vect_t* r2, uint8_t max_zone, zone* zones, uint8_t color); + + + +int zone_filtre_min_surface(unsigned char* data, int16_t x_in, int16_t y_in, + uint8_t color, unsigned int num_zone, zone* p); + +void reset_drop_zone(void); +void display_drop_zones(uint8_t n_columns, uint8_t n_lintels, zone* zones); + +unsigned int solve_objects_dropping(unsigned int points, unsigned int points_max, + uint8_t n_columns, uint8_t n_lintels, + uint8_t zones_num, zone* zones, int8_t sisters[MAX_ZONES][MAX_SISTER_PER_ZONE], uint8_t working_zone); + +uint8_t process_img(unsigned char *buffer, int16_t x_in, int16_t y_in, + zone * all_zones, uint8_t max_zones); + + +uint8_t color2h(uint8_t color); +uint8_t h2color(uint8_t color); + +int8_t get_column_dropzone(unsigned char *buffer, int16_t x_in, int16_t y_in, + uint8_t working_zone, int16_t center_x, int16_t center_y, + int16_t * dropzone_x, int16_t * dropzone_y); + + +uint8_t is_temple_there(unsigned char * buffer, int16_t x_in, int16_t y_in, + uint8_t h, int16_t center_x, int16_t center_y); + + + +int8_t find_temple_dropzone(unsigned char *buffer, int16_t x_in, int16_t y_in, + uint8_t working_zone, int16_t center_x, int16_t center_y, + int16_t * dropzone_x, int16_t * dropzone_y); + +void process_img_to_zone(unsigned char *buffer, int16_t x_in, int16_t y_in); + +#define PIXEL2CM (300./27.) + + +extern uint8_t g_zone_num; +extern zone g_all_zones[MAX_ZONES]; diff --git a/projects/microb2009/sensorboard/main.c b/projects/microb2009/sensorboard/main.c new file mode 100755 index 0000000..82fa2a5 --- /dev/null +++ b/projects/microb2009/sensorboard/main.c @@ -0,0 +1,279 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.4 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> +#include <avr/eeprom.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> +#include <aversive/error.h> + +#include <ax12.h> +#include <uart.h> +#include <spi.h> +#include <i2c.h> +#include <encoders_spi.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <time.h> +#include <adc.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "../common/eeprom_mapping.h" +#include "../common/i2c_commands.h" + +#include "main.h" +#include "ax12_user.h" +#include "cmdline.h" +#include "sensor.h" +#include "actuator.h" +#include "cs.h" +#include "i2c_protocol.h" +#include "beacon.h" +#include "scanner.h" + +/* 0 means "programmed" + * ---- with 16 Mhz quartz + * CKSEL 3-0 : 0111 + * SUT 1-0 : 10 + * CKDIV8 : 1 + * ---- bootloader + * BOOTZ 1-0 : 01 (4K bootloader) + * BOOTRST : 0 (reset on bootloader) + * ---- jtag + * jtagen : 0 + */ + +struct genboard gen; +struct sensorboard sensorboard; + +/***********************/ + +void bootloader(void) +{ +#define BOOTLOADER_ADDR 0x3f000 + if (pgm_read_byte_far(BOOTLOADER_ADDR) == 0xff) { + printf_P(PSTR("Bootloader is not present\r\n")); + return; + } + cli(); + BRAKE_ON(); + /* ... very specific :( */ + TIMSK0 = 0; + TIMSK1 = 0; + TIMSK2 = 0; + TIMSK3 = 0; + TIMSK4 = 0; + TIMSK5 = 0; + EIMSK = 0; + UCSR0B = 0; + UCSR1B = 0; + UCSR2B = 0; + UCSR3B = 0; + SPCR = 0; + TWCR = 0; + ACSR = 0; + ADCSRA = 0; + + EIND = 1; + __asm__ __volatile__ ("ldi r31,0xf8\n"); + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("eijmp\n"); + + /* never returns */ +} + +void do_led_blink(__attribute__((unused)) void *dummy) +{ +#if 1 /* simple blink */ + static uint8_t a=0; + + if(a) + LED1_ON(); + else + LED1_OFF(); + + a = !a; +#endif +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + cpt++; + sei(); + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +int main(void) +{ + /* brake */ + BRAKE_OFF(); + BRAKE_DDR(); + + /* CPLD reset on PG3 */ + DDRG |= 1<<3; + PORTG &= ~(1<<3); /* implicit */ + + /* LEDS */ + DDRJ |= 0x0c; + DDRL = 0xc0; + LED1_OFF(); + memset(&gen, 0, sizeof(gen)); + memset(&sensorboard, 0, sizeof(sensorboard)); + sensorboard.flags = DO_ENCODERS | DO_CS | DO_POWER; // DO_BD + + /* UART */ + uart_init(); +#if CMDLINE_UART == 3 + fdevopen(uart3_dev_send, uart3_dev_recv); + uart_register_rx_event(3, emergency); +#elif CMDLINE_UART == 1 + fdevopen(uart1_dev_send, uart1_dev_recv); + uart_register_rx_event(1, emergency); +#else +# error not supported +#endif + + //eeprom_write_byte(EEPROM_MAGIC_ADDRESS, EEPROM_MAGIC_SENSORBOARD); + /* check eeprom to avoid to run the bad program */ + if (eeprom_read_byte(EEPROM_MAGIC_ADDRESS) != + EEPROM_MAGIC_SENSORBOARD) { + sei(); + printf_P(PSTR("Bad eeprom value\r\n")); + while(1); + } + + /* LOGS */ + error_register_emerg(mylog); + error_register_error(mylog); + error_register_warning(mylog); + error_register_notice(mylog); + error_register_debug(mylog); + + /* SPI + ENCODERS */ + encoders_spi_init(); /* this will also init spi hardware */ + + /* I2C */ + i2c_protocol_init(); + i2c_init(I2C_MODE_SLAVE, I2C_SENSORBOARD_ADDR); + i2c_register_recv_event(i2c_recvevent); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* PWM */ + PWM_NG_TIMER_16BITS_INIT(1, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_1); + PWM_NG_TIMER_16BITS_INIT(4, TIMER_16_MODE_PWM_10, + TIMER4_PRESCALER_DIV_1); + + PWM_NG_INIT16(&gen.pwm1_4A, 4, A, 10, PWM_NG_MODE_SIGNED | + PWM_NG_MODE_SIGN_INVERTED, + &PORTD, 4); + PWM_NG_INIT16(&gen.pwm2_4B, 4, B, 10, PWM_NG_MODE_SIGNED, + &PORTD, 5); + PWM_NG_INIT16(&gen.pwm3_1A, 1, A, 10, PWM_NG_MODE_SIGNED, + &PORTD, 6); + PWM_NG_INIT16(&gen.pwm4_1B, 1, B, 10, PWM_NG_MODE_SIGNED, + &PORTD, 7); + + + /* servos */ + PWM_NG_TIMER_16BITS_INIT(3, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&gen.servo1, 3, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_TIMER_16BITS_INIT(5, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&gen.servo2, 5, A, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&gen.servo3, 5, B, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&gen.servo4, 5, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + + /* SCHEDULER */ + scheduler_init(); + + scheduler_add_periodical_event_priority(do_led_blink, NULL, + 100000L / SCHEDULER_UNIT, + LED_PRIO); + /* all cs management */ + microb_cs_init(); + + /* sensors, will also init hardware adc */ + sensor_init(); + + /* TIME */ + time_init(TIME_PRIO); + + /* ax12 */ + ax12_user_init(); + + /* beacon */ + beacon_init(); + scheduler_add_periodical_event_priority(beacon_calc, NULL, + 20000L / SCHEDULER_UNIT, + BEACON_PRIO); + + + + /* scan */ + + + scanner_init(); + scheduler_add_periodical_event_priority(do_scan, NULL, + (1024L*1L) / SCHEDULER_UNIT, + CS_PRIO-1); + + sei(); + + scan_params.speed = SCAN_DEFAULT_SPEED; + scan_params.debug = 0; + + scanner_calibre_mirror(); + scanner_calibre_laser(); + + beacon_calibre_pos(); + + + printf_P(PSTR("\r\n")); + printf_P(PSTR("Dass das Gluck deinen Haus setzt.\r\n")); + cmdline_interact(); + + + + return 0; +} diff --git a/projects/microb2009/sensorboard/main.h b/projects/microb2009/sensorboard/main.h new file mode 100755 index 0000000..3a4ff83 --- /dev/null +++ b/projects/microb2009/sensorboard/main.h @@ -0,0 +1,154 @@ +/* + * Copyright Droids Corporation (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.h,v 1.4 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#define LED_TOGGLE(port, bit) do { \ + if (port & _BV(bit)) \ + port &= ~_BV(bit); \ + else \ + port |= _BV(bit); \ + } while(0) + +#define LED1_ON() sbi(PORTJ, 2) +#define LED1_OFF() cbi(PORTJ, 2) +#define LED1_TOGGLE() LED_TOGGLE(PORTJ, 2) + +#define LED2_ON() sbi(PORTL, 7) +#define LED2_OFF() cbi(PORTL, 7) +#define LED2_TOGGLE() LED_TOGGLE(PORTL, 7) + +#define LED3_ON() sbi(PORTJ, 3) +#define LED3_OFF() cbi(PORTJ, 3) +#define LED3_TOGGLE() LED_TOGGLE(PORTJ, 3) + +#define LED4_ON() sbi(PORTL, 6) +#define LED4_OFF() cbi(PORTL, 6) +#define LED4_TOGGLE() LED_TOGGLE(PORTL, 6) + +#define BRAKE_DDR() do { DDRJ |= 0xF0; } while(0) +#define BRAKE_ON() do { PORTJ |= 0xF0; } while(0) +#define BRAKE_OFF() do { PORTJ &= 0x0F; } while(0) + +#define BEACON_ENCODER ((void *)0) +#define SCANNER_ENCODER ((void *)1) + +#define BEACON_PWM ((void *)&gen.pwm1_4A) +#define SCANNER_PWM ((void *)&gen.pwm2_4B) +#define PICKUP_WHEEL_L_PWM ((void *)&gen.pwm3_1A) +#define PICKUP_WHEEL_R_PWM ((void *)&gen.pwm4_1B) + +#define BEACON_POS_SENSOR 2 +#define SCANNER_POS_SENSOR 7 +#define SCANNER_MAXCOLUMN_SENSOR 1 + + + +#define SCANNER_POS_OUT 179 +#define SCANNER_POS_CALIBRE 370 +#define SCANNER_POS_IN 400 + + +/** ERROR NUMS */ +#define E_USER_I2C_PROTO 195 +#define E_USER_SENSOR 196 +#define E_USER_BEACON 197 +#define E_USER_SCANNER 198 +#define E_USER_IMGPROCESS 199 + +#define LED_PRIO 170 +#define TIME_PRIO 160 +#define ADC_PRIO 120 +#define CS_PRIO 100 +#define BEACON_PRIO 80 +#define I2C_POLL_PRIO 20 + +#define CS_PERIOD 5000L + +#define NB_LOGS 4 + +/* generic to all boards */ +struct genboard { + /* command line interface */ + struct rdline rdl; + char prompt[RDLINE_PROMPT_SIZE]; + + /* motors */ + struct pwm_ng pwm1_4A; + struct pwm_ng pwm2_4B; + struct pwm_ng pwm3_1A; + struct pwm_ng pwm4_1B; + + /* servos */ + struct pwm_ng servo1; + struct pwm_ng servo2; + struct pwm_ng servo3; + struct pwm_ng servo4; + + /* ax12 interface */ + AX12 ax12; + + /* log */ + uint8_t logs[NB_LOGS+1]; + uint8_t log_level; + uint8_t debug; +}; + +struct cs_block { + uint8_t on; + struct cs cs; + struct pid_filter pid; + struct quadramp_filter qr; + struct blocking_detection bd; +}; + +/* sensorboard specific */ +struct sensorboard { +#define DO_ENCODERS 1 +#define DO_CS 2 +#define DO_BD 4 +#define DO_POWER 8 + uint8_t flags; /* misc flags */ + + /* control systems */ + struct cs_block beacon; + struct cs_block scanner; + + /* robot status */ + uint8_t our_color; +}; + +extern struct genboard gen; +extern struct sensorboard sensorboard; + +/* start the bootloader */ +void bootloader(void); + +#define wait_cond_or_timeout(cond, timeout) \ +({ \ + microseconds __us = time_get_us2(); \ + uint8_t __ret = 1; \ + while(! (cond)) { \ + if (time_get_us2() - __us > (timeout)*1000L) {\ + __ret = 0; \ + break; \ + } \ + } \ + __ret; \ +}) diff --git a/projects/microb2009/sensorboard/pid_config.h b/projects/microb2009/sensorboard/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/projects/microb2009/sensorboard/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/projects/microb2009/sensorboard/rdline_config.h b/projects/microb2009/sensorboard/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/sensorboard/scanner.c b/projects/microb2009/sensorboard/scanner.c new file mode 100644 index 0000000..dfc869e --- /dev/null +++ b/projects/microb2009/sensorboard/scanner.c @@ -0,0 +1,898 @@ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/error.h> +#include <aversive/pgmspace.h> +#include <pwm_ng.h> +#include <pid.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <adc.h> +#include <spi.h> +#include <ax12.h> + +#include <time.h> +#include <blocking_detection_manager.h> + +#include <encoders_spi.h> + +#include <rdline.h> + +#include "sensor.h" + +#include <uart.h> + +#include "main.h" +#include "scanner.h" + +#include "cmdline.h" + + +#include "scan_h_l.h" + + +#include <vect_base.h> +#include "img_processing.h" + + +#include "../common/i2c_commands.h" + +#define SCANNER_DEBUG(args...) DEBUG(E_USER_SCANNER, args) +#define SCANNER_NOTICE(args...) NOTICE(E_USER_SCANNER, args) +#define SCANNER_ERROR(args...) ERROR(E_USER_SCANNER, args) + + +#define MODULO_TIMER (1023L) + +#define COEFF_TIMER (2) +#define COEFF_MULT (1000L) +#define COEFF_MULT2 (1000L) + +double TELEMETRE_A = TELEMETRE_A_INIT; +double TELEMETRE_B = TELEMETRE_B_INIT; + + + + +struct scan_params scan_params; + +static volatile int32_t scan_delta_pos; +static volatile int32_t scan_tick_cur = 0; +static volatile int32_t scan_tick_prev = 0; +/*static volatile int32_t count = 0; +static volatile int32_t count_diff_rising = 0; +static volatile int32_t count_diff_falling = 0; +*/ +static int32_t scanner_coeff = 0; + +//static volatile int8_t valid_scanner = 0; + +static volatile int32_t scan_pos_cur = 0; + +static int32_t pos_ref = 0; + + +int32_t encoders_spi_get_value_scanner(void *number) +{ + int32_t ret; + + ret = encoders_spi_get_value(number); + return ret*4; +} + + +void encoders_spi_set_value_scanner(void * number, int32_t v) +{ + encoders_spi_set_value(number, v/4); +} + +int32_t encoders_spi_update_scanner(void * number) +{ + int32_t ret; + uint8_t flags; + + IRQ_LOCK(flags); + ret = encoders_spi_get_value_scanner(number); + scan_delta_pos = ret - scan_pos_cur; + scan_pos_cur = ret; + scan_tick_prev = scan_tick_cur; + scan_tick_cur = TCNT3; + + scanner_coeff = (scan_delta_pos * COEFF_MULT) / + ((scan_tick_cur - scan_tick_prev + MODULO_TIMER + 1) & MODULO_TIMER); + + IRQ_UNLOCK(flags); + + + return ret; +} + +int32_t encoders_spi_get_value_scanner_interpolation(void * number) +{ + uint8_t flags; + int32_t pos; + + IRQ_LOCK(flags); + pos = scan_pos_cur; + pos += (scanner_coeff * ((TCNT3 - scan_tick_cur + MODULO_TIMER + 1)& MODULO_TIMER ))/ + COEFF_MULT; + + IRQ_UNLOCK(flags); + + return pos; +} + + +void scanner_reset_pos(void) +{ + pwm_ng_set(SCANNER_PWM, 0); + encoders_spi_set_value_scanner(SCANNER_ENCODER, 0); +} + +void scanner_init(void) +{ + + scan_params.working = 0; + scan_params.must_stop = 0; + + scanner_reset_pos(); + pos_ref = encoders_spi_get_value_scanner(SCANNER_ENCODER); + + //memset(&scanner, 0, sizeof(struct scanner)); + + scan_delta_pos = 0; + + /*for(i=0;i<SCANNER_MAX_SAMPLE;i++) + scanner_sample_size[i] = 0;*/ + + + +} + + +#define SCANNER_OFFSET_CALIBRE 1500 + +#define CALIBRE_LASER_SAMPLE 100 + + + + + + +void scanner_calibre_laser(void) +{ + unsigned int i; + int32_t laser_value = 0; + + /* arm out */ + pwm_ng_set(&gen.servo3, SCANNER_POS_OUT); + + /* set mirror to have vertical laser */ + cs_set_consign(&sensorboard.scanner.cs, (35L*SCANNER_STEP_TOUR)/100); + + wait_ms(500); + + /* + laser must point on the ground: + we sample laser in order to determine + laser cold/warm calibration + */ + + for (i = 0; i<CALIBRE_LASER_SAMPLE; i++){ + laser_value += adc_get_value( ADC_REF_AVCC | MUX_ADC13 ); + wait_ms(2); + } + + laser_value/=CALIBRE_LASER_SAMPLE; + + SCANNER_NOTICE("laser calibration value %"PRIi32"", laser_value); + + quadramp_set_1st_order_vars(&sensorboard.scanner.qr, scan_params.speed, scan_params.speed); /* set speed */ + cs_set_consign(&sensorboard.scanner.cs, 0); + wait_ms(200); + + + TELEMETRE_B = TELEMETRE_B_INIT + ((double)(424 - laser_value))*6./90.; + + SCANNER_NOTICE("TEL B value %2.2f", TELEMETRE_B); + + + /* arm in */ + + pwm_ng_set(&gen.servo3, SCANNER_POS_IN); + + +} + + + + + +void scanner_calibre_mirror(void) +{ + + sensorboard.flags &= ~DO_CS; + + + + /* set arm in calibre position */ + pwm_ng_set(&gen.servo3, SCANNER_POS_CALIBRE); + wait_ms(500); + + + + /* init scanner pos */ + pwm_ng_set(SCANNER_PWM, 100); + + /* find rising edge of the mirror*/ + wait_ms(100); + while (sensor_get(SCANNER_POS_SENSOR)); + wait_ms(100); + while (!sensor_get(SCANNER_POS_SENSOR)); + + pwm_ng_set(SCANNER_PWM, 0); + + + scanner_reset_pos(); + pid_reset(&sensorboard.scanner.pid); + cs_set_consign(&sensorboard.scanner.cs, 0); + + + quadramp_reset(&sensorboard.scanner.qr); + + + sensorboard.flags |= DO_CS; + + + /* + set mirror to set laser point at maximum + distance from robot + */ + encoders_spi_set_value_scanner(SCANNER_ENCODER, -SCANNER_OFFSET_CALIBRE); + wait_ms(100); + + /* arm in */ + + pwm_ng_set(&gen.servo3, SCANNER_POS_IN); + +} + + +/* arm must be in OUT position! */ +void scanner_do_scan(void){ + scan_params.working = 1; + scan_params.dropzone_h = -1; + + + quadramp_set_1st_order_vars(&sensorboard.scanner.qr, scan_params.speed, scan_params.speed); /* set speed */ + + scan_params.sample_i = MAX_SAMPLE; + scan_params.pos_start_scan = encoders_spi_get_value_scanner(SCANNER_ENC); + + memset(scan_params.sample_tab, 0xff, MAX_SAMPLE*sizeof(uint8_t)); + + cs_set_consign(&sensorboard.scanner.cs, scan_params.pos_start_scan+SCANNER_STEP_TOUR*200L); + + scan_params.last_col_n = 0; + scan_params.last_row_n = 0; + scan_params.last_sample = 0; + + +} + + +void scanner_end_process(void) +{ + int16_t dropzone_x, dropzone_y; + int8_t ret; + uint32_t t1, t2; + + t1 = time_get_us2(); + + + SCANNER_NOTICE("process img algo %d", scan_params.algo); + if (scan_params.algo == I2C_SCANNER_ALGO_COLUMN_DROPZONE) { + SCANNER_NOTICE("column dropzone h: %d x:%d y:%d", scan_params.drop_zone.working_zone, + scan_params.drop_zone.center_x, scan_params.drop_zone.center_y); + + ret = get_column_dropzone(scan_params.sample_tab, PIX_PER_SCAN, MAX_SAMPLE/PIX_PER_SCAN, + scan_params.drop_zone.working_zone, scan_params.drop_zone.center_x, scan_params.drop_zone.center_y, + &dropzone_x, &dropzone_y); + + scan_params.dropzone_h = ret; + scan_params.dropzone_x = dropzone_x; + scan_params.dropzone_y = dropzone_y; + + SCANNER_NOTICE("best column h:%d x:%d y:%d", + scan_params.dropzone_h, + scan_params.dropzone_x, scan_params.dropzone_y); + + + } + else if (scan_params.algo == I2C_SCANNER_ALGO_CHECK_TEMPLE){ + SCANNER_NOTICE("checktemple h: %d x:%d y:%d", scan_params.check_temple.level, + scan_params.check_temple.temple_x, scan_params.check_temple.temple_y); + ret = is_temple_there(scan_params.sample_tab, PIX_PER_SCAN, MAX_SAMPLE/PIX_PER_SCAN, + scan_params.check_temple.level, scan_params.check_temple.temple_x, scan_params.check_temple.temple_y); + + scan_params.dropzone_h = ret?scan_params.check_temple.level:-1; + } + else if (scan_params.algo == I2C_SCANNER_ALGO_TEMPLE_DROPZONE){ + SCANNER_NOTICE("temple dropzone h: %d x:%d y:%d", scan_params.drop_zone.working_zone, + scan_params.drop_zone.center_x, scan_params.drop_zone.center_y); + ret = find_temple_dropzone(scan_params.sample_tab, PIX_PER_SCAN, MAX_SAMPLE/PIX_PER_SCAN, + scan_params.drop_zone.working_zone, scan_params.drop_zone.center_x, scan_params.drop_zone.center_y, + &dropzone_x, &dropzone_y); + + scan_params.dropzone_h = ret; + scan_params.dropzone_x = dropzone_x; + scan_params.dropzone_y = dropzone_y; + + SCANNER_NOTICE("best temple h:%d x:%d y:%d", + scan_params.dropzone_h, + scan_params.dropzone_x, scan_params.dropzone_y); + + } + + scan_params.working = 0; + + t2 = time_get_us2(); + SCANNER_NOTICE("process total time %"PRIi32"",t2-t1); + + +} + + +void scanner_scan_autonomous(void) +{ + /* arm out*/ + pwm_ng_set(&gen.servo3, SCANNER_POS_OUT); + time_wait_ms(300); + + scanner_do_scan(); + + while(scan_params.sample_i > 0){ + time_wait_ms(10); + } + + /* arm in */ + pwm_ng_set(&gen.servo3, SCANNER_POS_IN); + +} + + +/* + * called from IRQ: + * mode can be off/prepare/start, see in i2c_commands.h + */ +void scanner_set_mode(uint8_t mode) +{ + if (mode == I2C_SENSORBOARD_SCANNER_PREPARE){ + /* reset flag max pos */ + scan_params.max_column_detected = 0; + + /* arm out */ + pwm_ng_set(&gen.servo3, SCANNER_POS_OUT); + + } + else if (mode == I2C_SENSORBOARD_SCANNER_STOP){ + /* arm in */ + pwm_ng_set(&gen.servo3, SCANNER_POS_IN); + scan_params.must_stop = 1; + } + else if (mode == I2C_SENSORBOARD_SCANNER_START){ + scan_params.max_column_detected = 0; + scan_params.must_stop = 0; + + + /* start scan in background */ + scanner_do_scan(); + } + + +} + +/* +void scanner_stop(void) +{ + sensorboard.scanner.on = 0; + pwm_ng_set(SCANNER_PWM, 0); +} +*/ + + +/* +int32_t encoders_spi_get_scanner_speed(void * dummy) +{ + return scanner_speed; +} +*/ + + +//uint8_t sample_tab[MAX_SAMPLE]; +//uint16_t sample_i = 0; + + +//#define offset_a (75.*M_PI/180.) +//float offset_a; +//float offset_b; + +//int32_t pos_start_scan; + + +/* get motor angle in radian; return mirror angle in radian, cos a sin a */ +void ang2_a_mirror(float b, float * c_a, float* s_a, float* a) +{ + float x2, y2; + float A, DELTA, B, D; + + b+=scan_params.offset_b; + x2 = X + l1*cos(b); + y2 = Y + l1*sin(b); + + A = (l3*l3 + x2*x2 + y2*y2 - l2*l2)/(2*l3); + + DELTA = -(A*A - x2*x2 - y2*y2); + B = sqrt(DELTA); + + D = x2*x2 + y2*y2; + + *c_a = (x2*A + y2*B)/D; + *s_a = -(x2*B - y2*A)/D; + + *a = atan2(*s_a, *c_a); + + *a += scan_params.offset_a; + // *s_a = sin(*a); + // *c_a = cos(*a); + +} + +/* get telemeter dist , cos a, sin a, a and return H, L of scanned point */ +void ang2_H_L(float l_telemetre, float c_a, float s_a, float a, float *H, float *L) +{ + float d; + d = h_mirror*c_a/s_a; + *H = (l_telemetre - l_mirror - d)*sin(2*a); + *L = l_mirror + d + *H/tan(2*a); + + //*H+= 8*sin(a-scan_params.offset_a); +} + + + +//int32_t last_col_n; +//int32_t last_row_n; +//uint8_t last_sample; + +//uint8_t h_limit[] = {40, 53, 66, 78, 94, 111, 123}; +//uint8_t h_limit[] = {37, 48, 61, 72, 94, 111, 123}; + +/* last high is dummy, to deal higher columns */ +uint8_t h_limit[] = {68, 79, 93, 107, 121, 138, 155, 170, 250}; +#define H_MARGIN 7 + + +#if 0 +void do_scan(void * dummy) +{ + + unsigned int i; + int16_t a; + int32_t row_n; + int32_t col_n; + + + int32_t tour_pos; + int32_t pos, last_pos; + int32_t pos_tmp ; + int32_t mot_pos; + float dist; + uint8_t min_sample; + + float b, c_a, s_a, H, L, m_a; + int32_t H_fin; + + + if (scan_params.sample_i==0) + return; + + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + + if (scan_params.sample_i==1){ + SCANNER_DEBUG("dump end enc %ld %d ", mot_pos, PIX_PER_SCAN); + //scanner.flags &= (~CS_ON); + + + + /* stop scan at cur pos + 10 round */ + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + mot_pos = SCANNER_STEP_TOUR * ((mot_pos/SCANNER_STEP_TOUR) + 1) ; + + SCANNER_DEBUG("set to %ld ", mot_pos); + + cs_set_consign(&sensorboard.scanner.cs, mot_pos); + //pwm_ng_set(SCANNER_MOT_PWM, 0); + + + } + + mot_pos-= scan_params.pos_start_scan; + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC13 ); + + + //dist = (a-TELEMETRE_B)/TELEMETRE_A; + dist = TELEMETRE_A * a +TELEMETRE_B; + + //SCANNER_DEBUG("enc val = %ld", encoders_microb_get_value((void *)SCANNER_ENC)); + + + //sample_tab[MAX_SAMPLE-sample_i] = a>0x1ff?0x1FF:a; + //sample_tab[MAX_SAMPLE-sample_i] |= PINF&2?0x200:0; + + + row_n = (mot_pos)/(SCANNER_STEP_TOUR/2); +#if 0 + /* separe scan forward/backword */ + if (row_n%2){ + row_n/=2; + } + else{ + row_n/=2; + row_n+=30; + } +#endif + + tour_pos = (mot_pos)%(SCANNER_STEP_TOUR); + + b = (2.*M_PI)*(float)tour_pos/(float)(SCANNER_STEP_TOUR); + + ang2_a_mirror(b, &c_a, &s_a, &m_a); + ang2_H_L(dist, c_a, s_a, m_a, &H, &L); + + + SCANNER_DEBUG("%ld %d", tour_pos, a); + + if (H >0){ + printf("zarb H\n"); + H = 0; + } + + if (dist> SCAN_MAX_DIST){ + H = 0; + L = 0; + } + + H = H;//m_a*180/M_PI; + L = L;//(L-100)*PIX_PER_SCAN; + + //SCANNER_DEBUG("polling : ADC0 = %i %f",a, dist); + //SCANNER_DEBUG("%f %f %2.2f %f", H, L, m_a*180./M_PI, dist); + + + //SCANNER_DEBUG("%f %f", dist, m_a*180/M_PI); + + H=(H+SCAN_H_MAX)*SCAN_H_COEF; + L-=SCAN_L_MIN; + + + /* XXX may never append */ + if (L<0) + L=0; + + + /* first filter => pixel modulo level */ +#define H_BASE 10 +#define H_MUL 14 + H_fin = H;//+SCAN_H_MAX; + //H_fin = ((H_fin-H_BASE)/H_MUL)*H_MUL + H_BASE; + + if (scan_params.filter){ + H_fin = 11; // default is level 11 + for (i=0;i<sizeof(h_limit)/sizeof(uint8_t);i++){ + if (H < h_limit[i]-H_MARGIN){ + H_fin = i; + break; + } + } + } + + //SCANNER_DEBUG("%f %f", dist, m_a*180/M_PI); + //SCANNER_DEBUG("%f %f", m_a*180/M_PI, b*180/M_PI); + + //SCANNER_DEBUG("%d %f", a, b*180/M_PI); + //SCANNER_DEBUG("%f %f %f", H, m_a*180/M_PI, offset_b); + + //SCANNER_DEBUG("%d %2.2f ", a, tour_pos); + + + //SCANNER_DEBUG("%f %f %ld %d", H, L, tour_pos, a); + + + /* + if (row_n%2){ + //tour_pos = ((SCANNER_STEP_TOUR/2)-tour_pos); + tour_pos = (tour_pos*PIX_PER_SCAN)/(SCANNER_STEP_TOUR); + } + else{ + tour_pos = ((SCANNER_STEP_TOUR-tour_pos)*PIX_PER_SCAN)/(SCANNER_STEP_TOUR); + } + */ + col_n = (PIX_PER_SCAN*L)/(SCAN_L_MAX-SCAN_L_MIN); + if (col_n>PIX_PER_SCAN) + printf("BUG!!! RECALC MAX L"); + + //col_n = (PIX_PER_SCAN+col_n -5)%PIX_PER_SCAN; + + //pos = (row_n*SCANNER_STEP_TOUR + tour_pos)/STEP_PER_POS; + //pos= row_n*PIX_PER_SCAN+tour_pos; + //last_pos= last_row_n*PIX_PER_SCAN+last_tour_pos; + + + + pos= row_n*PIX_PER_SCAN+col_n; + last_pos= scan_params.last_row_n*PIX_PER_SCAN+scan_params.last_col_n; + + //SCANNER_DEBUG("%ld %ld %ld %ld", row_n, col_n, pos, H_fin); + + //a-=0x100; + a-=200; + //a/=10; + + if (0<= pos && pos <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos] = a>0xff?0xFF:a; + //sample_tab[(int)L] = H ; + scan_params.sample_tab[pos] = H_fin; + nop(); + if ((scan_params.last_row_n == row_n) && ABS(last_pos-pos)>1){ + /* we have a hole, pad it with minimal hight */ + if (H_fin>scan_params.last_sample) + min_sample = scan_params.last_sample; + else + min_sample = H_fin; + + //printf("(%ld, %ld) (%ld %ld)", last_col_n, last_row_n, col_n, row_n); + + /* fill grow, avoid erasing curent pos */ + if (pos > last_pos){ + pos_tmp = last_pos; + last_pos = pos; + //printf("loop1 on (%ld, %ld) %ld", pos_tmp, last_pos, last_pos-pos_tmp); + + } + else{ + pos_tmp = pos+1; + //printf("loop1 on (%ld, %ld) %ld", pos_tmp, last_pos, last_pos-pos_tmp); + } + + + for (;pos_tmp< last_pos;pos_tmp++){ + if (0< pos_tmp && pos_tmp <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos_tmp] = min_sample; + nop(); + + } + + + } + + scan_params.last_row_n = row_n; + scan_params.last_col_n = col_n; + scan_params.last_sample = H_fin; + + + //printf("pos : %ld", pos); + //sample_tab[sample_i] = a>0x1ff?0x1FF:a; + + //sample_ok_tab[MAX_SAMPLE-sample_i] = PORTF&2; + + /* + if (((pos <MAX_SAMPLE)) && (tour_pos<=(SCANNER_STEP_TOUR/2))) + sample_tab[pos] = 0xffff; + */ + scan_params.sample_i--; +} +#endif + + + +void do_scan(void * dummy) +{ + + int i, j; + int16_t a; + int32_t row_n; + int32_t col_n; + + + int32_t tour_pos; + int32_t pos, last_pos; + int32_t pos_tmp ; + int32_t mot_pos; + uint8_t min_sample; + double H, L; + int32_t H_fin, L_fin; + + uint8_t flags; + + union{ + uint16_t u16; + lookup_h_l h_l; + }val; + + + + if (scan_params.sample_i==0) + return; + + + + scan_params.max_column_detected = !!sensor_get(SCANNER_MAXCOLUMN_SENSOR); + + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + if (scan_params.sample_i==1 || scan_params.max_column_detected || scan_params.must_stop ){ + + /* reset sample num in case of max column detected */ + IRQ_LOCK(flags); + scan_params.sample_i = 1; + IRQ_UNLOCK(flags); + + + SCANNER_DEBUG("dump end enc %"PRIi32" %d ", mot_pos, PIX_PER_SCAN); + //scanner.flags &= (~CS_ON); + + /* stop scan at cur pos + 10 round */ + mot_pos = encoders_spi_get_value_scanner_interpolation((void *)SCANNER_ENC); + mot_pos = SCANNER_STEP_TOUR * ((mot_pos/SCANNER_STEP_TOUR) + 1) ; + + SCANNER_DEBUG("set to %"PRIi32" ", mot_pos); + + cs_set_consign(&sensorboard.scanner.cs, mot_pos); + //pwm_ng_set(SCANNER_MOT_PWM, 0); + + + /* end working */ + + //scanner_end_process(); + if (!scan_params.must_stop && !scan_params.max_column_detected) + process_img_to_zone(scan_params.sample_tab, PIX_PER_SCAN, MAX_SAMPLE/PIX_PER_SCAN); + + + scan_params.working = 0; + + } + + mot_pos-= scan_params.pos_start_scan; + + a = adc_get_value( ADC_REF_AVCC | MUX_ADC13 ); + + + tour_pos = (mot_pos)%(SCANNER_STEP_TOUR); + + + if (scan_params.debug != 0) + SCANNER_DEBUG("%ld %d ", tour_pos, a); + + /* lookup in precomputed array */ + + + j = (DIM_DIST * (telemetre_to_cm(a)-TELEMETRE_MIN_CM))/(TELEMETRE_MAX_CM - TELEMETRE_MIN_CM); + i = (DIM_ANGLE * tour_pos)/STEP_PER_ROUND; + + + if (j<0) + j=0; + if (j>=DIM_DIST) + j = DIM_DIST-1; + + if (i>=DIM_ANGLE) + i = DIM_ANGLE-1; + + + val.u16 = pgm_read_word_near(&array_h_l[j][i]); + + + //val.u16 = pgm_read_word_near(&array_h_l[(a-TELEMETRE_MIN)/DIST_STEP][mot_pos/ANGLE_STEP]); + //val.u16 = pgm_read_word_near(&array_h_l[a][tp]); + H = val.h_l.h; + L = val.h_l.l; + /* + val.u16 = pgm_read_word_near(&array_h_l[(a-TELEMETRE_MIN)/DIST_STEP][mot_pos/ANGLE_STEP]); + + H = val.h_l.h; + L = val.h_l.l; + */ + H_fin = H; + L_fin = L; + + + if (L<=0) + L = 0; + + col_n = (PIX_PER_SCAN*L)/(SCAN_L_MAX-SCAN_L_MIN); + if (col_n>=PIX_PER_SCAN) { + //printf("BUG!!! RECALC MAX L"); + col_n = PIX_PER_SCAN-1; + } + + //col_n = (PIX_PER_SCAN+col_n -5)%PIX_PER_SCAN; + + //pos = (row_n*SCANNER_STEP_TOUR + tour_pos)/STEP_PER_POS; + //pos= row_n*PIX_PER_SCAN+tour_pos; + //last_pos= last_row_n*PIX_PER_SCAN+last_tour_pos; + + row_n = (mot_pos)/(SCANNER_STEP_TOUR/2); + + + pos= row_n*PIX_PER_SCAN+col_n; + last_pos= scan_params.last_row_n*PIX_PER_SCAN+scan_params.last_col_n; + + //SCANNER_DEBUG("%ld %ld %ld %ld", row_n, col_n, pos, H_fin); + + //a-=0x100; + a-=200; + //a/=10; + + if (0<= pos && pos <MAX_SAMPLE)// && row_n%2) + //sample_tab[pos] = a>0xff?0xFF:a; + //sample_tab[(int)L] = H ; + scan_params.sample_tab[pos] = H_fin; + nop(); + if ((scan_params.last_row_n == row_n) && ABS(last_pos-pos)>1){ + /* we have a hole, pad it with minimal hight */ + if (H_fin>scan_params.last_sample) + min_sample = scan_params.last_sample; + else + min_sample = H_fin; + + //printf("(%ld, %ld) (%ld %ld)", last_col_n, last_row_n, col_n, row_n); + + /* fill grow, avoid erasing curent pos */ + if (pos > last_pos){ + pos_tmp = last_pos; + last_pos = pos; + //printf("loop1 on (%ld, %ld) %ld", pos_tmp, last_pos, last_pos-pos_tmp); + + } + else{ + pos_tmp = pos+1; + //printf("loop1 on (%ld, %ld) %ld", pos_tmp, last_pos, last_pos-pos_tmp); + } + + + for (;pos_tmp< last_pos;pos_tmp++){ + if (0< pos_tmp && pos_tmp <MAX_SAMPLE){ + //scan_params.sample_tab[pos_tmp] = min_sample; + nop(); + } + + } + + + } + + scan_params.last_row_n = row_n; + scan_params.last_col_n = col_n; + scan_params.last_sample = H_fin; + + + //printf("pos : %ld", pos); + //sample_tab[sample_i] = a>0x1ff?0x1FF:a; + + //sample_ok_tab[MAX_SAMPLE-sample_i] = PORTF&2; + + /* + if (((pos <MAX_SAMPLE)) && (tour_pos<=(SCANNER_STEP_TOUR/2))) + sample_tab[pos] = 0xffff; + */ + IRQ_LOCK(flags); + scan_params.sample_i--; + IRQ_UNLOCK(flags); + +} diff --git a/projects/microb2009/sensorboard/scanner.h b/projects/microb2009/sensorboard/scanner.h new file mode 100644 index 0000000..2a549c8 --- /dev/null +++ b/projects/microb2009/sensorboard/scanner.h @@ -0,0 +1,158 @@ + +#define SCANNER_ENC ((void *)1) + +/* relative motor position from mirror axis */ +#define X 4.5 +#define Y -1.25 + +/* length of motor arm*/ +#define l1 0.9 + +/* length of bielle */ +#define l2 2.113 + +/* length of mirror (rotating axe to bielle) */ +//#define l3 4.714 +#define l3 4.1613 + +/* distance from telemetre to mirror axis */ +#define l_mirror 24.0 + +/* higth between mirror axis and horizontal laser beam*/ +#define h_mirror -1.0 + + +/* transform telemeter unit to cm + using linear approximation + d_telemetre = a * cm + b +*/ +//#define TELEMETRE_A (16.76) +//#define TELEMETRE_B (-476.) + + +#define TELEMETRE_A_INIT 0.067325 +#define TELEMETRE_B_INIT 23.225 + + +extern double TELEMETRE_A; +extern double TELEMETRE_B; + + + + +#define SCAN_L_MIN 15. +#define SCAN_L_MAX 40. + +#define SCAN_H_MAX 40. +#define SCAN_H_COEF (255./(SCAN_H_MAX+10.)) + +#define SCAN_MAX_DIST 70. + +#define MAX_SAMPLE (1500L) + + +// TRUE encoder value: 3531.75 +#define SCANNER_STEP_TOUR (14127L) + +//#define PIX_PER_SCAN 30L +#define PIX_PER_SCAN (25L) + +void scanner_init(void); +void scanner_set_mode(uint8_t mode); + +void scanner_end_process(void); + +void scanner_calibre_laser(void); +void scanner_calibre_mirror(void); + + +void scanner_scan_autonomous(void); + +int32_t encoders_spi_update_scanner(void * number); +int32_t encoders_spi_get_value_scanner(void *number); + +void do_scan(void * dummy); + + + +struct scan_params{ + uint16_t sample_i; + float offset_a; + float offset_b; + int speed; + uint8_t filter; + int32_t pos_start_scan; + + int32_t last_col_n; + int32_t last_row_n; + uint8_t last_sample; + + uint8_t debug; + uint8_t sample_tab[MAX_SAMPLE+10]; + volatile uint8_t working; + uint8_t must_stop; + + + uint8_t algo; + + + union { + struct { + uint8_t working_zone; + int16_t center_x; + int16_t center_y; + } drop_zone; + + struct { + uint8_t level; + int16_t temple_x; + int16_t temple_y; + } check_temple; + }; + + + + /* + for column drop zone answer + */ + int8_t dropzone_h; + int16_t dropzone_x; + int16_t dropzone_y; + + uint8_t max_column_detected; +}; + + + +#define STEP_PER_ROUND 14127 + +#define TELEMETRE_MIN 66 +#define TELEMETRE_MAX 466 + + +#define TELEMETRE_MIN_CM (25) +#define TELEMETRE_MAX_CM (55) + + +#define DIM_ANGLE (400/4) +#define DIM_DIST ((TELEMETRE_MAX_CM - TELEMETRE_MIN_CM)*3) + + + +#define ANGLE_STEP (STEP_PER_ROUND/DIM_ANGLE +1) +#define DIST_STEP ((TELEMETRE_MAX - TELEMETRE_MIN) /DIM_DIST +1) + + +typedef struct _lookup_h_l{ + uint16_t h:4; + uint16_t l:12; +}lookup_h_l; + +#define telemetre_to_cm(t) ((double)(TELEMETRE_A * ((double)(t)) + TELEMETRE_B)) + +#define SCAN_DEFAULT_SPEED 600 + + +extern struct scan_params scan_params; + + diff --git a/projects/microb2009/sensorboard/scheduler_config.h b/projects/microb2009/sensorboard/scheduler_config.h new file mode 100755 index 0000000..2547a24 --- /dev/null +++ b/projects/microb2009/sensorboard/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.2 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 8 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/microb2009/sensorboard/sensor.c b/projects/microb2009/sensorboard/sensor.c new file mode 100644 index 0000000..6cfb491 --- /dev/null +++ b/projects/microb2009/sensorboard/sensor.c @@ -0,0 +1,258 @@ +/* + * Copyright Droids Corporation (2009) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: sensor.c,v 1.3 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#include <stdlib.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <adc.h> +#include <scheduler.h> +#include <ax12.h> +#include <pwm_ng.h> + +#include <pid.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <blocking_detection_manager.h> + +#include <parse.h> +#include <rdline.h> + +#include "main.h" +#include "sensor.h" + +/************ ADC */ + +struct adc_infos { + uint16_t config; + int16_t value; + int16_t prev_val; + int16_t (*filter)(struct adc_infos *, int16_t); +}; + +/* reach 90% of the value in 4 samples */ +int16_t rii_light(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + (int32_t)adc->prev_val / 2; + return adc->prev_val / 2; +} + +/* reach 90% of the value in 8 samples */ +int16_t rii_medium(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + ((int32_t)adc->prev_val * 3) / 4; + return adc->prev_val / 4; +} + +/* reach 90% of the value in 16 samples */ +int16_t rii_strong(struct adc_infos *adc, int16_t val) +{ + adc->prev_val = val + ((int32_t)adc->prev_val * 7) / 8; + return adc->prev_val / 8; +} + + +#define ADC_CONF(x) ( ADC_REF_AVCC | ADC_MODE_INT | MUX_ADC##x ) + +/* define which ADC to poll, see in sensor.h */ +static struct adc_infos adc_infos[ADC_MAX] = { + + [ADC_CSENSE1] = { .config = ADC_CONF(0), .filter = rii_medium }, + [ADC_CSENSE2] = { .config = ADC_CONF(1), .filter = rii_medium }, + [ADC_CSENSE3] = { .config = ADC_CONF(2), .filter = rii_medium }, + [ADC_CSENSE4] = { .config = ADC_CONF(3), .filter = rii_medium }, + + /* add adc on "cap" pins if needed */ +/* [ADC_CAP1] = { .config = ADC_CONF(10) }, */ +/* [ADC_CAP2] = { .config = ADC_CONF(11) }, */ +/* [ADC_CAP3] = { .config = ADC_CONF(12) }, */ +/* [ADC_CAP4] = { .config = ADC_CONF(13) }, */ +}; + +static void adc_event(int16_t result); + +/* called every 10 ms, see init below */ +static void do_adc(void *dummy) +{ + /* launch first conversion */ + adc_launch(adc_infos[0].config); +} + +static void adc_event(int16_t result) +{ + static uint8_t i = 0; + + /* filter value if needed */ + if (adc_infos[i].filter) + adc_infos[i].value = adc_infos[i].filter(&adc_infos[i], + result); + else + adc_infos[i].value = result; + + i ++; + if (i >= ADC_MAX) + i = 0; + else + adc_launch(adc_infos[i].config); +} + +int16_t sensor_get_adc(uint8_t i) +{ + int16_t tmp; + uint8_t flags; + + IRQ_LOCK(flags); + tmp = adc_infos[i].value; + IRQ_UNLOCK(flags); + return tmp; +} + +/************ boolean sensors */ + + +struct sensor_filter { + uint8_t filter; + uint8_t prev; + uint8_t thres_off; + uint8_t thres_on; + uint8_t cpt; + uint8_t invert; +}; + +/* pullup mapping: + * CAP 5,6,7,8 + * voltage div mapping: + * CAP 1 + */ +static struct sensor_filter sensor_filter[SENSOR_MAX] = { + [S_CAP1] = { 1, 0, 0, 1, 0, 0 }, /* 0 */ + [S_CAP2] = { 1, 0, 0, 1, 0, 0 }, /* 1 */ + [S_CAP3] = { 1, 0, 0, 1, 0, 0 }, /* 2 */ + [S_CAP4] = { 1, 0, 0, 1, 0, 0 }, /* 3 */ + [S_CAP5] = { 1, 0, 0, 1, 0, 0 }, /* 4 */ + [S_CAP6] = { 1, 0, 0, 1, 0, 0 }, /* 5 */ + [S_CAP7] = { 1, 0, 0, 1, 0, 0 }, /* 6 */ + [S_CAP8] = { 1, 0, 0, 1, 0, 0 }, /* 7 */ + [S_RESERVED1] = { 10, 0, 3, 7, 0, 0 }, /* 8 */ + [S_RESERVED2] = { 10, 0, 3, 7, 0, 0 }, /* 9 */ + [S_RESERVED3] = { 1, 0, 0, 1, 0, 0 }, /* 10 */ + [S_RESERVED4] = { 1, 0, 0, 1, 0, 0 }, /* 11 */ + [S_RESERVED5] = { 1, 0, 0, 1, 0, 0 }, /* 12 */ + [S_RESERVED6] = { 1, 0, 0, 1, 0, 0 }, /* 13 */ + [S_RESERVED7] = { 1, 0, 0, 1, 0, 0 }, /* 14 */ + [S_RESERVED8] = { 1, 0, 0, 1, 0, 0 }, /* 15 */ +}; + +/* value of filtered sensors */ +static uint16_t sensor_filtered = 0; + +/* sensor mapping : + * 0-3: PORTK 2->5 (cap1 -> cap4) (adc10 -> adc13) + * 4-5: PORTL 0->1 (cap5 -> cap6) + * 6-7: PORTE 3->4 (cap7 -> cap8) + * 8-15: reserved + */ + +uint16_t sensor_get_all(void) +{ + uint16_t tmp; + uint8_t flags; + IRQ_LOCK(flags); + tmp = sensor_filtered; + IRQ_UNLOCK(flags); + return tmp; +} + +uint8_t sensor_get(uint8_t i) +{ + uint16_t tmp = sensor_get_all(); + return (tmp & _BV(i)); +} + +/* get the physical value of pins */ +static uint16_t sensor_read(void) +{ + uint16_t tmp = 0; + tmp |= (uint16_t)((PINK & (_BV(2)|_BV(3)|_BV(4)|_BV(5))) >> 2) << 0; + tmp |= (uint16_t)((PINL & (_BV(0)|_BV(1))) >> 0) << 4; + tmp |= (uint16_t)((PINE & (_BV(3)|_BV(4))) >> 3) << 6; + /* add reserved sensors here */ + return tmp; +} + +/* called every 10 ms, see init below */ +static void do_boolean_sensors(void *dummy) +{ + uint8_t i; + uint8_t flags; + uint16_t sensor = sensor_read(); + uint16_t tmp = 0; + + for (i=0; i<SENSOR_MAX; i++) { + if ((1 << i) & sensor) { + if (sensor_filter[i].cpt < sensor_filter[i].filter) + sensor_filter[i].cpt++; + if (sensor_filter[i].cpt >= sensor_filter[i].thres_on) + sensor_filter[i].prev = 1; + } + else { + if (sensor_filter[i].cpt > 0) + sensor_filter[i].cpt--; + if (sensor_filter[i].cpt <= sensor_filter[i].thres_off) + sensor_filter[i].prev = 0; + } + + if (sensor_filter[i].prev) { + tmp |= (1UL << i); + } + } + IRQ_LOCK(flags); + sensor_filtered = tmp; + IRQ_UNLOCK(flags); +} + + + +/************ global sensor init */ +#define BACKGROUND_ADC 0 + +/* called every 10 ms, see init below */ +static void do_sensors(void *dummy) +{ + if (BACKGROUND_ADC) + do_adc(NULL); + do_boolean_sensors(NULL); +} + +void sensor_init(void) +{ + adc_init(); + if (BACKGROUND_ADC) + adc_register_event(adc_event); + /* CS EVENT */ + scheduler_add_periodical_event_priority(do_sensors, NULL, + 10000L / SCHEDULER_UNIT, + ADC_PRIO); + +} + diff --git a/projects/microb2009/sensorboard/sensor.h b/projects/microb2009/sensorboard/sensor.h new file mode 100644 index 0000000..c2b18a7 --- /dev/null +++ b/projects/microb2009/sensorboard/sensor.h @@ -0,0 +1,56 @@ +/* + * Copyright Droids Corporation (2009) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: sensor.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +/* synchronize with sensor.c */ +#define ADC_CSENSE1 0 +#define ADC_CSENSE2 1 +#define ADC_CSENSE3 2 +#define ADC_CSENSE4 3 +#define ADC_MAX 4 + +/* synchronize with sensor.c */ +#define S_CAP1 0 +#define S_CAP2 1 +#define S_CAP3 2 +#define S_CAP4 3 +#define S_CAP5 4 +#define S_CAP6 5 +#define S_CAP7 6 +#define S_CAP8 7 +#define S_RESERVED1 8 +#define S_RESERVED2 9 +#define S_RESERVED3 10 +#define S_RESERVED4 11 +#define S_RESERVED5 12 +#define S_RESERVED6 13 +#define S_RESERVED7 14 +#define S_RESERVED8 15 +#define SENSOR_MAX 16 + +void sensor_init(void); + +/* get filtered values for adc */ +int16_t sensor_get_adc(uint8_t i); + +/* get filtered values of boolean sensors */ +uint16_t sensor_get_all(void); +uint8_t sensor_get(uint8_t i); diff --git a/projects/microb2009/sensorboard/spi_config.h b/projects/microb2009/sensorboard/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/microb2009/sensorboard/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/microb2009/sensorboard/time_config.h b/projects/microb2009/sensorboard/time_config.h new file mode 100755 index 0000000..e0f7f2a --- /dev/null +++ b/projects/microb2009/sensorboard/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 25000l diff --git a/projects/microb2009/sensorboard/timer_config.h b/projects/microb2009/sensorboard/timer_config.h new file mode 100755 index 0000000..810525c --- /dev/null +++ b/projects/microb2009/sensorboard/timer_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1 2009-03-29 18:44:54 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 diff --git a/projects/microb2009/sensorboard/uart_config.h b/projects/microb2009/sensorboard/uart_config.h new file mode 100644 index 0000000..2a27e07 --- /dev/null +++ b/projects/microb2009/sensorboard/uart_config.h @@ -0,0 +1,102 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.3 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART1 definitions + */ + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 64 +#define UART1_TX_FIFO_SIZE 64 +#define UART1_NBITS 8 + +#define UART1_PARITY UART_PARTITY_NONE + +#define UART1_STOP_BIT UART_STOP_BITS_1 + + +/* + * UART3 definitions + */ + +/* compile uart3 fonctions, undefine it to pass compilation */ +#define UART3_COMPILE + +/* enable uart3 if == 1, disable if == 0 */ +#define UART3_ENABLED 1 + +/* enable uart3 interrupts if == 1, disable if == 0 */ +#define UART3_INTERRUPT_ENABLED 1 + +#define UART3_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART3_USE_DOUBLE_SPEED 1 +//#define UART3_USE_DOUBLE_SPEED 1 + +#define UART3_RX_FIFO_SIZE 64 +#define UART3_TX_FIFO_SIZE 64 +//#define UART3_NBITS 5 +//#define UART3_NBITS 6 +//#define UART3_NBITS 7 +#define UART3_NBITS 8 +//#define UART3_NBITS 9 + +#define UART3_PARITY UART_PARTITY_NONE +//#define UART3_PARITY UART_PARTITY_ODD +//#define UART3_PARITY UART_PARTITY_EVEN + +#define UART3_STOP_BIT UART_STOP_BITS_1 +//#define UART3_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/projects/microb2009/tests/CVS/Entries b/projects/microb2009/tests/CVS/Entries new file mode 100644 index 0000000..6c0fba3 --- /dev/null +++ b/projects/microb2009/tests/CVS/Entries @@ -0,0 +1,6 @@ +D/arm_test//// +D/atm2560//// +D/bootloader//// +D/encoders_at90s2313//// +D/oa//// +D/spi_test//// diff --git a/projects/microb2009/tests/CVS/Repository b/projects/microb2009/tests/CVS/Repository new file mode 100644 index 0000000..fd97f84 --- /dev/null +++ b/projects/microb2009/tests/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests diff --git a/projects/microb2009/tests/CVS/Root b/projects/microb2009/tests/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/CVS/Template b/projects/microb2009/tests/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/arm_test/.config b/projects/microb2009/tests/arm_test/.config new file mode 100755 index 0000000..642a479 --- /dev/null +++ b/projects/microb2009/tests/arm_test/.config @@ -0,0 +1,273 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +# CONFIG_STANDARD_PRINTF is not set +CONFIG_ADVANCED_PRINTF=y +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +CONFIG_MODULE_TIME=y +CONFIG_MODULE_TIME_CREATE_CONFIG=y +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +CONFIG_MODULE_I2C=y +CONFIG_MODULE_I2C_MASTER=y +# CONFIG_MODULE_I2C_MULTIMASTER is not set +CONFIG_MODULE_I2C_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +CONFIG_MODULE_PWM_NG=y +CONFIG_MODULE_ADC=y +CONFIG_MODULE_ADC_CREATE_CONFIG=y + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +CONFIG_MODULE_AX12=y +CONFIG_MODULE_AX12_CREATE_CONFIG=y + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +CONFIG_MODULE_ENCODERS_MICROB=y +CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG=y +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y + +# +# Filters +# +CONFIG_MODULE_PID=y +CONFIG_MODULE_PID_CREATE_CONFIG=y +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/microb2009/tests/arm_test/CVS/Entries b/projects/microb2009/tests/arm_test/CVS/Entries new file mode 100644 index 0000000..35c677b --- /dev/null +++ b/projects/microb2009/tests/arm_test/CVS/Entries @@ -0,0 +1,22 @@ +/.config/1.7/Sun Mar 15 20:08:51 2009// +/Makefile/1.3/Sat Jan 3 16:19:30 2009// +/adc_config.h/1.1/Fri Dec 26 13:08:29 2008// +/arm_xy.c/1.1/Sun Mar 15 20:08:51 2009// +/arm_xy.h/1.1/Sun Mar 15 20:08:51 2009// +/ax12_config.h/1.1/Fri Dec 26 13:08:29 2008// +/commands.c/1.6/Sun Mar 15 20:08:51 2009// +/encoders_microb_config.h/1.1/Fri Dec 26 13:08:29 2008// +/error_config.h/1.1/Fri Dec 26 13:08:29 2008// +/i2c_config.h/1.1/Fri Jan 30 20:38:49 2009// +/i2c_protocol.c/1.1/Fri Jan 30 20:38:49 2009// +/main.c/1.6/Sun Mar 15 20:08:51 2009// +/main.h/1.3/Sun Mar 15 20:08:51 2009// +/pid_config.h/1.1/Fri Dec 26 13:08:29 2008// +/pwm_config.h/1.2/Fri Jan 23 23:10:25 2009// +/rdline_config.h/1.1/Fri Dec 26 13:08:29 2008// +/scheduler_config.h/1.1/Fri Dec 26 13:08:29 2008// +/spi_config.h/1.1/Fri Feb 20 21:10:01 2009// +/time_config.h/1.2/Sun Mar 15 20:08:51 2009// +/timer_config.h/1.1/Fri Dec 26 13:08:29 2008// +/uart_config.h/1.2/Sat Jan 3 16:19:30 2009// +D diff --git a/projects/microb2009/tests/arm_test/CVS/Repository b/projects/microb2009/tests/arm_test/CVS/Repository new file mode 100644 index 0000000..d001c3b --- /dev/null +++ b/projects/microb2009/tests/arm_test/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests/arm_test diff --git a/projects/microb2009/tests/arm_test/CVS/Root b/projects/microb2009/tests/arm_test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/arm_test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/arm_test/CVS/Template b/projects/microb2009/tests/arm_test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/arm_test/Makefile b/projects/microb2009/tests/arm_test/Makefile new file mode 100755 index 0000000..781873c --- /dev/null +++ b/projects/microb2009/tests/arm_test/Makefile @@ -0,0 +1,29 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. +# VALUE, absolute or relative path : example ../.. # + +CFLAGS += -Werror + +# List C source files here. (C dependencies are automatically generated.) +SRC = commands.c $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/tests/arm_test/adc_config.h b/projects/microb2009/tests/arm_test/adc_config.h new file mode 100755 index 0000000..a29d1ac --- /dev/null +++ b/projects/microb2009/tests/arm_test/adc_config.h @@ -0,0 +1,34 @@ +#ifndef _ADC_CONFIG_H_ +#define _ADC_CONFIG_H_ + +/* Uncomment the ADC inputs you want to use */ +/* #define ADC0_USE */ +/* #define ADC1_USE */ +/* #define ADC2_USE */ +/* #define ADC3_USE */ +/* #define ADC4_USE */ +/* #define ADC5_USE */ +/* #define ADC6_USE */ +/* #define ADC7_USE */ + +/* Uncomment the ADC reference you want to use */ +#define ADC_REF_EXT +/* #define ADC_REF_AVCC */ +/* #define ADC_REF_INTERNAL */ + +/* This feature is only available for ATmega48/88/168 */ +#define ADC_POWER_REDUCTION + +/* Frequency (kHz) of the converter - Has to be between 50 and 200 */ +/* -- Not used for now -- */ +#define ADC_FREQUENCY 50 + +/* Filter coefficient: number of loops before a constant converted value */ +/* is almost equal to the result given by adc_get_result(). */ +/* -- Not used for now -- */ +#define ADC_FILTER_COEFF 10 + +/* Enable power consumption reduction */ +#define USE_ADC_SHUTDOWN + +#endif // _ADC_CONFIG_H_ diff --git a/projects/microb2009/tests/arm_test/arm_xy.c b/projects/microb2009/tests/arm_test/arm_xy.c new file mode 100755 index 0000000..205810e --- /dev/null +++ b/projects/microb2009/tests/arm_test/arm_xy.c @@ -0,0 +1,487 @@ +#include <stdio.h> +#include <stdlib.h> +#include <math.h> +#include <stdint.h> +#include <inttypes.h> + +#include <aversive.h> + +#include <aversive/wait.h> + + +#include <uart.h> +#include <i2c.h> +#include <ax12.h> +#include <parse.h> +#include <rdline.h> +#include <pwm_ng.h> +#include <encoders_microb.h> +#include <timer.h> +#include <scheduler.h> +#include <pid.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <adc.h> +#include <spi.h> + +#include "main.h" + +#include "arm_xy.h" + +arm_pts_t mat_angle[DIM_D][DIM_H]; + + + +/* process shoulder + elbow angles from height and distance */ +int8_t cart2angle(int32_t h, int32_t d, double *alpha, double *beta) +{ + double theta, l, phi; + + //l = SquareRootDouble((double)(d*d + h*h)); + l = sqrt((double)(d*d + h*h)); + if (l>2*ARM_L) + return -1; + theta = atan2f((double)h, (double)d); + phi = acosf(l/(2*ARM_L)); + + *alpha = theta+phi; + *beta = -2*phi; + + return 0; +} + + +/* process height and distance from shoulder + elbow angles */ +void angle2cart(double alpha, double beta, int32_t *h, int32_t *d) +{ + double tmp_a; + int32_t tmp_h, tmp_d; + + tmp_h = ARM_L * sin(alpha); + tmp_d = ARM_L * cos(alpha); + + tmp_a = alpha+beta; + *h = tmp_h + ARM_L * sin(tmp_a); + *d = tmp_d + ARM_L * cos(tmp_a); + +} + +void wrist_angle_deg2robot_r(double wrist_deg, + double *wrist_out) +{ + *wrist_out = wrist_deg * 3.41 + 875; +} + + +void wrist_angle_deg2robot_l(double wrist_deg, + double *wrist_out) +{ + *wrist_out = wrist_deg * 3.41 + 40; +} + + +#define ARM_S_OFFSET -16000 +#define ARM_E_OFFSET 660 + +/* convert an angle in radian into a robot-specific unit + * for shoulder and elbow */ +void angle_rad2robot_r(double shoulder_rad, double elbow_rad, + double *shoulder_robot, double *elbow_robot) +{ + *shoulder_robot = -shoulder_rad * 4 * 66 * 512. / (2*M_PI) + ARM_S_OFFSET; + *elbow_robot = elbow_rad * 3.41 * 360. / (2*M_PI) + ARM_E_OFFSET; +} + + +#define ARM_LEFT_S_OFFSET -16000 +#define ARM_LEFT_E_OFFSET 470 + + +/* convert an angle in radian into a robot-specific unit + * for shoulder and elbow for LEFT ARM*/ +void angle_rad2robot_l(double shoulder_rad, double elbow_rad, + double *shoulder_robot, double *elbow_robot) +{ + *shoulder_robot = -shoulder_rad * 4 * 66 * 512. / (2*M_PI) + ARM_LEFT_S_OFFSET; + *elbow_robot = elbow_rad * 3.41 * 360. / (2*M_PI) + ARM_LEFT_E_OFFSET; +} + + + +/* convert a robot-specific unit into an angle in radian + * for shoulder and elbow */ +void angle_robot2rad_r(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad) +{ + *shoulder_rad = -((shoulder_robot - ARM_S_OFFSET)*(2*M_PI))/(4 * 66 * 512.); + *elbow_rad = ((elbow_robot - ARM_E_OFFSET) * (2*M_PI))/(3.41 * 360.); +} + +/* convert a robot-specific unit into an angle in radian + * for shoulder and elbow for LEFT ARM*/ +void angle_robot2rad_l(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad) +{ + *shoulder_rad = -((shoulder_robot - ARM_LEFT_S_OFFSET)*(2*M_PI))/(4 * 66 * 512.); + *elbow_rad = ((elbow_robot - ARM_LEFT_E_OFFSET) * (2*M_PI))/(3.41 * 360.); +} + + +/* generate the angle matrix for each (d,h) position */ +void init_arm_matrix(void) +{ + int8_t d, h, ret; + double a, b; + + for (d = 0; d < DIM_D; d++){ + for (h = 0; h < DIM_H; h++){ + ret = cart2angle((h * DIM_COEF - ARM_H), d * DIM_COEF, &a, &b); + if (ret) { + mat_angle[d][h].p_shoulder = 0; + mat_angle[d][h].p_elbow = 0; + } + else { + angle_rad2robot_r(a, b, &a, &b); + mat_angle[d][h].p_shoulder = a / INT_M_SHOULDER; + mat_angle[d][h].p_elbow = b / INT_M_ELBOW; + } + } + } +} + +void dump_matrix(void) +{ + int8_t d, h; + for (h = 0; h < DIM_H; h++) { + for (d = 0; d < DIM_D; d++) { + printf("%6d %4d ", mat_angle[d][h].p_shoulder*INT_M_SHOULDER, mat_angle[d][h].p_elbow*INT_M_ELBOW); + } + printf("\n"); + } +} + +/* same than cart2angle, but uses a bilinear interpolation */ +int8_t coord2ij(int32_t d, int32_t h, int32_t *d_o, int32_t *h_o) +{ + int8_t i_o, j_o; + + int32_t a00, a10, a11, a01; + uint16_t b00, b10, b11, b01; + + int32_t poids1, poids2; + int32_t atmp1, atmp2, btmp1, btmp2; + + if (d*d + h*h >(ARM_L*2)*(ARM_L*2)) + return -6; + + i_o = d / DIM_COEF; + j_o = (h+ARM_H) / DIM_COEF; + + if (i_o >= DIM_D || j_o >= DIM_H || i_o < 0 || j_o < 0) + return -1; + + a00 = mat_angle[i_o][j_o].p_shoulder * INT_M_SHOULDER; + b00 = mat_angle[i_o][j_o].p_elbow * INT_M_ELBOW; + if (!(a00 || b00)) + return -2; + a10 = mat_angle[i_o+1][j_o].p_shoulder * INT_M_SHOULDER; + b10 = mat_angle[i_o+1][j_o].p_elbow * INT_M_ELBOW; + if (!(a10 || b10)) + return -3; + + a11 = mat_angle[i_o+1][j_o+1].p_shoulder * INT_M_SHOULDER; + b11 = mat_angle[i_o+1][j_o+1].p_elbow * INT_M_ELBOW; + if (!(a11 || b11)) + return -4; + + a01 = mat_angle[i_o][j_o+1].p_shoulder * INT_M_SHOULDER; + b01 = mat_angle[i_o][j_o+1].p_elbow * INT_M_ELBOW; + if (!(a01 || b01)) + return -5; + + poids1 = d - DIM_COEF * i_o; + poids2 = DIM_COEF * (i_o+1) - d; + + atmp1 = (poids1*a10 + poids2*a00)/DIM_COEF; + btmp1 = (poids1*b10 + poids2*b00)/DIM_COEF; + + atmp2 = (poids1*a11 + poids2*a01)/DIM_COEF; + btmp2 = (poids1*b11 + poids2*b01)/DIM_COEF; + + poids1 = (h+ARM_H) - DIM_COEF*j_o; + poids2 = DIM_COEF*(j_o+1) - (h+ARM_H); + + *d_o = (poids1*atmp2 + poids2*atmp1) / DIM_COEF; + *h_o = (poids1*btmp2 + poids2*btmp1) / DIM_COEF; + + return 0; +} + + +int8_t arm_get_coord(int16_t d,int16_t h, int32_t *d_o, int32_t *h_o) +{ + int8_t ret; + double a, b; + + ret = coord2ij(d,h, d_o,h_o); + if (!ret) + return ret; + + ret = cart2angle(h, d, &a, &b); + if (ret<0) + return ret; + + angle_rad2robot_r(a, b, &a, &b); + *d_o = a; + *h_o = b; + return ret; + +} + +void test_arm_pos(void) +{ + int16_t d, h; + int8_t ret; + int32_t as, ae; + + for (d=-300; d<300; d+=25){ + for (h=-300; h<300; h+=25){ + ret = arm_get_coord(d,h, &as, &ae); + if (ret < 0) + as = ae = 0; + printf("%7ld %4ld ", as, ae); + } + printf("\n"); + } +} +/* +#define ARM_PERIOD 50000 + +#define ARM_MAX_DIST 80 +#define ARM_MAX_E 10000 +#define ARM_MAX_S 30000 +*/ + +//100000 us for max shoulder / max elbow +//en us +#define ARM_PERIOD 50000L + +#define ARM_MAX_DIST 40L +// 2331 step/s => +//#define ARM_MAX_E ((2331L*ARM_PERIOD)/1000000L) +/* +// 800step/CS => 160step/ms +#define ARM_MAX_S ((160L*ARM_PERIOD)/1000L) +*/ +// 4000step/CS => 800step/ms +//#define ARM_MAX_S ((800L*ARM_PERIOD)/1000L) + + + +/* TEST TEST XXX */ +#define ARM_MAX_E (((1500L*ARM_PERIOD)/1000000L)) +#define ARM_MAX_S (((1500L*ARM_PERIOD)/1000L)) + + + + +/* return: + 0 => at last pos + >0 => need more step + <0 => unreachable pos +*/ +int8_t arm_do_step(Arm_Pos *arm_pos, + int32_t *arm_h, int32_t *arm_d, int32_t fin_h, int32_t fin_d, + int32_t *as, int32_t *ae, int32_t *aw, + double *as_fin_rad, double *ae_fin_rad, + uint32_t *next_time, + int32_t *s_quad, int32_t *e_quad) +{ + int8_t ret; + int32_t diff_h, diff_d, l; + double as_fin, ae_fin, as_cur, ae_cur, as_cur_rad, ae_cur_rad;//, as_fin_rad, ae_fin_rad; + double as_coef, ae_coef; + int32_t as_diff, ae_diff; + + + diff_h = fin_h-*arm_h; + diff_d = fin_d-*arm_d; + + //printf("1 dh %ld dd %ld\r\n", diff_h, diff_d); + + l = sqrt(diff_h*diff_h + diff_d*diff_d); + + if (l>ARM_MAX_DIST){ + diff_h = diff_h*ARM_MAX_DIST/l; + diff_d = diff_d*ARM_MAX_DIST/l; + } + + //printf("2 l: %ld dh %ld dd %ld\r\n", l, diff_h, diff_d); + + + fin_h = *arm_h+diff_h; + fin_d = *arm_d+diff_d; + + //printf("2 fh %ld fd %ld\r\n", fin_h, fin_d); + + /* calc for current angle */ + ret = cart2angle(*arm_h, *arm_d, &as_cur_rad, &ae_cur_rad); + if (ret) + return ret; + + /* calc for next step */ + ret = cart2angle(fin_h, fin_d, as_fin_rad, ae_fin_rad); + if (ret) + return ret; + + + + //printf("3 as_cur %f ae_cur %f \r\n", as_cur_rad, ae_cur_rad); + //printf("4 as_fin %f ae_fin %f \r\n", *as_fin_rad, *ae_fin_rad); + + + arm_pos->angle_rad2robot(as_cur_rad, ae_cur_rad, + &as_cur, &ae_cur); + arm_pos->angle_rad2robot(*as_fin_rad, *ae_fin_rad, + &as_fin, &ae_fin); + + + //printf("5 as_cur %f ae_cur %f \r\n", as_cur, ae_cur); + //printf("6 as_fin %f ae_fin %f \r\n", as_fin, ae_fin); + + + as_diff = as_fin-as_cur; + ae_diff = ae_fin-ae_cur; + + //printf("7 asdiff %ld aediff %ld \r\n", as_diff, ae_diff); + + + *arm_h = fin_h; + *arm_d = fin_d; + + /* XXX we are at pos, set default speed */ + *s_quad = 800; + *e_quad = 0x3ff; + + if (!as_diff && !ae_diff){ + /* printf("reaching end\r\n"); */ + *as = as_fin; + *ae = ae_fin; + *next_time = 0; + + + return 0; + } + + /* test if one activator is in position */ + if (as_diff == 0){ + //printf("as reached\r\n"); + ae_coef = (double)ARM_MAX_E/(double)ae_diff; + *next_time = ARM_PERIOD*ABS(ae_coef); + + *e_quad = ABS(ae_coef)*ABS(ae_diff); + + *as = as_cur; + *ae = ae_cur+ae_diff; + + + } + else if (ae_diff == 0){ + //printf("ae reached\r\n"); + as_coef = (double)ARM_MAX_S/(double)as_diff; + *next_time = ARM_PERIOD/ABS(as_coef); + + + *s_quad = ABS(as_coef)*ABS(as_diff); + + *as = as_cur+as_diff; + *ae = ae_cur; + } + + else{ + as_coef = (double)ARM_MAX_S/(double)as_diff; + ae_coef = (double)ARM_MAX_E/(double)ae_diff; + + //printf("asc %f aec %f\r\n", as_coef, ae_coef); + + *as = as_cur+as_diff; + *ae = ae_cur+ae_diff; + + + if (ABS(as_coef)>=ABS(ae_coef)){ + /* elbow is limitating */ + + //printf("e limit %ld %ld \r\n", as_diff, ae_diff); + + *next_time = ARM_PERIOD/ABS(ae_coef); + //*next_time = ARM_PERIOD*ae_diff/ARM_MAX_E; + + + *s_quad = ABS(ae_coef)*ABS(as_diff); + *e_quad = ABS(ae_coef)*ABS(ae_diff); + + + } + else{ + /* shoulder is limitating */ + + //printf("s limit %ld %ld \r\n", as_diff, ae_diff); + + *next_time = ARM_PERIOD/ABS(as_coef); + + *s_quad = ABS(as_coef)*ABS(as_diff); + *e_quad = ABS(as_coef)*ABS(ae_diff); + + + } + } + + *s_quad = (*s_quad*CS_PERIOD)/ARM_PERIOD; + *e_quad = (0x3ff*(*e_quad))/ARM_MAX_E; + + //printf("max e %ld\r\n", *e_quad); + /*avoid limits*/ + if (!*s_quad) + *s_quad = 1; + if (!*e_quad) + *e_quad = 1; + + + //printf("8 sq %ld eq %ld \r\n", *s_quad, *e_quad); + + return 1; + +} + + +#if 0 + +int main(void) +{ + double a, b; + int8_t ret; + int32_t as, ae; + ret = cart2angle(100, 100, &a, &b); + printf("ret %d %f %f\n", ret, a*180/M_PI, b*180/M_PI); + + init_arm_matrix(); + dump_matrix(); + + + int32_t px = 100; + int32_t py = -230; + ret = coord2ij(px,py, &as, &ae); + printf("ret %d %ld %ld\n", ret, as, ae); + + + ret = cart2angle(py, px, &a, &b); + printf("ret %d %f %f\n", ret, a*180/M_PI, b*180/M_PI); + + ret = arm_get_coord(px,py, &as, &ae); + printf("ret %d %ld %ld\n", ret, as, ae); + + test_arm_pos(); + return 0; +} +#endif diff --git a/projects/microb2009/tests/arm_test/arm_xy.h b/projects/microb2009/tests/arm_test/arm_xy.h new file mode 100644 index 0000000..3e0e215 --- /dev/null +++ b/projects/microb2009/tests/arm_test/arm_xy.h @@ -0,0 +1,142 @@ +#include <stdio.h> +#include <stdlib.h> +#include <math.h> +#include <stdint.h> +#include <inttypes.h> + +#include <aversive.h> + +#define ARM_L 130UL +#define ARM_H 250UL + +#define DIM_COEF 50 +#define DIM_D 6 /* distance */ +#define DIM_H 10 /* height */ + +/* coefs to fit in a integer */ +#define INT_M_SHOULDER 3 +#define INT_M_ELBOW 3 + +#define sqrtf sqrt +#define acosf acos +#define atan2f atan2 + +typedef struct arm_pts +{ + int16_t p_shoulder; + uint8_t p_elbow; +} arm_pts_t; + + +typedef struct arm_pos{ + int32_t h; + int32_t d; + int32_t w; + + int32_t goal_h; + int32_t goal_d; + int32_t goal_w; + + + volatile int8_t state; + + void (*wrist_angle_deg2robot)(double wrist_edg, + double *wrist_out); + + void (*angle_rad2robot)(double shoulder_deg, double elbow_deg, + double *shoulder_out, double *elbow_out); + + void (*angle_robot2rad)(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad); + + int8_t ELBOW_AX12; + int8_t WRIST_AX12; + + +}Arm_Pos; + + + +/* process shoulder + elbow angles from height and distance */ +int8_t cart2angle(int32_t h, int32_t d, double *alpha, double *beta); + +/* process height and distance from shoulder + elbow angles */ +void angle2cart(double alpha, double beta, int32_t *h, int32_t *d); + +void wrist_angle_deg2robot_r(double wrist_edg, + double *wrist_out); + +void wrist_angle_deg2robot_l(double wrist_edg, + double *wrist_out); + +/* convert an angle in degree into a robot-specific unit + * for shoulder and elbow */ +void angle_rad2robot_r(double shoulder_deg, double elbow_deg, + double *shoulder_out, double *elbow_out); + +void angle_rad2robot_l(double shoulder_deg, double elbow_deg, + double *shoulder_out, double *elbow_out); + + +/* convert a robot-specific unit into an angle in radian + * for shoulder and elbow */ +void angle_robot2rad_r(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad); +void angle_robot2rad_l(double shoulder_robot, double elbow_robot, + double *shoulder_rad, double *elbow_rad); + + +/* generate the angle matrix for each (d,h) position */ +void init_arm_matrix(void); +void dump_matrix(void); + +/* same than cart2angle, but uses a bilinear interpolation */ +int8_t coord2ij(int32_t d, int32_t h, int32_t *d_o, int32_t *h_o); + +int8_t arm_get_coord(int16_t d,int16_t h, int32_t *d_o, int32_t *h_o); + +void test_arm_pos(void); + +/* +int8_t arm_do_step(int32_t *arm_h, int32_t *arm_d, int32_t fin_h, int32_t fin_d, + int32_t *as, int32_t *ae, uint32_t *next_time, + int32_t *s_quad); +*/ + +int8_t arm_do_step(Arm_Pos *arm_pos, + int32_t *arm_h, int32_t *arm_d, int32_t fin_h, int32_t fin_d, + int32_t *as, int32_t *ae, int32_t *aw, + double *as_fin_rad, double *ae_fin_rad, + uint32_t *next_time, + int32_t *s_quad, int32_t *e_quad); + +#if 0 + +int main(void) +{ + double a, b; + int8_t ret; + int32_t as, ae; + ret = cart2angle(100, 100, &a, &b); + printf("ret %d %f %f\n", ret, a*180/M_PI, b*180/M_PI); + + init_arm_matrix(); + dump_matrix(); + + + int32_t px = 100; + int32_t py = -230; + ret = coord2ij(px,py, &as, &ae); + printf("ret %d %ld %ld\n", ret, as, ae); + + + ret = cart2angle(py, px, &a, &b); + printf("ret %d %f %f\n", ret, a*180/M_PI, b*180/M_PI); + + ret = arm_get_coord(px,py, &as, &ae); + printf("ret %d %ld %ld\n", ret, as, ae); + + test_arm_pos(); + return 0; +} +#endif diff --git a/projects/microb2009/tests/arm_test/ax12_config.h b/projects/microb2009/tests/arm_test/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/projects/microb2009/tests/arm_test/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/projects/microb2009/tests/arm_test/commands.c b/projects/microb2009/tests/arm_test/commands.c new file mode 100755 index 0000000..61a06bd --- /dev/null +++ b/projects/microb2009/tests/arm_test/commands.c @@ -0,0 +1,2189 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.6 2009-03-15 20:08:51 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <i2c.h> +#include <ax12.h> +#include <parse.h> +#include <parse_num.h> +#include <parse_string.h> +#include <uart.h> +#include <encoders_microb.h> +#include <pwm_ng.h> +#include <pid.h> +#include <spi.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> + +#include <scheduler.h> + +#include "main.h" + +#include "arm_xy.h" + +extern AX12 ax12; + +#define AX12_MAX_RETRY 2 + +uint8_t AX12_read_int_retry(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t *val) +{ + int8_t err, i; + for (i=0;i<AX12_MAX_RETRY;i++){ + err = AX12_read_int(ax12, id, address, val); + if (!err) + return err; + } + + printf("AX12: retry %d times err: %d\r\n", AX12_MAX_RETRY, err); + return err; +} + +uint8_t AX12_write_int_retry(AX12 *ax12, uint8_t id, AX12_ADDRESS address, + uint16_t data) +{ + int8_t err, i; + for (i=0;i<AX12_MAX_RETRY;i++){ + err = AX12_write_int(ax12, id, address,data); + if (!err) + return err; + } + + printf("AX12: retry %d times err: %d\r\n", AX12_MAX_RETRY, err); + return err; +} + +uint8_t addr_from_string(const char *s) +{ + /* 16 bits */ + if (!strcmp_P(s, PSTR("cw_angle_limit"))) + return AA_CW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("ccw_angle_limit"))) + return AA_CCW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("max_torque"))) + return AA_MAX_TORQUE_L; + if (!strcmp_P(s, PSTR("down_calibration"))) + return AA_DOWN_CALIBRATION_L; + if (!strcmp_P(s, PSTR("up_calibration"))) + return AA_UP_CALIBRATION_L; + if (!strcmp_P(s, PSTR("torque_limit"))) + return AA_TORQUE_LIMIT_L; + if (!strcmp_P(s, PSTR("position"))) + return AA_PRESENT_POSITION_L; + if (!strcmp_P(s, PSTR("speed"))) + return AA_PRESENT_SPEED_L; + if (!strcmp_P(s, PSTR("load"))) + return AA_PRESENT_LOAD_L; + if (!strcmp_P(s, PSTR("moving_speed"))) + return AA_MOVING_SPEED_L; + if (!strcmp_P(s, PSTR("model"))) + return AA_MODEL_NUMBER_L; + if (!strcmp_P(s, PSTR("goal_pos"))) + return AA_GOAL_POSITION_L; + if (!strcmp_P(s, PSTR("punch"))) + return AA_PUNCH_L; + + /* 8 bits */ + if (!strcmp_P(s, PSTR("firmware"))) + return AA_FIRMWARE; + if (!strcmp_P(s, PSTR("id"))) + return AA_ID; + if (!strcmp_P(s, PSTR("baudrate"))) + return AA_BAUD_RATE; + if (!strcmp_P(s, PSTR("delay"))) + return AA_DELAY_TIME; + if (!strcmp_P(s, PSTR("high_lim_temp"))) + return AA_HIGHEST_LIMIT_TEMP; + if (!strcmp_P(s, PSTR("low_lim_volt"))) + return AA_LOWEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("high_lim_volt"))) + return AA_HIGHEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("status_return"))) + return AA_STATUS_RETURN_LEVEL; + if (!strcmp_P(s, PSTR("alarm_led"))) + return AA_ALARM_LED; + if (!strcmp_P(s, PSTR("alarm_shutdown"))) + return AA_ALARM_SHUTDOWN; + if (!strcmp_P(s, PSTR("torque_enable"))) + return AA_TORQUE_ENABLE; + if (!strcmp_P(s, PSTR("led"))) + return AA_LED; + if (!strcmp_P(s, PSTR("cw_comp_margin"))) + return AA_CW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("ccw_comp_margin"))) + return AA_CCW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("cw_comp_slope"))) + return AA_CW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("ccw_comp_slope"))) + return AA_CCW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("voltage"))) + return AA_PRESENT_VOLTAGE; + if (!strcmp_P(s, PSTR("temp"))) + return AA_PRESENT_TEMP; + if (!strcmp_P(s, PSTR("reginst"))) + return AA_PRESENT_REGINST; + if (!strcmp_P(s, PSTR("moving"))) + return AA_MOVING; + if (!strcmp_P(s, PSTR("lock"))) + return AA_LOCK; + + return 0; +} + + + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(void * parsed_result, void * data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Spi_Test */ + +/* this structure is filled when cmd_spi_test is parsed successfully */ +struct cmd_spi_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_spi_test is parsed successfully */ +static void cmd_spi_test_parsed(void * parsed_result, void * data) +{ +#if 0 + uint8_t i, ret; + + for (i=0; i<3; i++) { + spi_slave_select(0); + ret = spi_send_and_receive_byte(i); + spi_slave_deselect(0); + printf_P(PSTR("Sent %d, received %d\r\n"), i, ret); + } +#else + printf_P(PSTR("disabled\r\n")); +#endif +} + +prog_char str_spi_test_arg0[] = "spi_test"; +parse_pgm_token_string_t cmd_spi_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_spi_test_result, arg0, str_spi_test_arg0); + +prog_char help_spi_test[] = "Test the SPI"; +parse_pgm_inst_t cmd_spi_test = { + .f = cmd_spi_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_spi_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_spi_test_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Bootloader */ + +/* this structure is filled when cmd_bootloader is parsed successfully */ +struct cmd_bootloader_result { + fixed_string_t arg0; +}; + +/* function called when cmd_bootloader is parsed successfully */ +static void cmd_bootloader_parsed(void * parsed_result, void * data) +{ +#ifdef __AVR_ATmega128__ +#define BOOTLOADER_ADDR 0x1e000 +#else +#define BOOTLOADER_ADDR 0x3f000 +#endif + if (pgm_read_byte_far(BOOTLOADER_ADDR) == 0xff) { + printf_P(PSTR("Bootloader is not present\r\n")); + return; + } + cli(); + /* ... very specific :( */ +#ifdef __AVR_ATmega128__ + TIMSK = 0; + ETIMSK = 0; +#else + /* XXX */ +#endif + EIMSK = 0; + UCSR0B = 0; + UCSR1B = 0; + SPCR = 0; + TWCR = 0; + ACSR = 0; + ADCSRA = 0; + +#ifdef __AVR_ATmega128__ + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("ldi r31,0xf0\n"); + __asm__ __volatile__ ("ijmp\n"); +#else + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("ldi r31,0xf8\n"); + __asm__ __volatile__ ("ldi eind,0x01\n"); + __asm__ __volatile__ ("eijmp\n"); +#endif +} + +prog_char str_bootloader_arg0[] = "bootloader"; +parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0); + +prog_char help_bootloader[] = "Bootloader the board"; +parse_pgm_inst_t cmd_bootloader = { + .f = cmd_bootloader_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_bootloader, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_bootloader_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Ax12_Stress */ + +/* this structure is filled when cmd_ax12_stress is parsed successfully */ +struct cmd_ax12_stress_result { + fixed_string_t arg0; + uint8_t id; + uint32_t num; + +}; + +/* function called when cmd_ax12_stress is parsed successfully */ +static void cmd_ax12_stress_parsed(void * parsed_result, void * data) +{ + uint32_t i, nb_errs = 0; + uint8_t val; + microseconds t = time_get_us2(); + struct cmd_ax12_stress_result *res = parsed_result; + + for (i=0; i<res->num; i++) { + if (AX12_read_byte(&ax12, res->id, AA_ID, &val) != 0) + nb_errs ++; + if (uart_recv_nowait(0) != -1) + break; + + } + + printf_P(PSTR("%ld errors / %ld\r\n"), nb_errs, i); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %ld ms\r\n"), t); +} + +prog_char str_ax12_stress_arg0[] = "ax12_stress"; +parse_pgm_token_string_t cmd_ax12_stress_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_ax12_stress_result, arg0, str_ax12_stress_arg0); +parse_pgm_token_num_t cmd_ax12_stress_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_ax12_stress_result, id, UINT8); +parse_pgm_token_num_t cmd_ax12_stress_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_ax12_stress_result, num, UINT32); + +prog_char help_ax12_stress[] = "Ax12_Stress the board"; +parse_pgm_inst_t cmd_ax12_stress = { + .f = cmd_ax12_stress_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_ax12_stress, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_ax12_stress_arg0, + (prog_void *)&cmd_ax12_stress_arg1, + (prog_void *)&cmd_ax12_stress_arg2, + NULL, + }, +}; + + +/**********************************************************/ +/* Test */ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_test_result { + fixed_string_t arg0; + uint16_t arg1; + uint16_t arg2; +}; + +#define R_ELBOW_AX12 1 +#define R_WRIST_AX12 2 + +#define L_ELBOW_AX12 4 +#define L_WRIST_AX12 3 + + +#define FINGER_AX12 5 + + +void arm_l_goto(int32_t shoulder, uint16_t elbow, uint16_t wrist) +{ + uint8_t err; + + //printf("%ld %d %d\r\n", shoulder, elbow, wrist); + //wait_ms(1); + //cs_set_consign(&arm.cs_mot, shoulder); + err = AX12_write_int(&ax12, L_ELBOW_AX12, AA_GOAL_POSITION_L, elbow); + if (!err) + err = AX12_write_int(&ax12, L_WRIST_AX12, AA_GOAL_POSITION_L, wrist); + if (err) + printf_P(PSTR("AX12 error %x !\r\n"), err); +} + + +void arm_goto(Arm_Pos * arm_pos, int32_t shoulder, uint16_t elbow, uint16_t wrist) +{ + uint8_t err; + + //printf("%ld %d %d\r\n", shoulder, elbow, wrist); + //wait_ms(1); + cs_set_consign(&arm.cs_mot, shoulder); + err = AX12_write_int(&ax12, arm_pos->ELBOW_AX12, AA_GOAL_POSITION_L, elbow); + if (!err) + err = AX12_write_int(&ax12, arm_pos->WRIST_AX12, AA_GOAL_POSITION_L, wrist); + if (err) + printf_P(PSTR("AX12 error %x !\r\n"), err); +} + +void arm_goto_dh(Arm_Pos* arm_pos, int32_t shoulder, uint16_t elbow) +{ + uint8_t err; + cs_set_consign(&arm.cs_mot, shoulder); + err = AX12_write_int(&ax12, arm_pos->ELBOW_AX12, AA_GOAL_POSITION_L, elbow); + if (err) + printf_P(PSTR("AX12 error %x !\r\n"), err); +} + +void finger_right(void) +{ + AX12_write_int(&ax12, FINGER_AX12, AA_GOAL_POSITION_L, 666); +} + +void finger_left(void) +{ + AX12_write_int(&ax12, FINGER_AX12, AA_GOAL_POSITION_L, 340); +} + +void finger_center(void) +{ + AX12_write_int(&ax12, FINGER_AX12, AA_GOAL_POSITION_L, 490); +} + +/* +#define arm_take_high_v1() arm_goto(-18700, 204, 455) +#define arm_take_low_v1() arm_goto(-11000, 273, 480) +#define arm_take_high_v2() arm_goto(-18700, 204, 154) +#define arm_take_low_v2() arm_goto(-11000, 273, 139) +#define arm_intermediate() arm_goto(-35700, 297, 385) +#define arm_drop_v2() arm_goto(-16810, 667, 564) +#define arm_drop_v1() arm_goto(-16810, 667, 904) +*/ + +#define arm_take_high_v1() arm_goto(-11533, 295, 477) +#define arm_take_low_v1() arm_goto(-9835 , 311, 470) +#define arm_take_high_v2() arm_goto(-11553, 295, 126) +#define arm_take_low_v2() arm_goto(-9835, 311, 118) +#define arm_intermediate() arm_goto(-25753, 299, 252) +#define arm_drop_v2() arm_goto(-2427, 656, 396) +#define arm_drop_v1() arm_goto(-11280, 547, 699) + +#define arm_drop_v3() arm_goto(-11280, 547, 396) +//#define arm_drop_v4() arm_goto(-11000, 656, 699) + + + +#define ARM_INTER_WAIT +/* function called when cmd_test is parsed successfully */ +static void cmd_test_parsed(void * parsed_result, void * data) +{ +#if 0 + uint8_t i=0; + struct cmd_test_result *res = parsed_result; + uint16_t t_w = res->arg1; + int16_t ppwm = res->arg2; + + AX12_write_int(&ax12, ELBOW_AX12, AA_MOVING_SPEED_L, 1000); +/* int8_t err; */ + + /* Set some AX12 parameters */ +/* err = AX12_write_int(&ax12,0xFE,AA_TORQUE_ENABLE,0x1); */ +/* if (!err) */ +/* AX12_write_int(&ax12,0xFE,AA_PUNCH_L,0x20); */ +/* if (!err) */ +/* AX12_write_int(&ax12,0xFE,AA_TORQUE_LIMIT_L,0x3FF); */ +/* if (!err) */ +/* AX12_write_int(&ax12,0xFE,AA_MOVING_SPEED_L,0x3FF); */ +/* if (!err) */ +/* AX12_write_byte(&ax12,0xFE,AA_ALARM_LED,0xEF); */ +/* if (err) { */ +/* printf_P(PSTR("AX12 error %x !\r\n"), err); */ +/* return; */ +/* } */ + + for (i=0; i<1; i++) { + arm_take_high_v1(); + wait_ms(t_w); + pwm_ng_set(&arm.pwm1B, ppwm); + arm_take_low_v1(); + wait_ms(t_w); + arm_take_high_v1(); + wait_ms(t_w); + + + arm_take_high_v2(); + wait_ms(t_w); + pwm_ng_set(&arm.pwm3C, ppwm); + arm_take_low_v2(); + wait_ms(t_w); + arm_take_high_v2(); + wait_ms(t_w); + + + arm_intermediate(); + wait_ms(t_w); +/* arm_intermediate2(); */ +/* wait_ms(250); */ + arm_drop_v2(); + wait_ms(t_w); + pwm_ng_set(&arm.pwm3C, -ppwm); + wait_ms(50); + pwm_ng_set(&arm.pwm3C, 0); + + arm_drop_v3(); + wait_ms(t_w); + //arm_drop_v4(); + //wait_ms(t_w); + arm_drop_v1(); + wait_ms(t_w); + pwm_ng_set(&arm.pwm1B, -ppwm); + wait_ms(50); + pwm_ng_set(&arm.pwm1B, 0); + + arm_intermediate(); + wait_ms(t_w); + } +#endif +} + +prog_char str_test_arg0[] = "test"; +parse_pgm_token_string_t cmd_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_test_result, arg0, str_test_arg0); +parse_pgm_token_num_t cmd_test_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_test_result, arg1, UINT16); +parse_pgm_token_num_t cmd_test_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_test_result, arg2, UINT16); + +prog_char help_test[] = "Test func timewait pump_pwm"; +parse_pgm_inst_t cmd_test = { + .f = cmd_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_test_arg0, + (prog_void *)&cmd_test_arg1, + (prog_void *)&cmd_test_arg2, + NULL, + }, +}; + + +/**********************************************************/ +/* armxy */ + +/* this structure is filled when cmd_armxy is parsed successfully */ +struct cmd_armxy_result { + fixed_string_t arg0; + int16_t arg1; + int16_t arg2; + int16_t arg3; +}; + + + +Arm_Pos arm_pos_r; +Arm_Pos arm_pos_l; + +#define ARM_STATE_MOV 1 +#define ARM_STATE_IN_POS 2 + + + +/* +int32_t arm_h = 0; +int32_t arm_d = 260; +int32_t arm_w = 110; +*/ + +int8_t arm_do_xy_sched_update(Arm_Pos *arm_pos) +{ + + int8_t ret; + int32_t fin_h, fin_d; + int32_t as; + int32_t ae; + int32_t aw; + int32_t s_quad; + int32_t e_quad; + + uint32_t next_time; + double as_fin_rad, ae_fin_rad; + int32_t as_deg, ae_deg; + //double wrist_out; + + //printf("upt called\r\n"); + fin_h = arm_pos->goal_h; + fin_d = arm_pos->goal_d; + + arm_pos->state = ARM_STATE_MOV; + + //quadramp_set_1st_order_vars(&arm.qr_mot, 800, 800); /* set speed */ + + + + + + + + ret = arm_do_step(arm_pos, &arm_pos->h, &arm_pos->d, + fin_h, fin_d, + &as, &ae, &aw, + &as_fin_rad, &ae_fin_rad, + &next_time, &s_quad, &e_quad); + //printf("ret: %d\r\n", ret); + /* + printf("do_step: %d arm_h %ld arm_d: %ld as: %ld ae:%ld\r\n", + ret, + arm_pos->h, arm_pos->d, + as, ae); + printf("asdeg %f aedeg %f nextt:%ld squad: %ld equad: %ld\r\n", + ((as_fin_rad*180)/M_PI), ((ae_fin_rad*180)/M_PI), + next_time, + s_quad, e_quad); + */ + + //printf("ret: %d time: %ld\r\n", ret, next_time); + as_deg = (as_fin_rad*180.)/M_PI; + ae_deg = (ae_fin_rad*180.)/M_PI; + + + aw = -arm_pos->goal_w+as_deg+ae_deg; + + /* printf("as_deg: %ld ae_deg: %ld aw deg: %ld\r\n", as_deg, ae_deg, aw); */ + /* + wrist_angle_deg2robot(arm_pos->goal_w, + &wrist_out); + */ + + /* printf("w_out: %f\r\n", wrist_out); */ + + if (ret<0) + return arm_pos->state = ret; // XXX + + + quadramp_set_1st_order_vars(&arm.qr_mot, s_quad, s_quad); /* set speed */ + AX12_write_int(&ax12, arm_pos->ELBOW_AX12, AA_MOVING_SPEED_L, e_quad); + + + + arm_goto_dh(arm_pos, as, ae); + + //wait_ms(next_time/1000); + + if (ret == 0){ + //printf("set arm end\r\n"); + arm_pos->state = ARM_STATE_IN_POS; + return 0; + } + + if (next_time<SCHEDULER_UNIT) + next_time = SCHEDULER_UNIT; + + ret = scheduler_add_single_event_priority((void *)arm_do_xy_sched_update, + arm_pos, + next_time/SCHEDULER_UNIT, + 50); + + + //printf("add event %ld\r\n", next_time/SCHEDULER_UNIT ); + + + + return 0; + +} + + + +/* +#define SPEED_NEAR_STOP 15 +#define CS_NEAR_STEP 50 +*/ + +#define ARM_NEAR_POS 8 +#define ARM_NEAR_SPEED0 100 + +#define CS_NEAR_POS 100 + + + + +#define ARM_MAX_AX12_SS 1000 + + +#define MOV_MAX_TIMEOUT 100L + + + +int8_t arm_do_xy_nowait(Arm_Pos *arm_pos, int16_t armh, int16_t armd, int16_t w_angle, int32_t *wrist_wait_time) +{ + int8_t ret; + + + double as_fin_rad, ae_fin_rad, wrist_out; + int32_t as_deg, ae_deg, aw_deg; + uint16_t wrist_cur; + int32_t wrist_diff; + + + arm_pos->goal_h = armh; + arm_pos->goal_d = armd; + arm_pos->goal_w = w_angle; + + arm_pos->state = ARM_STATE_MOV; + + if (wrist_wait_time) + *wrist_wait_time = 0; + + /* calc for final pos */ + ret = cart2angle(armh, armd, &as_fin_rad, &ae_fin_rad); + if (ret) + return ret; + + + + /*give directly final wrist pos*/ + //AX12_write_int(&ax12, WRIST_AX12, AA_MOVING_SPEED_L, 0x3ff); + + as_deg = (as_fin_rad*180.)/M_PI; + ae_deg = (ae_fin_rad*180.)/M_PI; + aw_deg = -arm_pos->goal_w+as_deg+ae_deg; + arm_pos->wrist_angle_deg2robot(aw_deg, + &wrist_out); + /* calc theorical wrist movement duration */ + ret = AX12_read_int(&ax12, arm_pos->WRIST_AX12, AA_PRESENT_POSITION_L, &wrist_cur); + + wrist_diff = wrist_out-wrist_cur; + + + if (ret) + printf_P(PSTR("AX12 read pos wrist error %x !\r\n"), ret); + else{ + if (wrist_diff && wrist_wait_time) + *wrist_wait_time = (1000*ABS((int32_t)wrist_diff))/ARM_MAX_AX12_SS; + } + + ret = AX12_write_int(&ax12, arm_pos->WRIST_AX12, AA_GOAL_POSITION_L, wrist_out); + if (ret) + printf_P(PSTR("AX12 wrist final pos error %x !\r\n"), ret); + + arm_do_xy_sched_update(arm_pos); + + while(arm_pos->state == ARM_STATE_MOV){ + } + + if (arm_pos->state != ARM_STATE_IN_POS) + printf("error wait no speed ret: %d\r\n", arm_pos->state); + return ret; + + +} + +int8_t arm_do_xy_wait_nospeed(Arm_Pos *arm_pos, int16_t armh, int16_t armd, int16_t w_angle) +{ + int8_t ret; + int16_t spd1, spd2; + int16_t val1, val2; + int16_t valp1, valp2; + int32_t cs_err; + + microseconds t1,t2 ; + + int32_t wrist_wait_time; + + + ret = arm_do_xy_nowait(arm_pos, armh, armd, w_angle, &wrist_wait_time); + + //printf("wwt %ld\r\n", wrist_wait_time); + + //ret = arm_do_xy(arm_pos, armh, armd, w_angle); + //ret = arm_do_xy_sched(arm_pos, armh, armd, w_angle); + + t1 = time_get_us2(); + while (1){ + AX12_read_int(&ax12, arm_pos->ELBOW_AX12, AA_PRESENT_SPEED_L, (uint16_t*)&spd1); + AX12_read_int(&ax12, arm_pos->WRIST_AX12, AA_PRESENT_SPEED_L, (uint16_t*)&spd2); + + AX12_read_int(&ax12, arm_pos->ELBOW_AX12, AA_GOAL_POSITION_L, (uint16_t*)&val1); + AX12_read_int(&ax12, arm_pos->WRIST_AX12, AA_GOAL_POSITION_L, (uint16_t*)&val2); + + AX12_read_int(&ax12, arm_pos->ELBOW_AX12, AA_PRESENT_POSITION_L, (uint16_t*)&valp1); + AX12_read_int(&ax12, arm_pos->WRIST_AX12, AA_PRESENT_POSITION_L, (uint16_t*)&valp2); + + + val1-=valp1; + val2-=valp2; + + + cs_err = cs_get_error(&arm.cs_mot); + + if (ABS(val1)<ARM_NEAR_POS && ABS(val2)<ARM_NEAR_POS && ABS(cs_err)<CS_NEAR_POS && + ABS(spd1)<ARM_NEAR_SPEED0 && ABS(spd2)<ARM_NEAR_SPEED0) + break; + + t2 = time_get_us2(); + + /* TIME OUT XXX ms */ + if (t2-t1>(MOV_MAX_TIMEOUT+wrist_wait_time)*1000L){ + printf("wait speed timeout: %d %d %ld spd %d %d\r\n", + val1,val2, + ABS(cs_err), + spd1, spd2); + break; + } + + + } + + return ret; +} + + +/* function called when cmd_armxy is parsed successfully */ +static void cmd_armxy_parsed(void * parsed_result, void * data) +{ + struct cmd_armxy_result *res = parsed_result; + int16_t armx = res->arg1; + int16_t army = res->arg2; + int16_t wrist_angle_deg = res->arg3; + Arm_Pos *arm_pos; + + if (!strcmp_P(res->arg0, PSTR("rarmxy"))) + arm_pos = &arm_pos_r; + else + arm_pos = &arm_pos_l; + + + arm_do_xy_wait_nospeed(arm_pos, armx,army, wrist_angle_deg); + + + return ; + + + + + +} + +prog_char str_armxy_arg0[] = "larmxy#rarmxy"; +parse_pgm_token_string_t cmd_armxy_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_armxy_result, arg0, str_armxy_arg0); +parse_pgm_token_num_t cmd_armxy_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_armxy_result, arg1, INT16); +parse_pgm_token_num_t cmd_armxy_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_armxy_result, arg2, INT16); +parse_pgm_token_num_t cmd_armxy_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_armxy_result, arg3, INT16); + +prog_char help_armxy[] = "Armxy x y "; +parse_pgm_inst_t cmd_armxy = { + .f = cmd_armxy_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_armxy, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_armxy_arg0, + (prog_void *)&cmd_armxy_arg1, + (prog_void *)&cmd_armxy_arg2, + (prog_void *)&cmd_armxy_arg3, + NULL, + }, +}; + + + + + +/**********************************************************/ +/* arm_circ */ + +/* this structure is filled when cmd_arm_circ is parsed successfully */ +struct cmd_arm_circ_result { + fixed_string_t arg0; + uint8_t step; +}; + +/* function called when cmd_arm_circ is parsed successfully */ +static void cmd_arm_circ_parsed(void * parsed_result, void * data) +{ +#if 0 + int32_t i; + double a; + struct cmd_arm_circ_result *res = parsed_result; + //int32_t l = 90; + int32_t add_h, add_d; + + add_h = 0; + add_d = 170; + + /* + for (i=0; i<360; i+=res->step) { + a = (double)(i*2*M_PI/360.); + arm_do_xy(&arm_pos_r, add_h+l*sin(a), add_d+l*cos(a) , 10); + + } + */ +#endif +} + +prog_char str_arm_circ_arg0[] = "arm_circ"; +parse_pgm_token_string_t cmd_arm_circ_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_circ_result, arg0, str_arm_circ_arg0); +parse_pgm_token_num_t cmd_arm_circ_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_arm_circ_result, step, UINT8); + +prog_char help_arm_circ[] = "Arm_Circ the board"; +parse_pgm_inst_t cmd_arm_circ = { + .f = cmd_arm_circ_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_circ, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_circ_arg0, + (prog_void *)&cmd_arm_circ_arg1, + NULL, + }, +}; + + + +/**********************************************************/ +/* arm_harv */ + +/* this structure is filled when cmd_arm_harv is parsed successfully */ +struct cmd_arm_harv_result { + fixed_string_t arg0; + uint16_t wait; + int16_t hight; +}; + +#define ANGL1 2 +#define ANGL2 110 + +#define PWM_PUMP -3000 + +#define ARM_GET_D 68 + +//#define ARM_LOW_H -150 +#define ARM_LOW_D 210 + +#define FINGER_DELAY 200 + + +#define ARM_GET_H -150 +/* function called when cmd_arm_harv is parsed successfully */ +static void cmd_arm_harv_parsed(void * parsed_result, void * data) +{ + struct cmd_arm_harv_result *res = parsed_result; + + /*get column*/ + finger_left(); + wait_ms(FINGER_DELAY); + finger_center(); + wait_ms(FINGER_DELAY); + + arm_do_xy_nowait(&arm_pos_r, ARM_GET_H+10, ARM_GET_D, ANGL1, NULL); + + finger_right(); + wait_ms(FINGER_DELAY); + + /* TAKE COLUMN */ + //arm_do_xy_wait_nospeed(&arm_pos_r, 130, 130, ANGL1); + + arm_do_xy_wait_nospeed(&arm_pos_r, ARM_GET_H, ARM_GET_D, ANGL1); + + finger_left(); + + wait_ms(res->wait); + + pwm_ng_set(&arm.pwm1B, PWM_PUMP); + wait_ms(40); + + //self.ser.write("pwm 1B -3000\n"); + wait_ms(res->wait); + + //arm_do_xy_wait_nospeed(&arm_pos_r, -120, ARM_GET_D, ANGL1); + wait_ms(res->wait); + arm_do_xy_wait_nospeed(&arm_pos_r, ARM_GET_H+10, ARM_GET_D, ANGL2); + + + + /* WAIT LOLO FOR COLUMN*/ + finger_right(); + wait_ms(600); + + wait_ms(res->wait); + arm_do_xy_wait_nospeed(&arm_pos_r, ARM_GET_H, ARM_GET_D, ANGL2); + pwm_ng_set(&arm.pwm3C, PWM_PUMP); + + wait_ms(res->wait); + + + finger_left(); + wait_ms(40); + + + arm_do_xy_wait_nospeed(&arm_pos_r, res->hight+80,ARM_LOW_D-140,ANGL2); + wait_ms(res->wait); + arm_do_xy_wait_nospeed(&arm_pos_r, res->hight+80, ARM_LOW_D, ANGL2); + wait_ms(res->wait); + + + + + + /******** MAKE COLUMN *******/ + + arm_do_xy_wait_nospeed(&arm_pos_r, res->hight+10, ARM_LOW_D, ANGL2); + //plak arm_do_xy_wait_nospeed(&arm_pos_r, res->hight, ARM_LOW_D, ANGL2); + wait_ms(res->wait); + wait_ms(150); + pwm_ng_set(&arm.pwm3C, -PWM_PUMP); + wait_ms(res->wait); + wait_ms(100); + + + //arm_do_xy_nowait(&arm_pos_r, res->hight+65,ARM_LOW_D,ANGL2, NULL); + wait_ms(res->wait); + + arm_do_xy_wait_nospeed(&arm_pos_r, res->hight+65,ARM_LOW_D,ANGL1); + wait_ms(res->wait); + arm_do_xy_wait_nospeed(&arm_pos_r, res->hight+40,ARM_LOW_D,ANGL1); + //plak arm_do_xy_wait_nospeed(&arm_pos_r, res->hight+30,ARM_LOW_D,ANGL1); + wait_ms(res->wait); + wait_ms(150); + pwm_ng_set(&arm.pwm1B, -PWM_PUMP); + wait_ms(res->wait); + wait_ms(100); + + arm_do_xy_nowait(&arm_pos_r, res->hight+70,ARM_LOW_D,ANGL1, NULL); + + + pwm_ng_set(&arm.pwm1B, 0); + pwm_ng_set(&arm.pwm3C, 0); + + + arm_do_xy_nowait(&arm_pos_r, res->hight+80,ARM_LOW_D-140,ANGL1, NULL); + + arm_do_xy_nowait(&arm_pos_r, -100,80,ANGL1, NULL); + +} + +prog_char str_arm_harv_arg0[] = "arm_harv"; +parse_pgm_token_string_t cmd_arm_harv_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_harv_result, arg0, str_arm_harv_arg0); +parse_pgm_token_num_t cmd_arm_harv_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_arm_harv_result, wait, UINT16); +parse_pgm_token_num_t cmd_arm_harv_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_arm_harv_result, hight, INT16); + +prog_char help_arm_harv[] = "Arm_Harv the board"; +parse_pgm_inst_t cmd_arm_harv = { + .f = cmd_arm_harv_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_harv, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_harv_arg0, + (prog_void *)&cmd_arm_harv_arg1, + (prog_void *)&cmd_arm_harv_arg2, + NULL, + }, +}; + + + + +/**********************************************************/ +/* Arm_Straight */ + +/* this structure is filled when cmd_arm_straight is parsed successfully */ +struct cmd_arm_straight_result { + fixed_string_t arg0; + uint32_t arg1; + uint32_t arg2; + fixed_string_t arg3; +}; + +/* function called when cmd_arm_straight is parsed successfully */ +static void cmd_arm_straight_parsed(void * parsed_result, void * data) +{ + int32_t pos_shoulder[] = { + -15510, + -17181, + -18852, + -20524, + -22470, + -24416, + -26363, + -28309, + -30255, + -32464, + -34673, + -36881, + -39090, + -41299, + -43080, + -44861, + -46642, + -48423, + -50204, + -51026, + -51849, + -52671, + -53493, + -54316, + -54443, + -54370, + -54398, + }; + /* vitesse servo : 3ff = 114RPM = 233.2 pas/100ms */ + int32_t pos_elbow[] = { + 316, + 301, + 286, + 271, + 261, + 250, + 240, + 230, + 220, + 216, + 212, + 208, + 204, + 200, + 204, + 208, + 212, + 216, + 220, + 230, + 240, + 250, + 261, + 271, + 286, + 301, + 316, + }; + + int8_t i; + int32_t speed_shoulder; + int32_t speed_elbow; + int32_t arm_period; + int8_t arm_step; + int8_t arm_max_pos; + int8_t arm_world; + microseconds t_start; + + int8_t tab_len = sizeof(pos_elbow)/sizeof(int32_t); + + struct cmd_arm_straight_result *res = parsed_result; + + arm_period = res->arg1; + arm_step = res->arg2; + if (arm_step<0 || arm_step > tab_len){ + printf("bad step => reset to 1\r\n"); + arm_step = 1; + } + arm_world = strcmp("real", res->arg3); + printf("speed: %ld step:%d\r\n", arm_period, arm_step); + + //arm_goto(pos_shoulder[0], pos_elbow[0], 500); + printf("ready\r\n"); + while(uart_recv_nowait(0) == -1); + + arm_max_pos = (tab_len/arm_step)*arm_step; + + printf("tstart %ld\r\n", time_get_us2()); + /* 50 ms per incr */ + for (i=0; i<tab_len-arm_step; i+=arm_step) { + t_start = time_get_us2(); + + speed_shoulder = pos_shoulder[i+arm_step] - pos_shoulder[i]; + speed_shoulder /= arm_period/CS_PERIOD; /* period is 5ms */ + if (speed_shoulder < 0) + speed_shoulder = -speed_shoulder; + + speed_elbow = pos_elbow[i+arm_step] - pos_elbow[i]; + speed_elbow *= 0x3ff; + speed_elbow /= (233*arm_period/100000); + if (speed_elbow < 0) + speed_elbow = -speed_elbow; + + if (arm_world){ + printf("shoulder : %ld, %ld / elbow : %ld, %ld\r\n", + pos_shoulder[i], speed_shoulder, + pos_elbow[i], speed_elbow); + } + else{ + quadramp_set_1st_order_vars(&arm.qr_mot, speed_shoulder, speed_shoulder); + cs_set_consign(&arm.cs_mot, pos_shoulder[i]); + + AX12_write_int(&ax12, R_ELBOW_AX12, AA_MOVING_SPEED_L, speed_elbow); + AX12_write_int(&ax12, R_ELBOW_AX12, AA_GOAL_POSITION_L, pos_elbow[i]); + while(time_get_us2() - t_start < arm_period); + + } + } + printf("tstop %ld\r\n", time_get_us2()); + + + /* reset QUADRAMP */ + quadramp_set_1st_order_vars(&arm.qr_mot, 800, 800); /* set speed */ + quadramp_set_2nd_order_vars(&arm.qr_mot, 100, 100); /* set accel */ + +} + +prog_char str_arm_straight_arg0[] = "arm_straight"; +parse_pgm_token_string_t cmd_arm_straight_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_straight_result, arg0, str_arm_straight_arg0); +parse_pgm_token_num_t cmd_arm_straight_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_arm_straight_result, arg1, UINT32); +parse_pgm_token_num_t cmd_arm_straight_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_arm_straight_result, arg2, UINT32); +prog_char str_event_arg3[] = "sim#real"; +parse_pgm_token_string_t cmd_arm_straight_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_arm_straight_result, arg3, str_event_arg3); + + +prog_char help_arm_straight[] = "Arm_Straight func speed step"; +parse_pgm_inst_t cmd_arm_straight = { + .f = cmd_arm_straight_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_straight, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_straight_arg0, + (prog_void *)&cmd_arm_straight_arg1, + (prog_void *)&cmd_arm_straight_arg2, + (prog_void *)&cmd_arm_straight_arg3, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_baudrate is parsed successfully */ +struct cmd_baudrate_result { + fixed_string_t arg0; + uint32_t arg1; +}; + +/* function called when cmd_baudrate is parsed successfully */ +static void cmd_baudrate_parsed(void * parsed_result, void * data) +{ + struct cmd_baudrate_result *res = parsed_result; + struct uart_config c; + + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); + uart_getconf(1, &c); + c.baudrate = res->arg1; + uart_setconf(1, &c); + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); +} + +prog_char str_baudrate_arg0[] = "baudrate"; +parse_pgm_token_string_t cmd_baudrate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0, str_baudrate_arg0); +parse_pgm_token_num_t cmd_baudrate_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1, UINT32); + +prog_char help_baudrate[] = "Change ax12 baudrate"; +parse_pgm_inst_t cmd_baudrate = { + .f = cmd_baudrate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_baudrate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_baudrate_arg0, + (prog_void *)&cmd_baudrate_arg1, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_arm_goto is parsed successfully */ +struct cmd_arm_goto_result { + fixed_string_t arg0; + int32_t arg1; + uint16_t arg2; + uint16_t arg3; +}; + +/* function called when cmd_arm_goto is parsed successfully */ +static void cmd_arm_goto_parsed(void * parsed_result, void * data) +{ + struct cmd_arm_goto_result *res = parsed_result; + Arm_Pos * arm_pos; + if (!strcmp(res->arg0, "rarm_goto")) + arm_pos = &arm_pos_r; + else + arm_pos = &arm_pos_l; + arm_goto(arm_pos, res->arg1, res->arg2, res->arg3); + +} + +prog_char str_arm_goto_arg0[] = "larm_goto#rarm_goto"; +parse_pgm_token_string_t cmd_arm_goto_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_result, arg0, str_arm_goto_arg0); +parse_pgm_token_num_t cmd_arm_goto_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg1, INT32); +parse_pgm_token_num_t cmd_arm_goto_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg2, UINT16); +parse_pgm_token_num_t cmd_arm_goto_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg3, UINT16); + +prog_char help_arm_goto[] = "Change arm position (shoulder, elbow, wrist)"; +parse_pgm_inst_t cmd_arm_goto = { + .f = cmd_arm_goto_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_goto, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_goto_arg0, + (prog_void *)&cmd_arm_goto_arg1, + (prog_void *)&cmd_arm_goto_arg2, + (prog_void *)&cmd_arm_goto_arg3, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_arm_capture is parsed successfully */ +struct cmd_arm_capture_result { + fixed_string_t arg0; +}; + +/* function called when cmd_arm_capture is parsed successfully */ +static void cmd_arm_capture_parsed(void * parsed_result, void * data) +{ + struct cmd_arm_goto_result *res = parsed_result; + uint16_t elbow, wrist; + int32_t shoulder; + uint8_t ret = 0; + Arm_Pos *arm_pos; + + if (!strcmp_P(res->arg0, "rarm_capture")) + arm_pos = &arm_pos_r; + else + arm_pos = &arm_pos_l; + + + ret |= AX12_read_int(&ax12, arm_pos->ELBOW_AX12, AA_PRESENT_POSITION_L, &elbow); + ret |= AX12_read_int(&ax12, arm_pos->WRIST_AX12, AA_PRESENT_POSITION_L, &wrist); + shoulder = encoders_microb_get_value((void *)ARM_ENC); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%ld %d %d\r\n"), shoulder, elbow, wrist); +} + +prog_char str_arm_capture_arg0[] = "rarm_capture#larm_capture"; +parse_pgm_token_string_t cmd_arm_capture_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_capture_result, arg0, str_arm_capture_arg0); + +prog_char help_arm_capture[] = "Change arm position (shoulder, elbow, wrist)"; +parse_pgm_inst_t cmd_arm_capture = { + .f = cmd_arm_capture_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_capture, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_capture_arg0, + NULL, + }, +}; +/**********************************************************/ +/* Uint16 */ + + +/* this structure is filled when cmd_uint16_read is parsed successfully */ +struct cmd_uint16_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint16_t val; +}; + +/* function called when cmd_uint16_read is parsed successfully */ +static void cmd_uint16_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint16_t val; + uint8_t addr = addr_from_string(res->arg1); + ret = AX12_read_int(&ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.4x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint16_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint16_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0); +prog_char str_uint16_arg1[] = "moving_speed#model#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#down_calibration#up_calibration#torque_limit#" + "position#speed#load#punch"; +parse_pgm_token_string_t cmd_uint16_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1); +parse_pgm_token_num_t cmd_uint16_num = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, num, UINT8); + +prog_char help_uint16_read[] = "Read uint16 value (type, num)"; +parse_pgm_inst_t cmd_uint16_read = { + .f = cmd_uint16_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0, + (prog_void *)&cmd_uint16_arg1, + (prog_void *)&cmd_uint16_num, + NULL, + }, +}; + +/* function called when cmd_uint16_write is parsed successfully */ +static void cmd_uint16_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint8_t addr = addr_from_string(res->arg1); + printf_P(PSTR("writing %s: %d [0x%.4x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_int(&ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint16_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint16_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0_w); +prog_char str_uint16_arg1_w[] = "moving_speed#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#torque_limit#punch"; +parse_pgm_token_string_t cmd_uint16_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1_w); +parse_pgm_token_num_t cmd_uint16_val = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, val, UINT16); + +prog_char help_uint16_write[] = "Write uint16 value (write, num, val)"; +parse_pgm_inst_t cmd_uint16_write = { + .f = cmd_uint16_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0_w, + (prog_void *)&cmd_uint16_arg1_w, + (prog_void *)&cmd_uint16_num, + (prog_void *)&cmd_uint16_val, + NULL, + }, +}; + +/**********************************************************/ +/* Uint8 */ + + +/* this structure is filled when cmd_uint8_read is parsed successfully */ +struct cmd_uint8_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint8_t val; +}; + +/* function called when cmd_uint8_read is parsed successfully */ +static void cmd_uint8_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t ret; + uint8_t val; + uint8_t addr = addr_from_string(res->arg1); + + ret = AX12_read_byte(&ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.2x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint8_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint8_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0); +prog_char str_uint8_arg1[] = "id#firmware#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "voltage#temp#reginst#moving#lock"; +parse_pgm_token_string_t cmd_uint8_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1); +parse_pgm_token_num_t cmd_uint8_num = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, num, UINT8); + +prog_char help_uint8_read[] = "Read uint8 value (type, num)"; +parse_pgm_inst_t cmd_uint8_read = { + .f = cmd_uint8_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0, + (prog_void *)&cmd_uint8_arg1, + (prog_void *)&cmd_uint8_num, + NULL, + }, +}; + +/* function called when cmd_uint8_write is parsed successfully */ +static void cmd_uint8_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t addr = addr_from_string(res->arg1); + uint8_t ret; + printf_P(PSTR("writing %s: %d [0x%.2x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_byte(&ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint8_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint8_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0_w); +prog_char str_uint8_arg1_w[] = "id#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "reginst#lock"; +parse_pgm_token_string_t cmd_uint8_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1_w); +parse_pgm_token_num_t cmd_uint8_val = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, val, UINT8); + +prog_char help_uint8_write[] = "Write uint8 value (write, num, val)"; +parse_pgm_inst_t cmd_uint8_write = { + .f = cmd_uint8_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0_w, + (prog_void *)&cmd_uint8_arg1_w, + (prog_void *)&cmd_uint8_num, + (prog_void *)&cmd_uint8_val, + NULL, + }, +}; + +/**********************************************************/ +/* Encoders tests */ + +/* this structure is filled when cmd_encoders is parsed successfully */ +struct cmd_encoders_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_encoders is parsed successfully */ +static void cmd_encoders_parsed(void * parsed_result, void * data) +{ + while(uart_recv_nowait(0) == -1) { + printf_P(PSTR("% .8ld % .8ld % .8ld % .8ld\r\n"), + encoders_microb_get_value((void *)0), + encoders_microb_get_value((void *)1), + encoders_microb_get_value((void *)2), + encoders_microb_get_value((void *)3)); + wait_ms(100); + } +} + +prog_char str_encoders_arg0[] = "encoders"; +parse_pgm_token_string_t cmd_encoders_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg0, str_encoders_arg0); +prog_char str_encoders_arg1[] = "show"; +parse_pgm_token_string_t cmd_encoders_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg1, str_encoders_arg1); + +prog_char help_encoders[] = "Show encoders values"; +parse_pgm_inst_t cmd_encoders = { + .f = cmd_encoders_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_encoders, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_encoders_arg0, + (prog_void *)&cmd_encoders_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pwms tests */ + +/* this structure is filled when cmd_pwm is parsed successfully */ +struct cmd_pwm_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; +}; + +/* function called when cmd_pwm is parsed successfully */ +static void cmd_pwm_parsed(void * parsed_result, void * data) +{ + void * pwm_ptr = NULL; + struct cmd_pwm_result * res = parsed_result; + + DDRB |= 0x84; + + if (!strcmp_P(res->arg1, PSTR("1A"))) + pwm_ptr = &arm.pwm1A; + else if (!strcmp_P(res->arg1, PSTR("1B"))) + pwm_ptr = &arm.pwm1B; + else if (!strcmp_P(res->arg1, PSTR("3C"))) + pwm_ptr = &arm.pwm3C; + else if (!strcmp_P(res->arg1, PSTR("2"))) { + if (res->arg2 == 0) + PORTB &= ~0x84; + if (res->arg2 == 1) { + PORTB &= ~0x80; + PORTB |= 0x4; + } + if (res->arg2 == 0) { + PORTB &= ~0x04; + PORTB |= 0x80; + } + if (res->arg2 == 0) + PORTB |= 0x84; + + //pwm_ptr = &arm.pwm2; + + } + + if (pwm_ptr) + pwm_ng_set(pwm_ptr, res->arg2); + + printf_P(PSTR("done\r\n")); +} + +prog_char str_pwm_arg0[] = "pwm"; +parse_pgm_token_string_t cmd_pwm_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg0, str_pwm_arg0); +prog_char str_pwm_arg1[] = "1A#1B#3C#2"; +parse_pgm_token_string_t cmd_pwm_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg1, str_pwm_arg1); +parse_pgm_token_num_t cmd_pwm_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pwm_result, arg2, INT16); + +prog_char help_pwm[] = "Set pwm values [-4096 ; 4095]"; +parse_pgm_inst_t cmd_pwm = { + .f = cmd_pwm_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pwm, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pwm_arg0, + (prog_void *)&cmd_pwm_arg1, + (prog_void *)&cmd_pwm_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Gains for control system */ + +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t p; + int16_t i; + int16_t d; +}; + +/* function called when cmd_gain is parsed successfully */ +static void cmd_gain_parsed(void * parsed_result, void * data) +{ + struct cmd_gain_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + pid_set_gains(&arm.pid_mot, res->p, res->i, res->d); + } + /* else it is a "show" */ + + printf_P(PSTR("arm %d %d %d\r\n"), + pid_get_gain_P(&arm.pid_mot), + pid_get_gain_I(&arm.pid_mot), + pid_get_gain_D(&arm.pid_mot)); +} + +prog_char str_gain_arg0[] = "gain"; +parse_pgm_token_string_t cmd_gain_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, arg0, str_gain_arg0); +prog_char str_gain_arg1[] = "arm"; +parse_pgm_token_string_t cmd_gain_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, arg1, str_gain_arg1); +parse_pgm_token_num_t cmd_gain_p = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, p, INT16); +parse_pgm_token_num_t cmd_gain_i = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, i, INT16); +parse_pgm_token_num_t cmd_gain_d = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, d, INT16); + +prog_char help_gain[] = "Set gain values for PID"; +parse_pgm_inst_t cmd_gain = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_gain_arg1, + (prog_void *)&cmd_gain_p, + (prog_void *)&cmd_gain_i, + (prog_void *)&cmd_gain_d, + NULL, + }, +}; + +/* show */ + +prog_char str_gain_show_arg[] = "show"; +parse_pgm_token_string_t cmd_gain_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, arg1, str_gain_show_arg); + +prog_char help_gain_show[] = "Show gain values for PID"; +parse_pgm_inst_t cmd_gain_show = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_gain_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Speeds for control system */ + +/* this structure is filled when cmd_speed is parsed successfully */ +struct cmd_speed_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint16_t s; +}; + +/* function called when cmd_speed is parsed successfully */ +static void cmd_speed_parsed(void * parsed_result, void * data) +{ +#if 0 + struct cmd_speed_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + ramp_set_vars(&ext.r_b, res->s, res->s); /* set speed */ + } + + printf_P(PSTR("arm %lu\r\n"), + ext.r_b.var_pos); +#else + printf_P(PSTR("DISABLED FOR NOW\r\n")); +#endif +} + +prog_char str_speed_arg0[] = "speed"; +parse_pgm_token_string_t cmd_speed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, arg0, str_speed_arg0); +prog_char str_speed_arg1[] = "arm#show"; +parse_pgm_token_string_t cmd_speed_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, arg1, str_speed_arg1); +parse_pgm_token_num_t cmd_speed_s = TOKEN_NUM_INITIALIZER(struct cmd_speed_result, s, UINT16); + +prog_char help_speed[] = "Set speed values for ramp filter"; +parse_pgm_inst_t cmd_speed = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_speed_arg1, + (prog_void *)&cmd_speed_s, + NULL, + }, +}; + +/* show */ + +prog_char str_speed_show_arg[] = "show"; +parse_pgm_token_string_t cmd_speed_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, arg1, str_speed_show_arg); + +prog_char help_speed_show[] = "Show speed values for ramp filter"; +parse_pgm_inst_t cmd_speed_show = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_speed_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Pos for control system */ + +/* this structure is filled when cmd_pos is parsed successfully */ +struct cmd_pos_result { + fixed_string_t arg0; + fixed_string_t arg1; + int32_t p; +}; + +/* function called when cmd_pos is parsed successfully */ +static void cmd_pos_parsed(void * parsed_result, void * data) +{ + struct cmd_pos_result * res = parsed_result; + // uint8_t i; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + cs_set_consign(&arm.cs_mot, res->p); + } + +#if 0 + for (i=0; i<50; i++) { + printf("%ld %ld %ld\r\n", + pid_get_value_in(&arm.pid_mot), + pid_get_value_out(&arm.pid_mot), + pid_get_value_D(&arm.pid_mot) + ); + } +#endif +} + +prog_char str_pos_arg0[] = "pos"; +parse_pgm_token_string_t cmd_pos_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pos_result, arg0, str_pos_arg0); +prog_char str_pos_arg1[] = "arm"; +parse_pgm_token_string_t cmd_pos_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pos_result, arg1, str_pos_arg1); +parse_pgm_token_num_t cmd_pos_p = TOKEN_NUM_INITIALIZER(struct cmd_pos_result, p, INT32); + +prog_char help_pos[] = "Set pos value"; +parse_pgm_inst_t cmd_pos = { + .f = cmd_pos_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pos, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pos_arg0, + (prog_void *)&cmd_pos_arg1, + (prog_void *)&cmd_pos_p, + NULL, + }, +}; + + +/**********************************************************/ +/* Events on/off */ + +/* this structure is filled when cmd_event is parsed successfully */ +struct cmd_event_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + + +void init_arm(void) +{ + uint32_t shoulder_robot; + uint16_t elbow_robot, wrist_robot; + double shoulder_rad, elbow_rad; + int32_t h, d; + + /* init arm xy pos */ + shoulder_robot = encoders_microb_get_value(ARM_ENC); + AX12_read_int(&ax12, R_ELBOW_AX12, AA_PRESENT_POSITION_L, &elbow_robot); + AX12_read_int(&ax12, R_WRIST_AX12, AA_PRESENT_POSITION_L, &wrist_robot); + + AX12_write_int(&ax12, R_ELBOW_AX12, AA_MOVING_SPEED_L, 0x3ff); + AX12_write_int(&ax12, R_WRIST_AX12, AA_MOVING_SPEED_L, 0x3ff); + + + arm_pos_r.wrist_angle_deg2robot = wrist_angle_deg2robot_r; + arm_pos_l.wrist_angle_deg2robot = wrist_angle_deg2robot_l; + + arm_pos_r.angle_rad2robot = angle_rad2robot_r; + arm_pos_l.angle_rad2robot = angle_rad2robot_l; + + arm_pos_r.angle_robot2rad = angle_robot2rad_r; + arm_pos_l.angle_robot2rad = angle_robot2rad_l; + + arm_pos_r.ELBOW_AX12 = R_ELBOW_AX12; + arm_pos_l.ELBOW_AX12 = L_ELBOW_AX12; + + arm_pos_r.WRIST_AX12 = R_WRIST_AX12; + arm_pos_l.WRIST_AX12 = L_WRIST_AX12; + + + arm_pos_r.angle_robot2rad(shoulder_robot, elbow_robot, + &shoulder_rad, &elbow_rad); + angle2cart(shoulder_rad, elbow_rad, &h, &d); + printf("init: h:%ld d:%ld w:%d\r\n", h, d, wrist_robot); + + arm_pos_r.h = h; + arm_pos_r.d = d; + arm_pos_r.w = wrist_robot; + arm_pos_r.goal_h = h; + arm_pos_r.goal_d = d; + arm_pos_r.goal_w = wrist_robot; + arm_pos_r.state = ARM_STATE_IN_POS; + + + arm_pos_l.h = h; + arm_pos_l.d = d; + arm_pos_l.w = wrist_robot; + arm_pos_l.goal_h = h; + arm_pos_l.goal_d = d; + arm_pos_l.goal_w = wrist_robot; + arm_pos_l.state = ARM_STATE_IN_POS; + + + +} + + +/* function called when cmd_event is parsed successfully */ +static void cmd_event_parsed(void * parsed_result, void * data) +{ + u08 bit=0; + struct cmd_event_result * res = parsed_result; + + + + if (!strcmp_P(res->arg1, PSTR("cs"))) { + if (!strcmp_P(res->arg2, PSTR("on"))) { + pwm_ng_set(ARM_MOT_PWM, 0); + printf_P(PSTR("ax12 will start\r\n")); + while(uart_recv_nowait(0) == -1); + AX12_write_int(&ax12,0xFE,AA_TORQUE_ENABLE,0x1); + AX12_write_int(&ax12, R_ELBOW_AX12, AA_GOAL_POSITION_L, 660); + AX12_write_int(&ax12, R_WRIST_AX12, AA_GOAL_POSITION_L, 613); + printf_P(PSTR("Set the arm to 0\r\n")); + while(uart_recv_nowait(0) == -1); + encoders_microb_set_value(ARM_ENC, 0); + + + printf_P(PSTR("Set scanner to 0\r\n")); + while(uart_recv_nowait(0) == -1); + encoders_microb_set_value(SCANNER_ENC, 0); + scanner.flags |= CS_ON; + + init_arm(); + + + } + bit = CS_ON; + } +/* else if (!strcmp_P(res->arg1, PSTR("catapult"))) */ +/* bit = CATAPULT_CS_ON; */ + + if (!strcmp_P(res->arg2, PSTR("on"))) + arm.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) + arm.flags &= (~bit); + + printf_P(PSTR("%s is %s\r\n"), res->arg1, + (bit & arm.flags) ? "on":"off"); +} + +prog_char str_event_arg0[] = "event"; +parse_pgm_token_string_t cmd_event_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg0); +prog_char str_event_arg1[] = "cs"; +parse_pgm_token_string_t cmd_event_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg1); +prog_char str_event_arg2[] = "on#off#show"; +parse_pgm_token_string_t cmd_event_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg2, str_event_arg2); + +prog_char help_event[] = "Enable/disable events"; +parse_pgm_inst_t cmd_event = { + .f = cmd_event_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_event, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_event_arg0, + (prog_void *)&cmd_event_arg1, + (prog_void *)&cmd_event_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Maximums for control system */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint32_t in; + uint32_t i; + uint32_t out; +}; + +/* function called when cmd_maximum is parsed successfully */ +static void cmd_maximum_parsed(void * parsed_result, void * data) +{ + struct cmd_maximum_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + pid_set_maximums(&arm.pid_mot, res->in, res->i, res->out); + } + /* else it is a "show" */ + + printf_P(PSTR("maximum arm %lu %lu %lu\r\n"), + pid_get_max_in(&arm.pid_mot), + pid_get_max_I(&arm.pid_mot), + pid_get_max_out(&arm.pid_mot)); +} + +prog_char str_maximum_arg0[] = "maximum"; +parse_pgm_token_string_t cmd_maximum_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, arg0, str_maximum_arg0); +prog_char str_maximum_arg1[] = "arm"; +parse_pgm_token_string_t cmd_maximum_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, arg1, str_maximum_arg1); +parse_pgm_token_num_t cmd_maximum_in = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, in, UINT32); +parse_pgm_token_num_t cmd_maximum_i = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, i, UINT32); +parse_pgm_token_num_t cmd_maximum_out = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, out, UINT32); + +prog_char help_maximum[] = "Set maximum values for PID (in, I, out)"; +parse_pgm_inst_t cmd_maximum = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_maximum_arg1, + (prog_void *)&cmd_maximum_in, + (prog_void *)&cmd_maximum_i, + (prog_void *)&cmd_maximum_out, + NULL, + }, +}; + +/* show */ + +prog_char str_maximum_show_arg[] = "show"; +parse_pgm_token_string_t cmd_maximum_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, arg1, str_maximum_show_arg); + +prog_char help_maximum_show[] = "Show maximum values for PID"; +parse_pgm_inst_t cmd_maximum_show = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_maximum_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Quadramp for control system */ + +/* this structure is filled when cmd_quadramp is parsed successfully */ +struct cmd_quadramp_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint32_t ap; + uint32_t an; + uint32_t sp; + uint32_t sn; +}; + +/* function called when cmd_quadramp is parsed successfully */ +static void cmd_quadramp_parsed(void * parsed_result, void * data) +{ + struct cmd_quadramp_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + quadramp_set_1st_order_vars(&arm.qr_mot, res->sp, res->sn); + quadramp_set_2nd_order_vars(&arm.qr_mot, res->ap, res->an); + } +/* else if (!strcmp_P(res->arg1, PSTR("distance"))) { */ +/* quadramp_set_1st_order_vars(&arm.qr_d, res->sp, res->sn); */ +/* quadramp_set_2nd_order_vars(&arm.qr_d, res->ap, res->an); */ +/* } */ + /* else it's a "show" */ + + printf_P(PSTR("quadramp arm %ld %ld %ld %ld\r\n"), + arm.qr_mot.var_2nd_ord_pos, + arm.qr_mot.var_2nd_ord_neg, + arm.qr_mot.var_1st_ord_pos, + arm.qr_mot.var_1st_ord_neg); +} + +prog_char str_quadramp_arg0[] = "quadramp"; +parse_pgm_token_string_t cmd_quadramp_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, arg0, str_quadramp_arg0); +prog_char str_quadramp_arg1[] = "arm"; +parse_pgm_token_string_t cmd_quadramp_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, arg1, str_quadramp_arg1); +parse_pgm_token_num_t cmd_quadramp_ap = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, ap, UINT32); +parse_pgm_token_num_t cmd_quadramp_an = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, an, UINT32); +parse_pgm_token_num_t cmd_quadramp_sp = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sp, UINT32); +parse_pgm_token_num_t cmd_quadramp_sn = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sn, UINT32); + +prog_char help_quadramp[] = "Set quadramp values (acc+, acc-, speed+, speed-)"; +parse_pgm_inst_t cmd_quadramp = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_quadramp_arg1, + (prog_void *)&cmd_quadramp_ap, + (prog_void *)&cmd_quadramp_an, + (prog_void *)&cmd_quadramp_sp, + (prog_void *)&cmd_quadramp_sn, + + NULL, + }, +}; + +/* show */ + +prog_char str_quadramp_show_arg[] = "show"; +parse_pgm_token_string_t cmd_quadramp_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, arg1, str_quadramp_show_arg); + +prog_char help_quadramp_show[] = "Get quadramp values for control system"; +parse_pgm_inst_t cmd_quadramp_show = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_quadramp_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* sample ADC */ +extern uint16_t sample_i; +//extern uint16_t sample_tab[MAX_SAMPLE]; +/* this structure is filled when cmd_sample is parsed successfully */ +struct cmd_sample_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint16_t offset_a; +}; + +extern int32_t pos_start_scan; +int32_t scan_frwd = 0; +/* function called when cmd_sample is parsed successfully */ +static void cmd_sample_parsed(void * parsed_result, void * data) +{ + struct cmd_sample_result * res = parsed_result; + uint16_t i; + scan_frwd++; + //int32_t cs_err, cs_out, cs_in; + + printf_P(PSTR("cmd sample called!\r\n")); + printf_P(PSTR("arg %s %d!\r\n"), res->arg1, res->offset_a); + + offset_a = (((float)res->offset_a)*M_PI/180.); + + if (!strcmp_P(res->arg1, PSTR("start"))) { + sample_i = MAX_SAMPLE; + pos_start_scan = encoders_microb_get_value(SCANNER_ENC); + + memset(sample_tab, 0xff, MAX_SAMPLE*sizeof(uint8_t)); + + + //encoders_microb_set_value(SCANNER_ENC, 0); + cs_set_consign(&scanner.cs_mot, pos_start_scan+SCANNER_STEP_TOUR*200L); + + last_tour_n = 0; + last_tour_pos = 0; + + /* + while (uart_recv_nowait(0)==-1){ + wait_ms(200); + cs_err = cs_get_error(&scanner.cs_mot); + cs_out = cs_get_out(&scanner.cs_mot); + cs_in = cs_get_filtered_feedback(&scanner.cs_mot); + printf_P(PSTR("err: %ld out: %ld in: %ld\r\n"), cs_err, cs_out, cs_in); + + } + */ + + } + + + + + else if (!strcmp_P(res->arg1, PSTR("dump"))) { + printf_P(PSTR("start dumping\r\n")); + + for (i=0;i<MAX_SAMPLE;i++) + printf_P(PSTR("%d %d \r\n"),sample_tab[i]&0x1ff, sample_tab[i]&0x200?1:0); + printf_P(PSTR("end dumping (pos: %ld)\r\n"), + encoders_microb_get_value((void *)SCANNER_ENC)); + } + +} + +prog_char str_sample_arg0[] = "sample"; +parse_pgm_token_string_t cmd_sample_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_sample_result, arg0, str_sample_arg0); +prog_char str_sample_arg1[] = "start#dump"; +parse_pgm_token_string_t cmd_sample_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_sample_result, arg1, str_sample_arg1); +parse_pgm_token_num_t cmd_sample_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_sample_result, offset_a, UINT16); + +prog_char help_sample[] = "Sample func"; +parse_pgm_inst_t cmd_sample = { + .f = cmd_sample_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_sample, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_sample_arg0, + (prog_void *)&cmd_sample_arg1, + (prog_void *)&cmd_sample_arg2, + NULL, + }, +}; + + +/**********************************************************/ + + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_spi_test, + (parse_pgm_inst_t *)&cmd_bootloader, + (parse_pgm_inst_t *)&cmd_ax12_stress, + (parse_pgm_inst_t *)&cmd_armxy, + (parse_pgm_inst_t *)&cmd_arm_circ, + (parse_pgm_inst_t *)&cmd_arm_harv, + (parse_pgm_inst_t *)&cmd_test, + (parse_pgm_inst_t *)&cmd_arm_straight, + (parse_pgm_inst_t *)&cmd_baudrate, + (parse_pgm_inst_t *)&cmd_arm_goto, + (parse_pgm_inst_t *)&cmd_arm_capture, + (parse_pgm_inst_t *)&cmd_sample, + (parse_pgm_inst_t *)&cmd_uint16_read, + (parse_pgm_inst_t *)&cmd_uint16_write, + (parse_pgm_inst_t *)&cmd_uint8_read, + (parse_pgm_inst_t *)&cmd_uint8_write, + (parse_pgm_inst_t *)&cmd_encoders, + (parse_pgm_inst_t *)&cmd_pwm, + (parse_pgm_inst_t *)&cmd_gain, + (parse_pgm_inst_t *)&cmd_gain_show, + (parse_pgm_inst_t *)&cmd_speed, + (parse_pgm_inst_t *)&cmd_speed_show, + (parse_pgm_inst_t *)&cmd_pos, + (parse_pgm_inst_t *)&cmd_event, + (parse_pgm_inst_t *)&cmd_maximum, + (parse_pgm_inst_t *)&cmd_maximum_show, + (parse_pgm_inst_t *)&cmd_quadramp, + (parse_pgm_inst_t *)&cmd_quadramp_show, + + NULL, +}; diff --git a/projects/microb2009/tests/arm_test/encoders_microb_config.h b/projects/microb2009/tests/arm_test/encoders_microb_config.h new file mode 100755 index 0000000..7606df2 --- /dev/null +++ b/projects/microb2009/tests/arm_test/encoders_microb_config.h @@ -0,0 +1,45 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: encoders_microb_config.h,v 1.1 2008-12-26 13:08:29 zer0 Exp $ + * + */ +#ifndef _ENCODERS_MICROB_CONFIG_H_ +#define _ENCODERS_MICROB_CONFIG_H_ + +/** number of the LAST encoders used + 1 */ +#define ENCODERS_MICROB_NUMBER 4 + +#define ENCODERS_MICROB_SEL_PORT PORTE +#define ENCODERS_MICROB_SEL_BIT 6 + +#define ENCODERS_MICROB0_ENABLED +#define ENCODERS_MICROB0_PIN PINA + +#define ENCODERS_MICROB1_ENABLED +#define ENCODERS_MICROB1_PIN PINA + +#define ENCODERS_MICROB2_ENABLED +#define ENCODERS_MICROB2_PIN PINC + +#define ENCODERS_MICROB3_ENABLED +#define ENCODERS_MICROB3_PIN PINC + + +// ... until 7 + +#endif diff --git a/projects/microb2009/tests/arm_test/error_config.h b/projects/microb2009/tests/arm_test/error_config.h new file mode 100755 index 0000000..a7528f9 --- /dev/null +++ b/projects/microb2009/tests/arm_test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2008-12-26 13:08:29 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/tests/arm_test/i2c_config.h b/projects/microb2009/tests/arm_test/i2c_config.h new file mode 100644 index 0000000..03ae3e3 --- /dev/null +++ b/projects/microb2009/tests/arm_test/i2c_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.1 2009-01-30 20:38:49 zer0 Exp $ + * + */ + + +#define I2C_BITRATE 1 // divider dor i2c baudrate, see TWBR in doc +#define I2C_PRESCALER 3 // prescaler config, rate = 2^(n*2) + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 32 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 32 diff --git a/projects/microb2009/tests/arm_test/i2c_protocol.c b/projects/microb2009/tests/arm_test/i2c_protocol.c new file mode 100644 index 0000000..6efb8f4 --- /dev/null +++ b/projects/microb2009/tests/arm_test/i2c_protocol.c @@ -0,0 +1,86 @@ +/* + * Copyright Droids Corporation (2007) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_protocol.c,v 1.1 2009-01-30 20:38:49 zer0 Exp $ + * + */ + + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <uart.h> +#include <i2c.h> +#include <time.h> + +#include "../common/i2c_commands.h" +#include "strat_base.h" +#include "main.h" +#include "i2c_protocol.h" + +//#define DEBUG_FROM_EXT + +#define I2C_TIMEOUT 100 /* ms */ +#define I2C_MAX_ERRORS 40 + +/* used for commands */ +uint8_t command_buf[I2C_SEND_BUFFER_SIZE]; + +void i2c_protocol_init(void) +{ +} + +void i2c_poll_slaves(void * dummy) +{ +} + +/* called when the xmit is finished */ +void i2c_sendevent(int8_t size) +{ + if (size > 0) { + } + else { + i2c_errors++; + NOTICE(E_USER_I2C_PROTO, "send error size=%d", size); + } +} + +/* called rx event */ +void i2c_recvevent(uint8_t * buf, int8_t size) +{ + if (size < 0) { + goto error; + } + + for (i = 0; i<size; i++) { + printf("%x ", buf[1]); + } + printf("\r\n"); + + return; + error: + NOTICE(E_USER_I2C_PROTO, "recv error size=%d", size); +} + +void i2c_recvbyteevent(uint8_t hwstatus, uint8_t i, uint8_t c) +{ +} + + diff --git a/projects/microb2009/tests/arm_test/main.c b/projects/microb2009/tests/arm_test/main.c new file mode 100755 index 0000000..8f8eeb4 --- /dev/null +++ b/projects/microb2009/tests/arm_test/main.c @@ -0,0 +1,622 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.6 2009-03-15 20:08:51 zer0 Exp $ + * + */ + +/* + * Cmdline interface for AX12. Use the PC to command a daisy-chain of + * AX12 actuators with a nice command line interface. + * + * The circuit should be as following: + * + * |----------| + * | uart0|------->--- PC (baudrate=57600) + * | |-------<--- + * | atmega128| + * | | + * | uart1|---->---+-- AX12 (baudrate 1 000 000) + * | |----<---| + * |----------| + * + * Note that RX and TX pins of UART1 are connected together to provide + * a half-duplex UART emulation. + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <uart.h> +#include <i2c.h> +#include <ax12.h> +#include <parse.h> +#include <rdline.h> +#include <pwm_ng.h> +#include <encoders_microb.h> +#include <timer.h> +#include <scheduler.h> +#include <pid.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> +#include <adc.h> +#include <spi.h> + +#include "main.h" + +#include "arm_xy.h" + +/* for cmdline interface */ +struct rdline rdl; +char prompt[RDLINE_PROMPT_SIZE]; +extern parse_pgm_ctx_t main_ctx[]; + +/* structure defining the AX12 servo */ +AX12 ax12; +struct arm arm; + +struct arm scanner; + +/* for storing mesures*/ +uint8_t sample_tab[MAX_SAMPLE]; +uint16_t sample_i = 0; + +/******** For cmdline. See in commands.c for the list of commands. */ +static void write_char(char c) +{ + uart_send(0, c); +} + +static void +valid_buffer(const char * buf, uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char * buf, char * dstbuf, uint8_t dstsize, + int16_t * state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + +/********************************* AX12 commands */ + +/* + * --- use uart1 + * + * We use synchronous access (not interrupt driven) to the hardware + * UART, because we have to be sure that the transmission/reception is + * really finished when we return from the functions. + * + * We don't use the CM-5 circuit as described in the AX12 + * documentation, we simply connect TX and RX and use TXEN + RXEN + + * DDR to manage the port directions. + */ + +static volatile uint8_t ax12_state = AX12_STATE_READ; +extern volatile struct cirbuf g_tx_fifo[]; /* uart fifo */ +static volatile uint8_t ax12_nsent = 0; + +/* Called by ax12 module to send a character on serial line. Count the + * number of transmitted bytes. It will be used in ax12_recv_char() to + * drop the bytes that we transmitted. */ +static int8_t ax12_send_char(uint8_t c) +{ + uart_send(1, c); + ax12_nsent++; + return 0; +} + +/* for atmega256 */ +#ifndef TXEN +#define TXEN TXEN0 +#endif + +/* called by uart module when the character has been written in + * UDR. It does not mean that the byte is physically transmitted. */ +static void ax12_send_callback(char c) +{ + if (ax12_state == AX12_STATE_READ) { + /* disable TX when last byte is pushed. */ + if (CIRBUF_IS_EMPTY(&g_tx_fifo[1])) + UCSR1B &= ~(1<<TXEN); + } +} + +/* Called by ax12 module when we want to receive a char. Note that we + * also receive the bytes we sent ! So we need to drop them. */ +static int16_t ax12_recv_char(void) +{ + microseconds t = time_get_us2(); + int c; + while (1) { + c = uart_recv_nowait(1); + if (c != -1) { + if (ax12_nsent == 0) + return c; + ax12_nsent --; + } + + /* 50 ms timeout */ + if ((time_get_us2() - t) > 50000) + return -1; + } + return c; +} + +/* called by ax12 module when we want to switch serial line. As we + * work in interruption mode, this function can be called to switch + * back in read mode even if the bytes are not really transmitted on + * the line. That's why in this case we do nothing, we will fall back + * in read mode in any case when xmit is finished -- see in + * ax12_send_callback() -- */ +static void ax12_switch_uart(uint8_t state) +{ + uint8_t flags; + + if (state == AX12_STATE_WRITE) { + IRQ_LOCK(flags); + ax12_nsent=0; + while (uart_recv_nowait(1) != -1); + UCSR1B |= (1<<TXEN); + ax12_state = AX12_STATE_WRITE; + IRQ_UNLOCK(flags); + } + else { + IRQ_LOCK(flags); + if (CIRBUF_IS_EMPTY(&g_tx_fifo[1])) + UCSR1B &= ~(1<<TXEN); + ax12_state = AX12_STATE_READ; + IRQ_UNLOCK(flags); + } +} + +/***********************/ + +void do_led_blink(void * dummy) +{ +#if 1 /* simple blink */ + static uint8_t a=0; + + if(a) + LED1_ON(); + else + LED1_OFF(); + + a = !a; +#endif +} + +/* called every 5 ms */ +static void do_cs(void * dummy) +{ + if (arm.flags & CS_ON) + cs_manage(&arm.cs_mot); + + if (scanner.flags & CS_ON){ + cs_manage(&scanner.cs_mot); + + } + +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + static uint8_t encoder_running = 0; + + cpt++; + + /* log ? */ + if (encoder_running) + return; + + encoder_running = 1; + sei(); + + encoders_microb_manage(NULL); + encoder_running = 0; + + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +/* sending "pop" on uart0 resets the robot */ +static void emergency(char c) { + static uint8_t i = 0; + + if( (i == 0 && c == 'p') || + (i == 1 && c == 'o') || + (i == 2 && c == 'p') ) + i++; + else if ( !(i == 1 && c == 'p') ) + i = 0; + if(i == 3){ + reset(); + //PORTG|=0x3; + + } +} + +//#define SCANNER_STEP_TOUR (3525L) + +/* called every 1 ms */ +#define STEP_PER_POS 64L +#define PIX_PER_SCAN 80L + +int32_t pos_start_scan; +int32_t last_tour_n; +int32_t last_tour_pos; + + + + +#define X 45. +#define Y -11. +#define l1 9. +#define l2 21.13 +#define l3 47.14 +#define l_mirror 235. +#define h_mirror 15. + + +//#define offset_a (75.*M_PI/180.) +float offset_a; + +/* get motor angle in radian; return mirror angle in radian, cos a sin a */ +void ang2_a_mirror(float b, float * c_a, float* s_a, float* a) +{ + float x2, y2; + float A, DELTA, B, D; + + b+=offset_a; + x2 = X + l1*cos(b); + y2 = Y + l1*sin(b); + + A = (l3*l3+(x2)*(x2)+(y2)*(y2)-l2*l2)/(2*l3); + + DELTA = -(A*A-(x2)*(x2)-(y2)*(y2)); + B = sqrt(DELTA); + + D = (x2)*(x2)+(y2)*(y2); + + *c_a = (x2*A+y2*B)/D; + *s_a = -(x2*B-y2*A)/D; + + *a = atan2(*s_a, *c_a); +} + +/* get telemeter dist , cos a, sin a, a and return H, L of scanned point */ +void ang2_H_L(float l_telemetre, float c_a, float s_a, float a, float *H, float *L) +{ + float d; + d = h_mirror*c_a/s_a; + *H = (l_telemetre - l_mirror - d)*sin(2*a); + *L = l_mirror + d + *H/tan(2*a); +} + +// d_telemetre = a * cm + b +#define TELEMETRE_A (16.76) +#define TELEMETRE_B (-476.) + +static void do_adc(void * dummy) +{ + + int16_t a; + int32_t tour_n; + int32_t tour_pos; + int32_t pos, pos_tmp, last_pos; + int32_t mot_pos; + float dist; + + float b, c_a, s_a, H, L, m_a; + + + if (sample_i==0) + return; + + mot_pos = encoders_microb_get_value((void *)SCANNER_ENC); + mot_pos-=pos_start_scan; + + if (sample_i==1){ + printf_P(PSTR("dump end enc %ld %d \r\n"), mot_pos, PIX_PER_SCAN); + //scanner.flags &= (~CS_ON); + + mot_pos = SCANNER_STEP_TOUR*(encoders_microb_get_value((void *)SCANNER_ENC)/SCANNER_STEP_TOUR+1L); + cs_set_consign(&scanner.cs_mot, mot_pos); + //pwm_ng_set(SCANNER_MOT_PWM, 0); + + + } + a = adc_get_value( ADC_REF_AVCC | MUX_ADC0 ); + //printf_P(PSTR("polling : ADC0 = %i\n"),a); + dist = (a-TELEMETRE_B)/TELEMETRE_A; + + //printf_P(PSTR("enc val = %ld\r\n"), encoders_microb_get_value((void *)SCANNER_ENC)); + + + //sample_tab[MAX_SAMPLE-sample_i] = a>0x1ff?0x1FF:a; + //sample_tab[MAX_SAMPLE-sample_i] |= PINF&2?0x200:0; + + + tour_n = (mot_pos)/(SCANNER_STEP_TOUR); + tour_pos = (mot_pos)%(SCANNER_STEP_TOUR); + + b = (2.*M_PI)*(float)tour_pos/(float)(SCANNER_STEP_TOUR); + ang2_a_mirror(b, &c_a, &s_a, &m_a); + ang2_H_L(dist, c_a, s_a, m_a, &H, &L); + + H = H;//m_a*180/M_PI; + L = L;//(L-100)*PIX_PER_SCAN; + + + //printf_P(PSTR("%f %f\r\n"), dist, m_a*180/M_PI); + //printf_P(PSTR("%f %f\r\n"), m_a*180/M_PI, b*180/M_PI); + + //printf_P(PSTR("%d %f\r\n"), a, b*180/M_PI); + //printf_P(PSTR("%f %f\r\n"), H, L); + printf_P(PSTR("%f %f %f\r\n"), H, m_a*180/M_PI, offset_a); + if (tour_n%2){ + //tour_pos = ((SCANNER_STEP_TOUR/2)-tour_pos); + tour_pos = (tour_pos*PIX_PER_SCAN)/(SCANNER_STEP_TOUR); + } + else{ + tour_pos = ((SCANNER_STEP_TOUR-tour_pos)*PIX_PER_SCAN)/(SCANNER_STEP_TOUR); + } + + + + //pos = (tour_n*SCANNER_STEP_TOUR + tour_pos)/STEP_PER_POS; + pos= tour_n*PIX_PER_SCAN+tour_pos; + last_pos= last_tour_n*PIX_PER_SCAN+last_tour_pos; + + //a-=0x100; + a-=200; + //a/=10; + + if (pos <MAX_SAMPLE)// && tour_n%2) + //sample_tab[pos] = a>0xff?0xFF:a; + //sample_tab[(int)L] = H ; + sample_tab[pos] = H; + nop(); + + if (last_tour_n == tour_n){ + if (pos > last_pos){ + pos_tmp = pos; + pos = last_pos; + last_pos = pos_tmp; + } + for (pos_tmp=pos;pos_tmp< last_pos;pos_tmp++){ + if (pos_tmp <MAX_SAMPLE)// && tour_n%2) + //sample_tab[pos_tmp] = a>0xff?0xFF:a; + nop(); + + } + + } + + + + last_tour_n = tour_n; + last_tour_pos = tour_pos; + + + //printf("pos : %ld\r\n", pos); + //sample_tab[sample_i] = a>0x1ff?0x1FF:a; + + //sample_ok_tab[MAX_SAMPLE-sample_i] = PORTF&2; + + /* + if (((pos <MAX_SAMPLE)) && (tour_pos<=(SCANNER_STEP_TOUR/2))) + sample_tab[pos] = 0xffff; + */ + sample_i--; +} + +int main(void) +{ + int c; + const char * history; + int8_t ret; + + /* brake */ + DDRG=0x3; + PORTG=0x0; + + /* LEDS */ + DDRE=0x0C; + + LED1_OFF(); + memset(&arm, 0, sizeof(struct arm)); + + /* PID */ + pid_init(&arm.pid_mot); + pid_set_gains(&arm.pid_mot, 80, 5, 250); + pid_set_maximums(&arm.pid_mot, 0, 10000, 4095); + pid_set_out_shift(&arm.pid_mot, 6); + pid_set_derivate_filter(&arm.pid_mot, 6); + + + /* QUADRAMP */ + quadramp_init(&arm.qr_mot); + quadramp_set_1st_order_vars(&arm.qr_mot, 200, 200); /* set speed */ + quadramp_set_2nd_order_vars(&arm.qr_mot, 20, 20); /* set accel */ + + /* CS */ + memset(&scanner, 0, sizeof(struct arm)); + + cs_init(&arm.cs_mot); + cs_set_consign_filter(&arm.cs_mot, quadramp_do_filter, &arm.qr_mot); + cs_set_correct_filter(&arm.cs_mot, pid_do_filter, &arm.pid_mot); + cs_set_process_in(&arm.cs_mot, pwm_ng_set, ARM_MOT_PWM); + cs_set_process_out(&arm.cs_mot, encoders_microb_get_value, ARM_ENC); + cs_set_consign(&arm.cs_mot, 0); + + + + pid_init(&scanner.pid_mot); + pid_set_gains(&scanner.pid_mot, 80, 5, 250); + pid_set_maximums(&scanner.pid_mot, 0, 10000, 2047); + pid_set_out_shift(&scanner.pid_mot, 6); + pid_set_derivate_filter(&scanner.pid_mot, 6); + + + quadramp_init(&scanner.qr_mot); + quadramp_set_1st_order_vars(&scanner.qr_mot, 40, 40); /* set speed */ + quadramp_set_2nd_order_vars(&scanner.qr_mot, 20, 20); /* set accel */ + + + cs_init(&scanner.cs_mot); + cs_set_consign_filter(&scanner.cs_mot, quadramp_do_filter, &scanner.qr_mot); + cs_set_correct_filter(&scanner.cs_mot, pid_do_filter, &scanner.pid_mot); + cs_set_process_in(&scanner.cs_mot, pwm_ng_set, SCANNER_MOT_PWM); + cs_set_process_out(&scanner.cs_mot, encoders_microb_get_value, SCANNER_ENC); + cs_set_consign(&scanner.cs_mot, 0); + + //scanner.flags |= CS_ON; + + + +#if 0 + /* SPI */ + spi_init(SPI_MODE_MASTER, SPI_FORMAT_2, SPI_CLK_RATE_16); + spi_set_data_order(SPI_MSB_FIRST); + spi_register_ss_line(&SS_PORT, SS_BIT); +#endif + + /* UART */ + /* Initialize full duplex uart direction port */ + sbi(PORTD,3); /* pullup */ + uart_init(); + /* disable rx intr, needed for AX12 !! */ + //UCSRnB &= ~( (1 << RXCIE) | (1 << UDRIE) | (1 << TXCIE) ); + + ax12_switch_uart(AX12_STATE_READ); + fdevopen(uart0_dev_send, uart0_dev_recv); + uart_register_rx_event(0, emergency); + + /* I2C */ + wait_ms(50); +/* i2c_protocol_init(); */ + i2c_init(I2C_MODE_MASTER, 0/* I2C_MAIN_ADDR */); +/* i2c_register_recv_event(i2c_recvevent); */ +/* i2c_register_send_event(i2c_sendevent); */ +/* scheduler_add_periodical_event_priority(i2c_poll_slaves, NULL, */ +/* 8000L / SCHEDULER_UNIT, I2C_POLL_PRIO); */ + + /* AX12 */ + AX12_init(&ax12); + AX12_set_hardware_send(&ax12, ax12_send_char); + AX12_set_hardware_recv(&ax12, ax12_recv_char); + AX12_set_hardware_switch(&ax12, ax12_switch_uart); + uart_register_tx_event(1, ax12_send_callback); + + /* ENCODERS */ + encoders_microb_init(); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* SCHEDULER */ + scheduler_init(); + scheduler_add_periodical_event_priority(do_led_blink, NULL, + 100000L / SCHEDULER_UNIT, + LED_PRIO); + /* PWM */ + PWM_NG_TIMER_16BITS_INIT(1, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_1); + + PWM_NG_TIMER_16BITS_INIT(3, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_1); + +/* pwm_ng_timer_8bits_init(2, TIMER_8_MODE_PWM, */ +/* TIMER1_PRESCALER_DIV_1); */ + PWM_NG_INIT16(&arm.pwm1A, 1, A, 10, PWM_NG_MODE_SIGNED | + PWM_NG_MODE_SIGN_INVERTED, &PORTB, 0); + PWM_NG_INIT16(&arm.pwm1B, 1, B, 10, PWM_NG_MODE_SIGNED, + &PORTB, 1); + PWM_NG_INIT16(&arm.pwm3C, 3, C, 10, PWM_NG_MODE_SIGNED, + &PORTE, 4); +/* PWM_NG_INIT8(&arm.pwm2, 2, 10, PWM_NG_MODE_SIGNED, */ +/* &PORTB, 2); */ + + /* CS EVENT */ + scheduler_add_periodical_event_priority(do_cs, NULL, + CS_PERIOD / SCHEDULER_UNIT, + CS_PRIO); + + /* ADC EVENT */ + + adc_init(); + scheduler_add_periodical_event_priority(do_adc, NULL, + 2000L / SCHEDULER_UNIT, + CS_PRIO-1); + + wait_ms(200); + + /* arm xy init matrix */ + init_arm_matrix(); + + /* TIME */ + time_init(TIME_PRIO); + + wait_ms(200); + + sei(); + + printf_P(PSTR("Coucou\r\n")); + + /* set status return level to 2 and torque to 0 */ + AX12_write_int(&ax12,0xFE, AA_TORQUE_ENABLE, 0x00); + AX12_write_byte(&ax12, 0xFE, AA_STATUS_RETURN_LEVEL, 2); + + rdline_init(&rdl, write_char, valid_buffer, complete_buffer); + snprintf(prompt, sizeof(prompt), "ax12 > "); + rdline_newline(&rdl, prompt); + + + while (1) { + c = uart_recv_nowait(0); + if (c == -1) + continue; + ret = rdline_char_in(&rdl, c); + if (ret != 2 && ret != 0) { + history = rdline_get_buffer(&rdl); + if (strlen(history) > 1) + rdline_add_history(&rdl, history); + rdline_newline(&rdl, prompt); + } + } + + return 0; +} diff --git a/projects/microb2009/tests/arm_test/main.h b/projects/microb2009/tests/arm_test/main.h new file mode 100755 index 0000000..429db04 --- /dev/null +++ b/projects/microb2009/tests/arm_test/main.h @@ -0,0 +1,66 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.h,v 1.3 2009-03-15 20:08:51 zer0 Exp $ + * + */ + +#define LED1_ON() sbi(PORTE, 2) +#define LED1_OFF() cbi(PORTE, 2) + +#define LED2_ON() sbi(PORTE, 3) +#define LED2_OFF() cbi(PORTE, 3) + +#define ARM_MOT_PWM (&arm.pwm1B) +#define SCANNER_MOT_PWM (&arm.pwm1A) + + +#define ARM_ENC ((void *)0) +#define SCANNER_ENC ((void *)1) + +#define CS_PERIOD 5000L +#define LED_PRIO 170 +#define TIME_PRIO 160 +#define CS_PRIO 150 + +struct arm { +#define CS_ON 1 + uint8_t flags; + struct cs cs_mot; + struct pid_filter pid_mot; + struct quadramp_filter qr_mot; + struct pwm_ng pwm1A; + struct pwm_ng pwm1B; + struct pwm_ng pwm3C; + struct pwm_ng pwm2; +}; + +#define MAX_SAMPLE (1200L) + /* was 1000 */ + +extern struct arm arm; +extern struct arm scanner; + +extern uint8_t sample_tab[MAX_SAMPLE]; + +extern int32_t last_tour_n; +extern int32_t last_tour_pos; + +//64*14*4 (+1?) +#define SCANNER_STEP_TOUR (3532L) + +extern float offset_a; diff --git a/projects/microb2009/tests/arm_test/pid_config.h b/projects/microb2009/tests/arm_test/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/projects/microb2009/tests/arm_test/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/projects/microb2009/tests/arm_test/pwm_config.h b/projects/microb2009/tests/arm_test/pwm_config.h new file mode 100755 index 0000000..5b700e4 --- /dev/null +++ b/projects/microb2009/tests/arm_test/pwm_config.h @@ -0,0 +1,66 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: pwm_config.h,v 1.2 2009-01-23 23:10:25 zer0 Exp $ + * + */ + +/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0 + * Config for PWM + */ + +#ifndef _PWM_CONFIG_ +#define _PWM_CONFIG_ + +#define _PWM_CONFIG_VERSION_ 2 + +/* Which PWM are enabled ? */ +#define PWM1A_ENABLED +#define PWM1B_ENABLED +/* #define PWM1C_ENABLED */ +/* #define PWM3A_ENABLED */ +/* #define PWM3B_ENABLED */ +#define PWM3C_ENABLED + +/** max value for PWM entry, default 12 bits > 4095 */ +#define PWM_SIGNIFICANT_BITS 12 + +#define TIMER1_MODE TIMER_16_MODE_PWM_10 +#define TIMER1_PRESCALE TIMER1_PRESCALER_DIV_1 + +#define TIMER3_MODE TIMER_16_MODE_PWM_10 +#define TIMER3_PRESCALE TIMER3_PRESCALER_DIV_1 + + +#define PWM1A_MODE (PWM_SIGNED // | PWM_SIGN_INVERTED) +#define PWM1A_SIGN_PORT PORTB +#define PWM1A_SIGN_BIT 0 + +#define PWM1B_MODE (PWM_SIGNED) +#define PWM1B_SIGN_PORT PORTB +#define PWM1B_SIGN_BIT 1 + +#define PWM3C_MODE (PWM_SIGNED) /* left */ +#define PWM3C_SIGN_PORT PORTE +#define PWM3C_SIGN_BIT 4 + +/* #define PWM2_MODE (PWM_SIGNED) */ +/* #define PWM2_SIGN_PORT PORTB */ +/* #define PWM2_SIGN_BIT 2 */ + +#endif + diff --git a/projects/microb2009/tests/arm_test/rdline_config.h b/projects/microb2009/tests/arm_test/rdline_config.h new file mode 100755 index 0000000..e69de29 diff --git a/projects/microb2009/tests/arm_test/scheduler_config.h b/projects/microb2009/tests/arm_test/scheduler_config.h new file mode 100755 index 0000000..1f1f619 --- /dev/null +++ b/projects/microb2009/tests/arm_test/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1 2008-12-26 13:08:29 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 7 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/microb2009/tests/arm_test/spi_config.h b/projects/microb2009/tests/arm_test/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/microb2009/tests/arm_test/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/microb2009/tests/arm_test/time_config.h b/projects/microb2009/tests/arm_test/time_config.h new file mode 100755 index 0000000..c92429b --- /dev/null +++ b/projects/microb2009/tests/arm_test/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.2 2009-03-15 20:08:51 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 1000l diff --git a/projects/microb2009/tests/arm_test/timer_config.h b/projects/microb2009/tests/arm_test/timer_config.h new file mode 100755 index 0000000..b6ee274 --- /dev/null +++ b/projects/microb2009/tests/arm_test/timer_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1 2008-12-26 13:08:29 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 diff --git a/projects/microb2009/tests/arm_test/uart_config.h b/projects/microb2009/tests/arm_test/uart_config.h new file mode 100755 index 0000000..bd4c09e --- /dev/null +++ b/projects/microb2009/tests/arm_test/uart_config.h @@ -0,0 +1,104 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2 2009-01-03 16:19:30 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 64 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + +/* + * UART1 definitions + */ + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 115200 +//#define UART1_BAUDRATE 1000000 + + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +//#define UART1_USE_DOUBLE_SPEED 0 +#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 32 +#define UART1_TX_FIFO_SIZE 32 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +//#define UART1_STOP_BIT UART_STOP_BITS_1 +#define UART1_STOP_BIT UART_STOP_BITS_2 + + +#endif + diff --git a/projects/microb2009/tests/atm2560/.config b/projects/microb2009/tests/atm2560/.config new file mode 100644 index 0000000..17f2fd1 --- /dev/null +++ b/projects/microb2009/tests/atm2560/.config @@ -0,0 +1,242 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_MCU_ATMEGA2560=y +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_SCHEDULER=y +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +CONFIG_MODULE_TIME=y +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +CONFIG_MODULE_I2C=y +CONFIG_MODULE_I2C_MASTER=y +# CONFIG_MODULE_I2C_MULTIMASTER is not set +CONFIG_MODULE_I2C_CREATE_CONFIG=y +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +CONFIG_MODULE_PWM_NG=y +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +CONFIG_MODULE_AX12=y +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +CONFIG_MODULE_CONTROL_SYSTEM_MANAGER=y +CONFIG_MODULE_PID=y +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +CONFIG_MODULE_QUADRAMP=y +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/microb2009/tests/atm2560/CVS/Entries b/projects/microb2009/tests/atm2560/CVS/Entries new file mode 100644 index 0000000..a7c5bb1 --- /dev/null +++ b/projects/microb2009/tests/atm2560/CVS/Entries @@ -0,0 +1,15 @@ +/.config/1.2/Fri Feb 20 21:10:01 2009// +/Makefile/1.2/Fri Feb 20 21:10:01 2009// +/ax12_config.h/1.1/Fri Feb 20 21:10:01 2009// +/commands.c/1.1/Fri Feb 20 21:10:01 2009// +/i2c_config.h/1.1/Fri Feb 20 21:10:01 2009// +/main.c/1.2/Fri Feb 20 21:10:01 2009// +/main.h/1.1/Fri Feb 20 21:10:01 2009// +/pid_config.h/1.1/Fri Feb 20 21:10:01 2009// +/rdline_config.h/1.1/Fri Feb 20 21:10:01 2009// +/scheduler_config.h/1.1/Fri Feb 20 21:10:01 2009// +/spi_config.h/1.1/Fri Feb 20 21:10:01 2009// +/time_config.h/1.1/Fri Feb 20 21:10:01 2009// +/timer_config.h/1.1/Fri Feb 20 21:10:01 2009// +/uart_config.h/1.2/Fri Feb 20 21:10:01 2009// +D diff --git a/projects/microb2009/tests/atm2560/CVS/Repository b/projects/microb2009/tests/atm2560/CVS/Repository new file mode 100644 index 0000000..4e1445a --- /dev/null +++ b/projects/microb2009/tests/atm2560/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests/atm2560 diff --git a/projects/microb2009/tests/atm2560/CVS/Root b/projects/microb2009/tests/atm2560/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/atm2560/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/atm2560/CVS/Template b/projects/microb2009/tests/atm2560/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/atm2560/Makefile b/projects/microb2009/tests/atm2560/Makefile new file mode 100755 index 0000000..81af460 --- /dev/null +++ b/projects/microb2009/tests/atm2560/Makefile @@ -0,0 +1,31 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. +# VALUE, absolute or relative path : example ../.. # + +# CFLAGS += -Werror + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c commands.c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +AVRDUDE_DELAY=50 + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/tests/atm2560/ax12_config.h b/projects/microb2009/tests/atm2560/ax12_config.h new file mode 100755 index 0000000..072e8fb --- /dev/null +++ b/projects/microb2009/tests/atm2560/ax12_config.h @@ -0,0 +1,7 @@ +#ifndef _AX12_CONFIG_H_ +#define _AX12_CONFIG_H_ + +#define AX12_MAX_PARAMS 32 + + +#endif/*_AX12_CONFIG_H_*/ diff --git a/projects/microb2009/tests/atm2560/commands.c b/projects/microb2009/tests/atm2560/commands.c new file mode 100644 index 0000000..d3e5437 --- /dev/null +++ b/projects/microb2009/tests/atm2560/commands.c @@ -0,0 +1,1313 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <i2c.h> +#include <ax12.h> +#include <parse.h> +#include <parse_num.h> +#include <parse_string.h> +#include <uart.h> +#include <pwm_ng.h> +#include <pid.h> +#include <spi.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> + +#include "main.h" + +extern AX12 ax12; + +uint8_t addr_from_string(const char *s) +{ + /* 16 bits */ + if (!strcmp_P(s, PSTR("cw_angle_limit"))) + return AA_CW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("ccw_angle_limit"))) + return AA_CCW_ANGLE_LIMIT_L; + if (!strcmp_P(s, PSTR("max_torque"))) + return AA_MAX_TORQUE_L; + if (!strcmp_P(s, PSTR("down_calibration"))) + return AA_DOWN_CALIBRATION_L; + if (!strcmp_P(s, PSTR("up_calibration"))) + return AA_UP_CALIBRATION_L; + if (!strcmp_P(s, PSTR("torque_limit"))) + return AA_TORQUE_LIMIT_L; + if (!strcmp_P(s, PSTR("position"))) + return AA_PRESENT_POSITION_L; + if (!strcmp_P(s, PSTR("speed"))) + return AA_PRESENT_SPEED_L; + if (!strcmp_P(s, PSTR("load"))) + return AA_PRESENT_LOAD_L; + if (!strcmp_P(s, PSTR("moving_speed"))) + return AA_MOVING_SPEED_L; + if (!strcmp_P(s, PSTR("model"))) + return AA_MODEL_NUMBER_L; + if (!strcmp_P(s, PSTR("goal_pos"))) + return AA_GOAL_POSITION_L; + if (!strcmp_P(s, PSTR("punch"))) + return AA_PUNCH_L; + + /* 8 bits */ + if (!strcmp_P(s, PSTR("firmware"))) + return AA_FIRMWARE; + if (!strcmp_P(s, PSTR("id"))) + return AA_ID; + if (!strcmp_P(s, PSTR("baudrate"))) + return AA_BAUD_RATE; + if (!strcmp_P(s, PSTR("delay"))) + return AA_DELAY_TIME; + if (!strcmp_P(s, PSTR("high_lim_temp"))) + return AA_HIGHEST_LIMIT_TEMP; + if (!strcmp_P(s, PSTR("low_lim_volt"))) + return AA_LOWEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("high_lim_volt"))) + return AA_HIGHEST_LIMIT_VOLTAGE; + if (!strcmp_P(s, PSTR("status_return"))) + return AA_STATUS_RETURN_LEVEL; + if (!strcmp_P(s, PSTR("alarm_led"))) + return AA_ALARM_LED; + if (!strcmp_P(s, PSTR("alarm_shutdown"))) + return AA_ALARM_SHUTDOWN; + if (!strcmp_P(s, PSTR("torque_enable"))) + return AA_TORQUE_ENABLE; + if (!strcmp_P(s, PSTR("led"))) + return AA_LED; + if (!strcmp_P(s, PSTR("cw_comp_margin"))) + return AA_CW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("ccw_comp_margin"))) + return AA_CCW_COMPLIANCE_MARGIN; + if (!strcmp_P(s, PSTR("cw_comp_slope"))) + return AA_CW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("ccw_comp_slope"))) + return AA_CCW_COMPLIANCE_SLOPE; + if (!strcmp_P(s, PSTR("voltage"))) + return AA_PRESENT_VOLTAGE; + if (!strcmp_P(s, PSTR("temp"))) + return AA_PRESENT_TEMP; + if (!strcmp_P(s, PSTR("reginst"))) + return AA_PRESENT_REGINST; + if (!strcmp_P(s, PSTR("moving"))) + return AA_MOVING; + if (!strcmp_P(s, PSTR("lock"))) + return AA_LOCK; + + return 0; +} + + + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(void * parsed_result, void * data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Spi_Test */ + +/* this structure is filled when cmd_spi_test is parsed successfully */ +struct cmd_spi_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_spi_test is parsed successfully */ +static void cmd_spi_test_parsed(void * parsed_result, void * data) +{ +#if 0 + uint8_t i, ret; + + for (i=0; i<3; i++) { + spi_slave_select(0); + ret = spi_send_and_receive_byte(i); + spi_slave_deselect(0); + printf_P(PSTR("Sent %d, received %d\r\n"), i, ret); + } +#else + printf_P(PSTR("disabled\r\n")); +#endif +} + +prog_char str_spi_test_arg0[] = "spi_test"; +parse_pgm_token_string_t cmd_spi_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_spi_test_result, arg0, str_spi_test_arg0); + +prog_char help_spi_test[] = "Test the SPI"; +parse_pgm_inst_t cmd_spi_test = { + .f = cmd_spi_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_spi_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_spi_test_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Bootloader */ + +/* this structure is filled when cmd_bootloader is parsed successfully */ +struct cmd_bootloader_result { + fixed_string_t arg0; +}; + +/* function called when cmd_bootloader is parsed successfully */ +static void cmd_bootloader_parsed(void *parsed_result, void *data) +{ +#define BOOTLOADER_ADDR 0x3f000 + if (pgm_read_byte_far(BOOTLOADER_ADDR) == 0xff) { + printf_P(PSTR("Bootloader is not present\r\n")); + return; + } + cli(); + /* ... very specific :( */ + TIMSK0 = 0; + TIMSK1 = 0; + TIMSK2 = 0; + TIMSK3 = 0; + TIMSK4 = 0; + TIMSK5 = 0; + EIMSK = 0; + UCSR0B = 0; + UCSR1B = 0; + UCSR2B = 0; + UCSR3B = 0; + SPCR = 0; + TWCR = 0; + ACSR = 0; + ADCSRA = 0; + + EIND = 1; + __asm__ __volatile__ ("ldi r31,0xf8\n"); + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("eijmp\n"); +} + +prog_char str_bootloader_arg0[] = "bootloader"; +parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0); + +prog_char help_bootloader[] = "Launch the bootloader"; +parse_pgm_inst_t cmd_bootloader = { + .f = cmd_bootloader_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_bootloader, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_bootloader_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Ax12_Stress */ + +/* this structure is filled when cmd_ax12_stress is parsed successfully */ +struct cmd_ax12_stress_result { + fixed_string_t arg0; +}; + +/* function called when cmd_ax12_stress is parsed successfully */ +static void cmd_ax12_stress_parsed(void * parsed_result, void * data) +{ + int i, nb_errs = 0; + uint8_t val; + microseconds t = time_get_us2(); + + for (i=0; i<1000; i++) { + if (AX12_read_byte(&ax12, 3, AA_ID, &val) != 0) + nb_errs ++; + } + + printf_P(PSTR("%d errors / 1000\r\n"), nb_errs); + t = (time_get_us2() - t) / 1000; + printf_P(PSTR("Test done in %d ms\r\n"), (int)t); +} + +prog_char str_ax12_stress_arg0[] = "ax12_stress"; +parse_pgm_token_string_t cmd_ax12_stress_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_ax12_stress_result, arg0, str_ax12_stress_arg0); + +prog_char help_ax12_stress[] = "Ax12_Stress the board"; +parse_pgm_inst_t cmd_ax12_stress = { + .f = cmd_ax12_stress_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_ax12_stress, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_ax12_stress_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Test */ + +/* this structure is filled when cmd_test is parsed successfully */ +struct cmd_test_result { + fixed_string_t arg0; +}; + +#define ELBOW_AX12 1 +#define WRIST_AX12 2 +void arm_goto(int32_t shoulder, uint16_t elbow, uint16_t wrist) +{ + uint8_t err; + + printf("%ld %d\r\n", shoulder, elbow); + cs_set_consign(&arm.cs_mot, shoulder); + err = AX12_write_int(&ax12, ELBOW_AX12, AA_GOAL_POSITION_L, elbow); + if (!err) + AX12_write_int(&ax12, WRIST_AX12, AA_GOAL_POSITION_L, wrist); + if (err) + printf_P(PSTR("AX12 error %x !\r\n"), err); +} + +#define arm_take_high_v1() arm_goto(-18700, 204, 455) +#define arm_take_low_v1() arm_goto(-11000, 273, 480) +#define arm_take_high_v2() arm_goto(-18700, 204, 154) +#define arm_take_low_v2() arm_goto(-11000, 273, 139) +#define arm_intermediate() arm_goto(-35700, 297, 385) +#define arm_drop_v2() arm_goto(-16810, 667, 564) +#define arm_drop_v1() arm_goto(-16810, 667, 904) + +/* function called when cmd_test is parsed successfully */ +static void cmd_test_parsed(void * parsed_result, void * data) +{ + uint8_t i=0; +/* int8_t err; */ + + /* Set some AX12 parameters */ +/* err = AX12_write_int(&ax12,0xFE,AA_TORQUE_ENABLE,0x1); */ +/* if (!err) */ +/* AX12_write_int(&ax12,0xFE,AA_PUNCH_L,0x20); */ +/* if (!err) */ +/* AX12_write_int(&ax12,0xFE,AA_TORQUE_LIMIT_L,0x3FF); */ +/* if (!err) */ +/* AX12_write_int(&ax12,0xFE,AA_MOVING_SPEED_L,0x3FF); */ +/* if (!err) */ +/* AX12_write_byte(&ax12,0xFE,AA_ALARM_LED,0xEF); */ +/* if (err) { */ +/* printf_P(PSTR("AX12 error %x !\r\n"), err); */ +/* return; */ +/* } */ + + for (i=0; i<1; i++) { + arm_take_high_v1(); + wait_ms(500); + // pwm_ng_set(&arm.pwm1B, 4095); + arm_take_low_v1(); + wait_ms(500); + arm_take_high_v1(); + wait_ms(500); + arm_take_high_v2(); + wait_ms(500); + arm_take_low_v2(); + wait_ms(500); + arm_take_high_v2(); + wait_ms(500); + arm_intermediate(); + wait_ms(500); +/* arm_intermediate2(); */ +/* wait_ms(250); */ + arm_drop_v2(); + wait_ms(500); + // pwm_ng_set(&arm.pwm1B, -4095); + arm_drop_v1(); + wait_ms(500); + // pwm_ng_set(&arm.pwm1B, 0); + wait_ms(500); + arm_intermediate(); + wait_ms(500); + } +} + +prog_char str_test_arg0[] = "test"; +parse_pgm_token_string_t cmd_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_test_result, arg0, str_test_arg0); + +prog_char help_test[] = "Test func"; +parse_pgm_inst_t cmd_test = { + .f = cmd_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_test_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Arm_Straight */ + +/* this structure is filled when cmd_arm_straight is parsed successfully */ +struct cmd_arm_straight_result { + fixed_string_t arg0; +}; + +/* function called when cmd_arm_straight is parsed successfully */ +static void cmd_arm_straight_parsed(void * parsed_result, void * data) +{ + int32_t pos_shoulder[] = { + -15510, + -17181, + -18852, + -20524, + -22470, + -24416, + -26363, + -28309, + -30255, + -32464, + -34673, + -36881, + -39090, + -41299, + -43080, + -44861, + -46642, + -48423, + -50204, + -51026, + -51849, + -52671, + -53493, + -54316, + -54443, + -54370, + -54398, + }; + /* vitesse servo : 3ff = 114RPM = 233.2 pas/100ms */ + int32_t pos_elbow[] = { + 316, + 301, + 286, + 271, + 261, + 250, + 240, + 230, + 220, + 216, + 212, + 208, + 204, + 200, + 204, + 208, + 212, + 216, + 220, + 230, + 240, + 250, + 261, + 271, + 286, + 301, + 316, + }; + + int8_t i; + int32_t speed_shoulder; + int32_t speed_elbow; + + arm_goto(pos_shoulder[0], pos_elbow[0], 500); + printf("ready\r\n"); + while(uart_recv_nowait(0) == -1); + + /* 50 ms per incr */ + for (i=1; i<26; i++) { + speed_shoulder = pos_shoulder[i] - pos_shoulder[i-1]; + speed_shoulder /= 10; /* period is 5ms */ + if (speed_shoulder < 0) + speed_shoulder = -speed_shoulder; + + speed_elbow = pos_elbow[i] - pos_elbow[i-1]; + speed_elbow *= 0x3ff; + speed_elbow *= 2; + speed_elbow /= 233; + if (speed_elbow < 0) + speed_elbow = -speed_elbow; + +#if 1 + printf("shoulder : %ld, %ld / elbow : %ld, %ld\r\n", + pos_shoulder[i], speed_shoulder, + pos_elbow[i], speed_elbow); +#else + quadramp_set_1st_order_vars(&arm.qr_mot, speed_shoulder, speed_shoulder); + cs_set_consign(&arm.cs_mot, pos_shoulder[i]); + + AX12_write_int(&ax12, ELBOW_AX12, AA_MOVING_SPEED_L, speed_elbow); + AX12_write_int(&ax12, ELBOW_AX12, AA_GOAL_POSITION_L, pos_elbow[i]); + + time_wait_ms(50); +#endif + } +} + +prog_char str_arm_straight_arg0[] = "arm_straight"; +parse_pgm_token_string_t cmd_arm_straight_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_straight_result, arg0, str_arm_straight_arg0); + +prog_char help_arm_straight[] = "Arm_Straight func"; +parse_pgm_inst_t cmd_arm_straight = { + .f = cmd_arm_straight_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_straight, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_straight_arg0, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_baudrate is parsed successfully */ +struct cmd_baudrate_result { + fixed_string_t arg0; + uint32_t arg1; +}; + +/* function called when cmd_baudrate is parsed successfully */ +static void cmd_baudrate_parsed(void * parsed_result, void * data) +{ + struct cmd_baudrate_result *res = parsed_result; + struct uart_config c; + + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); + uart_getconf(1, &c); + c.baudrate = res->arg1; + uart_setconf(1, &c); + printf_P(PSTR("%d %d\r\n"), UBRR1H, UBRR1L); +} + +prog_char str_baudrate_arg0[] = "baudrate"; +parse_pgm_token_string_t cmd_baudrate_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0, str_baudrate_arg0); +parse_pgm_token_num_t cmd_baudrate_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1, UINT32); + +prog_char help_baudrate[] = "Change ax12 baudrate"; +parse_pgm_inst_t cmd_baudrate = { + .f = cmd_baudrate_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_baudrate, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_baudrate_arg0, + (prog_void *)&cmd_baudrate_arg1, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_arm_goto is parsed successfully */ +struct cmd_arm_goto_result { + fixed_string_t arg0; + int32_t arg1; + uint16_t arg2; + uint16_t arg3; +}; + +/* function called when cmd_arm_goto is parsed successfully */ +static void cmd_arm_goto_parsed(void * parsed_result, void * data) +{ + struct cmd_arm_goto_result *res = parsed_result; + arm_goto(res->arg1, res->arg2, res->arg3); +} + +prog_char str_arm_goto_arg0[] = "arm_goto"; +parse_pgm_token_string_t cmd_arm_goto_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_goto_result, arg0, str_arm_goto_arg0); +parse_pgm_token_num_t cmd_arm_goto_arg1 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg1, INT32); +parse_pgm_token_num_t cmd_arm_goto_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg2, UINT16); +parse_pgm_token_num_t cmd_arm_goto_arg3 = TOKEN_NUM_INITIALIZER(struct cmd_arm_goto_result, arg3, UINT16); + +prog_char help_arm_goto[] = "Change arm position (shoulder, elbow, wrist)"; +parse_pgm_inst_t cmd_arm_goto = { + .f = cmd_arm_goto_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_goto, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_goto_arg0, + (prog_void *)&cmd_arm_goto_arg1, + (prog_void *)&cmd_arm_goto_arg2, + (prog_void *)&cmd_arm_goto_arg3, + NULL, + }, +}; + +/**********************************************************/ + +/* this structure is filled when cmd_arm_capture is parsed successfully */ +struct cmd_arm_capture_result { + fixed_string_t arg0; +}; + +/* function called when cmd_arm_capture is parsed successfully */ +static void cmd_arm_capture_parsed(void * parsed_result, void * data) +{ +#ifdef notyet + uint16_t elbow, wrist; + int32_t shoulder; + uint8_t ret = 0; + + ret |= AX12_read_int(&ax12, ELBOW_AX12, AA_PRESENT_POSITION_L, &elbow); + ret |= AX12_read_int(&ax12, WRIST_AX12, AA_PRESENT_POSITION_L, &wrist); + shoulder = encoders_microb_get_value((void *)ARM_ENC); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%ld %d %d\r\n"), shoulder, elbow, wrist); +#endif +} + +prog_char str_arm_capture_arg0[] = "arm_capture"; +parse_pgm_token_string_t cmd_arm_capture_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_arm_capture_result, arg0, str_arm_capture_arg0); + +prog_char help_arm_capture[] = "Change arm position (shoulder, elbow, wrist)"; +parse_pgm_inst_t cmd_arm_capture = { + .f = cmd_arm_capture_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_arm_capture, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_arm_capture_arg0, + NULL, + }, +}; +/**********************************************************/ +/* Uint16 */ + + +/* this structure is filled when cmd_uint16_read is parsed successfully */ +struct cmd_uint16_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint16_t val; +}; + +/* function called when cmd_uint16_read is parsed successfully */ +static void cmd_uint16_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint16_t val; + uint8_t addr = addr_from_string(res->arg1); + ret = AX12_read_int(&ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.4x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint16_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint16_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0); +prog_char str_uint16_arg1[] = "moving_speed#model#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#down_calibration#up_calibration#torque_limit#" + "position#speed#load#punch"; +parse_pgm_token_string_t cmd_uint16_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1); +parse_pgm_token_num_t cmd_uint16_num = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, num, UINT8); + +prog_char help_uint16_read[] = "Read uint16 value (type, num)"; +parse_pgm_inst_t cmd_uint16_read = { + .f = cmd_uint16_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0, + (prog_void *)&cmd_uint16_arg1, + (prog_void *)&cmd_uint16_num, + NULL, + }, +}; + +/* function called when cmd_uint16_write is parsed successfully */ +static void cmd_uint16_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint16_result *res = parsed_result; + uint8_t ret; + uint8_t addr = addr_from_string(res->arg1); + printf_P(PSTR("writing %s: %d [0x%.4x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_int(&ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint16_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint16_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg0, str_uint16_arg0_w); +prog_char str_uint16_arg1_w[] = "moving_speed#goal_pos#cw_angle_limit#ccw_angle_limit#" + "max_torque#torque_limit#punch"; +parse_pgm_token_string_t cmd_uint16_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint16_result, arg1, str_uint16_arg1_w); +parse_pgm_token_num_t cmd_uint16_val = TOKEN_NUM_INITIALIZER(struct cmd_uint16_result, val, UINT16); + +prog_char help_uint16_write[] = "Write uint16 value (write, num, val)"; +parse_pgm_inst_t cmd_uint16_write = { + .f = cmd_uint16_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint16_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint16_arg0_w, + (prog_void *)&cmd_uint16_arg1_w, + (prog_void *)&cmd_uint16_num, + (prog_void *)&cmd_uint16_val, + NULL, + }, +}; + +/**********************************************************/ +/* Uint8 */ + + +/* this structure is filled when cmd_uint8_read is parsed successfully */ +struct cmd_uint8_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint8_t num; + uint8_t val; +}; + +/* function called when cmd_uint8_read is parsed successfully */ +static void cmd_uint8_read_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t ret; + uint8_t val; + uint8_t addr = addr_from_string(res->arg1); + + ret = AX12_read_byte(&ax12, res->num, addr, &val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); + printf_P(PSTR("%s: %d [0x%.2x]\r\n"), res->arg1, val, val); +} + +prog_char str_uint8_arg0[] = "read"; +parse_pgm_token_string_t cmd_uint8_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0); +prog_char str_uint8_arg1[] = "id#firmware#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "voltage#temp#reginst#moving#lock"; +parse_pgm_token_string_t cmd_uint8_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1); +parse_pgm_token_num_t cmd_uint8_num = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, num, UINT8); + +prog_char help_uint8_read[] = "Read uint8 value (type, num)"; +parse_pgm_inst_t cmd_uint8_read = { + .f = cmd_uint8_read_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_read, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0, + (prog_void *)&cmd_uint8_arg1, + (prog_void *)&cmd_uint8_num, + NULL, + }, +}; + +/* function called when cmd_uint8_write is parsed successfully */ +static void cmd_uint8_write_parsed(void * parsed_result, void * data) +{ + struct cmd_uint8_result *res = parsed_result; + uint8_t addr = addr_from_string(res->arg1); + uint8_t ret; + printf_P(PSTR("writing %s: %d [0x%.2x]\r\n"), res->arg1, + res->val, res->val); + ret = AX12_write_byte(&ax12, res->num, addr, res->val); + if (ret) + printf_P(PSTR("AX12 error %.2x!\r\n"), ret); +} + +prog_char str_uint8_arg0_w[] = "write"; +parse_pgm_token_string_t cmd_uint8_arg0_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg0, str_uint8_arg0_w); +prog_char str_uint8_arg1_w[] = "id#baudrate#delay#high_lim_temp#" + "low_lim_volt#high_lim_volt#status_return#alarm_led#" + "alarm_shutdown#torque_enable#led#cw_comp_margin#" + "ccw_comp_margin#cw_comp_slope#ccw_comp_slope#" + "reginst#lock"; +parse_pgm_token_string_t cmd_uint8_arg1_w = TOKEN_STRING_INITIALIZER(struct cmd_uint8_result, arg1, str_uint8_arg1_w); +parse_pgm_token_num_t cmd_uint8_val = TOKEN_NUM_INITIALIZER(struct cmd_uint8_result, val, UINT8); + +prog_char help_uint8_write[] = "Write uint8 value (write, num, val)"; +parse_pgm_inst_t cmd_uint8_write = { + .f = cmd_uint8_write_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_uint8_write, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_uint8_arg0_w, + (prog_void *)&cmd_uint8_arg1_w, + (prog_void *)&cmd_uint8_num, + (prog_void *)&cmd_uint8_val, + NULL, + }, +}; + +/**********************************************************/ +/* Encoders tests */ + +/* this structure is filled when cmd_encoders is parsed successfully */ +struct cmd_encoders_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_encoders is parsed successfully */ +static void cmd_encoders_parsed(void * parsed_result, void * data) +{ +#ifdef notyet + while(uart_recv_nowait(0) == -1) { + printf_P(PSTR("% .8ld % .8ld % .8ld % .8ld\r\n"), + encoders_microb_get_value((void *)0), + encoders_microb_get_value((void *)1), + encoders_microb_get_value((void *)2), + encoders_microb_get_value((void *)3)); + wait_ms(100); + } +#endif +} + +prog_char str_encoders_arg0[] = "encoders"; +parse_pgm_token_string_t cmd_encoders_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg0, str_encoders_arg0); +prog_char str_encoders_arg1[] = "show"; +parse_pgm_token_string_t cmd_encoders_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg1, str_encoders_arg1); + +prog_char help_encoders[] = "Show encoders values"; +parse_pgm_inst_t cmd_encoders = { + .f = cmd_encoders_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_encoders, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_encoders_arg0, + (prog_void *)&cmd_encoders_arg1, + NULL, + }, +}; + +/**********************************************************/ +/* Pwms tests */ + +/* this structure is filled when cmd_pwm is parsed successfully */ +struct cmd_pwm_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t arg2; +}; + +/* function called when cmd_pwm is parsed successfully */ +static void cmd_pwm_parsed(void * parsed_result, void * data) +{ + void * pwm_ptr = NULL; + struct cmd_pwm_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("1(2A)"))) + pwm_ptr = &arm.pwm1_2A; + else if (!strcmp_P(res->arg1, PSTR("2(1A)"))) + pwm_ptr = &arm.pwm2_1A; + else if (!strcmp_P(res->arg1, PSTR("3(1B)"))) + pwm_ptr = &arm.pwm3_1B; + else if (!strcmp_P(res->arg1, PSTR("4(1C)"))) + pwm_ptr = &arm.pwm4_1C; + + else if (!strcmp_P(res->arg1, PSTR("s1(3A)"))) + pwm_ptr = &arm.servo1; + else if (!strcmp_P(res->arg1, PSTR("s2(3B)"))) + pwm_ptr = &arm.servo2; + else if (!strcmp_P(res->arg1, PSTR("s3(3C)"))) + pwm_ptr = &arm.servo3; + else if (!strcmp_P(res->arg1, PSTR("s4(5A)"))) + pwm_ptr = &arm.servo4; + else if (!strcmp_P(res->arg1, PSTR("s5(5B)"))) + pwm_ptr = &arm.servo5; + else if (!strcmp_P(res->arg1, PSTR("s6(5C)"))) + pwm_ptr = &arm.servo6; + + if (pwm_ptr) + pwm_ng_set(pwm_ptr, res->arg2); + + printf_P(PSTR("done\r\n")); +} + +prog_char str_pwm_arg0[] = "pwm"; +parse_pgm_token_string_t cmd_pwm_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg0, str_pwm_arg0); +prog_char str_pwm_arg1[] = "1(2A)#2(1A)#3(1B)#4(1C)#s1(3A)#s2(3B)#s3(3C)#s4(5A)#s5(5B)#s6(5C)"; +parse_pgm_token_string_t cmd_pwm_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pwm_result, arg1, str_pwm_arg1); +parse_pgm_token_num_t cmd_pwm_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_pwm_result, arg2, INT16); + +prog_char help_pwm[] = "Set pwm values [-4096 ; 4095]"; +parse_pgm_inst_t cmd_pwm = { + .f = cmd_pwm_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pwm, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pwm_arg0, + (prog_void *)&cmd_pwm_arg1, + (prog_void *)&cmd_pwm_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Gains for control system */ + +/* this structure is filled when cmd_gain is parsed successfully */ +struct cmd_gain_result { + fixed_string_t arg0; + fixed_string_t arg1; + int16_t p; + int16_t i; + int16_t d; +}; + +/* function called when cmd_gain is parsed successfully */ +static void cmd_gain_parsed(void * parsed_result, void * data) +{ + struct cmd_gain_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + pid_set_gains(&arm.pid_mot, res->p, res->i, res->d); + } + /* else it is a "show" */ + + printf_P(PSTR("arm %d %d %d\r\n"), + pid_get_gain_P(&arm.pid_mot), + pid_get_gain_I(&arm.pid_mot), + pid_get_gain_D(&arm.pid_mot)); +} + +prog_char str_gain_arg0[] = "gain"; +parse_pgm_token_string_t cmd_gain_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, arg0, str_gain_arg0); +prog_char str_gain_arg1[] = "arm"; +parse_pgm_token_string_t cmd_gain_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, arg1, str_gain_arg1); +parse_pgm_token_num_t cmd_gain_p = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, p, INT16); +parse_pgm_token_num_t cmd_gain_i = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, i, INT16); +parse_pgm_token_num_t cmd_gain_d = TOKEN_NUM_INITIALIZER(struct cmd_gain_result, d, INT16); + +prog_char help_gain[] = "Set gain values for PID"; +parse_pgm_inst_t cmd_gain = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_gain_arg1, + (prog_void *)&cmd_gain_p, + (prog_void *)&cmd_gain_i, + (prog_void *)&cmd_gain_d, + NULL, + }, +}; + +/* show */ + +prog_char str_gain_show_arg[] = "show"; +parse_pgm_token_string_t cmd_gain_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_gain_result, arg1, str_gain_show_arg); + +prog_char help_gain_show[] = "Show gain values for PID"; +parse_pgm_inst_t cmd_gain_show = { + .f = cmd_gain_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_gain_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_gain_arg0, + (prog_void *)&cmd_gain_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Speeds for control system */ + +/* this structure is filled when cmd_speed is parsed successfully */ +struct cmd_speed_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint16_t s; +}; + +/* function called when cmd_speed is parsed successfully */ +static void cmd_speed_parsed(void * parsed_result, void * data) +{ +#if 0 + struct cmd_speed_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + ramp_set_vars(&ext.r_b, res->s, res->s); /* set speed */ + } + + printf_P(PSTR("arm %lu\r\n"), + ext.r_b.var_pos); +#else + printf_P(PSTR("DISABLED FOR NOW\r\n")); +#endif +} + +prog_char str_speed_arg0[] = "speed"; +parse_pgm_token_string_t cmd_speed_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, arg0, str_speed_arg0); +prog_char str_speed_arg1[] = "arm#show"; +parse_pgm_token_string_t cmd_speed_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, arg1, str_speed_arg1); +parse_pgm_token_num_t cmd_speed_s = TOKEN_NUM_INITIALIZER(struct cmd_speed_result, s, UINT16); + +prog_char help_speed[] = "Set speed values for ramp filter"; +parse_pgm_inst_t cmd_speed = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_speed_arg1, + (prog_void *)&cmd_speed_s, + NULL, + }, +}; + +/* show */ + +prog_char str_speed_show_arg[] = "show"; +parse_pgm_token_string_t cmd_speed_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_speed_result, arg1, str_speed_show_arg); + +prog_char help_speed_show[] = "Show speed values for ramp filter"; +parse_pgm_inst_t cmd_speed_show = { + .f = cmd_speed_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_speed_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_speed_arg0, + (prog_void *)&cmd_speed_show_arg, + NULL, + }, +}; + + +/**********************************************************/ +/* Pos for control system */ + +/* this structure is filled when cmd_pos is parsed successfully */ +struct cmd_pos_result { + fixed_string_t arg0; + fixed_string_t arg1; + int32_t p; +}; + +/* function called when cmd_pos is parsed successfully */ +static void cmd_pos_parsed(void * parsed_result, void * data) +{ + struct cmd_pos_result * res = parsed_result; + // uint8_t i; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + cs_set_consign(&arm.cs_mot, res->p); + } + +#if 0 + for (i=0; i<50; i++) { + printf("%ld %ld %ld\r\n", + pid_get_value_in(&arm.pid_mot), + pid_get_value_out(&arm.pid_mot), + pid_get_value_D(&arm.pid_mot) + ); + } +#endif +} + +prog_char str_pos_arg0[] = "pos"; +parse_pgm_token_string_t cmd_pos_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_pos_result, arg0, str_pos_arg0); +prog_char str_pos_arg1[] = "arm"; +parse_pgm_token_string_t cmd_pos_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_pos_result, arg1, str_pos_arg1); +parse_pgm_token_num_t cmd_pos_p = TOKEN_NUM_INITIALIZER(struct cmd_pos_result, p, INT32); + +prog_char help_pos[] = "Set pos value"; +parse_pgm_inst_t cmd_pos = { + .f = cmd_pos_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_pos, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_pos_arg0, + (prog_void *)&cmd_pos_arg1, + (prog_void *)&cmd_pos_p, + NULL, + }, +}; + + +/**********************************************************/ +/* Events on/off */ + +/* this structure is filled when cmd_event is parsed successfully */ +struct cmd_event_result { + fixed_string_t arg0; + fixed_string_t arg1; + fixed_string_t arg2; +}; + +/* function called when cmd_event is parsed successfully */ +static void cmd_event_parsed(void * parsed_result, void * data) +{ +#ifdef notyet + u08 bit=0; + + struct cmd_event_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("cs"))) { + if (!strcmp_P(res->arg2, PSTR("on"))) { + pwm_ng_set(ARM_MOT_PWM, 0); + printf_P(PSTR("ax12 will start\r\n")); + while(uart_recv_nowait(0) == -1); + AX12_write_int(&ax12,0xFE,AA_TORQUE_ENABLE,0x1); + AX12_write_int(&ax12, ELBOW_AX12, AA_GOAL_POSITION_L, 660); + AX12_write_int(&ax12, WRIST_AX12, AA_GOAL_POSITION_L, 613); + printf_P(PSTR("Set the arm to 0\r\n")); + while(uart_recv_nowait(0) == -1); + // encoders_microb_set_value(ARM_ENC, 0); + } + bit = CS_ON; + } +/* else if (!strcmp_P(res->arg1, PSTR("catapult"))) */ +/* bit = CATAPULT_CS_ON; */ + + if (!strcmp_P(res->arg2, PSTR("on"))) + arm.flags |= bit; + else if (!strcmp_P(res->arg2, PSTR("off"))) + arm.flags &= (~bit); + printf_P(PSTR("%s is %s\r\n"), res->arg1, + (bit & arm.flags) ? "on":"off"); +#endif +} + +prog_char str_event_arg0[] = "event"; +parse_pgm_token_string_t cmd_event_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg0); +prog_char str_event_arg1[] = "cs"; +parse_pgm_token_string_t cmd_event_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg1, str_event_arg1); +prog_char str_event_arg2[] = "on#off#show"; +parse_pgm_token_string_t cmd_event_arg2 = TOKEN_STRING_INITIALIZER(struct cmd_event_result, arg2, str_event_arg2); + +prog_char help_event[] = "Enable/disable events"; +parse_pgm_inst_t cmd_event = { + .f = cmd_event_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_event, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_event_arg0, + (prog_void *)&cmd_event_arg1, + (prog_void *)&cmd_event_arg2, + NULL, + }, +}; + +/**********************************************************/ +/* Maximums for control system */ + +/* this structure is filled when cmd_maximum is parsed successfully */ +struct cmd_maximum_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint32_t in; + uint32_t i; + uint32_t out; +}; + +/* function called when cmd_maximum is parsed successfully */ +static void cmd_maximum_parsed(void * parsed_result, void * data) +{ + struct cmd_maximum_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + pid_set_maximums(&arm.pid_mot, res->in, res->i, res->out); + } + /* else it is a "show" */ + + printf_P(PSTR("maximum arm %lu %lu %lu\r\n"), + pid_get_max_in(&arm.pid_mot), + pid_get_max_I(&arm.pid_mot), + pid_get_max_out(&arm.pid_mot)); +} + +prog_char str_maximum_arg0[] = "maximum"; +parse_pgm_token_string_t cmd_maximum_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, arg0, str_maximum_arg0); +prog_char str_maximum_arg1[] = "arm"; +parse_pgm_token_string_t cmd_maximum_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, arg1, str_maximum_arg1); +parse_pgm_token_num_t cmd_maximum_in = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, in, UINT32); +parse_pgm_token_num_t cmd_maximum_i = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, i, UINT32); +parse_pgm_token_num_t cmd_maximum_out = TOKEN_NUM_INITIALIZER(struct cmd_maximum_result, out, UINT32); + +prog_char help_maximum[] = "Set maximum values for PID (in, I, out)"; +parse_pgm_inst_t cmd_maximum = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_maximum_arg1, + (prog_void *)&cmd_maximum_in, + (prog_void *)&cmd_maximum_i, + (prog_void *)&cmd_maximum_out, + NULL, + }, +}; + +/* show */ + +prog_char str_maximum_show_arg[] = "show"; +parse_pgm_token_string_t cmd_maximum_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_maximum_result, arg1, str_maximum_show_arg); + +prog_char help_maximum_show[] = "Show maximum values for PID"; +parse_pgm_inst_t cmd_maximum_show = { + .f = cmd_maximum_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_maximum_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_maximum_arg0, + (prog_void *)&cmd_maximum_show_arg, + NULL, + }, +}; + +/**********************************************************/ +/* Quadramp for control system */ + +/* this structure is filled when cmd_quadramp is parsed successfully */ +struct cmd_quadramp_result { + fixed_string_t arg0; + fixed_string_t arg1; + uint32_t ap; + uint32_t an; + uint32_t sp; + uint32_t sn; +}; + +/* function called when cmd_quadramp is parsed successfully */ +static void cmd_quadramp_parsed(void * parsed_result, void * data) +{ + struct cmd_quadramp_result * res = parsed_result; + + if (!strcmp_P(res->arg1, PSTR("arm"))) { + quadramp_set_1st_order_vars(&arm.qr_mot, res->sp, res->sn); + quadramp_set_2nd_order_vars(&arm.qr_mot, res->ap, res->an); + } +/* else if (!strcmp_P(res->arg1, PSTR("distance"))) { */ +/* quadramp_set_1st_order_vars(&arm.qr_d, res->sp, res->sn); */ +/* quadramp_set_2nd_order_vars(&arm.qr_d, res->ap, res->an); */ +/* } */ + /* else it's a "show" */ + + printf_P(PSTR("quadramp arm %ld %ld %ld %ld\r\n"), + arm.qr_mot.var_2nd_ord_pos, + arm.qr_mot.var_2nd_ord_neg, + arm.qr_mot.var_1st_ord_pos, + arm.qr_mot.var_1st_ord_neg); +} + +prog_char str_quadramp_arg0[] = "quadramp"; +parse_pgm_token_string_t cmd_quadramp_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, arg0, str_quadramp_arg0); +prog_char str_quadramp_arg1[] = "arm"; +parse_pgm_token_string_t cmd_quadramp_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, arg1, str_quadramp_arg1); +parse_pgm_token_num_t cmd_quadramp_ap = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, ap, UINT32); +parse_pgm_token_num_t cmd_quadramp_an = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, an, UINT32); +parse_pgm_token_num_t cmd_quadramp_sp = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sp, UINT32); +parse_pgm_token_num_t cmd_quadramp_sn = TOKEN_NUM_INITIALIZER(struct cmd_quadramp_result, sn, UINT32); + +prog_char help_quadramp[] = "Set quadramp values (acc+, acc-, speed+, speed-)"; +parse_pgm_inst_t cmd_quadramp = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_quadramp_arg1, + (prog_void *)&cmd_quadramp_ap, + (prog_void *)&cmd_quadramp_an, + (prog_void *)&cmd_quadramp_sp, + (prog_void *)&cmd_quadramp_sn, + + NULL, + }, +}; + +/* show */ + +prog_char str_quadramp_show_arg[] = "show"; +parse_pgm_token_string_t cmd_quadramp_show_arg = TOKEN_STRING_INITIALIZER(struct cmd_quadramp_result, arg1, str_quadramp_show_arg); + +prog_char help_quadramp_show[] = "Get quadramp values for control system"; +parse_pgm_inst_t cmd_quadramp_show = { + .f = cmd_quadramp_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_quadramp_show, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_quadramp_arg0, + (prog_void *)&cmd_quadramp_show_arg, + NULL, + }, +}; + + +/**********************************************************/ + + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_spi_test, + (parse_pgm_inst_t *)&cmd_bootloader, + (parse_pgm_inst_t *)&cmd_ax12_stress, + (parse_pgm_inst_t *)&cmd_test, + (parse_pgm_inst_t *)&cmd_arm_straight, + (parse_pgm_inst_t *)&cmd_baudrate, + (parse_pgm_inst_t *)&cmd_arm_goto, + (parse_pgm_inst_t *)&cmd_arm_capture, + (parse_pgm_inst_t *)&cmd_uint16_read, + (parse_pgm_inst_t *)&cmd_uint16_write, + (parse_pgm_inst_t *)&cmd_uint8_read, + (parse_pgm_inst_t *)&cmd_uint8_write, + (parse_pgm_inst_t *)&cmd_encoders, + (parse_pgm_inst_t *)&cmd_pwm, + (parse_pgm_inst_t *)&cmd_gain, + (parse_pgm_inst_t *)&cmd_gain_show, + (parse_pgm_inst_t *)&cmd_speed, + (parse_pgm_inst_t *)&cmd_speed_show, + (parse_pgm_inst_t *)&cmd_pos, + (parse_pgm_inst_t *)&cmd_event, + (parse_pgm_inst_t *)&cmd_maximum, + (parse_pgm_inst_t *)&cmd_maximum_show, + (parse_pgm_inst_t *)&cmd_quadramp, + (parse_pgm_inst_t *)&cmd_quadramp_show, + + NULL, +}; diff --git a/projects/microb2009/tests/atm2560/i2c_config.h b/projects/microb2009/tests/atm2560/i2c_config.h new file mode 100644 index 0000000..26924f3 --- /dev/null +++ b/projects/microb2009/tests/atm2560/i2c_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: i2c_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + + +#define I2C_BITRATE 1 // divider dor i2c baudrate, see TWBR in doc +#define I2C_PRESCALER 3 // prescaler config, rate = 2^(n*2) + +/* Size of transmission buffer */ +#define I2C_SEND_BUFFER_SIZE 16 + +/* Size of reception buffer */ +#define I2C_RECV_BUFFER_SIZE 16 diff --git a/projects/microb2009/tests/atm2560/main.c b/projects/microb2009/tests/atm2560/main.c new file mode 100755 index 0000000..1927bc6 --- /dev/null +++ b/projects/microb2009/tests/atm2560/main.c @@ -0,0 +1,270 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <parse.h> +#include <rdline.h> +#include <ax12.h> +#include <uart.h> +#include <pwm_ng.h> +#include <timer.h> +#include <scheduler.h> +#include <pid.h> +#include <time.h> +#include <quadramp.h> +#include <control_system_manager.h> + +#include "main.h" + +/* ---- with 16 Mhz quartz + * CKSEL 3-0 : 0110 + * SUT 1-0 : 00 + * CKDIV8 : 1 + * ---- bootloader + * BOOTZ 1-0 : 01 (4K bootloader) + * BOOTRST : 0 (reset on bootloader) + */ + +/* for cmdline interface */ +struct rdline rdl; +char prompt[RDLINE_PROMPT_SIZE]; +extern parse_pgm_ctx_t main_ctx[]; + +AX12 ax12; +struct arm arm; + + +/******** For cmdline. See in commands.c for the list of commands. */ +static void write_char(char c) +{ + uart_send(3, c); +} + +static void +valid_buffer(const char * buf, uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char * buf, char * dstbuf, uint8_t dstsize, + int16_t * state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + + +/***********************/ + +void do_led_blink(void * dummy) +{ +#if 1 /* simple blink */ + static uint8_t a=0; + + if(a) + LED1_ON(); + else + LED1_OFF(); + + a = !a; +#endif +} + +/* called every 5 ms */ +static void do_cs(void * dummy) +{ + if (arm.flags & CS_ON) + cs_manage(&arm.cs_mot); +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + + cpt++; + sei(); + + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +/* sending "pop" on uart0 resets the robot */ +static void emergency(char c) +{ + static uint8_t i = 0; + + if ((i == 0 && c == 'p') || + (i == 1 && c == 'o') || + (i == 2 && c == 'p')) + i++; + else if ( !(i == 1 && c == 'p') ) + i = 0; + if (i == 3) + reset(); +} + +int main(void) +{ + int c; + const char *history, *buffer; + int8_t ret, same = 0; + + /* brake */ + DDRJ = 0xF0; + PORTJ = 0; + + /* CPLD on XXX */ + + /* LEDS */ + DDRJ |= 0x0c; + DDRL = 0xc0; + LED1_OFF(); + memset(&arm, 0, sizeof(struct arm)); + + /* PID */ + pid_init(&arm.pid_mot); + pid_set_gains(&arm.pid_mot, 20, 0, 0); + pid_set_maximums(&arm.pid_mot, 0, 30000, 4095); + pid_set_out_shift(&arm.pid_mot, 6); + pid_set_derivate_filter(&arm.pid_mot, 6); + + /* QUADRAMP */ + quadramp_init(&arm.qr_mot); + quadramp_set_1st_order_vars(&arm.qr_mot, 800, 800); /* set speed */ + quadramp_set_2nd_order_vars(&arm.qr_mot, 20, 20); /* set accel */ + + /* CS */ +/* cs_init(&arm.cs_mot); */ +/* cs_set_consign_filter(&arm.cs_mot, quadramp_do_filter, &arm.qr_mot); */ +/* cs_set_correct_filter(&arm.cs_mot, pid_do_filter, &arm.pid_mot); */ +/* cs_set_process_in(&arm.cs_mot, pwm_ng_set, ARM_MOT_PWM); */ +/* cs_set_process_out(&arm.cs_mot, encoders_microb_get_value, ARM_ENC); */ +/* cs_set_consign(&arm.cs_mot, 0); */ + +#if 0 + /* SPI */ + spi_init(SPI_MODE_MASTER, SPI_FORMAT_2, SPI_CLK_RATE_16); + spi_set_data_order(SPI_MSB_FIRST); + spi_register_ss_line(&SS_PORT, SS_BIT); +#endif + + + uart_init(); + fdevopen(uart3_dev_send, uart3_dev_recv); + uart_register_rx_event(3, emergency); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* SCHEDULER */ + scheduler_init(); + scheduler_add_periodical_event_priority(do_led_blink, NULL, + 100000L / SCHEDULER_UNIT, + LED_PRIO); + + /* PWM */ + PWM_NG_TIMER_8BITS_INIT_B(2, TIMER_8_MODE_PWM, + TIMER2_PRESCALER_DIV_1); + PWM_NG_TIMER_16BITS_INIT(1, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_1); + + PWM_NG_INIT8_B(&arm.pwm1_2A, 2, A, 8, PWM_NG_MODE_SIGNED, + &PORTD, 4); + PWM_NG_INIT16(&arm.pwm2_1A, 1, A, 10, PWM_NG_MODE_SIGNED, + &PORTD, 5); + PWM_NG_INIT16(&arm.pwm3_1B, 1, B, 10, PWM_NG_MODE_SIGNED, + &PORTD, 6); + PWM_NG_INIT16(&arm.pwm4_1C, 1, C, 10, PWM_NG_MODE_SIGNED, + &PORTD, 7); + + + /* servos */ + PWM_NG_TIMER_16BITS_INIT(3, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + /* 1 et 2 ko XXX */ + PWM_NG_INIT16(&arm.servo1, 3, A, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&arm.servo2, 3, B, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&arm.servo3, 3, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_TIMER_16BITS_INIT(5, TIMER_16_MODE_PWM_10, + TIMER1_PRESCALER_DIV_256); + PWM_NG_INIT16(&arm.servo4, 5, A, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&arm.servo5, 5, B, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + PWM_NG_INIT16(&arm.servo6, 5, C, 10, PWM_NG_MODE_NORMAL, + NULL, 0); + + + /* CS EVENT */ + scheduler_add_periodical_event_priority(do_cs, NULL, + 5000L / SCHEDULER_UNIT, + CS_PRIO); + /* TIME */ + time_init(TIME_PRIO); + + printf_P(PSTR("Coucou\r\n")); + sei(); + + rdline_init(&rdl, write_char, valid_buffer, complete_buffer); + snprintf(prompt, sizeof(prompt), "atm2560 > "); + rdline_newline(&rdl, prompt); + + + while (1) { + c = uart_recv_nowait(3); + if (c == -1) + continue; + ret = rdline_char_in(&rdl, c); + if (ret != 2 && ret != 0) { + buffer = rdline_get_buffer(&rdl); + history = rdline_get_history_item(&rdl, 0); + if (history) { + same = !memcmp(buffer, history, strlen(history)) && + buffer[strlen(history)] == '\n'; + } + else + same = 0; + if (strlen(buffer) > 1 && !same) + rdline_add_history(&rdl, buffer); + rdline_newline(&rdl, prompt); + } + } + + return 0; +} diff --git a/projects/microb2009/tests/atm2560/main.h b/projects/microb2009/tests/atm2560/main.h new file mode 100755 index 0000000..86bc075 --- /dev/null +++ b/projects/microb2009/tests/atm2560/main.h @@ -0,0 +1,57 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +#define LED1_ON() sbi(PORTJ, 2) +#define LED1_OFF() cbi(PORTJ, 2) + +#define LED2_ON() sbi(PORTJ, 3) +#define LED2_OFF() cbi(PORTJ, 3) + +#define ARM_MOT_PWM (&arm.pwm1A) +#define ARM_ENC ((void *)0) + +#define LED_PRIO 170 +#define TIME_PRIO 160 +#define CS_PRIO 150 + +struct arm { +#define CS_ON 1 + uint8_t flags; + struct cs cs_mot; + struct pid_filter pid_mot; + struct quadramp_filter qr_mot; + + /* motors */ + struct pwm_ng pwm1_2A; + struct pwm_ng pwm2_1A; + struct pwm_ng pwm3_1B; + struct pwm_ng pwm4_1C; + + /* servos */ + struct pwm_ng servo1; + struct pwm_ng servo2; + struct pwm_ng servo3; + struct pwm_ng servo4; + struct pwm_ng servo5; + struct pwm_ng servo6; +}; + +extern struct arm arm; diff --git a/projects/microb2009/tests/atm2560/pid_config.h b/projects/microb2009/tests/atm2560/pid_config.h new file mode 100755 index 0000000..fa95f08 --- /dev/null +++ b/projects/microb2009/tests/atm2560/pid_config.h @@ -0,0 +1,30 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * + */ + +#ifndef PID_CONFIG_H +#define PID_CONFIG_H + +/** the derivate term can be filtered to remove the noise. This value + * is the maxium sample count to keep in memory to do this + * filtering. For an instance of pid, this count is defined o*/ +#define PID_DERIVATE_FILTER_MAX_SIZE 4 + +#endif diff --git a/projects/microb2009/tests/atm2560/rdline_config.h b/projects/microb2009/tests/atm2560/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/atm2560/scheduler_config.h b/projects/microb2009/tests/atm2560/scheduler_config.h new file mode 100755 index 0000000..7583358 --- /dev/null +++ b/projects/microb2009/tests/atm2560/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 7 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/microb2009/tests/atm2560/spi_config.h b/projects/microb2009/tests/atm2560/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/microb2009/tests/atm2560/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/microb2009/tests/atm2560/time_config.h b/projects/microb2009/tests/atm2560/time_config.h new file mode 100755 index 0000000..14db608 --- /dev/null +++ b/projects/microb2009/tests/atm2560/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 25000l diff --git a/projects/microb2009/tests/atm2560/timer_config.h b/projects/microb2009/tests/atm2560/timer_config.h new file mode 100755 index 0000000..47d9f18 --- /dev/null +++ b/projects/microb2009/tests/atm2560/timer_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 diff --git a/projects/microb2009/tests/atm2560/uart_config.h b/projects/microb2009/tests/atm2560/uart_config.h new file mode 100644 index 0000000..b78e7ab --- /dev/null +++ b/projects/microb2009/tests/atm2560/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART3 definitions + */ + +/* compile uart3 fonctions, undefine it to pass compilation */ +#define UART3_COMPILE + +/* enable uart3 if == 1, disable if == 0 */ +#define UART3_ENABLED 1 + +/* enable uart3 interrupts if == 1, disable if == 0 */ +#define UART3_INTERRUPT_ENABLED 1 + +#define UART3_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART3_USE_DOUBLE_SPEED 1 +//#define UART3_USE_DOUBLE_SPEED 1 + +#define UART3_RX_FIFO_SIZE 4 +#define UART3_TX_FIFO_SIZE 4 +//#define UART3_NBITS 5 +//#define UART3_NBITS 6 +//#define UART3_NBITS 7 +#define UART3_NBITS 8 +//#define UART3_NBITS 9 + +#define UART3_PARITY UART_PARTITY_NONE +//#define UART3_PARITY UART_PARTITY_ODD +//#define UART3_PARITY UART_PARTITY_EVEN + +#define UART3_STOP_BIT UART_STOP_BITS_1 +//#define UART3_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif + diff --git a/projects/microb2009/tests/bootloader/.config b/projects/microb2009/tests/bootloader/.config new file mode 100644 index 0000000..f46e9c5 --- /dev/null +++ b/projects/microb2009/tests/bootloader/.config @@ -0,0 +1,270 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_MCU_ATMEGA2560=y +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# + +# +# Some radio devices require SPI to be activated +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/microb2009/tests/bootloader/CVS/Entries b/projects/microb2009/tests/bootloader/CVS/Entries new file mode 100644 index 0000000..4426fad --- /dev/null +++ b/projects/microb2009/tests/bootloader/CVS/Entries @@ -0,0 +1,7 @@ +/.config/1.2/Fri Feb 20 21:10:01 2009// +/Makefile/1.2/Fri Jan 30 20:38:49 2009// +/error_config.h/1.1/Sat Jan 3 16:19:30 2009// +/main.c/1.2/Fri Feb 20 21:10:01 2009// +/rdline_config.h/1.1/Fri Feb 20 21:10:01 2009// +/uart_config.h/1.2/Fri Feb 20 21:10:01 2009// +D diff --git a/projects/microb2009/tests/bootloader/CVS/Repository b/projects/microb2009/tests/bootloader/CVS/Repository new file mode 100644 index 0000000..e24c638 --- /dev/null +++ b/projects/microb2009/tests/bootloader/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests/bootloader diff --git a/projects/microb2009/tests/bootloader/CVS/Root b/projects/microb2009/tests/bootloader/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/bootloader/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/bootloader/CVS/Template b/projects/microb2009/tests/bootloader/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/bootloader/Makefile b/projects/microb2009/tests/bootloader/Makefile new file mode 100755 index 0000000..12440bf --- /dev/null +++ b/projects/microb2009/tests/bootloader/Makefile @@ -0,0 +1,36 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. +# VALUE, absolute or relative path : example ../.. # + +CFLAGS += -Werror +# atm128 +# address is 0xf000 (in words) +# LDFLAGS += -Wl,--section-start=.text=1e000 + +# atm2560 +# address is 0x1f800 (in words) +LDFLAGS += -Wl,--section-start=.text=3f000 + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/tests/bootloader/error_config.h b/projects/microb2009/tests/bootloader/error_config.h new file mode 100644 index 0000000..4125dcf --- /dev/null +++ b/projects/microb2009/tests/bootloader/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2009-01-03 16:19:30 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/tests/bootloader/main.c b/projects/microb2009/tests/bootloader/main.c new file mode 100755 index 0000000..a62171a --- /dev/null +++ b/projects/microb2009/tests/bootloader/main.c @@ -0,0 +1,217 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.2 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +/* + * A simple bootloader example. + */ + +#include <aversive.h> +#include <aversive/wait.h> +#include <aversive/pgmspace.h> +#include <uart.h> + +#include <stdlib.h> +#include <string.h> +#include <util/crc16.h> +#include <avr/boot.h> + +#if defined __AVR_ATmega128__ +#define UARTNUM 0 +#elif defined __AVR_ATmega2560__ +#define UARTNUM 3 +#endif + + +#define NOECHO + +#ifdef NOECHO +#define echo(c) do {} while(0) +#else +#define echo(c) uart_send(UARTNUM, c) +#endif + +static void bootloader_puts(const char *buf) +{ + while (*buf) + uart_send(UARTNUM, *(buf++)); +} + +static uint32_t bootloader_query_hex(void) +{ + char buf[8]; + uint8_t i=0; + int c; + + memset(buf, 0, sizeof(buf)); + while (1) { + while ((c=uart_recv_nowait(UARTNUM)) == -1); + if (i >= sizeof(buf) - 1) + continue; + if (c == '\n' || c == '\r') { + echo('\r'); + echo('\n'); + break; + } + echo(c); + buf[i++] = c; + } + return strtol(buf, NULL, 16); +} + +static void launch_app(void) +{ + bootloader_puts("BOOT\r\n"); + wait_ms(500); + MCUCR = (1 << IVCE); + MCUCR = (0 << IVSEL); + reset(); +} + +static void disp_digit(uint8_t x) +{ + if (x < 10) + uart_send(UARTNUM, '0' + x); + else + uart_send(UARTNUM, 'a' - 10 + x); +} + +static void disp_hex8(uint8_t x) +{ + disp_digit(x>>4); + disp_digit(x&0xf); +} + +static void disp_hex16(uint16_t x) +{ + disp_hex8(x>>8); + disp_hex8(x); +} + +static void crc_app(void) +{ + uint32_t start_addr, addr, size; + uint8_t c; + uint16_t crc = 0xffff; + + bootloader_puts("start addr?\r\n"); + start_addr = bootloader_query_hex(); + if (start_addr > FLASHEND) + goto fail; + bootloader_puts("size?\r\n"); + size = bootloader_query_hex(); + if (start_addr + size > FLASHEND) + goto fail; + for (addr=start_addr; addr<start_addr+size; addr++) { + c = pgm_read_byte_far(addr); + crc = _crc_ccitt_update(crc, c); + } + disp_hex16(crc); + return; + fail: + bootloader_puts("KO"); +} + +static void prog_page(void) +{ + int c; + uint32_t addr; + uint16_t i; + uint16_t crc = 0xffff; + uint8_t buf[SPM_PAGESIZE]; + +#define SPM_PAGEMASK ((uint32_t)SPM_PAGESIZE-1) + bootloader_puts("addr?\r\n"); + addr = bootloader_query_hex(); + if (addr > FLASHEND) + goto fail; + /* start_addr must be page aligned */ + if (addr & SPM_PAGEMASK) + goto fail; + + bootloader_puts("addr ok\r\n"); + + /* data is received like the .bin format (which is already in + * little endian) */ + for (i=0; i<SPM_PAGESIZE; i++) { + while ((c=uart_recv_nowait(UARTNUM)) == -1); + crc = _crc_ccitt_update(crc, c); + buf[i] = c; + } + disp_hex16(crc); + bootloader_puts(" (y to valid)\r\n"); + while ((c=uart_recv_nowait(UARTNUM)) == -1); + if (c != 'y') + goto fail; + + /* erase page */ + eeprom_busy_wait(); + boot_page_erase(addr); + boot_spm_busy_wait(); + + /* Set up little-endian word and fill tmp buf. */ + for (i=0; i<SPM_PAGESIZE; i+=2) { + uint16_t w = buf[i] + ((uint16_t)(buf[i+1]) << 8); + boot_page_fill(addr + i, w); + } + + boot_page_write(addr); + boot_spm_busy_wait(); + + /* Reenable RWW-section again. We need this if we want to jump + * back to the application after bootloading. */ + boot_rww_enable(); + + bootloader_puts("OK"); + return; + fail: + bootloader_puts("KO"); +} + +int main(void) +{ + int c; + + uart_init(); + + /* move interrupt vector in bootloader section */ + MCUCR = (1 << IVCE); + MCUCR = (1 << IVSEL); + + sei(); + + bootloader_puts("\r\n"); + while (1) { + bootloader_puts("cmd>"); + while ((c=uart_recv_nowait(UARTNUM)) == -1); + if (c == 'x') + launch_app(); + else if (c == 'c') + crc_app(); + else if (c == 'p') + prog_page(); + else + bootloader_puts("bad cmd (p:prog_page c:crc x:exec)"); + bootloader_puts("\r\n"); + } + + return 0; +} diff --git a/projects/microb2009/tests/bootloader/rdline_config.h b/projects/microb2009/tests/bootloader/rdline_config.h new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/bootloader/uart_config.h b/projects/microb2009/tests/bootloader/uart_config.h new file mode 100755 index 0000000..57fe5cf --- /dev/null +++ b/projects/microb2009/tests/bootloader/uart_config.h @@ -0,0 +1,76 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.2 2009-02-20 21:10:01 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +#if defined __AVR_ATmega128__ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +#define UART0_USE_DOUBLE_SPEED 0 + +#define UART0_RX_FIFO_SIZE 64 +#define UART0_TX_FIFO_SIZE 16 + +#define UART0_NBITS 8 +#define UART0_PARITY UART_PARTITY_NONE +#define UART0_STOP_BIT UART_STOP_BITS_1 + +#elif defined __AVR_ATmega2560__ + +/* compile uart3 fonctions, undefine it to pass compilation */ +#define UART3_COMPILE + +/* enable uart3 if == 1, disable if == 0 */ +#define UART3_ENABLED 1 + +/* enable uart3 interrupts if == 1, disable if == 0 */ +#define UART3_INTERRUPT_ENABLED 1 + +#define UART3_BAUDRATE 57600 + +#define UART3_USE_DOUBLE_SPEED 0 + +#define UART3_RX_FIFO_SIZE 64 +#define UART3_TX_FIFO_SIZE 16 + +#define UART3_NBITS 8 +#define UART3_PARITY UART_PARTITY_NONE +#define UART3_STOP_BIT UART_STOP_BITS_1 + +#endif /* avr type */ + +#endif + diff --git a/projects/microb2009/tests/encoders_at90s2313/.config b/projects/microb2009/tests/encoders_at90s2313/.config new file mode 100755 index 0000000..44d2d33 --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/.config @@ -0,0 +1,249 @@ +# +# Automatically generated make config: don't edit +# + +# +# Hardware +# +CONFIG_MCU_AT90S2313=y +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +# CONFIG_MCU_ATMEGA128 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=10000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +# CONFIG_MATH_LIB is not set +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# + +# +# Enable math library in generation options to see all modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set + +# +# Communication modules +# + +# +# uart needs circular buffer, mf2 client may need scheduler +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set + +# +# Filters +# +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# + +# +# Crypto modules depend on utils module +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# + +# +# Encoding modules depend on utils module +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# + +# +# Debug modules depend on utils module +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/microb2009/tests/encoders_at90s2313/CVS/Entries b/projects/microb2009/tests/encoders_at90s2313/CVS/Entries new file mode 100644 index 0000000..1a9a42b --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/CVS/Entries @@ -0,0 +1,5 @@ +/.config/1.1/Fri Dec 26 13:08:29 2008// +/Makefile/1.1/Fri Dec 26 13:08:29 2008// +/encoders.S/1.1/Fri Dec 26 13:08:29 2008// +/gen_tableau.py/1.1/Fri Dec 26 13:08:29 2008// +D diff --git a/projects/microb2009/tests/encoders_at90s2313/CVS/Repository b/projects/microb2009/tests/encoders_at90s2313/CVS/Repository new file mode 100644 index 0000000..cd38576 --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests/encoders_at90s2313 diff --git a/projects/microb2009/tests/encoders_at90s2313/CVS/Root b/projects/microb2009/tests/encoders_at90s2313/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/encoders_at90s2313/CVS/Template b/projects/microb2009/tests/encoders_at90s2313/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/encoders_at90s2313/Makefile b/projects/microb2009/tests/encoders_at90s2313/Makefile new file mode 100755 index 0000000..55b89a3 --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/Makefile @@ -0,0 +1,22 @@ +TARGET = encoders + +AVERSIVE_DIR = ../../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = $(TARGET).S + +AVRDUDE_DELAY=30 + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/projects/microb2009/tests/encoders_at90s2313/encoders.S b/projects/microb2009/tests/encoders_at90s2313/encoders.S new file mode 100755 index 0000000..443da06 --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/encoders.S @@ -0,0 +1,893 @@ + ;; PIND = X X X SEL A1 B1 A2 B2 + + ;; r2 -> codeur 1 + ;; r3 -> codeur 2 + + ;; r17 -> codAB + ;; r5 -> codAB_prec + ;; r18 -> 0 + +.global main + + .type main, @function +main: + ;; DDRB = 0xFF, en sortie + ldi r24,lo8(-1) + out 55-0x20,r24 + + ;; on initialise à 0 les registres + ldi r17,0 + ldi r18,0 + ldi r30,0 + ldi r31,1 + mov r5,r30 + mov r2,r30 + mov r3,r30 + + + ;; Etapes : + ;; Lit le port + ;; Saute à l'adresse PORT * 2 + offset + ;; Saute a la routine d'incrément qui va bien + ;; Met a jour la sortie + ;; Retourne au début +boucle: + ;; 1 cycle + out 56-0x20,r2 + + ;; r5 va contenir l'etat precedent de codAB, décalé de 4 vers la gauche + ;; 1 cycle + mov r5,r17 + ;; 1 cycle + swap r5 + + ;; Lit le pinD (les 4 LSB) dans r17 + ;; 1 cycle + in r17,48-0x20 + ;; 1 cycle + cbr r17,0xF0 + + ;; on le place dans r0 + ;; 1 cycle + mov r0, r17 + + ;; on y additionne l'etat precedent (r5) + ;; 1 cycle + add r0,r5 + + ;; On met tout ça dans Z (r30/r31) + ;; 1 cycle + mov r30,r0 + + ;; On saute à l'adresse du tableau + ;; 2 cycles + ijmp + + + +moins_moins: + ;; 1 cycle + dec r2 + ;; 2 cycles + rjmp boucle +moins_zero: + dec r2 + rjmp boucle +moins_plus: + dec r2 + rjmp boucle + +zero_moins: + rjmp boucle +zero_zero: + rjmp boucle +zero_plus: + rjmp boucle + +plus_moins: + inc r2 + rjmp boucle +plus_zero: + inc r2 + rjmp boucle +plus_plus: + inc r2 + rjmp boucle + + + +; lecture_sel: +; ;; Lit le pinD dans r6 pour récupérer le bit SEL +; in r6,48-0x20 + +; ;; Passe l'instruction suivante si le bit de sel est 0 +; ;; (skip if bit in register is cleared) +; sbrc r6,4 +; rjmp cpt2 + +; cpt1: +; out 56-0x20,r2 +; rjmp boucle + +; cpt2: +; out 56-0x20,r3 +; rjmp boucle + + + +.org 0x1DE +tableau: + + ;; VAL = 0 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 0 0 + ;; 2 cycles + rjmp zero_zero + + ;; VAL = 1 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 0 1 + rjmp zero_plus + + ;; VAL = 2 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 0 3 + rjmp zero_moins + + ;; VAL = 3 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 0 2 + rjmp zero_zero + + ;; VAL = 4 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 1 0 + rjmp plus_zero + + ;; VAL = 5 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 1 1 + rjmp plus_plus + + ;; VAL = 6 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 1 3 + rjmp plus_moins + + ;; VAL = 7 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 1 2 + rjmp plus_zero + + ;; VAL = 8 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 3 0 + rjmp moins_zero + + ;; VAL = 9 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 3 1 + rjmp moins_plus + + ;; VAL = 10 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 3 3 + rjmp moins_moins + + ;; VAL = 11 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 3 2 + rjmp moins_zero + + ;; VAL = 12 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 2 0 + rjmp zero_zero + + ;; VAL = 13 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 2 1 + rjmp zero_plus + + ;; VAL = 14 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 2 3 + rjmp zero_moins + + ;; VAL = 15 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 0 2 2 + rjmp zero_zero + + ;; VAL = 16 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 0 0 + rjmp zero_moins + + ;; VAL = 17 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 0 1 + rjmp zero_zero + + ;; VAL = 18 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 0 3 + rjmp zero_zero + + ;; VAL = 19 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 0 2 + rjmp zero_plus + + ;; VAL = 20 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 1 0 + rjmp plus_moins + + ;; VAL = 21 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 1 1 + rjmp plus_zero + + ;; VAL = 22 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 1 3 + rjmp plus_zero + + ;; VAL = 23 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 1 2 + rjmp plus_plus + + ;; VAL = 24 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 3 0 + rjmp moins_moins + + ;; VAL = 25 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 3 1 + rjmp moins_zero + + ;; VAL = 26 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 3 3 + rjmp moins_zero + + ;; VAL = 27 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 3 2 + rjmp moins_plus + + ;; VAL = 28 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 2 0 + rjmp zero_moins + + ;; VAL = 29 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 2 1 + rjmp zero_zero + + ;; VAL = 30 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 2 3 + rjmp zero_zero + + ;; VAL = 31 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 1 2 2 + rjmp zero_plus + + ;; VAL = 32 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 0 0 + rjmp zero_plus + + ;; VAL = 33 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 0 1 + rjmp zero_zero + + ;; VAL = 34 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 0 3 + rjmp zero_zero + + ;; VAL = 35 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 0 2 + rjmp zero_moins + + ;; VAL = 36 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 1 0 + rjmp plus_plus + + ;; VAL = 37 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 1 1 + rjmp plus_zero + + ;; VAL = 38 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 1 3 + rjmp plus_zero + + ;; VAL = 39 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 1 2 + rjmp plus_moins + + ;; VAL = 40 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 3 0 + rjmp moins_plus + + ;; VAL = 41 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 3 1 + rjmp moins_zero + + ;; VAL = 42 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 3 3 + rjmp moins_zero + + ;; VAL = 43 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 3 2 + rjmp moins_moins + + ;; VAL = 44 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 2 0 + rjmp zero_plus + + ;; VAL = 45 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 2 1 + rjmp zero_zero + + ;; VAL = 46 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 2 3 + rjmp zero_zero + + ;; VAL = 47 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 3 2 2 + rjmp zero_moins + + ;; VAL = 48 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 0 0 + rjmp zero_zero + + ;; VAL = 49 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 0 1 + rjmp zero_moins + + ;; VAL = 50 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 0 3 + rjmp zero_plus + + ;; VAL = 51 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 0 2 + rjmp zero_zero + + ;; VAL = 52 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 1 0 + rjmp plus_zero + + ;; VAL = 53 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 1 1 + rjmp plus_moins + + ;; VAL = 54 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 1 3 + rjmp plus_plus + + ;; VAL = 55 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 1 2 + rjmp plus_zero + + ;; VAL = 56 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 3 0 + rjmp moins_zero + + ;; VAL = 57 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 3 1 + rjmp moins_moins + + ;; VAL = 58 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 3 3 + rjmp moins_plus + + ;; VAL = 59 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 3 2 + rjmp moins_zero + + ;; VAL = 60 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 2 0 + rjmp zero_zero + + ;; VAL = 61 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 2 1 + rjmp zero_moins + + ;; VAL = 62 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 2 3 + rjmp zero_plus + + ;; VAL = 63 - C1(t-1) C2(t-1) C1 C2 (naturel) 0 2 2 2 + rjmp zero_zero + + ;; VAL = 64 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 0 0 + rjmp moins_zero + + ;; VAL = 65 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 0 1 + rjmp moins_plus + + ;; VAL = 66 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 0 3 + rjmp moins_moins + + ;; VAL = 67 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 0 2 + rjmp moins_zero + + ;; VAL = 68 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 1 0 + rjmp zero_zero + + ;; VAL = 69 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 1 1 + rjmp zero_plus + + ;; VAL = 70 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 1 3 + rjmp zero_moins + + ;; VAL = 71 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 1 2 + rjmp zero_zero + + ;; VAL = 72 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 3 0 + rjmp zero_zero + + ;; VAL = 73 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 3 1 + rjmp zero_plus + + ;; VAL = 74 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 3 3 + rjmp zero_moins + + ;; VAL = 75 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 3 2 + rjmp zero_zero + + ;; VAL = 76 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 2 0 + rjmp plus_zero + + ;; VAL = 77 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 2 1 + rjmp plus_plus + + ;; VAL = 78 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 2 3 + rjmp plus_moins + + ;; VAL = 79 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 0 2 2 + rjmp plus_zero + + ;; VAL = 80 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 0 0 + rjmp moins_moins + + ;; VAL = 81 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 0 1 + rjmp moins_zero + + ;; VAL = 82 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 0 3 + rjmp moins_zero + + ;; VAL = 83 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 0 2 + rjmp moins_plus + + ;; VAL = 84 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 1 0 + rjmp zero_moins + + ;; VAL = 85 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 1 1 + rjmp zero_zero + + ;; VAL = 86 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 1 3 + rjmp zero_zero + + ;; VAL = 87 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 1 2 + rjmp zero_plus + + ;; VAL = 88 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 3 0 + rjmp zero_moins + + ;; VAL = 89 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 3 1 + rjmp zero_zero + + ;; VAL = 90 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 3 3 + rjmp zero_zero + + ;; VAL = 91 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 3 2 + rjmp zero_plus + + ;; VAL = 92 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 2 0 + rjmp plus_moins + + ;; VAL = 93 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 2 1 + rjmp plus_zero + + ;; VAL = 94 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 2 3 + rjmp plus_zero + + ;; VAL = 95 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 1 2 2 + rjmp plus_plus + + ;; VAL = 96 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 0 0 + rjmp moins_plus + + ;; VAL = 97 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 0 1 + rjmp moins_zero + + ;; VAL = 98 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 0 3 + rjmp moins_zero + + ;; VAL = 99 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 0 2 + rjmp moins_moins + + ;; VAL = 100 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 1 0 + rjmp zero_plus + + ;; VAL = 101 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 1 1 + rjmp zero_zero + + ;; VAL = 102 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 1 3 + rjmp zero_zero + + ;; VAL = 103 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 1 2 + rjmp zero_moins + + ;; VAL = 104 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 3 0 + rjmp zero_plus + + ;; VAL = 105 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 3 1 + rjmp zero_zero + + ;; VAL = 106 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 3 3 + rjmp zero_zero + + ;; VAL = 107 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 3 2 + rjmp zero_moins + + ;; VAL = 108 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 2 0 + rjmp plus_plus + + ;; VAL = 109 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 2 1 + rjmp plus_zero + + ;; VAL = 110 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 2 3 + rjmp plus_zero + + ;; VAL = 111 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 3 2 2 + rjmp plus_moins + + ;; VAL = 112 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 0 0 + rjmp moins_zero + + ;; VAL = 113 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 0 1 + rjmp moins_moins + + ;; VAL = 114 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 0 3 + rjmp moins_plus + + ;; VAL = 115 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 0 2 + rjmp moins_zero + + ;; VAL = 116 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 1 0 + rjmp zero_zero + + ;; VAL = 117 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 1 1 + rjmp zero_moins + + ;; VAL = 118 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 1 3 + rjmp zero_plus + + ;; VAL = 119 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 1 2 + rjmp zero_zero + + ;; VAL = 120 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 3 0 + rjmp zero_zero + + ;; VAL = 121 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 3 1 + rjmp zero_moins + + ;; VAL = 122 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 3 3 + rjmp zero_plus + + ;; VAL = 123 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 3 2 + rjmp zero_zero + + ;; VAL = 124 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 2 0 + rjmp plus_zero + + ;; VAL = 125 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 2 1 + rjmp plus_moins + + ;; VAL = 126 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 2 3 + rjmp plus_plus + + ;; VAL = 127 - C1(t-1) C2(t-1) C1 C2 (naturel) 1 2 2 2 + rjmp plus_zero + + ;; VAL = 128 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 0 0 + rjmp plus_zero + + ;; VAL = 129 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 0 1 + rjmp plus_plus + + ;; VAL = 130 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 0 3 + rjmp plus_moins + + ;; VAL = 131 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 0 2 + rjmp plus_zero + + ;; VAL = 132 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 1 0 + rjmp zero_zero + + ;; VAL = 133 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 1 1 + rjmp zero_plus + + ;; VAL = 134 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 1 3 + rjmp zero_moins + + ;; VAL = 135 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 1 2 + rjmp zero_zero + + ;; VAL = 136 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 3 0 + rjmp zero_zero + + ;; VAL = 137 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 3 1 + rjmp zero_plus + + ;; VAL = 138 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 3 3 + rjmp zero_moins + + ;; VAL = 139 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 3 2 + rjmp zero_zero + + ;; VAL = 140 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 2 0 + rjmp moins_zero + + ;; VAL = 141 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 2 1 + rjmp moins_plus + + ;; VAL = 142 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 2 3 + rjmp moins_moins + + ;; VAL = 143 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 0 2 2 + rjmp moins_zero + + ;; VAL = 144 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 0 0 + rjmp plus_moins + + ;; VAL = 145 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 0 1 + rjmp plus_zero + + ;; VAL = 146 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 0 3 + rjmp plus_zero + + ;; VAL = 147 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 0 2 + rjmp plus_plus + + ;; VAL = 148 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 1 0 + rjmp zero_moins + + ;; VAL = 149 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 1 1 + rjmp zero_zero + + ;; VAL = 150 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 1 3 + rjmp zero_zero + + ;; VAL = 151 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 1 2 + rjmp zero_plus + + ;; VAL = 152 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 3 0 + rjmp zero_moins + + ;; VAL = 153 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 3 1 + rjmp zero_zero + + ;; VAL = 154 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 3 3 + rjmp zero_zero + + ;; VAL = 155 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 3 2 + rjmp zero_plus + + ;; VAL = 156 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 2 0 + rjmp moins_moins + + ;; VAL = 157 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 2 1 + rjmp moins_zero + + ;; VAL = 158 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 2 3 + rjmp moins_zero + + ;; VAL = 159 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 1 2 2 + rjmp moins_plus + + ;; VAL = 160 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 0 0 + rjmp plus_plus + + ;; VAL = 161 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 0 1 + rjmp plus_zero + + ;; VAL = 162 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 0 3 + rjmp plus_zero + + ;; VAL = 163 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 0 2 + rjmp plus_moins + + ;; VAL = 164 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 1 0 + rjmp zero_plus + + ;; VAL = 165 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 1 1 + rjmp zero_zero + + ;; VAL = 166 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 1 3 + rjmp zero_zero + + ;; VAL = 167 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 1 2 + rjmp zero_moins + + ;; VAL = 168 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 3 0 + rjmp zero_plus + + ;; VAL = 169 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 3 1 + rjmp zero_zero + + ;; VAL = 170 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 3 3 + rjmp zero_zero + + ;; VAL = 171 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 3 2 + rjmp zero_moins + + ;; VAL = 172 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 2 0 + rjmp moins_plus + + ;; VAL = 173 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 2 1 + rjmp moins_zero + + ;; VAL = 174 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 2 3 + rjmp moins_zero + + ;; VAL = 175 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 3 2 2 + rjmp moins_moins + + ;; VAL = 176 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 0 0 + rjmp plus_zero + + ;; VAL = 177 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 0 1 + rjmp plus_moins + + ;; VAL = 178 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 0 3 + rjmp plus_plus + + ;; VAL = 179 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 0 2 + rjmp plus_zero + + ;; VAL = 180 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 1 0 + rjmp zero_zero + + ;; VAL = 181 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 1 1 + rjmp zero_moins + + ;; VAL = 182 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 1 3 + rjmp zero_plus + + ;; VAL = 183 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 1 2 + rjmp zero_zero + + ;; VAL = 184 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 3 0 + rjmp zero_zero + + ;; VAL = 185 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 3 1 + rjmp zero_moins + + ;; VAL = 186 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 3 3 + rjmp zero_plus + + ;; VAL = 187 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 3 2 + rjmp zero_zero + + ;; VAL = 188 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 2 0 + rjmp moins_zero + + ;; VAL = 189 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 2 1 + rjmp moins_moins + + ;; VAL = 190 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 2 3 + rjmp moins_plus + + ;; VAL = 191 - C1(t-1) C2(t-1) C1 C2 (naturel) 3 2 2 2 + rjmp moins_zero + + ;; VAL = 192 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 0 0 + rjmp zero_zero + + ;; VAL = 193 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 0 1 + rjmp zero_plus + + ;; VAL = 194 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 0 3 + rjmp zero_moins + + ;; VAL = 195 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 0 2 + rjmp zero_zero + + ;; VAL = 196 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 1 0 + rjmp moins_zero + + ;; VAL = 197 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 1 1 + rjmp moins_plus + + ;; VAL = 198 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 1 3 + rjmp moins_moins + + ;; VAL = 199 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 1 2 + rjmp moins_zero + + ;; VAL = 200 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 3 0 + rjmp plus_zero + + ;; VAL = 201 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 3 1 + rjmp plus_plus + + ;; VAL = 202 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 3 3 + rjmp plus_moins + + ;; VAL = 203 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 3 2 + rjmp plus_zero + + ;; VAL = 204 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 2 0 + rjmp zero_zero + + ;; VAL = 205 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 2 1 + rjmp zero_plus + + ;; VAL = 206 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 2 3 + rjmp zero_moins + + ;; VAL = 207 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 0 2 2 + rjmp zero_zero + + ;; VAL = 208 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 0 0 + rjmp zero_moins + + ;; VAL = 209 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 0 1 + rjmp zero_zero + + ;; VAL = 210 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 0 3 + rjmp zero_zero + + ;; VAL = 211 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 0 2 + rjmp zero_plus + + ;; VAL = 212 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 1 0 + rjmp moins_moins + + ;; VAL = 213 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 1 1 + rjmp moins_zero + + ;; VAL = 214 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 1 3 + rjmp moins_zero + + ;; VAL = 215 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 1 2 + rjmp moins_plus + + ;; VAL = 216 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 3 0 + rjmp plus_moins + + ;; VAL = 217 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 3 1 + rjmp plus_zero + + ;; VAL = 218 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 3 3 + rjmp plus_zero + + ;; VAL = 219 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 3 2 + rjmp plus_plus + + ;; VAL = 220 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 2 0 + rjmp zero_moins + + ;; VAL = 221 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 2 1 + rjmp zero_zero + + ;; VAL = 222 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 2 3 + rjmp zero_zero + + ;; VAL = 223 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 1 2 2 + rjmp zero_plus + + ;; VAL = 224 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 0 0 + rjmp zero_plus + + ;; VAL = 225 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 0 1 + rjmp zero_zero + + ;; VAL = 226 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 0 3 + rjmp zero_zero + + ;; VAL = 227 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 0 2 + rjmp zero_moins + + ;; VAL = 228 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 1 0 + rjmp moins_plus + + ;; VAL = 229 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 1 1 + rjmp moins_zero + + ;; VAL = 230 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 1 3 + rjmp moins_zero + + ;; VAL = 231 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 1 2 + rjmp moins_moins + + ;; VAL = 232 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 3 0 + rjmp plus_plus + + ;; VAL = 233 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 3 1 + rjmp plus_zero + + ;; VAL = 234 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 3 3 + rjmp plus_zero + + ;; VAL = 235 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 3 2 + rjmp plus_moins + + ;; VAL = 236 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 2 0 + rjmp zero_plus + + ;; VAL = 237 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 2 1 + rjmp zero_zero + + ;; VAL = 238 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 2 3 + rjmp zero_zero + + ;; VAL = 239 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 3 2 2 + rjmp zero_moins + + ;; VAL = 240 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 0 0 + rjmp zero_zero + + ;; VAL = 241 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 0 1 + rjmp zero_moins + + ;; VAL = 242 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 0 3 + rjmp zero_plus + + ;; VAL = 243 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 0 2 + rjmp zero_zero + + ;; VAL = 244 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 1 0 + rjmp moins_zero + + ;; VAL = 245 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 1 1 + rjmp moins_moins + + ;; VAL = 246 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 1 3 + rjmp moins_plus + + ;; VAL = 247 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 1 2 + rjmp moins_zero + + ;; VAL = 248 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 3 0 + rjmp plus_zero + + ;; VAL = 249 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 3 1 + rjmp plus_moins + + ;; VAL = 250 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 3 3 + rjmp plus_plus + + ;; VAL = 251 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 3 2 + rjmp plus_zero + + ;; VAL = 252 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 2 0 + rjmp zero_zero + + ;; VAL = 253 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 2 1 + rjmp zero_moins + + ;; VAL = 254 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 2 3 + rjmp zero_plus + + ;; VAL = 255 - C1(t-1) C2(t-1) C1 C2 (naturel) 2 2 2 2 + rjmp zero_zero + + + + + diff --git a/projects/microb2009/tests/encoders_at90s2313/gen_tableau.py b/projects/microb2009/tests/encoders_at90s2313/gen_tableau.py new file mode 100755 index 0000000..e71dd7c --- /dev/null +++ b/projects/microb2009/tests/encoders_at90s2313/gen_tableau.py @@ -0,0 +1,35 @@ +def gray2nat(x): + if (x==3):return 2 + if (x==2):return 3 + return x + +# C1(t-1) C2(t-1) C1 C2 +for i in range(256): + cod1 = (i&0x0C)>>2 + cod2 = (i&0x03)>>0 + cod1_prec = (i&0xC0)>>6 + cod2_prec = (i&0x30)>>4 + + inc1 = gray2nat(cod1) - gray2nat(cod1_prec) + if inc1==3: texte1= "moins" + if inc1==2: texte1= "zero" + if inc1==1: texte1= "plus" + if inc1==0: texte1= "zero" + if inc1==-1: texte1= "moins" + if inc1==-2: texte1= "zero" + if inc1==-3: texte1= "plus" + + inc2 = gray2nat(cod2) - gray2nat(cod2_prec) + if inc2==3: texte2= "moins" + if inc2==2: texte2= "zero" + if inc2==1: texte2= "plus" + if inc2==0: texte2= "zero" + if inc2==-1: texte2= "moins" + if inc2==-2: texte2= "zero" + if inc2==-3: texte2= "plus" + + + print + print " ;; VAL = %3d - C1(t-1) C2(t-1) C1 C2 (naturel) %3d %3d %3d %3d"%(i,gray2nat(cod1_prec),gray2nat(cod2_prec), + gray2nat(cod1),gray2nat(cod2)) + print " rjmp %s_%s"%(texte1,texte2) diff --git a/projects/microb2009/tests/oa/.config b/projects/microb2009/tests/oa/.config new file mode 100644 index 0000000..78fe038 --- /dev/null +++ b/projects/microb2009/tests/oa/.config @@ -0,0 +1,251 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=12000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_NO_PRINTF is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +# CONFIG_MODULE_CIRBUF is not set +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_GEOMETRY=y +CONFIG_MODULE_GEOMETRY_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER is not set +# CONFIG_MODULE_SCHEDULER_CREATE_CONFIG is not set +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +CONFIG_MODULE_SCHEDULER_TIMER0=y +# CONFIG_MODULE_SCHEDULER_MANUAL is not set +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# +# CONFIG_MODULE_UART is not set +# CONFIG_MODULE_UART_9BITS is not set +# CONFIG_MODULE_UART_CREATE_CONFIG is not set +# CONFIG_MODULE_SPI is not set +# CONFIG_MODULE_SPI_CREATE_CONFIG is not set +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +# CONFIG_MODULE_TIMER is not set +# CONFIG_MODULE_TIMER_CREATE_CONFIG is not set +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_VT100 is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set +# CONFIG_MODULE_PARSE_NO_FLOAT is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders (you need comm/spi for encoders_spi) +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_SPI is not set +# CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +CONFIG_MODULE_OBSTACLE_AVOIDANCE=y +CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG=y + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" +CONFIG_AVRDUDE_BAUDRATE=19200 + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set +# CONFIG_AVRDUDE_CHECK_SIGNATURE is not set diff --git a/projects/microb2009/tests/oa/CVS/Entries b/projects/microb2009/tests/oa/CVS/Entries new file mode 100644 index 0000000..d4f414a --- /dev/null +++ b/projects/microb2009/tests/oa/CVS/Entries @@ -0,0 +1,8 @@ +/.config/1.2/Wed May 27 20:04:07 2009// +/Makefile/1.1/Fri Apr 24 19:30:42 2009// +/error_config.h/1.1/Fri Apr 24 19:30:42 2009// +/geometry_config.h/1.1/Sat May 2 10:12:53 2009// +/graph.py/1.3/Wed May 27 20:04:07 2009// +/main.c/1.4/Wed May 27 20:04:07 2009// +/obstacle_avoidance_config.h/1.3/Wed May 27 20:04:07 2009// +D diff --git a/projects/microb2009/tests/oa/CVS/Repository b/projects/microb2009/tests/oa/CVS/Repository new file mode 100644 index 0000000..69236c8 --- /dev/null +++ b/projects/microb2009/tests/oa/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests/oa diff --git a/projects/microb2009/tests/oa/CVS/Root b/projects/microb2009/tests/oa/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/oa/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/oa/CVS/Template b/projects/microb2009/tests/oa/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/oa/Makefile b/projects/microb2009/tests/oa/Makefile new file mode 100644 index 0000000..dfdae06 --- /dev/null +++ b/projects/microb2009/tests/oa/Makefile @@ -0,0 +1,16 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. + +SRC = $(TARGET).c + +ASRC = + +CFLAGS += -Wall -Werror + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + diff --git a/projects/microb2009/tests/oa/error_config.h b/projects/microb2009/tests/oa/error_config.h new file mode 100644 index 0000000..3dae63c --- /dev/null +++ b/projects/microb2009/tests/oa/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2009-04-24 19:30:42 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/tests/oa/geometry_config.h b/projects/microb2009/tests/oa/geometry_config.h new file mode 100644 index 0000000..7f88b2a --- /dev/null +++ b/projects/microb2009/tests/oa/geometry_config.h @@ -0,0 +1,5 @@ +#define PLAYGROUND_X_MIN 250 +#define PLAYGROUND_X_MAX 2750 + +#define PLAYGROUND_Y_MIN 250 +#define PLAYGROUND_Y_MAX 1850 diff --git a/projects/microb2009/tests/oa/graph.py b/projects/microb2009/tests/oa/graph.py new file mode 100644 index 0000000..ef5ed40 --- /dev/null +++ b/projects/microb2009/tests/oa/graph.py @@ -0,0 +1,159 @@ +import sys, re, math +import numpy as np +import matplotlib +import matplotlib.path as mpath +import matplotlib.patches as mpatches +import matplotlib.pyplot as plt +from matplotlib.patches import Arrow, Circle, Wedge, Polygon +from matplotlib.collections import PatchCollection +import popen2, random + +Path = mpath.Path + + +def build_poly(ptlist): + polydata = [] + polydata.append((Path.MOVETO, (ptlist[0]))) + for pt in ptlist[1:]: + polydata.append((Path.LINETO, (pt))) + polydata.append((Path.CLOSEPOLY, (ptlist[0]))) + codes, verts = zip(*polydata) + poly = mpath.Path(verts, codes) + x, y = zip(*poly.vertices) + return x,y + +def build_path(ptlist): + polydata = [] + polydata.append((Path.MOVETO, (ptlist[0]))) + for pt in ptlist[1:]: + polydata.append((Path.LINETO, (pt))) + codes, verts = zip(*polydata) + poly = mpath.Path(verts, codes) + x, y = zip(*poly.vertices) + return x,y + +def graph(filename, stx, sty, sta, enx, eny, opx, opy): + cmd = "./main %d %d %d %d %d %d %d"%(stx, sty, sta, enx, eny, opx, opy) + o,i = popen2.popen2(cmd) + i.close() + s = o.read(1000000) + o.close() + + open(filename + ".txt", "w").write(s) + + if len(s) == 1000000: + gloupix() + + fig = plt.figure() + ax = fig.add_subplot(111) + + # area + x,y = build_poly([(0,0), (3000,0), (3000,2100), (0,2100)]) + ax.plot(x, y, 'g-') + + x,y = build_poly([(250,250), (2750,250), (2750,1850), (250,1850)]) + ax.plot(x, y, 'g--') + + # central disc + patches = [ Circle((1500, 1050), 150) ] + + poly = None + poly_wait_pts = 0 + start = None + path = None + for l in s.split("\n"): + m = re.match("robot at: (-?\d+) (-?\d+) (-?\d+)", l) + if m: + x,y,a = (int(m.groups()[0]), int(m.groups()[1]), int(m.groups()[2])) + path = [ (x,y) ] + a_rad = (a * math.pi / 180.) + dx = 150 * math.cos(a_rad) + dy = 150 * math.sin(a_rad) + patches += [ Circle((x, y), 50) ] + patches += [ Arrow(x, y, dx, dy, 50) ] + + m = re.match("oa_start_end_points\(\) \((-?\d+),(-?\d+)\) \((-?\d+),(-?\d+)\)", l) + if m: + dst_x,dst_y = (int(m.groups()[2]), int(m.groups()[3])) + patches += [ Circle((dst_x, dst_y), 50) ] + + m = re.match("oa_new_poly\(size=(-?\d+)\)", l) + if m: + poly_wait_pts = int(m.groups()[0]) + poly = [] + + m = re.match("oponent at: (-?\d+) (-?\d+)", l) + if m: + poly_wait_pts = 4 + poly = [] + + m = re.match("oa_poly_set_point\(\) \((-?\d+),(-?\d+)\)", l) + if m: + poly.append((int(m.groups()[0]), int(m.groups()[1]))) + poly_wait_pts -= 1 + if poly_wait_pts == 0: + x,y = build_poly(poly) + ax.plot(x, y, 'r-') + + m = re.match("GOTO (-?\d+),(-?\d+)", l) + if m: + path.append((int(m.groups()[0]), int(m.groups()[1]))) + + m = re.match("With avoidance .: x=(-?\d+) y=(-?\d+)", l) + if m: + path.append((int(m.groups()[0]), int(m.groups()[1]))) + + p = PatchCollection(patches, cmap=matplotlib.cm.jet, alpha=0.4) + ax.add_collection(p) + + x,y = build_path(path) + ax.plot(x, y, 'bo-') + + ax.grid() + ax.set_xlim(-100, 3100) + ax.set_ylim(-100, 2200) + #ax.set_title('spline paths') + #plt.show() + fig.savefig(filename) + +# args are: startx, starty, starta, endx, endy, oppx, oppy +graph("normal1.png", 500, 1000, 180, 2000, 1500, 1500, 2000) +graph("normal2.png", 500, 300, 50, 2000, 1500, 2500, 2000) +graph("normal3.png", 500, 1000, 100, 1000, 1500, 2500, 1000) +graph("normal4.png", 500, 300, 0, 2500, 1700, 1000, 1000) +graph("normal5.png", 500, 1500, 0, 2500, 1700, 500, 1000) + +# echappement +graph("escape1.png", 5200, 1000, 0, 2500, 1700, 2500, 1000) +graph("escape2.png", 500, 1300, 0, 2500, 1700, 500, 1000) +graph("escape3.png", 500, 1000, 180, 2000, 1500, 1500, 2000) + +# pas d'echappement possible... petit carre +graph("small_square1.png", 500, 300, 0, 2500, 1700, 500, 500) +graph("small_square2.png", 500, 1000, 0, 2500, 1700, 500, 1000) +graph("small_square3.png", 590, 1000, 0, 2500, 1700, 500, 1000) +graph("small_square4.png", 560, 1000, 0, 2500, 1700, 300, 1000) +graph("small_square5.png", 550, 1000, 0, 2500, 1700, 250, 1000) +graph("small_square6.png", 5750, 1000, 0, 2500, 1700, 2750, 1000) + +# impossible +graph("impossible1.png", 500, 300, 0, 2700, 1800, 2700, 1800) +graph("impossible2.png", 500, 300, 0, 2700, 1800, 2400, 1500) +graph("impossible3.png", 500, 300, 0, 1500, 1150, 2700, 1800 ) + +#test current +graph("current01.png", 1274,709, 58, 1312, 400, 2274, 1241 ) + + +random.seed(0) +for i in range(100): + stx = random.randint(-50, 3050) + sty = random.randint(-50, 2050) + enx = random.randint(-50, 3050) + eny = random.randint(-50, 2050) + opx = random.randint(-50, 3050) + opy = random.randint(-50, 2050) + name = "random%d.png"%(i) + print (name, stx, sty, 0, enx, eny, opx, opy) + graph(name, stx, sty, 0, enx, eny, opx, opy) + diff --git a/projects/microb2009/tests/oa/main.c b/projects/microb2009/tests/oa/main.c new file mode 100644 index 0000000..43e0e1f --- /dev/null +++ b/projects/microb2009/tests/oa/main.c @@ -0,0 +1,537 @@ +#include <math.h> +#include <stdlib.h> +#include <stdio.h> +#include <stdarg.h> + +#include <aversive.h> +#include <aversive/error.h> + +#include <vect_base.h> +#include <lines.h> +#include <polygon.h> +#include <obstacle_avoidance.h> + +#ifndef HOST_VERSION +#error only for host +#endif + +#define M_2PI (M_PI*2) +#define E_USER_STRAT 200 + +#define ROBOT_X 1000 +#define ROBOT_Y 1000 +#define ROBOT_A 0.5 /* radian */ +#define ROBOT_A_DEG ((int)((ROBOT_A*180)/3.14159)) + +#define OPP_X 2000 +#define OPP_Y 1500 + +#define DST_X 1500 +#define DST_Y 2000 + +#define PLAYGROUND_X_MIN 250 +#define PLAYGROUND_X_MAX 2750 +#define PLAYGROUND_Y_MIN 250 +#define PLAYGROUND_Y_MAX 1850 + +int16_t robot_x = ROBOT_X; +int16_t robot_y = ROBOT_Y; +double robot_a = ROBOT_A; +int16_t robot_a_deg = ROBOT_A_DEG; + +int16_t opp_x = OPP_X; +int16_t opp_y = OPP_Y; + +int16_t dst_x = DST_X; +int16_t dst_y = DST_Y; + + +#define EDGE_NUMBER 5 + + +double norm(double x, double y) +{ + return sqrt(x*x + y*y); +} + +/* return the distance between two points */ +int16_t distance_between(int16_t x1, int16_t y1, int16_t x2, int16_t y2) +{ + int32_t x,y; + x = (x2-x1); + x = x*x; + y = (y2-y1); + y = y*y; + return sqrt(x+y); +} + +void rotate(double *x, double *y, double rot) +{ + double l, a; + + l = norm(*x, *y); + a = atan2(*y, *x); + + a += rot; + *x = l * cos(a); + *y = l * sin(a); +} + + +void set_rotated_pentagon(poly_t *pol, int16_t radius, + int16_t x, int16_t y) +{ + + double c_a, s_a; + uint8_t i; + double px1, py1, px2, py2; + double a_rad; + + a_rad = atan2(y - robot_y, x - robot_x); + + + /* generate pentagon */ + c_a = cos(-2*M_PI/EDGE_NUMBER); + s_a = sin(-2*M_PI/EDGE_NUMBER); + + /* + px1 = radius; + py1 = 0; + */ + px1 = radius * cos(a_rad + 2*M_PI/(2*EDGE_NUMBER)); + py1 = radius * sin(a_rad + 2*M_PI/(2*EDGE_NUMBER)); + + + for (i = 0; i < EDGE_NUMBER; i++){ + oa_poly_set_point(pol, x + px1, y + py1, i); + + px2 = px1*c_a + py1*s_a; + py2 = -px1*s_a + py1*c_a; + + px1 = px2; + py1 = py2; + } + +} + +void set_rotated_poly(poly_t *pol, int16_t w, int16_t l, + int16_t x, int16_t y) +{ + double tmp_x, tmp_y; + double a_rad; + + a_rad = atan2(y - robot_y, x - robot_x); + + /* point 1 */ + tmp_x = w; + tmp_y = l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 0); + + /* point 2 */ + tmp_x = -w; + tmp_y = l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 1); + + /* point 3 */ + tmp_x = -w; + tmp_y = -l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 2); + + /* point 4 */ + tmp_x = w; + tmp_y = -l; + rotate(&tmp_x, &tmp_y, a_rad); + tmp_x += x; + tmp_y += y; + oa_poly_set_point(pol, tmp_x, tmp_y, 3); +} + +#define DISC_PENTA_DIAG 500 +#define DISC_X 1500 +#define DISC_Y 1050 + +void set_central_disc_poly(poly_t *pol) +{ + set_rotated_pentagon(pol, DISC_PENTA_DIAG, + DISC_X, DISC_Y); +} + +/* /!\ half size */ +#define O_WIDTH 360 +#define O_LENGTH 500 + +void set_opponent_poly(poly_t *pol, int16_t w, int16_t l) +{ + int16_t x, y; + x = opp_x; + y = opp_y; + DEBUG(E_USER_STRAT, "oponent at: %d %d", x, y); + + /* place poly even if invalid, because it's -100 */ + set_rotated_poly(pol, w, l, x, y); +} + +/* don't care about polygons further than this distance for + * strat_escape */ +#define ESCAPE_POLY_THRES 1000 + +/* don't reduce opp if opp is too far */ +#define REDUCE_POLY_THRES 600 + +/* has to be longer than any poly */ +#define ESCAPE_VECT_LEN 3000 + +/* go in playground, loop until out of poly */ +/* XXX return end timer??? */ +static int8_t go_in_area(void) +{ + point_t poly_pts_area[4]; + poly_t poly_area; + + point_t robot_pt, disc_pt, dst_pt; + + robot_pt.x = robot_x; + robot_pt.y = robot_y; + disc_pt.x = DISC_X; + disc_pt.y = DISC_Y; + + /* Go in playground */ + if (!is_in_boundingbox(&robot_pt)){ + NOTICE(E_USER_STRAT, "not in playground %d, %d", robot_x, robot_y); + + poly_area.l = 4; + poly_area.pts = poly_pts_area; + poly_pts_area[0].x = PLAYGROUND_X_MIN; + poly_pts_area[0].y = PLAYGROUND_Y_MIN; + + poly_pts_area[1].x = PLAYGROUND_X_MAX; + poly_pts_area[1].y = PLAYGROUND_Y_MIN; + + poly_pts_area[2].x = PLAYGROUND_X_MAX; + poly_pts_area[2].y = PLAYGROUND_Y_MAX; + + poly_pts_area[3].x = PLAYGROUND_X_MIN; + poly_pts_area[3].y = PLAYGROUND_Y_MAX; + + + is_crossing_poly(robot_pt, disc_pt, &dst_pt, &poly_area); + NOTICE(E_USER_STRAT, "pt dst %d, %d", dst_pt.x, dst_pt.y); + + /* XXX */ + robot_pt.x = dst_pt.x; + robot_pt.y = dst_pt.y; + + robot_x = dst_pt.x; + robot_y = dst_pt.y; + + NOTICE(E_USER_STRAT, "GOTO %d,%d", + dst_pt.x, dst_pt.y); + + return 1; + } + + return 0; +} + + +/* + * Escape from polygons if needed. + */ +static int8_t escape_from_poly(poly_t *pol_disc, + int16_t opp_x, int16_t opp_y, + int16_t opp_w, int16_t opp_l, + poly_t *pol_opp) +{ + uint8_t in_disc = 0, in_opp = 0; + double escape_dx = 0, escape_dy = 0; + double disc_dx = 0, disc_dy = 0; + double opp_dx = 0, opp_dy = 0; + double len; + + point_t robot_pt, opp_pt, disc_pt, dst_pt; + point_t intersect_disc_pt, intersect_opp_pt; + + robot_pt.x = robot_x; + robot_pt.y = robot_y; + opp_pt.x = opp_x; + opp_pt.y = opp_y; + disc_pt.x = DISC_X; + disc_pt.y = DISC_Y; + + /* escape from other poly if necessary */ + if (is_point_in_poly(pol_disc, robot_x, robot_y) == 1) + in_disc = 1; + if (is_point_in_poly(pol_opp, robot_x, robot_y) == 1) + in_opp = 1; + + if (in_disc == 0 && in_opp == 0) { + NOTICE(E_USER_STRAT, "no need to escape"); + return 0; + } + + NOTICE(E_USER_STRAT, "in_disc=%d, in_opp=%d", in_disc, in_opp); + + /* process escape vector */ + + if (distance_between(robot_x, robot_y, DISC_X, DISC_Y) < ESCAPE_POLY_THRES) { + disc_dx = robot_x - DISC_X; + disc_dy = robot_y - DISC_Y; + NOTICE(E_USER_STRAT, " robot is near disc: vect=%2.2f,%2.2f", + disc_dx, disc_dy); + len = norm(disc_dx, disc_dy); + if (len != 0) { + disc_dx /= len; + disc_dy /= len; + } + else { + disc_dx = 1.0; + disc_dy = 0.0; + } + escape_dx += disc_dx; + escape_dy += disc_dy; + } + + if (distance_between(robot_x, robot_y, opp_x, opp_y) < ESCAPE_POLY_THRES) { + opp_dx = robot_x - opp_x; + opp_dy = robot_y - opp_y; + NOTICE(E_USER_STRAT, " robot is near opp: vect=%2.2f,%2.2f", + opp_dx, opp_dy); + len = norm(opp_dx, opp_dy); + if (len != 0) { + opp_dx /= len; + opp_dy /= len; + } + else { + opp_dx = 1.0; + opp_dy = 0.0; + } + escape_dx += opp_dx; + escape_dy += opp_dy; + } + + /* normalize escape vector */ + len = norm(escape_dx, escape_dy); + if (len != 0) { + escape_dx /= len; + escape_dy /= len; + } + else { + if (pol_disc != NULL) { + /* rotate 90° */ + escape_dx = disc_dy; + escape_dy = disc_dx; + } + else if (pol_opp != NULL) { + /* rotate 90° */ + escape_dx = opp_dy; + escape_dy = opp_dx; + } + else { /* should not happen */ + opp_dx = 1.0; + opp_dy = 0.0; + } + } + + NOTICE(E_USER_STRAT, " escape vect = %2.2f,%2.2f", + escape_dx, escape_dy); + + /* process the correct len of escape vector */ + + dst_pt.x = robot_pt.x + escape_dx * ESCAPE_VECT_LEN; + dst_pt.y = robot_pt.y + escape_dy * ESCAPE_VECT_LEN; + + NOTICE(E_USER_STRAT, "robot pt %d %d \r\ndst point %d,%d", + robot_pt.x, robot_pt.y, + dst_pt.x, dst_pt.y); + + if (in_disc) { + if (is_crossing_poly(robot_pt, dst_pt, &intersect_disc_pt, + pol_disc) == 1) { + /* we add 2 mm to be sure we are out of th polygon */ + dst_pt.x = intersect_disc_pt.x + escape_dx * 2; + dst_pt.y = intersect_disc_pt.y + escape_dy * 2; + if (is_point_in_poly(pol_opp, dst_pt.x, dst_pt.y) != 1) { + + if (!is_in_boundingbox(&dst_pt)) + return -1; + + robot_x = dst_pt.x; + robot_y = dst_pt.y; + + /* XXX */ + NOTICE(E_USER_STRAT, "GOTO %d,%d (%d)", + robot_x, robot_y, + is_point_in_poly(pol_opp, robot_x, robot_y)); + return 0; + } + } + } + + if (in_opp) { + if (is_crossing_poly(robot_pt, dst_pt, &intersect_opp_pt, + pol_opp) == 1) { + /* we add 2 cm to be sure we are out of th polygon */ + dst_pt.x = intersect_opp_pt.x + escape_dx * 2; + dst_pt.y = intersect_opp_pt.y + escape_dy * 2; + + if (is_point_in_poly(pol_disc, dst_pt.x, dst_pt.y) != 1) { + + if (!is_in_boundingbox(&dst_pt)) + return -1; + + robot_x = dst_pt.x; + robot_y = dst_pt.y; + + /* XXX */ + NOTICE(E_USER_STRAT, "GOTO %d,%d (%d)", + robot_x, robot_y, + is_point_in_poly(pol_opp, robot_x, robot_y)); + return 0; + } + } + } + + /* should not happen */ + return -1; +} + + + + +static int8_t goto_and_avoid(int16_t x, int16_t y) +{ + int8_t len = -1, i; + point_t *p; + poly_t *pol_disc, *pol_opp; + int16_t posx, posy; + int8_t ret; + int16_t opp_w; + int16_t opp_l; + point_t p_dst; + + opp_w = O_WIDTH; + opp_l = O_LENGTH; + + posx = robot_x; + posy = robot_y; + + oa_init(); + pol_disc = oa_new_poly(EDGE_NUMBER); + set_central_disc_poly(pol_disc); + pol_opp = oa_new_poly(4); + set_opponent_poly(pol_opp, O_WIDTH, O_LENGTH); + + go_in_area(); + + p_dst.x = x; + p_dst.y = y; + if (!is_in_boundingbox(&p_dst)) { + NOTICE(E_USER_STRAT, " dst is not in playground"); + return -1; + } + + if (is_point_in_poly(pol_disc, x, y)) { + NOTICE(E_USER_STRAT, " dst is in disc"); + return -1; + } + if (is_point_in_poly(pol_opp, x, y)) { + NOTICE(E_USER_STRAT, " dst is in opp"); + return -1; + } + while (opp_w && opp_l) { + + ret = escape_from_poly(pol_disc, + opp_x, opp_y, + opp_w, opp_l, + pol_opp); + if (ret == 0) { + oa_reset(); + oa_start_end_points(robot_x, robot_y, x, y); + oa_dump(); + + len = oa_process(); + if (len >= 0) + break; + } + if (distance_between(robot_x, robot_y, opp_x, opp_y) < REDUCE_POLY_THRES ) { + if (opp_w == 0) + opp_l /= 2; + opp_w /= 2; + } + else { + NOTICE(E_USER_STRAT, "oa_process() returned %d", len); + + /* XXX */ + return -1; + } + + NOTICE(E_USER_STRAT, "reducing opponent %d %d", opp_w, opp_l); + set_opponent_poly(pol_opp, opp_w, opp_l); + } + + p = oa_get_path(); + for (i=0 ; i<len ; i++) { + DEBUG(E_USER_STRAT, "With avoidance %d: x=%d y=%d", i, p->x, p->y); + p++; + } + + return 0; +} + +/* log function, add a command to configure + * it dynamically */ +void mylog(struct error * e, ...) +{ + va_list ap; + + va_start(ap, e); + + vfprintf(stdout, e->text, ap); + printf_P(PSTR("\r\n")); + va_end(ap); +} + +#ifdef HOST_VERSION +int main(int argc, char **argv) +#else +int main(void) +#endif +{ +#ifdef HOST_VERSION + if (argc != 8) { + printf("bad args\n"); + return -1; + } + robot_x = atoi(argv[1]); + robot_y = atoi(argv[2]); + robot_a_deg = atoi(argv[3]); + robot_a = (((double)robot_a_deg*M_PI)/3.14159); + dst_x = atoi(argv[4]); + dst_y = atoi(argv[5]); + opp_x = atoi(argv[6]); + opp_y = atoi(argv[7]); +#endif + /* LOGS */ + error_register_emerg(mylog); + error_register_error(mylog); + error_register_warning(mylog); + error_register_notice(mylog); + error_register_debug(mylog); + + polygon_set_boundingbox(PLAYGROUND_X_MIN, PLAYGROUND_Y_MIN, + PLAYGROUND_X_MAX, PLAYGROUND_Y_MAX); + + DEBUG(E_USER_STRAT, "robot at: %d %d %d", robot_x, robot_y, robot_a_deg); + goto_and_avoid(dst_x, dst_y); + + return 0; +} diff --git a/projects/microb2009/tests/oa/obstacle_avoidance_config.h b/projects/microb2009/tests/oa/obstacle_avoidance_config.h new file mode 100644 index 0000000..ec33028 --- /dev/null +++ b/projects/microb2009/tests/oa/obstacle_avoidance_config.h @@ -0,0 +1,25 @@ +/* + * Copyright Droids Corporation, Microb Technology (2009) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: obstacle_avoidance_config.h,v 1.3 2009-05-27 20:04:07 zer0 Exp $ + * + */ + +#define MAX_POLY 3 +#define MAX_PTS 12 +#define MAX_RAYS 150 +#define MAX_CHKPOINTS 6 diff --git a/projects/microb2009/tests/spi_test/.config b/projects/microb2009/tests/spi_test/.config new file mode 100644 index 0000000..220fe41 --- /dev/null +++ b/projects/microb2009/tests/spi_test/.config @@ -0,0 +1,242 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_ATMEGA1281 is not set +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +# CONFIG_MCU_ATMEGA2560 is not set +# CONFIG_MCU_ATMEGA256 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +# CONFIG_FORMAT_IHEX is not set +# CONFIG_FORMAT_SREC is not set +CONFIG_FORMAT_BINARY=y + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +# CONFIG_MODULE_SCHEDULER_USE_TIMERS is not set +# CONFIG_MODULE_SCHEDULER_TIMER0 is not set +CONFIG_MODULE_SCHEDULER_MANUAL=y +# CONFIG_MODULE_TIME is not set +# CONFIG_MODULE_TIME_CREATE_CONFIG is not set +# CONFIG_MODULE_TIME_EXT is not set +# CONFIG_MODULE_TIME_EXT_CREATE_CONFIG is not set + +# +# Communication modules +# +CONFIG_MODULE_UART=y +# CONFIG_MODULE_UART_9BITS is not set +CONFIG_MODULE_UART_CREATE_CONFIG=y +CONFIG_MODULE_SPI=y +CONFIG_MODULE_SPI_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_PWM_NG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +CONFIG_MODULE_VT100=y +CONFIG_MODULE_RDLINE=y +CONFIG_MODULE_RDLINE_CREATE_CONFIG=y +CONFIG_MODULE_RDLINE_KILL_BUF=y +CONFIG_MODULE_RDLINE_HISTORY=y +CONFIG_MODULE_PARSE=y + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set +# CONFIG_MODULE_AX12 is not set +# CONFIG_MODULE_AX12_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set +# CONFIG_MODULE_BLOCKING_DETECTION_MANAGER is not set +# CONFIG_MODULE_OBSTACLE_AVOIDANCE is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_PID_CREATE_CONFIG is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Radio devices +# +# CONFIG_MODULE_CC2420 is not set +# CONFIG_MODULE_CC2420_CREATE_CONFIG is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +CONFIG_MODULE_ERROR=y +CONFIG_MODULE_ERROR_CREATE_CONFIG=y + +# +# Programmer options +# +CONFIG_AVRDUDE=y +# CONFIG_AVARICE is not set + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +# CONFIG_AVRDUDE_PROG_AVR109 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/microb2009/tests/spi_test/CVS/Entries b/projects/microb2009/tests/spi_test/CVS/Entries new file mode 100644 index 0000000..8bf41f6 --- /dev/null +++ b/projects/microb2009/tests/spi_test/CVS/Entries @@ -0,0 +1,12 @@ +/.config/1.1/Fri Jan 30 20:42:17 2009// +/Makefile/1.1/Fri Jan 30 20:42:17 2009// +/commands.c/1.1/Fri Jan 30 20:42:17 2009// +/error_config.h/1.1/Fri Jan 30 20:42:17 2009// +/main.c/1.1/Fri Jan 30 20:42:17 2009// +/main.h/1.1/Fri Jan 30 20:42:17 2009// +/rdline_config.h/1.1/Fri Jan 30 20:42:17 2009// +/scheduler_config.h/1.1/Fri Jan 30 20:42:17 2009// +/spi_config.h/1.1/Fri Jan 30 20:42:17 2009// +/timer_config.h/1.1/Fri Jan 30 20:42:17 2009// +/uart_config.h/1.1/Fri Jan 30 20:42:17 2009// +D diff --git a/projects/microb2009/tests/spi_test/CVS/Repository b/projects/microb2009/tests/spi_test/CVS/Repository new file mode 100644 index 0000000..0c8ed43 --- /dev/null +++ b/projects/microb2009/tests/spi_test/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2009/tests/spi_test diff --git a/projects/microb2009/tests/spi_test/CVS/Root b/projects/microb2009/tests/spi_test/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2009/tests/spi_test/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2009/tests/spi_test/CVS/Template b/projects/microb2009/tests/spi_test/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/microb2009/tests/spi_test/Makefile b/projects/microb2009/tests/spi_test/Makefile new file mode 100755 index 0000000..781873c --- /dev/null +++ b/projects/microb2009/tests/spi_test/Makefile @@ -0,0 +1,29 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../../../.. +# VALUE, absolute or relative path : example ../.. # + +CFLAGS += -Werror + +# List C source files here. (C dependencies are automatically generated.) +SRC = commands.c $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk + +program_noerase: $(TARGET).$(FORMAT_EXTENSION) $(TARGET).eep + echo $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + $(AVRDUDE) -D -V $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) ;\ + diff --git a/projects/microb2009/tests/spi_test/commands.c b/projects/microb2009/tests/spi_test/commands.c new file mode 100755 index 0000000..c6c60a2 --- /dev/null +++ b/projects/microb2009/tests/spi_test/commands.c @@ -0,0 +1,211 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: commands.c,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + * Olivier MATZ <zer0@droids-corp.org> + */ + + +#include <stdio.h> +#include <string.h> + +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <parse.h> +#include <parse_num.h> +#include <parse_string.h> +#include <uart.h> +#include <spi.h> + +#include "main.h" + + +/**********************************************************/ +/* Reset */ + +/* this structure is filled when cmd_reset is parsed successfully */ +struct cmd_reset_result { + fixed_string_t arg0; +}; + +/* function called when cmd_reset is parsed successfully */ +static void cmd_reset_parsed(void * parsed_result, void * data) +{ + reset(); +} + +prog_char str_reset_arg0[] = "reset"; +parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0); + +prog_char help_reset[] = "Reset the board"; +parse_pgm_inst_t cmd_reset = { + .f = cmd_reset_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_reset, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_reset_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Spi_Test */ + +/* this structure is filled when cmd_spi_test is parsed successfully */ +struct cmd_spi_test_result { + fixed_string_t arg0; +}; + +/* function called when cmd_spi_test is parsed successfully */ +static void cmd_spi_test_parsed(void * parsed_result, void * data) +{ +#if 0 + uint8_t i, ret; + + for (i=0; i<3; i++) { + spi_slave_select(0); + ret = spi_send_and_receive_byte(i); + spi_slave_deselect(0); + printf_P(PSTR("Sent %d, received %d\r\n"), i, ret); + } +#else + printf_P(PSTR("disabled\r\n")); +#endif +} + +prog_char str_spi_test_arg0[] = "spi_test"; +parse_pgm_token_string_t cmd_spi_test_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_spi_test_result, arg0, str_spi_test_arg0); + +prog_char help_spi_test[] = "Test the SPI"; +parse_pgm_inst_t cmd_spi_test = { + .f = cmd_spi_test_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_spi_test, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_spi_test_arg0, + NULL, + }, +}; + +/**********************************************************/ +/* Bootloader */ + +/* this structure is filled when cmd_bootloader is parsed successfully */ +struct cmd_bootloader_result { + fixed_string_t arg0; +}; + +/* function called when cmd_bootloader is parsed successfully */ +static void cmd_bootloader_parsed(void * parsed_result, void * data) +{ +#define BOOTLOADER_ADDR 0x1e000 + if (pgm_read_byte_far(BOOTLOADER_ADDR) == 0xff) { + printf_P(PSTR("Bootloader is not present\r\n")); + return; + } + cli(); + /* ... very specific :( */ +#ifdef __AVR_ATmega128__ + TIMSK = 0; + ETIMSK = 0; +#else + /* XXX */ +#endif + EIMSK = 0; + UCSR0B = 0; + UCSR1B = 0; + SPCR = 0; + TWCR = 0; + ACSR = 0; + ADCSRA = 0; + + __asm__ __volatile__ ("ldi r30,0x00\n"); + __asm__ __volatile__ ("ldi r31,0xf0\n"); + __asm__ __volatile__ ("ijmp\n"); +} + +prog_char str_bootloader_arg0[] = "bootloader"; +parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0); + +prog_char help_bootloader[] = "Bootloader the board"; +parse_pgm_inst_t cmd_bootloader = { + .f = cmd_bootloader_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_bootloader, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_bootloader_arg0, + NULL, + }, +}; + +#ifdef notyet +/**********************************************************/ +/* Encoders tests */ + +/* this structure is filled when cmd_encoders is parsed successfully */ +struct cmd_encoders_result { + fixed_string_t arg0; + fixed_string_t arg1; +}; + +/* function called when cmd_encoders is parsed successfully */ +static void cmd_encoders_parsed(void * parsed_result, void * data) +{ + while(uart_recv_nowait(0) == -1) { + printf_P(PSTR("% .8ld % .8ld % .8ld % .8ld\r\n"), + encoders_microb_get_value((void *)0), + encoders_microb_get_value((void *)1), + encoders_microb_get_value((void *)2), + encoders_microb_get_value((void *)3)); + wait_ms(100); + } +} + +prog_char str_encoders_arg0[] = "encoders"; +parse_pgm_token_string_t cmd_encoders_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg0, str_encoders_arg0); +prog_char str_encoders_arg1[] = "show"; +parse_pgm_token_string_t cmd_encoders_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_encoders_result, arg1, str_encoders_arg1); + +prog_char help_encoders[] = "Show encoders values"; +parse_pgm_inst_t cmd_encoders = { + .f = cmd_encoders_parsed, /* function to call */ + .data = NULL, /* 2nd arg of func */ + .help_str = help_encoders, + .tokens = { /* token list, NULL terminated */ + (prog_void *)&cmd_encoders_arg0, + (prog_void *)&cmd_encoders_arg1, + NULL, + }, +}; +#endif + +/**********************************************************/ + + +/* in progmem */ +parse_pgm_ctx_t main_ctx[] = { + (parse_pgm_inst_t *)&cmd_reset, + (parse_pgm_inst_t *)&cmd_spi_test, + (parse_pgm_inst_t *)&cmd_bootloader, +#ifdef notyet + (parse_pgm_inst_t *)&cmd_encoders, +#endif + + NULL, +}; diff --git a/projects/microb2009/tests/spi_test/error_config.h b/projects/microb2009/tests/spi_test/error_config.h new file mode 100755 index 0000000..2ccf894 --- /dev/null +++ b/projects/microb2009/tests/spi_test/error_config.h @@ -0,0 +1,31 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: error_config.h,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + */ + +#ifndef _ERROR_CONFIG_ +#define _ERROR_CONFIG_ + +/** enable the dump of the comment */ +#define ERROR_DUMP_TEXTLOG + +/** enable the dump of filename and line number */ +#define ERROR_DUMP_FILE_LINE + +#endif diff --git a/projects/microb2009/tests/spi_test/main.c b/projects/microb2009/tests/spi_test/main.c new file mode 100755 index 0000000..a37e6a0 --- /dev/null +++ b/projects/microb2009/tests/spi_test/main.c @@ -0,0 +1,158 @@ +/* + * Copyright Droids Corporation + * Olivier Matz <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + */ + +#include <stdio.h> +#include <string.h> + +#include <aversive.h> +#include <aversive/pgmspace.h> +#include <aversive/wait.h> + +#include <uart.h> +#include <parse.h> +#include <rdline.h> +#include <timer.h> +#include <scheduler.h> +#include <spi.h> + +#include "main.h" + +/* for cmdline interface */ +struct rdline rdl; +char prompt[RDLINE_PROMPT_SIZE]; +extern parse_pgm_ctx_t main_ctx[]; + +/******** For cmdline. See in commands.c for the list of commands. */ +static void write_char(char c) +{ + uart_send(0, c); +} + +static void +valid_buffer(const char * buf, uint8_t size) +{ + int8_t ret; + ret = parse(main_ctx, buf); + if (ret == PARSE_AMBIGUOUS) + printf_P(PSTR("Ambiguous command\r\n")); + else if (ret == PARSE_NOMATCH) + printf_P(PSTR("Command not found\r\n")); + else if (ret == PARSE_BAD_ARGS) + printf_P(PSTR("Bad arguments\r\n")); +} + +static int8_t +complete_buffer(const char * buf, char * dstbuf, uint8_t dstsize, + int16_t * state) +{ + return complete(main_ctx, buf, state, dstbuf, dstsize); +} + +/***********************/ + +void do_led_blink(void * dummy) +{ +#if 1 /* simple blink */ + static uint8_t a=0; + + if(a) + LED1_ON(); + else + LED1_OFF(); + + a = !a; +#endif +} + +static void main_timer_interrupt(void) +{ + static uint8_t cpt = 0; + + cpt++; + sei(); + + if ((cpt & 0x3) == 0) + scheduler_interrupt(); +} + +/* sending "pop" on uart0 resets the robot */ +static void emergency(char c) { + static uint8_t i = 0; + + if( (i == 0 && c == 'p') || + (i == 1 && c == 'o') || + (i == 2 && c == 'p') ) + i++; + else if ( !(i == 1 && c == 'p') ) + i = 0; + if(i == 3) + reset(); +} + +int main(void) +{ + int c; + const char * history; + int8_t ret; + + /* SPI */ + spi_init(SPI_MODE_MASTER, SPI_FORMAT_2, SPI_CLK_RATE_16); + spi_set_data_order(SPI_MSB_FIRST); + spi_register_ss_line(&SS_PORT, SS_BIT); + + /* UART */ + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + uart_register_rx_event(0, emergency); + + /* TIMER */ + timer_init(); + timer0_register_OV_intr(main_timer_interrupt); + + /* SCHEDULER */ + scheduler_init(); + scheduler_add_periodical_event_priority(do_led_blink, NULL, + 100000L / SCHEDULER_UNIT, + LED_PRIO); + sei(); + + printf_P(PSTR("Coucou\r\n")); + + rdline_init(&rdl, write_char, valid_buffer, complete_buffer); + snprintf(prompt, sizeof(prompt), "ax12 > "); + rdline_newline(&rdl, prompt); + + while (1) { + c = uart_recv_nowait(0); + if (c == -1) + continue; + ret = rdline_char_in(&rdl, c); + if (ret != 2 && ret != 0) { + history = rdline_get_buffer(&rdl); + if (strlen(history) > 1) + rdline_add_history(&rdl, history); + rdline_newline(&rdl, prompt); + } + } + + return 0; +} diff --git a/projects/microb2009/tests/spi_test/main.h b/projects/microb2009/tests/spi_test/main.h new file mode 100755 index 0000000..e902330 --- /dev/null +++ b/projects/microb2009/tests/spi_test/main.h @@ -0,0 +1,32 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.h,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + */ + +// XXX values are not correct for this board +#define LED1_ON() sbi(PORTE, 2) +#define LED1_OFF() cbi(PORTE, 2) + +#define LED2_ON() sbi(PORTE, 3) +#define LED2_OFF() cbi(PORTE, 3) + +#define LED_PRIO 170 +#define TIME_PRIO 160 +#define CS_PRIO 150 + diff --git a/projects/microb2009/tests/spi_test/rdline_config.h b/projects/microb2009/tests/spi_test/rdline_config.h new file mode 100755 index 0000000..e69de29 diff --git a/projects/microb2009/tests/spi_test/scheduler_config.h b/projects/microb2009/tests/spi_test/scheduler_config.h new file mode 100755 index 0000000..ece1958 --- /dev/null +++ b/projects/microb2009/tests/spi_test/scheduler_config.h @@ -0,0 +1,47 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 4 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 7 + + +#define SCHEDULER_UNIT_FLOAT 512.0 +#define SCHEDULER_UNIT 512L + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/microb2009/tests/spi_test/spi_config.h b/projects/microb2009/tests/spi_test/spi_config.h new file mode 100644 index 0000000..76697c3 --- /dev/null +++ b/projects/microb2009/tests/spi_test/spi_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation (2008) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* + * Author : Julien LE GUEN - jlg@jleguen.info + */ + + +/* + * Configure HERE your SPI module + */ + + + +/* Number of slave devices in your system + * Each slave have a dedicated SS line that you have to register + * before using the SPI module + */ +#define SPI_MAX_SLAVES 1 + diff --git a/projects/microb2009/tests/spi_test/timer_config.h b/projects/microb2009/tests/spi_test/timer_config.h new file mode 100755 index 0000000..17e2470 --- /dev/null +++ b/projects/microb2009/tests/spi_test/timer_config.h @@ -0,0 +1,36 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 diff --git a/projects/microb2009/tests/spi_test/uart_config.h b/projects/microb2009/tests/spi_test/uart_config.h new file mode 100755 index 0000000..de9cf4c --- /dev/null +++ b/projects/microb2009/tests/spi_test/uart_config.h @@ -0,0 +1,104 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1 2009-01-30 20:42:17 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 57600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 64 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + +/* + * UART1 definitions + */ + +/* compile uart1 fonctions, undefine it to pass compilation */ +#define UART1_COMPILE + +/* enable uart1 if == 1, disable if == 0 */ +#define UART1_ENABLED 1 + +/* enable uart1 interrupts if == 1, disable if == 0 */ +#define UART1_INTERRUPT_ENABLED 1 + +#define UART1_BAUDRATE 115200 +//#define UART1_BAUDRATE 1000000 + + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +//#define UART1_USE_DOUBLE_SPEED 0 +#define UART1_USE_DOUBLE_SPEED 1 + +#define UART1_RX_FIFO_SIZE 32 +#define UART1_TX_FIFO_SIZE 32 +//#define UART1_NBITS 5 +//#define UART1_NBITS 6 +//#define UART1_NBITS 7 +#define UART1_NBITS 8 +//#define UART1_NBITS 9 + +#define UART1_PARITY UART_PARTITY_NONE +//#define UART1_PARITY UART_PARTITY_ODD +//#define UART1_PARITY UART_PARTITY_EVEN + +//#define UART1_STOP_BIT UART_STOP_BITS_1 +#define UART1_STOP_BIT UART_STOP_BITS_2 + + +#endif + diff --git a/projects/microb2010/CVS/Entries b/projects/microb2010/CVS/Entries new file mode 100644 index 0000000..1784810 --- /dev/null +++ b/projects/microb2010/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/projects/microb2010/CVS/Repository b/projects/microb2010/CVS/Repository new file mode 100644 index 0000000..e3084c1 --- /dev/null +++ b/projects/microb2010/CVS/Repository @@ -0,0 +1 @@ +aversive_projects/microb2010 diff --git a/projects/microb2010/CVS/Root b/projects/microb2010/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/microb2010/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/microb2010/CVS/Template b/projects/microb2010/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/profiling_example/.config b/projects/profiling_example/.config new file mode 100644 index 0000000..8e1c3d6 --- /dev/null +++ b/projects/profiling_example/.config @@ -0,0 +1,217 @@ +# +# Automatically generated by make menuconfig: don't edit +# + +# +# Hardware +# +# CONFIG_MCU_AT90S2313 is not set +# CONFIG_MCU_AT90S2323 is not set +# CONFIG_MCU_AT90S3333 is not set +# CONFIG_MCU_AT90S2343 is not set +# CONFIG_MCU_ATTINY22 is not set +# CONFIG_MCU_ATTINY26 is not set +# CONFIG_MCU_AT90S4414 is not set +# CONFIG_MCU_AT90S4433 is not set +# CONFIG_MCU_AT90S4434 is not set +# CONFIG_MCU_AT90S8515 is not set +# CONFIG_MCU_AT90S8534 is not set +# CONFIG_MCU_AT90S8535 is not set +# CONFIG_MCU_AT86RF401 is not set +# CONFIG_MCU_ATMEGA103 is not set +# CONFIG_MCU_ATMEGA603 is not set +# CONFIG_MCU_AT43USB320 is not set +# CONFIG_MCU_AT43USB355 is not set +# CONFIG_MCU_AT76C711 is not set +# CONFIG_MCU_ATMEGA8 is not set +# CONFIG_MCU_ATMEGA48 is not set +# CONFIG_MCU_ATMEGA88 is not set +# CONFIG_MCU_ATMEGA8515 is not set +# CONFIG_MCU_ATMEGA8535 is not set +# CONFIG_MCU_ATTINY13 is not set +# CONFIG_MCU_ATTINY2313 is not set +# CONFIG_MCU_ATMEGA16 is not set +# CONFIG_MCU_ATMEGA161 is not set +# CONFIG_MCU_ATMEGA162 is not set +# CONFIG_MCU_ATMEGA163 is not set +# CONFIG_MCU_ATMEGA165 is not set +# CONFIG_MCU_ATMEGA168 is not set +# CONFIG_MCU_ATMEGA169 is not set +# CONFIG_MCU_ATMEGA32 is not set +# CONFIG_MCU_ATMEGA323 is not set +# CONFIG_MCU_ATMEGA325 is not set +# CONFIG_MCU_ATMEGA3250 is not set +# CONFIG_MCU_ATMEGA64 is not set +# CONFIG_MCU_ATMEGA645 is not set +# CONFIG_MCU_ATMEGA6450 is not set +CONFIG_MCU_ATMEGA128=y +# CONFIG_MCU_AT90CAN128 is not set +# CONFIG_MCU_AT94K is not set +# CONFIG_MCU_AT90S1200 is not set +CONFIG_QUARTZ=16000000 + +# +# Generation options +# +# CONFIG_OPTM_0 is not set +# CONFIG_OPTM_1 is not set +# CONFIG_OPTM_2 is not set +# CONFIG_OPTM_3 is not set +CONFIG_OPTM_S=y +CONFIG_MATH_LIB=y +# CONFIG_FDEVOPEN_COMPAT is not set +# CONFIG_MINIMAL_PRINTF is not set +CONFIG_STANDARD_PRINTF=y +# CONFIG_ADVANCED_PRINTF is not set +CONFIG_FORMAT_IHEX=y +# CONFIG_FORMAT_SREC is not set +# CONFIG_FORMAT_BINARY is not set + +# +# Base modules +# +CONFIG_MODULE_CIRBUF=y +# CONFIG_MODULE_CIRBUF_LARGE is not set +# CONFIG_MODULE_FIXED_POINT is not set +# CONFIG_MODULE_VECT2 is not set +CONFIG_MODULE_SCHEDULER=y +CONFIG_MODULE_SCHEDULER_CREATE_CONFIG=y +CONFIG_MODULE_SCHEDULER_USE_TIMERS=y +CONFIG_MODULE_TIME=y +CONFIG_MODULE_TIME_CREATE_CONFIG=y + +# +# Communication modules +# +CONFIG_MODULE_UART=y +CONFIG_MODULE_UART_CREATE_CONFIG=y +# CONFIG_MODULE_I2C is not set +# CONFIG_MODULE_I2C_MASTER is not set +# CONFIG_MODULE_I2C_MULTIMASTER is not set +# CONFIG_MODULE_I2C_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_CLIENT is not set +# CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER is not set +# CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG is not set +# CONFIG_MODULE_MF2_SERVER is not set +# CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG is not set + +# +# Hardware modules +# +CONFIG_MODULE_TIMER=y +CONFIG_MODULE_TIMER_CREATE_CONFIG=y +# CONFIG_MODULE_TIMER_DYNAMIC is not set +# CONFIG_MODULE_PWM is not set +# CONFIG_MODULE_PWM_CREATE_CONFIG is not set +# CONFIG_MODULE_ADC is not set +# CONFIG_MODULE_ADC_CREATE_CONFIG is not set + +# +# IHM modules +# +# CONFIG_MODULE_MENU is not set +# CONFIG_MODULE_RDLINE is not set +# CONFIG_MODULE_RDLINE_CREATE_CONFIG is not set +# CONFIG_MODULE_RDLINE_KILL_BUF is not set +# CONFIG_MODULE_RDLINE_HISTORY is not set +# CONFIG_MODULE_PARSE is not set + +# +# External devices modules +# +# CONFIG_MODULE_LCD is not set +# CONFIG_MODULE_LCD_CREATE_CONFIG is not set +# CONFIG_MODULE_MULTISERVO is not set +# CONFIG_MODULE_MULTISERVO_CREATE_CONFIG is not set + +# +# Brushless motor drivers (you should enable pwm modules to see all) +# +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE is not set +# CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG is not set + +# +# Encoders +# +# CONFIG_MODULE_ENCODERS_MICROB is not set +# CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG is not set +# CONFIG_MODULE_ENCODERS_EIRBOT is not set +# CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG is not set + +# +# Robot specific modules +# +# CONFIG_MODULE_ROBOT_SYSTEM is not set +# CONFIG_MODULE_POSITION_MANAGER is not set +# CONFIG_MODULE_TRAJECTORY_MANAGER is not set + +# +# Control system modules +# +# CONFIG_MODULE_CONTROL_SYSTEM_MANAGER is not set +# CONFIG_MODULE_PID is not set +# CONFIG_MODULE_RAMP is not set +# CONFIG_MODULE_QUADRAMP is not set +# CONFIG_MODULE_QUADRAMP_DERIVATE is not set +# CONFIG_MODULE_BIQUAD is not set + +# +# Crypto modules +# +# CONFIG_MODULE_AES is not set +# CONFIG_MODULE_AES_CTR is not set +# CONFIG_MODULE_MD5 is not set +# CONFIG_MODULE_MD5_HMAC is not set +# CONFIG_MODULE_RC4 is not set + +# +# Encodings modules +# +# CONFIG_MODULE_BASE64 is not set +# CONFIG_MODULE_HAMMING is not set + +# +# Debug modules +# +# CONFIG_MODULE_DIAGNOSTIC is not set +# CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG is not set +# CONFIG_MODULE_ERROR is not set +# CONFIG_MODULE_ERROR_CREATE_CONFIG is not set + +# +# Programmer options +# +# CONFIG_AVRDUDE is not set +CONFIG_AVARICE=y + +# +# Avrdude +# +# CONFIG_AVRDUDE_PROG_FUTURELEC is not set +# CONFIG_AVRDUDE_PROG_ABCMINI is not set +# CONFIG_AVRDUDE_PROG_PICOWEB is not set +# CONFIG_AVRDUDE_PROG_SP12 is not set +# CONFIG_AVRDUDE_PROG_ALF is not set +# CONFIG_AVRDUDE_PROG_BASCOM is not set +# CONFIG_AVRDUDE_PROG_DT006 is not set +# CONFIG_AVRDUDE_PROG_PONY_STK200 is not set +CONFIG_AVRDUDE_PROG_STK200=y +# CONFIG_AVRDUDE_PROG_PAVR is not set +# CONFIG_AVRDUDE_PROG_BUTTERFLY is not set +# CONFIG_AVRDUDE_PROG_AVR910 is not set +# CONFIG_AVRDUDE_PROG_STK500 is not set +# CONFIG_AVRDUDE_PROG_AVRISP is not set +# CONFIG_AVRDUDE_PROG_BSD is not set +# CONFIG_AVRDUDE_PROG_DAPA is not set +# CONFIG_AVRDUDE_PROG_JTAG1 is not set +CONFIG_AVRDUDE_PORT="/dev/parport0" + +# +# Avarice +# +CONFIG_AVARICE_PORT="/dev/ttyS0" +CONFIG_AVARICE_DEBUG_PORT=1234 +CONFIG_AVARICE_PROG_MKI=y +# CONFIG_AVARICE_PROG_MKII is not set diff --git a/projects/profiling_example/CVS/Entries b/projects/profiling_example/CVS/Entries new file mode 100644 index 0000000..436045b --- /dev/null +++ b/projects/profiling_example/CVS/Entries @@ -0,0 +1,9 @@ +/.config/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +/Makefile/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +/main.c/1.1.2.2/Sun Oct 28 22:31:58 2007//Tb_zer0 +/parse_symbols.py/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +/scheduler_config.h/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +/time_config.h/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +/timer_config.h/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +/uart_config.h/1.1.2.1/Sun Oct 28 22:28:19 2007//Tb_zer0 +D diff --git a/projects/profiling_example/CVS/Repository b/projects/profiling_example/CVS/Repository new file mode 100644 index 0000000..9800f7f --- /dev/null +++ b/projects/profiling_example/CVS/Repository @@ -0,0 +1 @@ +aversive/projects/profiling_example diff --git a/projects/profiling_example/CVS/Root b/projects/profiling_example/CVS/Root new file mode 100644 index 0000000..9b45e6e --- /dev/null +++ b/projects/profiling_example/CVS/Root @@ -0,0 +1 @@ +:ext:cvs.droids-corp.org:/var/lib/cvs diff --git a/projects/profiling_example/CVS/Tag b/projects/profiling_example/CVS/Tag new file mode 100644 index 0000000..3a80432 --- /dev/null +++ b/projects/profiling_example/CVS/Tag @@ -0,0 +1 @@ +Tb_zer0 diff --git a/projects/profiling_example/CVS/Template b/projects/profiling_example/CVS/Template new file mode 100644 index 0000000..e69de29 diff --git a/projects/profiling_example/Makefile b/projects/profiling_example/Makefile new file mode 100644 index 0000000..36b9f84 --- /dev/null +++ b/projects/profiling_example/Makefile @@ -0,0 +1,21 @@ +TARGET = main + +# repertoire des modules +AVERSIVE_DIR = ../.. + +# List C source files here. (C dependencies are automatically generated.) +SRC = $(TARGET).c + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +######################################## + +-include .aversive_conf +include $(AVERSIVE_DIR)/mk/aversive_project.mk diff --git a/projects/profiling_example/main.c b/projects/profiling_example/main.c new file mode 100644 index 0000000..d6e153c --- /dev/null +++ b/projects/profiling_example/main.c @@ -0,0 +1,196 @@ +/* + * Copyright Droids Corporation (2007) + * Olivier MATZ <zer0@droids-corp.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: main.c,v 1.1.2.2 2007-10-28 22:31:58 zer0 Exp $ + * + * + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <aversive/wait.h> +#include <scheduler.h> +#include <timer.h> +#include <time.h> +#include <uart.h> + +/* + * The TIMER2 is used to randomly interrupt the running program and + * display the address of the interrupted function on the serial port. + * + * The addresses can be parsed using the python program in the same + * dir: + * ./parse_symbols.py compiler_files/main.sym + * + * The stdin of the python script is the list of addresses. Below is + * its output: + * + * 50.88% (145/285) time_wait_ms[00000b5a] + * 13.33% (038/285) test2[00000130] + * 11.23% (032/285) time_get_s[0000069e] + * 8.07% (023/285) main[00000156] + * 7.37% (021/285) test1[00000122] + * 4.56% (013/285) scheduler_interrupt[00000dcc] + * 4.56% (013/285) time_increment[000007e8] + */ + + +#define PROFILE_TIME 10 +volatile int a = 0; + +void __attribute__ ((noinline)) dump_reg(uint16_t pc) +{ + static volatile uint8_t cpt = PROFILE_TIME; + + if (cpt == 1) { + OCR2 = 0x80 + (rand()&0x7F); + + TCCR2 = 2; + TCNT2 = 0; + } + else if (cpt == 0) { + OCR2 = 0; + TCCR2 = 4; + TCNT2 = 0; + cpt = PROFILE_TIME; + printf("%.4x\n", pc); + } + cpt--; +} + + +void SIG_OUTPUT_COMPARE2(void) __attribute__ ((signal , naked, __INTR_ATTRS)); + +void SIG_OUTPUT_COMPARE2(void) +{ + asm volatile("push r1" "\n\t" + "push __tmp_reg__" "\n\t" + + /* save sreg */ + "in __tmp_reg__,__SREG__" "\n\t" + "push __tmp_reg__" "\n\t" + "eor r1, r1" "\n\t" + + /* save used regs (see avr-gcc doc about used regs) */ + "push r18" "\n\t" + "push r19" "\n\t" + "push r20" "\n\t" + "push r21" "\n\t" + "push r22" "\n\t" + "push r23" "\n\t" + "push r24" "\n\t" + "push r25" "\n\t" + "push r26" "\n\t" + "push r27" "\n\t" + "push r30" "\n\t" + "push r31" "\n\t" + + /* load sp in r30/r31 */ + "in r30, __SP_L__" "\n\t" + "in r31, __SP_H__" "\n\t" + + /* point to saved PC */ + "subi r30, lo8(-16)" "\n\t" + "sbci r31, hi8(-16)" "\n\t" + + /* load Program Counter into r24-r25 */ + "ldd r25, Z+0" "\n\t" + "ldd r24, Z+1" "\n\t" + + /* call dump_reg, params are in r24-25 */ + "call dump_reg" "\n\t" + + /* restore regs */ + "pop r31" "\n\t" + "pop r30" "\n\t" + "pop r27" "\n\t" + "pop r26" "\n\t" + "pop r25" "\n\t" + "pop r24" "\n\t" + "pop r23" "\n\t" + "pop r22" "\n\t" + "pop r21" "\n\t" + "pop r20" "\n\t" + "pop r19" "\n\t" + "pop r18" "\n\t" + + /* sreg */ + "pop __tmp_reg__" "\n\t" + "out __SREG__, __tmp_reg__" "\n\t" + + /* tmp reg */ + "pop __tmp_reg__" "\n\t" + "pop r1" "\n\t" + + "reti" "\n\t" + : + : + ); +} + + +void __attribute__((noinline)) test1(void) +{ + a=2; +} + +void __attribute__((noinline)) test2(void) +{ + a=1; + a=2; + a=3; +} + +void test_sched(void * dummy) +{ + time_wait_ms(50); +} + + +int main(void) +{ + uart_init(); + fdevopen(uart0_dev_send, uart0_dev_recv); + timer_init(); + scheduler_init(); + time_init(200); + + srand(0x1337); + sei(); + printf("Start profiling during 10 secs\n"); + + scheduler_add_periodical_event(test_sched, NULL, 100000L / SCHEDULER_UNIT); + + OCR2 = 0; + TCNT2 = 0; + TCCR2 = 4; + sbi(TIMSK, OCIE2); + + while(time_get_s() < 10) { + test1(); + test2(); + }; + + TCCR2=0; + printf("Finished\n"); + while(1); + + return 0; +} diff --git a/projects/profiling_example/parse_symbols.py b/projects/profiling_example/parse_symbols.py new file mode 100755 index 0000000..3845576 --- /dev/null +++ b/projects/profiling_example/parse_symbols.py @@ -0,0 +1,65 @@ +#!/usr/bin/python + +import sys + +if len(sys.argv) != 2: + print "Bad arguments" + print "Usage: parse_symbols.py file.sym" + sys.exit(1) + +symlist=[] +global_cpt=0 + +f=open(sys.argv[1]) + +# parse .sym file and fill a list +while True: + l=f.readline() + if l=='': + break + + address, type, name = l[:-1].split(' ') + if type != 'T': + continue + + # print "%x %s"%(int(address,16),name) + symlist.append([int(address, 16), name, 0]) + +f.close() + + +while True: + l=sys.stdin.readline() + if l=='': + break + + try: + add=int(l, 16)*2 + except: + print "Bad value" + continue + + prev = None + i=1 + while i < len(symlist): + address, name, cpt = symlist[i] + if add < address: + symlist[i-1][2] += 1 + global_cpt += 1 + break + i+=1 + + # address cannot be in last symbols, so we + # suppose it is not found + if i == len(symlist): + print "Cannot find symbol" + break + +symlist.sort(cmp=lambda x,y:x[2]<y[2] and 1 or -1) + +for sym in symlist: + address, name, cpt = sym + if not cpt: + continue + print "%2.2f%% (%.3d/%.3d) %s[%.8x]"%( (float(cpt)*100.)/global_cpt, cpt, + global_cpt, name, address) diff --git a/projects/profiling_example/scheduler_config.h b/projects/profiling_example/scheduler_config.h new file mode 100644 index 0000000..b0029f6 --- /dev/null +++ b/projects/profiling_example/scheduler_config.h @@ -0,0 +1,50 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: scheduler_config.h,v 1.1.2.1 2007-10-28 22:28:19 zer0 Exp $ + * + */ + +#ifndef _SCHEDULER_CONFIG_H_ +#define _SCHEDULER_CONFIG_H_ + +#define _SCHEDULER_CONFIG_VERSION_ 3 + +/** maximum number of allocated events */ +#define SCHEDULER_NB_MAX_EVENT 2 + + +//#define SCHEDULER_CK TIMER0_PRESCALER_DIV_8 +//#define SCHEDULER_CLOCK_PRESCALER 8 + +/** the num of the timer to use for the scheduler */ +#define SCHEDULER_TIMER_NUM 0 + +/** number of allowed imbricated scheduler interrupts. The maximum + * should be SCHEDULER_NB_MAX_EVENT since we never need to imbricate + * more than once per event. If it is less, it can avoid to browse the + * event table, events are delayed (we loose precision) but it takes + * less CPU */ +#define SCHEDULER_NB_STACKING_MAX SCHEDULER_NB_MAX_EVENT + +/** define it for debug infos (not recommended, because very slow on + * an AVR, it uses printf in an interrupt). It can be useful if + * prescaler is very high, making the timer interrupt period very + * long in comparison to printf() */ +/* #define SCHEDULER_DEBUG */ + +#endif // _SCHEDULER_CONFIG_H_ diff --git a/projects/profiling_example/time_config.h b/projects/profiling_example/time_config.h new file mode 100644 index 0000000..a3db6e4 --- /dev/null +++ b/projects/profiling_example/time_config.h @@ -0,0 +1,23 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: time_config.h,v 1.1.2.1 2007-10-28 22:28:19 zer0 Exp $ + * + */ + +/** precision of the time processor, in us */ +#define TIME_PRECISION 10000l diff --git a/projects/profiling_example/timer_config.h b/projects/profiling_example/timer_config.h new file mode 100644 index 0000000..8b75f06 --- /dev/null +++ b/projects/profiling_example/timer_config.h @@ -0,0 +1,39 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2006) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: timer_config.h,v 1.1.2.1 2007-10-28 22:28:19 zer0 Exp $ + * + */ + +#define TIMER0_ENABLED + +/* #define TIMER1_ENABLED */ +/* #define TIMER1A_ENABLED */ +/* #define TIMER1B_ENABLED */ +/* #define TIMER1C_ENABLED */ + +/* #define TIMER2_ENABLED */ + +/* #define TIMER3_ENABLED */ +/* #define TIMER3A_ENABLED */ +/* #define TIMER3B_ENABLED */ +/* #define TIMER3C_ENABLED */ + +#define TIMER0_PRESCALER_DIV 8 +/* #define TIMER1_PRESCALER_DIV 1 */ +/* #define TIMER2_PRESCALER_DIV 1 */ +/* #define TIMER3_PRESCALER_DIV 1 */ diff --git a/projects/profiling_example/uart_config.h b/projects/profiling_example/uart_config.h new file mode 100644 index 0000000..efd38d5 --- /dev/null +++ b/projects/profiling_example/uart_config.h @@ -0,0 +1,72 @@ +/* + * Copyright Droids Corporation, Microb Technology, Eirbot (2005) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Revision : $Id: uart_config.h,v 1.1.2.1 2007-10-28 22:28:19 zer0 Exp $ + * + */ + +/* Droids-corp 2004 - Zer0 + * config for uart module + */ + +#ifndef UART_CONFIG_H +#define UART_CONFIG_H + +/* + * UART0 definitions + */ + +/* compile uart0 fonctions, undefine it to pass compilation */ +#define UART0_COMPILE + +/* enable uart0 if == 1, disable if == 0 */ +#define UART0_ENABLED 1 + +/* enable uart0 interrupts if == 1, disable if == 0 */ +#define UART0_INTERRUPT_ENABLED 1 + +#define UART0_BAUDRATE 9600 + +/* + * if you enable this, the maximum baudrate you can reach is + * higher, but the precision is lower. + */ +#define UART0_USE_DOUBLE_SPEED 0 +//#define UART0_USE_DOUBLE_SPEED 1 + +#define UART0_RX_FIFO_SIZE 4 +#define UART0_TX_FIFO_SIZE 16 +//#define UART0_NBITS 5 +//#define UART0_NBITS 6 +//#define UART0_NBITS 7 +#define UART0_NBITS 8 +//#define UART0_NBITS 9 + +#define UART0_PARITY UART_PARTITY_NONE +//#define UART0_PARITY UART_PARTITY_ODD +//#define UART0_PARITY UART_PARTITY_EVEN + +#define UART0_STOP_BIT UART_STOP_BITS_1 +//#define UART0_STOP_BIT UART_STOP_BITS_2 + + + + +/* .... same for uart 1, 2, 3 ... */ + +#endif +