From: Rasesh Mody Date: Wed, 19 Oct 2016 04:11:16 +0000 (-0700) Subject: net/qede/base: formatting changes X-Git-Tag: spdx-start~5464 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=d2e7d931d0ad;p=dpdk.git net/qede/base: formatting changes Fixes white spaces and tabs. Signed-off-by: Rasesh Mody --- diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h index 295a41f946..4574800a9a 100644 --- a/drivers/net/qede/base/common_hsi.h +++ b/drivers/net/qede/base/common_hsi.h @@ -9,9 +9,9 @@ #ifndef __COMMON_HSI__ #define __COMMON_HSI__ -#define CORE_SPQE_PAGE_SIZE_BYTES 4096 +#define CORE_SPQE_PAGE_SIZE_BYTES 4096 -#define FW_MAJOR_VERSION 8 +#define FW_MAJOR_VERSION 8 #define FW_MINOR_VERSION 7 #define FW_REVISION_VERSION 7 #define FW_ENGINEERING_VERSION 0 @@ -21,68 +21,68 @@ /***********************/ /* PCI functions */ -#define MAX_NUM_PORTS_K2 (4) -#define MAX_NUM_PORTS_BB (2) -#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) +#define MAX_NUM_PORTS_K2 (4) +#define MAX_NUM_PORTS_BB (2) +#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) -#define MAX_NUM_PFS_K2 (16) -#define MAX_NUM_PFS_BB (8) -#define MAX_NUM_PFS (MAX_NUM_PFS_K2) -#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ +#define MAX_NUM_PFS_K2 (16) +#define MAX_NUM_PFS_BB (8) +#define MAX_NUM_PFS (MAX_NUM_PFS_K2) +#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ -#define MAX_NUM_VFS_K2 (192) -#define MAX_NUM_VFS_BB (120) -#define MAX_NUM_VFS (MAX_NUM_VFS_K2) +#define MAX_NUM_VFS_K2 (192) +#define MAX_NUM_VFS_BB (120) +#define MAX_NUM_VFS (MAX_NUM_VFS_K2) #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) -#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) +#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) -#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) +#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) -#define MAX_NUM_VPORTS_K2 (208) -#define MAX_NUM_VPORTS_BB (160) -#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) +#define MAX_NUM_VPORTS_K2 (208) +#define MAX_NUM_VPORTS_BB (160) +#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) #define MAX_NUM_L2_QUEUES_K2 (320) #define MAX_NUM_L2_QUEUES_BB (256) -#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) +#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ #define NUM_PHYS_TCS_4PORT_K2 (4) -#define NUM_OF_PHYS_TCS (8) +#define NUM_OF_PHYS_TCS (8) -#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) -#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) +#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) +#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) -#define LB_TC (NUM_OF_PHYS_TCS) +#define LB_TC (NUM_OF_PHYS_TCS) /* Num of possible traffic priority values */ -#define NUM_OF_PRIO (8) +#define NUM_OF_PRIO (8) -#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) -#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) -#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) -#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) +#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) +#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) +#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) +#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) /* CIDs */ -#define NUM_OF_CONNECTION_TYPES (8) -#define NUM_OF_LCIDS (320) -#define NUM_OF_LTIDS (320) +#define NUM_OF_CONNECTION_TYPES (8) +#define NUM_OF_LCIDS (320) +#define NUM_OF_LTIDS (320) /*****************/ /* CDU CONSTANTS */ /*****************/ -#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) -#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) +#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) +#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) /*****************/ /* DQ CONSTANTS */ /*****************/ /* DEMS */ -#define DQ_DEMS_LEGACY 0 +#define DQ_DEMS_LEGACY 0 /* XCM agg val selection */ #define DQ_XCM_AGG_VAL_SEL_WORD2 0 @@ -107,7 +107,7 @@ DQ_XCM_AGG_VAL_SEL_WORD4 #define DQ_XCM_CORE_SPQ_PROD_CMD \ DQ_XCM_AGG_VAL_SEL_WORD4 -#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 +#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 /* XCM agg counter flag selection */ #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 @@ -140,22 +140,22 @@ /*****************/ /* number of TX queues in the QM */ -#define MAX_QM_TX_QUEUES_K2 512 -#define MAX_QM_TX_QUEUES_BB 448 -#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 +#define MAX_QM_TX_QUEUES_K2 512 +#define MAX_QM_TX_QUEUES_BB 448 +#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 /* number of Other queues in the QM */ -#define MAX_QM_OTHER_QUEUES_BB 64 -#define MAX_QM_OTHER_QUEUES_K2 128 -#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 +#define MAX_QM_OTHER_QUEUES_BB 64 +#define MAX_QM_OTHER_QUEUES_K2 128 +#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 /* number of queues in a PF queue group */ -#define QM_PF_QUEUE_GROUP_SIZE 8 +#define QM_PF_QUEUE_GROUP_SIZE 8 /* base number of Tx PQs in the CM PQ representation. * should be used when storing PQ IDs in CM PQ registers and context */ -#define CM_TX_PQ_BASE 0x200 +#define CM_TX_PQ_BASE 0x200 /* QM registers data */ #define QM_LINE_CRD_REG_WIDTH 16 @@ -164,7 +164,7 @@ #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) #define QM_WFQ_CRD_REG_WIDTH 32 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) -#define QM_RL_CRD_REG_WIDTH 32 +#define QM_RL_CRD_REG_WIDTH 32 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) /*****************/ @@ -185,100 +185,100 @@ /* IGU CONSTANTS */ /*****************/ -#define MAX_SB_PER_PATH_K2 (368) -#define MAX_SB_PER_PATH_BB (288) +#define MAX_SB_PER_PATH_K2 (368) +#define MAX_SB_PER_PATH_BB (288) #define MAX_TOT_SB_PER_PATH \ MAX_SB_PER_PATH_K2 -#define MAX_SB_PER_PF_MIMD 129 -#define MAX_SB_PER_PF_SIMD 64 -#define MAX_SB_PER_VF 64 +#define MAX_SB_PER_PF_MIMD 129 +#define MAX_SB_PER_PF_SIMD 64 +#define MAX_SB_PER_VF 64 /* Memory addresses on the BAR for the IGU Sub Block */ -#define IGU_MEM_BASE 0x0000 +#define IGU_MEM_BASE 0x0000 -#define IGU_MEM_MSIX_BASE 0x0000 -#define IGU_MEM_MSIX_UPPER 0x0101 -#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff +#define IGU_MEM_MSIX_BASE 0x0000 +#define IGU_MEM_MSIX_UPPER 0x0101 +#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff -#define IGU_MEM_PBA_MSIX_BASE 0x0200 -#define IGU_MEM_PBA_MSIX_UPPER 0x0202 -#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff +#define IGU_MEM_PBA_MSIX_BASE 0x0200 +#define IGU_MEM_PBA_MSIX_UPPER 0x0202 +#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff -#define IGU_CMD_INT_ACK_BASE 0x0400 +#define IGU_CMD_INT_ACK_BASE 0x0400 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ MAX_TOT_SB_PER_PATH - \ 1) -#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff +#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff -#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 -#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 -#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 +#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 +#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 +#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 -#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 -#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 -#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 -#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 +#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 +#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 +#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 +#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 -#define IGU_CMD_PROD_UPD_BASE 0x0600 +#define IGU_CMD_PROD_UPD_BASE 0x0600 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ MAX_TOT_SB_PER_PATH - \ 1) -#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff +#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff /*****************/ /* PXP CONSTANTS */ /*****************/ /* PTT and GTT */ -#define PXP_NUM_PF_WINDOWS 12 -#define PXP_PER_PF_ENTRY_SIZE 8 -#define PXP_NUM_GLOBAL_WINDOWS 243 -#define PXP_GLOBAL_ENTRY_SIZE 4 -#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 -#define PXP_PF_WINDOW_ADMIN_START 0 -#define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 +#define PXP_NUM_PF_WINDOWS 12 +#define PXP_PER_PF_ENTRY_SIZE 8 +#define PXP_NUM_GLOBAL_WINDOWS 243 +#define PXP_GLOBAL_ENTRY_SIZE 4 +#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 +#define PXP_PF_WINDOW_ADMIN_START 0 +#define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ PXP_PF_WINDOW_ADMIN_LENGTH - 1) -#define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 +#define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ PXP_PER_PF_ENTRY_SIZE) #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ - PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) -#define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) +#define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ PXP_GLOBAL_ENTRY_SIZE) -#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ - (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ - PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) -#define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 -#define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 -#define PXP_PF_ME_OPAQUE_ADDR 0x1f8 -#define PXP_PF_ME_CONCRETE_ADDR 0x1fc - -#define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 -#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS -#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 -#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ - (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ +#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ + (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) +#define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 +#define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 +#define PXP_PF_ME_OPAQUE_ADDR 0x1f8 +#define PXP_PF_ME_CONCRETE_ADDR 0x1fc + +#define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 +#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS +#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 +#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ + (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) -#define PXP_EXTERNAL_BAR_PF_WINDOW_END \ - (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ +#define PXP_EXTERNAL_BAR_PF_WINDOW_END \ + (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) -#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ +#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS -#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 -#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ - (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ +#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 +#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ + (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) -#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ - (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ +#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ + (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) -#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 -#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 +#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 +#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 /* ILT Records */ #define PXP_NUM_ILT_RECORDS_BB 7600 @@ -301,10 +301,10 @@ /* Async data KCQ CQE */ struct async_data { - __le32 cid; - __le16 itid; - u8 error_code; - u8 fw_debug_param; + __le32 cid; + __le16 itid; + u8 error_code; + u8 fw_debug_param; }; struct regpair { @@ -359,12 +359,12 @@ struct event_ring_entry { __le16 reserved0; __le16 echo; u8 fw_return_code; - u8 flags; + u8 flags; #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 - union event_ring_data data; + union event_ring_data data; }; /* Multi function mode */ @@ -444,8 +444,8 @@ struct core_db_data { #define CORE_DB_DATA_RESERVED_SHIFT 5 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 - u8 agg_flags; - __le16 spq_prod; + u8 agg_flags; + __le16 spq_prod; }; /* Enum of doorbell aggregative command selection */ @@ -479,10 +479,10 @@ struct db_legacy_addr { /* Igu interrupt command */ enum igu_int_cmd { - IGU_INT_ENABLE = 0, + IGU_INT_ENABLE = 0, IGU_INT_DISABLE = 1, - IGU_INT_NOP = 2, - IGU_INT_NOP2 = 3, + IGU_INT_NOP = 2, + IGU_INT_NOP2 = 3, MAX_IGU_INT_CMD }; @@ -508,8 +508,8 @@ struct igu_prod_cons_update { /* Igu segments access for default status block only */ enum igu_seg_access { - IGU_SEG_ACCESS_REG = 0, - IGU_SEG_ACCESS_ATTN = 1, + IGU_SEG_ACCESS_REG = 0, + IGU_SEG_ACCESS_ATTN = 1, MAX_IGU_SEG_ACCESS }; @@ -574,13 +574,13 @@ struct pxp_pretend_concrete_fid { union pxp_pretend_fid { struct pxp_pretend_concrete_fid concrete_fid; - __le16 opaque_fid; + __le16 opaque_fid; }; /* Pxp Pretend Command Register. */ struct pxp_pretend_cmd { - union pxp_pretend_fid fid; - __le16 control; + union pxp_pretend_fid fid; + __le16 control; #define PXP_PRETEND_CMD_PATH_MASK 0x1 #define PXP_PRETEND_CMD_PATH_SHIFT 0 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 @@ -603,30 +603,30 @@ struct pxp_pretend_cmd { /* PTT Record in PXP Admin Window. */ struct pxp_ptt_entry { - __le32 offset; + __le32 offset; #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 - struct pxp_pretend_cmd pretend; + struct pxp_pretend_cmd pretend; }; /* RSS hash type */ enum rss_hash_type { - RSS_HASH_TYPE_DEFAULT = 0, - RSS_HASH_TYPE_IPV4 = 1, - RSS_HASH_TYPE_TCP_IPV4 = 2, - RSS_HASH_TYPE_IPV6 = 3, - RSS_HASH_TYPE_TCP_IPV6 = 4, - RSS_HASH_TYPE_UDP_IPV4 = 5, - RSS_HASH_TYPE_UDP_IPV6 = 6, + RSS_HASH_TYPE_DEFAULT = 0, + RSS_HASH_TYPE_IPV4 = 1, + RSS_HASH_TYPE_TCP_IPV4 = 2, + RSS_HASH_TYPE_IPV6 = 3, + RSS_HASH_TYPE_TCP_IPV6 = 4, + RSS_HASH_TYPE_UDP_IPV4 = 5, + RSS_HASH_TYPE_UDP_IPV6 = 6, MAX_RSS_HASH_TYPE }; /* status block structure */ struct status_block { - __le16 pi_array[PIS_PER_SB]; - __le32 sb_num; + __le16 pi_array[PIS_PER_SB]; + __le32 sb_num; #define STATUS_BLOCK_SB_NUM_MASK 0x1FF #define STATUS_BLOCK_SB_NUM_SHIFT 0 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index db72f0333f..c83b22bf51 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -21,7 +21,7 @@ #define VER_SIZE 16 /* @DPDK ARRAY_DECL */ #define ECORE_WFQ_UNIT 100 -#include "../qede_logs.h" /* @DPDK */ +#include "../qede_logs.h" /* @DPDK */ /* Constants */ #define ECORE_WID_SIZE (1024) @@ -77,7 +77,7 @@ do { \ static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) { u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | - (cid * ECORE_PF_DEMS_SIZE); + (cid * ECORE_PF_DEMS_SIZE); return db_addr; } @@ -105,10 +105,10 @@ static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) #ifndef __EXTRACT__LINUX__ enum DP_LEVEL { - ECORE_LEVEL_VERBOSE = 0x0, - ECORE_LEVEL_INFO = 0x1, - ECORE_LEVEL_NOTICE = 0x2, - ECORE_LEVEL_ERR = 0x3, + ECORE_LEVEL_VERBOSE = 0x0, + ECORE_LEVEL_INFO = 0x1, + ECORE_LEVEL_NOTICE = 0x2, + ECORE_LEVEL_ERR = 0x3, }; #define ECORE_LOG_LEVEL_SHIFT (30) @@ -118,31 +118,31 @@ enum DP_LEVEL { enum DP_MODULE { #ifndef LINUX_REMOVE - ECORE_MSG_DRV = 0x0001, - ECORE_MSG_PROBE = 0x0002, - ECORE_MSG_LINK = 0x0004, - ECORE_MSG_TIMER = 0x0008, - ECORE_MSG_IFDOWN = 0x0010, - ECORE_MSG_IFUP = 0x0020, - ECORE_MSG_RX_ERR = 0x0040, - ECORE_MSG_TX_ERR = 0x0080, - ECORE_MSG_TX_QUEUED = 0x0100, - ECORE_MSG_INTR = 0x0200, - ECORE_MSG_TX_DONE = 0x0400, - ECORE_MSG_RX_STATUS = 0x0800, - ECORE_MSG_PKTDATA = 0x1000, - ECORE_MSG_HW = 0x2000, - ECORE_MSG_WOL = 0x4000, + ECORE_MSG_DRV = 0x0001, + ECORE_MSG_PROBE = 0x0002, + ECORE_MSG_LINK = 0x0004, + ECORE_MSG_TIMER = 0x0008, + ECORE_MSG_IFDOWN = 0x0010, + ECORE_MSG_IFUP = 0x0020, + ECORE_MSG_RX_ERR = 0x0040, + ECORE_MSG_TX_ERR = 0x0080, + ECORE_MSG_TX_QUEUED = 0x0100, + ECORE_MSG_INTR = 0x0200, + ECORE_MSG_TX_DONE = 0x0400, + ECORE_MSG_RX_STATUS = 0x0800, + ECORE_MSG_PKTDATA = 0x1000, + ECORE_MSG_HW = 0x2000, + ECORE_MSG_WOL = 0x4000, #endif - ECORE_MSG_SPQ = 0x10000, - ECORE_MSG_STATS = 0x20000, - ECORE_MSG_DCB = 0x40000, - ECORE_MSG_IOV = 0x80000, - ECORE_MSG_SP = 0x100000, - ECORE_MSG_STORAGE = 0x200000, - ECORE_MSG_CXT = 0x800000, - ECORE_MSG_ILT = 0x2000000, - ECORE_MSG_DEBUG = 0x8000000, + ECORE_MSG_SPQ = 0x10000, + ECORE_MSG_STATS = 0x20000, + ECORE_MSG_DCB = 0x40000, + ECORE_MSG_IOV = 0x80000, + ECORE_MSG_SP = 0x100000, + ECORE_MSG_STORAGE = 0x200000, + ECORE_MSG_CXT = 0x800000, + ECORE_MSG_ILT = 0x2000000, + ECORE_MSG_DEBUG = 0x8000000, /* to be added...up to 0x8000000 */ }; #endif @@ -166,8 +166,8 @@ struct ecore_mcp_info; struct ecore_dcbx_info; struct ecore_rt_data { - u32 *init_val; - bool *b_valid; + u32 *init_val; + bool *b_valid; }; enum ecore_tunn_mode { @@ -188,31 +188,31 @@ enum ecore_tunn_clss { struct ecore_tunn_start_params { unsigned long tunn_mode; - u16 vxlan_udp_port; - u16 geneve_udp_port; - u8 update_vxlan_udp_port; - u8 update_geneve_udp_port; - u8 tunn_clss_vxlan; - u8 tunn_clss_l2geneve; - u8 tunn_clss_ipgeneve; - u8 tunn_clss_l2gre; - u8 tunn_clss_ipgre; + u16 vxlan_udp_port; + u16 geneve_udp_port; + u8 update_vxlan_udp_port; + u8 update_geneve_udp_port; + u8 tunn_clss_vxlan; + u8 tunn_clss_l2geneve; + u8 tunn_clss_ipgeneve; + u8 tunn_clss_l2gre; + u8 tunn_clss_ipgre; }; struct ecore_tunn_update_params { unsigned long tunn_mode_update_mask; unsigned long tunn_mode; - u16 vxlan_udp_port; - u16 geneve_udp_port; - u8 update_rx_pf_clss; - u8 update_tx_pf_clss; - u8 update_vxlan_udp_port; - u8 update_geneve_udp_port; - u8 tunn_clss_vxlan; - u8 tunn_clss_l2geneve; - u8 tunn_clss_ipgeneve; - u8 tunn_clss_l2gre; - u8 tunn_clss_ipgre; + u16 vxlan_udp_port; + u16 geneve_udp_port; + u8 update_rx_pf_clss; + u8 update_tx_pf_clss; + u8 update_vxlan_udp_port; + u8 update_geneve_udp_port; + u8 tunn_clss_vxlan; + u8 tunn_clss_l2geneve; + u8 tunn_clss_ipgeneve; + u8 tunn_clss_l2gre; + u8 tunn_clss_ipgre; }; struct ecore_hw_sriov_info { @@ -244,7 +244,7 @@ struct ecore_hw_sriov_info { */ enum ecore_pci_personality { ECORE_PCI_ETH, - ECORE_PCI_DEFAULT /* default in shmem */ + ECORE_PCI_DEFAULT /* default in shmem */ }; /* All VFs are symmetric, all counters are PF + all VFs */ @@ -322,11 +322,11 @@ struct ecore_hw_info { u32 resc_num[ECORE_MAX_RESC]; u32 feat_num[ECORE_MAX_FEATURES]; -#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) -#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) -#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ + #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) + #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) + #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ RESC_NUM(_p_hwfn, resc)) -#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) + #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) u8 num_tc; u8 ooo_tc; @@ -346,18 +346,18 @@ struct ecore_hw_info { u8 max_chains_per_vf; u32 port_mode; - u32 hw_mode; + u32 hw_mode; unsigned long device_capabilities; }; struct ecore_hw_cid_data { - u32 cid; - bool b_cid_allocated; - u8 vfid; /* 1-based; 0 signals this is for a PF */ + u32 cid; + bool b_cid_allocated; + u8 vfid; /* 1-based; 0 signals this is for a PF */ /* Additional identifiers */ - u16 opaque_fid; - u8 vport_id; + u16 opaque_fid; + u8 vport_id; }; /* maximun size of read/write commands (HW limit) */ @@ -365,7 +365,7 @@ struct ecore_hw_cid_data { struct ecore_dmae_info { /* Mutex for synchronizing access to functions */ - osal_mutex_t mutex; + osal_mutex_t mutex; u8 channel; @@ -389,33 +389,33 @@ struct ecore_dmae_info { }; struct ecore_wfq_data { - u32 default_min_speed; /* When wfq feature is not configured */ - u32 min_speed; /* when feature is configured for any 1 vport */ + u32 default_min_speed; /* When wfq feature is not configured */ + u32 min_speed; /* when feature is configured for any 1 vport */ bool configured; }; struct ecore_qm_info { - struct init_qm_pq_params *qm_pq_params; + struct init_qm_pq_params *qm_pq_params; struct init_qm_vport_params *qm_vport_params; - struct init_qm_port_params *qm_port_params; - u16 start_pq; - u8 start_vport; - u8 pure_lb_pq; - u8 offload_pq; - u8 pure_ack_pq; - u8 ooo_pq; - u8 vf_queues_offset; - u16 num_pqs; - u16 num_vf_pqs; - u8 num_vports; - u8 max_phys_tcs_per_port; - bool pf_rl_en; - bool pf_wfq_en; - bool vport_rl_en; - bool vport_wfq_en; - u8 pf_wfq; - u32 pf_rl; - struct ecore_wfq_data *wfq_data; + struct init_qm_port_params *qm_port_params; + u16 start_pq; + u8 start_vport; + u8 pure_lb_pq; + u8 offload_pq; + u8 pure_ack_pq; + u8 ooo_pq; + u8 vf_queues_offset; + u16 num_pqs; + u16 num_vf_pqs; + u8 num_vports; + u8 max_phys_tcs_per_port; + bool pf_rl_en; + bool pf_wfq_en; + bool vport_rl_en; + bool vport_wfq_en; + u8 pf_wfq; + u32 pf_rl; + struct ecore_wfq_data *wfq_data; }; struct storm_stats { @@ -437,106 +437,106 @@ struct ecore_fw_data { }; struct ecore_hwfn { - struct ecore_dev *p_dev; - u8 my_id; /* ID inside the PF */ + struct ecore_dev *p_dev; + u8 my_id; /* ID inside the PF */ #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) - u8 rel_pf_id; /* Relative to engine */ - u8 abs_pf_id; -#define ECORE_PATH_ID(_p_hwfn) \ + u8 rel_pf_id; /* Relative to engine*/ + u8 abs_pf_id; + #define ECORE_PATH_ID(_p_hwfn) \ (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) - u8 port_id; - bool b_active; + u8 port_id; + bool b_active; - u32 dp_module; - u8 dp_level; - char name[NAME_SIZE]; - void *dp_ctx; + u32 dp_module; + u8 dp_level; + char name[NAME_SIZE]; + void *dp_ctx; - bool first_on_engine; - bool hw_init_done; + bool first_on_engine; + bool hw_init_done; - u8 num_funcs_on_engine; + u8 num_funcs_on_engine; /* BAR access */ - void OSAL_IOMEM *regview; - void OSAL_IOMEM *doorbells; - u64 db_phys_addr; - unsigned long db_size; + void OSAL_IOMEM *regview; + void OSAL_IOMEM *doorbells; + u64 db_phys_addr; + unsigned long db_size; /* PTT pool */ - struct ecore_ptt_pool *p_ptt_pool; + struct ecore_ptt_pool *p_ptt_pool; /* HW info */ - struct ecore_hw_info hw_info; + struct ecore_hw_info hw_info; /* rt_array (for init-tool) */ - struct ecore_rt_data rt_data; + struct ecore_rt_data rt_data; /* SPQ */ - struct ecore_spq *p_spq; + struct ecore_spq *p_spq; /* EQ */ - struct ecore_eq *p_eq; + struct ecore_eq *p_eq; - /* Consolidate Q */ - struct ecore_consq *p_consq; + /* Consolidate Q*/ + struct ecore_consq *p_consq; /* Slow-Path definitions */ - osal_dpc_t sp_dpc; - bool b_sp_dpc_enabled; + osal_dpc_t sp_dpc; + bool b_sp_dpc_enabled; - struct ecore_ptt *p_main_ptt; - struct ecore_ptt *p_dpc_ptt; + struct ecore_ptt *p_main_ptt; + struct ecore_ptt *p_dpc_ptt; - struct ecore_sb_sp_info *p_sp_sb; - struct ecore_sb_attn_info *p_sb_attn; + struct ecore_sb_sp_info *p_sp_sb; + struct ecore_sb_attn_info *p_sb_attn; /* Protocol related */ - struct ecore_ooo_info *p_ooo_info; - struct ecore_pf_params pf_params; + struct ecore_ooo_info *p_ooo_info; + struct ecore_pf_params pf_params; /* Array of sb_info of all status blocks */ - struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; - u16 num_sbs; + struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; + u16 num_sbs; - struct ecore_cxt_mngr *p_cxt_mngr; + struct ecore_cxt_mngr *p_cxt_mngr; - /* Flag indicating whether interrupts are enabled or not */ - bool b_int_enabled; - bool b_int_requested; + /* Flag indicating whether interrupts are enabled or not*/ + bool b_int_enabled; + bool b_int_requested; /* True if the driver requests for the link */ - bool b_drv_link_init; + bool b_drv_link_init; - struct ecore_vf_iov *vf_iov_info; - struct ecore_pf_iov *pf_iov_info; - struct ecore_mcp_info *mcp_info; - struct ecore_dcbx_info *p_dcbx_info; + struct ecore_vf_iov *vf_iov_info; + struct ecore_pf_iov *pf_iov_info; + struct ecore_mcp_info *mcp_info; + struct ecore_dcbx_info *p_dcbx_info; - struct ecore_hw_cid_data *p_tx_cids; - struct ecore_hw_cid_data *p_rx_cids; + struct ecore_hw_cid_data *p_tx_cids; + struct ecore_hw_cid_data *p_rx_cids; - struct ecore_dmae_info dmae_info; + struct ecore_dmae_info dmae_info; /* QM init */ - struct ecore_qm_info qm_info; + struct ecore_qm_info qm_info; /* Buffer for unzipping firmware data */ #ifdef CONFIG_ECORE_ZIPPED_FW void *unzip_buf; #endif - struct dbg_tools_data dbg_info; + struct dbg_tools_data dbg_info; - struct z_stream_s *stream; + struct z_stream_s *stream; /* PWM region specific data */ - u32 dpi_size; - u32 dpi_count; - u32 dpi_start_offset; /* this is used to - * calculate th - * doorbell address - */ + u32 dpi_size; + u32 dpi_count; + u32 dpi_start_offset; /* this is used to + * calculate th + * doorbell address + */ }; #ifndef __EXTRACT__LINUX__ @@ -548,12 +548,12 @@ enum ecore_mf_mode { #endif struct ecore_dev { - u32 dp_module; - u8 dp_level; - char name[NAME_SIZE]; - void *dp_ctx; + u32 dp_module; + u8 dp_level; + char name[NAME_SIZE]; + void *dp_ctx; - u8 type; + u8 type; #define ECORE_DEV_TYPE_BB (0 << 0) #define ECORE_DEV_TYPE_AH (1 << 0) /* Translate type/revision combo into the proper conditions */ @@ -571,112 +571,112 @@ struct ecore_dev { u16 vendor_id; u16 device_id; - u16 chip_num; -#define CHIP_NUM_MASK 0xffff -#define CHIP_NUM_SHIFT 16 + u16 chip_num; + #define CHIP_NUM_MASK 0xffff + #define CHIP_NUM_SHIFT 16 - u16 chip_rev; -#define CHIP_REV_MASK 0xf -#define CHIP_REV_SHIFT 12 + u16 chip_rev; + #define CHIP_REV_MASK 0xf + #define CHIP_REV_SHIFT 12 #ifndef ASIC_ONLY -#define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) -#define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) -#define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) -#define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \ + #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) + #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) + #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) + #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \ CHIP_REV_IS_EMUL_B0(_p_dev)) -#define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) -#define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) -#define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \ + #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) + #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) + #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \ CHIP_REV_IS_FPGA_B0(_p_dev)) -#define CHIP_REV_IS_SLOW(_p_dev) \ + #define CHIP_REV_IS_SLOW(_p_dev) \ (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) -#define CHIP_REV_IS_A0(_p_dev) \ + #define CHIP_REV_IS_A0(_p_dev) \ (CHIP_REV_IS_EMUL_A0(_p_dev) || \ CHIP_REV_IS_FPGA_A0(_p_dev) || \ !(_p_dev)->chip_rev) -#define CHIP_REV_IS_B0(_p_dev) \ + #define CHIP_REV_IS_B0(_p_dev) \ (CHIP_REV_IS_EMUL_B0(_p_dev) || \ CHIP_REV_IS_FPGA_B0(_p_dev) || \ (_p_dev)->chip_rev == 1) #define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev)) #else -#define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev) -#define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1) + #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev) + #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1) #endif - u16 chip_metal; -#define CHIP_METAL_MASK 0xff -#define CHIP_METAL_SHIFT 4 + u16 chip_metal; + #define CHIP_METAL_MASK 0xff + #define CHIP_METAL_SHIFT 4 - u16 chip_bond_id; -#define CHIP_BOND_ID_MASK 0xf -#define CHIP_BOND_ID_SHIFT 0 + u16 chip_bond_id; + #define CHIP_BOND_ID_MASK 0xf + #define CHIP_BOND_ID_SHIFT 0 - u8 num_engines; - u8 num_ports_in_engines; - u8 num_funcs_in_port; + u8 num_engines; + u8 num_ports_in_engines; + u8 num_funcs_in_port; - u8 path_id; - enum ecore_mf_mode mf_mode; -#define IS_MF_DEFAULT(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) + u8 path_id; + enum ecore_mf_mode mf_mode; + #define IS_MF_DEFAULT(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) - int pcie_width; - int pcie_speed; + int pcie_width; + int pcie_speed; u8 ver_str[VER_SIZE]; /* Add MF related configuration */ - u8 mcp_rev; - u8 boot_mode; + u8 mcp_rev; + u8 boot_mode; - u8 wol; + u8 wol; - u32 int_mode; - enum ecore_coalescing_mode int_coalescing_mode; + u32 int_mode; + enum ecore_coalescing_mode int_coalescing_mode; u8 rx_coalesce_usecs; u8 tx_coalesce_usecs; /* Start Bar offset of first hwfn */ - void OSAL_IOMEM *regview; - void OSAL_IOMEM *doorbells; - u64 db_phys_addr; - unsigned long db_size; + void OSAL_IOMEM *regview; + void OSAL_IOMEM *doorbells; + u64 db_phys_addr; + unsigned long db_size; /* PCI */ - u8 cache_shift; + u8 cache_shift; /* Init */ - const struct iro *iro_arr; -#define IRO (p_hwfn->p_dev->iro_arr) + const struct iro *iro_arr; + #define IRO (p_hwfn->p_dev->iro_arr) /* HW functions */ - u8 num_hwfns; - struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; + u8 num_hwfns; + struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; /* SRIOV */ struct ecore_hw_sriov_info sriov_info; - unsigned long tunn_mode; + unsigned long tunn_mode; #define IS_ECORE_SRIOV(edev) (!!((edev)->sriov_info.total_vfs)) - bool b_is_vf; + bool b_is_vf; - u32 drv_type; + u32 drv_type; - struct ecore_eth_stats *reset_stats; - struct ecore_fw_data *fw_data; + struct ecore_eth_stats *reset_stats; + struct ecore_fw_data *fw_data; - u32 mcp_nvm_resp; + u32 mcp_nvm_resp; /* Recovery */ - bool recov_in_prog; + bool recov_in_prog; #ifndef ASIC_ONLY - bool b_is_emul_full; + bool b_is_emul_full; #endif - void *firmware; + void *firmware; - u64 fw_len; + u64 fw_len; }; @@ -707,10 +707,10 @@ struct ecore_dev { * @return OSAL_INLINE u8 */ static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev, - u32 concrete_fid) + u32 concrete_fid) { - u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); - u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); + u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); + u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); u8 sw_fid; diff --git a/drivers/net/qede/base/ecore_chain.h b/drivers/net/qede/base/ecore_chain.h index c57344902f..bc18c41d42 100644 --- a/drivers/net/qede/base/ecore_chain.h +++ b/drivers/net/qede/base/ecore_chain.h @@ -129,7 +129,7 @@ struct ecore_chain { (1 + ((sizeof(struct ecore_chain_next) - 1) / \ (elem_size))) : 0) -#define USABLE_ELEMS_PER_PAGE(elem_size, mode) \ +#define USABLE_ELEMS_PER_PAGE(elem_size, mode) \ ((u32)(ELEMS_PER_PAGE(elem_size) - \ UNUSABLE_ELEMS_PER_PAGE(elem_size, mode))) @@ -183,7 +183,7 @@ static OSAL_INLINE u16 ecore_chain_get_elem_left(struct ecore_chain *p_chain) (u32)p_chain->u.chain16.cons_idx); if (p_chain->mode == ECORE_CHAIN_MODE_NEXT_PTR) used -= p_chain->u.chain16.prod_idx / p_chain->elem_per_page - - p_chain->u.chain16.cons_idx / p_chain->elem_per_page; + p_chain->u.chain16.cons_idx / p_chain->elem_per_page; return (u16)(p_chain->capacity - used); } @@ -196,11 +196,11 @@ ecore_chain_get_elem_left_u32(struct ecore_chain *p_chain) OSAL_ASSERT(is_chain_u32(p_chain)); used = (u32)(((u64)ECORE_U32_MAX + 1 + - (u64)(p_chain->u.chain32.prod_idx)) - - (u64)p_chain->u.chain32.cons_idx); + (u64)(p_chain->u.chain32.prod_idx)) - + (u64)p_chain->u.chain32.cons_idx); if (p_chain->mode == ECORE_CHAIN_MODE_NEXT_PTR) used -= p_chain->u.chain32.prod_idx / p_chain->elem_per_page - - p_chain->u.chain32.cons_idx / p_chain->elem_per_page; + p_chain->u.chain32.cons_idx / p_chain->elem_per_page; return p_chain->capacity - used; } @@ -518,14 +518,14 @@ static OSAL_INLINE void ecore_chain_reset(struct ecore_chain *p_chain) switch (p_chain->intended_use) { case ECORE_CHAIN_USE_TO_CONSUME_PRODUCE: case ECORE_CHAIN_USE_TO_PRODUCE: - /* Do nothing */ - break; + /* Do nothing */ + break; case ECORE_CHAIN_USE_TO_CONSUME: - /* produce empty elements */ - for (i = 0; i < p_chain->capacity; i++) + /* produce empty elements */ + for (i = 0; i < p_chain->capacity; i++) ecore_chain_recycle_consumed(p_chain); - break; + break; } } diff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c index 1201c1a9e7..415d1c8ea6 100644 --- a/drivers/net/qede/base/ecore_cxt.c +++ b/drivers/net/qede/base/ecore_cxt.c @@ -807,8 +807,8 @@ static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients) if (!ilt_clients[i].active) continue; else - size += (ilt_clients[i].last.val - - ilt_clients[i].first.val + 1); + size += (ilt_clients[i].last.val - + ilt_clients[i].first.val + 1); return size; } @@ -1027,8 +1027,8 @@ enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn) p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; /* Initialize task sizes */ - p_mngr->task_type_size[0] = 512; /* @DPDK */ - p_mngr->task_type_size[1] = 128; /* @DPDK */ + p_mngr->task_type_size[0] = 512; /* @DPDK */ + p_mngr->task_type_size[1] = 128; /* @DPDK */ p_mngr->vf_count = p_hwfn->p_dev->sriov_info.total_vfs; /* Set the cxt mangr pointer priori to further allocations */ @@ -1383,11 +1383,11 @@ static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn) u32 blk_factor; /* For simplicty we set the 'block' to be an ILT page */ - STORE_RT_REG(p_hwfn, - PSWRQ2_REG_VF_BASE_RT_OFFSET, + STORE_RT_REG(p_hwfn, + PSWRQ2_REG_VF_BASE_RT_OFFSET, p_hwfn->hw_info.first_vf_in_pf); - STORE_RT_REG(p_hwfn, - PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, + STORE_RT_REG(p_hwfn, + PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, p_hwfn->hw_info.first_vf_in_pf + p_hwfn->p_dev->sriov_info.total_vfs); diff --git a/drivers/net/qede/base/ecore_cxt_api.h b/drivers/net/qede/base/ecore_cxt_api.h index d98dddb223..90aff3ea44 100644 --- a/drivers/net/qede/base/ecore_cxt_api.h +++ b/drivers/net/qede/base/ecore_cxt_api.h @@ -12,9 +12,9 @@ struct ecore_hwfn; struct ecore_cxt_info { - void *p_cxt; - u32 iid; - enum protocol_type type; + void *p_cxt; + u32 iid; + enum protocol_type type; }; #define MAX_TID_BLOCKS 512 @@ -22,7 +22,7 @@ struct ecore_tid_mem { u32 tid_size; u32 num_tids_per_block; u32 waste; - u8 *blocks[MAX_TID_BLOCKS]; /* 4K */ + u8 *blocks[MAX_TID_BLOCKS]; /* 4K */ }; static OSAL_INLINE void *get_task_mem(struct ecore_tid_mem *info, u32 tid) @@ -49,7 +49,7 @@ static OSAL_INLINE void *get_task_mem(struct ecore_tid_mem *info, u32 tid) * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn, +enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn, enum protocol_type type, u32 *p_cid); diff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c index 6a966cb917..18843c4a12 100644 --- a/drivers/net/qede/base/ecore_dcbx.c +++ b/drivers/net/qede/base/ecore_dcbx.c @@ -116,8 +116,8 @@ ecore_dcbx_set_pf_tcs(struct ecore_hw_info *p_info, if (personality == ECORE_PCI_ETH) p_info->non_offload_tc = tc; else - p_info->offload_tc = tc; - } + p_info->offload_tc = tc; +} } void diff --git a/drivers/net/qede/base/ecore_dcbx_api.h b/drivers/net/qede/base/ecore_dcbx_api.h index 7767d48e70..7cd8ee00b0 100644 --- a/drivers/net/qede/base/ecore_dcbx_api.h +++ b/drivers/net/qede/base/ecore_dcbx_api.h @@ -53,10 +53,10 @@ enum dcbx_protocol_type { struct ecore_dcbx_lldp_remote { u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; - bool enable_rx; - bool enable_tx; - u32 tx_interval; - u32 max_credit; + bool enable_rx; + bool enable_tx; + u32 tx_interval; + u32 max_credit; }; struct ecore_dcbx_lldp_local { @@ -65,17 +65,17 @@ struct ecore_dcbx_lldp_local { }; struct ecore_dcbx_app_prio { - u8 eth; + u8 eth; }; struct ecore_dcbx_params { u32 app_bitmap[DCBX_MAX_APP_PROTOCOL]; - u16 num_app_entries; - bool app_willing; - bool app_valid; - bool ets_willing; - bool ets_enabled; - bool valid; /* Indicate validity of params */ + u16 num_app_entries; + bool app_willing; + bool app_valid; + bool ets_willing; + bool ets_enabled; + bool valid; /* Indicate validity of params */ u32 ets_pri_tc_tbl[1]; u32 ets_tc_bw_tbl[2]; u32 ets_tc_tsa_tbl[2]; @@ -83,7 +83,7 @@ struct ecore_dcbx_params { bool pfc_enabled; u32 pfc_bitmap; u8 max_pfc_tc; - u8 max_ets_tc; + u8 max_ets_tc; }; struct ecore_dcbx_admin_params { @@ -129,7 +129,7 @@ struct ecore_dcbx_results { struct ecore_dcbx_app_metadata { enum dcbx_protocol_type id; - const char *name; /* @DPDK */ + const char *name; /* @DPDK */ enum ecore_pci_personality personality; }; diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 89faa35440..46d3e806f5 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -64,11 +64,11 @@ static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id) return BAR_ID_0 ? 256 * 1024 : 512 * 1024; } - DP_NOTICE(p_hwfn, false, + DP_NOTICE(p_hwfn, false, "BAR size not configured. Assuming BAR" " size of 512kB for GRC and 512kB for DB\n"); - return 512 * 1024; - } + return 512 * 1024; + } return 1 << (val + 15); } @@ -305,7 +305,7 @@ static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn, return ECORE_SUCCESS; -alloc_err: + alloc_err: DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n"); ecore_qm_info_free(p_hwfn); return ECORE_NOMEM; @@ -494,9 +494,9 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev) return ECORE_SUCCESS; -alloc_no_mem: + alloc_no_mem: rc = ECORE_NOMEM; -alloc_err: + alloc_err: ecore_resc_free(p_dev); return rc; } @@ -557,11 +557,11 @@ enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; - /* Make sure notification is not set before initiating final cleanup */ +/* Make sure notification is not set before initiating final cleanup */ if (REG_RD(p_hwfn, addr)) { DP_NOTICE(p_hwfn, false, "Unexpected; Found final cleanup notification " - "before initiating final cleanup\n"); + " before initiating final cleanup\n"); REG_WR(p_hwfn, addr, 0); } @@ -666,7 +666,7 @@ static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn) #ifndef ASIC_ONLY /* MFW-replacement initializations for non-ASIC */ static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt) + struct ecore_ptt *p_ptt) { u32 pl_hv = 1; int i; @@ -907,7 +907,7 @@ static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn, } ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1, - port); + port); ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port); ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port); ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port); @@ -935,10 +935,10 @@ static void ecore_link_init(struct ecore_hwfn *p_hwfn, /* Reset of XMAC */ /* FIXME: move to common start */ ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), - MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */ + MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */ OSAL_MSLEEP(1); ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), - MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */ + MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */ ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1); @@ -1078,7 +1078,7 @@ ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn, p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to * calculate the doorbell * address - */ + */ /* Update registers */ /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ @@ -1319,7 +1319,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); DP_VERBOSE(p_hwfn, ECORE_MSG_SP, - "Load request was sent.Resp:0x%x, Load code: 0x%x\n", + "Load request was sent. Resp:0x%x, Load code: 0x%x\n", rc, load_code); /* Only relevant for recovery: @@ -1411,8 +1411,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, #define ECORE_HW_STOP_RETRY_LIMIT (10) static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev, - struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt) + struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt) { int i; @@ -1436,9 +1436,9 @@ static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev, "Timers linear scans are not over" " [Connection %02x Tasks %02x]\n", (u8)ecore_rd(p_hwfn, p_ptt, - TM_REG_PF_SCAN_ACTIVE_CONN), + TM_REG_PF_SCAN_ACTIVE_CONN), (u8)ecore_rd(p_hwfn, p_ptt, - TM_REG_PF_SCAN_ACTIVE_TASK)); + TM_REG_PF_SCAN_ACTIVE_TASK)); } void ecore_hw_timers_stop_all(struct ecore_dev *p_dev) @@ -1679,7 +1679,7 @@ static void get_function_id(struct ecore_hwfn *p_hwfn) { /* ME Register */ p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, - PXP_PF_ME_OPAQUE_ADDR); + PXP_PF_ME_OPAQUE_ADDR); p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); @@ -1725,7 +1725,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn) struct ecore_sb_cnt_info sb_cnt_info; bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); - OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info)); + OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info)); #ifdef CONFIG_ECORE_SRIOV max_vf_vlan_filters = ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS; @@ -1733,19 +1733,19 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn) max_vf_vlan_filters = 0; #endif - ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info); + ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info); resc_num[ECORE_SB] = OSAL_MIN_T(u32, (MAX_SB_PER_PATH_BB / num_funcs), sb_cnt_info.sb_cnt); resc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 : - MAX_NUM_L2_QUEUES_BB) / num_funcs; + MAX_NUM_L2_QUEUES_BB) / num_funcs; resc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 : MAX_NUM_VPORTS_BB) / num_funcs; resc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : - ETH_RSS_ENGINE_NUM_BB) / num_funcs; + ETH_RSS_ENGINE_NUM_BB) / num_funcs; resc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 : - MAX_QM_TX_QUEUES_BB) / num_funcs; + MAX_QM_TX_QUEUES_BB) / num_funcs; resc_num[ECORE_RL] = 8; resc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; resc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS - @@ -1754,7 +1754,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn) /* TODO - there will be a problem in AH - there are only 11k lines */ resc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : - PXP_NUM_ILT_RECORDS_BB) / num_funcs; + PXP_NUM_ILT_RECORDS_BB) / num_funcs; #ifndef ASIC_ONLY if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { @@ -1840,7 +1840,7 @@ static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn, return ECORE_INVAL; } - /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ +/* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); addr = MCP_REG_SCRATCH + nvm_cfg1_offset + @@ -2003,8 +2003,8 @@ static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn, if (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) { num_funcs = 0; mask = 0xaaaa; - } else { - num_funcs = 1; + } else { + num_funcs = 1; mask = 0x5554; } @@ -2070,12 +2070,12 @@ static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn, p_hwfn->p_dev->num_ports_in_engines = 0; - for (i = 0; i < MAX_NUM_PORTS_K2; i++) { - port = ecore_rd(p_hwfn, p_ptt, - CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); - if (port & 1) - p_hwfn->p_dev->num_ports_in_engines++; - } + for (i = 0; i < MAX_NUM_PORTS_K2; i++) { + port = ecore_rd(p_hwfn, p_ptt, + CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); + if (port & 1) + p_hwfn->p_dev->num_ports_in_engines++; + } } static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, @@ -2095,8 +2095,8 @@ ecore_get_hw_info(struct ecore_hwfn *p_hwfn, enum _ecore_status_t rc; rc = ecore_iov_hw_info(p_hwfn, p_hwfn->p_main_ptt); - if (rc) - return rc; + if (rc) + return rc; /* TODO In get_hw_info, amoungst others: * Get MCP FW revision and determine according to it the supported @@ -2178,7 +2178,7 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev) p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, MISCS_REG_CHIP_NUM); p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, - MISCS_REG_CHIP_REV); + MISCS_REG_CHIP_REV); MASK_FIELD(CHIP_REV, p_dev->chip_rev); @@ -2214,7 +2214,7 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev) MISCS_REG_CHIP_TEST_REG) >> 4; MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id); p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, - MISCS_REG_CHIP_METAL); + MISCS_REG_CHIP_METAL); MASK_FIELD(CHIP_METAL, p_dev->chip_metal); DP_INFO(p_dev->hwfns, "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x" @@ -2344,11 +2344,11 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, #endif return rc; -err2: + err2: ecore_mcp_free(p_hwfn); -err1: + err1: ecore_hw_hwfn_free(p_hwfn); -err0: + err0: return rc; } @@ -2361,7 +2361,7 @@ enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality) return ecore_vf_hw_prepare(p_dev); /* Store the precompiled init data ptrs */ - ecore_init_iro_array(p_dev); + ecore_init_iro_array(p_dev); /* Initialize the first hwfn - will learn number of hwfns */ rc = ecore_hw_prepare_single(p_hwfn, @@ -2490,7 +2490,7 @@ static void ecore_chain_free_pbl(struct ecore_dev *p_dev, pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table, pbl_size); -out: + out: OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl); } @@ -2692,7 +2692,7 @@ enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev, return ECORE_SUCCESS; -nomem: + nomem: ecore_chain_free(p_dev, p_chain); return rc; } @@ -2848,7 +2848,7 @@ void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, } enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, + struct ecore_ptt *p_ptt, u16 filter) { u32 high, low, en; @@ -2887,7 +2887,7 @@ enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn, return ECORE_INVAL; } - DP_VERBOSE(p_hwfn, ECORE_MSG_HW, + DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "ETH type: %x is added at %d\n", filter, i); return ECORE_SUCCESS; @@ -2952,7 +2952,7 @@ void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, } enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt) + struct ecore_ptt *p_ptt) { u32 reg_tbl[] = { BRB_REG_HEADER_SIZE, @@ -3032,8 +3032,8 @@ enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn, } } } - return ECORE_SUCCESS; -} + return ECORE_SUCCESS; + } static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, @@ -3089,7 +3089,7 @@ enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn, goto out; p_hwfn->p_dev->rx_coalesce_usecs = coalesce; -out: + out: return rc; } @@ -3119,7 +3119,7 @@ enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn, goto out; p_hwfn->p_dev->tx_coalesce_usecs = coalesce; -out: + out: return rc; } @@ -3305,16 +3305,16 @@ static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn, if (p_hwfn->qm_info.wfq_data[i].configured) { u32 rate = p_hwfn->qm_info.wfq_data[i].min_speed; - use_wfq = true; - rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate); + use_wfq = true; + rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate); if (rc == ECORE_INVAL) { - DP_NOTICE(p_hwfn, false, + DP_NOTICE(p_hwfn, false, "Validation failed while" " configuring min rate\n"); - break; - } + break; } } + } if (rc == ECORE_SUCCESS && use_wfq) ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); diff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h index 535b82b5b9..1b78c328da 100644 --- a/drivers/net/qede/base/ecore_dev_api.h +++ b/drivers/net/qede/base/ecore_dev_api.h @@ -270,22 +270,22 @@ enum ecore_dmae_address_type_t { #define ECORE_DMAE_FLAG_COMPLETION_DST 0x00000008 struct ecore_dmae_params { - u32 flags; /* consists of ECORE_DMAE_FLAG_* values */ + u32 flags; /* consists of ECORE_DMAE_FLAG_* values */ u8 src_vfid; u8 dst_vfid; }; /** -* @brief ecore_dmae_host2grc - copy data from source addr to -* dmae registers using the given ptt -* -* @param p_hwfn -* @param p_ptt -* @param source_addr -* @param grc_addr (dmae_data_offset) -* @param size_in_dwords -* @param flags (one of the flags defined above) -*/ + * @brief ecore_dmae_host2grc - copy data from source addr to + * dmae registers using the given ptt + * + * @param p_hwfn + * @param p_ptt + * @param source_addr + * @param grc_addr (dmae_data_offset) + * @param size_in_dwords + * @param flags (one of the flags defined above) + */ enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, @@ -293,15 +293,15 @@ ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn, u32 grc_addr, u32 size_in_dwords, u32 flags); /** -* @brief ecore_dmae_grc2host - Read data from dmae data offset -* to source address using the given ptt -* -* @param p_ptt -* @param grc_addr (dmae_data_offset) -* @param dest_addr -* @param size_in_dwords -* @param flags - one of the flags defined above -*/ + * @brief ecore_dmae_grc2host - Read data from dmae data offset + * to source address using the given ptt + * + * @param p_ptt + * @param grc_addr (dmae_data_offset) + * @param dest_addr + * @param size_in_dwords + * @param flags - one of the flags defined above + */ enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, @@ -309,16 +309,16 @@ ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn, dma_addr_t dest_addr, u32 size_in_dwords, u32 flags); /** -* @brief ecore_dmae_host2host - copy data from to source address -* to a destination address (for SRIOV) using the given ptt -* -* @param p_hwfn -* @param p_ptt -* @param source_addr -* @param dest_addr -* @param size_in_dwords -* @param params -*/ + * @brief ecore_dmae_host2host - copy data from to source address + * to a destination address (for SRIOV) using the given ptt + * + * @param p_hwfn + * @param p_ptt + * @param source_addr + * @param dest_addr + * @param size_in_dwords + * @param params + */ enum _ecore_status_t ecore_dmae_host2host(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, @@ -398,8 +398,8 @@ enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn, * @param p_filter - MAC to add */ enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - u8 *p_filter); + struct ecore_ptt *p_ptt, + u8 *p_filter); /** * @brief ecore_llh_remove_mac_filter - removes a MAC filtre from llh @@ -419,7 +419,7 @@ void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, * @param filter - ethertype to add */ enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, + struct ecore_ptt *p_ptt, u16 filter); /** @@ -439,9 +439,9 @@ void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn, * @param p_ptt */ void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt); + struct ecore_ptt *p_ptt); - /** +/** *@brief Cleanup of previous driver remains prior to load * * @param p_hwfn @@ -461,7 +461,7 @@ enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, * @param p_hwfn * @param p_ptt * - * @return enum _ecore_status_t + * @return enum _ecore_status_t */ enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); diff --git a/drivers/net/qede/base/ecore_gtt_reg_addr.h b/drivers/net/qede/base/ecore_gtt_reg_addr.h index cc49fc7bc4..0eba1aa9a6 100644 --- a/drivers/net/qede/base/ecore_gtt_reg_addr.h +++ b/drivers/net/qede/base/ecore_gtt_reg_addr.h @@ -10,33 +10,33 @@ #define GTT_REG_ADDR_H /* Win 2 */ -#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL +#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL /* Win 3 */ -#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL +#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL /* Win 4 */ -#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL +#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL /* Win 5 */ -#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL +#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL /* Win 6 */ -#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL +#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL /* Win 7 */ -#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL +#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL /* Win 8 */ -#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL +#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL /* Win 9 */ -#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL +#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL /* Win 10 */ -#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL +#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL /* Win 11 */ -#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL +#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL #endif diff --git a/drivers/net/qede/base/ecore_gtt_values.h b/drivers/net/qede/base/ecore_gtt_values.h index f2efe24e20..2ddc5f19be 100644 --- a/drivers/net/qede/base/ecore_gtt_values.h +++ b/drivers/net/qede/base/ecore_gtt_values.h @@ -11,16 +11,16 @@ static u32 pxp_global_win[] = { 0, 0, - 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */ - 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */ - 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */ - 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */ - 0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */ - 0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */ - 0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */ - 0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */ - 0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */ - 0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */ + 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */ + 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */ + 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */ + 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */ + 0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */ + 0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */ + 0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */ + 0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */ + 0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */ + 0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */ 0, 0, 0, diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h index 9cd55c4885..877de8be8d 100644 --- a/drivers/net/qede/base/ecore_hsi_common.h +++ b/drivers/net/qede/base/ecore_hsi_common.h @@ -953,7 +953,7 @@ enum malicious_vf_error_id { VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */, VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */, ETH_PACKET_TOO_SMALL - /* TX packet is shorter then reported on BDs or from minimal size */ +/* TX packet is shorter then reported on BDs or from minimal size */ , ETH_ILLEGAL_VLAN_MODE /* Tx packet with marked as insert VLAN when its illegal */, @@ -1060,7 +1060,7 @@ struct pf_start_ramrod_data { u8 allow_npar_tx_switching; u8 inner_to_outer_pri_map[8]; u8 pri_map_valid - /* If inner_to_outer_pri_map is initialize then set pri_map_valid */ +/* If inner_to_outer_pri_map is initialize then set pri_map_valid */ ; __le32 outer_tag; u8 reserved0[4]; @@ -1244,7 +1244,7 @@ enum tunnel_clss { TUNNEL_CLSS_MAC_VNI , TUNNEL_CLSS_INNER_MAC_VLAN - /* Use MAC and VLAN from last L2 header for vport classification */ +/* Use MAC and VLAN from last L2 header for vport classification */ , TUNNEL_CLSS_INNER_MAC_VNI , diff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h index 80f4165fad..78cc55dc02 100644 --- a/drivers/net/qede/base/ecore_hsi_eth.h +++ b/drivers/net/qede/base/ecore_hsi_eth.h @@ -872,7 +872,7 @@ struct eth_vport_tpa_param { u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; u8 tpa_pkt_split_flg; u8 tpa_hdr_data_split_flg - /* If set, put header of first TPA segment on bd and data on SGE */ +/* If set, put header of first TPA segment on bd and data on SGE */ ; u8 tpa_gro_consistent_flg /* If set, GRO data consistent will checked for TPA continue */; @@ -882,10 +882,10 @@ struct eth_vport_tpa_param { __le16 tpa_min_size_to_start /* minimum TCP payload size for a packet to start aggregation */; __le16 tpa_min_size_to_cont - /* minimum TCP payload size for a packet to continue aggregation */ +/* minimum TCP payload size for a packet to continue aggregation */ ; u8 max_buff_num - /* maximal number of buffers that can be used for one aggregation */ +/* maximal number of buffers that can be used for one aggregation */ ; u8 reserved; }; @@ -1124,7 +1124,7 @@ struct vport_start_ramrod_data { u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */ ; u8 silent_vlan_removal_en; - /* If enable then innerVlan will be striped and not written to cqe */ +/* If enable then innerVlan will be striped and not written to cqe */ u8 untagged; struct eth_tx_err_vals tx_err_behav /* Desired behavior per TX error type */; diff --git a/drivers/net/qede/base/ecore_hw.c b/drivers/net/qede/base/ecore_hw.c index 5403b94bc8..e9b96d5792 100644 --- a/drivers/net/qede/base/ecore_hw.c +++ b/drivers/net/qede/base/ecore_hw.c @@ -108,15 +108,15 @@ struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn) } p_ptt = OSAL_LIST_FIRST_ENTRY(&p_hwfn->p_ptt_pool->free_list, - struct ecore_ptt, list_entry); - OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry, - &p_hwfn->p_ptt_pool->free_list); - OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock); + struct ecore_ptt, list_entry); + OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry, + &p_hwfn->p_ptt_pool->free_list); + OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock); DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "allocated ptt %d\n", p_ptt->idx); - return p_ptt; -} + return p_ptt; + } void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { @@ -298,7 +298,7 @@ void ecore_fid_pretend(struct ecore_hwfn *p_hwfn, SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); - /* Every pretend undos prev pretends, including previous port pretend */ +/* Every pretend undos prev pretends, including previous port pretend */ SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); diff --git a/drivers/net/qede/base/ecore_hw.h b/drivers/net/qede/base/ecore_hw.h index 894994476a..9603c996d8 100644 --- a/drivers/net/qede/base/ecore_hw.h +++ b/drivers/net/qede/base/ecore_hw.h @@ -115,7 +115,7 @@ u32 ecore_ptt_get_hw_addr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); * * @return u32 */ -u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt); +u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt); /** * @brief ecore_ptt_set_win - Set PTT Window's GRC BAR address @@ -124,7 +124,7 @@ u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt); * @param new_hw_addr * @param p_ptt */ -void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn, +void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 new_hw_addr); /** @@ -135,8 +135,8 @@ void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn, * * @return struct ecore_ptt * */ -struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn, - enum reserved_ptts ptt_idx); +struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn, + enum reserved_ptts ptt_idx); /** * @brief ecore_wr - Write value to BAR using the given ptt @@ -146,7 +146,7 @@ struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn, * @param val * @param hw_addr */ -void ecore_wr(struct ecore_hwfn *p_hwfn, +void ecore_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr, u32 val); /** @@ -169,8 +169,8 @@ u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr); * @param hw_addr * @param n */ -void ecore_memcpy_from(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, +void ecore_memcpy_from(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, void *dest, u32 hw_addr, osal_size_t n); /** @@ -183,8 +183,8 @@ void ecore_memcpy_from(struct ecore_hwfn *p_hwfn, * @param src * @param n */ -void ecore_memcpy_to(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, +void ecore_memcpy_to(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, u32 hw_addr, void *src, osal_size_t n); /** * @brief ecore_fid_pretend - pretend to another function when @@ -197,7 +197,7 @@ void ecore_memcpy_to(struct ecore_hwfn *p_hwfn, * @param fid - fid field of pxp_pretend structure. Can contain * either pf / vf, port/path fields are don't care. */ -void ecore_fid_pretend(struct ecore_hwfn *p_hwfn, +void ecore_fid_pretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u16 fid); /** @@ -208,7 +208,7 @@ void ecore_fid_pretend(struct ecore_hwfn *p_hwfn, * @param p_ptt * @param port_id - the port to pretend to */ -void ecore_port_pretend(struct ecore_hwfn *p_hwfn, +void ecore_port_pretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u8 port_id); /** @@ -235,7 +235,7 @@ u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid); * which is part of p_hwfn. * @param p_hwfn */ -enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn); +enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn); /** * @brief ecore_dmae_info_free - Free the dmae_info structure @@ -243,7 +243,7 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn); * * @param p_hwfn */ -void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn); +void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn); union ecore_qm_pq_params { struct { @@ -257,7 +257,7 @@ union ecore_qm_pq_params { } eth; }; -u16 ecore_get_qm_pq(struct ecore_hwfn *p_hwfn, +u16 ecore_get_qm_pq(struct ecore_hwfn *p_hwfn, enum protocol_type proto, union ecore_qm_pq_params *params); enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev, diff --git a/drivers/net/qede/base/ecore_hw_defs.h b/drivers/net/qede/base/ecore_hw_defs.h index fa518cecd3..19816ff1e0 100644 --- a/drivers/net/qede/base/ecore_hw_defs.h +++ b/drivers/net/qede/base/ecore_hw_defs.h @@ -36,13 +36,13 @@ enum igu_ctrl_cmd { */ struct igu_ctrl_reg { u32 ctrl_data; -#define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ +#define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ #define IGU_CTRL_REG_FID_SHIFT 0 -#define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ +#define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 #define IGU_CTRL_REG_RESERVED_MASK 0x1 #define IGU_CTRL_REG_RESERVED_SHIFT 28 -#define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ +#define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ #define IGU_CTRL_REG_TYPE_SHIFT 31 }; diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c index 5440731b50..0844194317 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.c +++ b/drivers/net/qede/base/ecore_init_fw_funcs.c @@ -206,7 +206,7 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn, for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) { if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1) - num_tcs_in_port++; + num_tcs_in_port++; } phys_lines_per_tc = phys_lines / num_tcs_in_port; /* init registers per active TC */ @@ -293,9 +293,9 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn, tc < NUM_OF_PHYS_TCS; tc++) { if (((port_params[port_id].active_phys_tcs >> - tc) & 0x1) == 1) { + tc) & 0x1) == 1) { voq = PHYS_VOQ(port_id, tc, - max_phys_tcs_per_port); + max_phys_tcs_per_port); STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(voq), phys_blocks); @@ -412,7 +412,7 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn, u32 curr_mask = is_first_pf ? 0 : ecore_rd(p_hwfn, p_ptt, QM_REG_MAXPQSIZETXSEL_0 - + i * 4); + + i * 4); STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i, curr_mask | tx_pq_vf_mask[i]); @@ -518,8 +518,8 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn, vport_params[i].first_tx_pq_id[tc]; if (vport_pq_id != QM_INVALID_PQ_ID) { STORE_RT_REG(p_hwfn, - QM_REG_WFQVPCRD_RT_OFFSET + - vport_pq_id, + QM_REG_WFQVPCRD_RT_OFFSET + + vport_pq_id, QM_WFQ_CRD_REG_SIGN_BIT); STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h index 5280cd7a07..0c8d1fb5f8 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.h +++ b/drivers/net/qede/base/ecore_init_fw_funcs.h @@ -26,8 +26,8 @@ struct init_qm_pq_params; * @return The required host memory size in 4KB units. */ u32 ecore_qm_pf_mem_size(u8 pf_id, - u32 num_pf_cids, - u32 num_vf_cids, + u32 num_pf_cids, + u32 num_vf_cids, u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); /** * @brief ecore_qm_common_rt_init - @@ -45,33 +45,33 @@ u32 ecore_qm_pf_mem_size(u8 pf_id, * @return 0 on success, -1 on error. */ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn, - u8 max_ports_per_engine, - u8 max_phys_tcs_per_port, - bool pf_rl_en, - bool pf_wfq_en, - bool vport_rl_en, - bool vport_wfq_en, + u8 max_ports_per_engine, + u8 max_phys_tcs_per_port, + bool pf_rl_en, + bool pf_wfq_en, + bool vport_rl_en, + bool vport_wfq_en, struct init_qm_port_params port_params[MAX_NUM_PORTS]); int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - u8 port_id, - u8 pf_id, - u8 max_phys_tcs_per_port, - bool is_first_pf, - u32 num_pf_cids, - u32 num_vf_cids, - u32 num_tids, - u16 start_pq, - u16 num_pf_pqs, - u16 num_vf_pqs, - u8 start_vport, - u8 num_vports, - u16 pf_wfq, - u32 pf_rl, - struct init_qm_pq_params *pq_params, - struct init_qm_vport_params *vport_params); + struct ecore_ptt *p_ptt, + u8 port_id, + u8 pf_id, + u8 max_phys_tcs_per_port, + bool is_first_pf, + u32 num_pf_cids, + u32 num_vf_cids, + u32 num_tids, + u16 start_pq, + u16 num_pf_pqs, + u16 num_vf_pqs, + u8 start_vport, + u8 num_vports, + u16 pf_wfq, + u32 pf_rl, + struct init_qm_pq_params *pq_params, + struct init_qm_vport_params *vport_params); /** * @brief ecore_init_pf_wfq Initializes the WFQ weight of the specified PF * @@ -109,7 +109,7 @@ int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn, * @return 0 on success, -1 on error. */ int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, + struct ecore_ptt *p_ptt, u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq); /** * @brief ecore_init_vport_rl Initializes the rate limit of the specified VPORT @@ -137,8 +137,8 @@ int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn, * waiting for QM command done. */ bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - bool is_release_cmd, + struct ecore_ptt *p_ptt, + bool is_release_cmd, bool is_tx_pq, u16 start_pq, u16 num_pqs); /** * @brief ecore_init_nig_ets - initializes the NIG ETS arbiter @@ -152,7 +152,7 @@ bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn, * requirements are ignored when is_lb is cleared. */ void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, + struct ecore_ptt *p_ptt, struct init_ets_req *req, bool is_lb); /** * @brief ecore_init_nig_lb_rl - initializes the NIG LB RLs @@ -163,8 +163,8 @@ void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn, * @param req - the NIG LB RLs initialization requirements. */ void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - struct init_nig_lb_rl_req *req); + struct ecore_ptt *p_ptt, + struct init_nig_lb_rl_req *req); /** * @brief ecore_init_nig_pri_tc_map - initializes the NIG priority to TC map. * @@ -174,8 +174,8 @@ void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn, * @param req - required mapping from prioirties to TCs. */ void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - struct init_nig_pri_tc_map_req *req); + struct ecore_ptt *p_ptt, + struct init_nig_pri_tc_map_req *req); /** * @brief ecore_init_prs_ets - initializes the PRS Rx ETS arbiter * @@ -227,7 +227,7 @@ void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn, /** * @brief ecore_set_vxlan_enable - enable or disable VXLAN tunnel in HW * - * @param p_ptt - ptt window used for writing the registers. + * @param p_ptt - ptt window used for writing the registers. * @param vxlan_enable - vxlan enable flag. */ void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn, diff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c index e6e4c36be0..71bad30c7f 100644 --- a/drivers/net/qede/base/ecore_init_ops.c +++ b/drivers/net/qede/base/ecore_init_ops.c @@ -251,9 +251,9 @@ static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn, b_can_dmae); if (rc) break; - } - break; } + break; + } case INIT_ARR_STANDARD: size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE); rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c index bed9ea389b..e4c002ac59 100644 --- a/drivers/net/qede/base/ecore_int.c +++ b/drivers/net/qede/base/ecore_int.c @@ -100,7 +100,7 @@ static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn) #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT (0) #define ECORE_PSWHST_ATTENTION_VF_DISABLED (0x1) #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) -#define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) +#define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0x1e) #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) @@ -1138,7 +1138,7 @@ void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie) return; } - /* Check the validity of the DPC ptt. If not ack interrupts and fail */ +/* Check the validity of the DPC ptt. If not ack interrupts and fail */ if (!p_hwfn->p_dpc_ptt) { DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n"); ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1); @@ -1676,7 +1676,7 @@ static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn, enum _ecore_status_t ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, - enum ecore_int_mode int_mode) + enum ecore_int_mode int_mode) { enum _ecore_status_t rc = ECORE_SUCCESS; u32 tmp; @@ -2102,10 +2102,10 @@ u16 ecore_int_queue_id_from_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id) return sb_id - p_info->igu_base_sb_iov + p_info->igu_sb_cnt; } - DP_NOTICE(p_hwfn, true, "SB %d not in range for function\n", - sb_id); - return 0; -} + DP_NOTICE(p_hwfn, true, "SB %d not in range for function\n", + sb_id); + return 0; + } void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev) { diff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h index 17c952136b..eeec8ca0cb 100644 --- a/drivers/net/qede/base/ecore_int.h +++ b/drivers/net/qede/base/ecore_int.h @@ -169,8 +169,8 @@ void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn, * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt); +enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt); /** * @brief ecore_int_free diff --git a/drivers/net/qede/base/ecore_iov_api.h b/drivers/net/qede/base/ecore_iov_api.h index b34a9c6bb2..5ad4ec67ad 100644 --- a/drivers/net/qede/base/ecore_iov_api.h +++ b/drivers/net/qede/base/ecore_iov_api.h @@ -21,22 +21,22 @@ #define IS_PF_SRIOV(p_hwfn) (0) #endif #define IS_PF_SRIOV_ALLOC(p_hwfn) (!!((p_hwfn)->pf_iov_info)) -#define IS_PF_PDA(p_hwfn) 0 /* @@TBD Michalk */ +#define IS_PF_PDA(p_hwfn) 0 /* @@TBD Michalk */ /* @@@ TBD MichalK - what should this number be*/ #define ECORE_MAX_VF_CHAINS_PER_PF 16 /* vport update extended feature tlvs flags */ enum ecore_iov_vport_update_flag { - ECORE_IOV_VP_UPDATE_ACTIVATE = 0, - ECORE_IOV_VP_UPDATE_VLAN_STRIP = 1, - ECORE_IOV_VP_UPDATE_TX_SWITCH = 2, - ECORE_IOV_VP_UPDATE_MCAST = 3, - ECORE_IOV_VP_UPDATE_ACCEPT_PARAM = 4, - ECORE_IOV_VP_UPDATE_RSS = 5, - ECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN = 6, - ECORE_IOV_VP_UPDATE_SGE_TPA = 7, - ECORE_IOV_VP_UPDATE_MAX = 8, + ECORE_IOV_VP_UPDATE_ACTIVATE = 0, + ECORE_IOV_VP_UPDATE_VLAN_STRIP = 1, + ECORE_IOV_VP_UPDATE_TX_SWITCH = 2, + ECORE_IOV_VP_UPDATE_MCAST = 3, + ECORE_IOV_VP_UPDATE_ACCEPT_PARAM = 4, + ECORE_IOV_VP_UPDATE_RSS = 5, + ECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN = 6, + ECORE_IOV_VP_UPDATE_SGE_TPA = 7, + ECORE_IOV_VP_UPDATE_MAX = 8, }; struct ecore_mcp_link_params; @@ -67,21 +67,21 @@ struct ecore_public_vf_info { #ifdef CONFIG_ECORE_SW_CHANNEL /* This is SW channel related only... */ enum mbx_state { - VF_PF_UNKNOWN_STATE = 0, - VF_PF_WAIT_FOR_START_REQUEST = 1, - VF_PF_WAIT_FOR_NEXT_CHUNK_OF_REQUEST = 2, - VF_PF_REQUEST_IN_PROCESSING = 3, - VF_PF_RESPONSE_READY = 4, + VF_PF_UNKNOWN_STATE = 0, + VF_PF_WAIT_FOR_START_REQUEST = 1, + VF_PF_WAIT_FOR_NEXT_CHUNK_OF_REQUEST = 2, + VF_PF_REQUEST_IN_PROCESSING = 3, + VF_PF_RESPONSE_READY = 4, }; struct ecore_iov_sw_mbx { - enum mbx_state mbx_state; + enum mbx_state mbx_state; - u32 request_size; - u32 request_offset; + u32 request_size; + u32 request_offset; - u32 response_size; - u32 response_offset; + u32 response_size; + u32 response_offset; }; /** @@ -93,7 +93,7 @@ struct ecore_iov_sw_mbx { * @return struct ecore_iov_sw_mbx* */ struct ecore_iov_sw_mbx *ecore_iov_get_vf_sw_mbx(struct ecore_hwfn *p_hwfn, - u16 rel_vf_id); + u16 rel_vf_id); #endif #ifdef CONFIG_ECORE_SRIOV @@ -457,9 +457,9 @@ void ecore_iov_get_vf_req_virt_mbx_params(struct ecore_hwfn *p_hwfn, * @param p_reply_virt_size */ void ecore_iov_get_vf_reply_virt_mbx_params(struct ecore_hwfn *p_hwfn, - u16 rel_vf_id, + u16 rel_vf_id, void **pp_reply_virt_addr, - u16 *p_reply_virt_size); + u16 *p_reply_virt_size); /** * @brief Validate if the given length is a valid vfpf message diff --git a/drivers/net/qede/base/ecore_iro.h b/drivers/net/qede/base/ecore_iro.h index dd53ea9cf1..7cabdf7050 100644 --- a/drivers/net/qede/base/ecore_iro.h +++ b/drivers/net/qede/base/ecore_iro.h @@ -10,24 +10,24 @@ #define __IRO_H__ /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */ -#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) -#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) +#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) +#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) /* Tstorm port statistics */ #define TSTORM_PORT_STAT_OFFSET(port_id) \ (IRO[1].base + ((port_id) * IRO[1].m1)) -#define TSTORM_PORT_STAT_SIZE (IRO[1].size) +#define TSTORM_PORT_STAT_SIZE (IRO[1].size) /* Ustorm VF-PF Channel ready flag */ #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \ (IRO[3].base + ((vf_id) * IRO[3].m1)) -#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) +#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) /* Ustorm Final flr cleanup ack */ #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \ (IRO[4].base + ((pf_id) * IRO[4].m1)) -#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) +#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) /* Ustorm Event ring consumer */ #define USTORM_EQE_CONS_OFFSET(pf_id) \ (IRO[5].base + ((pf_id) * IRO[5].m1)) -#define USTORM_EQE_CONS_SIZE (IRO[5].size) +#define USTORM_EQE_CONS_SIZE (IRO[5].size) /* Ustorm Common Queue ring consumer */ #define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \ (IRO[6].base + ((global_queue_id) * IRO[6].m1)) diff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h index c818b58091..548ad1472b 100644 --- a/drivers/net/qede/base/ecore_iro_values.h +++ b/drivers/net/qede/base/ecore_iro_values.h @@ -10,49 +10,49 @@ #define __IRO_VALUES_H__ static const struct iro iro_arr[44] = { - {0x0, 0x0, 0x0, 0x0, 0x8}, + { 0x0, 0x0, 0x0, 0x0, 0x8}, {0x4db0, 0x60, 0x0, 0x0, 0x60}, {0x6418, 0x20, 0x0, 0x0, 0x20}, {0x500, 0x8, 0x0, 0x0, 0x4}, {0x480, 0x8, 0x0, 0x0, 0x4}, - {0x0, 0x8, 0x0, 0x0, 0x2}, + { 0x0, 0x8, 0x0, 0x0, 0x2}, {0x80, 0x8, 0x0, 0x0, 0x2}, {0x4938, 0x0, 0x0, 0x0, 0x78}, - {0x3df0, 0x0, 0x0, 0x0, 0x78}, - {0x29b0, 0x0, 0x0, 0x0, 0x78}, + { 0x3df0, 0x0, 0x0, 0x0, 0x78}, + { 0x29b0, 0x0, 0x0, 0x0, 0x78}, {0x4d38, 0x0, 0x0, 0x0, 0x78}, {0x56c8, 0x0, 0x0, 0x0, 0x78}, - {0x7e48, 0x0, 0x0, 0x0, 0x78}, - {0xa28, 0x8, 0x0, 0x0, 0x8}, + { 0x7e48, 0x0, 0x0, 0x0, 0x78}, + { 0xa28, 0x8, 0x0, 0x0, 0x8}, {0x61f8, 0x10, 0x0, 0x0, 0x10}, {0xb500, 0x30, 0x0, 0x0, 0x30}, - {0x95b8, 0x30, 0x0, 0x0, 0x30}, + { 0x95b8, 0x30, 0x0, 0x0, 0x30}, {0x5898, 0x40, 0x0, 0x0, 0x40}, {0x1f8, 0x10, 0x0, 0x0, 0x8}, {0xa228, 0x0, 0x0, 0x0, 0x4}, - {0x8050, 0x40, 0x0, 0x0, 0x30}, + { 0x8050, 0x40, 0x0, 0x0, 0x30}, {0xcf8, 0x8, 0x0, 0x0, 0x8}, - {0x2b48, 0x80, 0x0, 0x0, 0x38}, + { 0x2b48, 0x80, 0x0, 0x0, 0x38}, {0xadf0, 0x0, 0x0, 0x0, 0xf0}, {0xaee0, 0x8, 0x0, 0x0, 0x8}, {0x80, 0x8, 0x0, 0x0, 0x8}, - {0xac0, 0x8, 0x0, 0x0, 0x8}, - {0x2578, 0x8, 0x0, 0x0, 0x8}, - {0x24f8, 0x8, 0x0, 0x0, 0x8}, - {0x0, 0x8, 0x0, 0x0, 0x8}, - {0x200, 0x10, 0x8, 0x0, 0x8}, + { 0xac0, 0x8, 0x0, 0x0, 0x8}, + { 0x2578, 0x8, 0x0, 0x0, 0x8}, + { 0x24f8, 0x8, 0x0, 0x0, 0x8}, + { 0x0, 0x8, 0x0, 0x0, 0x8}, + { 0x200, 0x10, 0x8, 0x0, 0x8}, {0x17f8, 0x8, 0x0, 0x0, 0x2}, {0x19f8, 0x10, 0x8, 0x0, 0x2}, {0xd988, 0x38, 0x0, 0x0, 0x24}, {0x11040, 0x10, 0x0, 0x0, 0x8}, {0x11670, 0x38, 0x0, 0x0, 0x18}, {0xaeb8, 0x30, 0x0, 0x0, 0x10}, - {0x86f8, 0x28, 0x0, 0x0, 0x18}, + { 0x86f8, 0x28, 0x0, 0x0, 0x18}, {0xebf8, 0x10, 0x0, 0x0, 0x10}, {0xde08, 0x40, 0x0, 0x0, 0x30}, {0x121a0, 0x38, 0x0, 0x0, 0x8}, {0xf060, 0x20, 0x0, 0x0, 0x20}, - {0x2b80, 0x80, 0x0, 0x0, 0x10}, + { 0x2b80, 0x80, 0x0, 0x0, 0x10}, {0x50a0, 0x10, 0x0, 0x0, 0x10}, }; diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index 9e6ef5a4dc..b31523b1cf 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -234,7 +234,7 @@ ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn, SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) || - !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED))); + !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED))); SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)); @@ -429,7 +429,7 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn, rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); if (rc != ECORE_SUCCESS) { - /* Return spq entry which is taken in ecore_sp_init_request() */ + /* Return spq entry which is taken in ecore_sp_init_request()*/ ecore_spq_return_entry(p_hwfn, p_ent); return rc; } @@ -632,7 +632,7 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn, dma_addr_t bd_chain_phys_addr, dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size, - void OSAL_IOMEM * *pp_prod) + void OSAL_IOMEM **pp_prod) { struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id]; u8 abs_stats_id = 0; @@ -788,7 +788,7 @@ ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn, * In addition, VFs require the answer to come as eqe to PF. */ p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid == - p_hwfn->hw_info.opaque_fid) && + p_hwfn->hw_info.opaque_fid) && !eq_completion_only) || cqe_completion; p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) || @@ -876,7 +876,7 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, u8 sb_index, dma_addr_t pbl_addr, u16 pbl_size, - void OSAL_IOMEM * *pp_doorbell) + void OSAL_IOMEM **pp_doorbell) { struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id]; union ecore_qm_pq_params pq_params; @@ -1274,7 +1274,7 @@ ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn, u8 abs_vport_id = 0; int i; - rc = ecore_fw_vport(p_hwfn, + rc = ecore_fw_vport(p_hwfn, (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? p_filter_cmd->vport_to_add_to : p_filter_cmd->vport_to_remove_from, &abs_vport_id); @@ -1306,9 +1306,9 @@ ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn, ETH_MULTICAST_MAC_BINS_IN_REGS); if (p_filter_cmd->opcode == ECORE_FILTER_ADD) { - /* filter ADD op is explicit set op and it removes - * any existing filters for the vport. - */ + /* filter ADD op is explicit set op and it removes + * any existing filters for the vport. + */ for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { u32 bit; diff --git a/drivers/net/qede/base/ecore_l2.h b/drivers/net/qede/base/ecore_l2.h index b0850ca40f..5594a08422 100644 --- a/drivers/net/qede/base/ecore_l2.h +++ b/drivers/net/qede/base/ecore_l2.h @@ -103,7 +103,7 @@ ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn, * @return enum _ecore_status_t */ enum _ecore_status_t -ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn, +ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn, u16 opaque_fid, u32 cid, u16 rx_queue_id, @@ -134,7 +134,7 @@ ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn, * @return enum _ecore_status_t */ enum _ecore_status_t -ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn, +ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn, u16 opaque_fid, u16 tx_queue_id, u32 cid, diff --git a/drivers/net/qede/base/ecore_l2_api.h b/drivers/net/qede/base/ecore_l2_api.h index b41dd7fefe..ab9aca0a68 100644 --- a/drivers/net/qede/base/ecore_l2_api.h +++ b/drivers/net/qede/base/ecore_l2_api.h @@ -14,17 +14,17 @@ #ifndef __EXTRACT__LINUX__ enum ecore_rss_caps { - ECORE_RSS_IPV4 = 0x1, - ECORE_RSS_IPV6 = 0x2, - ECORE_RSS_IPV4_TCP = 0x4, - ECORE_RSS_IPV6_TCP = 0x8, - ECORE_RSS_IPV4_UDP = 0x10, - ECORE_RSS_IPV6_UDP = 0x20, + ECORE_RSS_IPV4 = 0x1, + ECORE_RSS_IPV6 = 0x2, + ECORE_RSS_IPV4_TCP = 0x4, + ECORE_RSS_IPV6_TCP = 0x8, + ECORE_RSS_IPV4_UDP = 0x10, + ECORE_RSS_IPV6_UDP = 0x20, }; /* Should be the same as ETH_RSS_IND_TABLE_ENTRIES_NUM */ #define ECORE_RSS_IND_TABLE_SIZE 128 -#define ECORE_RSS_KEY_SIZE 10 /* size in 32b chunks */ +#define ECORE_RSS_KEY_SIZE 10 /* size in 32b chunks */ #endif struct ecore_rss_params { @@ -35,7 +35,7 @@ struct ecore_rss_params { u8 update_rss_ind_table; u8 update_rss_key; u8 rss_caps; - u8 rss_table_size_log; /* The table size is 2 ^ rss_table_size_log */ + u8 rss_table_size_log; /* The table size is 2 ^ rss_table_size_log */ u16 rss_ind_table[ECORE_RSS_IND_TABLE_SIZE]; u32 rss_key[ECORE_RSS_KEY_SIZE]; }; @@ -63,8 +63,8 @@ enum ecore_filter_opcode { ECORE_FILTER_ADD, ECORE_FILTER_REMOVE, ECORE_FILTER_MOVE, - ECORE_FILTER_REPLACE, /* Delete all MACs and add new one instead */ - ECORE_FILTER_FLUSH, /* Removes all filters */ + ECORE_FILTER_REPLACE, /* Delete all MACs and add new one instead */ + ECORE_FILTER_FLUSH, /* Removes all filters */ }; enum ecore_filter_ucast_type { @@ -97,7 +97,7 @@ struct ecore_filter_mcast { enum ecore_filter_opcode opcode; u8 vport_to_add_to; u8 vport_to_remove_from; - u8 num_mc_addrs; + u8 num_mc_addrs; #define ECORE_MAX_MC_ADDRS 64 unsigned char mac[ECORE_MAX_MC_ADDRS][ETH_ALEN]; }; @@ -138,12 +138,12 @@ ecore_filter_mcast_cmd(struct ecore_dev *p_dev, /* Set "accept" filters */ enum _ecore_status_t ecore_filter_accept_cmd(struct ecore_dev *p_dev, - u8 vport, - struct ecore_filter_accept_flags accept_flags, - u8 update_accept_any_vlan, - u8 accept_any_vlan, - enum spq_mode comp_mode, - struct ecore_spq_comp_cb *p_comp_data); + u8 vport, + struct ecore_filter_accept_flags accept_flags, + u8 update_accept_any_vlan, + u8 accept_any_vlan, + enum spq_mode comp_mode, + struct ecore_spq_comp_cb *p_comp_data); /** * @brief ecore_sp_eth_rx_queue_start - RX Queue Start Ramrod @@ -156,11 +156,11 @@ ecore_filter_accept_cmd(struct ecore_dev *p_dev, * @param rx_queue_id RX Queue ID: Zero based, per VPort, allocated * by assignment (=rssId) * @param vport_id VPort ID - * @param u8 stats_id VPort ID which the queue stats + * @param u8 stats_id VPort ID which the queue stats * will be added to * @param sb Status Block of the Function Event Ring * @param sb_index Index into the status block of the - * Function Event Ring + * Function Event Ring * @param bd_max_bytes Maximum bytes that can be placed on a BD * @param bd_chain_phys_addr Physical address of BDs for receive. * @param cqe_pbl_addr Physical address of the CQE PBL Table. @@ -182,7 +182,7 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn, dma_addr_t bd_chain_phys_addr, dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size, - void OSAL_IOMEM * *pp_prod); + void OSAL_IOMEM **pp_prod); /** * @brief ecore_sp_eth_rx_queue_stop - @@ -224,7 +224,7 @@ ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn, * @param pbl_addr address of the pbl array * @param pbl_size number of entries in pbl * @param pp_doorbell Pointer to place doorbell pointer (May be NULL). - * This address should be used with the + * This address should be used with the * DIRECT_REG_WR macro. * * @return enum _ecore_status_t @@ -255,7 +255,7 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn, u16 tx_queue_id); -enum ecore_tpa_mode { +enum ecore_tpa_mode { ECORE_TPA_MODE_NONE, ECORE_TPA_MODE_RSC, ECORE_TPA_MODE_GRO, @@ -293,28 +293,28 @@ ecore_sp_vport_start(struct ecore_hwfn *p_hwfn, struct ecore_sp_vport_start_params *p_params); struct ecore_sp_vport_update_params { - u16 opaque_fid; - u8 vport_id; - u8 update_vport_active_rx_flg; - u8 vport_active_rx_flg; - u8 update_vport_active_tx_flg; - u8 vport_active_tx_flg; - u8 update_inner_vlan_removal_flg; - u8 inner_vlan_removal_flg; - u8 silent_vlan_removal_flg; - u8 update_default_vlan_enable_flg; - u8 default_vlan_enable_flg; - u8 update_default_vlan_flg; - u16 default_vlan; - u8 update_tx_switching_flg; - u8 tx_switching_flg; - u8 update_approx_mcast_flg; - u8 update_anti_spoofing_en_flg; - u8 anti_spoofing_en; - u8 update_accept_any_vlan_flg; - u8 accept_any_vlan; - unsigned long bins[8]; - struct ecore_rss_params *rss_params; + u16 opaque_fid; + u8 vport_id; + u8 update_vport_active_rx_flg; + u8 vport_active_rx_flg; + u8 update_vport_active_tx_flg; + u8 vport_active_tx_flg; + u8 update_inner_vlan_removal_flg; + u8 inner_vlan_removal_flg; + u8 silent_vlan_removal_flg; + u8 update_default_vlan_enable_flg; + u8 default_vlan_enable_flg; + u8 update_default_vlan_flg; + u16 default_vlan; + u8 update_tx_switching_flg; + u8 tx_switching_flg; + u8 update_approx_mcast_flg; + u8 update_anti_spoofing_en_flg; + u8 anti_spoofing_en; + u8 update_accept_any_vlan_flg; + u8 accept_any_vlan; + unsigned long bins[8]; + struct ecore_rss_params *rss_params; struct ecore_filter_accept_flags accept_flags; struct ecore_sge_tpa_params *sge_tpa_params; }; diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c index 9dd2eed380..2823113120 100644 --- a/drivers/net/qede/base/ecore_mcp.c +++ b/drivers/net/qede/base/ecore_mcp.c @@ -333,7 +333,7 @@ enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn, } enum _ecore_status_t ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, + struct ecore_ptt *p_ptt, u32 cmd, u32 param, union drv_union_data *p_union_data, u32 *o_mcp_resp, @@ -354,18 +354,18 @@ enum _ecore_status_t ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock); if (p_union_data != OSAL_NULL) { - union_data_addr = p_hwfn->mcp_info->drv_mb_addr + - OFFSETOF(struct public_drv_mb, union_data); + union_data_addr = p_hwfn->mcp_info->drv_mb_addr + + OFFSETOF(struct public_drv_mb, union_data); ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, p_union_data, sizeof(*p_union_data)); - } +} rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, o_mcp_resp, o_mcp_param); OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock); - return rc; + return rc; } enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn, @@ -577,7 +577,7 @@ static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn, DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP), "Received transceiver state update [0x%08x] from mfw" - "[Addr 0x%x]\n", + " [Addr 0x%x]\n", transceiver_state, (u32)(p_hwfn->mcp_info->port_addr + OFFSETOF(struct public_port, transceiver_data))); @@ -661,18 +661,18 @@ static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn, if (p_hwfn->mcp_info->func_info.bandwidth_max && p_link->speed) { u8 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; - __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt, - p_link, max_bw); + __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt, + p_link, max_bw); } if (p_hwfn->mcp_info->func_info.bandwidth_min && p_link->speed) { u8 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; - __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt, - p_link, min_bw); + __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt, + p_link, min_bw); - ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, - p_link->min_pf_rate); + ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, + p_link->min_pf_rate); } p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); @@ -1090,8 +1090,8 @@ enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev, DP_VERBOSE(p_dev, ECORE_MSG_IOV, "VF requested MFW vers prior to ACQUIRE\n"); - return ECORE_INVAL; - } + return ECORE_INVAL; + } global_offsize = ecore_rd(p_hwfn, p_ptt, SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info-> diff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h index 448c30bbcf..7af4349537 100644 --- a/drivers/net/qede/base/ecore_mcp.h +++ b/drivers/net/qede/base/ecore_mcp.h @@ -38,10 +38,10 @@ struct ecore_mcp_info { u32 port_addr; /* Address of the port configuration (link) */ u16 drv_mb_seq; /* Current driver mailbox sequence */ u16 drv_pulse_seq; /* Current driver pulse sequence */ - struct ecore_mcp_link_params link_input; - struct ecore_mcp_link_state link_output; + struct ecore_mcp_link_params link_input; + struct ecore_mcp_link_state link_output; struct ecore_mcp_link_capabilities link_capabilities; - struct ecore_mcp_function_info func_info; + struct ecore_mcp_function_info func_info; u8 *mfw_mb_cur; u8 *mfw_mb_shadow; diff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h index 7360b35664..530c0ecdc9 100644 --- a/drivers/net/qede/base/ecore_mcp_api.h +++ b/drivers/net/qede/base/ecore_mcp_api.h @@ -13,8 +13,8 @@ struct ecore_mcp_link_speed_params { bool autoneg; - u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ - u32 forced_speed; /* In Mb/s */ + u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ + u32 forced_speed; /* In Mb/s */ }; struct ecore_mcp_link_pause_params { @@ -26,7 +26,7 @@ struct ecore_mcp_link_pause_params { struct ecore_mcp_link_params { struct ecore_mcp_link_speed_params speed; struct ecore_mcp_link_pause_params pause; - u32 loopback_mode; /* in PMM_LOOPBACK values */ + u32 loopback_mode; /* in PMM_LOOPBACK values */ }; struct ecore_mcp_link_capabilities { @@ -36,9 +36,9 @@ struct ecore_mcp_link_capabilities { struct ecore_mcp_link_state { bool link_up; - u32 line_speed; /* In Mb/s */ - u32 min_pf_rate; /* In Mb/s */ - u32 speed; /* In Mb/s */ + u32 line_speed; /* In Mb/s */ + u32 min_pf_rate; /* In Mb/s */ + u32 speed; /* In Mb/s */ bool full_duplex; bool an; @@ -237,7 +237,7 @@ enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev, * ECORE_BUSY - Operation failed */ enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev, - u32 *media_type); + u32 *media_type); /** * @brief - Sends a command to the MCP mailbox. @@ -542,7 +542,7 @@ enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd, * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. */ enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr, - u8 *p_buf, u32 len); + u8 *p_buf, u32 len); /** * @brief Read from sfp diff --git a/drivers/net/qede/base/ecore_proto_if.h b/drivers/net/qede/base/ecore_proto_if.h index 2fecbc865a..bcbd9f0950 100644 --- a/drivers/net/qede/base/ecore_proto_if.h +++ b/drivers/net/qede/base/ecore_proto_if.h @@ -18,11 +18,11 @@ struct ecore_eth_pf_params { * and these parameters need to be passed as arguments * to update_pf_params routine invoked before slowpath start */ - u16 num_cons; + u16 num_cons; }; struct ecore_pf_params { - struct ecore_eth_pf_params eth_pf_params; + struct ecore_eth_pf_params eth_pf_params; }; #endif diff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h index 1f5139ea21..cc8a8ed19e 100644 --- a/drivers/net/qede/base/ecore_rt_defs.h +++ b/drivers/net/qede/base/ecore_rt_defs.h @@ -10,93 +10,93 @@ #define __RT_DEFS_H__ /* Runtime array offsets */ -#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 -#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 -#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 -#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 -#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 -#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 -#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 -#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 -#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 -#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 -#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 -#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 -#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 -#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 -#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 -#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 -#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 -#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 -#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18 -#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19 -#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20 -#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21 -#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22 -#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23 -#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24 -#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 -#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 -#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 -#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 -#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497 -#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 -#define CAU_REG_PI_MEMORY_RT_OFFSET 2233 -#define CAU_REG_PI_MEMORY_RT_SIZE 4416 -#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649 -#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650 -#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651 -#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652 -#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653 -#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654 -#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659 -#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660 -#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661 -#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662 -#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663 -#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664 -#define SRC_REG_FIRSTFREE_RT_OFFSET 6665 -#define SRC_REG_FIRSTFREE_RT_SIZE 2 -#define SRC_REG_LASTFREE_RT_OFFSET 6667 -#define SRC_REG_LASTFREE_RT_SIZE 2 -#define SRC_REG_COUNTFREE_RT_OFFSET 6669 -#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670 -#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671 -#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672 -#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673 -#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674 -#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675 -#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676 -#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677 -#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678 -#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679 -#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680 -#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681 -#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682 -#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683 -#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684 -#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685 -#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686 -#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687 -#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688 -#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689 -#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690 -#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691 -#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692 -#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693 -#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694 -#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695 -#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696 -#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697 -#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698 -#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699 -#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700 -#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701 -#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702 -#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703 -#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704 -#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 -#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704 +#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 +#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 +#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 +#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 +#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 +#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 +#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 +#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 +#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 +#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 +#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 +#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 +#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 +#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 +#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 +#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 +#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 +#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 +#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18 +#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19 +#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20 +#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21 +#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22 +#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23 +#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24 +#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 +#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 +#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 +#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 +#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497 +#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 +#define CAU_REG_PI_MEMORY_RT_OFFSET 2233 +#define CAU_REG_PI_MEMORY_RT_SIZE 4416 +#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649 +#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650 +#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651 +#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652 +#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653 +#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654 +#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659 +#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660 +#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661 +#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662 +#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663 +#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664 +#define SRC_REG_FIRSTFREE_RT_OFFSET 6665 +#define SRC_REG_FIRSTFREE_RT_SIZE 2 +#define SRC_REG_LASTFREE_RT_OFFSET 6667 +#define SRC_REG_LASTFREE_RT_SIZE 2 +#define SRC_REG_COUNTFREE_RT_OFFSET 6669 +#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670 +#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671 +#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672 +#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673 +#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674 +#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675 +#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676 +#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677 +#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678 +#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679 +#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680 +#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681 +#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682 +#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683 +#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684 +#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685 +#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686 +#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687 +#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688 +#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689 +#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690 +#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691 +#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692 +#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693 +#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694 +#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695 +#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696 +#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697 +#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698 +#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699 +#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700 +#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701 +#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702 +#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703 +#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704 +#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 +#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707 @@ -107,9 +107,9 @@ #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714 -#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 +#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130 -#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 +#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29642 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29643 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29644 @@ -178,11 +178,11 @@ #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29707 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29708 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29709 -#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 +#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 #define QM_REG_VOQCRDLINE_RT_OFFSET 29837 -#define QM_REG_VOQCRDLINE_RT_SIZE 20 +#define QM_REG_VOQCRDLINE_RT_SIZE 20 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29857 -#define QM_REG_VOQINITCRDLINE_RT_SIZE 20 +#define QM_REG_VOQINITCRDLINE_RT_SIZE 20 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29877 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29878 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29879 @@ -303,42 +303,42 @@ #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29994 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29995 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29996 -#define QM_REG_RLGLBLINCVAL_RT_SIZE 256 +#define QM_REG_RLGLBLINCVAL_RT_SIZE 256 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30252 -#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 +#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 #define QM_REG_RLGLBLCRD_RT_OFFSET 30508 -#define QM_REG_RLGLBLCRD_RT_SIZE 256 +#define QM_REG_RLGLBLCRD_RT_SIZE 256 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30764 #define QM_REG_RLPFPERIOD_RT_OFFSET 30765 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30766 #define QM_REG_RLPFINCVAL_RT_OFFSET 30767 -#define QM_REG_RLPFINCVAL_RT_SIZE 16 +#define QM_REG_RLPFINCVAL_RT_SIZE 16 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30783 -#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 +#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 #define QM_REG_RLPFCRD_RT_OFFSET 30799 -#define QM_REG_RLPFCRD_RT_SIZE 16 +#define QM_REG_RLPFCRD_RT_SIZE 16 #define QM_REG_RLPFENABLE_RT_OFFSET 30815 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30816 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30817 -#define QM_REG_WFQPFWEIGHT_RT_SIZE 16 +#define QM_REG_WFQPFWEIGHT_RT_SIZE 16 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30833 -#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 +#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 #define QM_REG_WFQPFCRD_RT_OFFSET 30849 -#define QM_REG_WFQPFCRD_RT_SIZE 160 +#define QM_REG_WFQPFCRD_RT_SIZE 160 #define QM_REG_WFQPFENABLE_RT_OFFSET 31009 #define QM_REG_WFQVPENABLE_RT_OFFSET 31010 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31011 -#define QM_REG_BASEADDRTXPQ_RT_SIZE 512 +#define QM_REG_BASEADDRTXPQ_RT_SIZE 512 #define QM_REG_TXPQMAP_RT_OFFSET 31523 -#define QM_REG_TXPQMAP_RT_SIZE 512 +#define QM_REG_TXPQMAP_RT_SIZE 512 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32035 -#define QM_REG_WFQVPWEIGHT_RT_SIZE 512 +#define QM_REG_WFQVPWEIGHT_RT_SIZE 512 #define QM_REG_WFQVPCRD_RT_OFFSET 32547 -#define QM_REG_WFQVPCRD_RT_SIZE 512 +#define QM_REG_WFQVPCRD_RT_SIZE 512 #define QM_REG_WFQVPMAP_RT_OFFSET 33059 -#define QM_REG_WFQVPMAP_RT_SIZE 512 +#define QM_REG_WFQVPMAP_RT_SIZE 512 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33571 -#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 +#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33731 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33732 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33733 @@ -347,22 +347,22 @@ #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33736 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33737 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33738 -#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 +#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33742 -#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4 +#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33746 -#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 +#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33750 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33751 -#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 +#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33783 -#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 +#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33799 -#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 +#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33815 -#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 +#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33831 -#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33847 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33848 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33849 diff --git a/drivers/net/qede/base/ecore_sp_api.h b/drivers/net/qede/base/ecore_sp_api.h index e80f5ef3e2..71e235940c 100644 --- a/drivers/net/qede/base/ecore_sp_api.h +++ b/drivers/net/qede/base/ecore_sp_api.h @@ -12,9 +12,9 @@ #include "ecore_status.h" enum spq_mode { - ECORE_SPQ_MODE_BLOCK, /* Client will poll a designated mem. address */ - ECORE_SPQ_MODE_CB, /* Client supplies a callback */ - ECORE_SPQ_MODE_EBLOCK, /* ECORE should block until completion */ + ECORE_SPQ_MODE_BLOCK, /* Client will poll a designated mem. address */ + ECORE_SPQ_MODE_CB, /* Client supplies a callback */ + ECORE_SPQ_MODE_EBLOCK, /* ECORE should block until completion */ }; struct ecore_hwfn; @@ -22,9 +22,9 @@ union event_ring_data; struct eth_slow_path_rx_cqe; struct ecore_spq_comp_cb { - void (*function)(struct ecore_hwfn *, + void (*function)(struct ecore_hwfn *, void *, union event_ring_data *, u8 fw_return_code); - void *cookie; + void *cookie; }; /** diff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c index e9ac898855..e15041534b 100644 --- a/drivers/net/qede/base/ecore_sp_commands.c +++ b/drivers/net/qede/base/ecore_sp_commands.c @@ -391,7 +391,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn, break; default: DP_NOTICE(p_hwfn, true, "Unknown personality %d\n", - p_hwfn->hw_info.personality); + p_hwfn->hw_info.personality); p_ramrod->personality = PERSONALITY_ETH; } diff --git a/drivers/net/qede/base/ecore_sp_commands.h b/drivers/net/qede/base/ecore_sp_commands.h index e281ab0eba..22c7462a8d 100644 --- a/drivers/net/qede/base/ecore_sp_commands.h +++ b/drivers/net/qede/base/ecore_sp_commands.h @@ -21,12 +21,12 @@ struct ecore_sp_init_data { * e.g., in IOV scenarios. CID might defer between SPQ and * other elements. */ - u32 cid; - u16 opaque_fid; + u32 cid; + u16 opaque_fid; /* Information regarding operation upon sending & completion */ - enum spq_mode comp_mode; - struct ecore_spq_comp_cb *p_comp_data; + enum spq_mode comp_mode; + struct ecore_spq_comp_cb *p_comp_data; }; diff --git a/drivers/net/qede/base/ecore_spq.c b/drivers/net/qede/base/ecore_spq.c index b263693f35..440f5b380f 100644 --- a/drivers/net/qede/base/ecore_spq.c +++ b/drivers/net/qede/base/ecore_spq.c @@ -49,7 +49,7 @@ static void ecore_spq_blocking_cb(struct ecore_hwfn *p_hwfn, } static enum _ecore_status_t ecore_spq_block(struct ecore_hwfn *p_hwfn, - struct ecore_spq_entry *p_ent, + struct ecore_spq_entry *p_ent, u8 *p_fw_ret) { int sleep_count = SPQ_BLOCK_SLEEP_LENGTH; @@ -83,7 +83,7 @@ static enum _ecore_status_t ecore_spq_block(struct ecore_hwfn *p_hwfn, if (comp_done->done == 1) { if (p_fw_ret) *p_fw_ret = comp_done->fw_return_code; - return ECORE_SUCCESS; + return ECORE_SUCCESS; } OSAL_MSLEEP(5); sleep_count--; @@ -310,9 +310,9 @@ enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn, p_eqe->protocol_id, /* Event Protocol ID */ p_eqe->reserved0, /* Reserved */ OSAL_LE16_TO_CPU(p_eqe->echo), - p_eqe->fw_return_code, /* FW return code for SP - * ramrods - */ + p_eqe->fw_return_code, /* FW return code for SP + * ramrods + */ p_eqe->flags); if (GET_FIELD(p_eqe->flags, EVENT_RING_ENTRY_ASYNC)) { @@ -345,7 +345,7 @@ struct ecore_eq *ecore_eq_alloc(struct ecore_hwfn *p_hwfn, u16 num_elem) return OSAL_NULL; } - /* Allocate and initialize EQ chain */ + /* Allocate and initialize EQ chain*/ if (ecore_chain_alloc(p_hwfn->p_dev, ECORE_CHAIN_USE_TO_PRODUCE, ECORE_CHAIN_MODE_PBL, @@ -607,32 +607,32 @@ ecore_spq_add_entry(struct ecore_hwfn *p_hwfn, p_spq->unlimited_pending_count++; return ECORE_SUCCESS; - } + } else { + struct ecore_spq_entry *p_en2; - struct ecore_spq_entry *p_en2; + p_en2 = OSAL_LIST_FIRST_ENTRY(&p_spq->free_pool, + struct ecore_spq_entry, + list); + OSAL_LIST_REMOVE_ENTRY(&p_en2->list, &p_spq->free_pool); - p_en2 = OSAL_LIST_FIRST_ENTRY(&p_spq->free_pool, - struct ecore_spq_entry, - list); - OSAL_LIST_REMOVE_ENTRY(&p_en2->list, &p_spq->free_pool); - - /* Copy the ring element physical pointer to the new - * entry, since we are about to override the entire ring - * entry and don't want to lose the pointer. - */ - p_ent->elem.data_ptr = p_en2->elem.data_ptr; + /* Copy the ring element physical pointer to the new + * entry, since we are about to override the entire ring + * entry and don't want to lose the pointer. + */ + p_ent->elem.data_ptr = p_en2->elem.data_ptr; - /* Setting the cookie to the comp_done of the - * new element. - */ - if (p_ent->comp_cb.cookie == &p_ent->comp_done) - p_ent->comp_cb.cookie = &p_en2->comp_done; + /* Setting the cookie to the comp_done of the + * new element. + */ + if (p_ent->comp_cb.cookie == &p_ent->comp_done) + p_ent->comp_cb.cookie = &p_en2->comp_done; - *p_en2 = *p_ent; + *p_en2 = *p_ent; - OSAL_FREE(p_hwfn->p_dev, p_ent); + OSAL_FREE(p_hwfn->p_dev, p_ent); - p_ent = p_en2; + p_ent = p_en2; + } } /* entry is to be placed in 'pending' queue */ @@ -682,18 +682,18 @@ static enum _ecore_status_t ecore_spq_post_list(struct ecore_hwfn *p_hwfn, !OSAL_LIST_IS_EMPTY(head)) { struct ecore_spq_entry *p_ent = OSAL_LIST_FIRST_ENTRY(head, struct ecore_spq_entry, list); - OSAL_LIST_REMOVE_ENTRY(&p_ent->list, head); + OSAL_LIST_REMOVE_ENTRY(&p_ent->list, head); OSAL_LIST_PUSH_TAIL(&p_ent->list, &p_spq->completion_pending); - p_spq->comp_sent_count++; - - rc = ecore_spq_hw_post(p_hwfn, p_spq, p_ent); - if (rc) { - OSAL_LIST_REMOVE_ENTRY(&p_ent->list, - &p_spq->completion_pending); - __ecore_spq_return_entry(p_hwfn, p_ent); - return rc; + p_spq->comp_sent_count++; + + rc = ecore_spq_hw_post(p_hwfn, p_spq, p_ent); + if (rc) { + OSAL_LIST_REMOVE_ENTRY(&p_ent->list, + &p_spq->completion_pending); + __ecore_spq_return_entry(p_hwfn, p_ent); + return rc; + } } - } return ECORE_SUCCESS; } diff --git a/drivers/net/qede/base/ecore_spq.h b/drivers/net/qede/base/ecore_spq.h index 5c1686543b..74484ab563 100644 --- a/drivers/net/qede/base/ecore_spq.h +++ b/drivers/net/qede/base/ecore_spq.h @@ -16,24 +16,24 @@ #include "ecore_sp_api.h" union ramrod_data { - struct pf_start_ramrod_data pf_start; - struct pf_update_ramrod_data pf_update; - struct rx_queue_start_ramrod_data rx_queue_start; - struct rx_queue_update_ramrod_data rx_queue_update; - struct rx_queue_stop_ramrod_data rx_queue_stop; - struct tx_queue_start_ramrod_data tx_queue_start; - struct tx_queue_stop_ramrod_data tx_queue_stop; - struct vport_start_ramrod_data vport_start; - struct vport_stop_ramrod_data vport_stop; - struct vport_update_ramrod_data vport_update; - struct core_rx_start_ramrod_data core_rx_queue_start; - struct core_rx_stop_ramrod_data core_rx_queue_stop; - struct core_tx_start_ramrod_data core_tx_queue_start; - struct core_tx_stop_ramrod_data core_tx_queue_stop; - struct vport_filter_update_ramrod_data vport_filter_update; - - struct vf_start_ramrod_data vf_start; - struct vf_stop_ramrod_data vf_stop; + struct pf_start_ramrod_data pf_start; + struct pf_update_ramrod_data pf_update; + struct rx_queue_start_ramrod_data rx_queue_start; + struct rx_queue_update_ramrod_data rx_queue_update; + struct rx_queue_stop_ramrod_data rx_queue_stop; + struct tx_queue_start_ramrod_data tx_queue_start; + struct tx_queue_stop_ramrod_data tx_queue_stop; + struct vport_start_ramrod_data vport_start; + struct vport_stop_ramrod_data vport_stop; + struct vport_update_ramrod_data vport_update; + struct core_rx_start_ramrod_data core_rx_queue_start; + struct core_rx_stop_ramrod_data core_rx_queue_stop; + struct core_tx_start_ramrod_data core_tx_queue_start; + struct core_tx_stop_ramrod_data core_tx_queue_stop; + struct vport_filter_update_ramrod_data vport_filter_update; + + struct vf_start_ramrod_data vf_start; + struct vf_stop_ramrod_data vf_stop; }; #define EQ_MAX_CREDIT 0xffffffff @@ -45,83 +45,83 @@ enum spq_priority { union ecore_spq_req_comp { struct ecore_spq_comp_cb cb; - u64 *done_addr; + u64 *done_addr; }; /* SPQ_MODE_EBLOCK */ struct ecore_spq_comp_done { u64 done; - u8 fw_return_code; + u8 fw_return_code; }; struct ecore_spq_entry { - osal_list_entry_t list; + osal_list_entry_t list; - u8 flags; + u8 flags; /* HSI slow path element */ - struct slow_path_element elem; + struct slow_path_element elem; - union ramrod_data ramrod; + union ramrod_data ramrod; - enum spq_priority priority; + enum spq_priority priority; /* pending queue for this entry */ - osal_list_t *queue; + osal_list_t *queue; - enum spq_mode comp_mode; - struct ecore_spq_comp_cb comp_cb; - struct ecore_spq_comp_done comp_done; /* SPQ_MODE_EBLOCK */ + enum spq_mode comp_mode; + struct ecore_spq_comp_cb comp_cb; + struct ecore_spq_comp_done comp_done; /* SPQ_MODE_EBLOCK */ }; struct ecore_eq { - struct ecore_chain chain; - u8 eq_sb_index; /* index within the SB */ - __le16 *p_fw_cons; /* ptr to index value */ + struct ecore_chain chain; + u8 eq_sb_index; /* index within the SB */ + __le16 *p_fw_cons; /* ptr to index value */ }; struct ecore_consq { - struct ecore_chain chain; + struct ecore_chain chain; }; struct ecore_spq { - osal_spinlock_t lock; + osal_spinlock_t lock; - osal_list_t unlimited_pending; - osal_list_t pending; - osal_list_t completion_pending; - osal_list_t free_pool; + osal_list_t unlimited_pending; + osal_list_t pending; + osal_list_t completion_pending; + osal_list_t free_pool; - struct ecore_chain chain; + struct ecore_chain chain; /* allocated dma-able memory for spq entries (+ramrod data) */ - dma_addr_t p_phys; - struct ecore_spq_entry *p_virt; + dma_addr_t p_phys; + struct ecore_spq_entry *p_virt; /* Bitmap for handling out-of-order completions */ -#define SPQ_RING_SIZE \ +#define SPQ_RING_SIZE \ (CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element)) #define SPQ_COMP_BMAP_SIZE \ (SPQ_RING_SIZE / (sizeof(unsigned long) * 8 /* BITS_PER_LONG */)) - unsigned long p_comp_bitmap[SPQ_COMP_BMAP_SIZE]; - u8 comp_bitmap_idx; -#define SPQ_COMP_BMAP_SET_BIT(p_spq, idx) \ -(OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) + unsigned long p_comp_bitmap[SPQ_COMP_BMAP_SIZE]; + u8 comp_bitmap_idx; +#define SPQ_COMP_BMAP_SET_BIT(p_spq, idx) \ + (OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) -#define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx) \ -(OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) +#define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx) \ + (OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) -#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx) \ -(OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) +#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx) \ + (OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap)) /* Statistics */ - u32 unlimited_pending_count; - u32 normal_count; - u32 high_count; - u32 comp_sent_count; - u32 comp_count; + u32 unlimited_pending_count; + u32 normal_count; + u32 high_count; + u32 comp_sent_count; + u32 comp_count; - u32 cid; + u32 cid; }; struct ecore_port; @@ -136,9 +136,9 @@ struct ecore_hwfn; * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn, +enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn, struct ecore_spq_entry *p_ent, - u8 *fw_return_code); + u8 *fw_return_code); /** * @brief ecore_spq_allocate - Alloocates & initializes the SPQ and EQ. @@ -147,7 +147,7 @@ enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn, * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_spq_alloc(struct ecore_hwfn *p_hwfn); +enum _ecore_status_t ecore_spq_alloc(struct ecore_hwfn *p_hwfn); /** * @brief ecore_spq_setup - Reset the SPQ to its start state. @@ -184,8 +184,8 @@ ecore_spq_get_entry(struct ecore_hwfn *p_hwfn, struct ecore_spq_entry **pp_ent); * @param p_hwfn * @param p_ent */ -void ecore_spq_return_entry(struct ecore_hwfn *p_hwfn, - struct ecore_spq_entry *p_ent); +void ecore_spq_return_entry(struct ecore_hwfn *p_hwfn, + struct ecore_spq_entry *p_ent); /** * @brief ecore_eq_allocate - Allocates & initializes an EQ struct * @@ -228,8 +228,8 @@ void ecore_eq_prod_update(struct ecore_hwfn *p_hwfn, u16 prod); * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn, - void *cookie); +enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn, + void *cookie); /** * @brief ecore_spq_completion - Completes a single event @@ -240,10 +240,10 @@ enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn, * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn, - __le16 echo, - u8 fw_return_code, - union event_ring_data *p_data); +enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn, + __le16 echo, + u8 fw_return_code, + union event_ring_data *p_data); /** * @brief ecore_spq_get_cid - Given p_hwfn, return cid for the hwfn's SPQ @@ -262,7 +262,7 @@ u32 ecore_spq_get_cid(struct ecore_hwfn *p_hwfn); * * @return struct ecore_eq* - a newly allocated structure; NULL upon error. */ -struct ecore_consq *ecore_consq_alloc(struct ecore_hwfn *p_hwfn); +struct ecore_consq *ecore_consq_alloc(struct ecore_hwfn *p_hwfn); /** * @brief ecore_consq_setup - Reset the ConsQ to its start diff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c index 1b3119d210..d8d1aac047 100644 --- a/drivers/net/qede/base/ecore_sriov.c +++ b/drivers/net/qede/base/ecore_sriov.c @@ -393,16 +393,16 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn, int *pos = &p_hwfn->p_dev->sriov_info.pos; *pos = OSAL_PCI_FIND_EXT_CAPABILITY(p_hwfn->p_dev, - PCI_EXT_CAP_ID_SRIOV); + PCI_EXT_CAP_ID_SRIOV); if (!*pos) { DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "No PCIe IOV support\n"); - return ECORE_SUCCESS; - } + return ECORE_SUCCESS; + } - rc = ecore_iov_pci_cfg_info(p_dev); - if (rc) - return rc; + rc = ecore_iov_pci_cfg_info(p_dev); + if (rc) + return rc; } else if (!p_hwfn->p_dev->sriov_info.pos) { DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "No PCIe IOV support\n"); return ECORE_SUCCESS; @@ -413,7 +413,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn, * after the first engine's VFs. */ p_hwfn->hw_info.first_vf_in_pf = p_hwfn->p_dev->sriov_info.offset + - p_hwfn->abs_pf_id - 16; + p_hwfn->abs_pf_id - 16; if (ECORE_PATH_ID(p_hwfn)) p_hwfn->hw_info.first_vf_in_pf -= MAX_NUM_VFS_BB; @@ -448,12 +448,12 @@ void ecore_iov_set_vf_to_disable(struct ecore_hwfn *p_hwfn, { struct ecore_vf_info *vf; - vf = ecore_iov_get_vf_info(p_hwfn, rel_vf_id, false); - if (!vf) + vf = ecore_iov_get_vf_info(p_hwfn, rel_vf_id, false); + if (!vf) return; - vf->to_disable = to_disable; -} + vf->to_disable = to_disable; + } void ecore_iov_set_vfs_to_disable(struct ecore_hwfn *p_hwfn, u8 to_disable) { @@ -504,7 +504,7 @@ static OSAL_INLINE void ecore_iov_vf_semi_clear_err(struct ecore_hwfn *p_hwfn, ecore_wr(p_hwfn, p_ptt, PSEM_REG_VF_ERROR, 1); } -static void ecore_iov_vf_pglue_clear_err(struct ecore_hwfn *p_hwfn, +static void ecore_iov_vf_pglue_clear_err(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u8 abs_vfid) { ecore_wr(p_hwfn, p_ptt, @@ -754,7 +754,7 @@ enum _ecore_status_t ecore_iov_init_hw_for_vf(struct ecore_hwfn *p_hwfn, { enum _ecore_status_t rc = ECORE_SUCCESS; struct ecore_vf_info *vf = OSAL_NULL; - u8 num_of_vf_available_chains = 0; + u8 num_of_vf_available_chains = 0; u32 cids; u8 i; @@ -896,9 +896,9 @@ static void ecore_iov_lock_vf_pf_channel(struct ecore_hwfn *p_hwfn, /* vf->op_current = tlv; @@@TBD MichalK */ /* log the lock */ - DP_VERBOSE(p_hwfn, - ECORE_MSG_IOV, - "VF[%d]: vf pf channel locked by %s\n", + DP_VERBOSE(p_hwfn, + ECORE_MSG_IOV, + "VF[%d]: vf pf channel locked by %s\n", vf->abs_vf_id, ecore_channel_tlvs_string[tlv]); } @@ -921,9 +921,9 @@ static void ecore_iov_unlock_vf_pf_channel(struct ecore_hwfn *p_hwfn, /* mutex_unlock(&vf->op_mutex); @@@TBD MichalK add the lock */ /* log the unlock */ - DP_VERBOSE(p_hwfn, - ECORE_MSG_IOV, - "VF[%d]: vf pf channel unlocked by %s\n", + DP_VERBOSE(p_hwfn, + ECORE_MSG_IOV, + "VF[%d]: vf pf channel unlocked by %s\n", vf->abs_vf_id, ecore_channel_tlvs_string[expected_tlv]); /* record the locking op */ @@ -1131,9 +1131,9 @@ static void ecore_iov_vf_cleanup(struct ecore_hwfn *p_hwfn, OSAL_IOV_VF_CLEANUP(p_hwfn, p_vf->relative_vf_id); } -static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - struct ecore_vf_info *vf) +static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + struct ecore_vf_info *vf) { struct ecore_iov_vf_mbx *mbx = &vf->vf_mbx; struct vfpf_acquire_tlv *req = &mbx->req_virt->acquire; @@ -1148,7 +1148,7 @@ static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn, req->vfdev_info.fw_minor != FW_MINOR_VERSION || req->vfdev_info.fw_revision != FW_REVISION_VERSION || req->vfdev_info.fw_engineering != FW_ENGINEERING_VERSION) { - DP_INFO(p_hwfn, + DP_INFO(p_hwfn, "VF[%d] is running an incompatible driver [VF needs" " FW %02x:%02x:%02x:%02x but Hypervisor is" " using %02x:%02x:%02x:%02x]\n", @@ -1323,25 +1323,25 @@ ecore_iov_reconfigure_unicast_vlan(struct ecore_hwfn *p_hwfn, /* Reconfigure vlans */ for (i = 0; i < ECORE_ETH_VF_NUM_VLAN_FILTERS + 1; i++) { if (p_vf->shadow_config.vlans[i].used) { - filter.type = ECORE_FILTER_VLAN; - filter.vlan = p_vf->shadow_config.vlans[i].vid; - DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, + filter.type = ECORE_FILTER_VLAN; + filter.vlan = p_vf->shadow_config.vlans[i].vid; + DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "Reconfig VLAN [0x%04x] for VF [%04x]\n", - filter.vlan, p_vf->relative_vf_id); - rc = ecore_sp_eth_filter_ucast(p_hwfn, - p_vf->opaque_fid, - &filter, - ECORE_SPQ_MODE_CB, + filter.vlan, p_vf->relative_vf_id); + rc = ecore_sp_eth_filter_ucast(p_hwfn, + p_vf->opaque_fid, + &filter, + ECORE_SPQ_MODE_CB, OSAL_NULL); - if (rc) { - DP_NOTICE(p_hwfn, true, - "Failed to configure VLAN [%04x]" - " to VF [%04x]\n", - filter.vlan, p_vf->relative_vf_id); - break; - } + if (rc) { + DP_NOTICE(p_hwfn, true, + "Failed to configure VLAN [%04x]" + " to VF [%04x]\n", + filter.vlan, p_vf->relative_vf_id); + break; } } + } return rc; } @@ -1646,14 +1646,14 @@ static void ecore_iov_vf_mbx_start_txq(struct ecore_hwfn *p_hwfn, pq_params.eth.vf_id = vf->relative_vf_id; rc = ecore_sp_eth_txq_start_ramrod(p_hwfn, - vf->opaque_fid, - vf->vf_queues[req->tx_qid].fw_tx_qid, - vf->vf_queues[req->tx_qid].fw_cid, - vf->vport_id, - vf->abs_vf_id + 0x10, - req->hw_sb, - req->sb_index, - req->pbl_addr, + vf->opaque_fid, + vf->vf_queues[req->tx_qid].fw_tx_qid, + vf->vf_queues[req->tx_qid].fw_cid, + vf->vport_id, + vf->abs_vf_id + 0x10, + req->hw_sb, + req->sb_index, + req->pbl_addr, req->pbl_size, &pq_params); if (rc) @@ -1852,12 +1852,12 @@ ecore_iov_vp_update_act_param(struct ecore_hwfn *p_hwfn, p_act_tlv = (struct vfpf_vport_update_activate_tlv *) ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv); if (p_act_tlv) { - p_data->update_vport_active_rx_flg = p_act_tlv->update_rx; - p_data->vport_active_rx_flg = p_act_tlv->active_rx; - p_data->update_vport_active_tx_flg = p_act_tlv->update_tx; - p_data->vport_active_tx_flg = p_act_tlv->active_tx; - *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACTIVATE; - } + p_data->update_vport_active_rx_flg = p_act_tlv->update_rx; + p_data->vport_active_rx_flg = p_act_tlv->active_rx; + p_data->update_vport_active_tx_flg = p_act_tlv->update_tx; + p_data->vport_active_tx_flg = p_act_tlv->active_tx; + *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACTIVATE; +} } static void @@ -1905,10 +1905,10 @@ ecore_iov_vp_update_tx_switch(struct ecore_hwfn *p_hwfn, #endif if (p_tx_switch_tlv) { - p_data->update_tx_switching_flg = 1; - p_data->tx_switching_flg = p_tx_switch_tlv->tx_switching; - *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_TX_SWITCH; - } + p_data->update_tx_switching_flg = 1; + p_data->tx_switching_flg = p_tx_switch_tlv->tx_switching; + *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_TX_SWITCH; +} } static void @@ -1924,12 +1924,12 @@ ecore_iov_vp_update_mcast_bin_param(struct ecore_hwfn *p_hwfn, ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv); if (p_mcast_tlv) { - p_data->update_approx_mcast_flg = 1; - OSAL_MEMCPY(p_data->bins, p_mcast_tlv->bins, - sizeof(unsigned long) * - ETH_MULTICAST_MAC_BINS_IN_REGS); - *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_MCAST; - } + p_data->update_approx_mcast_flg = 1; + OSAL_MEMCPY(p_data->bins, p_mcast_tlv->bins, + sizeof(unsigned long) * + ETH_MULTICAST_MAC_BINS_IN_REGS); + *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_MCAST; +} } static void @@ -1952,8 +1952,8 @@ ecore_iov_vp_update_accept_flag(struct ecore_hwfn *p_hwfn, p_accept_tlv->update_tx_mode; p_data->accept_flags.tx_accept_filter = p_accept_tlv->tx_accept_filter; - *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_PARAM; - } + *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_PARAM; +} } static void @@ -1969,11 +1969,11 @@ ecore_iov_vp_update_accept_any_vlan(struct ecore_hwfn *p_hwfn, ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv); if (p_accept_any_vlan) { - p_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan; - p_data->update_accept_any_vlan_flg = - p_accept_any_vlan->update_accept_any_vlan_flg; - *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN; - } + p_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan; + p_data->update_accept_any_vlan_flg = + p_accept_any_vlan->update_accept_any_vlan_flg; + *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_ACCEPT_ANY_VLAN; +} } static void @@ -1991,48 +1991,48 @@ ecore_iov_vp_update_rss_param(struct ecore_hwfn *p_hwfn, p_rss_tlv = (struct vfpf_vport_update_rss_tlv *) ecore_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv); if (p_rss_tlv) { - OSAL_MEMSET(p_rss, 0, sizeof(struct ecore_rss_params)); - - p_rss->update_rss_config = - !!(p_rss_tlv->update_rss_flags & - VFPF_UPDATE_RSS_CONFIG_FLAG); - p_rss->update_rss_capabilities = - !!(p_rss_tlv->update_rss_flags & - VFPF_UPDATE_RSS_CAPS_FLAG); - p_rss->update_rss_ind_table = - !!(p_rss_tlv->update_rss_flags & - VFPF_UPDATE_RSS_IND_TABLE_FLAG); - p_rss->update_rss_key = + OSAL_MEMSET(p_rss, 0, sizeof(struct ecore_rss_params)); + + p_rss->update_rss_config = + !!(p_rss_tlv->update_rss_flags & + VFPF_UPDATE_RSS_CONFIG_FLAG); + p_rss->update_rss_capabilities = + !!(p_rss_tlv->update_rss_flags & + VFPF_UPDATE_RSS_CAPS_FLAG); + p_rss->update_rss_ind_table = + !!(p_rss_tlv->update_rss_flags & + VFPF_UPDATE_RSS_IND_TABLE_FLAG); + p_rss->update_rss_key = !!(p_rss_tlv->update_rss_flags & VFPF_UPDATE_RSS_KEY_FLAG); - p_rss->rss_enable = p_rss_tlv->rss_enable; - p_rss->rss_eng_id = vf->relative_vf_id + 1; - p_rss->rss_caps = p_rss_tlv->rss_caps; - p_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log; - OSAL_MEMCPY(p_rss->rss_ind_table, p_rss_tlv->rss_ind_table, - sizeof(p_rss->rss_ind_table)); - OSAL_MEMCPY(p_rss->rss_key, p_rss_tlv->rss_key, - sizeof(p_rss->rss_key)); + p_rss->rss_enable = p_rss_tlv->rss_enable; + p_rss->rss_eng_id = vf->relative_vf_id + 1; + p_rss->rss_caps = p_rss_tlv->rss_caps; + p_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log; + OSAL_MEMCPY(p_rss->rss_ind_table, p_rss_tlv->rss_ind_table, + sizeof(p_rss->rss_ind_table)); + OSAL_MEMCPY(p_rss->rss_key, p_rss_tlv->rss_key, + sizeof(p_rss->rss_key)); table_size = OSAL_MIN_T(u16, OSAL_ARRAY_SIZE(p_rss->rss_ind_table), - (1 << p_rss_tlv->rss_table_size_log)); + (1 << p_rss_tlv->rss_table_size_log)); - max_q_idx = OSAL_ARRAY_SIZE(vf->vf_queues); + max_q_idx = OSAL_ARRAY_SIZE(vf->vf_queues); - for (i = 0; i < table_size; i++) { - q_idx = p_rss->rss_ind_table[i]; + for (i = 0; i < table_size; i++) { + q_idx = p_rss->rss_ind_table[i]; if (q_idx >= max_q_idx) { - DP_NOTICE(p_hwfn, true, + DP_NOTICE(p_hwfn, true, "rss_ind_table[%d] = %d, rxq is out of range\n", - i, q_idx); + i, q_idx); /* TBD: fail the request mark VF as malicious */ p_rss->rss_ind_table[i] = vf->vf_queues[0].fw_rx_qid; } else if (!vf->vf_queues[q_idx].rxq_active) { - DP_NOTICE(p_hwfn, true, - "rss_ind_table[%d] = %d, rxq is not active\n", - i, q_idx); + DP_NOTICE(p_hwfn, true, + "rss_ind_table[%d] = %d, rxq is not active\n", + i, q_idx); /* TBD: fail the request mark VF as malicious */ p_rss->rss_ind_table[i] = vf->vf_queues[0].fw_rx_qid; @@ -2040,10 +2040,10 @@ ecore_iov_vp_update_rss_param(struct ecore_hwfn *p_hwfn, p_rss->rss_ind_table[i] = vf->vf_queues[q_idx].fw_rx_qid; } - } + } - p_data->rss_params = p_rss; - *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_RSS; + p_data->rss_params = p_rss; + *tlvs_mask |= 1 << ECORE_IOV_VP_UPDATE_RSS; } else { p_data->rss_params = OSAL_NULL; } @@ -2172,8 +2172,8 @@ out: static enum _ecore_status_t ecore_iov_vf_update_unicast_shadow(struct ecore_hwfn *p_hwfn, - struct ecore_vf_info *p_vf, - struct ecore_filter_ucast *p_params) + struct ecore_vf_info *p_vf, + struct ecore_filter_ucast *p_params) { int i; @@ -2212,11 +2212,11 @@ ecore_iov_vf_update_unicast_shadow(struct ecore_hwfn *p_hwfn, p_params->opcode == ECORE_FILTER_REPLACE) { for (i = 0; i < ECORE_ETH_VF_NUM_VLAN_FILTERS + 1; i++) if (!p_vf->shadow_config.vlans[i].used) { - p_vf->shadow_config.vlans[i].used = true; + p_vf->shadow_config.vlans[i].used = true; p_vf->shadow_config.vlans[i].vid = p_params->vlan; - break; - } + break; + } if (i == ECORE_ETH_VF_NUM_VLAN_FILTERS + 1) { DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "VF [%d] - Tries to configure more than %d vlan filters\n", @@ -2737,11 +2737,11 @@ void ecore_iov_process_mbx_req(struct ecore_hwfn *p_hwfn, /* check if tlv type is known */ if (ecore_iov_tlv_supported(mbx->first_tlv.tl.type)) { - /* Lock the per vf op mutex and note the locker's identity. - * The unlock will take place in mbx response. - */ - ecore_iov_lock_vf_pf_channel(p_hwfn, - p_vf, mbx->first_tlv.tl.type); + /* Lock the per vf op mutex and note the locker's identity. + * The unlock will take place in mbx response. + */ + ecore_iov_lock_vf_pf_channel(p_hwfn, + p_vf, mbx->first_tlv.tl.type); /* switch on the opcode */ switch (mbx->first_tlv.tl.type) { diff --git a/drivers/net/qede/base/ecore_sriov.h b/drivers/net/qede/base/ecore_sriov.h index 3471e5c683..7eca169470 100644 --- a/drivers/net/qede/base/ecore_sriov.h +++ b/drivers/net/qede/base/ecore_sriov.h @@ -57,13 +57,13 @@ struct ecore_vf_iov { * a message */ struct ecore_iov_vf_mbx { - union vfpf_tlvs *req_virt; - dma_addr_t req_phys; - union pfvf_tlvs *reply_virt; - dma_addr_t reply_phys; + union vfpf_tlvs *req_virt; + dma_addr_t req_phys; + union pfvf_tlvs *reply_virt; + dma_addr_t reply_phys; /* Address in VF where a pending message is located */ - dma_addr_t pending_req; + dma_addr_t pending_req; u8 *offset; @@ -72,12 +72,12 @@ struct ecore_iov_vf_mbx { #endif /* VF GPA address */ - u32 vf_addr_lo; - u32 vf_addr_hi; + u32 vf_addr_lo; + u32 vf_addr_hi; - struct vfpf_first_tlv first_tlv; /* saved VF request header */ + struct vfpf_first_tlv first_tlv; /* saved VF request header */ - u8 flags; + u8 flags; #define VF_MSG_INPROCESS 0x1 /* failsafe - the FW should prevent * more then one pending msg */ @@ -101,11 +101,11 @@ enum int_mod { }; enum vf_state { - VF_FREE = 0, /* VF ready to be acquired holds no resc */ - VF_ACQUIRED = 1, /* VF, acquired, but not initalized */ - VF_ENABLED = 2, /* VF, Enabled */ - VF_RESET = 3, /* VF, FLR'd, pending cleanup */ - VF_STOPPED = 4 /* VF, Stopped */ + VF_FREE = 0, /* VF ready to be acquired holds no resc */ + VF_ACQUIRED = 1, /* VF, acquired, but not initalized */ + VF_ENABLED = 2, /* VF, Enabled */ + VF_RESET = 3, /* VF, FLR'd, pending cleanup */ + VF_STOPPED = 4 /* VF, Stopped */ }; struct ecore_vf_vlan_shadow { @@ -124,34 +124,34 @@ struct ecore_vf_shadow_config { struct ecore_vf_info { struct ecore_iov_vf_mbx vf_mbx; enum vf_state state; - u8 to_disable; + u8 to_disable; - struct ecore_bulletin bulletin; - dma_addr_t vf_bulletin; + struct ecore_bulletin bulletin; + dma_addr_t vf_bulletin; - u32 concrete_fid; - u16 opaque_fid; - u16 mtu; + u32 concrete_fid; + u16 opaque_fid; + u16 mtu; - u8 vport_id; - u8 relative_vf_id; - u8 abs_vf_id; + u8 vport_id; + u8 relative_vf_id; + u8 abs_vf_id; #define ECORE_VF_ABS_ID(p_hwfn, p_vf) (ECORE_PATH_ID(p_hwfn) ? \ (p_vf)->abs_vf_id + MAX_NUM_VFS_BB : \ (p_vf)->abs_vf_id) - u8 vport_instance; /* Number of active vports */ - u8 num_rxqs; - u8 num_txqs; + u8 vport_instance; /* Number of active vports */ + u8 num_rxqs; + u8 num_txqs; - u8 num_sbs; + u8 num_sbs; - u8 num_mac_filters; - u8 num_vlan_filters; + u8 num_mac_filters; + u8 num_vlan_filters; u8 num_mc_filters; - struct ecore_vf_q_info vf_queues[ECORE_MAX_VF_CHAINS_PER_PF]; - u16 igu_sbs[ECORE_MAX_VF_CHAINS_PER_PF]; + struct ecore_vf_q_info vf_queues[ECORE_MAX_VF_CHAINS_PER_PF]; + u16 igu_sbs[ECORE_MAX_VF_CHAINS_PER_PF]; /* TODO - Only windows is using it - should be removed */ u8 was_malicious; @@ -159,7 +159,7 @@ struct ecore_vf_info { void *ctx; struct ecore_public_vf_info p_vf_info; bool spoof_chk; /* Current configured on HW */ - bool req_spoofchk_val; /* Requested value */ + bool req_spoofchk_val; /* Requested value */ /* Stores the configuration requested by VF */ struct ecore_vf_shadow_config shadow_config; @@ -176,21 +176,21 @@ struct ecore_vf_info { * capability enabled. */ struct ecore_pf_iov { - struct ecore_vf_info vfs_array[MAX_NUM_VFS]; - u64 pending_events[ECORE_VF_ARRAY_LENGTH]; - u64 pending_flr[ECORE_VF_ARRAY_LENGTH]; - u16 base_vport_id; + struct ecore_vf_info vfs_array[MAX_NUM_VFS]; + u64 pending_events[ECORE_VF_ARRAY_LENGTH]; + u64 pending_flr[ECORE_VF_ARRAY_LENGTH]; + u16 base_vport_id; /* Allocate message address continuosuly and split to each VF */ - void *mbx_msg_virt_addr; - dma_addr_t mbx_msg_phys_addr; - u32 mbx_msg_size; - void *mbx_reply_virt_addr; - dma_addr_t mbx_reply_phys_addr; - u32 mbx_reply_size; - void *p_bulletins; - dma_addr_t bulletins_phys; - u32 bulletins_size; + void *mbx_msg_virt_addr; + dma_addr_t mbx_msg_phys_addr; + u32 mbx_msg_size; + void *mbx_reply_virt_addr; + dma_addr_t mbx_reply_phys_addr; + u32 mbx_reply_size; + void *p_bulletins; + dma_addr_t bulletins_phys; + u32 bulletins_size; }; #ifdef CONFIG_ECORE_SRIOV @@ -217,7 +217,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn, * * @return pointer to the newly placed tlv */ -void *ecore_add_tlv(struct ecore_hwfn *p_hwfn, +void *ecore_add_tlv(struct ecore_hwfn *p_hwfn, u8 **offset, u16 type, u16 length); /** @@ -260,9 +260,9 @@ void ecore_iov_free(struct ecore_hwfn *p_hwfn); * @param echo * @param data */ -enum _ecore_status_t ecore_sriov_eqe_event(struct ecore_hwfn *p_hwfn, - u8 opcode, - __le16 echo, +enum _ecore_status_t ecore_sriov_eqe_event(struct ecore_hwfn *p_hwfn, + u8 opcode, + __le16 echo, union event_ring_data *data); /** diff --git a/drivers/net/qede/base/ecore_status.h b/drivers/net/qede/base/ecore_status.h index 98d40bb534..6277bc80c5 100644 --- a/drivers/net/qede/base/ecore_status.h +++ b/drivers/net/qede/base/ecore_status.h @@ -10,18 +10,18 @@ #define __ECORE_STATUS_H__ enum _ecore_status_t { - ECORE_UNKNOWN_ERROR = -12, - ECORE_NORESOURCES = -11, - ECORE_NODEV = -10, + ECORE_UNKNOWN_ERROR = -12, + ECORE_NORESOURCES = -11, + ECORE_NODEV = -10, ECORE_ABORTED = -9, - ECORE_AGAIN = -8, + ECORE_AGAIN = -8, ECORE_NOTIMPL = -7, - ECORE_EXISTS = -6, - ECORE_IO = -5, + ECORE_EXISTS = -6, + ECORE_IO = -5, ECORE_TIMEOUT = -4, - ECORE_INVAL = -3, - ECORE_BUSY = -2, - ECORE_NOMEM = -1, + ECORE_INVAL = -3, + ECORE_BUSY = -2, + ECORE_NOMEM = -1, ECORE_SUCCESS = 0, /* PENDING is not an error and should be positive */ ECORE_PENDING = 1, diff --git a/drivers/net/qede/base/ecore_vf.c b/drivers/net/qede/base/ecore_vf.c index d32fb35ae9..a03a2ce9a6 100644 --- a/drivers/net/qede/base/ecore_vf.c +++ b/drivers/net/qede/base/ecore_vf.c @@ -264,7 +264,7 @@ static enum _ecore_status_t ecore_vf_pf_acquire(struct ecore_hwfn *p_hwfn) p_hwfn->p_dev->chip_num = pfdev_info->chip_num & 0xffff; return 0; -} + } enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev) { @@ -280,7 +280,7 @@ enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev) "regview should be initialized before" " ecore_vf_hw_prepare is called\n"); return ECORE_INVAL; - } +} /* Set the doorbell bar. Assumption: regview is set */ p_hwfn->doorbells = (u8 OSAL_IOMEM *)p_hwfn->regview + @@ -310,7 +310,7 @@ enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev) vfpf_tlvs)); if (!p_sriov->vf2pf_request) { DP_NOTICE(p_hwfn, true, - "Failed to allocate `vf2pf_request' DMA memory\n"); + "Failed to allocate `vf2pf_request' DMA memory\n"); goto free_p_sriov; } @@ -388,7 +388,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn, dma_addr_t bd_chain_phys_addr, dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size, - void OSAL_IOMEM * *pp_prod) + void OSAL_IOMEM **pp_prod) { struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; struct vfpf_start_rxq_tlv *req; @@ -421,7 +421,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn, hw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid]; *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview + - MSTORM_QZONE_START(p_hwfn->p_dev) + + MSTORM_QZONE_START(p_hwfn->p_dev) + (hw_qid) * MSTORM_QZONE_SIZE + OFFSETOF(struct mstorm_eth_queue_zone, rx_producers); @@ -481,7 +481,7 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn, u8 sb_index, dma_addr_t pbl_addr, u16 pbl_size, - void OSAL_IOMEM * *pp_doorbell) + void OSAL_IOMEM **pp_doorbell) { struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; struct vfpf_start_txq_tlv *req; @@ -519,8 +519,8 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn, u8 cid = p_iov->acquire_resp.resc.cid[tx_queue_id]; *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells + - DB_ADDR_VF(cid, DQ_DEMS_LEGACY); - } + DB_ADDR_VF(cid, DQ_DEMS_LEGACY); + } return rc; } @@ -1117,7 +1117,7 @@ enum _ecore_status_t ecore_vf_pf_int_cleanup(struct ecore_hwfn *p_hwfn) rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp)); if (rc) - return rc; + return rc; if (resp->hdr.status != PFVF_STATUS_SUCCESS) return ECORE_INVAL; diff --git a/drivers/net/qede/base/ecore_vf.h b/drivers/net/qede/base/ecore_vf.h index 334b588ccd..7600710885 100644 --- a/drivers/net/qede/base/ecore_vf.h +++ b/drivers/net/qede/base/ecore_vf.h @@ -18,7 +18,7 @@ /** * * @brief hw preparation for VF - * sends ACQUIRE message + * sends ACQUIRE message * * @param p_dev * @@ -63,7 +63,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn, dma_addr_t bd_chain_phys_addr, dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size, - void OSAL_IOMEM * *pp_prod); + void OSAL_IOMEM **pp_prod); /** * @@ -76,7 +76,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn, * @param sb_index - index within the status block * @param bd_chain_phys_addr - physical address of tx chain * @param pp_doorbell - pointer to address to which to - * write the doorbell too.. + * write the doorbell too.. * * @return enum _ecore_status_t */ @@ -86,7 +86,7 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn, u8 sb_index, dma_addr_t pbl_addr, u16 pbl_size, - void OSAL_IOMEM * *pp_doorbell); + void OSAL_IOMEM **pp_doorbell); /** * @@ -98,7 +98,7 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn, * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn, +enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn, u16 rx_qid, bool cqe_completion); /** @@ -110,8 +110,8 @@ enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn, * * @return enum _ecore_status_t */ -enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn, - u16 tx_qid); +enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn, + u16 tx_qid); /** * @brief VF - update the RX queue by sending a message to the @@ -127,10 +127,10 @@ enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn, * @return enum _ecore_status_t */ enum _ecore_status_t ecore_vf_pf_rxqs_update(struct ecore_hwfn *p_hwfn, - u16 rx_queue_id, - u8 num_rxqs, - u8 comp_cqe_flg, - u8 comp_event_flg); + u16 rx_queue_id, + u8 num_rxqs, + u8 comp_cqe_flg, + u8 comp_event_flg); /** * @@ -191,12 +191,12 @@ u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id); * @return enum _ecore_status */ enum _ecore_status_t ecore_vf_pf_vport_start(struct ecore_hwfn *p_hwfn, - u8 vport_id, - u16 mtu, - u8 inner_vlan_removal, - enum ecore_tpa_mode tpa_mode, - u8 max_buffers_per_cqe, - u8 only_untagged); + u8 vport_id, + u16 mtu, + u8 inner_vlan_removal, + enum ecore_tpa_mode tpa_mode, + u8 max_buffers_per_cqe, + u8 only_untagged); /** * @brief ecore_vf_pf_vport_stop - stop the VF's vport diff --git a/drivers/net/qede/base/ecore_vf_api.h b/drivers/net/qede/base/ecore_vf_api.h index f28b6860c1..a2b4ba5d55 100644 --- a/drivers/net/qede/base/ecore_vf_api.h +++ b/drivers/net/qede/base/ecore_vf_api.h @@ -79,7 +79,7 @@ void ecore_vf_get_num_vlan_filters(struct ecore_hwfn *p_hwfn, /** * @brief Get number of MAC filters allocated for VF by ecore * - * @param p_hwfn + * @param p_hwfn * @param num_mac - allocated MAC filters */ void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn, @@ -101,7 +101,7 @@ bool ecore_vf_check_mac(struct ecore_hwfn *p_hwfn, u8 *mac); * @param hwfn * @param dst_mac * @param p_is_forced - out param which indicate in case mac - * exist if it forced or not. + * exist if it forced or not. * * @return bool - return true if mac exist and false if * not. diff --git a/drivers/net/qede/base/ecore_vfpf_if.h b/drivers/net/qede/base/ecore_vfpf_if.h index 2fa4d15554..e98a2a7595 100644 --- a/drivers/net/qede/base/ecore_vfpf_if.h +++ b/drivers/net/qede/base/ecore_vfpf_if.h @@ -21,18 +21,18 @@ * **/ struct vf_pf_resc_request { - u8 num_rxqs; - u8 num_txqs; - u8 num_sbs; - u8 num_mac_filters; - u8 num_vlan_filters; - u8 num_mc_filters; /* No limit so superfluous */ + u8 num_rxqs; + u8 num_txqs; + u8 num_sbs; + u8 num_mac_filters; + u8 num_vlan_filters; + u8 num_mc_filters; /* No limit so superfluous */ u16 padding; }; struct hw_sb_info { - u16 hw_sb_id; /* aka absolute igu id, used to ack the sb */ - u8 sb_qid; /* used to update DHC for sb */ + u16 hw_sb_id; /* aka absolute igu id, used to ack the sb */ + u8 sb_qid; /* used to update DHC for sb */ u8 padding[5]; }; @@ -114,8 +114,8 @@ struct vfpf_acquire_tlv { u8 fw_revision; u8 fw_engineering; u32 driver_version; - u16 opaque_fid; /* ME register value */ - u8 os_type; /* VFPF_ACQUIRE_OS_* value */ + u16 opaque_fid; /* ME register value */ + u8 os_type; /* VFPF_ACQUIRE_OS_* value */ u8 padding[5]; } vfdev_info; @@ -128,17 +128,17 @@ struct vfpf_acquire_tlv { /* receive side scaling tlv */ struct vfpf_vport_update_rss_tlv { - struct channel_tlv tl; + struct channel_tlv tl; u8 update_rss_flags; -#define VFPF_UPDATE_RSS_CONFIG_FLAG (1 << 0) -#define VFPF_UPDATE_RSS_CAPS_FLAG (1 << 1) -#define VFPF_UPDATE_RSS_IND_TABLE_FLAG (1 << 2) -#define VFPF_UPDATE_RSS_KEY_FLAG (1 << 3) + #define VFPF_UPDATE_RSS_CONFIG_FLAG (1 << 0) + #define VFPF_UPDATE_RSS_CAPS_FLAG (1 << 1) + #define VFPF_UPDATE_RSS_IND_TABLE_FLAG (1 << 2) + #define VFPF_UPDATE_RSS_KEY_FLAG (1 << 3) u8 rss_enable; u8 rss_caps; - u8 rss_table_size_log; /* The table size is 2 ^ rss_table_size_log */ + u8 rss_table_size_log; /* The table size is 2 ^ rss_table_size_log */ u16 rss_ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; u32 rss_key[T_ETH_RSS_KEY_SIZE]; }; @@ -172,7 +172,7 @@ struct pfvf_acquire_resp_tlv { #define PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED (1 << 0) u16 db_size; - u8 indices_per_sb; + u8 indices_per_sb; u8 os_type; /* Thesee should match the PF's ecore_dev values */ @@ -192,19 +192,19 @@ struct pfvf_acquire_resp_tlv { * this struct with suggested amount of resources for next * acquire request */ -#define PFVF_MAX_QUEUES_PER_VF 16 -#define PFVF_MAX_SBS_PER_VF 16 + #define PFVF_MAX_QUEUES_PER_VF 16 + #define PFVF_MAX_SBS_PER_VF 16 struct hw_sb_info hw_sbs[PFVF_MAX_SBS_PER_VF]; - u8 hw_qid[PFVF_MAX_QUEUES_PER_VF]; - u8 cid[PFVF_MAX_QUEUES_PER_VF]; - - u8 num_rxqs; - u8 num_txqs; - u8 num_sbs; - u8 num_mac_filters; - u8 num_vlan_filters; - u8 num_mc_filters; - u8 padding[2]; + u8 hw_qid[PFVF_MAX_QUEUES_PER_VF]; + u8 cid[PFVF_MAX_QUEUES_PER_VF]; + + u8 num_rxqs; + u8 num_txqs; + u8 num_sbs; + u8 num_mac_filters; + u8 num_vlan_filters; + u8 num_mc_filters; + u8 padding[2]; } resc; u32 bulletin_size; @@ -225,141 +225,141 @@ struct vfpf_init_tlv { /* Setup Queue */ struct vfpf_start_rxq_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; /* physical addresses */ aligned_u64 rxq_addr; aligned_u64 deprecated_sge_addr; aligned_u64 cqe_pbl_addr; - u16 cqe_pbl_size; - u16 hw_sb; - u16 rx_qid; - u16 hc_rate; /* desired interrupts per sec. */ + u16 cqe_pbl_size; + u16 hw_sb; + u16 rx_qid; + u16 hc_rate; /* desired interrupts per sec. */ - u16 bd_max_bytes; - u16 stat_id; - u8 sb_index; - u8 padding[3]; + u16 bd_max_bytes; + u16 stat_id; + u8 sb_index; + u8 padding[3]; }; struct vfpf_start_txq_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; /* physical addresses */ aligned_u64 pbl_addr; - u16 pbl_size; - u16 stat_id; - u16 tx_qid; - u16 hw_sb; - - u32 flags; /* VFPF_QUEUE_FLG_X flags */ - u16 hc_rate; /* desired interrupts per sec. */ - u8 sb_index; - u8 padding[3]; + u16 pbl_size; + u16 stat_id; + u16 tx_qid; + u16 hw_sb; + + u32 flags; /* VFPF_QUEUE_FLG_X flags */ + u16 hc_rate; /* desired interrupts per sec. */ + u8 sb_index; + u8 padding[3]; }; /* Stop RX Queue */ struct vfpf_stop_rxqs_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; - u16 rx_qid; - u8 num_rxqs; - u8 cqe_completion; - u8 padding[4]; + u16 rx_qid; + u8 num_rxqs; + u8 cqe_completion; + u8 padding[4]; }; /* Stop TX Queues */ struct vfpf_stop_txqs_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; - u16 tx_qid; - u8 num_txqs; - u8 padding[5]; + u16 tx_qid; + u8 num_txqs; + u8 padding[5]; }; struct vfpf_update_rxq_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; aligned_u64 deprecated_sge_addr[PFVF_MAX_QUEUES_PER_VF]; - u16 rx_qid; - u8 num_rxqs; - u8 flags; -#define VFPF_RXQ_UPD_INIT_SGE_DEPRECATE_FLAG (1 << 0) -#define VFPF_RXQ_UPD_COMPLETE_CQE_FLAG (1 << 1) -#define VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG (1 << 2) + u16 rx_qid; + u8 num_rxqs; + u8 flags; + #define VFPF_RXQ_UPD_INIT_SGE_DEPRECATE_FLAG (1 << 0) + #define VFPF_RXQ_UPD_COMPLETE_CQE_FLAG (1 << 1) + #define VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG (1 << 2) - u8 padding[4]; + u8 padding[4]; }; /* Set Queue Filters */ struct vfpf_q_mac_vlan_filter { u32 flags; -#define VFPF_Q_FILTER_DEST_MAC_VALID 0x01 -#define VFPF_Q_FILTER_VLAN_TAG_VALID 0x02 -#define VFPF_Q_FILTER_SET_MAC 0x100 /* set/clear */ + #define VFPF_Q_FILTER_DEST_MAC_VALID 0x01 + #define VFPF_Q_FILTER_VLAN_TAG_VALID 0x02 + #define VFPF_Q_FILTER_SET_MAC 0x100 /* set/clear */ - u8 mac[ETH_ALEN]; + u8 mac[ETH_ALEN]; u16 vlan_tag; - u8 padding[4]; + u8 padding[4]; }; /* Start a vport */ struct vfpf_vport_start_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; aligned_u64 sb_addr[PFVF_MAX_SBS_PER_VF]; - u32 tpa_mode; - u16 dep1; - u16 mtu; + u32 tpa_mode; + u16 dep1; + u16 mtu; - u8 vport_id; - u8 inner_vlan_removal; + u8 vport_id; + u8 inner_vlan_removal; - u8 only_untagged; - u8 max_buffers_per_cqe; + u8 only_untagged; + u8 max_buffers_per_cqe; - u8 padding[4]; + u8 padding[4]; }; /* Extended tlvs - need to add rss, mcast, accept mode tlvs */ struct vfpf_vport_update_activate_tlv { - struct channel_tlv tl; - u8 update_rx; - u8 update_tx; - u8 active_rx; - u8 active_tx; + struct channel_tlv tl; + u8 update_rx; + u8 update_tx; + u8 active_rx; + u8 active_tx; }; struct vfpf_vport_update_tx_switch_tlv { - struct channel_tlv tl; - u8 tx_switching; - u8 padding[3]; + struct channel_tlv tl; + u8 tx_switching; + u8 padding[3]; }; struct vfpf_vport_update_vlan_strip_tlv { - struct channel_tlv tl; - u8 remove_vlan; - u8 padding[3]; + struct channel_tlv tl; + u8 remove_vlan; + u8 padding[3]; }; struct vfpf_vport_update_mcast_bin_tlv { - struct channel_tlv tl; - u8 padding[4]; + struct channel_tlv tl; + u8 padding[4]; aligned_u64 bins[8]; }; struct vfpf_vport_update_accept_param_tlv { struct channel_tlv tl; - u8 update_rx_mode; - u8 update_tx_mode; - u8 rx_accept_filter; - u8 tx_accept_filter; + u8 update_rx_mode; + u8 update_tx_mode; + u8 rx_accept_filter; + u8 tx_accept_filter; }; struct vfpf_vport_update_accept_any_vlan_tlv { @@ -371,29 +371,29 @@ struct vfpf_vport_update_accept_any_vlan_tlv { }; struct vfpf_vport_update_sge_tpa_tlv { - struct channel_tlv tl; + struct channel_tlv tl; - u16 sge_tpa_flags; -#define VFPF_TPA_IPV4_EN_FLAG (1 << 0) -#define VFPF_TPA_IPV6_EN_FLAG (1 << 1) -#define VFPF_TPA_PKT_SPLIT_FLAG (1 << 2) -#define VFPF_TPA_HDR_DATA_SPLIT_FLAG (1 << 3) -#define VFPF_TPA_GRO_CONSIST_FLAG (1 << 4) + u16 sge_tpa_flags; + #define VFPF_TPA_IPV4_EN_FLAG (1 << 0) + #define VFPF_TPA_IPV6_EN_FLAG (1 << 1) + #define VFPF_TPA_PKT_SPLIT_FLAG (1 << 2) + #define VFPF_TPA_HDR_DATA_SPLIT_FLAG (1 << 3) + #define VFPF_TPA_GRO_CONSIST_FLAG (1 << 4) - u8 update_sge_tpa_flags; -#define VFPF_UPDATE_SGE_DEPRECATED_FLAG (1 << 0) -#define VFPF_UPDATE_TPA_EN_FLAG (1 << 1) -#define VFPF_UPDATE_TPA_PARAM_FLAG (1 << 2) + u8 update_sge_tpa_flags; + #define VFPF_UPDATE_SGE_DEPRECATED_FLAG (1 << 0) + #define VFPF_UPDATE_TPA_EN_FLAG (1 << 1) + #define VFPF_UPDATE_TPA_PARAM_FLAG (1 << 2) - u8 max_buffers_per_cqe; + u8 max_buffers_per_cqe; - u16 deprecated_sge_buff_size; - u16 tpa_max_size; - u16 tpa_min_size_to_start; - u16 tpa_min_size_to_cont; + u16 deprecated_sge_buff_size; + u16 tpa_max_size; + u16 tpa_min_size_to_start; + u16 tpa_min_size_to_cont; - u8 tpa_max_aggs_num; - u8 padding[7]; + u8 tpa_max_aggs_num; + u8 padding[7]; }; @@ -405,15 +405,15 @@ struct vfpf_vport_update_tlv { }; struct vfpf_ucast_filter_tlv { - struct vfpf_first_tlv first_tlv; + struct vfpf_first_tlv first_tlv; - u8 opcode; - u8 type; + u8 opcode; + u8 type; - u8 mac[ETH_ALEN]; + u8 mac[ETH_ALEN]; - u16 vlan; - u16 padding[3]; + u16 vlan; + u16 padding[3]; }; struct tlv_buffer_size { @@ -421,26 +421,26 @@ struct tlv_buffer_size { }; union vfpf_tlvs { - struct vfpf_first_tlv first_tlv; - struct vfpf_acquire_tlv acquire; + struct vfpf_first_tlv first_tlv; + struct vfpf_acquire_tlv acquire; struct vfpf_init_tlv init; - struct vfpf_start_rxq_tlv start_rxq; - struct vfpf_start_txq_tlv start_txq; - struct vfpf_stop_rxqs_tlv stop_rxqs; - struct vfpf_stop_txqs_tlv stop_txqs; - struct vfpf_update_rxq_tlv update_rxq; - struct vfpf_vport_start_tlv start_vport; - struct vfpf_vport_update_tlv vport_update; - struct vfpf_ucast_filter_tlv ucast_filter; + struct vfpf_start_rxq_tlv start_rxq; + struct vfpf_start_txq_tlv start_txq; + struct vfpf_stop_rxqs_tlv stop_rxqs; + struct vfpf_stop_txqs_tlv stop_txqs; + struct vfpf_update_rxq_tlv update_rxq; + struct vfpf_vport_start_tlv start_vport; + struct vfpf_vport_update_tlv vport_update; + struct vfpf_ucast_filter_tlv ucast_filter; struct channel_list_end_tlv list_end; - struct tlv_buffer_size tlv_buf_size; + struct tlv_buffer_size tlv_buf_size; }; union pfvf_tlvs { - struct pfvf_def_resp_tlv default_resp; - struct pfvf_acquire_resp_tlv acquire_resp; + struct pfvf_def_resp_tlv default_resp; + struct pfvf_acquire_resp_tlv acquire_resp; struct channel_list_end_tlv list_end; - struct tlv_buffer_size tlv_buf_size; + struct tlv_buffer_size tlv_buf_size; }; /* This is a structure which is allocated in the VF, which the PF may update @@ -533,7 +533,7 @@ struct ecore_bulletin { enum { /*!!!!! Make sure to update STRINGS structure accordingly !!!!!*/ - CHANNEL_TLV_NONE, /* ends tlv sequence */ + CHANNEL_TLV_NONE, /* ends tlv sequence */ CHANNEL_TLV_ACQUIRE, CHANNEL_TLV_VPORT_START, CHANNEL_TLV_VPORT_UPDATE, diff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h index 046bbb2064..71ef615a84 100644 --- a/drivers/net/qede/base/eth_common.h +++ b/drivers/net/qede/base/eth_common.h @@ -12,43 +12,43 @@ /* ETH FW CONSTANTS */ /********************/ #define ETH_CACHE_LINE_SIZE 64 -#define ETH_RX_CQE_GAP 32 -#define ETH_MAX_RAMROD_PER_CON 8 -#define ETH_TX_BD_PAGE_SIZE_BYTES 4096 -#define ETH_RX_BD_PAGE_SIZE_BYTES 4096 -#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 -#define ETH_RX_NUM_NEXT_PAGE_BDS 2 - -#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 -#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 -#define ETH_TX_MAX_LSO_HDR_NBD 4 -#define ETH_TX_MIN_BDS_PER_LSO_PKT 3 -#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 -#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 -#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 +#define ETH_RX_CQE_GAP 32 +#define ETH_MAX_RAMROD_PER_CON 8 +#define ETH_TX_BD_PAGE_SIZE_BYTES 4096 +#define ETH_RX_BD_PAGE_SIZE_BYTES 4096 +#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 +#define ETH_RX_NUM_NEXT_PAGE_BDS 2 + +#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 +#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 +#define ETH_TX_MAX_LSO_HDR_NBD 4 +#define ETH_TX_MIN_BDS_PER_LSO_PKT 3 +#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 +#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 +#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8)) #define ETH_TX_MAX_LSO_HDR_BYTES 510 #define ETH_TX_LSO_WINDOW_BDS_NUM 18 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFFFF -#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS +#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS #define ETH_RX_MAX_BUFF_PER_PKT 5 /* num of MAC/VLAN filters */ -#define ETH_NUM_MAC_FILTERS 512 -#define ETH_NUM_VLAN_FILTERS 512 +#define ETH_NUM_MAC_FILTERS 512 +#define ETH_NUM_VLAN_FILTERS 512 /* approx. multicast constants */ -#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 -#define ETH_MULTICAST_MAC_BINS 256 -#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) +#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 +#define ETH_MULTICAST_MAC_BINS 256 +#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) /* ethernet vport update constants */ -#define ETH_FILTER_RULES_COUNT 10 -#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 -#define ETH_RSS_KEY_SIZE_REGS 10 +#define ETH_FILTER_RULES_COUNT 10 +#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 +#define ETH_RSS_KEY_SIZE_REGS 10 #define ETH_RSS_ENGINE_NUM_K2 207 #define ETH_RSS_ENGINE_NUM_BB 127 @@ -115,14 +115,14 @@ struct eth_tx_data_1st_bd { __le16 vlan /* VLAN to insert to packet (if needed). */; /* Number of BDs in packet. Should be at least 2 in non-LSO * packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet. - */ + */ u8 nbds; struct eth_tx_1st_bd_flags bd_flags; __le16 bitfields; #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0 -#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 -#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 +#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 +#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2 }; diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h index 71922654e2..6f4b4f80b8 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -26,7 +26,7 @@ #define MCP_GLOB_PORT_MAX 4 /* Global */ #define MCP_GLOB_FUNC_MAX 16 /* Global */ -typedef u32 offsize_t; /* In DWORDS !!! */ +typedef u32 offsize_t; /* In DWORDS !!! */ /* Offset from the beginning of the MCP scratchpad */ #define OFFSIZE_OFFSET_SHIFT 0 #define OFFSIZE_OFFSET_MASK 0x0000ffff @@ -35,18 +35,18 @@ typedef u32 offsize_t; /* In DWORDS !!! */ #define OFFSIZE_SIZE_MASK 0xffff0000 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ -#define SECTION_OFFSET(_offsize) \ -((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) +#define SECTION_OFFSET(_offsize) \ + ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) /* SECTION_SIZE is calculating the size in bytes out of offsize */ -#define SECTION_SIZE(_offsize) \ -(((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) +#define SECTION_SIZE(_offsize) \ + (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) -#define SECTION_ADDR(_offsize, idx) \ +#define SECTION_ADDR(_offsize, idx) \ (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ -(_pub_base + offsetof(struct mcp_public_data, sections[_section])) + (_pub_base + offsetof(struct mcp_public_data, sections[_section])) /* PHY configuration */ struct pmm_phy_cfg { @@ -54,13 +54,13 @@ struct pmm_phy_cfg { #define PMM_SPEED_AUTONEG 0 #define PMM_SPEED_SMARTLINQ 0x8 - u32 pause; /* bitmask */ + u32 pause; /* bitmask */ #define PMM_PAUSE_NONE 0x0 #define PMM_PAUSE_AUTONEG 0x1 #define PMM_PAUSE_RX 0x2 #define PMM_PAUSE_TX 0x4 - u32 adv_speed; /* Default should be the speed_cap_mask */ + u32 adv_speed; /* Default should be the speed_cap_mask */ u32 loopback_mode; #define PMM_LOOPBACK_NONE 0 #define PMM_LOOPBACK_INT_PHY 1 @@ -76,7 +76,7 @@ struct pmm_phy_cfg { }; struct port_mf_cfg { - u32 dynamic_cfg; /* device control channel */ + u32 dynamic_cfg; /* device control channel */ #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff #define PORT_MF_CFG_OV_TAG_SHIFT 0 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK @@ -88,51 +88,51 @@ struct port_mf_cfg { * MUST be synced with struct pmm_stats_map */ struct pmm_stats { - u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter */ - u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter */ - u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter */ - u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter */ - u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter */ + u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ + u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ + u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ + u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ + u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged */ - u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter */ - u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter */ - u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter */ + u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ + u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ + u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame ctr */ - u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter */ - u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter */ - u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter */ - u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter */ - u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter */ - u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ - u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter */ - u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ - u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ - u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ - u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ + u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ + u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ + u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ + u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ + u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ + u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ + u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ + u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ + u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ + u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ + u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ - u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter */ - u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter */ - u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter */ + u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ + u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ + u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame ctr */ - u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ - u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ + u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ + u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC */ u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ - u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ - u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ - u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ - u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ + u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ + u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ + u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ + u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ u64 rxpok; /* 0x22 (Offset 0x138) RX good frame */ - u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ - u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ - u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ - u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ - u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ + u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ + u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ + u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ + u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ + u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ }; struct brb_stats { @@ -151,18 +151,18 @@ struct port_stats { * | ports | | | | | *======+==================+=========+=========+========+====================== * BB | 1x100G | This is special mode, where there are 2 HW func - * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1 - * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 - * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 + * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 + * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 + * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 - * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 - * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA - * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA - * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA - * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA - * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA + * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 + * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA + * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA + * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA + * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA + * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA *======+==================+=========+=========+========+======================= */ @@ -216,13 +216,13 @@ struct lldp_config_params_s { u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; /* Holds local Port ID TLV header, subtype and 9B of payload. * If firtst byte is 0, then we will use default port ID - */ + */ u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; }; struct lldp_status_params_s { u32 prefix_seq_num; - u32 status; /* TBD */ + u32 status; /* TBD */ /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; @@ -245,11 +245,11 @@ struct dcbx_ets_feature { #define DCBX_ETS_CBS_SHIFT 3 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 #define DCBX_ETS_MAX_TCS_SHIFT 4 - u32 pri_tc_tbl[1]; + u32 pri_tc_tbl[1]; #define DCBX_CEE_STRICT_PRIORITY 0xf #define DCBX_CEE_STRICT_PRIORITY_TC 0x7 - u32 tc_bw_tbl[2]; - u32 tc_tsa_tbl[2]; + u32 tc_bw_tbl[2]; + u32 tc_tsa_tbl[2]; #define DCBX_ETS_TSA_STRICT 0 #define DCBX_ETS_TSA_CBS 1 #define DCBX_ETS_TSA_ETS 2 @@ -287,12 +287,12 @@ struct dcbx_app_priority_feature { /* Not in use * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8 - */ + */ #define DCBX_APP_MAX_TCS_MASK 0x0000f000 #define DCBX_APP_MAX_TCS_SHIFT 12 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 #define DCBX_APP_NUM_ENTRIES_SHIFT 16 - struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; + struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; }; /* FW structure in BE */ @@ -350,7 +350,7 @@ struct dcbx_mib { * #define DCBX_CONFIG_VERSION_DISABLED 0 * #define DCBX_CONFIG_VERSION_IEEE 1 * #define DCBX_CONFIG_VERSION_CEE 2 - */ + */ struct dcbx_features features; u32 suffix_seq_num; }; @@ -367,9 +367,9 @@ struct lldp_system_tlvs_buffer_s { /* */ /**************************************/ struct public_global { - u32 max_path; /* 32bit is wasty, but this will be used often */ + u32 max_path; /* 32bit is wasty, but this will be used often */ u32 max_ports; /* (Global) 32bit is wasty, this will be used often */ -#define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ +#define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ #define MODE_2P 2 #define MODE_3P 3 #define MODE_4P 4 @@ -406,7 +406,7 @@ struct public_global { struct fw_flr_mb { u32 aggint; u32 opgen_addr; - u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ + u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ #define ACCUM_ACK_PF_BASE 0 #define ACCUM_ACK_PF_SHIFT 0 @@ -424,10 +424,10 @@ struct public_path { * mcp_vf_disabled is set by the MCP to indicate the driver about VFs * which were disabled/flred */ - u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ + u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ u32 process_kill; - /* Reset on mcp reset, and incremented for eveny process kill event. */ +/* Reset on mcp reset, and incremented for eveny process kill event. */ #define PROCESS_KILL_COUNTER_MASK 0x0000ffff #define PROCESS_KILL_COUNTER_SHIFT 0 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 @@ -464,7 +464,7 @@ struct dci_fc_npiv_tbl { ****************************************************************************/ struct public_port { - u32 validity_map; /* 0x0 (4*2 = 0x8) */ + u32 validity_map; /* 0x0 (4*2 = 0x8) */ /* validity bits */ #define MCP_VALIDITY_PCI_CFG 0x00100000 @@ -485,7 +485,7 @@ struct public_port { #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 u32 link_status; -#define LINK_STATUS_LINK_UP 0x00000001 +#define LINK_STATUS_LINK_UP 0x00000001 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) @@ -501,7 +501,7 @@ struct public_port { #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 -#define LINK_STATUS_PFC_ENABLED 0x00000100 +#define LINK_STATUS_PFC_ENABLED 0x00000100 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 @@ -537,15 +537,15 @@ struct public_port { struct port_stats stats; u32 media_type; -#define MEDIA_UNSPECIFIED 0x0 +#define MEDIA_UNSPECIFIED 0x0 #define MEDIA_SFPP_10G_FIBER 0x1 #define MEDIA_XFP_FIBER 0x2 -#define MEDIA_DA_TWINAX 0x3 -#define MEDIA_BASE_T 0x4 +#define MEDIA_DA_TWINAX 0x3 +#define MEDIA_BASE_T 0x4 #define MEDIA_SFP_1G_FIBER 0x5 -#define MEDIA_MODULE_FIBER 0x6 -#define MEDIA_KR 0xf0 -#define MEDIA_NOT_PRESENT 0xff +#define MEDIA_MODULE_FIBER 0x6 +#define MEDIA_KR 0xf0 +#define MEDIA_NOT_PRESENT 0xff u32 lfa_status; #define LFA_LINK_FLAP_REASON_OFFSET 0 @@ -574,7 +574,7 @@ struct public_port { struct dcbx_mib remote_dcbx_mib; struct dcbx_mib operational_dcbx_mib; - /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ +/* FC_NPIV table offset & size in NVRAM value of 0 means not present */ u32 fc_npiv_nvram_tbl_addr; u32 fc_npiv_nvram_tbl_size; u32 transceiver_data; @@ -641,7 +641,7 @@ struct public_func { /* MTU size per funciton is needed for the OV feature */ u32 mtu_size; - /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ +/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ /* For PCP values 0-3 use the map lower */ /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 @@ -650,7 +650,7 @@ struct public_func { /* For PCP values 4-7 use the map upper */ /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 - */ + */ u32 c2s_pcp_map_upper; /* For PCP default value get the MSB byte of the map default */ @@ -683,7 +683,7 @@ struct public_func { u32 status; #define FUNC_STATUS_VLINK_DOWN 0x00000001 - u32 mac_upper; /* MAC */ + u32 mac_upper; /* MAC */ #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK @@ -692,14 +692,14 @@ struct public_func { u32 dpdk_rsvd2[4]; - u32 ovlan_stag; /* tags */ + u32 ovlan_stag; /* tags */ #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff #define FUNC_MF_CFG_OV_STAG_SHIFT 0 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK - u32 pf_allocation; /* vf per pf */ + u32 pf_allocation; /* vf per pf */ - u32 preserve_data; /* Will be used bt CCM */ + u32 preserve_data; /* Will be used bt CCM */ u32 driver_last_activity_ts; @@ -707,7 +707,7 @@ struct public_func { * drv_ack_vf_disabled is set by the PF driver to ack handled disabled * VFs */ - u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ + u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ u32 drv_id; #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff @@ -747,7 +747,7 @@ struct public_func { */ struct mcp_mac { - u32 mac_upper; /* Upper 16 bits are always zeroes */ + u32 mac_upper; /* Upper 16 bits are always zeroes */ u32 mac_lower; }; @@ -784,12 +784,12 @@ struct ocbb_data_stc { }; union drv_union_data { - u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */ - struct mcp_mac wol_mac; /* UNLOAD_DONE */ + u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */ + struct mcp_mac wol_mac; /* UNLOAD_DONE */ struct pmm_phy_cfg drv_phy_cfg; - struct mcp_val64 val64; /* For PHY / AVS commands */ + struct mcp_val64 val64; /* For PHY / AVS commands */ u8 raw_data[MCP_DRV_NVM_BUF_LEN]; @@ -822,7 +822,7 @@ struct public_drv_mb { /* Vitaly: LLDP commands */ #define DRV_MSG_CODE_SET_LLDP 0x24000000 #define DRV_MSG_CODE_SET_DCBX 0x25000000 - /* OneView feature driver HSI */ + /* OneView feature driver HSI*/ #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 @@ -893,7 +893,7 @@ struct public_drv_mb { #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 - /* LLDP / DCBX params */ + /* LLDP / DCBX params*/ #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 @@ -925,7 +925,7 @@ struct public_drv_mb { #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 - /* configure vf MSIX params */ + /* configure vf MSIX params*/ #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 @@ -943,16 +943,16 @@ struct public_drv_mb { #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 -#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 +#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF -#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) +#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 -#define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 +#define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 @@ -1063,7 +1063,7 @@ struct public_drv_mb { #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 -#define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 +#define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 #define FW_MSG_CODE_GPIO_OK 0x00160000 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 @@ -1152,7 +1152,7 @@ enum MFW_DRV_MSG_TYPE { ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) struct public_mfw_mb { - u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ + u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; }; @@ -1163,8 +1163,8 @@ struct public_mfw_mb { /* */ /**************************************/ enum public_sections { - PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ - PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ + PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ + PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ PUBLIC_GLOBAL, PUBLIC_PATH, PUBLIC_PORT, @@ -1202,4 +1202,4 @@ struct mcp_public_data { #define MAX_I2C_TRANSACTION_SIZE 16 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 -#endif /* MCP_PUBLIC_H */ +#endif /* MCP_PUBLIC_H */ diff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h index 7f1a60dd55..8d99880a4a 100644 --- a/drivers/net/qede/base/nvm_cfg.h +++ b/drivers/net/qede/base/nvm_cfg.h @@ -22,8 +22,8 @@ struct nvm_cfg_mac_address { u32 mac_addr_hi; -#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF -#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 + #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF + #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 u32 mac_addr_lo; }; @@ -31,107 +31,107 @@ struct nvm_cfg_mac_address { * nvm_cfg1 structs ******************************************/ struct nvm_cfg1_glob { - u32 generic_cont0; /* 0x0 */ -#define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F -#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 -#define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 -#define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 -#define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 -#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 -#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 -#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 -#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 -#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 -#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 -#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 -#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 -#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 -#define NVM_CFG1_GLOB_MF_MODE_BD 0x6 -#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 -#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 -#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 -#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 -#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 -#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 -#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 -#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 -#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 -#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 -#define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 -#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 -#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 -#define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 -#define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 -#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 -#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 -#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000 -#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31 -#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0 -#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1 - u32 engineering_change[3]; /* 0x4 */ - u32 manufacturing_id; /* 0x10 */ - u32 serial_number[4]; /* 0x14 */ - u32 pcie_cfg; /* 0x24 */ -#define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 -#define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 -#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 -#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 -#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 -#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 -#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 -#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 -#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 -#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 -#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 -#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 -#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 + u32 generic_cont0; /* 0x0 */ + #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F + #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 + #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 + #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 + #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 + #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 + #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 + #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 + #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 + #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 + #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 + #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 + #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 + #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 + #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 + #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 + #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 + #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 + #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 + #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 + #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 + #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 + #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 + #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 + #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 + #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 + #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 + #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 + #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 + #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 + #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 + #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 + #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000 + #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31 + #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0 + #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1 + u32 engineering_change[3]; /* 0x4 */ + u32 manufacturing_id; /* 0x10 */ + u32 serial_number[4]; /* 0x14 */ + u32 pcie_cfg; /* 0x24 */ + #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 + #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 + #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 + #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 + #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 + #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 + #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 + #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 + #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 + #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 + #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 + #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 + #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 -#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 -#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 -#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 -#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 -#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 -#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 -#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 -#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 -#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 -#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 -#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 -#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 -#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 -#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 -#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 + #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 + #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 + #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 + #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 + #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 + #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 + #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 + #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 + #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 + #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 + #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 + #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 + #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 + #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 + #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 /* Set the duration, in seconds, fan failure signal should be * sampled */ #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 -#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 - u32 mgmt_traffic; /* 0x28 */ -#define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 -#define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 -#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE -#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 -#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 -#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 -#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 -#define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 -#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 -#define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 -#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 -#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 -#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 -#define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 -#define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 -#define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 -#define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 + #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 + u32 mgmt_traffic; /* 0x28 */ + #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 + #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 + #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE + #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 + #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 + #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 + #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 + #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 + #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 + #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 + #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 + #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 + #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 + #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 + #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 + #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 + #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 /* Indicates whether external thermal sonsor is available */ -#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 -#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 -#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 -#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 - u32 core_cfg; /* 0x2C */ -#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF -#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 + #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 + #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 + #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 + #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 + u32 core_cfg; /* 0x2C */ + #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF + #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2 @@ -153,753 +153,753 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18 -#define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 -#define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 -#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 -#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 -#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 -#define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 -#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 -#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 -#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 -#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 - u32 e_lane_cfg1; /* 0x30 */ -#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F -#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 -#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 -#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 -#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 -#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 -#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 -#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 -#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 -#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 -#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 -#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 -#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 -#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 -#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 -#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 - u32 e_lane_cfg2; /* 0x34 */ -#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 -#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 -#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 -#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 -#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 -#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 -#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 -#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 -#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 -#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 -#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 -#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 -#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 -#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 -#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 -#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 -#define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 -#define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 -#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 -#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 -#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 -#define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 -#define NVM_CFG1_GLOB_NCSI_OFFSET 12 -#define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 -#define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 + #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 + #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 + #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 + #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 + #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 + #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 + #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 + #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 + #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 + #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 + u32 e_lane_cfg1; /* 0x30 */ + #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F + #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 + #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 + #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 + #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 + #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 + #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 + #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 + #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 + #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 + #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 + #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 + #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 + #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 + #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 + #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 + u32 e_lane_cfg2; /* 0x34 */ + #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 + #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 + #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 + #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 + #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 + #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 + #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 + #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 + #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 + #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 + #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 + #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 + #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 + #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 + #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 + #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 + #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 + #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 + #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 + #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 + #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 + #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 + #define NVM_CFG1_GLOB_NCSI_OFFSET 12 + #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 + #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 /* Maximum advertised pcie link width */ -#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 -#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 + #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 + #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_16_LANES 0x0 -#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 -#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 -#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 -#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 + #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 + #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 + #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 + #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 /* ASPM L1 mode */ -#define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 -#define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 -#define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 -#define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 -#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 -#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 -#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 -#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 -#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 -#define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 + #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 + #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 + #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 + #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 + #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 + #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 + #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 + #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 + #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 + #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 -#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 -#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 -#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 -#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 -#define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 + #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 + #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 + #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 + #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 + #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 /* Set the PLDM sensor modes */ -#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 -#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 -#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 -#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 -#define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 - u32 f_lane_cfg1; /* 0x38 */ -#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F -#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 -#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 -#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 -#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 -#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 -#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 -#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 -#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 -#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 -#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 -#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 -#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 -#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 -#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 -#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 - u32 f_lane_cfg2; /* 0x3C */ -#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 -#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 -#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 -#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 -#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 -#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 -#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 -#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 -#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 -#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 -#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 -#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 -#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 -#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 -#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 -#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 + #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 + #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 + #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 + #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 + #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 + u32 f_lane_cfg1; /* 0x38 */ + #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F + #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 + #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 + #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 + #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 + #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 + #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 + #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 + #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 + #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 + #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 + #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 + #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 + #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 + #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 + #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 + u32 f_lane_cfg2; /* 0x3C */ + #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 + #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 + #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 + #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 + #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 + #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 + #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 + #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 + #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 + #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 + #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 + #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 + #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 + #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 + #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 + #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 /* Control the period between two successive checks */ #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 + #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 /* Set shutdown temperature */ #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 + #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 /* Set max. count for over operational temperature */ -#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 -#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 + #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 + #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 u32 eagle_preemphasis; /* 0x40 */ -#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 + #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 u32 eagle_driver_current; /* 0x44 */ -#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 + #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 u32 falcon_preemphasis; /* 0x48 */ -#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 + #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 u32 falcon_driver_current; /* 0x4C */ -#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 - u32 pci_id; /* 0x50 */ -#define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF -#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 + #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 + u32 pci_id; /* 0x50 */ + #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF + #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 /* Set caution temperature */ #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16 + #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16 /* Set external thermal sensor I2C address */ #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 -#define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 - u32 pci_subsys_id; /* 0x54 */ -#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF -#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 -#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 -#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 - u32 bar; /* 0x58 */ -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE -#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE -#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF -#define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 -#define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 -#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 -#define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 -#define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 -#define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 -#define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 -#define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 -#define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 -#define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 -#define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 -#define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 -#define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA -#define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB -#define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC -#define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD -#define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE -#define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF + #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 + u32 pci_subsys_id; /* 0x54 */ + #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF + #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 + #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 + #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 + u32 bar; /* 0x58 */ + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE + #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE + #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF + #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 + #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 + #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 + #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 + #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 + #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 + #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 + #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 + #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 + #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 + #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 + #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 + #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA + #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB + #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC + #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD + #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE + #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF /* Set the duration, in seconds, fan failure signal should be * sampled */ -#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 -#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 + #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 + #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 u32 eagle_txfir_main; /* 0x5C */ -#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 + #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 u32 eagle_txfir_post; /* 0x60 */ -#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 + #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 u32 falcon_txfir_main; /* 0x64 */ -#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 + #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 u32 falcon_txfir_post; /* 0x68 */ -#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF -#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 -#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 -#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 -#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 -#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 - u32 manufacture_ver; /* 0x6C */ -#define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F -#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 -#define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 -#define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 -#define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 -#define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 -#define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 -#define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 -#define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 -#define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 - u32 manufacture_time; /* 0x70 */ -#define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F -#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 -#define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 -#define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 -#define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 -#define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 - u32 led_global_settings; /* 0x74 */ -#define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F -#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 -#define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 -#define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 -#define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 -#define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 -#define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 -#define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 - u32 generic_cont1; /* 0x78 */ -#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF -#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 - u32 mbi_version; /* 0x7C */ -#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF -#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 -#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 -#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 - u32 mbi_date; /* 0x80 */ - u32 misc_sig; /* 0x84 */ + #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF + #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 + #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 + #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 + #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 + #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 + u32 manufacture_ver; /* 0x6C */ + #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F + #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 + #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 + #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 + #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 + #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 + #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 + #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 + #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 + #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 + u32 manufacture_time; /* 0x70 */ + #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F + #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 + #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 + #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 + #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 + #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 + u32 led_global_settings; /* 0x74 */ + #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F + #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 + #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 + #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 + #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 + #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 + #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 + #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 + u32 generic_cont1; /* 0x78 */ + #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF + #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 + u32 mbi_version; /* 0x7C */ + #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF + #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 + #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 + #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 + u32 mbi_date; /* 0x80 */ + u32 misc_sig; /* 0x84 */ /* Define the GPIO mapping to switch i2c mux */ -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F -#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 - u32 device_capabilities; /* 0x88 */ -#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 - u32 power_dissipated; /* 0x8C */ -#define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF -#define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 -#define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 -#define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 -#define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 -#define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 - u32 power_consumed; /* 0x90 */ -#define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF -#define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 -#define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 -#define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 -#define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 -#define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 -#define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 -#define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 - u32 efi_version; /* 0x94 */ + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F + #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 + u32 device_capabilities; /* 0x88 */ + #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 + u32 power_dissipated; /* 0x8C */ + #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF + #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 + #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 + #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 + #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 + #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 + u32 power_consumed; /* 0x90 */ + #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF + #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 + #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 + #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 + #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 + #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 + u32 efi_version; /* 0x94 */ u32 reserved[42]; /* 0x98 */ }; struct nvm_cfg1_path { - u32 reserved[30]; /* 0x0 */ + u32 reserved[30]; /* 0x0 */ }; struct nvm_cfg1_port { - u32 reserved__m_relocated_to_option_123; /* 0x0 */ - u32 reserved__m_relocated_to_option_124; /* 0x4 */ - u32 generic_cont0; /* 0x8 */ -#define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF -#define NVM_CFG1_PORT_LED_MODE_OFFSET 0 -#define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 -#define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 -#define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 -#define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 -#define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 -#define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 -#define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 -#define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 -#define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 -#define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 -#define NVM_CFG1_PORT_LED_MODE_PHY8 0xA -#define NVM_CFG1_PORT_LED_MODE_PHY9 0xB -#define NVM_CFG1_PORT_LED_MODE_MAC4 0xC -#define NVM_CFG1_PORT_LED_MODE_PHY10 0xD -#define NVM_CFG1_PORT_LED_MODE_PHY11 0xE -#define NVM_CFG1_PORT_LED_MODE_PHY12 0xF -#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 -#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 -#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 -#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 -#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 -#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 -#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 -#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 -#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 - u32 pcie_cfg; /* 0xC */ -#define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 -#define NVM_CFG1_PORT_RESERVED15_OFFSET 0 - u32 features; /* 0x10 */ -#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 -#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 -#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 -#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 -#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 -#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 -#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 -#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 - u32 speed_cap_mask; /* 0x14 */ -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 -#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 + u32 reserved__m_relocated_to_option_123; /* 0x0 */ + u32 reserved__m_relocated_to_option_124; /* 0x4 */ + u32 generic_cont0; /* 0x8 */ + #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF + #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 + #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 + #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 + #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 + #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 + #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 + #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 + #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 + #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 + #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 + #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 + #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA + #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB + #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC + #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD + #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE + #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF + #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 + #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 + #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 + #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 + #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 + #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 + #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 + #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 + #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 + u32 pcie_cfg; /* 0xC */ + #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 + #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 + u32 features; /* 0x10 */ + #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 + #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 + #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 + #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 + #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 + #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 + #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 + #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 + u32 speed_cap_mask; /* 0x14 */ + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 -#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40 - u32 link_settings; /* 0x18 */ -#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F -#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 + u32 link_settings; /* 0x18 */ + #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F + #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7 -#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 -#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 -#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 -#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 -#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 -#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 + #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 + #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 + #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 + #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 + #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7 -#define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8 -#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 -#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 -#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 -#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 -#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8 + #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 + #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 + #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 + #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 + #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 -#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 + #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 -#define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 -#define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 -#define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 -#define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 -#define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 -#define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 + #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 + #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 + #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 + #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 + #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 + #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_NONE 0x0 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_FIRECODE 0x1 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_RS 0x2 - u32 phy_cfg; /* 0x1C */ -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 -#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 -#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 -#define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 -#define NVM_CFG1_PORT_AN_MODE_OFFSET 24 -#define NVM_CFG1_PORT_AN_MODE_NONE 0x0 -#define NVM_CFG1_PORT_AN_MODE_CL73 0x1 -#define NVM_CFG1_PORT_AN_MODE_CL37 0x2 -#define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 + u32 phy_cfg; /* 0x1C */ + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 + #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 + #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 + #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 + #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 + #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 + #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 + #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 + #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4 #define NVM_CFG1_PORT_AN_MODE_HPAM 0x5 #define NVM_CFG1_PORT_AN_MODE_SGMII 0x6 - u32 mgmt_traffic; /* 0x20 */ -#define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F -#define NVM_CFG1_PORT_RESERVED61_OFFSET 0 - u32 ext_phy; /* 0x24 */ -#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF -#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 -#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 -#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1 -#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 -#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 - u32 mba_cfg1; /* 0x28 */ -#define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 -#define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 -#define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 -#define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 -#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 -#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 -#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 -#define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 -#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 -#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 -#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 -#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 -#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 -#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 -#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 -#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 -#define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 -#define NVM_CFG1_PORT_RESERVED5_OFFSET 9 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 + u32 mgmt_traffic; /* 0x20 */ + #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F + #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 + u32 ext_phy; /* 0x24 */ + #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF + #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 + #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 + #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1 + #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 + #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 + u32 mba_cfg1; /* 0x28 */ + #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 + #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 + #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 + #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 + #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 + #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 + #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 + #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 + #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 + #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 + #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 + #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 + #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 + #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 + #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 + #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 + #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 + #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7 -#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 -#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 - u32 mba_cfg2; /* 0x2C */ -#define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF -#define NVM_CFG1_PORT_RESERVED65_OFFSET 0 -#define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 -#define NVM_CFG1_PORT_RESERVED66_OFFSET 16 - u32 vf_cfg; /* 0x30 */ -#define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF -#define NVM_CFG1_PORT_RESERVED8_OFFSET 0 -#define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 -#define NVM_CFG1_PORT_RESERVED6_OFFSET 16 - struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ - u32 led_port_settings; /* 0x3C */ -#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF -#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 -#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 -#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 -#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 -#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 -#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 -#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 -#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8 -#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10 -#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20 + #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 + u32 mba_cfg2; /* 0x2C */ + #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF + #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 + #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 + #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 + u32 vf_cfg; /* 0x30 */ + #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF + #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 + #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 + #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 + struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ + u32 led_port_settings; /* 0x3C */ + #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF + #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 + #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 + #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 + #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 + #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40 - u32 transceiver_00; /* 0x40 */ + u32 transceiver_00; /* 0x40 */ /* Define for mapping of transceiver signal module absent */ -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F -#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F + #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 /* Define the GPIO mux settings to switch i2c mux to this port */ -#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 -#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 -#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 -#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 - u32 device_ids; /* 0x44 */ -#define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF -#define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 -#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 -#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 - u32 board_cfg; /* 0x48 */ - /* This field defines the board technology + #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 + #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 + #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 + #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 + u32 device_ids; /* 0x44 */ + #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF + #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 + #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 + #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 + u32 board_cfg; /* 0x48 */ + /* This field defines the board technology * (backpane,transceiver,external PHY) */ -#define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF -#define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 -#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 -#define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 -#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 -#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 -#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 + #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF + #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 + #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 + #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 + #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 + #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 + #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 /* This field defines the GPIO mapped to tx_disable signal in SFP */ -#define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 -#define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 -#define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA -#define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB -#define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC -#define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD -#define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE -#define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF -#define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 -#define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A -#define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B -#define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C -#define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D -#define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E -#define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F -#define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 + #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 + #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 + #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA + #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB + #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC + #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD + #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE + #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF + #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 + #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A + #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B + #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C + #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D + #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E + #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F + #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 u32 reserved[131]; /* 0x4C */ }; struct nvm_cfg1_func { - struct nvm_cfg_mac_address mac_address; /* 0x0 */ - u32 rsrv1; /* 0x8 */ -#define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF -#define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 -#define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 -#define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 - u32 rsrv2; /* 0xC */ -#define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF -#define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 -#define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 -#define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 - u32 device_id; /* 0x10 */ -#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF -#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 -#define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 -#define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 - u32 cmn_cfg; /* 0x14 */ -#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 -#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 -#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 -#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 -#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 -#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 -#define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 -#define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 -#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 -#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 -#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 -#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 -#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 -#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 -#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 - u32 pci_cfg; /* 0x18 */ -#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F -#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 + struct nvm_cfg_mac_address mac_address; /* 0x0 */ + u32 rsrv1; /* 0x8 */ + #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF + #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 + #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 + #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 + u32 rsrv2; /* 0xC */ + #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF + #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 + #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 + #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 + u32 device_id; /* 0x10 */ + #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF + #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 + #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 + #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 + u32 cmn_cfg; /* 0x14 */ + #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 + #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 + #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 + #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 + #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 + #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 + #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 + #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 + #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 + #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 + #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 + #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 + #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 + #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 + #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 + u32 pci_cfg; /* 0x18 */ + #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F + #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 #define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7 -#define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 -#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 -#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 -#define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 -#define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 -#define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 -#define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 -#define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 -#define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 -#define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 -#define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 -#define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 -#define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA -#define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB -#define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC -#define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD -#define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE -#define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF -#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 -#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 - u32 preboot_generic_cfg; /* 0x2C */ -#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF -#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 -#define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 -#define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 - u32 reserved[8]; /* 0x30 */ + #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 + #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 + #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 + #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 + #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 + #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 + #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 + #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 + #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 + #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 + #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 + #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 + #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA + #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB + #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC + #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD + #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE + #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF + #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 + #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 + u32 preboot_generic_cfg; /* 0x2C */ + #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF + #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 + #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 + #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 + u32 reserved[8]; /* 0x30 */ }; struct nvm_cfg1 { - struct nvm_cfg1_glob glob; /* 0x0 */ - struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */ - struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ - struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ + struct nvm_cfg1_glob glob; /* 0x0 */ + struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */ + struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ + struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ }; /******************************************