From: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Date: Wed, 18 Jan 2017 17:31:00 +0000 (+0000)
Subject: doc: add ZUC to crypto matrices
X-Git-Tag: spdx-start~4693
X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=da696d56636526b65f3894f0cc7122ae190e3e5e;p=dpdk.git

doc: add ZUC to crypto matrices

When ZUC PMD was added, it was not added in the
Crypto Device Supported Functionality Matrices.
This commit adds a column in all the matrices, plus
the ZUC EEA3/EIA3 algorithms.

Fixes: cf7685d68f00 ("crypto/zuc: add driver for ZUC library")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
---

diff --git a/doc/guides/cryptodevs/overview.rst b/doc/guides/cryptodevs/overview.rst
index 8e03cddb96..bd5f0ad9f5 100644
--- a/doc/guides/cryptodevs/overview.rst
+++ b/doc/guides/cryptodevs/overview.rst
@@ -33,66 +33,68 @@ Crypto Device Supported Functionality Matrices
 Supported Feature Flags
 
 .. csv-table::
-   :header: "Feature Flags", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
+   :header: "Feature Flags", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
    :stub-columns: 1
 
-   "RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO",x,x,x,x,x,x
-   "RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO",,,,,,
-   "RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING",x,x,x,x,x,x
-   "RTE_CRYPTODEV_FF_CPU_SSE",,,x,,x,x
-   "RTE_CRYPTODEV_FF_CPU_AVX",,,x,,x,x
-   "RTE_CRYPTODEV_FF_CPU_AVX2",,,x,,,
-   "RTE_CRYPTODEV_FF_CPU_AVX512",,,x,,,
-   "RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,,
-   "RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,,
+   "RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO",x,x,x,x,x,x,x
+   "RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO",,,,,,,
+   "RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING",x,x,x,x,x,x,x
+   "RTE_CRYPTODEV_FF_CPU_SSE",,,x,,x,x,
+   "RTE_CRYPTODEV_FF_CPU_AVX",,,x,,x,x,
+   "RTE_CRYPTODEV_FF_CPU_AVX2",,,x,,,,
+   "RTE_CRYPTODEV_FF_CPU_AVX512",,,x,,,,
+   "RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,,,
+   "RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,,,
 
 Supported Cipher Algorithms
 
 .. csv-table::
-   :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
+   :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
    :stub-columns: 1
 
-   "NULL",,x,,,,
-   "AES_CBC_128",x,,x,,,
-   "AES_CBC_192",x,,x,,,
-   "AES_CBC_256",x,,x,,,
-   "AES_CTR_128",x,,x,,,
-   "AES_CTR_192",x,,x,,,
-   "AES_CTR_256",x,,x,,,
-   "DES_CBC",x,,,,,
-   "SNOW3G_UEA2",x,,,,x,
-   "KASUMI_F8",,,,,,x
+   "NULL",,x,,,,,
+   "AES_CBC_128",x,,x,,,,
+   "AES_CBC_192",x,,x,,,,
+   "AES_CBC_256",x,,x,,,,
+   "AES_CTR_128",x,,x,,,,
+   "AES_CTR_192",x,,x,,,,
+   "AES_CTR_256",x,,x,,,,
+   "DES_CBC",x,,,,,,
+   "SNOW3G_UEA2",x,,,,x,,
+   "KASUMI_F8",,,,,,x,
+   "ZUC_EEA3",,,,,,,x
 
 Supported Authentication Algorithms
 
 .. csv-table::
-   :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
+   :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
    :stub-columns: 1
 
-   "NONE",,x,,,,
-   "MD5",,,,,,
-   "MD5_HMAC",,,x,,,
-   "SHA1",,,,,,
-   "SHA1_HMAC",x,,x,,,
-   "SHA224",,,,,,
-   "SHA224_HMAC",,,x,,,
-   "SHA256",,,,,,
-   "SHA256_HMAC",x,,x,,,
-   "SHA384",,,,,,
-   "SHA384_HMAC",,,x,,,
-   "SHA512",,,,,,
-   "SHA512_HMAC",x,,x,,,
-   "AES_XCBC",x,,x,,,
-   "AES_GMAC",,,,x,,
-   "SNOW3G_UIA2",x,,,,x,
-   "KASUMI_F9",,,,,,x
+   "NONE",,x,,,,,
+   "MD5",,,,,,,
+   "MD5_HMAC",,,x,,,,
+   "SHA1",,,,,,,
+   "SHA1_HMAC",x,,x,,,,
+   "SHA224",,,,,,,
+   "SHA224_HMAC",,,x,,,,
+   "SHA256",,,,,,,
+   "SHA256_HMAC",x,,x,,,,
+   "SHA384",,,,,,,
+   "SHA384_HMAC",,,x,,,,
+   "SHA512",,,,,,,
+   "SHA512_HMAC",x,,x,,,,
+   "AES_XCBC",x,,x,,,,
+   "AES_GMAC",,,,x,,,
+   "SNOW3G_UIA2",x,,,,x,,
+   "KASUMI_F9",,,,,,x,
+   "ZUC_EIA3",,,,,,,x
 
 Supported AEAD Algorithms
 
 .. csv-table::
-   :header: "AEAD Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
+   :header: "AEAD Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
    :stub-columns: 1
 
-   "AES_GCM_128",x,,,x,,
-   "AES_GCM_192",x,,,,,
-   "AES_GCM_256",x,,,x,,
+   "AES_GCM_128",x,,,x,,,
+   "AES_GCM_192",x,,,,,,
+   "AES_GCM_256",x,,,x,,,