From: Nithin Dabilpuram Date: Wed, 23 Jun 2021 04:46:12 +0000 (+0530) Subject: net/cnxk: support device infos query X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=dac12650eb1a5f9cb89f0da8355c6ce002f1e88d;p=dpdk.git net/cnxk: support device infos query Add support to retrieve dev infos get for CN9K and CN10K. Signed-off-by: Nithin Dabilpuram --- diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index d316af3d5f..ce5732566b 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -16,6 +16,9 @@ Features Features of the CNXK Ethdev PMD are: +- SR-IOV VF +- Lock-free Tx queue + Prerequisites ------------- diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 2c23464a6b..b426340263 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -4,6 +4,10 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y +Lock-free Tx queue = Y +SR-IOV = Y +Multiprocess aware = Y Linux = Y ARMv8 = Y Usage doc = Y diff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini index de78516e3a..292ac1e584 100644 --- a/doc/guides/nics/features/cnxk_vec.ini +++ b/doc/guides/nics/features/cnxk_vec.ini @@ -4,6 +4,10 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y +Lock-free Tx queue = Y +SR-IOV = Y +Multiprocess aware = Y Linux = Y ARMv8 = Y Usage doc = Y diff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini index 9c96351a3d..bc2eb8ad4c 100644 --- a/doc/guides/nics/features/cnxk_vf.ini +++ b/doc/guides/nics/features/cnxk_vf.ini @@ -4,6 +4,9 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y +Lock-free Tx queue = Y +Multiprocess aware = Y Linux = Y ARMv8 = Y Usage doc = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 109fd35338..066e01ca89 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -38,7 +38,9 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev) } /* CNXK platform independent eth dev ops */ -struct eth_dev_ops cnxk_eth_dev_ops; +struct eth_dev_ops cnxk_eth_dev_ops = { + .dev_infos_get = cnxk_nix_info_get, +}; static int cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 97e3a15f3c..8d9a7e0169 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -15,9 +15,40 @@ #define CNXK_ETH_DEV_PMD_VERSION "1.0" +/* VLAN tag inserted by NIX_TX_VTAG_ACTION. + * In Tx space is always reserved for this in FRS. + */ +#define CNXK_NIX_MAX_VTAG_INS 2 +#define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS) + +/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */ +#define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8) + +#define CNXK_NIX_RX_MIN_DESC 16 +#define CNXK_NIX_RX_MIN_DESC_ALIGN 16 +#define CNXK_NIX_RX_NB_SEG_MAX 6 +#define CNXK_NIX_RX_DEFAULT_RING_SZ 4096 /* Max supported SQB count */ #define CNXK_NIX_TX_MAX_SQB 512 +/* If PTP is enabled additional SEND MEM DESC is required which + * takes 2 words, hence max 7 iova address are possible + */ +#if defined(RTE_LIBRTE_IEEE1588) +#define CNXK_NIX_TX_NB_SEG_MAX 7 +#else +#define CNXK_NIX_TX_NB_SEG_MAX 9 +#endif + +#define CNXK_NIX_RSS_L3_L4_SRC_DST \ + (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \ + ETH_RSS_L4_DST_ONLY) + +#define CNXK_NIX_RSS_OFFLOAD \ + (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ + ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \ + CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN) + #define CNXK_NIX_TX_OFFLOAD_CAPA \ (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \ DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \ @@ -77,6 +108,8 @@ extern struct eth_dev_ops cnxk_eth_dev_ops; int cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev); int cnxk_nix_remove(struct rte_pci_device *pci_dev); +int cnxk_nix_info_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *dev_info); /* Devargs */ int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c new file mode 100644 index 0000000000..4a45956541 --- /dev/null +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include + +int +cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + int max_rx_pktlen; + + max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN - + CNXK_NIX_MAX_VTAG_ACT_SIZE); + + devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN; + devinfo->max_rx_pktlen = max_rx_pktlen; + devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT; + devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT; + devinfo->max_mac_addrs = dev->max_mac_entries; + devinfo->max_vfs = pci_dev->max_vfs; + devinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD; + devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD; + + devinfo->rx_offload_capa = dev->rx_offload_capa; + devinfo->tx_offload_capa = dev->tx_offload_capa; + devinfo->rx_queue_offload_capa = 0; + devinfo->tx_queue_offload_capa = 0; + + devinfo->reta_size = dev->nix.reta_sz; + devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN; + devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD; + + devinfo->default_rxconf = (struct rte_eth_rxconf){ + .rx_drop_en = 0, + .offloads = 0, + }; + + devinfo->default_txconf = (struct rte_eth_txconf){ + .offloads = 0, + }; + + devinfo->default_rxportconf = (struct rte_eth_dev_portconf){ + .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ, + }; + + devinfo->rx_desc_lim = (struct rte_eth_desc_lim){ + .nb_max = UINT16_MAX, + .nb_min = CNXK_NIX_RX_MIN_DESC, + .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN, + .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX, + .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX, + }; + devinfo->rx_desc_lim.nb_max = + RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max, + CNXK_NIX_RX_MIN_DESC_ALIGN); + + devinfo->tx_desc_lim = (struct rte_eth_desc_lim){ + .nb_max = UINT16_MAX, + .nb_min = 1, + .nb_align = 1, + .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX, + .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX, + }; + + devinfo->speed_capa = dev->speed_capa; + devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | + RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + return 0; +} diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build index ff05389ee3..7df228eb31 100644 --- a/drivers/net/cnxk/meson.build +++ b/drivers/net/cnxk/meson.build @@ -11,6 +11,7 @@ endif sources = files( 'cnxk_ethdev.c', 'cnxk_ethdev_devargs.c', + 'cnxk_ethdev_ops.c', ) # CN9K