From: Hemant Agrawal Date: Fri, 8 Dec 2017 05:21:18 +0000 (+0530) Subject: bus/fslmc: expose platform SoC value register X-Git-Tag: spdx-start~589 X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=e0ded73b5b78d5767d12f06e714e4dfa864b2f35;p=dpdk.git bus/fslmc: expose platform SoC value register This patch expose the dpaa2 soc platform family type. This is required to make some soc variant specific decision during configuration and runtime. Signed-off-by: Hemant Agrawal --- diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 3c20422801..6e349a7159 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -50,6 +50,9 @@ static struct dpio_dev_list dpio_dev_list = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */ static uint32_t io_space_count; +/* Variable to store DPAA2 platform type */ +uint32_t dpaa2_svr_family; + /*Stashing Macros default for LS208x*/ static int dpaa2_core_cluster_base = 0x04; static int dpaa2_cluster_sz = 2; @@ -239,26 +242,6 @@ static int dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id) { int sdest, ret; - static int first_time; - - /* find the SoC type for the first time */ - if (!first_time) { - struct mc_soc_version mc_plat_info = {0}; - - if (mc_get_soc_version(dpio_dev->dpio, - CMD_PRI_LOW, &mc_plat_info)) { - PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n"); - } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) { - dpaa2_core_cluster_base = 0x02; - dpaa2_cluster_sz = 4; - PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected"); - } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) { - dpaa2_core_cluster_base = 0x00; - dpaa2_cluster_sz = 2; - PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected"); - } - first_time = 1; - } /* Set the Stashing Destination */ if (cpu_id < 0) { @@ -473,6 +456,25 @@ dpaa2_create_dpio_device(int vdev_fd, rte_free(dpio_dev); } + /* find the SoC type for the first time */ + if (!dpaa2_svr_family) { + struct mc_soc_version mc_plat_info = {0}; + + if (mc_get_soc_version(dpio_dev->dpio, + CMD_PRI_LOW, &mc_plat_info)) { + PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n"); + } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) { + dpaa2_core_cluster_base = 0x02; + dpaa2_cluster_sz = 4; + PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected"); + } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) { + dpaa2_core_cluster_base = 0x00; + dpaa2_cluster_sz = 2; + PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected"); + } + dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000); + } + TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next); RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpio.%d]\n", object_id); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h index b6f3638255..c0bd878243 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -28,6 +28,9 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); #define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev #define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal +/* Variable to store DPAA2 platform type */ +extern uint32_t dpaa2_svr_family; + extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id); diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index a1e30d63d2..f266d6d0e6 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -93,6 +93,7 @@ DPDK_17.11 { DPDK_18.02 { global: + dpaa2_svr_family; dpaa2_virt_mode; } DPDK_17.11; diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index a982242aad..24cd5ce7bf 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -392,7 +392,6 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, { struct dpaa2_dev_priv *priv = dev->data->dev_private; struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; - struct mc_soc_version mc_plat_info = {0}; struct dpaa2_queue *dpaa2_q; struct dpni_queue cfg; uint8_t options = 0; @@ -424,18 +423,20 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, /*if ls2088 or rev2 device, enable the stashing */ - if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) - PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n"); - - if ((mc_plat_info.svr & 0xffff0000) != SVR_LS2080A) { + if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { options |= DPNI_QUEUE_OPT_FLC; cfg.flc.stash_control = true; cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; /* 00 00 00 - last 6 bit represent annotation, context stashing, - * data stashing setting 01 01 00 (0x14) to enable - * 1 line data, 1 line annotation + * data stashing setting 01 01 00 (0x14) + * (in following order ->DS AS CS) + * to enable 1 line data, 1 line annotation. + * For LX2, this setting should be 01 00 00 (0x10) */ - cfg.flc.value |= 0x14; + if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) + cfg.flc.value |= 0x10; + else + cfg.flc.value |= 0x14; } ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, dpaa2_q->tc_index, flow_id, options, &cfg);