From: Igor Romanov Date: Thu, 7 Feb 2019 16:29:24 +0000 (+0000) Subject: net/sfc/base: support different Rx descriptor sizes X-Git-Url: http://git.droids-corp.org/?a=commitdiff_plain;h=eebbd4250d1f6a958820b83d179aa0f23eab273f;p=dpdk.git net/sfc/base: support different Rx descriptor sizes For consistency with the size of Tx descriptors, the size of Rx descriptors should be a part of NIC config, not a macro that is common for all NIC families. Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko --- diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h index 0116bc91ca..11c61d9e61 100644 --- a/drivers/net/sfc/base/ef10_impl.h +++ b/drivers/net/sfc/base/ef10_impl.h @@ -19,6 +19,7 @@ extern "C" { #define EF10_TXQ_MINNDESCS 512 +#define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t)) #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t)) /* Maximum independent of EFX_BUG35388_WORKAROUND. */ diff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c index f2b72571af..23b80d78f5 100644 --- a/drivers/net/sfc/base/ef10_rx.c +++ b/drivers/net/sfc/base/ef10_rx.c @@ -31,7 +31,7 @@ efx_mcdi_init_rxq( efx_mcdi_req_t req; EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN, MC_CMD_INIT_RXQ_V3_OUT_LEN); - int npages = EFX_RXQ_NBUFS(ndescs); + int npages = efx_rxq_nbufs(enp, ndescs); int i; efx_qword_t *dma_addr; uint64_t addr; @@ -41,7 +41,8 @@ efx_mcdi_init_rxq( EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs); - if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) { + if ((esmp == NULL) || + (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) { rc = EINVAL; goto fail1; } diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 506bdb5e1e..101bb4cd21 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1284,6 +1284,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_evq_timer_quantum_ns; uint32_t enc_evq_timer_max_us; uint32_t enc_clk_mult; + uint32_t enc_rx_desc_size; uint32_t enc_tx_desc_size; uint32_t enc_rx_prefix_size; uint32_t enc_rx_buf_align_start; @@ -2478,8 +2479,28 @@ efx_pseudo_hdr_pkt_length_get( #define EFX_RXQ_MAXNDESCS 4096 #define EFX_RXQ_MINNDESCS 512 +/* + * This macro is deprecated and will be removed. + * Use the function efx_rxq_size() instead. + */ #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) + +/* + * This macro is deprecated and will be removed. + * Use the function efx_rxq_nbufs() instead. + */ #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) + +extern __checkReturn size_t +efx_rxq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs); + +extern __checkReturn unsigned int +efx_rxq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs); + #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) typedef enum efx_rxq_type_e { diff --git a/drivers/net/sfc/base/efx_rx.c b/drivers/net/sfc/base/efx_rx.c index 8910cd5f7e..c0d7381287 100644 --- a/drivers/net/sfc/base/efx_rx.c +++ b/drivers/net/sfc/base/efx_rx.c @@ -766,6 +766,24 @@ fail1: return (rc); } + __checkReturn size_t +efx_rxq_size( + __in const efx_nic_t *enp, + __in unsigned int ndescs) +{ + const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); + + return (ndescs * encp->enc_rx_desc_size); +} + + __checkReturn unsigned int +efx_rxq_nbufs( + __in const efx_nic_t *enp, + __in unsigned int ndescs) +{ + return (efx_rxq_size(enp, ndescs) / EFX_BUF_SIZE); +} + void efx_rx_qenable( __in efx_rxq_t *erp) diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index b4fc3cc9ef..2fb54d85a1 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -186,6 +186,7 @@ hunt_board_cfg( /* Checksums for TSO sends can be incorrect on Huntington. */ encp->enc_bug61297_workaround = B_TRUE; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c index 9cfc5077c9..7d0c800476 100644 --- a/drivers/net/sfc/base/medford2_nic.c +++ b/drivers/net/sfc/base/medford2_nic.c @@ -101,6 +101,7 @@ medford2_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index 3f2c5b877c..fd711a96f7 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -99,6 +99,7 @@ medford_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE; encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE; /* Alignment for receive packet DMA buffers */ diff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h index 6f07b1ec7c..0689600257 100644 --- a/drivers/net/sfc/base/siena_impl.h +++ b/drivers/net/sfc/base/siena_impl.h @@ -34,6 +34,7 @@ extern "C" { #define SIENA_RXQ_MAXNDESCS 4096 #define SIENA_RXQ_MINNDESCS 512 +#define SIENA_RXQ_DESC_SIZE (sizeof (efx_qword_t)) #define SIENA_TXQ_DESC_SIZE (sizeof (efx_qword_t)) #define SIENA_NVRAM_CHUNK 0x80 diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index 987a32d2f1..894cf81443 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -104,6 +104,7 @@ siena_board_cfg( encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; + encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE; encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE; /* When hash header insertion is enabled, Siena inserts 16 bytes */