From 0aeb133c585fd6809cf7acb6a5dc4c54392ac575 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Mon, 30 May 2022 17:30:13 +0800 Subject: [PATCH] net/ngbe: fix PCIe related operations with bus API When using mailbox to request firmware to enable or disable PCIe bus master, there is a small probability that mailbox cannot respond. Change to use rte_pci_read_config() and rte_pci_write_config(), to avoid this problem. Fixes: ac6c5e9af56a ("net/ngbe: fix Tx hang on queue disable") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_hw.c | 25 +++++++++++++++++++------ drivers/net/ngbe/base/ngbe_osdep.h | 4 ++++ drivers/net/ngbe/ngbe_ethdev.c | 1 + 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index 050649e0a6..facc1d9e82 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -1058,17 +1058,30 @@ out: **/ s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable) { + struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back; s32 status = 0; - u16 addr = 0x04; - u32 data, i; + s32 ret = 0; + u32 i; + u16 reg; + + ret = rte_pci_read_config(pci_dev, ®, + sizeof(reg), PCI_COMMAND); + if (ret != sizeof(reg)) { + DEBUGOUT("Cannot read command from PCI config space!\n"); + return -1; + } - ngbe_hic_pcie_read(hw, addr, &data, 4); if (enable) - data |= 0x04; + reg |= PCI_COMMAND_MASTER; else - data &= ~0x04; + reg &= ~PCI_COMMAND_MASTER; - ngbe_hic_pcie_write(hw, addr, &data, 4); + ret = rte_pci_write_config(pci_dev, ®, + sizeof(reg), PCI_COMMAND); + if (ret != sizeof(reg)) { + DEBUGOUT("Cannot write command to PCI config space!\n"); + return -1; + } if (enable) goto out; diff --git a/drivers/net/ngbe/base/ngbe_osdep.h b/drivers/net/ngbe/base/ngbe_osdep.h index b62d793191..bf1fa30312 100644 --- a/drivers/net/ngbe/base/ngbe_osdep.h +++ b/drivers/net/ngbe/base/ngbe_osdep.h @@ -19,6 +19,7 @@ #include #include #include +#include #include "../ngbe_logs.h" @@ -180,4 +181,7 @@ static inline u64 REVERT_BIT_MASK64(u64 mask) #define ETH_P_8021Q 0x8100 #define ETH_P_8021AD 0x88A8 +#define PCI_COMMAND 0x04 +#define PCI_COMMAND_MASTER 0x4 + #endif /* _NGBE_OS_H_ */ diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 9df9f824a1..5ac1c27a58 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -356,6 +356,7 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; /* Vendor and Device ID need to be set before init of shared code */ + hw->back = pci_dev; hw->device_id = pci_dev->id.device_id; hw->vendor_id = pci_dev->id.vendor_id; hw->sub_system_id = pci_dev->id.subsystem_device_id; -- 2.39.5