From 0bca1d26780e2cdbe03a2cf007839cbba8c830c8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?N=C3=A9lio=20Laranjeiro?= Date: Thu, 11 Jan 2018 10:15:59 +0100 Subject: [PATCH] examples/ipsec-secgw: fix SPI byte order in flow item SPI field is defined in the RFC2406 [1] as a big endian field it should be provided in its final form to the drivers through RTE flow. [1] https://tools.ietf.org/html/rfc2406 Fixes: ec17993a145a ("examples/ipsec-secgw: support security offload") Cc: stable@dpdk.org Signed-off-by: Nelio Laranjeiro Acked-by: Akhil Goyal --- examples/ipsec-secgw/ipsec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/ipsec-secgw/ipsec.c b/examples/ipsec-secgw/ipsec.c index 4ef446dde3..a478b6ec6b 100644 --- a/examples/ipsec-secgw/ipsec.c +++ b/examples/ipsec-secgw/ipsec.c @@ -166,7 +166,7 @@ create_session(struct ipsec_ctx *ipsec_ctx, struct ipsec_sa *sa) sa->pattern[2].type = RTE_FLOW_ITEM_TYPE_ESP; sa->pattern[2].spec = &sa->esp_spec; sa->pattern[2].mask = &rte_flow_item_esp_mask; - sa->esp_spec.hdr.spi = sa->spi; + sa->esp_spec.hdr.spi = rte_cpu_to_be_32(sa->spi); sa->pattern[3].type = RTE_FLOW_ITEM_TYPE_END; -- 2.20.1