From 1fc24374a7e860b0a15d94ab7a8dc55ae4849ba2 Mon Sep 17 00:00:00 2001 From: Rasesh Mody Date: Sun, 8 Apr 2018 21:48:01 -0700 Subject: [PATCH] net/qede/base: semantic changes The changes included in this patch are for - formatting - comment rework/additions - relocate FW info, version related code - convert: __le16 to u16 __le32 to u32 etc. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/ecore_hsi_common.h | 89 ++++++++++++--- drivers/net/qede/base/ecore_hsi_debug_tools.h | 105 +++++++++-------- drivers/net/qede/base/ecore_hsi_eth.h | 6 +- drivers/net/qede/base/ecore_hsi_init_func.h | 33 +++--- drivers/net/qede/base/ecore_hsi_init_tool.h | 107 +++++------------- 5 files changed, 171 insertions(+), 169 deletions(-) diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h index 38ac5075aa..60951a15f9 100644 --- a/drivers/net/qede/base/ecore_hsi_common.h +++ b/drivers/net/qede/base/ecore_hsi_common.h @@ -948,7 +948,9 @@ struct core_tx_bd_data { /* Do not allow additional VLAN manipulations on this packet (DCB) */ #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 -/* Insert VLAN into packet */ +/* Insert VLAN into packet. Cannot be set for LB packets + * (tx_dst == CORE_TX_DEST_LB) + */ #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 /* This is the first BD of the packet (for debug) */ @@ -1071,11 +1073,11 @@ struct core_tx_update_ramrod_data { * Enum flag for what type of dcb data to update */ enum dcb_dscp_update_mode { -/* use when no change should be done to dcb data */ +/* use when no change should be done to DCB data */ DONT_UPDATE_DCB_DSCP, - UPDATE_DCB /* use to update only l2 (vlan) priority */, - UPDATE_DSCP /* use to update only l3 dscp */, - UPDATE_DCB_DSCP /* update vlan pri and dscp */, + UPDATE_DCB /* use to update only L2 (vlan) priority */, + UPDATE_DSCP /* use to update only IP DSCP */, + UPDATE_DCB_DSCP /* update vlan pri and DSCP */, MAX_DCB_DSCP_UPDATE_FLAG }; @@ -1293,10 +1295,12 @@ enum fw_flow_ctrl_mode { * GFT profile type. */ enum gft_profile_type { - GFT_PROFILE_TYPE_4_TUPLE /* 4 tuple, IP type and L4 type match. */, -/* L4 destination port, IP type and L4 type match. */ +/* tunnel type, inner 4 tuple, IP type and L4 type match. */ + GFT_PROFILE_TYPE_4_TUPLE, +/* tunnel type, inner L4 destination port, IP type and L4 type match. */ GFT_PROFILE_TYPE_L4_DST_PORT, - GFT_PROFILE_TYPE_IP_DST_ADDR /* IP destination port and IP type. */, +/* tunnel type, inner IP destination address and IP type match. */ + GFT_PROFILE_TYPE_IP_DST_ADDR, /* tunnel type, inner IP source address and IP type match. */ GFT_PROFILE_TYPE_IP_SRC_ADDR, GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */, @@ -1416,8 +1420,9 @@ struct vlan_header { * outer tag configurations */ struct outer_tag_config_struct { -/* Enables the STAG Priority Change , Should be 1 for Bette Davis and UFP with - * Host Control mode. Else - 0 +/* Enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette + * Davis, UFP with Host Control mode, and UFP with DCB over base interface. + * else - 0. */ u8 enable_stag_pri_change; /* If inner_to_outer_pri_map is initialize then set pri_map_valid */ @@ -1512,14 +1517,14 @@ struct pf_start_ramrod_data { /* - * Data for port update ramrod + * Per protocol DCB data */ struct protocol_dcb_data { - u8 dcb_enable_flag /* dcbEnable flag value */; - u8 dscp_enable_flag /* If set use dscp value */; - u8 dcb_priority /* dcbPri flag value */; - u8 dcb_tc /* dcb TC value */; - u8 dscp_val /* dscp value to write if dscp_enable_flag is set */; + u8 dcb_enable_flag /* Enable DCB */; + u8 dscp_enable_flag /* Enable updating DSCP value */; + u8 dcb_priority /* DCB priority */; + u8 dcb_tc /* DCB TC */; + u8 dscp_val /* DSCP value to write if dscp_enable_flag is set */; /* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged * frames */ @@ -1583,8 +1588,9 @@ struct pf_update_ramrod_data { /* core iwarp related fields */ struct protocol_dcb_data iwarp_dcb_data; __le16 mf_vlan /* new outer vlan id value */; -/* enables the inner to outer TAG priority mapping. Should be 1 for Bette Davis - * and UFP with Host Control mode, else - 0. +/* enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette + * Davis, UFP with Host Control mode, and UFP with DCB over base interface. + * else - 0 */ u8 enable_stag_pri_change; u8 reserved; @@ -2139,6 +2145,53 @@ struct e4_ystorm_core_conn_ag_ctx { }; +struct fw_asserts_ram_section { +/* The offset of the section in the RAM in RAM lines (64-bit units) */ + __le16 section_ram_line_offset; +/* The size of the section in RAM lines (64-bit units) */ + __le16 section_ram_line_size; +/* The offset of the asserts list within the section in dwords */ + u8 list_dword_offset; +/* The size of an assert list element in dwords */ + u8 list_element_dword_size; + u8 list_num_elements /* The number of elements in the asserts list */; +/* The offset of the next list index field within the section in dwords */ + u8 list_next_index_dword_offset; +}; + + +struct fw_ver_num { + u8 major /* Firmware major version number */; + u8 minor /* Firmware minor version number */; + u8 rev /* Firmware revision version number */; + u8 eng /* Firmware engineering version number (for bootleg versions) */; +}; + +struct fw_ver_info { + __le16 tools_ver /* Tools version number */; + u8 image_id /* FW image ID (e.g. main, l2b, kuku) */; + u8 reserved1; + struct fw_ver_num num /* FW version number */; + __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; + __le32 reserved2; +}; + +struct fw_info { + struct fw_ver_info ver /* FW version information */; +/* Info regarding the FW asserts section in the Storm RAM */ + struct fw_asserts_ram_section fw_asserts_section; +}; + + +struct fw_info_location { + __le32 grc_addr /* GRC address where the fw_info struct is located. */; +/* Size of the fw_info structure (thats located at the grc_addr). */ + __le32 size; +}; + + + + /* * IGU cleanup command */ diff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h index 8a1445102b..74b756c0b8 100644 --- a/drivers/net/qede/base/ecore_hsi_debug_tools.h +++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h @@ -225,7 +225,7 @@ enum bin_dbg_buffer_type { * Attention bit mapping */ struct dbg_attn_bit_mapping { - __le16 data; + u16 data; /* The index of an attention in the blocks attentions list * (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits * (if is_unused_bit_cnt=1) @@ -247,14 +247,14 @@ struct dbg_attn_block_type_data { /* Offset of this block attention names in the debug attention name offsets * array */ - __le16 names_offset; - __le16 reserved1; + u16 names_offset; + u16 reserved1; u8 num_regs /* Number of attention registers in this block */; u8 reserved2; /* Offset of this blocks attention registers in the attention registers array * (in dbg_attn_reg units) */ - __le16 regs_offset; + u16 regs_offset; }; /* @@ -272,20 +272,20 @@ struct dbg_attn_block { * Attention register result */ struct dbg_attn_reg_result { - __le32 data; + u32 data; /* STS attention register GRC address (in dwords) */ #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 /* Number of attention indexes in this register */ #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 -/* The offset of this registers attentions within the blocks attentions - * list (a value in the range 0..number of block attentions-1) +/* The offset of this registers attentions within the blocks attentions list + * (a value in the range 0..number of block attentions-1) */ - __le16 attn_idx_offset; - __le16 reserved; - __le32 sts_val /* Value read from the STS attention register */; - __le32 mask_val /* Value read from the MASK attention register */; + u16 block_attn_offset; + u16 reserved; + u32 sts_val /* Value read from the STS attention register */; + u32 mask_val /* Value read from the MASK attention register */; }; /* @@ -303,7 +303,7 @@ struct dbg_attn_block_result { /* Offset of this registers block attention names in the attention name offsets * array */ - __le16 names_offset; + u16 names_offset; /* result data for each register in the block in which at least one attention * bit is set */ @@ -316,7 +316,7 @@ struct dbg_attn_block_result { * mode header */ struct dbg_mode_hdr { - __le16 data; + u16 data; /* indicates if a mode expression should be evaluated (0/1) */ #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 @@ -331,12 +331,11 @@ struct dbg_mode_hdr { * Attention register */ struct dbg_attn_reg { - struct dbg_mode_hdr mode /* Mode header */; -/* The offset of this registers attentions within the blocks attentions - * list (a value in the range 0..number of block attentions-1) +/* The offset of this registers attentions within the blocks attentions list + * (a value in the range 0..number of block attentions-1) */ - __le16 attn_idx_offset; - __le32 data; + u16 block_attn_offset; + u32 data; /* STS attention register GRC address (in dwords) */ #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 @@ -344,9 +343,8 @@ struct dbg_attn_reg { #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 /* STS_CLR attention register GRC address (in dwords) */ - __le32 sts_clr_address; -/* MASK attention register GRC address (in dwords) */ - __le32 mask_address; + u32 sts_clr_address; + u32 mask_address /* MASK attention register GRC address (in dwords) */; }; @@ -370,7 +368,7 @@ struct dbg_bus_block { /* Indicates if this block has a latency events debug line (0/1). */ u8 has_latency_events; /* Offset of this blocks lines in the Debug Bus lines array. */ - __le16 lines_offset; + u16 lines_offset; }; @@ -383,7 +381,7 @@ struct dbg_bus_block_user_data { /* Indicates if this block has a latency events debug line (0/1). */ u8 has_latency_events; /* Offset of this blocks lines in the debug bus line name offsets array. */ - __le16 names_offset; + u16 names_offset; }; @@ -422,13 +420,13 @@ struct dbg_dump_cond_hdr { * memory data for registers dump */ struct dbg_dump_mem { - __le32 dword0; + u32 dword0; /* register address (in dwords) */ #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 - __le32 dword1; + u32 dword1; /* register size (in dwords) */ #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF #define DBG_DUMP_MEM_LENGTH_SHIFT 0 @@ -444,7 +442,7 @@ struct dbg_dump_mem { * register data for registers dump */ struct dbg_dump_reg { - __le32 data; + u32 data; /* register address (in dwords) */ #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ #define DBG_DUMP_REG_ADDRESS_SHIFT 0 @@ -460,7 +458,7 @@ struct dbg_dump_reg { * split header for registers dump */ struct dbg_dump_split_hdr { - __le32 hdr; + u32 hdr; /* size in dwords of the data following this header */ #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 @@ -474,8 +472,7 @@ struct dbg_dump_split_hdr { */ struct dbg_idle_chk_cond_hdr { struct dbg_mode_hdr mode /* Mode header */; -/* size in dwords of the data following this header */ - __le16 data_size; + u16 data_size /* size in dwords of the data following this header */; }; @@ -483,7 +480,7 @@ struct dbg_idle_chk_cond_hdr { * Idle Check condition register */ struct dbg_idle_chk_cond_reg { - __le32 data; + u32 data; /* Register GRC address (in dwords) */ #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 @@ -493,7 +490,7 @@ struct dbg_idle_chk_cond_reg { /* value from block_id enum */ #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 - __le16 num_entries /* number of registers entries to check */; + u16 num_entries /* number of registers entries to check */; u8 entry_size /* size of registers entry (in dwords) */; u8 start_entry /* index of the first entry to check */; }; @@ -503,7 +500,7 @@ struct dbg_idle_chk_cond_reg { * Idle Check info register */ struct dbg_idle_chk_info_reg { - __le32 data; + u32 data; /* Register GRC address (in dwords) */ #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 @@ -513,7 +510,7 @@ struct dbg_idle_chk_info_reg { /* value from block_id enum */ #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 - __le16 size /* register size in dwords */; + u16 size /* register size in dwords */; struct dbg_mode_hdr mode /* Mode header */; }; @@ -531,8 +528,8 @@ union dbg_idle_chk_reg { * Idle Check result header */ struct dbg_idle_chk_result_hdr { - __le16 rule_id /* Failing rule index */; - __le16 mem_entry_id /* Failing memory entry index */; + u16 rule_id /* Failing rule index */; + u16 mem_entry_id /* Failing memory entry index */; u8 num_dumped_cond_regs /* number of dumped condition registers */; u8 num_dumped_info_regs /* number of dumped condition registers */; u8 severity /* from dbg_idle_chk_severity_types enum */; @@ -552,7 +549,7 @@ struct dbg_idle_chk_result_reg_hdr { #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 u8 start_entry /* index of the first checked entry */; - __le16 size /* register size in dwords */; + u16 size /* register size in dwords */; }; @@ -560,7 +557,7 @@ struct dbg_idle_chk_result_reg_hdr { * Idle Check rule */ struct dbg_idle_chk_rule { - __le16 rule_id /* Idle Check rule ID */; + u16 rule_id /* Idle Check rule ID */; u8 severity /* value from dbg_idle_chk_severity_types enum */; u8 cond_id /* Condition ID */; u8 num_cond_regs /* number of condition registers */; @@ -570,11 +567,11 @@ struct dbg_idle_chk_rule { /* offset of this rules registers in the idle check register array * (in dbg_idle_chk_reg units) */ - __le16 reg_offset; + u16 reg_offset; /* offset of this rules immediate values in the immediate values array * (in dwords) */ - __le16 imm_offset; + u16 imm_offset; }; @@ -582,7 +579,7 @@ struct dbg_idle_chk_rule { * Idle Check rule parsing data */ struct dbg_idle_chk_rule_parsing_data { - __le32 data; + u32 data; /* indicates if this register has a FW message */ #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 @@ -693,8 +690,8 @@ struct dbg_bus_trigger_state_data { * Debug Bus memory address */ struct dbg_bus_mem_addr { - __le32 lo; - __le32 hi; + u32 lo; + u32 hi; }; /* @@ -703,7 +700,7 @@ struct dbg_bus_mem_addr { struct dbg_bus_pci_buf_data { struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; - __le32 size /* PCI buffer size in bytes */; + u32 size /* PCI buffer size in bytes */; }; /* @@ -747,21 +744,20 @@ struct dbg_bus_storm_data { u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; /* EID filter params to filter on. Valid only if eid_filter_en is set. */ union dbg_bus_storm_eid_params eid_filter_params; -/* CID to filter on. Valid only if cid_filter_en is set. */ - __le32 cid; + u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; }; /* * Debug Bus data */ struct dbg_bus_data { - __le32 app_version /* The tools version number of the application */; + u32 app_version /* The tools version number of the application */; u8 state /* The current debug bus state */; u8 hw_dwords /* HW dwords per cycle */; /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the * HW ID of dword/qword i */ - __le16 hw_id_mask; + u16 hw_id_mask; u8 num_enabled_blocks /* Number of blocks enabled for recording */; u8 num_enabled_storms /* Number of Storms enabled for recording */; u8 target /* Output target */; @@ -783,7 +779,7 @@ struct dbg_bus_data { * Valid only if both filter and trigger are enabled (0/1) */ u8 filter_post_trigger; - __le16 reserved; + u16 reserved; /* Indicates if the recording trigger is enabled (0/1) */ u8 trigger_en; /* trigger states data */ @@ -933,9 +929,10 @@ struct dbg_grc_data { /* Indicates if the GRC parameters were initialized */ u8 params_initialized; u8 reserved1; - __le16 reserved2; -/* Value of each GRC parameter. Array size must match enum dbg_grc_params. */ - __le32 param_val[48]; + u16 reserved2; +/* Value of each GRC parameter. Array size must match the enum dbg_grc_params. + */ + u32 param_val[48]; }; @@ -1088,11 +1085,11 @@ enum dbg_storms { * Idle Check data */ struct idle_chk_data { - __le32 buf_size /* Idle check buffer size in dwords */; + u32 buf_size /* Idle check buffer size in dwords */; /* Indicates if the idle check buffer size was set (0/1) */ u8 buf_size_set; u8 reserved1; - __le16 reserved2; + u16 reserved2; }; /* @@ -1110,7 +1107,7 @@ struct dbg_tools_data { u8 initialized /* Indicates if the data was initialized */; u8 use_dmae /* Indicates if DMAE should be used */; /* Numbers of registers that were read since last log */ - __le32 num_regs_read; + u32 num_regs_read; }; diff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h index 5d5a521348..3a1116901f 100644 --- a/drivers/net/qede/base/ecore_hsi_eth.h +++ b/drivers/net/qede/base/ecore_hsi_eth.h @@ -1045,11 +1045,11 @@ struct eth_vport_tpa_param { u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; -/* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment - * allowed +/* If set, start each TPA segment on new BD (GRO mode). One BD per segment + * allowed. */ u8 tpa_pkt_split_flg; -/* If set, put header of first TPA segment on bd and data on SGE */ +/* If set, put header of first TPA segment on first BD and data on second BD. */ u8 tpa_hdr_data_split_flg; /* If set, GRO data consistent will checked for TPA continue */ u8 tpa_gro_consistent_flg; diff --git a/drivers/net/qede/base/ecore_hsi_init_func.h b/drivers/net/qede/base/ecore_hsi_init_func.h index 8421d16870..f0f4bd617e 100644 --- a/drivers/net/qede/base/ecore_hsi_init_func.h +++ b/drivers/net/qede/base/ecore_hsi_init_func.h @@ -24,10 +24,10 @@ * BRB RAM init requirements */ struct init_brb_ram_req { - __le32 guranteed_per_tc /* guaranteed size per TC, in bytes */; - __le32 headroom_per_tc /* headroom size per TC, in bytes */; - __le32 min_pkt_size /* min packet size, in bytes */; - __le32 max_ports_per_engine /* min packet size, in bytes */; + u32 guranteed_per_tc /* guaranteed size per TC, in bytes */; + u32 headroom_per_tc /* headroom size per TC, in bytes */; + u32 min_pkt_size /* min packet size, in bytes */; + u32 max_ports_per_engine /* min packet size, in bytes */; u8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */; }; @@ -44,15 +44,14 @@ struct init_ets_tc_req { * (indicated by the weight field) */ u8 use_wfq; -/* An arbitration weight. Valid only if use_wfq is set. */ - __le16 weight; + u16 weight /* An arbitration weight. Valid only if use_wfq is set. */; }; /* * ETS init requirements */ struct init_ets_req { - __le32 mtu /* Max packet size (in bytes) */; + u32 mtu /* Max packet size (in bytes) */; /* ETS initialization requirements per TC. */ struct init_ets_tc_req tc_req[NUM_OF_TCS]; }; @@ -64,12 +63,12 @@ struct init_ets_req { */ struct init_nig_lb_rl_req { /* Global MAC+LB RL rate (in Mbps). If set to 0, the RL will be disabled. */ - __le16 lb_mac_rate; + u16 lb_mac_rate; /* Global LB RL rate (in Mbps). If set to 0, the RL will be disabled. */ - __le16 lb_rate; - __le32 mtu /* Max packet size (in bytes) */; + u16 lb_rate; + u32 mtu /* Max packet size (in bytes) */; /* RL rate per physical TC (in Mbps). If set to 0, the RL will be disabled. */ - __le16 tc_rate[NUM_OF_PHYS_TCS]; + u16 tc_rate[NUM_OF_PHYS_TCS]; }; @@ -98,10 +97,10 @@ struct init_qm_port_params { /* Vector of valid bits for active TCs used by this port */ u8 active_phys_tcs; /* number of PBF command lines that can be used by this port */ - __le16 num_pbf_cmd_lines; + u16 num_pbf_cmd_lines; /* number of BTB blocks that can be used by this port */ - __le16 num_btb_blocks; - __le16 reserved; + u16 num_btb_blocks; + u16 reserved; }; @@ -127,13 +126,13 @@ struct init_qm_vport_params { /* rate limit in Mb/sec units. a value of 0 means dont configure. ignored if * VPORT RL is globally disabled. */ - __le32 vport_rl; + u32 vport_rl; /* WFQ weight. A value of 0 means dont configure. ignored if VPORT WFQ is * globally disabled. */ - __le16 vport_wfq; + u16 vport_wfq; /* the first Tx PQ ID associated with this VPORT for each TC. */ - __le16 first_tx_pq_id[NUM_OF_TCS]; + u16 first_tx_pq_id[NUM_OF_TCS]; }; #endif /* __ECORE_HSI_INIT_FUNC__ */ diff --git a/drivers/net/qede/base/ecore_hsi_init_tool.h b/drivers/net/qede/base/ecore_hsi_init_tool.h index 1f57e9b21b..e0d3b2337d 100644 --- a/drivers/net/qede/base/ecore_hsi_init_tool.h +++ b/drivers/net/qede/base/ecore_hsi_init_tool.h @@ -30,59 +30,13 @@ enum chip_ids { }; -struct fw_asserts_ram_section { -/* The offset of the section in the RAM in RAM lines (64-bit units) */ - __le16 section_ram_line_offset; -/* The size of the section in RAM lines (64-bit units) */ - __le16 section_ram_line_size; -/* The offset of the asserts list within the section in dwords */ - u8 list_dword_offset; -/* The size of an assert list element in dwords */ - u8 list_element_dword_size; - u8 list_num_elements /* The number of elements in the asserts list */; -/* The offset of the next list index field within the section in dwords */ - u8 list_next_index_dword_offset; -}; - - -struct fw_ver_num { - u8 major /* Firmware major version number */; - u8 minor /* Firmware minor version number */; - u8 rev /* Firmware revision version number */; -/* Firmware engineering version number (for bootleg versions) */ - u8 eng; -}; - -struct fw_ver_info { - __le16 tools_ver /* Tools version number */; - u8 image_id /* FW image ID (e.g. main, l2b, kuku) */; - u8 reserved1; - struct fw_ver_num num /* FW version number */; - __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; - __le32 reserved2; -}; - -struct fw_info { - struct fw_ver_info ver /* FW version information */; -/* Info regarding the FW asserts section in the Storm RAM */ - struct fw_asserts_ram_section fw_asserts_section; -}; - - -struct fw_info_location { -/* GRC address where the fw_info struct is located. */ - __le32 grc_addr; -/* Size of the fw_info structure (thats located at the grc_addr). */ - __le32 size; -}; - /* * Binary buffer header */ struct bin_buffer_hdr { /* buffer offset in bytes from the beginning of the binary file */ - __le32 offset; - __le32 length /* buffer length in bytes */; + u32 offset; + u32 length /* buffer length in bytes */; }; @@ -103,7 +57,7 @@ enum bin_init_buffer_type { * init array header: raw */ struct init_array_raw_hdr { - __le32 data; + u32 data; /* Init array type, from init_array_types enum */ #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 @@ -116,7 +70,7 @@ struct init_array_raw_hdr { * init array header: standard */ struct init_array_standard_hdr { - __le32 data; + u32 data; /* Init array type, from init_array_types enum */ #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 @@ -129,7 +83,7 @@ struct init_array_standard_hdr { * init array header: zipped */ struct init_array_zipped_hdr { - __le32 data; + u32 data; /* Init array type, from init_array_types enum */ #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 @@ -142,7 +96,7 @@ struct init_array_zipped_hdr { * init array header: pattern */ struct init_array_pattern_hdr { - __le32 data; + u32 data; /* Init array type, from init_array_types enum */ #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 @@ -223,14 +177,14 @@ enum init_array_types { * init operation: callback */ struct init_callback_op { - __le32 op_data; + u32 op_data; /* Init operation, from init_op_types enum */ #define INIT_CALLBACK_OP_OP_MASK 0xF #define INIT_CALLBACK_OP_OP_SHIFT 0 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 - __le16 callback_id /* Callback ID */; - __le16 block_id /* Blocks ID */; + u16 callback_id /* Callback ID */; + u16 block_id /* Blocks ID */; }; @@ -238,7 +192,7 @@ struct init_callback_op { * init operation: delay */ struct init_delay_op { - __le32 op_data; + u32 op_data; /* Init operation, from init_op_types enum */ #define INIT_DELAY_OP_OP_MASK 0xF #define INIT_DELAY_OP_OP_SHIFT 0 @@ -252,7 +206,7 @@ struct init_delay_op { * init operation: if_mode */ struct init_if_mode_op { - __le32 op_data; + u32 op_data; /* Init operation, from init_op_types enum */ #define INIT_IF_MODE_OP_OP_MASK 0xF #define INIT_IF_MODE_OP_OP_SHIFT 0 @@ -261,9 +215,8 @@ struct init_if_mode_op { /* Commands to skip if the modes dont match */ #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 - __le16 reserved2; -/* offset (in bytes) in modes expression buffer */ - __le16 modes_buf_offset; + u16 reserved2; + u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; }; @@ -271,7 +224,7 @@ struct init_if_mode_op { * init operation: if_phase */ struct init_if_phase_op { - __le32 op_data; + u32 op_data; /* Init operation, from init_op_types enum */ #define INIT_IF_PHASE_OP_OP_MASK 0xF #define INIT_IF_PHASE_OP_OP_SHIFT 0 @@ -283,7 +236,7 @@ struct init_if_phase_op { /* Commands to skip if the phases dont match */ #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 - __le32 phase_data; + u32 phase_data; #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF @@ -308,21 +261,21 @@ enum init_mode_ops { * init operation: raw */ struct init_raw_op { - __le32 op_data; + u32 op_data; /* Init operation, from init_op_types enum */ #define INIT_RAW_OP_OP_MASK 0xF #define INIT_RAW_OP_OP_SHIFT 0 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ #define INIT_RAW_OP_PARAM1_SHIFT 4 - __le32 param2 /* Init param 2 */; + u32 param2 /* Init param 2 */; }; /* * init array params */ struct init_op_array_params { - __le16 size /* array size in dwords */; - __le16 offset /* array start offset in dwords */; + u16 size /* array size in dwords */; + u16 offset /* array start offset in dwords */; }; /* @@ -330,11 +283,11 @@ struct init_op_array_params { */ union init_write_args { /* value to write, used when init source is INIT_SRC_INLINE */ - __le32 inline_val; + u32 inline_val; /* number of zeros to write, used when init source is INIT_SRC_ZEROS */ - __le32 zeros_count; + u32 zeros_count; /* array offset to write, used when init source is INIT_SRC_ARRAY */ - __le32 array_offset; + u32 array_offset; /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */ struct init_op_array_params runtime; }; @@ -343,7 +296,7 @@ union init_write_args { * init operation: write */ struct init_write_op { - __le32 data; + u32 data; /* init operation, from init_op_types enum */ #define INIT_WRITE_OP_OP_MASK 0xF #define INIT_WRITE_OP_OP_SHIFT 0 @@ -365,7 +318,7 @@ struct init_write_op { * init operation: read */ struct init_read_op { - __le32 op_data; + u32 op_data; /* init operation, from init_op_types enum */ #define INIT_READ_OP_OP_MASK 0xF #define INIT_READ_OP_OP_SHIFT 0 @@ -378,7 +331,7 @@ struct init_read_op { #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF #define INIT_READ_OP_ADDRESS_SHIFT 9 /* expected polling value, used only when polling is done */ - __le32 expected_val; + u32 expected_val; }; /* @@ -444,11 +397,11 @@ enum init_source_types { * Internal RAM Offsets macro data */ struct iro { - __le32 base /* RAM field offset */; - __le16 m1 /* multiplier 1 */; - __le16 m2 /* multiplier 2 */; - __le16 m3 /* multiplier 3 */; - __le16 size /* RAM field size */; + u32 base /* RAM field offset */; + u16 m1 /* multiplier 1 */; + u16 m2 /* multiplier 2 */; + u16 m3 /* multiplier 3 */; + u16 size /* RAM field size */; }; #endif /* __ECORE_HSI_INIT_TOOL__ */ -- 2.20.1