From 22edb82ac7338b5294c324862c8f213a4643617d Mon Sep 17 00:00:00 2001 From: Kishore Padmanabha Date: Mon, 6 Jul 2020 13:54:44 +0530 Subject: [PATCH] net/bnxt: support VLAN header bitmap Add support for the vlan headers in the matching of the flow patterns. Signed-off-by: Kishore Padmanabha Signed-off-by: Somnath Kotur Signed-off-by: Venkat Duvvuru Reviewed-by: Mike Baucom Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 20 ++--- .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 84 ++++++++++--------- 2 files changed, 53 insertions(+), 51 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 1bf0b76d8d..a4dbd84316 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -442,43 +442,43 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, /* Update the hdr_bitmap of the vlans */ hdr_bit = ¶ms->hdr_bitmap; if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && + !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && !outer_vtag_num) { /* Update the vlan tag num */ outer_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM, outer_vtag_num); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_PRESENT, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_OO_VLAN); } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && + !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && outer_vtag_num == 1) { /* update the vlan tag num */ outer_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM, outer_vtag_num); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_TWO_VTAGS, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_OI_VLAN); } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && !inner_vtag_num) { /* update the vlan tag num */ inner_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM, inner_vtag_num); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_PRESENT, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_IO_VLAN); } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && - ULP_COMP_FLD_IDX_RD(params, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT) && inner_vtag_num == 1) { /* update the vlan tag num */ inner_vtag_num++; ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM, inner_vtag_num); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_TWO_VTAGS, 1); + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_II_VLAN); } else { BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n"); return BNXT_TF_RC_ERROR; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 695546437d..e13d20b4bb 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -61,18 +61,22 @@ enum bnxt_ulp_action_bit { enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001, - BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002, - BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004, - BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008, - BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010, - BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020, - BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040, - BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080, - BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100, - BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200, - BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400, - BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000 + BNXT_ULP_HDR_BIT_OO_VLAN = 0x0000000000000002, + BNXT_ULP_HDR_BIT_OI_VLAN = 0x0000000000000004, + BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000008, + BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000010, + BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000020, + BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000040, + BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000080, + BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000100, + BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000200, + BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000000400, + BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000000800, + BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000001000, + BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000002000, + BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000004000, + BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000008000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000010000 }; enum bnxt_ulp_act_type { @@ -92,35 +96,33 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_NOT_USED = 0, BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1, BNXT_ULP_CF_IDX_O_VTAG_NUM = 2, - BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 3, - BNXT_ULP_CF_IDX_O_TWO_VTAGS = 4, - BNXT_ULP_CF_IDX_I_VTAG_NUM = 5, - BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 6, - BNXT_ULP_CF_IDX_I_TWO_VTAGS = 7, - BNXT_ULP_CF_IDX_INCOMING_IF = 8, - BNXT_ULP_CF_IDX_DIRECTION = 9, - BNXT_ULP_CF_IDX_SVIF_FLAG = 10, - BNXT_ULP_CF_IDX_O_L3 = 11, - BNXT_ULP_CF_IDX_I_L3 = 12, - BNXT_ULP_CF_IDX_O_L4 = 13, - BNXT_ULP_CF_IDX_I_L4 = 14, - BNXT_ULP_CF_IDX_DEV_PORT_ID = 15, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 16, - BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 17, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 18, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 19, - BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 20, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 21, - BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 22, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 23, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 24, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 25, - BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 26, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 27, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 28, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 29, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 30, - BNXT_ULP_CF_IDX_LAST = 31 + BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3, + BNXT_ULP_CF_IDX_I_VTAG_NUM = 4, + BNXT_ULP_CF_IDX_I_TWO_VTAGS = 5, + BNXT_ULP_CF_IDX_INCOMING_IF = 6, + BNXT_ULP_CF_IDX_DIRECTION = 7, + BNXT_ULP_CF_IDX_SVIF_FLAG = 8, + BNXT_ULP_CF_IDX_O_L3 = 9, + BNXT_ULP_CF_IDX_I_L3 = 10, + BNXT_ULP_CF_IDX_O_L4 = 11, + BNXT_ULP_CF_IDX_I_L4 = 12, + BNXT_ULP_CF_IDX_DEV_PORT_ID = 13, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 14, + BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 15, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 16, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 17, + BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 18, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 19, + BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 20, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 21, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 22, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 23, + BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 24, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 25, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 26, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 27, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 28, + BNXT_ULP_CF_IDX_LAST = 29 }; enum bnxt_ulp_cond_opcode { -- 2.20.1