From 2c5e0dd21f3aa7e352f8842b46f807f65ffda37f Mon Sep 17 00:00:00 2001
From: Ciara Power <ciara.power@intel.com>
Date: Mon, 19 Oct 2020 15:48:51 +0200
Subject: [PATCH] net/mlx5: check max SIMD bitwidth

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_rxtx_vec.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c
index 711dcd35fa..f083038682 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec.c
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c
@@ -10,6 +10,7 @@
 #include <rte_mbuf.h>
 #include <rte_mempool.h>
 #include <rte_prefetch.h>
+#include <rte_vect.h>
 
 #include <mlx5_glue.h>
 #include <mlx5_prm.h>
@@ -148,6 +149,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev)
 	struct mlx5_priv *priv = dev->data->dev_private;
 	uint32_t i;
 
+	if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
+		return -ENOTSUP;
 	if (!priv->config.rx_vec_en)
 		return -ENOTSUP;
 	if (mlx5_mprq_enabled(dev))
-- 
2.20.1