From 2dcb5f798729589f4d9e33ede598f70ac59281f5 Mon Sep 17 00:00:00 2001 From: Konstantin Ananyev Date: Fri, 27 Sep 2019 14:50:52 +0100 Subject: [PATCH] eal: move cache line and IOVA related definitions Right now RTE_CACHE_ and IOVA definitions are located inside rte_memory.h That might cause an unwanted inclusions of arch/os specific header files. See [1] for particular problem example. Probably the simplest way to deal with such problems - move these definitions into rte_commmon.h Note that this move doesn't introduce any change in functionality. [1] https://bugs.dpdk.org/show_bug.cgi?id=321 Suggested-by: Vipin Varghese Signed-off-by: Konstantin Ananyev Acked-by: Michel Machado --- lib/librte_eal/common/include/rte_common.h | 45 ++++++++++++++++++++++ lib/librte_eal/common/include/rte_memory.h | 38 ------------------ 2 files changed, 45 insertions(+), 38 deletions(-) diff --git a/lib/librte_eal/common/include/rte_common.h b/lib/librte_eal/common/include/rte_common.h index 05a3a64016..7ee94d6988 100644 --- a/lib/librte_eal/common/include/rte_common.h +++ b/lib/librte_eal/common/include/rte_common.h @@ -291,6 +291,51 @@ rte_is_aligned(void *ptr, unsigned align) */ #define RTE_BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) +/*********** Cache line related macros ********/ + +/** Cache line mask. */ +#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) + +/** Return the first cache-aligned value greater or equal to size. */ +#define RTE_CACHE_LINE_ROUNDUP(size) \ + (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / \ + RTE_CACHE_LINE_SIZE)) + +/** Cache line size in terms of log2 */ +#if RTE_CACHE_LINE_SIZE == 64 +#define RTE_CACHE_LINE_SIZE_LOG2 6 +#elif RTE_CACHE_LINE_SIZE == 128 +#define RTE_CACHE_LINE_SIZE_LOG2 7 +#else +#error "Unsupported cache line size" +#endif + +/** Minimum Cache line size. */ +#define RTE_CACHE_LINE_MIN_SIZE 64 + +/** Force alignment to cache line. */ +#define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) + +/** Force minimum cache line alignment. */ +#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) + +/*********** PA/IOVA type definitions ********/ + +/** Physical address */ +typedef uint64_t phys_addr_t; +#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) + +/** + * IO virtual address type. + * When the physical addressing mode (IOVA as PA) is in use, + * the translation from an IO virtual address (IOVA) to a physical address + * is a direct mapping, i.e. the same value. + * Otherwise, in virtual mode (IOVA as VA), an IOMMU may do the translation. + */ +typedef uint64_t rte_iova_t; +#define RTE_BAD_IOVA ((rte_iova_t)-1) + + /** * Combines 32b inputs most significant set bits into the least * significant bits to construct a value with the same MSBs as x diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h index 4717dcb439..38e00e382c 100644 --- a/lib/librte_eal/common/include/rte_memory.h +++ b/lib/librte_eal/common/include/rte_memory.h @@ -39,44 +39,6 @@ enum rte_page_sizes { }; #define SOCKET_ID_ANY -1 /**< Any NUMA socket. */ -#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */ - -#define RTE_CACHE_LINE_ROUNDUP(size) \ - (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) -/**< Return the first cache-aligned value greater or equal to size. */ - -/**< Cache line size in terms of log2 */ -#if RTE_CACHE_LINE_SIZE == 64 -#define RTE_CACHE_LINE_SIZE_LOG2 6 -#elif RTE_CACHE_LINE_SIZE == 128 -#define RTE_CACHE_LINE_SIZE_LOG2 7 -#else -#error "Unsupported cache line size" -#endif - -#define RTE_CACHE_LINE_MIN_SIZE 64 /**< Minimum Cache line size. */ - -/** - * Force alignment to cache line. - */ -#define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) - -/** - * Force minimum cache line alignment. - */ -#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) - -typedef uint64_t phys_addr_t; /**< Physical address. */ -#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) -/** - * IO virtual address type. - * When the physical addressing mode (IOVA as PA) is in use, - * the translation from an IO virtual address (IOVA) to a physical address - * is a direct mapping, i.e. the same value. - * Otherwise, in virtual mode (IOVA as VA), an IOMMU may do the translation. - */ -typedef uint64_t rte_iova_t; -#define RTE_BAD_IOVA ((rte_iova_t)-1) /** * Physical memory segment descriptor. -- 2.20.1