From 31f83163cf2f9ac4d8c1884bb7d1fc8e15b1f540 Mon Sep 17 00:00:00 2001 From: Harry van Haaren Date: Thu, 15 Oct 2020 11:32:37 +0100 Subject: [PATCH] eal: add new prefetch write variants This commit adds new rte_prefetchX_write() variants, that suggest to the compiler to use a prefetch instruction with intention to write. As a compiler builtin, the compiler can choose based on compilation target what the best implementation for this instruction is. Three versions are provided, targeting the different levels of cache. Signed-off-by: Harry van Haaren Reviewed-by: Jerin Jacob Reviewed-by: Ruifeng Wang --- app/test/test_prefetch.c | 4 ++ doc/guides/rel_notes/release_20_11.rst | 6 ++ lib/librte_eal/include/generic/rte_prefetch.h | 65 +++++++++++++++++++ 3 files changed, 75 insertions(+) diff --git a/app/test/test_prefetch.c b/app/test/test_prefetch.c index 41f219af78..32e08f8afe 100644 --- a/app/test/test_prefetch.c +++ b/app/test/test_prefetch.c @@ -26,6 +26,10 @@ test_prefetch(void) rte_prefetch1(&a); rte_prefetch2(&a); + rte_prefetch0_write(&a); + rte_prefetch1_write(&a); + rte_prefetch2_write(&a); + return 0; } diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index c61d7fcf67..1f01775595 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -62,6 +62,12 @@ New Features The functions are provided as a generic stubs and x86 specific implementation. +* **Added prefetch with intention to write APIs.** + + Added new prefetch function variants e.g. ``rte_prefetch0_write``, + which allow the programmer to prefetch a cache line and also indicate + the intention to write. + * **Updated CRC modules of the net library.** * Added runtime selection of the optimal architecture-specific CRC path. diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h index 6e47bdfbad..df9764e0bc 100644 --- a/lib/librte_eal/include/generic/rte_prefetch.h +++ b/lib/librte_eal/include/generic/rte_prefetch.h @@ -5,6 +5,8 @@ #ifndef _RTE_PREFETCH_H_ #define _RTE_PREFETCH_H_ +#include + /** * @file * @@ -51,4 +53,67 @@ static inline void rte_prefetch2(const volatile void *p); */ static inline void rte_prefetch_non_temporal(const volatile void *p); +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Prefetch a cache line into all cache levels, with intention to write. This + * prefetch variant hints to the CPU that the program is expecting to write to + * the cache line being prefetched. + * + * @param p Address to prefetch + */ +__rte_experimental +static inline void +rte_prefetch0_write(const void *p) +{ + /* 1 indicates intention to write, 3 sets target cache level to L1. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 3); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Prefetch a cache line into all cache levels, except the 0th, with intention + * to write. This prefetch variant hints to the CPU that the program is + * expecting to write to the cache line being prefetched. + * + * @param p Address to prefetch + */ +__rte_experimental +static inline void +rte_prefetch1_write(const void *p) +{ + /* 1 indicates intention to write, 2 sets target cache level to L2. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 2); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Prefetch a cache line into all cache levels, except the 0th and 1st, with + * intention to write. This prefetch variant hints to the CPU that the program + * is expecting to write to the cache line being prefetched. + * + * @param p Address to prefetch + */ +__rte_experimental +static inline void +rte_prefetch2_write(const void *p) +{ + /* 1 indicates intention to write, 1 sets target cache level to L3. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 1); +} + #endif /* _RTE_PREFETCH_H_ */ -- 2.20.1