From 45e9be8b6c8d0c655bed7c5c77eeebd31e2348fc Mon Sep 17 00:00:00 2001 From: Gagandeep Singh Date: Fri, 12 Apr 2019 12:28:58 +0000 Subject: [PATCH] net/enetc: set interface mode for SXGMII Support for SXGMII port has been enabled. It will depends on boot loader information passed through IERB. Signed-off-by: Gagandeep Singh --- doc/guides/rel_notes/release_19_05.rst | 1 + drivers/net/enetc/base/enetc_hw.h | 13 ++++++++++++- drivers/net/enetc/enetc_ethdev.c | 11 +++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_19_05.rst b/doc/guides/rel_notes/release_19_05.rst index 0645e3220c..d44b6b57d6 100644 --- a/doc/guides/rel_notes/release_19_05.rst +++ b/doc/guides/rel_notes/release_19_05.rst @@ -147,6 +147,7 @@ New Features New features: * Added physical addressing mode support + * Added SXGMII interface support * **Updated the QuickAssist Technology PMD.** diff --git a/drivers/net/enetc/base/enetc_hw.h b/drivers/net/enetc/base/enetc_hw.h index f36fa11e07..e3738a6953 100644 --- a/drivers/net/enetc/base/enetc_hw.h +++ b/drivers/net/enetc/base/enetc_hw.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #ifndef _ENETC_HW_H_ @@ -84,6 +84,12 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20) #define ENETC_PCAPR0 0x00900 #define ENETC_PCAPR1 0x00904 +#define ENETC_PM0_IF_MODE 0x8300 +#define ENETC_PM1_IF_MODE 0x9300 +#define ENETC_PMO_IFM_RG BIT(2) +#define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) +#define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) +#define ENETC_PM0_IFM_XGMII BIT(12) #define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10) #define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff) @@ -109,6 +115,11 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_G_EIPBRR0 0x00bf8 #define ENETC_G_EIPBRR1 0x00bfc + +/* MAC Counters */ +#define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) +#define ENETC_G_EPFBLPR1_XGMII 0x80000000 + /* general register accessors */ #define enetc_rd_reg(reg) rte_read32((void *)(reg)) #define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg)) diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c index f1807b901c..91e9692d6b 100644 --- a/drivers/net/enetc/enetc_ethdev.c +++ b/drivers/net/enetc/enetc_ethdev.c @@ -139,6 +139,17 @@ enetc_dev_start(struct rte_eth_dev *dev) ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), val | ENETC_PMR_EN); + /* set auto-speed for RGMII */ + if (enetc_port_rd(&hw->hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { + enetc_port_wr(&hw->hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_RGAUTO); + enetc_port_wr(&hw->hw, ENETC_PM1_IF_MODE, ENETC_PM0_IFM_RGAUTO); + } + if (enetc_global_rd(&hw->hw, + ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) { + enetc_port_wr(&hw->hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_XGMII); + enetc_port_wr(&hw->hw, ENETC_PM1_IF_MODE, ENETC_PM0_IFM_XGMII); + } + return 0; } -- 2.20.1