From 4b748eef853ca2a21cc31fcb5dad8dfb226fe09a Mon Sep 17 00:00:00 2001 From: Beilei Xing Date: Wed, 15 May 2019 09:58:36 +0800 Subject: [PATCH] net/i40e: enable new device This patch removes ifdef to enable new device. Signed-off-by: Beilei Xing Acked-by: Qi Zhang --- drivers/net/i40e/base/i40e_adminq_cmd.h | 49 ------------------------- drivers/net/i40e/base/i40e_common.c | 6 --- drivers/net/i40e/base/i40e_devids.h | 2 - drivers/net/i40e/base/i40e_type.h | 2 - drivers/net/i40e/i40e_ethdev.c | 1 + 5 files changed, 1 insertion(+), 59 deletions(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index cf6ef63e39..b459be9212 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -1935,17 +1935,14 @@ enum i40e_aq_phy_type { I40E_PHY_TYPE_25GBASE_LR = 0x22, I40E_PHY_TYPE_25GBASE_AOC = 0x23, I40E_PHY_TYPE_25GBASE_ACC = 0x24, -#ifdef CARLSVILLE_HW I40E_PHY_TYPE_2_5GBASE_T = 0x30, I40E_PHY_TYPE_5GBASE_T = 0x31, -#endif I40E_PHY_TYPE_MAX, I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, I40E_PHY_TYPE_EMPTY = 0xFE, I40E_PHY_TYPE_DEFAULT = 0xFF, }; -#ifdef CARLSVILLE_HW #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ @@ -1984,66 +1981,22 @@ enum i40e_aq_phy_type { BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) -#else -#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ - BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ - BIT_ULL(I40E_PHY_TYPE_XAUI) | \ - BIT_ULL(I40E_PHY_TYPE_XFI) | \ - BIT_ULL(I40E_PHY_TYPE_SFI) | \ - BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ - BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ - BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ - BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ - BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ - BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ - BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ - BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ - BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ - BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ - BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ - BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ - BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ - BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ - BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ - BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ - BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ - BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) -#endif -#ifdef CARLSVILLE_HW #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 -#endif #define I40E_LINK_SPEED_100MB_SHIFT 0x1 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 -#ifdef CARLSVILLE_HW #define I40E_LINK_SPEED_5GB_SHIFT 0x7 -#endif enum i40e_aq_link_speed { I40E_LINK_SPEED_UNKNOWN = 0, I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), -#ifdef CARLSVILLE_HW I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), -#endif I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), @@ -2089,10 +2042,8 @@ struct i40e_aq_get_phy_abilities_resp { #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 -#ifdef CARLSVILLE_HW #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 -#endif u8 fec_cfg_curr_mod_ext_info; #define I40E_AQ_ENABLE_FEC_KR 0x01 #define I40E_AQ_ENABLE_FEC_RS 0x02 diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index fc1ac66dff..37911a99e5 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -35,9 +35,7 @@ STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) case I40E_DEV_ID_QSFP_C: case I40E_DEV_ID_10G_BASE_T: case I40E_DEV_ID_10G_BASE_T4: -#ifdef CARLSVILLE_HW case I40E_DEV_ID_10G_BASE_T_BC: -#endif case I40E_DEV_ID_20G_KR2: case I40E_DEV_ID_20G_KR2_A: case I40E_DEV_ID_25G_B: @@ -1265,10 +1263,8 @@ STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) break; case I40E_PHY_TYPE_100BASE_TX: case I40E_PHY_TYPE_1000BASE_T: -#ifdef CARLSVILLE_HW case I40E_PHY_TYPE_2_5GBASE_T: case I40E_PHY_TYPE_5GBASE_T: -#endif case I40E_PHY_TYPE_10GBASE_T: media = I40E_MEDIA_TYPE_BASET; break; @@ -6703,9 +6699,7 @@ enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, break; case I40E_DEV_ID_10G_BASE_T: case I40E_DEV_ID_10G_BASE_T4: -#ifdef CARLSVILLE_HW case I40E_DEV_ID_10G_BASE_T_BC: -#endif case I40E_DEV_ID_10G_BASE_T_X722: case I40E_DEV_ID_25G_B: case I40E_DEV_ID_25G_SFP28: diff --git a/drivers/net/i40e/base/i40e_devids.h b/drivers/net/i40e/base/i40e_devids.h index ab3f33bfae..f3c59bdea9 100644 --- a/drivers/net/i40e/base/i40e_devids.h +++ b/drivers/net/i40e/base/i40e_devids.h @@ -24,9 +24,7 @@ #define I40E_DEV_ID_25G_SFP28 0x158B #define I40E_DEV_ID_X710_N3000 0x0CF8 #define I40E_DEV_ID_XXV710_N3000 0x0D58 -#ifdef CARLSVILLE_HW #define I40E_DEV_ID_10G_BASE_T_BC 0x15FF -#endif #if defined(INTEGRATED_VF) || defined(VF_DRIVER) || defined(I40E_NDIS_SUPPORT) #define I40E_DEV_ID_VF 0x154C #define I40E_DEV_ID_VF_HV 0x1571 diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h index 7ba62cc121..112866bbf2 100644 --- a/drivers/net/i40e/base/i40e_type.h +++ b/drivers/net/i40e/base/i40e_type.h @@ -329,14 +329,12 @@ struct i40e_phy_info { I40E_PHY_TYPE_OFFSET) #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ I40E_PHY_TYPE_OFFSET) -#ifdef CARLSVILLE_HW /* Offset for 2.5G/5G PHY Types value to bit number conversion */ #define I40E_PHY_TYPE_OFFSET2 (-10) #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \ I40E_PHY_TYPE_OFFSET2) #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \ I40E_PHY_TYPE_OFFSET2) -#endif #define I40E_HW_CAP_MAX_GPIO 30 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index cab440f5a8..815baa1a65 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -435,6 +435,7 @@ static const struct rte_pci_id pci_id_i40e_map[] = { { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) }, { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) }, { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) }, + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) }, { .vendor_id = 0, /* sentinel */ }, }; -- 2.20.1