From 57936c36fd04b4cf1cf6e7d999363019181fc513 Mon Sep 17 00:00:00 2001 From: Nicolas Chautru Date: Sat, 18 Apr 2020 15:46:40 -0700 Subject: [PATCH] baseband/fpga_5gnr_fec: add info get function Add in the "info_get" function to the driver, to allow us to query the device. No capability are available yet. Linking bbdev-test to support the PMD with null capability. Signed-off-by: Nicolas Chautru Acked-by: Dave Burley Acked-by: Niall Power Acked-by: Akhil Goyal --- app/test-bbdev/Makefile | 3 ++ app/test-bbdev/meson.build | 3 ++ .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 9 ++++ .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 53 +++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile index 8272d2b1c8..dc29557f37 100644 --- a/app/test-bbdev/Makefile +++ b/app/test-bbdev/Makefile @@ -23,5 +23,8 @@ LDLIBS += -lm ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y) LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec endif +ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y) +LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec +endif include $(RTE_SDK)/mk/rte.app.mk diff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build index 0d9f684a12..18ab6a8c6c 100644 --- a/app/test-bbdev/meson.build +++ b/app/test-bbdev/meson.build @@ -9,3 +9,6 @@ deps += ['bbdev', 'bus_vdev'] if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC') deps += ['pmd_bbdev_fpga_lte_fec'] endif +if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC') + deps += ['pmd_bbdev_fpga_5gnr_fec'] +endif diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h index 98a2fe9ca8..ab51cb741c 100644 --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h @@ -227,4 +227,13 @@ struct fpga_5gnr_fec_device { bool pf_device; }; +/* Read a register of FPGA 5GNR FEC device */ +static inline uint32_t +fpga_reg_read_32(void *mmio_base, uint32_t offset) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + uint32_t ret = *((volatile uint32_t *)(reg_addr)); + return rte_le_to_cpu_32(ret); +} + #endif /* _FPGA_5GNR_FEC_H_ */ diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index ae0ec11190..b3f2d0ef6c 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -28,8 +28,61 @@ fpga_dev_close(struct rte_bbdev *dev __rte_unused) return 0; } +static void +fpga_dev_info_get(struct rte_bbdev *dev, + struct rte_bbdev_driver_info *dev_info) +{ + struct fpga_5gnr_fec_device *d = dev->data->dev_private; + uint32_t q_id = 0; + + static const struct rte_bbdev_op_cap bbdev_capabilities[] = { + RTE_BBDEV_END_OF_CAPABILITIES_LIST() + }; + + /* Check the HARQ DDR size available */ + uint8_t timeout_counter = 0; + uint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS); + while (harq_buf_ready != 1) { + usleep(FPGA_TIMEOUT_CHECK_INTERVAL); + timeout_counter++; + harq_buf_ready = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS); + if (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) { + rte_bbdev_log(ERR, "HARQ Buffer not ready %d", + harq_buf_ready); + harq_buf_ready = 1; + } + } + uint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); + + static struct rte_bbdev_queue_conf default_queue_conf; + default_queue_conf.socket = dev->data->socket_id; + default_queue_conf.queue_size = FPGA_RING_MAX_SIZE; + + dev_info->driver_name = dev->device->driver->name; + dev_info->queue_size_lim = FPGA_RING_MAX_SIZE; + dev_info->hardware_accelerated = true; + dev_info->min_alignment = 64; + dev_info->harq_buffer_size = (harq_buf_size >> 10) + 1; + dev_info->default_queue_conf = default_queue_conf; + dev_info->capabilities = bbdev_capabilities; + dev_info->cpu_flag_reqs = NULL; + + /* Calculates number of queues assigned to device */ + dev_info->max_num_queues = 0; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2)); + if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) + dev_info->max_num_queues++; + } +} + static const struct rte_bbdev_ops fpga_ops = { .close = fpga_dev_close, + .info_get = fpga_dev_info_get, }; /* Initialization Function */ -- 2.20.1