From 65be2ca6e0256836c0a74bfa27cc458f1f80b44d Mon Sep 17 00:00:00 2001 From: Gregory Etelson Date: Tue, 2 Nov 2021 10:53:39 +0200 Subject: [PATCH] common/mlx5: extend flex parser capabilities MLX5 PARSE_GRAPH_NODE is the main data structure used by the Flex Parser when a new parsing protocol is defined. While software creates PARSE_GRAPH_NODE object for a new protocol, it must verify that configuration parameters it uses comply with hardware limits. The patch queries hardware PARSE_GRAPH_NODE capabilities and stores ones in PMD internal configuration structure: - query capabilities from parse_graph_node attribute page - query max_num_prog_sample_field capability from HCA page 2 Signed-off-by: Gregory Etelson Reviewed-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 57 ++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 65 +++++++++++++++++++++++++++- drivers/common/mlx5/mlx5_prm.h | 50 ++++++++++++++++++++- 3 files changed, 168 insertions(+), 4 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 2a7dace259..9b5a3b181a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -729,6 +729,53 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, return parse_flex_obj; } +static int +mlx5_devx_cmd_query_hca_parse_graph_node_cap + (void *ctx, struct mlx5_hca_flex_attr *attr) +{ + uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; + uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; + void *hcattr; + int rc; + + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); + attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); + attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, + header_length_mode); + attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, + sample_offset_mode); + attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, + max_num_arc_in); + attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, + max_num_arc_out); + attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, + max_num_sample); + attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, + sample_id_in_out); + attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, + max_base_header_length); + attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, + max_sample_base_offset); + attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, + max_next_header_offset); + attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, + header_length_mask_width); + /* Get the max supported samples from HCA CAP 2 */ + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + attr->max_num_prog_sample = + MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); + return 0; +} + static int mlx5_devx_query_pkt_integrity_match(void *hcattr) { @@ -943,6 +990,16 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, log_max_num_meter_aso); } } + /* + * Flex item support needs max_num_prog_sample_field + * from the Capabilities 2 table for PARSE_GRAPH_NODE + */ + if (attr->parse_graph_flex_node) { + rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap + (ctx, &attr->flex); + if (rc) + return -1; + } if (attr->vdpa.valid) mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); if (!attr->eth_net_offloads) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 40e36fb914..9c9d0862e8 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -6,6 +6,7 @@ #define RTE_PMD_MLX5_DEVX_CMDS_H_ #include +#include #include "mlx5_glue.h" #include "mlx5_prm.h" @@ -86,6 +87,64 @@ struct mlx5_hca_flow_attr { uint32_t tunnel_header_2_3; }; +/** + * Accumulate port PARSE_GRAPH_NODE capabilities from + * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables + */ +__extension__ +struct mlx5_hca_flex_attr { + uint32_t node_in; + uint32_t node_out; + uint16_t header_length_mode; + uint16_t sample_offset_mode; + uint8_t max_num_arc_in; + uint8_t max_num_arc_out; + uint8_t max_num_sample; + uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ + uint8_t sample_id_in_out:1; + uint16_t max_base_header_length; + uint8_t max_sample_base_offset; + uint16_t max_next_header_offset; + uint8_t header_length_mask_width; +}; + +/* ISO C restricts enumerator values to range of 'int' */ +__extension__ +enum { + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) +}; + +enum { + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) +}; + +/* + * DWORD shift is the base for calculating header_length_field_mask + * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. + */ +#define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 + +static inline uint32_t +mlx5_hca_parse_graph_node_base_hdr_len_mask + (const struct mlx5_hca_flex_attr *attr) +{ + return (1 << attr->header_length_mask_width) - 1; +} + /* HCA supports this number of time periods for LRO. */ #define MLX5_LRO_NUM_SUPP_PERIODS 4 @@ -165,6 +224,7 @@ struct mlx5_hca_attr { struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; struct mlx5_hca_flow_attr flow; + struct mlx5_hca_flex_attr flex; int log_max_qp_sz; int log_max_cq_sz; int log_max_qp; @@ -587,8 +647,9 @@ int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, uint32_t ids[], uint32_t num); __rte_internal -struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, - struct mlx5_devx_graph_node_attr *data); +struct mlx5_devx_obj * +mlx5_devx_cmd_create_flex_parser(void *ctx, + struct mlx5_devx_graph_node_attr *data); __rte_internal int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index fb75f2da4d..4835d0406e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -975,7 +975,14 @@ struct mlx5_ifc_fte_match_set_misc4_bits { u8 prog_sample_field_id_2[0x20]; u8 prog_sample_field_value_3[0x20]; u8 prog_sample_field_id_3[0x20]; - u8 reserved_at_100[0x100]; + u8 prog_sample_field_value_4[0x20]; + u8 prog_sample_field_id_4[0x20]; + u8 prog_sample_field_value_5[0x20]; + u8 prog_sample_field_id_5[0x20]; + u8 prog_sample_field_value_6[0x20]; + u8 prog_sample_field_id_6[0x20]; + u8 prog_sample_field_value_7[0x20]; + u8 prog_sample_field_id_7[0x20]; }; struct mlx5_ifc_fte_match_set_misc5_bits { @@ -1245,6 +1252,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, + MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, }; @@ -1757,6 +1765,27 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 reserved_at_1c0[0x620]; }; +/** + * PARSE_GRAPH_NODE Capabilities Field Descriptions + */ +struct mlx5_ifc_parse_graph_node_cap_bits { + u8 node_in[0x20]; + u8 node_out[0x20]; + u8 header_length_mode[0x10]; + u8 sample_offset_mode[0x10]; + u8 max_num_arc_in[0x08]; + u8 max_num_arc_out[0x08]; + u8 max_num_sample[0x08]; + u8 reserved_at_78[0x07]; + u8 sample_id_in_out[0x1]; + u8 max_base_header_length[0x10]; + u8 reserved_at_90[0x08]; + u8 max_sample_base_offset[0x08]; + u8 max_next_header_offset[0x10]; + u8 reserved_at_b0[0x08]; + u8 header_length_mask_width[0x08]; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -1851,9 +1880,14 @@ struct mlx5_ifc_flow_table_nic_cap_bits { ft_field_support_2_nic_receive; }; +/* + * HCA Capabilities 2 + */ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_0[0x80]; /* End of DW4. */ - u8 reserved_at_80[0xb]; + u8 reserved_at_80[0x3]; + u8 max_num_prog_sample_field[0x5]; + u8 reserved_at_88[0x3]; u8 log_max_num_reserved_qpn[0x5]; u8 reserved_at_90[0x3]; u8 log_reserved_qpn_granularity[0x5]; @@ -3955,6 +3989,12 @@ enum mlx5_parse_graph_flow_match_sample_offset_mode { MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, }; +enum mlx5_parse_graph_flow_match_sample_tunnel_mode { + MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, + MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, + MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 +}; + /* Node index for an input / output arc of the flex parser graph. */ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_NULL = 0x0, @@ -3968,9 +4008,15 @@ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, + MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, + MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, }; +#define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 +#define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 +#define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 + /** * Convert a user mark to flow mark. * -- 2.39.5