From 6c9577bf24f25a48b38c6390177d32a6ddf26480 Mon Sep 17 00:00:00 2001 From: Andrew Rybchenko Date: Thu, 19 Apr 2018 12:36:46 +0100 Subject: [PATCH] net/sfc/base: detect equal stride super-buffer support Equal stride super-buffer Rx mode is supported on Medford2 by DPDK firmware variant. Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_nic.c | 6 ++++++ drivers/net/sfc/base/efx.h | 1 + drivers/net/sfc/base/siena_nic.c | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index e1f1c2e3e7..35b719ac89 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -1114,6 +1114,12 @@ ef10_get_datapath_caps( else encp->enc_rx_var_packed_stream_supported = B_FALSE; + /* Check if the firmware supports equal stride super-buffer mode */ + if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER)) + encp->enc_rx_es_super_buffer_supported = B_TRUE; + else + encp->enc_rx_es_super_buffer_supported = B_FALSE; + /* Check if the firmware supports FW subvariant w/o Tx checksumming */ if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM)) encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE; diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 0b75f0fcee..dea8d60d52 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1270,6 +1270,7 @@ typedef struct efx_nic_cfg_s { boolean_t enc_init_evq_v2_supported; boolean_t enc_rx_packed_stream_supported; boolean_t enc_rx_var_packed_stream_supported; + boolean_t enc_rx_es_super_buffer_supported; boolean_t enc_fw_subvariant_no_tx_csum_supported; boolean_t enc_pm_and_rxdp_counters; boolean_t enc_mac_stats_40g_tx_size_bins; diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index c3a949539c..15aa06b772 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -161,6 +161,7 @@ siena_board_cfg( encp->enc_allow_set_mac_with_installed_filters = B_TRUE; encp->enc_rx_packed_stream_supported = B_FALSE; encp->enc_rx_var_packed_stream_supported = B_FALSE; + encp->enc_rx_es_super_buffer_supported = B_FALSE; encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE; /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */ -- 2.20.1