From 84733fd0d75e4943f7f798e868e18d7ef0ed41ea Mon Sep 17 00:00:00 2001
From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Date: Wed, 18 Jan 2017 06:51:20 +0530
Subject: [PATCH] eal/arm64: fix memory barrier definition
dsb instruction based barrier is used for non smp
version of memory barrier.
Fixes: d708f01b7102 ("eal/arm: add atomic operations for ARMv8")
Cc: stable@dpdk.org
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index d854aac3ad..bc7de640c1 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -43,7 +43,8 @@ extern "C" {
#include "generic/rte_atomic.h"
-#define dmb(opt) do { asm volatile("dmb " #opt : : : "memory"); } while (0)
+#define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); }
+#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
/**
* General memory barrier.
@@ -54,7 +55,7 @@ extern "C" {
*/
static inline void rte_mb(void)
{
- dmb(ish);
+ dsb(sy);
}
/**
@@ -66,7 +67,7 @@ static inline void rte_mb(void)
*/
static inline void rte_wmb(void)
{
- dmb(ishst);
+ dsb(st);
}
/**
@@ -78,7 +79,7 @@ static inline void rte_wmb(void)
*/
static inline void rte_rmb(void)
{
- dmb(ishld);
+ dsb(ld);
}
#define rte_smp_mb() rte_mb()
--
2.39.5