From 84d79658660414e4985a455259c4b46e9e77366d Mon Sep 17 00:00:00 2001 From: Declan Doherty Date: Wed, 21 Dec 2016 22:05:00 +0000 Subject: [PATCH] crypto/aesni_mb: support AVX512 Release v0.44 of Intel(R) Multi-Buffer Crypto for IPsec library adds support for AVX512 instructions. This patch enables the new AVX512 accelerated functions from the aesni_mb_pmd crypto poll mode driver. This patch set requires that the aesni_mb_pmd is linked against the version 0.44 or greater of the Multi-Buffer Crypto for IPsec library. Signed-off-by: Declan Doherty Acked-by: Pablo de Lara --- doc/guides/cryptodevs/overview.rst | 1 + drivers/crypto/aesni_mb/aesni_mb_ops.h | 28 +++++++++++++++++++++- drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 7 +++++- lib/librte_cryptodev/rte_cryptodev.h | 2 ++ 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/doc/guides/cryptodevs/overview.rst b/doc/guides/cryptodevs/overview.rst index 2352b6a251..6a4a32a322 100644 --- a/doc/guides/cryptodevs/overview.rst +++ b/doc/guides/cryptodevs/overview.rst @@ -42,6 +42,7 @@ Supported Feature Flags "RTE_CRYPTODEV_FF_CPU_SSE",,,x,x,x,x "RTE_CRYPTODEV_FF_CPU_AVX",,,x,x,x,x "RTE_CRYPTODEV_FF_CPU_AVX2",,,x,x,, + "RTE_CRYPTODEV_FF_CPU_AVX512",,,x,,, "RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,, "RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,, diff --git a/drivers/crypto/aesni_mb/aesni_mb_ops.h b/drivers/crypto/aesni_mb/aesni_mb_ops.h index 0c119bf150..2d41d73cb8 100644 --- a/drivers/crypto/aesni_mb/aesni_mb_ops.h +++ b/drivers/crypto/aesni_mb/aesni_mb_ops.h @@ -44,7 +44,8 @@ enum aesni_mb_vector_mode { RTE_AESNI_MB_NOT_SUPPORTED = 0, RTE_AESNI_MB_SSE, RTE_AESNI_MB_AVX, - RTE_AESNI_MB_AVX2 + RTE_AESNI_MB_AVX2, + RTE_AESNI_MB_AVX512 }; typedef void (*md5_one_block_t)(void *data, void *digest); @@ -203,6 +204,31 @@ static const struct aesni_mb_ops job_ops[] = { aes_xcbc_expand_key_avx2 } } + }, + [RTE_AESNI_MB_AVX512] = { + .job = { + init_mb_mgr_avx512, + get_next_job_avx512, + submit_job_avx512, + get_completed_job_avx512, + flush_job_avx512 + }, + .aux = { + .one_block = { + md5_one_block_avx512, + sha1_one_block_avx512, + sha224_one_block_avx512, + sha256_one_block_avx512, + sha384_one_block_avx512, + sha512_one_block_avx512 + }, + .keyexp = { + aes_keyexp_128_avx512, + aes_keyexp_192_avx512, + aes_keyexp_256_avx512, + aes_xcbc_expand_key_avx512 + } + } } }; diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c index bafd4d723e..6d27d75285 100644 --- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c +++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c @@ -655,7 +655,9 @@ cryptodev_aesni_mb_create(const char *name, } /* Check CPU for supported vector instruction set */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + vector_mode = RTE_AESNI_MB_AVX512; + else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) vector_mode = RTE_AESNI_MB_AVX2; else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX)) vector_mode = RTE_AESNI_MB_AVX; @@ -702,6 +704,9 @@ cryptodev_aesni_mb_create(const char *name, case RTE_AESNI_MB_AVX2: dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2; break; + case RTE_AESNI_MB_AVX512: + dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX512; + break; default: break; } diff --git a/lib/librte_cryptodev/rte_cryptodev.h b/lib/librte_cryptodev/rte_cryptodev.h index 8f63e8f6b1..29d8eece87 100644 --- a/lib/librte_cryptodev/rte_cryptodev.h +++ b/lib/librte_cryptodev/rte_cryptodev.h @@ -225,6 +225,8 @@ struct rte_cryptodev_capabilities { /**< Utilises CPU AES-NI instructions */ #define RTE_CRYPTODEV_FF_HW_ACCELERATED (1ULL << 7) /**< Operations are off-loaded to an external hardware accelerator */ +#define RTE_CRYPTODEV_FF_CPU_AVX512 (1ULL << 8) +/**< Utilises CPU SIMD AVX512 instructions */ /** -- 2.20.1