From 8cce758d693a414a8a783a32c754d01a904f5930 Mon Sep 17 00:00:00 2001 From: Wenzhuo Lu Date: Wed, 23 Nov 2016 12:22:46 -0500 Subject: [PATCH] net/e1000/base: avoid packet loss for non-1G To avoid packet loss, Phase Lock Loop (PLL) clock gate time needs to be increased for non 1G speeds. Signed-off-by: Wenzhuo Lu --- drivers/net/e1000/base/e1000_ich8lan.c | 15 +++++++++++++++ drivers/net/e1000/base/e1000_ich8lan.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c index 4a5cef0d91..7aea8dd539 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.c +++ b/drivers/net/e1000/base/e1000_ich8lan.c @@ -1486,6 +1486,21 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) emi_addr = I217_RX_CONFIG; ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); + + if (hw->mac.type >= e1000_pch_lpt) { + u16 phy_reg; + + hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, + &phy_reg); + phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; + if (speed == SPEED_100 || speed == SPEED_10) + phy_reg |= 0x3E8; + else + phy_reg |= 0xFA; + hw->phy.ops.write_reg_locked(hw, + I217_PLL_CLOCK_GATE_REG, + phy_reg); + } hw->phy.ops.release(hw); if (ret_val) diff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h index 33e77fb878..6aa928891f 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.h +++ b/drivers/net/e1000/base/e1000_ich8lan.h @@ -237,6 +237,9 @@ POSSIBILITY OF SUCH DAMAGE. #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 #define HV_PM_CTRL_K1_ENABLE 0x4000 +#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) +#define I217_PLL_CLOCK_GATE_MASK 0x07FF + #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ /* Inband Control */ -- 2.20.1