From a02286c8d7c46a011cbd8fe840a6ab36ee18a95b Mon Sep 17 00:00:00 2001 From: Intel Date: Thu, 20 Dec 2012 00:00:00 +0100 Subject: [PATCH] ixgbe: minor changes Signed-off-by: Intel --- lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c | 89 ++++++++------- lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c | 119 ++++++++++---------- lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c | 7 +- lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h | 1 - lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c | 47 ++++---- lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c | 36 +++--- lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.h | 4 +- lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h | 1 + lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c | 40 +++---- lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 131 +++++++++++----------- lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c | 17 ++- lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c | 47 ++++---- 12 files changed, 274 insertions(+), 265 deletions(-) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c index 7bb6802ceb..fd66b46bfa 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c @@ -38,32 +38,32 @@ POSSIBILITY OF SUCH DAMAGE. u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); -static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg); -static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); +STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); -static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, bool autoneg_wait_to_complete); -static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete); -static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); -static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); -static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); +STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw); void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw); s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); -static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); +STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on); -static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); +STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, @@ -198,8 +198,7 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) mac->ops.check_link = &ixgbe_check_mac_link_82598; mac->ops.setup_link = &ixgbe_setup_mac_link_82598; mac->ops.flap_tx_laser = NULL; - mac->ops.get_link_capabilities = - &ixgbe_get_link_capabilities_82598; + mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598; mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598; /* Manageability interface */ @@ -321,7 +320,7 @@ s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) * * Determines the link capabilities by reading the AUTOC register. **/ -static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg) { @@ -343,17 +342,17 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, switch (autoc & IXGBE_AUTOC_LMS_MASK) { case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: *speed = IXGBE_LINK_SPEED_1GB_FULL; - *autoneg = FALSE; + *autoneg = false; break; case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: *speed = IXGBE_LINK_SPEED_10GB_FULL; - *autoneg = FALSE; + *autoneg = false; break; case IXGBE_AUTOC_LMS_1G_AN: *speed = IXGBE_LINK_SPEED_1GB_FULL; - *autoneg = TRUE; + *autoneg = true; break; case IXGBE_AUTOC_LMS_KX4_AN: @@ -363,7 +362,7 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX_SUPP) *speed |= IXGBE_LINK_SPEED_1GB_FULL; - *autoneg = TRUE; + *autoneg = true; break; default: @@ -380,7 +379,7 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, * * Returns the media type (fiber, copper, backplane) **/ -static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) +STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) { enum ixgbe_media_type media_type; @@ -450,7 +449,7 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) * so if it's on turn it off once we know link_speed. For * more details see 82598 Specification update. */ - hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); + hw->mac.ops.check_link(hw, &link_speed, &link_up, false); if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { switch (hw->fc.requested_mode) { case ixgbe_fc_full: @@ -564,7 +563,7 @@ out: * Configures link settings based on values in the ixgbe_hw struct. * Restarts the link. Performs autonegotiation if needed. **/ -static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, bool autoneg_wait_to_complete) { u32 autoc_reg; @@ -612,7 +611,7 @@ static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, * Function indicates success when phy link is available. If phy is not ready * within 5 seconds of MAC indicating link, the function returns error. **/ -static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) +STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) { u32 timeout; u16 an_reg; @@ -644,12 +643,12 @@ static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) * ixgbe_check_mac_link_82598 - Get link/speed status * @hw: pointer to hardware structure * @speed: pointer to link speed - * @link_up: TRUE is link is up, FALSE otherwise + * @link_up: true is link is up, false otherwise * @link_up_wait_to_complete: bool used to wait for link up or not * * Reads the links register to determine if link is up and the current speed **/ -static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete) { @@ -674,10 +673,10 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) { - *link_up = TRUE; + *link_up = true; break; } else { - *link_up = FALSE; + *link_up = false; } msec_delay(100); hw->phy.ops.read_reg(hw, 0xC79F, @@ -689,12 +688,12 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, } } else { if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) - *link_up = TRUE; + *link_up = true; else - *link_up = FALSE; + *link_up = false; } - if (*link_up == FALSE) + if (*link_up == false) goto out; } @@ -702,19 +701,19 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, if (link_up_wait_to_complete) { for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { if (links_reg & IXGBE_LINKS_UP) { - *link_up = TRUE; + *link_up = true; break; } else { - *link_up = FALSE; + *link_up = false; } msec_delay(100); links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); } } else { if (links_reg & IXGBE_LINKS_UP) - *link_up = TRUE; + *link_up = true; else - *link_up = FALSE; + *link_up = false; } if (links_reg & IXGBE_LINKS_SPEED) @@ -722,9 +721,9 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, else *speed = IXGBE_LINK_SPEED_1GB_FULL; - if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) && + if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) && (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS)) - *link_up = FALSE; + *link_up = false; /* if link is down, zero out the current_mode */ if (*link_up == FALSE) { @@ -739,12 +738,12 @@ out: * ixgbe_setup_mac_link_82598 - Set MAC link speed * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Set the link speed in the AUTOC register and restarts link. **/ -static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) { @@ -793,12 +792,12 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE if waiting is needed to complete + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true if waiting is needed to complete * * Sets the link speed in the AUTOC register in the MAC and restarts link. **/ -static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, +STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) @@ -824,7 +823,7 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, * clears all interrupts, performing a PHY reset, and performing a link (MAC) * reset. **/ -static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) +STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; s32 phy_status = IXGBE_SUCCESS; @@ -875,7 +874,7 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) } /* Reset PHY */ - if (hw->phy.reset_disable == FALSE) { + if (hw->phy.reset_disable == false) { /* PHY ops must be identified and initialized prior to reset */ /* Init PHY and function pointers, perform SFP setup */ @@ -931,9 +930,9 @@ mac_reset_top: * AUTOC value since the reset operation sets back to deaults. */ autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); - if (hw->mac.orig_link_settings_stored == FALSE) { + if (hw->mac.orig_link_settings_stored == false) { hw->mac.orig_autoc = autoc; - hw->mac.orig_link_settings_stored = TRUE; + hw->mac.orig_link_settings_stored = true; } else if (autoc != hw->mac.orig_autoc) { IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); } @@ -986,7 +985,7 @@ s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) * @rar: receive address register index to associate with a VMDq index * @vmdq: VMDq clear index (not used in 82598, but elsewhere) **/ -static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) +STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) { u32 rar_high; u32 rar_entries = hw->mac.num_rar_entries; @@ -1064,7 +1063,7 @@ s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, * * Clears the VLAN filer table, and the VMDq index associated with the filter **/ -static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) +STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) { u32 offset; u32 vlanbyte; diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c index 4dd3544680..986de332df 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c @@ -56,7 +56,7 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); -static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, +STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete); @@ -70,11 +70,11 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); -static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); +STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); -static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, +STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, u16 offset, u16 *data); -static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, +STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data); void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) @@ -295,7 +295,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & - IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; + IXGBE_FWSM_MODE_MASK) ? true : false; hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; @@ -306,6 +306,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) /* Manageability interface */ mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; + return ret_val; } @@ -313,7 +314,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) * ixgbe_get_link_capabilities_82599 - Determines link capabilities * @hw: pointer to hardware structure * @speed: pointer to link speed - * @negotiation: TRUE when autoneg or autotry is enabled + * @negotiation: true when autoneg or autotry is enabled * * Determines the link capabilities by reading the AUTOC register. **/ @@ -331,7 +332,7 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { *speed = IXGBE_LINK_SPEED_1GB_FULL; - *negotiation = TRUE; + *negotiation = true; goto out; } @@ -348,22 +349,22 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, switch (autoc & IXGBE_AUTOC_LMS_MASK) { case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: *speed = IXGBE_LINK_SPEED_1GB_FULL; - *negotiation = FALSE; + *negotiation = false; break; case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: *speed = IXGBE_LINK_SPEED_10GB_FULL; - *negotiation = FALSE; + *negotiation = false; break; case IXGBE_AUTOC_LMS_1G_AN: *speed = IXGBE_LINK_SPEED_1GB_FULL; - *negotiation = TRUE; + *negotiation = true; break; case IXGBE_AUTOC_LMS_10G_SERIAL: *speed = IXGBE_LINK_SPEED_10GB_FULL; - *negotiation = FALSE; + *negotiation = false; break; case IXGBE_AUTOC_LMS_KX4_KX_KR: @@ -375,7 +376,7 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX_SUPP) *speed |= IXGBE_LINK_SPEED_1GB_FULL; - *negotiation = TRUE; + *negotiation = true; break; case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: @@ -386,12 +387,12 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, *speed |= IXGBE_LINK_SPEED_10GB_FULL; if (autoc & IXGBE_AUTOC_KX_SUPP) *speed |= IXGBE_LINK_SPEED_1GB_FULL; - *negotiation = TRUE; + *negotiation = true; break; case IXGBE_AUTOC_LMS_SGMII_1G_100M: *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; - *negotiation = FALSE; + *negotiation = false; break; default: @@ -403,7 +404,7 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, if (hw->phy.multispeed_fiber) { *speed |= IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL; - *negotiation = TRUE; + *negotiation = true; } out: @@ -465,7 +466,7 @@ out: /** * ixgbe_start_mac_link_82599 - Setup MAC link settings * @hw: pointer to hardware structure - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Configures link settings based on values in the ixgbe_hw struct. * Restarts the link. Performs autonegotiation if needed. @@ -557,11 +558,11 @@ void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) * @hw: pointer to hardware structure * * When the driver changes the link speeds that it can support, - * it sets autotry_restart to TRUE to indicate that we need to + * it sets autotry_restart to true to indicate that we need to * initiate a new autotry session with the link partner. To do * so, we set the speed then disable and re-enable the tx laser, to * alert the link partner that it also needs to restart autotry on its - * end. This is consistent with TRUE clause 37 autoneg, which also + * end. This is consistent with true clause 37 autoneg, which also * involves a loss of signal. **/ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) @@ -571,7 +572,7 @@ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) if (hw->mac.autotry_restart) { ixgbe_disable_tx_laser_multispeed_fiber(hw); ixgbe_enable_tx_laser_multispeed_fiber(hw); - hw->mac.autotry_restart = FALSE; + hw->mac.autotry_restart = false; } } @@ -579,8 +580,8 @@ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Set the link speed in the AUTOC register and restarts link. **/ @@ -594,7 +595,7 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, u32 speedcnt = 0; u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); u32 i = 0; - bool link_up = FALSE; + bool link_up = false; bool negotiation; DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); @@ -615,7 +616,7 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; /* If we already have link at this speed, just jump out */ - status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); + status = ixgbe_check_link(hw, &link_speed, &link_up, false); if (status != IXGBE_SUCCESS) return status; @@ -651,7 +652,7 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, /* If we have link, just jump out */ status = ixgbe_check_link(hw, &link_speed, - &link_up, FALSE); + &link_up, false); if (status != IXGBE_SUCCESS) return status; @@ -666,7 +667,7 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; /* If we already have link at this speed, just jump out */ - status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); + status = ixgbe_check_link(hw, &link_speed, &link_up, false); if (status != IXGBE_SUCCESS) return status; @@ -696,7 +697,7 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, msec_delay(100); /* If we have link, just jump out */ - status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); + status = ixgbe_check_link(hw, &link_speed, &link_up, false); if (status != IXGBE_SUCCESS) return status; @@ -730,8 +731,8 @@ out: * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Implements the Intel SmartSpeed algorithm. **/ @@ -742,7 +743,7 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, s32 status = IXGBE_SUCCESS; ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; s32 i, j; - bool link_up = FALSE; + bool link_up = false; u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); @@ -767,7 +768,7 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, */ /* First, try to get link with full advertisement */ - hw->phy.smart_speed_active = FALSE; + hw->phy.smart_speed_active = false; for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, autoneg_wait_to_complete); @@ -785,7 +786,7 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, /* If we have link, just jump out */ status = ixgbe_check_link(hw, &link_speed, &link_up, - FALSE); + false); if (status != IXGBE_SUCCESS) goto out; @@ -803,7 +804,7 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, goto out; /* Turn SmartSpeed on to disable KR support */ - hw->phy.smart_speed_active = TRUE; + hw->phy.smart_speed_active = true; status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, autoneg_wait_to_complete); if (status != IXGBE_SUCCESS) @@ -819,7 +820,7 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, msec_delay(100); /* If we have link, just jump out */ - status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); + status = ixgbe_check_link(hw, &link_speed, &link_up, false); if (status != IXGBE_SUCCESS) goto out; @@ -828,7 +829,7 @@ s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, } /* We didn't get link. Turn SmartSpeed back off. */ - hw->phy.smart_speed_active = FALSE; + hw->phy.smart_speed_active = false; status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, autoneg_wait_to_complete); @@ -843,8 +844,8 @@ out: * ixgbe_setup_mac_link_82599 - Set MAC link speed * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Set the link speed in the AUTOC register and restarts link. **/ @@ -893,7 +894,7 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) autoc |= IXGBE_AUTOC_KX4_SUPP; if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && - (hw->phy.smart_speed_active == FALSE)) + (hw->phy.smart_speed_active == false)) autoc |= IXGBE_AUTOC_KR_SUPP; if (speed & IXGBE_LINK_SPEED_1GB_FULL) autoc |= IXGBE_AUTOC_KX_SUPP; @@ -957,12 +958,12 @@ out: * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE if waiting is needed to complete + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true if waiting is needed to complete * * Restarts link on PHY and MAC based on settings passed in. **/ -static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, +STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete) @@ -993,7 +994,7 @@ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) ixgbe_link_speed link_speed; s32 status; u32 ctrl, i, autoc, autoc2; - bool link_up = FALSE; + bool link_up = false; DEBUGFUNC("ixgbe_reset_hw_82599"); @@ -1016,14 +1017,14 @@ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) /* Setup SFP module if there is one present. */ if (hw->phy.sfp_setup_needed) { status = hw->mac.ops.setup_sfp(hw); - hw->phy.sfp_setup_needed = FALSE; + hw->phy.sfp_setup_needed = false; } if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) goto reset_hw_out; /* Reset PHY */ - if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) + if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) hw->phy.ops.reset(hw); mac_reset_top: @@ -1035,7 +1036,7 @@ mac_reset_top: */ ctrl = IXGBE_CTRL_LNK_RST; if (!hw->force_full_reset) { - hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); + hw->mac.ops.check_link(hw, &link_speed, &link_up, false); if (link_up) ctrl = IXGBE_CTRL_RST; } @@ -1079,7 +1080,7 @@ mac_reset_top: if (hw->mac.orig_link_settings_stored == FALSE) { hw->mac.orig_autoc = autoc; hw->mac.orig_autoc2 = autoc2; - hw->mac.orig_link_settings_stored = TRUE; + hw->mac.orig_link_settings_stored = true; } else { if (autoc != hw->mac.orig_autoc) IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | @@ -1149,7 +1150,7 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) } if (i >= IXGBE_FDIRCMD_CMD_POLL) { DEBUGOUT("Flow Director previous command isn't complete, " - "aborting table re-initialization. \n"); + "aborting table re-initialization.\n"); return IXGBE_ERR_FDIR_REINIT_FAILED; } @@ -1207,7 +1208,7 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) * @hw: pointer to hardware structure * @fdirctrl: value to write to flow director control register **/ -static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) +STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) { int i; @@ -1548,7 +1549,7 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, * generate a correctly swapped value we need to bit swap the mask and that * is what is accomplished by this function. **/ -static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) +STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) { u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; @@ -1596,9 +1597,8 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, */ /* verify bucket hash is cleared on hash generation */ - if (input_mask->formatted.bkt_hash) { + if (input_mask->formatted.bkt_hash) DEBUGOUT(" bucket hash should always be 0 in mask\n"); - } /* Program FDIRM and verify partial masks */ switch (input_mask->formatted.vm_pool & 0x7F) { @@ -1906,7 +1906,7 @@ s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) goto out; /* We need to run link autotry after the driver loads */ - hw->mac.autotry_restart = TRUE; + hw->mac.autotry_restart = true; if (ret_val == IXGBE_SUCCESS) ret_val = ixgbe_verify_fw_version_82599(hw); @@ -2129,7 +2129,7 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or * if the FW version is not supported. **/ -static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) +STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) { s32 status = IXGBE_ERR_EEPROM_VERSION; u16 fw_offset, fw_ptp_cfg_offset; @@ -2159,8 +2159,7 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) /* get the firmware version */ hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + - IXGBE_FW_PATCH_VERSION_4), - &fw_version); + IXGBE_FW_PATCH_VERSION_4), &fw_version); if (fw_version > 0x5) status = IXGBE_SUCCESS; @@ -2173,12 +2172,12 @@ fw_version_out: * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. * @hw: pointer to hardware structure * - * Returns TRUE if the LESM FW module is present and enabled. Otherwise - * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. + * Returns true if the LESM FW module is present and enabled. Otherwise + * returns false. Smart Speed must be disabled if LESM FW module is enabled. **/ bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) { - bool lesm_enabled = FALSE; + bool lesm_enabled = false; u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; s32 status; @@ -2207,7 +2206,7 @@ bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) if ((status == IXGBE_SUCCESS) && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) - lesm_enabled = TRUE; + lesm_enabled = true; out: return lesm_enabled; @@ -2224,7 +2223,7 @@ out: * * Retrieves 16 bit word(s) read from EEPROM **/ -static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, +STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; @@ -2258,7 +2257,7 @@ static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, * * Reads a 16 bit word from the EEPROM **/ -static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, +STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, u16 offset, u16 *data) { struct ixgbe_eeprom_info *eeprom = &hw->eeprom; diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c index 579449a0ac..0ca32a33ba 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c @@ -509,7 +509,7 @@ s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, * ixgbe_setup_phy_link_speed - Set auto advertise * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled + * @autoneg: true if autonegotiation enabled * * Sets the auto advertised capabilities **/ @@ -578,7 +578,7 @@ void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) * ixgbe_setup_link - Set link speed * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled + * @autoneg: true if autonegotiation enabled * * Configures link settings. Restarts the link. * Performs autonegotiation if needed. @@ -971,6 +971,7 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, build, ver), IXGBE_NOT_IMPLEMENTED); } + /** * ixgbe_read_analog_reg8 - Reads 8 bit analog register * @hw: pointer to hardware structure @@ -1087,7 +1088,7 @@ u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) } /** - * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics + * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics * @hw: pointer to hardware structure * @regval: bitfield to write to the Rx DMA register * diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h index a120f891d0..39eefd0143 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h @@ -163,5 +163,4 @@ s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix); s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs); - #endif /* _IXGBE_API_H_ */ diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c index fc28375367..d57a3978d0 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c @@ -182,7 +182,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) ixgbe_setup_fc(hw, 0); /* Clear adapter stopped flag */ - hw->adapter_stopped = FALSE; + hw->adapter_stopped = false; return IXGBE_SUCCESS; } @@ -634,7 +634,7 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) * Set the adapter_stopped flag so other driver functions stop touching * the hardware */ - hw->adapter_stopped = TRUE; + hw->adapter_stopped = true; /* Disable the receive unit */ IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0); @@ -2907,7 +2907,7 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) * Link must be up to auto-blink the LEDs; * Force it if link is down. */ - hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); + hw->mac.ops.check_link(hw, &speed, &link_up, false); if (!link_up) { autoc_reg |= IXGBE_AUTOC_AN_RESTART; @@ -3376,39 +3376,39 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, /* set the pool bit */ if (vind < 32) { bits = IXGBE_READ_REG(hw, - IXGBE_VLVFB(vlvf_index*2)); + IXGBE_VLVFB(vlvf_index * 2)); bits |= (1 << vind); IXGBE_WRITE_REG(hw, - IXGBE_VLVFB(vlvf_index*2), + IXGBE_VLVFB(vlvf_index * 2), bits); } else { bits = IXGBE_READ_REG(hw, - IXGBE_VLVFB((vlvf_index*2)+1)); - bits |= (1 << (vind-32)); + IXGBE_VLVFB((vlvf_index * 2) + 1)); + bits |= (1 << (vind - 32)); IXGBE_WRITE_REG(hw, - IXGBE_VLVFB((vlvf_index*2)+1), + IXGBE_VLVFB((vlvf_index * 2) + 1), bits); } } else { /* clear the pool bit */ if (vind < 32) { bits = IXGBE_READ_REG(hw, - IXGBE_VLVFB(vlvf_index*2)); + IXGBE_VLVFB(vlvf_index * 2)); bits &= ~(1 << vind); IXGBE_WRITE_REG(hw, - IXGBE_VLVFB(vlvf_index*2), + IXGBE_VLVFB(vlvf_index * 2), bits); bits |= IXGBE_READ_REG(hw, - IXGBE_VLVFB((vlvf_index*2)+1)); + IXGBE_VLVFB((vlvf_index * 2) + 1)); } else { bits = IXGBE_READ_REG(hw, - IXGBE_VLVFB((vlvf_index*2)+1)); - bits &= ~(1 << (vind-32)); + IXGBE_VLVFB((vlvf_index * 2) + 1)); + bits &= ~(1 << (vind - 32)); IXGBE_WRITE_REG(hw, - IXGBE_VLVFB((vlvf_index*2)+1), + IXGBE_VLVFB((vlvf_index * 2) + 1), bits); bits |= IXGBE_READ_REG(hw, - IXGBE_VLVFB(vlvf_index*2)); + IXGBE_VLVFB(vlvf_index * 2)); } } @@ -3464,8 +3464,8 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); - IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); - IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); + IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); + IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); } return IXGBE_SUCCESS; @@ -3475,7 +3475,7 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) * ixgbe_check_mac_link_generic - Determine link and speed status * @hw: pointer to hardware structure * @speed: pointer to link speed - * @link_up: TRUE when link is up + * @link_up: true when link is up * @link_up_wait_to_complete: bool used to wait for link up or not * * Reads the links register to determine if link is up and the current speed @@ -3501,19 +3501,19 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, if (link_up_wait_to_complete) { for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { if (links_reg & IXGBE_LINKS_UP) { - *link_up = TRUE; + *link_up = true; break; } else { - *link_up = FALSE; + *link_up = false; } msec_delay(100); links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); } } else { if (links_reg & IXGBE_LINKS_UP) - *link_up = TRUE; + *link_up = true; else - *link_up = FALSE; + *link_up = false; } if ((links_reg & IXGBE_LINKS_SPEED_82599) == @@ -3794,7 +3794,7 @@ static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) * @hw: pointer to the HW structure * @buffer: contains the command to write and where the return status will * be placed - * @lenght: lenght of buffer, must be multiple of 4 bytes + * @length: length of buffer, must be multiple of 4 bytes * * Communicates with the manageability block. On success return IXGBE_SUCCESS * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. @@ -4046,3 +4046,4 @@ void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); } + diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c index 1f885bbb51..0fcf2ca292 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c @@ -152,7 +152,7 @@ s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id) * * returns SUCCESS if it successfully received a message notification **/ -static s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id) +STATIC s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id) { struct ixgbe_mbx_info *mbx = &hw->mbx; int countdown = mbx->timeout; @@ -180,7 +180,7 @@ out: * * returns SUCCESS if it successfully received a message acknowledgement **/ -static s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id) +STATIC s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id) { struct ixgbe_mbx_info *mbx = &hw->mbx; int countdown = mbx->timeout; @@ -283,7 +283,7 @@ void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw) * This function is used to read the v2p mailbox without losing the read to * clear status bits. **/ -static u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw) +STATIC u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw) { u32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX); @@ -301,7 +301,7 @@ static u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw) * This function is used to check for the read to clear bits within * the V2P mailbox. **/ -static s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask) +STATIC s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask) { u32 v2p_mailbox = ixgbe_read_v2p_mailbox(hw); s32 ret_val = IXGBE_ERR_MBX; @@ -321,7 +321,7 @@ static s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask) * * returns SUCCESS if the PF has set the Status bit or else ERR_MBX **/ -static s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id) +STATIC s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id) { s32 ret_val = IXGBE_ERR_MBX; @@ -343,7 +343,7 @@ static s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id) * * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX **/ -static s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id) +STATIC s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id) { s32 ret_val = IXGBE_ERR_MBX; @@ -363,9 +363,9 @@ static s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id) * @hw: pointer to the HW structure * @mbx_id: id of mailbox to check * - * returns TRUE if the PF has set the reset done bit or else FALSE + * returns true if the PF has set the reset done bit or else false **/ -static s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id) +STATIC s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id) { s32 ret_val = IXGBE_ERR_MBX; @@ -387,7 +387,7 @@ static s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id) * * return SUCCESS if we obtained the mailbox lock **/ -static s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw) +STATIC s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw) { s32 ret_val = IXGBE_ERR_MBX; @@ -412,7 +412,7 @@ static s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw) * * returns SUCCESS if it successfully copied message into the buffer **/ -static s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size, +STATIC s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) { s32 ret_val; @@ -454,7 +454,7 @@ out_no_write: * * returns SUCCESS if it successfuly read message from buffer **/ -static s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size, +STATIC s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) { s32 ret_val = IXGBE_SUCCESS; @@ -514,7 +514,7 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw) mbx->stats.rsts = 0; } -static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) +STATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) { u32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index)); s32 ret_val = IXGBE_ERR_MBX; @@ -534,7 +534,7 @@ static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) * * returns SUCCESS if the VF has set the Status bit or else ERR_MBX **/ -static s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number) +STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number) { s32 ret_val = IXGBE_ERR_MBX; s32 index = IXGBE_MBVFICR_INDEX(vf_number); @@ -558,7 +558,7 @@ static s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number) * * returns SUCCESS if the VF has set the Status bit or else ERR_MBX **/ -static s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number) +STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number) { s32 ret_val = IXGBE_ERR_MBX; s32 index = IXGBE_MBVFICR_INDEX(vf_number); @@ -582,7 +582,7 @@ static s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number) * * returns SUCCESS if the VF has set the Status bit or else ERR_MBX **/ -static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) +STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) { u32 reg_offset = (vf_number < 32) ? 0 : 1; u32 vf_shift = vf_number % 32; @@ -618,7 +618,7 @@ static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) * * return SUCCESS if we obtained the mailbox lock **/ -static s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number) +STATIC s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number) { s32 ret_val = IXGBE_ERR_MBX; u32 p2v_mailbox; @@ -645,7 +645,7 @@ static s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number) * * returns SUCCESS if it successfully copied message into the buffer **/ -static s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size, +STATIC s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 vf_number) { s32 ret_val; @@ -688,7 +688,7 @@ out_no_write: * memory buffer. The presumption is that the caller knows that there was * a message due to a VF request so no polling for message is needed. **/ -static s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size, +STATIC s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 vf_number) { s32 ret_val; diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.h index 5c5a32ac07..55513245a3 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.h +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.h @@ -66,7 +66,7 @@ POSSIBILITY OF SUCH DAMAGE. /* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the - * PF. The reverse is TRUE if it is IXGBE_PF_*. + * PF. The reverse is true if it is IXGBE_PF_*. * Message ACK's are the value or'd with 0xF0000000 */ #define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with @@ -74,7 +74,7 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with * this are the NACK */ #define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still - clear to send requests */ + * clear to send requests */ #define IXGBE_VT_MSGINFO_SHIFT 16 /* bits 23:16 are used for extra info for certain messages */ #define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h index 2a7ac8e25a..45c0f80ddd 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h @@ -90,6 +90,7 @@ #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) +#define STATIC static #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i) #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c index cd367bc8f8..023b655d35 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c @@ -139,7 +139,7 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) { u16 phy_id = 0; - bool valid = FALSE; + bool valid = false; DEBUGFUNC("ixgbe_validate_phy_addr"); @@ -148,7 +148,7 @@ bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); if (phy_id != 0xFFFF && phy_id != 0x0) - valid = TRUE; + valid = true; return valid; } @@ -474,7 +474,7 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) u32 time_out; u32 max_time_out = 10; u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; - bool autoneg = FALSE; + bool autoneg = false; ixgbe_link_speed speed; DEBUGFUNC("ixgbe_setup_phy_link_generic"); @@ -564,7 +564,7 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled + * @autoneg: true if autonegotiation enabled **/ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, ixgbe_link_speed speed, @@ -614,7 +614,7 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); *speed = 0; - *autoneg = TRUE; + *autoneg = true; status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, IXGBE_MDIO_PMA_PMD_DEV_TYPE, @@ -652,7 +652,7 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, DEBUGFUNC("ixgbe_check_phy_link_tnx"); /* Initialize speed and link to default case */ - *link_up = FALSE; + *link_up = false; *speed = IXGBE_LINK_SPEED_10GB_FULL; /* @@ -666,12 +666,11 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); - phy_link = phy_data & - IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; + phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; phy_speed = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { - *link_up = TRUE; + *link_up = true; if (phy_speed == IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) *speed = IXGBE_LINK_SPEED_1GB_FULL; @@ -694,7 +693,7 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) u32 time_out; u32 max_time_out = 10; u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; - bool autoneg = FALSE; + bool autoneg = false; ixgbe_link_speed speed; DEBUGFUNC("ixgbe_setup_phy_link_tnx"); @@ -822,7 +821,7 @@ s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) { u16 phy_offset, control, eword, edata, block_crc; - bool end_data = FALSE; + bool end_data = false; u16 list_offset, data_offset; u16 phy_data = 0; s32 ret_val = IXGBE_SUCCESS; @@ -875,7 +874,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) msec_delay(edata); break; case IXGBE_DATA_NL: - DEBUGOUT("DATA: \n"); + DEBUGOUT("DATA:\n"); data_offset++; hw->eeprom.ops.read(hw, data_offset++, &phy_offset); @@ -891,10 +890,10 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) break; case IXGBE_CONTROL_NL: data_offset++; - DEBUGOUT("CONTROL: \n"); + DEBUGOUT("CONTROL:\n"); if (edata == IXGBE_CONTROL_EOL_NL) { DEBUGOUT("EOL\n"); - end_data = TRUE; + end_data = true; } else if (edata == IXGBE_CONTROL_SOL_NL) { DEBUGOUT("SOL\n"); } else { @@ -1052,15 +1051,15 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) } if (hw->phy.sfp_type != stored_sfp_type) - hw->phy.sfp_setup_needed = TRUE; + hw->phy.sfp_setup_needed = true; /* Determine if the SFP+ PHY is dual speed or not. */ - hw->phy.multispeed_fiber = FALSE; + hw->phy.multispeed_fiber = false; if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) - hw->phy.multispeed_fiber = TRUE; + hw->phy.multispeed_fiber = true; /* Determine PHY vendor */ if (hw->phy.type != ixgbe_phy_nl) { @@ -1159,7 +1158,8 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) status = IXGBE_SUCCESS; } else { DEBUGOUT("SFP+ module not supported\n"); - hw->phy.type = ixgbe_phy_sfp_unsupported; + hw->phy.type = + ixgbe_phy_sfp_unsupported; status = IXGBE_ERR_SFP_NOT_SUPPORTED; } } else { @@ -1179,6 +1179,8 @@ err_read_i2c_eeprom: return IXGBE_ERR_SFP_NOT_PRESENT; } + + /** * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence * @hw: pointer to hardware structure @@ -1814,7 +1816,7 @@ void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) } /** - * ixgbe_tn_check_overtemp - Checks if an overtemp occured. + * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. * @hw: pointer to hardware structure * * Checks if the LASI temp alarm status was triggered due to overtemp diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h index c46f8c1cd4..56e1b11366 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h @@ -205,8 +205,8 @@ POSSIBILITY OF SUCH DAMAGE. (0x0D00C + ((_i - 64) * 0x40)))) #define IXGBE_RDRXCTL 0x02F00 #define IXGBE_RDRXCTL_RSC_PUSH 0x80 +/* 8 of these 0x03C00 - 0x03C1C */ #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) - /* 8 of these 0x03C00 - 0x03C1C */ #define IXGBE_RXCTRL 0x03000 #define IXGBE_DROPEN 0x03D04 #define IXGBE_RXPBSIZE_SHIFT 10 @@ -251,7 +251,8 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ #define IXGBE_VT_CTL 0x051B0 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ -#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */ +/* 64 Mailboxes, 16 DW each */ +#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) @@ -303,7 +304,7 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_FDIRCMD 0x0EE2C /* Transmit DMA registers */ -#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ +#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) @@ -334,7 +335,8 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 #define IXGBE_SPOOF_VLANAS_SHIFT 8 #define IXGBE_PFVFSPOOF_REG_COUNT 8 -#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ +/* 16 of these (0-15) */ +#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* Tx DCA Control register : 128 of these (0-127) */ #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) #define IXGBE_TIPG 0x0CB00 @@ -354,8 +356,8 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_WUPL 0x05900 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ -#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host - * Filter Table */ +/* Ext Flexible Host Filter Table */ +#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 @@ -390,7 +392,8 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ -#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ +/* Mask for Ext. flex filters */ +#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ @@ -566,12 +569,13 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_RTTBCNRTT 0x05150 #define IXGBE_RTTBCNRD 0x0498C + /* FCoE DMA Context Registers */ #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ -#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ +#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0*/ #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ @@ -696,7 +700,7 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ -#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ +#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ @@ -746,8 +750,7 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_BMCIP_IPADDR_VALID 0x00000002 /* Management Bit Fields and Masks */ -#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Enable BMC2OS and OS2BMC - * traffic */ +#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ #define IXGBE_MANC_EN_BMC2OS_SHIFT 28 /* Firmware Semaphore Register */ @@ -1004,21 +1007,22 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_RSCCTL_MAXDESC_4 0x04 #define IXGBE_RSCCTL_MAXDESC_8 0x08 #define IXGBE_RSCCTL_MAXDESC_16 0x0C +#define IXGBE_RSCCTL_TS_DIS 0x02 /* RSCDBU Bit Masks */ #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 /* RDRXCTL Bit Masks */ -#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ +#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ #define IXGBE_RDRXCTL_MVMEN 0x00000020 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ -#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ -#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ -#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ +#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ +#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ +#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ /* RQTC Bit Masks and Shifts */ #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) @@ -1064,12 +1068,12 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ -#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ -#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ -#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ -#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ -#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */ -#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */ +#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ +#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ +#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ +#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ +#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ +#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ @@ -1079,24 +1083,24 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ /* MSCA Bit Masks */ -#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ +#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ #define IXGBE_MSCA_NP_ADDR_SHIFT 0 -#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ -#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ +#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ +#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ -#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ -#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */ -#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/ +#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ +#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ +#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ -#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ -#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ +#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ +#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ -#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ +#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ /* MSRWD bit masks */ #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF @@ -1130,10 +1134,10 @@ POSSIBILITY OF SUCH DAMAGE. #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ -#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ +#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ -#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ +#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 @@ -1354,10 +1358,11 @@ enum { #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ /* RMCS Bit Masks */ -#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ +#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ #define IXGBE_RMCS_RAC 0x00000004 -#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ +/* Deficit Fixed Prio ena */ +#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ @@ -1463,7 +1468,7 @@ enum { #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ -#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ +#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ @@ -1556,7 +1561,7 @@ enum { /* STATUS Bit Masks */ #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ -#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ +#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ @@ -1802,17 +1807,17 @@ enum { #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ -#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ -#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ +#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ +#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ #define IXGBE_ETH_LENGTH_OF_ADDRESS 6 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 -#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */ -#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */ +#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* words rd in burst */ +#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS -#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ +#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ #endif /* Number of 5 microseconds we wait for EERD read and @@ -1842,13 +1847,13 @@ enum { #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ -#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ -#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ -#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ -#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ -#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ -#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ -#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ +#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ +#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ +#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ +#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ +#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ +#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ +#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ @@ -1908,8 +1913,8 @@ enum { #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 /* Transmit Config masks */ -#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ -#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ +#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ +#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ /* Enable short packet padding to 64 bytes */ #define IXGBE_TX_PAD_ENABLE 0x00000400 @@ -1922,10 +1927,10 @@ enum { /* Receive Config masks */ #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ -#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ -#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ -#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ -#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ +#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ +#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ +#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ +#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ #define IXGBE_RXDCTL_RLPML_EN 0x00008000 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ @@ -2009,7 +2014,7 @@ enum { #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ -#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ +#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ @@ -2421,13 +2426,13 @@ struct ixgbe_adv_tx_context_desc { #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ -#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ -#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ +#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ +#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ -#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ +#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ @@ -2443,7 +2448,8 @@ struct ixgbe_adv_tx_context_desc { #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ -#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ +/* 1st&Last TSO-full iSCSI PDU */ +#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ @@ -2453,7 +2459,7 @@ struct ixgbe_adv_tx_context_desc { #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ -#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ +#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ @@ -2461,8 +2467,8 @@ struct ixgbe_adv_tx_context_desc { #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ -#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ -#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ +#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ +#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ @@ -2484,7 +2490,6 @@ typedef u32 ixgbe_link_speed; IXGBE_LINK_SPEED_1GB_FULL | \ IXGBE_LINK_SPEED_10GB_FULL) - /* Physical layer type */ typedef u32 ixgbe_physical_layer; #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c index 31c417dbf8..2ee27e6393 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c @@ -121,7 +121,7 @@ s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw) s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw) { /* Clear adapter stopped flag */ - hw->adapter_stopped = FALSE; + hw->adapter_stopped = false; return IXGBE_SUCCESS; } @@ -226,7 +226,7 @@ s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw) * Set the adapter_stopped flag so other driver functions stop touching * the hardware */ - hw->adapter_stopped = TRUE; + hw->adapter_stopped = true; /* Clear interrupt mask to stop from interrupts being generated */ IXGBE_VFWRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); @@ -460,8 +460,7 @@ s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr) msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; if (!ret_val) - if (msgbuf[0] == - (IXGBE_VF_SET_MACVLAN | IXGBE_VT_MSGTYPE_NACK)) + if (msgbuf[0] == (IXGBE_VF_SET_MACVLAN | IXGBE_VT_MSGTYPE_NACK)) ret_val = IXGBE_ERR_OUT_OF_MEM; return ret_val; @@ -471,8 +470,8 @@ s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr) * ixgbe_setup_mac_link_vf - Setup MAC link settings * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Set the link speed in the AUTOC register and restarts link. **/ @@ -488,8 +487,8 @@ s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, * ixgbe_check_mac_link_vf - Get link/speed status * @hw: pointer to hardware structure * @speed: pointer to link speed - * @link_up: TRUE is link is up, FALSE otherwise - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @link_up: true is link is up, false otherwise + * @autoneg_wait_to_complete: true when waiting for completion is needed * * Reads the links register to determine if link is up and the current speed **/ @@ -500,7 +499,7 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed, UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); if (!(hw->mbx.ops.check_for_rst(hw, 0))) { - *link_up = FALSE; + *link_up = false; *speed = 0; return -1; } diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c index 45de9e1daa..5daefa0ae3 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c @@ -63,10 +63,10 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw); s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); -static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); -static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); -static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); +STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); +STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); +STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); +STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); /** * ixgbe_init_ops_X540 - Inits func ptrs and MAC type @@ -131,11 +131,13 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; /* Link */ - mac->ops.get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic; + mac->ops.get_link_capabilities = + &ixgbe_get_copper_link_capabilities_generic; mac->ops.setup_link = &ixgbe_setup_mac_link_X540; mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; mac->ops.check_link = &ixgbe_check_mac_link_generic; + mac->mcft_size = 128; mac->vft_size = 128; mac->num_rar_entries = 128; @@ -150,7 +152,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) * enabled. */ mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & - IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; + IXGBE_FWSM_MODE_MASK) ? true : false; hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; @@ -168,15 +170,15 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) * ixgbe_get_link_capabilities_X540 - Determines link capabilities * @hw: pointer to hardware structure * @speed: pointer to link speed - * @negotiation: TRUE when autoneg or autotry is enabled + * @autoneg: true when autoneg or autotry is enabled * * Determines the link capabilities by reading the AUTOC register. **/ s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, ixgbe_link_speed *speed, - bool *negotiation) + bool *autoneg) { - ixgbe_get_copper_link_capabilities_generic(hw, speed, negotiation); + ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); return IXGBE_SUCCESS; } @@ -197,8 +199,8 @@ enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed **/ s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg, @@ -526,7 +528,7 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) pointer >= hw->eeprom.word_size) continue; - if (ixgbe_read_eerd_generic(hw, pointer, &length)!= + if (ixgbe_read_eerd_generic(hw, pointer, &length) != IXGBE_SUCCESS) { DEBUGOUT("EEPROM read failed\n"); break; @@ -665,7 +667,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy * EEPROM from shadow RAM to the flash device. **/ -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) +STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) { u32 flup; s32 status = IXGBE_ERR_EEPROM; @@ -712,7 +714,7 @@ out: * Polls the FLUDONE (bit 26) of the EEC Register to determine when the * flash update is done. **/ -static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) +STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) { u32 i; u32 reg; @@ -777,9 +779,9 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) goto out; } else { /* - * Firmware currently using resource (fwmask), hardware currently - * using resource (hwmask), or other software thread currently - * using resource (swmask) + * Firmware currently using resource (fwmask), hardware + * currently using resource (hwmask), or other software + * thread currently using resource (swmask) */ ixgbe_release_swfw_sync_semaphore(hw); msec_delay(5); @@ -798,7 +800,7 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) * bits in the SW_FW_SYNC register. */ swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); - if (swfw_sync & (fwmask| hwmask)) { + if (swfw_sync & (fwmask | hwmask)) { if (ixgbe_get_swfw_sync_semaphore(hw)) { ret_val = IXGBE_ERR_SWFW_SYNC; goto out; @@ -819,7 +821,7 @@ out: * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to release * - * Releases the SWFW semaphore throught the SW_FW_SYNC register + * Releases the SWFW semaphore through the SW_FW_SYNC register * for the specified function (CSR, PHY0, PHY1, EVM, Flash) **/ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) @@ -845,7 +847,7 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) * * Sets the hardware semaphores so SW/FW can gain control of shared resources **/ -static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) +STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) { s32 status = IXGBE_ERR_EEPROM; u32 timeout = 2000; @@ -883,7 +885,8 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) * was not granted because we don't have access to the EEPROM */ if (i >= timeout) { - DEBUGOUT("REGSMP Software NVM semaphore not granted.\n"); + DEBUGOUT("REGSMP Software NVM semaphore not " + "granted.\n"); ixgbe_release_swfw_sync_semaphore(hw); status = IXGBE_ERR_EEPROM; } @@ -901,7 +904,7 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) * * This function clears hardware semaphore bits. **/ -static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) +STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) { u32 swsm; -- 2.20.1