From a08f9cb698c3d4687765860e328dca727f7a516b Mon Sep 17 00:00:00 2001 From: Ke Zhang Date: Fri, 20 May 2022 03:00:23 +0000 Subject: [PATCH] net/iavf: fix Rx queue interrupt setting For Rx-Queue Interrupt Setting, when VF Rx interrupt disable (INTENA=0), there are two ways to write back descriptor to host memory: 1) Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register: Completed descriptors are posted to host memory according to the internal descriptor cache policy (in other words when a full cache line is available for write-back). A internal descriptor size is 16 bytes or 32 bytes, a cache line size is 64 bytes or 128 bytes from datasheet : PCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO) so the full cache line could contains 4 packets, it means Network card will send 4 packets to host when a full cache line is available. 2) Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register: Completed descriptors also trigger the ITR. Following ITR expiration, all leftover completed descriptors are posted to host memory. Network card will send packet to host even if only one descriptor is completed. Changing 1) to 2) to make sure VF send the packet to host even if there is only one Rx packet is ready in hardware. Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt") Cc: stable@dpdk.org Signed-off-by: Ke Zhang Acked-by: Qi Zhang --- drivers/net/iavf/iavf_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index 315ab15aad..a74056f0f1 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -1925,7 +1925,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START), - 0); + IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK); IAVF_WRITE_FLUSH(hw); return 0; -- 2.39.5