From aa08f3eb4ecf0997fd30ac073fcd895db71ef8e3 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Wed, 22 Jun 2022 14:56:09 +0800 Subject: [PATCH] net/txgbe: fix register polling Fix to poll some specific registers, which expect bit value 0. 'w32w' is used in registers where the write command bit is set and waits for the bit clear to complete the write. Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3139796911..911bb6e04e 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, } do { - all |= rd32(hw, reg); - value |= mask & all; + if (expect != 0) { + all |= rd32(hw, reg); + value |= mask & all; + } else { + all = rd32(hw, reg); + value = mask & all; + } if (value == expect) break; @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, #define wr32w(hw, reg, val, mask, slice) do { \ wr32((hw), reg, val); \ - po32m((hw), reg, mask, mask, NULL, 5, slice); \ + po32m((hw), reg, mask, 0, NULL, 5, slice); \ } while (0) #define TXGBE_XPCS_IDAADDR 0x13000 -- 2.39.5