From bdf5276fc94cf2d6a274a79d3bacafcaf658cbee Mon Sep 17 00:00:00 2001 From: Andrew Jackson Date: Thu, 16 Nov 2017 08:03:49 +0000 Subject: [PATCH] net/sfc/base: copy new header from firmware src Signed-off-by: Andrew Jackson Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/siena_flash.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/sfc/base/siena_flash.h b/drivers/net/sfc/base/siena_flash.h index e270055448..5fa3ea4458 100644 --- a/drivers/net/sfc/base/siena_flash.h +++ b/drivers/net/sfc/base/siena_flash.h @@ -113,15 +113,21 @@ typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_word_t checksum; /* of whole header area + firmware image */ efx_word_t firmware_version_d; efx_byte_t mcfw_subtype; - efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */ + efx_byte_t generation; /* MC (Medford and later): MC partition generation when */ + /* written to NVRAM. */ + /* MUM & SUC images: subtype. */ + /* (Otherwise set to 0) */ efx_dword_t firmware_text_offset; /* offset to firmware .text */ efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ efx_dword_t firmware_data_offset; /* offset to firmware .data */ efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ - efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */ - efx_dword_t reserved_c[7]; /* (set to 0) */ + efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */ + /* the key, or 0xffff if unsigned. (Otherwise set to 0) */ + efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */ + efx_byte_t reserved_b[3]; /* (set to 0) */ + efx_dword_t reserved_c[6]; /* (set to 0) */ } siena_mc_boot_hdr_t; #define SIENA_MC_BOOT_HDR_PADDING \ -- 2.20.1