From c2c1ccaec206b498252817895f07fe27dabf5add Mon Sep 17 00:00:00 2001 From: Arek Kusztal Date: Mon, 28 Jun 2021 17:34:27 +0100 Subject: [PATCH] crypto/qat: add Chacha-Poly in UCS-SPC mode This commit adds Chacha20-Poly1305 aglorithm that works in UCS (Unified crypto slice) SPC(Single-Pass) mode. Signed-off-by: Arek Kusztal Acked-by: Fan Zhang Acked-by: Akhil Goyal --- drivers/crypto/qat/qat_sym_capabilities.h | 32 ++++++++++++++++++++++- drivers/crypto/qat/qat_sym_session.c | 2 ++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h index fc8e667687..5c6e723466 100644 --- a/drivers/crypto/qat/qat_sym_capabilities.h +++ b/drivers/crypto/qat/qat_sym_capabilities.h @@ -1144,7 +1144,37 @@ }, \ }, } \ }, } \ - } \ + }, \ + { /* Chacha20-Poly1305 */ \ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ + {.sym = { \ + .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, \ + {.aead = { \ + .algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305, \ + .block_size = 64, \ + .key_size = { \ + .min = 32, \ + .max = 32, \ + .increment = 0 \ + }, \ + .digest_size = { \ + .min = 16, \ + .max = 16, \ + .increment = 0 \ + }, \ + .aad_size = { \ + .min = 0, \ + .max = 240, \ + .increment = 1 \ + }, \ + .iv_size = { \ + .min = 12, \ + .max = 12, \ + .increment = 0 \ + }, \ + }, } \ + }, } \ + } diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 04bc2d7e68..6b87fc0dfb 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -922,6 +922,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, case RTE_CRYPTO_AEAD_CHACHA20_POLY1305: if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ) return -EINVAL; + if (qat_dev_gen == QAT_GEN4) + session->is_ucs = 1; session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305; qat_sym_session_handle_single_pass(session, -- 2.20.1