From c344eab3eecb71203681e6c5c5b64aefb2d7ad94 Mon Sep 17 00:00:00 2001 From: Ferruh Yigit Date: Thu, 28 Jan 2016 12:20:23 +0000 Subject: [PATCH] eal: move cpu flags out of headers Move cpu_feature_table array from arch specific rte_cpuflags.h files to new arch specific rte_cpuflags.c files. Main motivation is to escape from static variable declarations in header files. cpu_feature_table has many copies in final binary, even exist in some object files that does not use this variable at all. And this can be a sample to create architecture specific source files and move some functions which are not performance sensitive from architecture header files to source files. Signed-off-by: Ferruh Yigit --- lib/librte_eal/bsdapp/eal/Makefile | 6 + lib/librte_eal/bsdapp/eal/rte_eal_version.map | 7 + lib/librte_eal/common/arch/arm/rte_cpuflags.c | 79 +++++++++++ .../common/arch/ppc_64/rte_cpuflags.c | 70 ++++++++++ .../common/arch/tile/rte_cpuflags.c | 36 +++++ lib/librte_eal/common/arch/x86/rte_cpuflags.c | 129 ++++++++++++++++++ lib/librte_eal/common/eal_common_cpuflags.c | 2 +- .../common/include/arch/arm/rte_cpuflags_32.h | 35 +---- .../common/include/arch/arm/rte_cpuflags_64.h | 16 +-- .../common/include/arch/ppc_64/rte_cpuflags.h | 41 +----- .../common/include/arch/tile/rte_cpuflags.h | 3 - .../common/include/arch/x86/rte_cpuflags.h | 99 +------------- lib/librte_eal/linuxapp/eal/Makefile | 6 + .../linuxapp/eal/rte_eal_version.map | 6 + 14 files changed, 352 insertions(+), 183 deletions(-) create mode 100644 lib/librte_eal/common/arch/arm/rte_cpuflags.c create mode 100644 lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c create mode 100644 lib/librte_eal/common/arch/tile/rte_cpuflags.c create mode 100644 lib/librte_eal/common/arch/x86/rte_cpuflags.c diff --git a/lib/librte_eal/bsdapp/eal/Makefile b/lib/librte_eal/bsdapp/eal/Makefile index 65b293f830..d7ca60b92b 100644 --- a/lib/librte_eal/bsdapp/eal/Makefile +++ b/lib/librte_eal/bsdapp/eal/Makefile @@ -33,7 +33,9 @@ include $(RTE_SDK)/mk/rte.vars.mk LIB = librte_eal.a +ARCH_DIR ?= $(RTE_ARCH) VPATH += $(RTE_SDK)/lib/librte_eal/common +VPATH += $(RTE_SDK)/lib/librte_eal/common/arch/$(ARCH_DIR) CFLAGS += -I$(SRCDIR)/include CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common @@ -82,6 +84,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += malloc_elem.c SRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += malloc_heap.c SRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += rte_keepalive.c +# from arch dir +SRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += rte_cpuflags.c + CFLAGS_eal.o := -D_GNU_SOURCE #CFLAGS_eal_thread.o := -D_GNU_SOURCE CFLAGS_eal_log.o := -D_GNU_SOURCE @@ -100,5 +105,6 @@ SYMLINK-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP)-include/exec-env := \ $(addprefix include/exec-env/,$(INC)) DEPDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += lib/librte_eal/common +DEPDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += lib/librte_eal/common/arch/$(ARCH_DIR) include $(RTE_SDK)/mk/rte.lib.mk diff --git a/lib/librte_eal/bsdapp/eal/rte_eal_version.map b/lib/librte_eal/bsdapp/eal/rte_eal_version.map index 9d7adf1c2a..6fa9c67352 100644 --- a/lib/librte_eal/bsdapp/eal/rte_eal_version.map +++ b/lib/librte_eal/bsdapp/eal/rte_eal_version.map @@ -135,3 +135,10 @@ DPDK_2.2 { rte_xen_dom0_supported; } DPDK_2.1; + +DPDK_2.3 { + global: + + rte_cpu_feature_table; + +} DPDK_2.2; diff --git a/lib/librte_eal/common/arch/arm/rte_cpuflags.c b/lib/librte_eal/common/arch/arm/rte_cpuflags.c new file mode 100644 index 0000000000..4348574093 --- /dev/null +++ b/lib/librte_eal/common/arch/arm/rte_cpuflags.c @@ -0,0 +1,79 @@ +/* + * BSD LICENSE + * + * Copyright (C) Cavium networks Ltd. 2015. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium networks nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "rte_cpuflags.h" + +#ifdef RTE_ARCH_64 +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP, 0) + FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 1) + FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 2) + FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP, 3) + FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP, 4) + FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP, 5) + FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP, 6) + FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP, 7) + FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1) +}; +#else +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0) + FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1) + FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2) + FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3) + FEAT_DEF(FAST_MULT, 0x00000001, 0, REG_HWCAP, 4) + FEAT_DEF(FPA, 0x00000001, 0, REG_HWCAP, 5) + FEAT_DEF(VFP, 0x00000001, 0, REG_HWCAP, 6) + FEAT_DEF(EDSP, 0x00000001, 0, REG_HWCAP, 7) + FEAT_DEF(JAVA, 0x00000001, 0, REG_HWCAP, 8) + FEAT_DEF(IWMMXT, 0x00000001, 0, REG_HWCAP, 9) + FEAT_DEF(CRUNCH, 0x00000001, 0, REG_HWCAP, 10) + FEAT_DEF(THUMBEE, 0x00000001, 0, REG_HWCAP, 11) + FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 12) + FEAT_DEF(VFPv3, 0x00000001, 0, REG_HWCAP, 13) + FEAT_DEF(VFPv3D16, 0x00000001, 0, REG_HWCAP, 14) + FEAT_DEF(TLS, 0x00000001, 0, REG_HWCAP, 15) + FEAT_DEF(VFPv4, 0x00000001, 0, REG_HWCAP, 16) + FEAT_DEF(IDIVA, 0x00000001, 0, REG_HWCAP, 17) + FEAT_DEF(IDIVT, 0x00000001, 0, REG_HWCAP, 18) + FEAT_DEF(VFPD32, 0x00000001, 0, REG_HWCAP, 19) + FEAT_DEF(LPAE, 0x00000001, 0, REG_HWCAP, 20) + FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 21) + FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP2, 0) + FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP2, 1) + FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2) + FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3) + FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4) + FEAT_DEF(V7L, 0x00000001, 0, REG_PLATFORM, 0) +}; +#endif + diff --git a/lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c b/lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c new file mode 100644 index 0000000000..7f4e6dd10b --- /dev/null +++ b/lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c @@ -0,0 +1,70 @@ +/* + * BSD LICENSE + * + * Copyright (C) IBM Corporation 2014. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of IBM Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "rte_cpuflags.h" + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0) + FEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1) + FEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6) + FEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7) + FEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8) + FEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9) + FEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10) + FEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11) + FEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12) + FEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13) + FEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14) + FEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15) + FEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16) + FEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17) + FEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18) + FEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19) + FEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20) + FEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21) + FEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22) + FEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23) + FEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24) + FEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25) + FEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26) + FEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27) + FEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28) + FEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29) + FEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30) + FEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31) + FEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26) + FEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27) + FEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28) + FEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29) + FEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30) + FEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31) +}; diff --git a/lib/librte_eal/common/arch/tile/rte_cpuflags.c b/lib/librte_eal/common/arch/tile/rte_cpuflags.c new file mode 100644 index 0000000000..4ca0a7b936 --- /dev/null +++ b/lib/librte_eal/common/arch/tile/rte_cpuflags.c @@ -0,0 +1,36 @@ +/* + * BSD LICENSE + * + * Copyright (C) EZchip Semiconductor Ltd. 2015. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of EZchip Semiconductor nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "rte_cpuflags.h" + +const struct feature_entry rte_cpu_feature_table[] = { +}; diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c new file mode 100644 index 0000000000..22dc57213f --- /dev/null +++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c @@ -0,0 +1,129 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "rte_cpuflags.h" + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0) + FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1) + FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2) + FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3) + FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4) + FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5) + FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6) + FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7) + FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8) + FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9) + FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10) + FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12) + FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13) + FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14) + FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15) + FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17) + FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18) + FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19) + FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20) + FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21) + FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22) + FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23) + FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24) + FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25) + FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26) + FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27) + FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28) + FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29) + FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30) + + FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0) + FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1) + FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2) + FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3) + FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4) + FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5) + FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6) + FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7) + FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8) + FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9) + FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11) + FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12) + FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13) + FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14) + FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15) + FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16) + FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17) + FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18) + FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19) + FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21) + FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22) + FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23) + FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24) + FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25) + FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26) + FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27) + FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28) + FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29) + FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31) + + FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0) + FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1) + FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2) + FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4) + FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5) + FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6) + + FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0) + FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1) + FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3) + + FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0) + FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2) + FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4) + FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5) + FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6) + FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7) + FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) + FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) + FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) + FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) + + FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) + FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) + + FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11) + FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20) + FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26) + FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27) + FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) + + FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) +}; diff --git a/lib/librte_eal/common/eal_common_cpuflags.c b/lib/librte_eal/common/eal_common_cpuflags.c index 8ba7b30e0c..9ba9b1e70d 100644 --- a/lib/librte_eal/common/eal_common_cpuflags.c +++ b/lib/librte_eal/common/eal_common_cpuflags.c @@ -79,7 +79,7 @@ rte_cpu_check_supported(void) fprintf(stderr, "ERROR: This system does not support \"%s\".\n" "Please check that RTE_MACHINE is set correctly.\n", - cpu_feature_table[compile_time_flags[i]].name); + rte_cpu_feature_table[compile_time_flags[i]].name); exit(1); } } diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h index 2106c41ba5..2ec0c2ec6f 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h @@ -45,6 +45,8 @@ extern "C" { #include "generic/rte_cpuflags.h" +extern const struct feature_entry rte_cpu_feature_table[]; + #ifndef AT_HWCAP #define AT_HWCAP 16 #endif @@ -100,37 +102,6 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ }; -static const struct feature_entry cpu_feature_table[] = { - FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0) - FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1) - FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2) - FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3) - FEAT_DEF(FAST_MULT, 0x00000001, 0, REG_HWCAP, 4) - FEAT_DEF(FPA, 0x00000001, 0, REG_HWCAP, 5) - FEAT_DEF(VFP, 0x00000001, 0, REG_HWCAP, 6) - FEAT_DEF(EDSP, 0x00000001, 0, REG_HWCAP, 7) - FEAT_DEF(JAVA, 0x00000001, 0, REG_HWCAP, 8) - FEAT_DEF(IWMMXT, 0x00000001, 0, REG_HWCAP, 9) - FEAT_DEF(CRUNCH, 0x00000001, 0, REG_HWCAP, 10) - FEAT_DEF(THUMBEE, 0x00000001, 0, REG_HWCAP, 11) - FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 12) - FEAT_DEF(VFPv3, 0x00000001, 0, REG_HWCAP, 13) - FEAT_DEF(VFPv3D16, 0x00000001, 0, REG_HWCAP, 14) - FEAT_DEF(TLS, 0x00000001, 0, REG_HWCAP, 15) - FEAT_DEF(VFPv4, 0x00000001, 0, REG_HWCAP, 16) - FEAT_DEF(IDIVA, 0x00000001, 0, REG_HWCAP, 17) - FEAT_DEF(IDIVT, 0x00000001, 0, REG_HWCAP, 18) - FEAT_DEF(VFPD32, 0x00000001, 0, REG_HWCAP, 19) - FEAT_DEF(LPAE, 0x00000001, 0, REG_HWCAP, 20) - FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 21) - FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP2, 0) - FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP2, 1) - FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2) - FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3) - FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4) - FEAT_DEF(V7L, 0x00000001, 0, REG_PLATFORM, 0) -}; - /* * Read AUXV software register and get cpu features for ARM */ @@ -169,7 +140,7 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) /* Flag does not match anything in the feature tables */ return -ENOENT; - feat = &cpu_feature_table[feature]; + feat = &rte_cpu_feature_table[feature]; if (!feat->leaf) /* This entry in the table wasn't filled out! */ diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_64.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_64.h index 7bcc12fd1c..b36040b2c0 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_64.h @@ -45,6 +45,8 @@ extern "C" { #include "generic/rte_cpuflags.h" +extern const struct feature_entry rte_cpu_feature_table[]; + #ifndef AT_HWCAP #define AT_HWCAP 16 #endif @@ -81,18 +83,6 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ }; -static const struct feature_entry cpu_feature_table[] = { - FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP, 0) - FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 1) - FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 2) - FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP, 3) - FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP, 4) - FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP, 5) - FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP, 6) - FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP, 7) - FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1) -}; - /* * Read AUXV software register and get cpu features for ARM */ @@ -132,7 +122,7 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) /* Flag does not match anything in the feature tables */ return -ENOENT; - feat = &cpu_feature_table[feature]; + feat = &rte_cpu_feature_table[feature]; if (!feat->leaf) /* This entry in the table wasn't filled out! */ diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h b/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h index df45047037..85c4c1a98a 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h @@ -44,6 +44,8 @@ extern "C" { #include "generic/rte_cpuflags.h" +extern const struct feature_entry rte_cpu_feature_table[]; + /* Symbolic values for the entries in the auxiliary table */ #define AT_HWCAP 16 #define AT_HWCAP2 26 @@ -96,43 +98,6 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ }; -static const struct feature_entry cpu_feature_table[] = { - FEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0) - FEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1) - FEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6) - FEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7) - FEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8) - FEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9) - FEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10) - FEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11) - FEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12) - FEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13) - FEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14) - FEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15) - FEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16) - FEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17) - FEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18) - FEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19) - FEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20) - FEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21) - FEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22) - FEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23) - FEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24) - FEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25) - FEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26) - FEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27) - FEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28) - FEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29) - FEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30) - FEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31) - FEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26) - FEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27) - FEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28) - FEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29) - FEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30) - FEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31) -}; - /* * Read AUXV software register and get cpu features for Power */ @@ -167,7 +132,7 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) /* Flag does not match anything in the feature tables */ return -ENOENT; - feat = &cpu_feature_table[feature]; + feat = &rte_cpu_feature_table[feature]; if (!feat->leaf) /* This entry in the table wasn't filled out! */ diff --git a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h index 08aa957021..a415857c7e 100644 --- a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h +++ b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h @@ -56,9 +56,6 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */ }; -static const struct feature_entry cpu_feature_table[] = { -}; - /* * Read AUXV software register and get cpu features for Power */ diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h index 89c0d9d4c9..120ea24be3 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h @@ -45,6 +45,8 @@ extern "C" { #include "generic/rte_cpuflags.h" +extern const struct feature_entry rte_cpu_feature_table[]; + enum rte_cpu_flag_t { /* (EAX 01h) ECX features*/ RTE_CPUFLAG_SSE3 = 0, /**< SSE3 */ @@ -158,101 +160,6 @@ enum cpu_register_t { RTE_REG_EDX, }; -static const struct feature_entry cpu_feature_table[] = { - FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0) - FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1) - FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2) - FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3) - FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4) - FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5) - FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6) - FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7) - FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8) - FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9) - FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10) - FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12) - FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13) - FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14) - FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15) - FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17) - FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18) - FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19) - FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20) - FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21) - FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22) - FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23) - FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24) - FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25) - FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26) - FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27) - FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28) - FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29) - FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30) - - FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0) - FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1) - FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2) - FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3) - FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4) - FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5) - FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6) - FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7) - FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8) - FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9) - FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11) - FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12) - FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13) - FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14) - FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15) - FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16) - FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17) - FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18) - FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19) - FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21) - FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22) - FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23) - FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24) - FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25) - FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26) - FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27) - FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28) - FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29) - FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31) - - FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0) - FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1) - FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2) - FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4) - FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5) - FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6) - - FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0) - FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1) - FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3) - - FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0) - FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2) - FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4) - FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5) - FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6) - FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7) - FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) - FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) - FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) - FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) - - FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) - FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) - - FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11) - FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20) - FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26) - FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27) - FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) - - FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) -}; - static inline void rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out) { @@ -287,7 +194,7 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) /* Flag does not match anything in the feature tables */ return -ENOENT; - feat = &cpu_feature_table[feature]; + feat = &rte_cpu_feature_table[feature]; if (!feat->leaf) /* This entry in the table wasn't filled out! */ diff --git a/lib/librte_eal/linuxapp/eal/Makefile b/lib/librte_eal/linuxapp/eal/Makefile index 26eced5435..6e262505cf 100644 --- a/lib/librte_eal/linuxapp/eal/Makefile +++ b/lib/librte_eal/linuxapp/eal/Makefile @@ -33,7 +33,9 @@ include $(RTE_SDK)/mk/rte.vars.mk LIB = librte_eal.a +ARCH_DIR ?= $(RTE_ARCH) EXPORT_MAP := rte_eal_version.map +VPATH += $(RTE_SDK)/lib/librte_eal/common/arch/$(ARCH_DIR) LIBABIVER := 2 @@ -92,6 +94,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += malloc_elem.c SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += malloc_heap.c SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += rte_keepalive.c +# from arch dir +SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += rte_cpuflags.c + CFLAGS_eal.o := -D_GNU_SOURCE CFLAGS_eal_interrupts.o := -D_GNU_SOURCE CFLAGS_eal_pci_vfio_mp_sync.o := -D_GNU_SOURCE @@ -121,5 +126,6 @@ SYMLINK-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP)-include/exec-env := \ $(addprefix include/exec-env/,$(INC)) DEPDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += lib/librte_eal/common +DEPDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += lib/librte_eal/common/arch/$(ARCH_DIR) include $(RTE_SDK)/mk/rte.lib.mk diff --git a/lib/librte_eal/linuxapp/eal/rte_eal_version.map b/lib/librte_eal/linuxapp/eal/rte_eal_version.map index cbe175f402..aa4fcbd498 100644 --- a/lib/librte_eal/linuxapp/eal/rte_eal_version.map +++ b/lib/librte_eal/linuxapp/eal/rte_eal_version.map @@ -138,3 +138,9 @@ DPDK_2.2 { rte_xen_dom0_supported; } DPDK_2.1; + +DPDK_2.3 { + global: + + rte_cpu_feature_table; +} DPDK_2.2; -- 2.20.1