From d97108a3323147b22e7b0ac8c9eda9495b5be608 Mon Sep 17 00:00:00 2001 From: Yongseok Koh Date: Thu, 18 Apr 2019 04:49:01 -0700 Subject: [PATCH] config: change defaults of armv8 Current default cache line size for armv8 CPUs having Implementor ID of 0x41 is 128 bytes, changing it to 64 bytes. Also, the max number of lcores is changed to 16 from 256. Signed-off-by: Yongseok Koh Reviewed-by: Honnappa Nagarahalli --- config/arm/meson.build | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 431f03e561..7fa6ed3105 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -33,6 +33,11 @@ flags_generic = [ ['RTE_MAX_LCORE', 256], ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] +flags_arm = [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_MAX_LCORE', 16], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 64]] flags_cavium = [ ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], @@ -89,7 +94,7 @@ machine_args_cavium = [ ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] -impl_0x41 = ['Arm', flags_generic, machine_args_generic] +impl_0x41 = ['Arm', flags_arm, machine_args_generic] impl_0x42 = ['Broadcom', flags_generic, machine_args_generic] impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium] impl_0x44 = ['DEC', flags_generic, machine_args_generic] -- 2.20.1