From dcfbc594f7ddc3f934693549854b70d2d94cf8cf Mon Sep 17 00:00:00 2001 From: Wei Zhao Date: Thu, 18 Apr 2019 12:58:15 +0800 Subject: [PATCH] net/iavf: fix queue interrupt for ice Enable CLEARPBA bit is required by ice NIC of A0/A1 version to enable Tx and Rx queue interrupt. Also enable CLEARPBA bit does no impact on IAVF behaviour when be hosted by other devices, so we can make it as default. Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt") Cc: stable@dpdk.org Signed-off-by: Wei Zhao Acked-by: Qi Zhang --- drivers/net/iavf/iavf_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index 7825cbc85c..7a0696ed72 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -1014,11 +1014,13 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) PMD_DRV_LOG(INFO, "MISC is also enabled for control"); IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01, IAVFINT_DYN_CTL01_INTENA_MASK | + IAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTL01_ITR_INDX_MASK); } else { IAVF_WRITE_REG(hw, IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START), IAVFINT_DYN_CTLN1_INTENA_MASK | + IAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTLN1_ITR_INDX_MASK); } -- 2.20.1