From fa8f86a14e2e5991c2ff10f5db6dea33f8e355e5 Mon Sep 17 00:00:00 2001 From: Jerin Jacob Date: Tue, 6 Apr 2021 20:10:54 +0530 Subject: [PATCH] common/cnxk: add build infrastructre and HW definition Add meson build infrastructure along with HW definition header file. This patch also adds cross-compile configs for arm for CN9K series and CN10K series of Marvell SoC's. Signed-off-by: Jerin Jacob Signed-off-by: Nithin Dabilpuram Signed-off-by: Sunil Kumar Kori Signed-off-by: Pavan Nikhilesh Signed-off-by: Satha Rao Signed-off-by: Kiran Kumar K --- drivers/common/cnxk/hw/nix.h | 2191 ++++++++++++++++++++++++++++ drivers/common/cnxk/hw/npa.h | 376 +++++ drivers/common/cnxk/hw/npc.h | 525 +++++++ drivers/common/cnxk/hw/rvu.h | 222 +++ drivers/common/cnxk/hw/sdp.h | 182 +++ drivers/common/cnxk/hw/sso.h | 233 +++ drivers/common/cnxk/hw/ssow.h | 70 + drivers/common/cnxk/hw/tim.h | 49 + drivers/common/cnxk/meson.build | 14 + drivers/common/cnxk/roc_api.h | 69 + drivers/common/cnxk/roc_bitfield.h | 15 + drivers/common/cnxk/roc_bits.h | 32 + drivers/common/cnxk/roc_platform.c | 5 + drivers/common/cnxk/roc_platform.h | 154 ++ drivers/common/cnxk/version.map | 4 + drivers/meson.build | 1 + 16 files changed, 4142 insertions(+) create mode 100644 drivers/common/cnxk/hw/nix.h create mode 100644 drivers/common/cnxk/hw/npa.h create mode 100644 drivers/common/cnxk/hw/npc.h create mode 100644 drivers/common/cnxk/hw/rvu.h create mode 100644 drivers/common/cnxk/hw/sdp.h create mode 100644 drivers/common/cnxk/hw/sso.h create mode 100644 drivers/common/cnxk/hw/ssow.h create mode 100644 drivers/common/cnxk/hw/tim.h create mode 100644 drivers/common/cnxk/meson.build create mode 100644 drivers/common/cnxk/roc_api.h create mode 100644 drivers/common/cnxk/roc_bitfield.h create mode 100644 drivers/common/cnxk/roc_bits.h create mode 100644 drivers/common/cnxk/roc_platform.c create mode 100644 drivers/common/cnxk/roc_platform.h create mode 100644 drivers/common/cnxk/version.map diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h new file mode 100644 index 0000000000..6b86002ead --- /dev/null +++ b/drivers/common/cnxk/hw/nix.h @@ -0,0 +1,2191 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __NIX_HW_H__ +#define __NIX_HW_H__ + +/* Register offsets */ + +#define NIX_AF_CFG (0x0ull) +#define NIX_AF_STATUS (0x10ull) +#define NIX_AF_NDC_CFG (0x18ull) +#define NIX_AF_CONST (0x20ull) +#define NIX_AF_CONST1 (0x28ull) +#define NIX_AF_CONST2 (0x30ull) +#define NIX_AF_CONST3 (0x38ull) +#define NIX_AF_SQ_CONST (0x40ull) +#define NIX_AF_CQ_CONST (0x48ull) +#define NIX_AF_RQ_CONST (0x50ull) +#define NIX_AF_PL_CONST (0x58ull) /* [CN10K, .) */ +#define NIX_AF_PSE_CONST (0x60ull) +#define NIX_AF_TL1_CONST (0x70ull) +#define NIX_AF_TL2_CONST (0x78ull) +#define NIX_AF_TL3_CONST (0x80ull) +#define NIX_AF_TL4_CONST (0x88ull) +#define NIX_AF_MDQ_CONST (0x90ull) +#define NIX_AF_MC_MIRROR_CONST (0x98ull) +#define NIX_AF_LSO_CFG (0xa8ull) +#define NIX_AF_BLK_RST (0xb0ull) +#define NIX_AF_TX_TSTMP_CFG (0xc0ull) +#define NIX_AF_PL_TS (0xc8ull) /* [CN10K, .) */ +#define NIX_AF_RX_CFG (0xd0ull) +#define NIX_AF_AVG_DELAY (0xe0ull) +#define NIX_AF_CINT_DELAY (0xf0ull) +#define NIX_AF_VWQE_TIMER (0xf8ull) /* [CN10K, .) */ +#define NIX_AF_RX_MCAST_BASE (0x100ull) +#define NIX_AF_RX_MCAST_CFG (0x110ull) +#define NIX_AF_RX_MCAST_BUF_BASE (0x120ull) +#define NIX_AF_RX_MCAST_BUF_CFG (0x130ull) +#define NIX_AF_RX_MIRROR_BUF_BASE (0x140ull) +#define NIX_AF_RX_MIRROR_BUF_CFG (0x148ull) +#define NIX_AF_LF_RST (0x150ull) +#define NIX_AF_GEN_INT (0x160ull) +#define NIX_AF_GEN_INT_W1S (0x168ull) +#define NIX_AF_GEN_INT_ENA_W1S (0x170ull) +#define NIX_AF_GEN_INT_ENA_W1C (0x178ull) +#define NIX_AF_ERR_INT (0x180ull) +#define NIX_AF_ERR_INT_W1S (0x188ull) +#define NIX_AF_ERR_INT_ENA_W1S (0x190ull) +#define NIX_AF_ERR_INT_ENA_W1C (0x198ull) +#define NIX_AF_RAS (0x1a0ull) +#define NIX_AF_RAS_W1S (0x1a8ull) +#define NIX_AF_RAS_ENA_W1S (0x1b0ull) +#define NIX_AF_RAS_ENA_W1C (0x1b8ull) +#define NIX_AF_RVU_INT (0x1c0ull) +#define NIX_AF_RVU_INT_W1S (0x1c8ull) +#define NIX_AF_RVU_INT_ENA_W1S (0x1d0ull) +#define NIX_AF_RVU_INT_ENA_W1C (0x1d8ull) +#define NIX_AF_TCP_TIMER (0x1e0ull) +/* [CN10k, .) */ +#define NIX_AF_RX_DEF_ETX(a) (0x1f0ull | (uint64_t)(a) << 3) +#define NIX_AF_RX_DEF_OL2 (0x200ull) +#define NIX_AF_RX_DEF_GEN0_COLOR (0x208ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_OIP4 (0x210ull) +#define NIX_AF_RX_DEF_GEN1_COLOR (0x218ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_IIP4 (0x220ull) +#define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x228ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_OIP6 (0x230ull) +#define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x238ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_IIP6 (0x240ull) +#define NIX_AF_RX_DEF_OTCP (0x250ull) +#define NIX_AF_RX_DEF_ITCP (0x260ull) +#define NIX_AF_RX_DEF_OUDP (0x270ull) +#define NIX_AF_RX_DEF_IUDP (0x280ull) +#define NIX_AF_RX_DEF_OSCTP (0x290ull) +#define NIX_AF_RX_DEF_CST_APAD_0 (0x298ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_ISCTP (0x2a0ull) +#define NIX_AF_RX_DEF_CST_APAD_1 (0x2a8ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_IPSECX(a) (0x2b0ull | (uint64_t)(a) << 3) +#define NIX_AF_RX_DEF_IIP4_DSCP (0x2e0ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_OIP4_DSCP (0x2e8ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_IIP6_DSCP (0x2f0ull) /* [CN10K, .) */ +#define NIX_AF_RX_DEF_OIP6_DSCP (0x2f8ull) /* [CN10K, .) */ +#define NIX_AF_RX_IPSEC_GEN_CFG (0x300ull) +#define NIX_AF_RX_IPSEC_VWQE_GEN_CFG (0x310ull) /* [CN10K, .) */ +#define NIX_AF_RX_CPTX_INST_QSEL(a) (0x320ull | (uint64_t)(a) << 3) +#define NIX_AF_RX_CPTX_CREDIT(a) (0x360ull | (uint64_t)(a) << 3) +#define NIX_AF_NDC_RX_SYNC (0x3e0ull) +#define NIX_AF_NDC_TX_SYNC (0x3f0ull) +#define NIX_AF_AQ_CFG (0x400ull) +#define NIX_AF_AQ_BASE (0x410ull) +#define NIX_AF_AQ_STATUS (0x420ull) +#define NIX_AF_AQ_DOOR (0x430ull) +#define NIX_AF_AQ_DONE_WAIT (0x440ull) +#define NIX_AF_AQ_DONE (0x450ull) +#define NIX_AF_AQ_DONE_ACK (0x460ull) +#define NIX_AF_AQ_DONE_TIMER (0x470ull) +#define NIX_AF_AQ_DONE_ENA_W1S (0x490ull) +#define NIX_AF_AQ_DONE_ENA_W1C (0x498ull) +#define NIX_AF_RX_LINKX_CFG(a) (0x540ull | (uint64_t)(a) << 16) +#define NIX_AF_RX_SW_SYNC (0x550ull) +#define NIX_AF_RX_LINKX_WRR_CFG(a) (0x560ull | (uint64_t)(a) << 16) +#define NIX_AF_SEB_CFG (0x5f0ull) /* [CN10K, .) */ +#define NIX_AF_EXPR_TX_FIFO_STATUS (0x640ull) /* [CN9K, CN10K) */ +#define NIX_AF_NORM_TX_FIFO_STATUS (0x648ull) +#define NIX_AF_SDP_TX_FIFO_STATUS (0x650ull) +#define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x660ull) +#define NIX_AF_TX_NPC_CAPTURE_INFO (0x668ull) +#define NIX_AF_TX_NPC_CAPTURE_RESPX(a) (0x680ull | (uint64_t)(a) << 3) +#define NIX_AF_SEB_ACTIVE_CYCLES_PCX(a) (0x6c0ull | (uint64_t)(a) << 3) +#define NIX_AF_SMQX_CFG(a) (0x700ull | (uint64_t)(a) << 16) +#define NIX_AF_SMQX_HEAD(a) (0x710ull | (uint64_t)(a) << 16) +#define NIX_AF_SMQX_TAIL(a) (0x720ull | (uint64_t)(a) << 16) +#define NIX_AF_SMQX_STATUS(a) (0x730ull | (uint64_t)(a) << 16) +#define NIX_AF_SMQX_NXT_HEAD(a) (0x740ull | (uint64_t)(a) << 16) +#define NIX_AF_SQM_ACTIVE_CYCLES_PC (0x770ull) +#define NIX_AF_SQM_SCLK_CNT (0x780ull) /* [CN10K, .) */ +#define NIX_AF_DWRR_SDP_MTU (0x790ull) /* [CN10K, .) */ +#define NIX_AF_DWRR_RPM_MTU (0x7a0ull) /* [CN10K, .) */ +#define NIX_AF_PSE_CHANNEL_LEVEL (0x800ull) +#define NIX_AF_PSE_SHAPER_CFG (0x810ull) +#define NIX_AF_PSE_ACTIVE_CYCLES_PC (0x8c0ull) +#define NIX_AF_MARK_FORMATX_CTL(a) (0x900ull | (uint64_t)(a) << 18) +#define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xa00ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xa10ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TX_LINKX_SW_XOFF(a) (0xa20ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TX_LINKX_NORM_CDT_ADJ(a) (0xa20ull | (uint64_t)(a) << 16) +#define NIX_AF_TX_LINKX_HW_XOFF(a) (0xa30ull | (uint64_t)(a) << 16) +#define NIX_AF_SDP_LINK_CREDIT (0xa40ull) +#define NIX_AF_SDP_LINK_CDT_ADJ (0xa50ull) /* [CN10K, .) */ +/* [CN9K, CN10K) */ +#define NIX_AF_SDP_SW_XOFFX(a) (0xa60ull | (uint64_t)(a) << 3) +#define NIX_AF_SDP_HW_XOFFX(a) (0xac0ull | (uint64_t)(a) << 3) +#define NIX_AF_TL4X_BP_STATUS(a) (0xb00ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xb10ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1_TW_ARB_CTL_DEBUG (0xbc0ull) /* [CN10K, .) */ +#define NIX_AF_TL1_TW_ARB_REQ_DEBUG (0xbc8ull) /* [CN10K, .) */ +#define NIX_AF_TL1X_SCHEDULE(a) (0xc00ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_SHAPE(a) (0xc10ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_CIR(a) (0xc20ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL1X_SHAPE_STATE(a) (0xc50ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL1X_SHAPE_STATE_CIR(a) (0xc50ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_SW_XOFF(a) (0xc70ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_TOPOLOGY(a) (0xc80ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_MD_DEBUG0(a) (0xcc0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_MD_DEBUG1(a) (0xcc8ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL1X_MD_DEBUG2(a) (0xcd0ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL2X_SHAPE_STATE_CIR(a) (0xcd0ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL1X_MD_DEBUG3(a) (0xcd8ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xd20ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_DROPPED_BYTES(a) (0xd30ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_RED_PACKETS(a) (0xd40ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_RED_BYTES(a) (0xd50ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xd60ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_YELLOW_BYTES(a) (0xd70ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_GREEN_PACKETS(a) (0xd80ull | (uint64_t)(a) << 16) +#define NIX_AF_TL1X_GREEN_BYTES(a) (0xd90ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQ_MD_COUNT (0xda0ull) /* [CN10K, .) */ +/* [CN10K, .) */ +#define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2_TW_ARB_CTL_DEBUG (0xdc0ull) /* [CN10K, .) */ +/* [CN10K, .) */ +#define NIX_AF_TL2_TWX_ARB_REQ_DEBUG0(a) (0xdc8ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL2_TWX_ARB_REQ_DEBUG1(a) (0xdd0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_SCHEDULE(a) (0xe00ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_SHAPE(a) (0xe10ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_CIR(a) (0xe20ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_PIR(a) (0xe30ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_SCHED_STATE(a) (0xe40ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL2X_SHAPE_STATE(a) (0xe50ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL2X_SHAPE_STATE_PIR(a) (0xe50ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_SW_XOFF(a) (0xe70ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_TOPOLOGY(a) (0xe80ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_PARENT(a) (0xe88ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_MD_DEBUG0(a) (0xec0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL2X_MD_DEBUG1(a) (0xec8ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL2X_MD_DEBUG2(a) (0xed0ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL3X_SHAPE_STATE_CIR(a) (0xed0ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL2X_MD_DEBUG3(a) (0xed8ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3_TW_ARB_CTL_DEBUG (0xfc0ull) /* [CN10K, .) */ +/* [CN10k, .) */ +#define NIX_AF_TL3_TWX_ARB_REQ_DEBUG0(a) (0xfc8ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL3_TWX_ARB_REQ_DEBUG1(a) (0xfd0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_SCHEDULE(a) (0x1000ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_SHAPE(a) (0x1010ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_CIR(a) (0x1020ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_PIR(a) (0x1030ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_SCHED_STATE(a) (0x1040ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL3X_SHAPE_STATE_PIR(a) (0x1050ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_SW_XOFF(a) (0x1070ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_TOPOLOGY(a) (0x1080ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_PARENT(a) (0x1088ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_MD_DEBUG0(a) (0x10c0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3X_MD_DEBUG1(a) (0x10c8ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL3X_MD_DEBUG2(a) (0x10d0ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL4X_SHAPE_STATE_CIR(a) (0x10d0ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL3X_MD_DEBUG3(a) (0x10d8ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4_TW_ARB_CTL_DEBUG (0x11c0ull) /* [CN10K, .) */ +/* [CN10K, .) */ +#define NIX_AF_TL4_TWX_ARB_REQ_DEBUG0(a) (0x11c8ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_TL4_TWX_ARB_REQ_DEBUG1(a) (0x11d0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_SCHEDULE(a) (0x1200ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_SHAPE(a) (0x1210ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_CIR(a) (0x1220ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_PIR(a) (0x1230ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_SCHED_STATE(a) (0x1240ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_SW_XOFF(a) (0x1270ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_TOPOLOGY(a) (0x1280ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_PARENT(a) (0x1288ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_MD_DEBUG0(a) (0x12c0ull | (uint64_t)(a) << 16) +#define NIX_AF_TL4X_MD_DEBUG1(a) (0x12c8ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL4X_MD_DEBUG2(a) (0x12d0ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_MDQX_SHAPE_STATE_CIR(a) (0x12d0ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL4X_MD_DEBUG3(a) (0x12d8ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQ_TW_ARB_CTL_DEBUG (0x13c0ull) /* [CN10K, .) */ +/* [CN10K, .) */ +#define NIX_AF_MDQ_TWX_ARB_REQ_DEBUG0(a) (0x13c8ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_MDQ_TWX_ARB_REQ_DEBUG1(a) (0x13d0ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_SCHEDULE(a) (0x1400ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_SHAPE(a) (0x1410ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_CIR(a) (0x1420ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_PIR(a) (0x1430ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_SCHED_STATE(a) (0x1440ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_MDQX_SHAPE_STATE_PIR(a) (0x1450ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_SW_XOFF(a) (0x1470ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_PARENT(a) (0x1480ull | (uint64_t)(a) << 16) +#define NIX_AF_MDQX_MD_DEBUG(a) (0x14c0ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0ull | (uint64_t)(a) << 16) +/* [CN9K, CN10K) */ +#define NIX_AF_TL3_TL2X_CFG(a) (0x1600ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610ull | (uint64_t)(a) << 16) +#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) \ + (0x1700ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) +#define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) \ + (0x1800ull | (uint64_t)(a) << 18 | (uint64_t)(b) << 3) +#define NIX_AF_TX_MCASTX(a) (0x1900ull | (uint64_t)(a) << 15) +#define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1a00ull | (uint64_t)(a) << 16) +#define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1a10ull | (uint64_t)(a) << 16) +#define NIX_AF_RX_BPIDX_STATUS(a) (0x1a20ull | (uint64_t)(a) << 17) +#define NIX_AF_RX_CHANX_CFG(a) (0x1a30ull | (uint64_t)(a) << 15) +#define NIX_AF_CINT_TIMERX(a) (0x1a40ull | (uint64_t)(a) << 18) +#define NIX_AF_LSO_FORMATX_FIELDX(a, b) \ + (0x1b00ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) +#define NIX_AF_LFX_CFG(a) (0x4000ull | (uint64_t)(a) << 17) +/* [CN10K, .) */ +#define NIX_AF_LINKX_CFG(a) (0x4010ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_SQS_CFG(a) (0x4020ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_TX_CFG2(a) (0x4028ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_SQS_BASE(a) (0x4030ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RQS_CFG(a) (0x4040ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RQS_BASE(a) (0x4050ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_CQS_CFG(a) (0x4060ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_CQS_BASE(a) (0x4070ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_TX_CFG(a) (0x4080ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_CFG(a) (0x40a0ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RSS_CFG(a) (0x40c0ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RSS_BASE(a) (0x40d0ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_QINTS_CFG(a) (0x4100ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_QINTS_BASE(a) (0x4110ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_CINTS_CFG(a) (0x4120ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_CINTS_BASE(a) (0x4130ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_TX_STATUS(a) (0x4180ull | (uint64_t)(a) << 17) +#define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) \ + (0x4200ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) +#define NIX_AF_LFX_LOCKX(a, b) \ + (0x4300ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) +#define NIX_AF_LFX_TX_STATX(a, b) \ + (0x4400ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) +#define NIX_AF_LFX_RX_STATX(a, b) \ + (0x4500ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) +#define NIX_AF_LFX_RSS_GRPX(a, b) \ + (0x4600ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) +#define NIX_AF_RX_NPC_MC_RCV (0x4700ull) +#define NIX_AF_RX_NPC_MC_DROP (0x4710ull) +#define NIX_AF_RX_NPC_MIRROR_RCV (0x4720ull) +#define NIX_AF_RX_NPC_MIRROR_DROP (0x4730ull) +/* [CN10K, .) */ +#define NIX_AF_LFX_VWQE_NORM_COMPL(a) (0x4740ull | (uint64_t)(a) << 17) +/* [CN10K, .) */ +#define NIX_AF_LFX_VWQE_RLS_TIMEOUT(a) (0x4750ull | (uint64_t)(a) << 17) +/* [CN10K, .) */ +#define NIX_AF_LFX_VWQE_HASH_FULL(a) (0x4760ull | (uint64_t)(a) << 17) +/* [CN10K, .) */ +#define NIX_AF_LFX_VWQE_SA_FULL(a) (0x4770ull | (uint64_t)(a) << 17) +#define NIX_AF_VWQE_HASH_FUNC_MASK (0x47a0ull) /* [CN10K, .) */ +#define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800ull | (uint64_t)(a) << 16) +/* [CN10K, .) */ +#define NIX_AF_RX_LINKX_WRR_OUT_CFG(a) (0x4a00ull | (uint64_t)(a) << 16) +#define NIX_PRIV_AF_INT_CFG (0x8000000ull) +#define NIX_PRIV_LFX_CFG(a) (0x8000010ull | (uint64_t)(a) << 8) +#define NIX_PRIV_LFX_INT_CFG(a) (0x8000020ull | (uint64_t)(a) << 8) +#define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030ull) + +#define NIX_LF_RX_SECRETX(a) (0x0ull | (uint64_t)(a) << 3) +#define NIX_LF_CFG (0x100ull) +#define NIX_LF_GINT (0x200ull) +#define NIX_LF_GINT_W1S (0x208ull) +#define NIX_LF_GINT_ENA_W1C (0x210ull) +#define NIX_LF_GINT_ENA_W1S (0x218ull) +#define NIX_LF_ERR_INT (0x220ull) +#define NIX_LF_ERR_INT_W1S (0x228ull) +#define NIX_LF_ERR_INT_ENA_W1C (0x230ull) +#define NIX_LF_ERR_INT_ENA_W1S (0x238ull) +#define NIX_LF_RAS (0x240ull) +#define NIX_LF_RAS_W1S (0x248ull) +#define NIX_LF_RAS_ENA_W1C (0x250ull) +#define NIX_LF_RAS_ENA_W1S (0x258ull) +#define NIX_LF_SQ_OP_ERR_DBG (0x260ull) +#define NIX_LF_MNQ_ERR_DBG (0x270ull) +#define NIX_LF_SEND_ERR_DBG (0x280ull) +#define NIX_LF_TX_STATX(a) (0x300ull | (uint64_t)(a) << 3) +#define NIX_LF_RX_STATX(a) (0x400ull | (uint64_t)(a) << 3) +#define NIX_LF_OP_SENDX(a) (0x800ull | (uint64_t)(a) << 3) +#define NIX_LF_RQ_OP_INT (0x900ull) +#define NIX_LF_RQ_OP_OCTS (0x910ull) +#define NIX_LF_RQ_OP_PKTS (0x920ull) +#define NIX_LF_RQ_OP_DROP_OCTS (0x930ull) +#define NIX_LF_RQ_OP_DROP_PKTS (0x940ull) +#define NIX_LF_RQ_OP_RE_PKTS (0x950ull) +#define NIX_LF_OP_IPSEC_DYNO_CNT (0x980ull) +#define NIX_LF_OP_VWQE_FLUSH (0x9a0ull) /* [CN10K, .) */ +#define NIX_LF_PL_OP_BAND_PROF (0x9c0ull) /* [CN10K, .) */ +#define NIX_LF_SQ_OP_INT (0xa00ull) +#define NIX_LF_SQ_OP_OCTS (0xa10ull) +#define NIX_LF_SQ_OP_PKTS (0xa20ull) +#define NIX_LF_SQ_OP_STATUS (0xa30ull) +#define NIX_LF_SQ_OP_DROP_OCTS (0xa40ull) +#define NIX_LF_SQ_OP_DROP_PKTS (0xa50ull) +#define NIX_LF_CQ_OP_INT (0xb00ull) +#define NIX_LF_CQ_OP_DOOR (0xb30ull) +#define NIX_LF_CQ_OP_STATUS (0xb40ull) +#define NIX_LF_QINTX_CNT(a) (0xc00ull | (uint64_t)(a) << 12) +#define NIX_LF_QINTX_INT(a) (0xc10ull | (uint64_t)(a) << 12) +#define NIX_LF_QINTX_ENA_W1S(a) (0xc20ull | (uint64_t)(a) << 12) +#define NIX_LF_QINTX_ENA_W1C(a) (0xc30ull | (uint64_t)(a) << 12) +#define NIX_LF_CINTX_CNT(a) (0xd00ull | (uint64_t)(a) << 12) +#define NIX_LF_CINTX_WAIT(a) (0xd10ull | (uint64_t)(a) << 12) +#define NIX_LF_CINTX_INT(a) (0xd20ull | (uint64_t)(a) << 12) +#define NIX_LF_CINTX_INT_W1S(a) (0xd30ull | (uint64_t)(a) << 12) +#define NIX_LF_CINTX_ENA_W1S(a) (0xd40ull | (uint64_t)(a) << 12) +#define NIX_LF_CINTX_ENA_W1C(a) (0xd50ull | (uint64_t)(a) << 12) +/* [CN10K, .) */ +#define NIX_LF_RX_GEN_COLOR_CONVX(a) (0x4740ull | (uint64_t)(a) << 3) +#define NIX_LF_RX_VLAN0_COLOR_CONV (0x4760ull) /* [CN10K, .) */ +#define NIX_LF_RX_VLAN1_COLOR_CONV (0x4768ull) /* [CN10K, .) */ +#define NIX_LF_RX_IIP_COLOR_CONV_LO (0x4770ull) /* [CN10K, .) */ +#define NIX_LF_RX_IIP_COLOR_CONV_HI (0x4778ull) /* [CN10K, .) */ +#define NIX_LF_RX_OIP_COLOR_CONV_LO (0x4780ull) /* [CN10K, .) */ +#define NIX_LF_RX_OIP_COLOR_CONV_HI (0x4788ull) /* [CN10K, .) */ + +/* Enum offsets */ + +#define NIX_STAT_LF_TX_TX_UCAST (0x0ull) +#define NIX_STAT_LF_TX_TX_BCAST (0x1ull) +#define NIX_STAT_LF_TX_TX_MCAST (0x2ull) +#define NIX_STAT_LF_TX_TX_DROP (0x3ull) +#define NIX_STAT_LF_TX_TX_OCTS (0x4ull) + +#define NIX_STAT_LF_RX_RX_OCTS (0x0ull) +#define NIX_STAT_LF_RX_RX_UCAST (0x1ull) +#define NIX_STAT_LF_RX_RX_BCAST (0x2ull) +#define NIX_STAT_LF_RX_RX_MCAST (0x3ull) +#define NIX_STAT_LF_RX_RX_DROP (0x4ull) +#define NIX_STAT_LF_RX_RX_DROP_OCTS (0x5ull) +#define NIX_STAT_LF_RX_RX_FCS (0x6ull) +#define NIX_STAT_LF_RX_RX_ERR (0x7ull) +#define NIX_STAT_LF_RX_RX_DRP_BCAST (0x8ull) +#define NIX_STAT_LF_RX_RX_DRP_MCAST (0x9ull) +#define NIX_STAT_LF_RX_RX_DRP_L3BCAST (0xaull) +#define NIX_STAT_LF_RX_RX_DRP_L3MCAST (0xbull) + +#define NIX_STAT_LF_RX_RX_GC_OCTS_PASSED (0xcull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_GC_PKTS_PASSED (0xdull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_YC_OCTS_PASSED (0xeull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_YC_PKTS_PASSED (0xfull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_RC_OCTS_PASSED (0x10ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_RC_PKTS_PASSED (0x11ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_GC_OCTS_DROP (0x12ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_GC_PKTS_DROP (0x13ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_YC_OCTS_DROP (0x14ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_YC_PKTS_DROP (0x15ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_RC_OCTS_DROP (0x16ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_RC_PKTS_DROP (0x17ull) /* [CN10K, .) */ +#define NIX_STAT_LF_RX_RX_CPT_DROP_PKTS (0x18ull) /* [CN10K, .) */ + +#define CGX_RX_PKT_CNT (0x0ull) /* [CN9K, CN10K) */ +#define CGX_RX_OCT_CNT (0x1ull) /* [CN9K, CN10K) */ +#define CGX_RX_PAUSE_PKT_CNT (0x2ull) /* [CN9K, CN10K) */ +#define CGX_RX_PAUSE_OCT_CNT (0x3ull) /* [CN9K, CN10K) */ +#define CGX_RX_DMAC_FILT_PKT_CNT (0x4ull) /* [CN9K, CN10K) */ +#define CGX_RX_DMAC_FILT_OCT_CNT (0x5ull) /* [CN9K, CN10K) */ +#define CGX_RX_FIFO_DROP_PKT_CNT (0x6ull) /* [CN9K, CN10K) */ +#define CGX_RX_FIFO_DROP_OCT_CNT (0x7ull) /* [CN9K, CN10K) */ +#define CGX_RX_ERR_CNT (0x8ull) /* [CN9K, CN10K) */ + +#define CGX_TX_COLLISION_DROP (0x0ull) /* [CN9K, CN10K) */ +#define CGX_TX_FRAME_DEFER_CNT (0x1ull) /* [CN9K, CN10K) */ +#define CGX_TX_MULTIPLE_COLLISION (0x2ull) /* [CN9K, CN10K) */ +#define CGX_TX_SINGLE_COLLISION (0x3ull) /* [CN9K, CN10K) */ +#define CGX_TX_OCT_CNT (0x4ull) /* [CN9K, CN10K) */ +#define CGX_TX_PKT_CNT (0x5ull) /* [CN9K, CN10K) */ +#define CGX_TX_1_63_PKT_CNT (0x6ull) /* [CN9K, CN10K) */ +#define CGX_TX_64_PKT_CNT (0x7ull) /* [CN9K, CN10K) */ +#define CGX_TX_65_127_PKT_CNT (0x8ull) /* [CN9K, CN10K) */ +#define CGX_TX_128_255_PKT_CNT (0x9ull) /* [CN9K, CN10K) */ +#define CGX_TX_256_511_PKT_CNT (0xaull) /* [CN9K, CN10K) */ +#define CGX_TX_512_1023_PKT_CNT (0xbull) /* [CN9K, CN10K) */ +#define CGX_TX_1024_1518_PKT_CNT (0xcull) /* [CN9K, CN10K) */ +#define CGX_TX_1519_MAX_PKT_CNT (0xdull) /* [CN9K, CN10K) */ +#define CGX_TX_BCAST_PKTS (0xeull) /* [CN9K, CN10K) */ +#define CGX_TX_MCAST_PKTS (0xfull) /* [CN9K, CN10K) */ +#define CGX_TX_UFLOW_PKTS (0x10ull) /* [CN9K, CN10K) */ +#define CGX_TX_PAUSE_PKTS (0x11ull) /* [CN9K, CN10K) */ + +#define RPM_MTI_STAT_RX_OCT_CNT (0x0ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_OCT_RECV_OK (0x1ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_ALIG_ERR (0x2ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CTRL_FRM_RECV (0x3ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_FRM_LONG (0x4ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_LEN_ERR (0x5ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_FRM_RECV (0x6ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_FRM_SEQ_ERR (0x7ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_VLAN_OK (0x8ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_IN_ERR (0x9ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_IN_UCAST_PKT (0xaull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_IN_MCAST_PKT (0xbull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_IN_BCAST_PKT (0xcull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_DRP_EVENTS (0xdull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_PKT (0xeull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_UNDER_SIZE (0xfull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_1_64_PKT_CNT (0x10ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_65_127_PKT_CNT (0x11ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_128_255_PKT_CNT (0x12ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_256_511_PKT_CNT (0x13ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_512_1023_PKT_CNT (0x14ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_1024_1518_PKT_CNT (0x15ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_1519_MAX_PKT_CNT (0x16ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_OVER_SIZE (0x17ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_JABBER (0x18ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_ETH_FRAGS (0x19ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_0 (0x1aull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_1 (0x1bull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_2 (0x1cull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_3 (0x1dull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_4 (0x1eull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_5 (0x1full) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_6 (0x20ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_7 (0x21ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_8 (0x22ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_9 (0x23ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_10 (0x24ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_11 (0x25ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_12 (0x26ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_13 (0x27ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_14 (0x28ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_CBFC_CLASS_15 (0x29ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_RX_MAC_CONTROL (0x2aull) /* [CN10K, .) */ + +#define RPM_MTI_STAT_TX_OCT_CNT (0x0ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_OCT_TX_OK (0x1ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_PAUSE_MAC_CTRL (0x2ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_FRAMES_OK (0x3ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_VLAN_OK (0x4ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_OUT_ERR (0x5ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_UCAST_PKT_CNT (0x6ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_MCAST_PKT_CNT (0x7ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_BCAST_PKT_CNT (0x8ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_1_64_PKT_CNT (0x9ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_65_127_PKT_CNT (0xaull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_128_255_PKT_CNT (0xbull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_256_511_PKT_CNT (0xcull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_512_1023_PKT_CNT (0xdull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_1024_1518_PKT_CNT (0xeull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_1519_MAX_PKT_CNT (0xfull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_0 (0x10ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_1 (0x11ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_2 (0x12ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_3 (0x13ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_4 (0x14ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_5 (0x15ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_6 (0x16ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_7 (0x17ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_8 (0x18ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_9 (0x19ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_10 (0x1aull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_11 (0x1bull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_12 (0x1cull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_13 (0x1dull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_14 (0x1eull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_CBFC_CLASS_15 (0x1full) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_MAC_CONTROL_FRAMES (0x20ull) /* [CN10K, .) */ +#define RPM_MTI_STAT_TX_PKT_CNT (0x21ull) /* [CN10K, .) */ + +#define NIX_SQOPERR_SQ_OOR (0x0ull) +#define NIX_SQOPERR_SQ_CTX_FAULT (0x1ull) +#define NIX_SQOPERR_SQ_CTX_POISON (0x2ull) +#define NIX_SQOPERR_SQ_DISABLED (0x3ull) +#define NIX_SQOPERR_MAX_SQE_SIZE_ERR (0x4ull) +#define NIX_SQOPERR_SQE_OFLOW (0x5ull) +#define NIX_SQOPERR_SQB_NULL (0x6ull) +#define NIX_SQOPERR_SQB_FAULT (0x7ull) +#define NIX_SQOPERR_SQE_SIZEM1_ZERO (0x8ull) /* [CN10K, .) */ + +#define NIX_SQINT_LMT_ERR (0x0ull) +#define NIX_SQINT_MNQ_ERR (0x1ull) +#define NIX_SQINT_SEND_ERR (0x2ull) +#define NIX_SQINT_SQB_ALLOC_FAIL (0x3ull) + +#define NIX_SEND_STATUS_GOOD (0x0ull) +#define NIX_SEND_STATUS_SQ_CTX_FAULT (0x1ull) +#define NIX_SEND_STATUS_SQ_CTX_POISON (0x2ull) +#define NIX_SEND_STATUS_SQB_FAULT (0x3ull) +#define NIX_SEND_STATUS_SQB_POISON (0x4ull) +#define NIX_SEND_STATUS_SEND_HDR_ERR (0x5ull) +#define NIX_SEND_STATUS_SEND_EXT_ERR (0x6ull) +#define NIX_SEND_STATUS_JUMP_FAULT (0x7ull) +#define NIX_SEND_STATUS_JUMP_POISON (0x8ull) +#define NIX_SEND_STATUS_SEND_CRC_ERR (0x10ull) +#define NIX_SEND_STATUS_SEND_IMM_ERR (0x11ull) +#define NIX_SEND_STATUS_SEND_SG_ERR (0x12ull) +#define NIX_SEND_STATUS_SEND_MEM_ERR (0x13ull) +#define NIX_SEND_STATUS_INVALID_SUBDC (0x14ull) +#define NIX_SEND_STATUS_SUBDC_ORDER_ERR (0x15ull) +#define NIX_SEND_STATUS_DATA_FAULT (0x16ull) +#define NIX_SEND_STATUS_DATA_POISON (0x17ull) +#define NIX_SEND_STATUS_NPC_DROP_ACTION (0x20ull) +#define NIX_SEND_STATUS_LOCK_VIOL (0x21ull) +#define NIX_SEND_STATUS_NPC_UCAST_CHAN_ERR (0x22ull) +#define NIX_SEND_STATUS_NPC_MCAST_CHAN_ERR (0x23ull) +#define NIX_SEND_STATUS_NPC_MCAST_ABORT (0x24ull) +#define NIX_SEND_STATUS_NPC_VTAG_PTR_ERR (0x25ull) +#define NIX_SEND_STATUS_NPC_VTAG_SIZE_ERR (0x26ull) +#define NIX_SEND_STATUS_SEND_MEM_FAULT (0x27ull) +#define NIX_SEND_STATUS_SEND_STATS_ERR (0x28ull) + +#define NIX_SENDSTATSALG_NOP (0x0ull) +#define NIX_SENDSTATSALG_ADD_PKT_CNT (0x1ull) +#define NIX_SENDSTATSALG_ADD_BYTE_CNT (0x2ull) +#define NIX_SENDSTATSALG_ADD_PKT_BYTE_CNT (0x3ull) +#define NIX_SENDSTATSALG_UPDATE_PKT_CNT_ON_DROP (0x4ull) +#define NIX_SENDSTATSALG_UPDATE_BYTE_CNT_ON_DROP (0x5ull) +#define NIX_SENDSTATSALG_UPDATE_PKT_BYTE_CNT_ON_DROP (0x6ull) + +#define NIX_SENDMEMDSZ_B64 (0x0ull) +#define NIX_SENDMEMDSZ_B32 (0x1ull) +#define NIX_SENDMEMDSZ_B16 (0x2ull) +#define NIX_SENDMEMDSZ_B8 (0x3ull) + +#define NIX_SENDMEMALG_SET (0x0ull) +#define NIX_SENDMEMALG_SETTSTMP (0x1ull) +#define NIX_SENDMEMALG_SETRSLT (0x2ull) +#define NIX_SENDMEMALG_ADD (0x8ull) +#define NIX_SENDMEMALG_SUB (0x9ull) +#define NIX_SENDMEMALG_ADDLEN (0xaull) +#define NIX_SENDMEMALG_SUBLEN (0xbull) +#define NIX_SENDMEMALG_ADDMBUF (0xcull) +#define NIX_SENDMEMALG_SUBMBUF (0xdull) + +#define NIX_SUBDC_NOP (0x0ull) +#define NIX_SUBDC_EXT (0x1ull) +#define NIX_SUBDC_CRC (0x2ull) +#define NIX_SUBDC_IMM (0x3ull) +#define NIX_SUBDC_SG (0x4ull) +#define NIX_SUBDC_MEM (0x5ull) +#define NIX_SUBDC_JUMP (0x6ull) +#define NIX_SUBDC_WORK (0x7ull) +#define NIX_SUBDC_SG2 (0x8ull) /* [CN10K, .) */ +#define NIX_SUBDC_AGE_AND_STATS (0x9ull) /* [CN10K, .) */ +#define NIX_SUBDC_SOD (0xfull) + +#define NIX_STYPE_STF (0x0ull) +#define NIX_STYPE_STT (0x1ull) +#define NIX_STYPE_STP (0x2ull) + +#define NIX_RX_ACTIONOP_DROP (0x0ull) +#define NIX_RX_ACTIONOP_UCAST (0x1ull) +#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull) +#define NIX_RX_ACTIONOP_MCAST (0x3ull) +#define NIX_RX_ACTIONOP_RSS (0x4ull) +#define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull) +#define NIX_RX_ACTIONOP_MIRROR (0x6ull) + +#define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull) +#define NIX_RX_VTAGACTION_VTAG1_RELPTR (0x4ull) +#define NIX_RX_VTAGACTION_VTAG_VALID (0x1ull) +#define NIX_TX_VTAGACTION_VTAG0_RELPTR (sizeof(struct nix_inst_hdr_s) + 2 * 6) +#define NIX_TX_VTAGACTION_VTAG1_RELPTR \ + (sizeof(struct nix_inst_hdr_s) + 2 * 6 + 4) +#define NIX_RQINT_DROP (0x0ull) +#define NIX_RQINT_RED (0x1ull) +#define NIX_RQINT_R2 (0x2ull) +#define NIX_RQINT_R3 (0x3ull) +#define NIX_RQINT_R4 (0x4ull) +#define NIX_RQINT_R5 (0x5ull) +#define NIX_RQINT_R6 (0x6ull) +#define NIX_RQINT_R7 (0x7ull) + +#define NIX_MAXSQESZ_W16 (0x0ull) +#define NIX_MAXSQESZ_W8 (0x1ull) + +#define NIX_LSOALG_NOP (0x0ull) +#define NIX_LSOALG_ADD_SEGNUM (0x1ull) +#define NIX_LSOALG_ADD_PAYLEN (0x2ull) +#define NIX_LSOALG_ADD_OFFSET (0x3ull) +#define NIX_LSOALG_TCP_FLAGS (0x4ull) + +#define NIX_MNQERR_SQ_CTX_FAULT (0x0ull) +#define NIX_MNQERR_SQ_CTX_POISON (0x1ull) +#define NIX_MNQERR_SQB_FAULT (0x2ull) +#define NIX_MNQERR_SQB_POISON (0x3ull) +#define NIX_MNQERR_TOTAL_ERR (0x4ull) +#define NIX_MNQERR_LSO_ERR (0x5ull) +#define NIX_MNQERR_CQ_QUERY_ERR (0x6ull) +#define NIX_MNQERR_MAX_SQE_SIZE_ERR (0x7ull) +#define NIX_MNQERR_MAXLEN_ERR (0x8ull) +#define NIX_MNQERR_SQE_SIZEM1_ZERO (0x9ull) + +#define NIX_MDTYPE_RSVD (0x0ull) +#define NIX_MDTYPE_FLUSH (0x1ull) +#define NIX_MDTYPE_PMD (0x2ull) + +#define NIX_NDC_TX_PORT_LMT (0x0ull) +#define NIX_NDC_TX_PORT_ENQ (0x1ull) +#define NIX_NDC_TX_PORT_MNQ (0x2ull) +#define NIX_NDC_TX_PORT_DEQ (0x3ull) +#define NIX_NDC_TX_PORT_DMA (0x4ull) +#define NIX_NDC_TX_PORT_XQE (0x5ull) + +#define NIX_NDC_RX_PORT_AQ (0x0ull) +#define NIX_NDC_RX_PORT_CQ (0x1ull) +#define NIX_NDC_RX_PORT_CINT (0x2ull) +#define NIX_NDC_RX_PORT_MC (0x3ull) +#define NIX_NDC_RX_PORT_PKT (0x4ull) +#define NIX_NDC_RX_PORT_RQ (0x5ull) + +#define NIX_RE_OPCODE_RE_NONE (0x0ull) +#define NIX_RE_OPCODE_RE_PARTIAL (0x1ull) +#define NIX_RE_OPCODE_RE_JABBER (0x2ull) +#define NIX_RE_OPCODE_RE_FCS (0x7ull) +#define NIX_RE_OPCODE_RE_FCS_RCV (0x8ull) +#define NIX_RE_OPCODE_RE_TERMINATE (0x9ull) +#define NIX_RE_OPCODE_RE_RX_CTL (0xbull) +#define NIX_RE_OPCODE_RE_SKIP (0xcull) +#define NIX_RE_OPCODE_RE_DMAPKT (0xfull) +#define NIX_RE_OPCODE_UNDERSIZE (0x10ull) +#define NIX_RE_OPCODE_OVERSIZE (0x11ull) +#define NIX_RE_OPCODE_OL2_LENMISM (0x12ull) + +#define NIX_REDALG_STD (0x0ull) +#define NIX_REDALG_SEND (0x1ull) +#define NIX_REDALG_STALL (0x2ull) +#define NIX_REDALG_DISCARD (0x3ull) + +#define NIX_RX_BAND_PROF_ACTIONRESULT_PASS (0x0ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_ACTIONRESULT_DROP (0x1ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_ACTIONRESULT_RED (0x2ull) /* [CN10K, .) */ + +#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x1ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_TOP (0x2ull) /* [CN10K, .) */ + +#define NIX_RX_COLORRESULT_GREEN (0x0ull) /* [CN10K, .) */ +#define NIX_RX_COLORRESULT_YELLOW (0x1ull) /* [CN10K, .) */ +#define NIX_RX_COLORRESULT_RED (0x2ull) /* [CN10K, .) */ + +#define NIX_RX_MCOP_RQ (0x0ull) +#define NIX_RX_MCOP_RSS (0x1ull) + +#define NIX_RX_PERRCODE_NPC_RESULT_ERR (0x2ull) +#define NIX_RX_PERRCODE_MCAST_FAULT (0x4ull) +#define NIX_RX_PERRCODE_MIRROR_FAULT (0x5ull) +#define NIX_RX_PERRCODE_MCAST_POISON (0x6ull) +#define NIX_RX_PERRCODE_MIRROR_POISON (0x7ull) +#define NIX_RX_PERRCODE_DATA_FAULT (0x8ull) +#define NIX_RX_PERRCODE_MEMOUT (0x9ull) +#define NIX_RX_PERRCODE_BUFS_OFLOW (0xaull) +#define NIX_RX_PERRCODE_OL3_LEN (0x10ull) +#define NIX_RX_PERRCODE_OL4_LEN (0x11ull) +#define NIX_RX_PERRCODE_OL4_CHK (0x12ull) +#define NIX_RX_PERRCODE_OL4_PORT (0x13ull) +#define NIX_RX_PERRCODE_IL3_LEN (0x20ull) +#define NIX_RX_PERRCODE_IL4_LEN (0x21ull) +#define NIX_RX_PERRCODE_IL4_CHK (0x22ull) +#define NIX_RX_PERRCODE_IL4_PORT (0x23ull) + +#define NIX_SA_ALG_NON_MS (0x0ull) /* [CN10K, .) */ +#define NIX_SA_ALG_MS_CISCO (0x1ull) /* [CN10K, .) */ +#define NIX_SA_ALG_MS_VIPTELA (0x2ull) /* [CN10K, .) */ + +#define NIX_SENDCRCALG_CRC32 (0x0ull) +#define NIX_SENDCRCALG_CRC32C (0x1ull) +#define NIX_SENDCRCALG_ONES16 (0x2ull) + +#define NIX_SENDL3TYPE_NONE (0x0ull) +#define NIX_SENDL3TYPE_IP4 (0x2ull) +#define NIX_SENDL3TYPE_IP4_CKSUM (0x3ull) +#define NIX_SENDL3TYPE_IP6 (0x4ull) + +#define NIX_SENDL4TYPE_NONE (0x0ull) +#define NIX_SENDL4TYPE_TCP_CKSUM (0x1ull) +#define NIX_SENDL4TYPE_SCTP_CKSUM (0x2ull) +#define NIX_SENDL4TYPE_UDP_CKSUM (0x3ull) + +#define NIX_SENDLDTYPE_LDD (0x0ull) +#define NIX_SENDLDTYPE_LDT (0x1ull) +#define NIX_SENDLDTYPE_LDWB (0x2ull) + +#define NIX_XQESZ_W64 (0x0ull) +#define NIX_XQESZ_W16 (0x1ull) + +#define NIX_XQE_TYPE_INVALID (0x0ull) +#define NIX_XQE_TYPE_RX (0x1ull) +#define NIX_XQE_TYPE_RX_IPSECS (0x2ull) +#define NIX_XQE_TYPE_RX_IPSECH (0x3ull) +#define NIX_XQE_TYPE_RX_IPSECD (0x4ull) +#define NIX_XQE_TYPE_RX_VWQE (0x5ull) /* [CN10K, .) */ +#define NIX_XQE_TYPE_RES_6 (0x6ull) +#define NIX_XQE_TYPE_RES_7 (0x7ull) +#define NIX_XQE_TYPE_SEND (0x8ull) +#define NIX_XQE_TYPE_RES_9 (0x9ull) +#define NIX_XQE_TYPE_RES_A (0xAull) +#define NIX_XQE_TYPE_RES_B (0xBull) +#define NIX_XQE_TYPE_RES_C (0xCull) +#define NIX_XQE_TYPE_RES_D (0xDull) +#define NIX_XQE_TYPE_RES_E (0xEull) +#define NIX_XQE_TYPE_RES_F (0xFull) + +#define NIX_TX_VTAGOP_NOP (0x0ull) +#define NIX_TX_VTAGOP_INSERT (0x1ull) +#define NIX_TX_VTAGOP_REPLACE (0x2ull) + +#define NIX_VTAGSIZE_T4 (0x0ull) +#define NIX_VTAGSIZE_T8 (0x1ull) + +#define NIX_TXLAYER_OL3 (0x0ull) +#define NIX_TXLAYER_OL4 (0x1ull) +#define NIX_TXLAYER_IL3 (0x2ull) +#define NIX_TXLAYER_IL4 (0x3ull) + +#define NIX_TX_ACTIONOP_DROP (0x0ull) +#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull) +#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull) +#define NIX_TX_ACTIONOP_MCAST (0x3ull) +#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull) + +#define NIX_AQ_COMP_NOTDONE (0x0ull) +#define NIX_AQ_COMP_GOOD (0x1ull) +#define NIX_AQ_COMP_SWERR (0x2ull) +#define NIX_AQ_COMP_CTX_POISON (0x3ull) +#define NIX_AQ_COMP_CTX_FAULT (0x4ull) +#define NIX_AQ_COMP_LOCKERR (0x5ull) +#define NIX_AQ_COMP_SQB_ALLOC_FAIL (0x6ull) + +#define NIX_AF_INT_VEC_RVU (0x0ull) +#define NIX_AF_INT_VEC_GEN (0x1ull) +#define NIX_AF_INT_VEC_AQ_DONE (0x2ull) +#define NIX_AF_INT_VEC_AF_ERR (0x3ull) +#define NIX_AF_INT_VEC_POISON (0x4ull) + +#define NIX_AQINT_GEN_RX_MCAST_DROP (0x0ull) +#define NIX_AQINT_GEN_RX_MIRROR_DROP (0x1ull) +#define NIX_AQINT_GEN_TL1_DRAIN (0x3ull) +#define NIX_AQINT_GEN_SMQ_FLUSH_DONE (0x4ull) + +#define NIX_AQ_INSTOP_NOP (0x0ull) +#define NIX_AQ_INSTOP_INIT (0x1ull) +#define NIX_AQ_INSTOP_WRITE (0x2ull) +#define NIX_AQ_INSTOP_READ (0x3ull) +#define NIX_AQ_INSTOP_LOCK (0x4ull) +#define NIX_AQ_INSTOP_UNLOCK (0x5ull) + +#define NIX_AQ_CTYPE_RQ (0x0ull) +#define NIX_AQ_CTYPE_SQ (0x1ull) +#define NIX_AQ_CTYPE_CQ (0x2ull) +#define NIX_AQ_CTYPE_MCE (0x3ull) +#define NIX_AQ_CTYPE_RSS (0x4ull) +#define NIX_AQ_CTYPE_DYNO (0x5ull) +#define NIX_AQ_CTYPE_BAND_PROF (0x6ull) /* [CN10K, .) */ + +#define NIX_COLORRESULT_GREEN (0x0ull) +#define NIX_COLORRESULT_YELLOW (0x1ull) +#define NIX_COLORRESULT_RED_SEND (0x2ull) +#define NIX_COLORRESULT_RED_DROP (0x3ull) + +#define NIX_CHAN_LBKX_CHX(a, b) \ + (0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b)) +#define NIX_CHAN_CPT_CH_END (0x4ffull) /* [CN10K, .) */ +#define NIX_CHAN_CPT_CH_START (0x400ull) /* [CN10K, .) */ +#define NIX_CHAN_R4 (0x400ull) /* [CN9K, CN10K) */ +#define NIX_CHAN_R5 (0x500ull) +#define NIX_CHAN_R6 (0x600ull) +#define NIX_CHAN_SDP_CH_END (0x7ffull) +#define NIX_CHAN_SDP_CH_START (0x700ull) +/* [CN9K, CN10K) */ +#define NIX_CHAN_CGXX_LMACX_CHX(a, b, c) \ + (0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c)) +/* [CN10K, .) */ +#define NIX_CHAN_RPMX_LMACX_CHX(a, b, c) \ + (0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c)) + +#define NIX_INTF_SDP (0x4ull) +#define NIX_INTF_CGX0 (0x0ull) /* [CN9K, CN10K) */ +#define NIX_INTF_CGX1 (0x1ull) /* [CN9K, CN10K) */ +#define NIX_INTF_CGX2 (0x2ull) /* [CN9K, CN10K) */ +#define NIX_INTF_RPM0 (0x0ull) /* [CN10K, .) */ +#define NIX_INTF_RPM1 (0x1ull) /* [CN10K, .) */ +#define NIX_INTF_RPM2 (0x2ull) /* [CN10K, .) */ +#define NIX_INTF_LBK0 (0x3ull) +#define NIX_INTF_CPT0 (0x5ull) /* [CN10K, .) */ + +#define NIX_CQERRINT_DOOR_ERR (0x0ull) +#define NIX_CQERRINT_WR_FULL (0x1ull) +#define NIX_CQERRINT_CQE_FAULT (0x2ull) + +#define NIX_LINK_SDP (0xdull) /* [CN10K, .) */ +#define NIX_LINK_CPT (0xeull) /* [CN10K, .) */ +#define NIX_LINK_MC (0xfull) /* [CN10K, .) */ +/* [CN10K, .) */ +#define NIX_LINK_RPMX_LMACX(a, b) \ + (0x00ull | ((uint64_t)(a) << 2) | (uint64_t)(b)) +#define NIX_LINK_LBK0 (0xcull) + +#define NIX_LF_INT_VEC_GINT (0x80ull) +#define NIX_LF_INT_VEC_ERR_INT (0x81ull) +#define NIX_LF_INT_VEC_POISON (0x82ull) +#define NIX_LF_INT_VEC_QINT_END (0x3full) +#define NIX_LF_INT_VEC_QINT_START (0x0ull) +#define NIX_LF_INT_VEC_CINT_END (0x7full) +#define NIX_LF_INT_VEC_CINT_START (0x40ull) + +#define NIX_INTF_RX (0x0ull) +#define NIX_INTF_TX (0x1ull) + +/* Enums definitions */ + +/* Structures definitions */ + +/* NIX aging and send stats subdescriptor structure */ +struct nix_age_and_send_stats_s { + uint64_t threshold : 29; + uint64_t latency_drop : 1; + uint64_t aging : 1; + uint64_t wmem : 1; + uint64_t ooffset : 12; + uint64_t ioffset : 12; + uint64_t sel : 1; + uint64_t alg : 3; + uint64_t subdc : 4; + uint64_t addr : 64; /* W1 */ +}; + +/* NIX admin queue instruction structure */ +struct nix_aq_inst_s { + uint64_t op : 4; + uint64_t ctype : 4; + uint64_t lf : 7; + uint64_t rsvd_23_15 : 9; + uint64_t cindex : 20; + uint64_t rsvd_62_44 : 19; + uint64_t doneint : 1; + uint64_t res_addr : 64; /* W1 */ +}; + +/* NIX admin queue result structure */ +struct nix_aq_res_s { + uint64_t op : 4; + uint64_t ctype : 4; + uint64_t compcode : 8; + uint64_t doneint : 1; + uint64_t rsvd_63_17 : 47; + uint64_t rsvd_127_64 : 64; /* W1 */ +}; + +/* NIX bandwidth profile structure */ +struct nix_band_prof_s { + uint64_t pc_mode : 2; + uint64_t icolor : 2; + uint64_t tnl_ena : 1; + uint64_t rsvd_7_5 : 3; + uint64_t peir_exponent : 5; + uint64_t rsvd_15_13 : 3; + uint64_t pebs_exponent : 5; + uint64_t rsvd_23_21 : 3; + uint64_t cir_exponent : 5; + uint64_t rsvd_31_29 : 3; + uint64_t cbs_exponent : 5; + uint64_t rsvd_39_37 : 3; + uint64_t peir_mantissa : 8; + uint64_t pebs_mantissa : 8; + uint64_t cir_mantissa : 8; + uint64_t cbs_mantissa : 8; + uint64_t lmode : 1; + uint64_t l_sellect : 3; + uint64_t rdiv : 4; + uint64_t adjust_exponent : 5; + uint64_t rsvd_86_85 : 2; + uint64_t adjust_mantissa : 9; + uint64_t gc_action : 2; + uint64_t yc_action : 2; + uint64_t rc_action : 2; + uint64_t meter_algo : 2; + uint64_t band_prof_id : 7; + uint64_t rsvd_118_111 : 8; + uint64_t hl_en : 1; + uint64_t rsvd_127_120 : 8; + uint64_t ts : 48; + uint64_t rsvd_191_176 : 16; + uint64_t pe_accum : 32; + uint64_t c_accum : 32; + uint64_t green_pkt_pass : 48; + uint64_t rsvd_319_304 : 16; + uint64_t yellow_pkt_pass : 48; + uint64_t rsvd_383_368 : 16; + uint64_t red_pkt_pass : 48; + uint64_t rsvd_447_432 : 16; + uint64_t green_octs_pass : 48; + uint64_t rsvd_511_496 : 16; + uint64_t yellow_octs_pass : 48; + uint64_t rsvd_575_560 : 16; + uint64_t red_octs_pass : 48; + uint64_t rsvd_639_624 : 16; + uint64_t green_pkt_drop : 48; + uint64_t rsvd_703_688 : 16; + uint64_t yellow_pkt_drop : 48; + uint64_t rsvd_767_752 : 16; + uint64_t red_pkt_drop : 48; + uint64_t rsvd_831_816 : 16; + uint64_t green_octs_drop : 48; + uint64_t rsvd_895_880 : 16; + uint64_t yellow_octs_drop : 48; + uint64_t rsvd_959_944 : 16; + uint64_t red_octs_drop : 48; + uint64_t rsvd_1023_1008 : 16; +}; + +/* NIX completion interrupt context hardware structure */ +struct nix_cint_hw_s { + uint64_t ecount : 32; + uint64_t qcount : 16; + uint64_t intr : 1; + uint64_t ena : 1; + uint64_t timer_idx : 8; + uint64_t rsvd_63_58 : 6; + uint64_t ecount_wait : 32; + uint64_t qcount_wait : 16; + uint64_t time_wait : 8; + uint64_t rsvd_127_120 : 8; +}; + +/* NIX completion queue entry header structure */ +struct nix_cqe_hdr_s { + uint64_t tag : 32; + uint64_t q : 20; + uint64_t rsvd_57_52 : 6; + uint64_t node : 2; + uint64_t cqe_type : 4; +}; + +/* NIX completion queue context structure */ +struct nix_cq_ctx_s { + uint64_t base : 64; /* W0 */ + uint64_t rsvd_67_64 : 4; + uint64_t bp_ena : 1; + uint64_t rsvd_71_69 : 3; + uint64_t bpid : 9; + uint64_t rsvd_83_81 : 3; + uint64_t qint_idx : 7; + uint64_t cq_err : 1; + uint64_t cint_idx : 7; + uint64_t avg_con : 9; + uint64_t wrptr : 20; + uint64_t tail : 20; + uint64_t head : 20; + uint64_t avg_level : 8; + uint64_t update_time : 16; + uint64_t bp : 8; + uint64_t drop : 8; + uint64_t drop_ena : 1; + uint64_t ena : 1; + uint64_t rsvd_211_210 : 2; + uint64_t substream : 20; + uint64_t caching : 1; + uint64_t rsvd_235_233 : 3; + uint64_t qsize : 4; + uint64_t cq_err_int : 8; + uint64_t cq_err_int_ena : 8; +}; + +/* NIX instruction header structure */ +struct nix_inst_hdr_s { + uint64_t pf_func : 16; + uint64_t sq : 20; + uint64_t rsvd_63_36 : 28; +}; + +/* NIX i/o virtual address structure */ +struct nix_iova_s { + uint64_t addr : 64; /* W0 */ +}; + +/* NIX IPsec dynamic ordering counter structure */ +struct nix_ipsec_dyno_s { + uint32_t count : 32; /* W0 */ +}; + +/* NIX memory value structure */ +struct nix_mem_result_s { + uint64_t v : 1; + uint64_t color : 2; + uint64_t rsvd_63_3 : 61; +}; + +/* NIX statistics operation write data structure */ +struct nix_op_q_wdata_s { + uint64_t rsvd_31_0 : 32; + uint64_t q : 20; + uint64_t rsvd_63_52 : 12; +}; + +/* NIX queue interrupt context hardware structure */ +struct nix_qint_hw_s { + uint32_t count : 22; + uint32_t rsvd_30_22 : 9; + uint32_t ena : 1; +}; + +/* [CN10K, .) NIX receive queue context structure */ +struct nix_cn10k_rq_ctx_hw_s { + uint64_t ena : 1; + uint64_t sso_ena : 1; + uint64_t ipsech_ena : 1; + uint64_t ena_wqwd : 1; + uint64_t cq : 20; + uint64_t rsvd_36_24 : 13; + uint64_t lenerr_dis : 1; + uint64_t csum_il4_dis : 1; + uint64_t csum_ol4_dis : 1; + uint64_t len_il4_dis : 1; + uint64_t len_il3_dis : 1; + uint64_t len_ol4_dis : 1; + uint64_t len_ol3_dis : 1; + uint64_t wqe_aura : 20; + uint64_t spb_aura : 20; + uint64_t lpb_aura : 20; + uint64_t sso_grp : 10; + uint64_t sso_tt : 2; + uint64_t pb_caching : 2; + uint64_t wqe_caching : 1; + uint64_t xqe_drop_ena : 1; + uint64_t spb_drop_ena : 1; + uint64_t lpb_drop_ena : 1; + uint64_t pb_stashing : 1; + uint64_t ipsecd_drop_en : 1; + uint64_t chi_ena : 1; + uint64_t rsvd_127_125 : 3; + uint64_t band_prof_id : 10; + uint64_t rsvd_138 : 1; + uint64_t policer_ena : 1; + uint64_t spb_sizem1 : 6; + uint64_t wqe_skip : 2; + uint64_t spb_high_sizem1 : 3; + uint64_t spb_ena : 1; + uint64_t lpb_sizem1 : 12; + uint64_t first_skip : 7; + uint64_t rsvd_171 : 1; + uint64_t later_skip : 6; + uint64_t xqe_imm_size : 6; + uint64_t rsvd_189_184 : 6; + uint64_t xqe_imm_copy : 1; + uint64_t xqe_hdr_split : 1; + uint64_t xqe_drop : 8; + uint64_t xqe_pass : 8; + uint64_t wqe_pool_drop : 8; + uint64_t wqe_pool_pass : 8; + uint64_t spb_aura_drop : 8; + uint64_t spb_aura_pass : 8; + uint64_t spb_pool_drop : 8; + uint64_t spb_pool_pass : 8; + uint64_t lpb_aura_drop : 8; + uint64_t lpb_aura_pass : 8; + uint64_t lpb_pool_drop : 8; + uint64_t lpb_pool_pass : 8; + uint64_t rsvd_319_288 : 32; + uint64_t ltag : 24; + uint64_t good_utag : 8; + uint64_t bad_utag : 8; + uint64_t flow_tagw : 6; + uint64_t ipsec_vwqe : 1; + uint64_t vwqe_ena : 1; + uint64_t vtime_wait : 8; + uint64_t max_vsize_exp : 4; + uint64_t vwqe_skip : 2; + uint64_t rsvd_383_382 : 2; + uint64_t octs : 48; + uint64_t rsvd_447_432 : 16; + uint64_t pkts : 48; + uint64_t rsvd_511_496 : 16; + uint64_t drop_octs : 48; + uint64_t rsvd_575_560 : 16; + uint64_t drop_pkts : 48; + uint64_t rsvd_639_624 : 16; + uint64_t re_pkts : 48; + uint64_t rsvd_702_688 : 15; + uint64_t ena_copy : 1; + uint64_t rsvd_739_704 : 36; + uint64_t rq_int : 8; + uint64_t rq_int_ena : 8; + uint64_t qint_idx : 7; + uint64_t rsvd_767_763 : 5; + uint64_t rsvd_831_768 : 64; /* W12 */ + uint64_t rsvd_895_832 : 64; /* W13 */ + uint64_t rsvd_959_896 : 64; /* W14 */ + uint64_t rsvd_1023_960 : 64; /* W15 */ +}; + +/* NIX receive queue context structure */ +struct nix_rq_ctx_hw_s { + uint64_t ena : 1; + uint64_t sso_ena : 1; + uint64_t ipsech_ena : 1; + uint64_t ena_wqwd : 1; + uint64_t cq : 20; + uint64_t substream : 20; + uint64_t wqe_aura : 20; + uint64_t spb_aura : 20; + uint64_t lpb_aura : 20; + uint64_t sso_grp : 10; + uint64_t sso_tt : 2; + uint64_t pb_caching : 2; + uint64_t wqe_caching : 1; + uint64_t xqe_drop_ena : 1; + uint64_t spb_drop_ena : 1; + uint64_t lpb_drop_ena : 1; + uint64_t wqe_skip : 2; + uint64_t rsvd_127_124 : 4; + uint64_t rsvd_139_128 : 12; + uint64_t spb_sizem1 : 6; + uint64_t rsvd_150_146 : 5; + uint64_t spb_ena : 1; + uint64_t lpb_sizem1 : 12; + uint64_t first_skip : 7; + uint64_t rsvd_171 : 1; + uint64_t later_skip : 6; + uint64_t xqe_imm_size : 6; + uint64_t rsvd_189_184 : 6; + uint64_t xqe_imm_copy : 1; + uint64_t xqe_hdr_split : 1; + uint64_t xqe_drop : 8; + uint64_t xqe_pass : 8; + uint64_t wqe_pool_drop : 8; + uint64_t wqe_pool_pass : 8; + uint64_t spb_aura_drop : 8; + uint64_t spb_aura_pass : 8; + uint64_t spb_pool_drop : 8; + uint64_t spb_pool_pass : 8; + uint64_t lpb_aura_drop : 8; + uint64_t lpb_aura_pass : 8; + uint64_t lpb_pool_drop : 8; + uint64_t lpb_pool_pass : 8; + uint64_t rsvd_319_288 : 32; + uint64_t ltag : 24; + uint64_t good_utag : 8; + uint64_t bad_utag : 8; + uint64_t flow_tagw : 6; + uint64_t rsvd_383_366 : 18; + uint64_t octs : 48; + uint64_t rsvd_447_432 : 16; + uint64_t pkts : 48; + uint64_t rsvd_511_496 : 16; + uint64_t drop_octs : 48; + uint64_t rsvd_575_560 : 16; + uint64_t drop_pkts : 48; + uint64_t rsvd_639_624 : 16; + uint64_t re_pkts : 48; + uint64_t rsvd_702_688 : 15; + uint64_t ena_copy : 1; + uint64_t rsvd_739_704 : 36; + uint64_t rq_int : 8; + uint64_t rq_int_ena : 8; + uint64_t qint_idx : 7; + uint64_t rsvd_767_763 : 5; + uint64_t rsvd_831_768 : 64; /* W12 */ + uint64_t rsvd_895_832 : 64; /* W13 */ + uint64_t rsvd_959_896 : 64; /* W14 */ + uint64_t rsvd_1023_960 : 64; /* W15 */ +}; + +/* [CN10K, .) NIX Receive queue context structure */ +struct nix_cn10k_rq_ctx_s { + uint64_t ena : 1; + uint64_t sso_ena : 1; + uint64_t ipsech_ena : 1; + uint64_t ena_wqwd : 1; + uint64_t cq : 20; + uint64_t rsvd_36_24 : 13; + uint64_t lenerr_dis : 1; + uint64_t csum_il4_dis : 1; + uint64_t csum_ol4_dis : 1; + uint64_t len_il4_dis : 1; + uint64_t len_il3_dis : 1; + uint64_t len_ol4_dis : 1; + uint64_t len_ol3_dis : 1; + uint64_t wqe_aura : 20; + uint64_t spb_aura : 20; + uint64_t lpb_aura : 20; + uint64_t sso_grp : 10; + uint64_t sso_tt : 2; + uint64_t pb_caching : 2; + uint64_t wqe_caching : 1; + uint64_t xqe_drop_ena : 1; + uint64_t spb_drop_ena : 1; + uint64_t lpb_drop_ena : 1; + uint64_t pb_stashing : 1; + uint64_t ipsecd_drop_en : 1; + uint64_t chi_ena : 1; + uint64_t rsvd_127_125 : 3; + uint64_t band_prof_id : 10; + uint64_t rsvd_138 : 1; + uint64_t policer_ena : 1; + uint64_t spb_sizem1 : 6; + uint64_t wqe_skip : 2; + uint64_t spb_high_sizem1 : 3; + uint64_t spb_ena : 1; + uint64_t lpb_sizem1 : 12; + uint64_t first_skip : 7; + uint64_t rsvd_171 : 1; + uint64_t later_skip : 6; + uint64_t xqe_imm_size : 6; + uint64_t rsvd_189_184 : 6; + uint64_t xqe_imm_copy : 1; + uint64_t xqe_hdr_split : 1; + uint64_t xqe_drop : 8; + uint64_t xqe_pass : 8; + uint64_t wqe_pool_drop : 8; + uint64_t wqe_pool_pass : 8; + uint64_t spb_aura_drop : 8; + uint64_t spb_aura_pass : 8; + uint64_t spb_pool_drop : 8; + uint64_t spb_pool_pass : 8; + uint64_t lpb_aura_drop : 8; + uint64_t lpb_aura_pass : 8; + uint64_t lpb_pool_drop : 8; + uint64_t lpb_pool_pass : 8; + uint64_t rsvd_291_288 : 4; + uint64_t rq_int : 8; + uint64_t rq_int_ena : 8; + uint64_t qint_idx : 7; + uint64_t rsvd_319_315 : 5; + uint64_t ltag : 24; + uint64_t good_utag : 8; + uint64_t bad_utag : 8; + uint64_t flow_tagw : 6; + uint64_t ipsec_vwqe : 1; + uint64_t vwqe_ena : 1; + uint64_t vtime_wait : 8; + uint64_t max_vsize_exp : 4; + uint64_t vwqe_skip : 2; + uint64_t rsvd_383_382 : 2; + uint64_t octs : 48; + uint64_t rsvd_447_432 : 16; + uint64_t pkts : 48; + uint64_t rsvd_511_496 : 16; + uint64_t drop_octs : 48; + uint64_t rsvd_575_560 : 16; + uint64_t drop_pkts : 48; + uint64_t rsvd_639_624 : 16; + uint64_t re_pkts : 48; + uint64_t rsvd_703_688 : 16; + uint64_t rsvd_767_704 : 64; /* W11 */ + uint64_t rsvd_831_768 : 64; /* W12 */ + uint64_t rsvd_895_832 : 64; /* W13 */ + uint64_t rsvd_959_896 : 64; /* W14 */ + uint64_t rsvd_1023_960 : 64; /* W15 */ +}; + +/* NIX receive queue context structure */ +struct nix_rq_ctx_s { + uint64_t ena : 1; + uint64_t sso_ena : 1; + uint64_t ipsech_ena : 1; + uint64_t ena_wqwd : 1; + uint64_t cq : 20; + uint64_t substream : 20; + uint64_t wqe_aura : 20; + uint64_t spb_aura : 20; + uint64_t lpb_aura : 20; + uint64_t sso_grp : 10; + uint64_t sso_tt : 2; + uint64_t pb_caching : 2; + uint64_t wqe_caching : 1; + uint64_t xqe_drop_ena : 1; + uint64_t spb_drop_ena : 1; + uint64_t lpb_drop_ena : 1; + uint64_t rsvd_127_122 : 6; + uint64_t rsvd_139_128 : 12; + uint64_t spb_sizem1 : 6; + uint64_t wqe_skip : 2; + uint64_t rsvd_150_148 : 3; + uint64_t spb_ena : 1; + uint64_t lpb_sizem1 : 12; + uint64_t first_skip : 7; + uint64_t rsvd_171 : 1; + uint64_t later_skip : 6; + uint64_t xqe_imm_size : 6; + uint64_t rsvd_189_184 : 6; + uint64_t xqe_imm_copy : 1; + uint64_t xqe_hdr_split : 1; + uint64_t xqe_drop : 8; + uint64_t xqe_pass : 8; + uint64_t wqe_pool_drop : 8; + uint64_t wqe_pool_pass : 8; + uint64_t spb_aura_drop : 8; + uint64_t spb_aura_pass : 8; + uint64_t spb_pool_drop : 8; + uint64_t spb_pool_pass : 8; + uint64_t lpb_aura_drop : 8; + uint64_t lpb_aura_pass : 8; + uint64_t lpb_pool_drop : 8; + uint64_t lpb_pool_pass : 8; + uint64_t rsvd_291_288 : 4; + uint64_t rq_int : 8; + uint64_t rq_int_ena : 8; + uint64_t qint_idx : 7; + uint64_t rsvd_319_315 : 5; + uint64_t ltag : 24; + uint64_t good_utag : 8; + uint64_t bad_utag : 8; + uint64_t flow_tagw : 6; + uint64_t rsvd_383_366 : 18; + uint64_t octs : 48; + uint64_t rsvd_447_432 : 16; + uint64_t pkts : 48; + uint64_t rsvd_511_496 : 16; + uint64_t drop_octs : 48; + uint64_t rsvd_575_560 : 16; + uint64_t drop_pkts : 48; + uint64_t rsvd_639_624 : 16; + uint64_t re_pkts : 48; + uint64_t rsvd_703_688 : 16; + uint64_t rsvd_767_704 : 64; /* W11 */ + uint64_t rsvd_831_768 : 64; /* W12 */ + uint64_t rsvd_895_832 : 64; /* W13 */ + uint64_t rsvd_959_896 : 64; /* W14 */ + uint64_t rsvd_1023_960 : 64; /* W15 */ +}; + +/* NIX receive side scaling entry structure */ +struct nix_rsse_s { + uint32_t rq : 20; + uint32_t rsvd_31_20 : 12; +}; + +/* NIX receive action structure */ +struct nix_rx_action_s { + uint64_t op : 4; + uint64_t pf_func : 16; + uint64_t index : 20; + uint64_t match_id : 16; + uint64_t flow_key_alg : 5; + uint64_t rsvd_63_61 : 3; +}; + +/* NIX receive immediate sub descriptor structure */ +struct nix_rx_imm_s { + uint64_t size : 16; + uint64_t apad : 3; + uint64_t rsvd_59_19 : 41; + uint64_t subdc : 4; +}; + +/* NIX receive multicast/mirror entry structure */ +struct nix_rx_mce_s { + uint64_t op : 2; + uint64_t rsvd_2 : 1; + uint64_t eol : 1; + uint64_t index : 20; + uint64_t rsvd_31_24 : 8; + uint64_t pf_func : 16; + uint64_t next : 16; +}; + +/* NIX receive parse structure */ +union nix_rx_parse_u { + struct { + uint64_t chan : 12; + uint64_t desc_sizem1 : 5; + uint64_t imm_copy : 1; + uint64_t express : 1; + uint64_t wqwd : 1; + uint64_t errlev : 4; + uint64_t errcode : 8; + uint64_t latype : 4; + uint64_t lbtype : 4; + uint64_t lctype : 4; + uint64_t ldtype : 4; + uint64_t letype : 4; + uint64_t lftype : 4; + uint64_t lgtype : 4; + uint64_t lhtype : 4; + uint64_t pkt_lenm1 : 16; + uint64_t l2m : 1; + uint64_t l2b : 1; + uint64_t l3m : 1; + uint64_t l3b : 1; + uint64_t vtag0_valid : 1; + uint64_t vtag0_gone : 1; + uint64_t vtag1_valid : 1; + uint64_t vtag1_gone : 1; + uint64_t pkind : 6; + uint64_t nix_idx : 2; + uint64_t vtag0_tci : 16; + uint64_t vtag1_tci : 16; + uint64_t laflags : 8; + uint64_t lbflags : 8; + uint64_t lcflags : 8; + uint64_t ldflags : 8; + uint64_t leflags : 8; + uint64_t lfflags : 8; + uint64_t lgflags : 8; + uint64_t lhflags : 8; + uint64_t eoh_ptr : 8; + uint64_t wqe_aura : 20; + uint64_t pb_aura : 20; + uint64_t match_id : 16; + uint64_t laptr : 8; + uint64_t lbptr : 8; + uint64_t lcptr : 8; + uint64_t ldptr : 8; + uint64_t leptr : 8; + uint64_t lfptr : 8; + uint64_t lgptr : 8; + uint64_t lhptr : 8; + uint64_t vtag0_ptr : 8; + uint64_t vtag1_ptr : 8; + uint64_t flow_key_alg : 5; + uint64_t rsvd_341 : 1; + uint64_t rsvd_349_342 : 8; + uint64_t rsvd_353_350 : 4; + uint64_t rsvd_359_354 : 6; + uint64_t color : 2; + uint64_t rsvd_381_362 : 20; + uint64_t rsvd_382 : 1; + uint64_t rsvd_383 : 1; + uint64_t rsvd_447_384 : 64; /* W6 */ + }; + struct { + uint64_t chan : 12; + uint64_t desc_sizem1 : 5; + uint64_t imm_copy : 1; + uint64_t express : 1; + uint64_t wqwd : 1; + uint64_t errlev : 4; + uint64_t errcode : 8; + uint64_t latype : 4; + uint64_t lbtype : 4; + uint64_t lctype : 4; + uint64_t ldtype : 4; + uint64_t letype : 4; + uint64_t lftype : 4; + uint64_t lgtype : 4; + uint64_t lhtype : 4; + uint64_t pkt_lenm1 : 16; + uint64_t l2m : 1; + uint64_t l2b : 1; + uint64_t l3m : 1; + uint64_t l3b : 1; + uint64_t vtag0_valid : 1; + uint64_t vtag0_gone : 1; + uint64_t vtag1_valid : 1; + uint64_t vtag1_gone : 1; + uint64_t pkind : 6; + uint64_t rsvd_95_94 : 2; + uint64_t vtag0_tci : 16; + uint64_t vtag1_tci : 16; + uint64_t laflags : 8; + uint64_t lbflags : 8; + uint64_t lcflags : 8; + uint64_t ldflags : 8; + uint64_t leflags : 8; + uint64_t lfflags : 8; + uint64_t lgflags : 8; + uint64_t lhflags : 8; + uint64_t eoh_ptr : 8; + uint64_t wqe_aura : 20; + uint64_t pb_aura : 20; + uint64_t match_id : 16; + uint64_t laptr : 8; + uint64_t lbptr : 8; + uint64_t lcptr : 8; + uint64_t ldptr : 8; + uint64_t leptr : 8; + uint64_t lfptr : 8; + uint64_t lgptr : 8; + uint64_t lhptr : 8; + uint64_t vtag0_ptr : 8; + uint64_t vtag1_ptr : 8; + uint64_t flow_key_alg : 5; + uint64_t rsvd_383_341 : 43; + uint64_t rsvd_447_384 : 64; /* W6 */ + } cn9k; +}; + +/* NIX receive scatter/gather sub descriptor structure */ +struct nix_rx_sg_s { + uint64_t seg1_size : 16; + uint64_t seg2_size : 16; + uint64_t seg3_size : 16; + uint64_t segs : 2; + uint64_t rsvd_59_50 : 10; + uint64_t subdc : 4; +}; + +/* NIX receive vtag action structure */ +union nix_rx_vtag_action_u { + struct { + uint64_t vtag0_relptr : 8; + uint64_t vtag0_lid : 3; + uint64_t sa_xor : 1; + uint64_t vtag0_type : 3; + uint64_t vtag0_valid : 1; + uint64_t sa_lo : 16; + uint64_t vtag1_relptr : 8; + uint64_t vtag1_lid : 3; + uint64_t rsvd_43 : 1; + uint64_t vtag1_type : 3; + uint64_t vtag1_valid : 1; + uint64_t sa_hi : 16; + }; + struct { + uint64_t vtag0_relptr : 8; + uint64_t vtag0_lid : 3; + uint64_t rsvd_11 : 1; + uint64_t vtag0_type : 3; + uint64_t vtag0_valid : 1; + uint64_t rsvd_31_16 : 16; + uint64_t vtag1_relptr : 8; + uint64_t vtag1_lid : 3; + uint64_t rsvd_43 : 1; + uint64_t vtag1_type : 3; + uint64_t vtag1_valid : 1; + uint64_t rsvd_63_48 : 16; + } cn9k; +}; + +/* NIX send completion structure */ +struct nix_send_comp_s { + uint64_t status : 8; + uint64_t sqe_id : 16; + uint64_t rsvd_63_24 : 40; +}; + +/* NIX send CRC sub descriptor structure */ +struct nix_send_crc_s { + uint64_t size : 16; + uint64_t start : 16; + uint64_t insert : 16; + uint64_t rsvd_57_48 : 10; + uint64_t alg : 2; + uint64_t subdc : 4; + uint64_t iv : 32; + uint64_t rsvd_127_96 : 32; +}; + +/* NIX send extended header sub descriptor structure */ +PLT_STD_C11 +union nix_send_ext_w0_u { + uint64_t u; + struct { + uint64_t lso_mps : 14; + uint64_t lso : 1; + uint64_t tstmp : 1; + uint64_t lso_sb : 8; + uint64_t lso_format : 5; + uint64_t rsvd_31_29 : 3; + uint64_t shp_chg : 9; + uint64_t shp_dis : 1; + uint64_t shp_ra : 2; + uint64_t markptr : 8; + uint64_t markform : 7; + uint64_t mark_en : 1; + uint64_t subdc : 4; + }; +}; + +PLT_STD_C11 +union nix_send_ext_w1_u { + uint64_t u; + struct { + uint64_t vlan0_ins_ptr : 8; + uint64_t vlan0_ins_tci : 16; + uint64_t vlan1_ins_ptr : 8; + uint64_t vlan1_ins_tci : 16; + uint64_t vlan0_ins_ena : 1; + uint64_t vlan1_ins_ena : 1; + uint64_t init_color : 2; + uint64_t rsvd_127_116 : 12; + }; + struct { + uint64_t vlan0_ins_ptr : 8; + uint64_t vlan0_ins_tci : 16; + uint64_t vlan1_ins_ptr : 8; + uint64_t vlan1_ins_tci : 16; + uint64_t vlan0_ins_ena : 1; + uint64_t vlan1_ins_ena : 1; + uint64_t rsvd_127_114 : 14; + } cn9k; +}; + +struct nix_send_ext_s { + union nix_send_ext_w0_u w0; + union nix_send_ext_w1_u w1; +}; + +/* NIX send header sub descriptor structure */ +PLT_STD_C11 +union nix_send_hdr_w0_u { + uint64_t u; + struct { + uint64_t total : 18; + uint64_t rsvd_18 : 1; + uint64_t df : 1; + uint64_t aura : 20; + uint64_t sizem1 : 3; + uint64_t pnc : 1; + uint64_t sq : 20; + }; +}; + +PLT_STD_C11 +union nix_send_hdr_w1_u { + uint64_t u; + struct { + uint64_t ol3ptr : 8; + uint64_t ol4ptr : 8; + uint64_t il3ptr : 8; + uint64_t il4ptr : 8; + uint64_t ol3type : 4; + uint64_t ol4type : 4; + uint64_t il3type : 4; + uint64_t il4type : 4; + uint64_t sqe_id : 16; + }; +}; + +struct nix_send_hdr_s { + union nix_send_hdr_w0_u w0; + union nix_send_hdr_w1_u w1; +}; + +/* NIX send immediate sub descriptor structure */ +struct nix_send_imm_s { + uint64_t size : 16; + uint64_t apad : 3; + uint64_t rsvd_59_19 : 41; + uint64_t subdc : 4; +}; + +/* NIX send jump sub descriptor structure */ +struct nix_send_jump_s { + uint64_t sizem1 : 7; + uint64_t rsvd_13_7 : 7; + uint64_t ld_type : 2; + uint64_t aura : 20; + uint64_t rsvd_58_36 : 23; + uint64_t f : 1; + uint64_t subdc : 4; + uint64_t addr : 64; /* W1 */ +}; + +/* NIX send memory sub descriptor structure */ +PLT_STD_C11 +union nix_send_mem_w0_u { + uint64_t u; + struct { + uint64_t offset : 16; + uint64_t rsvd_51_16 : 36; + uint64_t per_lso_seg : 1; + uint64_t wmem : 1; + uint64_t dsz : 2; + uint64_t alg : 4; + uint64_t subdc : 4; + }; + struct { + uint64_t offset : 16; + uint64_t rsvd_52_16 : 37; + uint64_t wmem : 1; + uint64_t dsz : 2; + uint64_t alg : 4; + uint64_t subdc : 4; + } cn9k; +}; + +struct nix_send_mem_s { + union nix_send_mem_w0_u w0; + uint64_t addr : 64; /* W1 */ +}; + +/* NIX send scatter/gather sub descriptor structure */ +PLT_STD_C11 +union nix_send_sg2_s { + uint64_t u; + struct { + uint64_t seg1_size : 16; + uint64_t aura : 20; + uint64_t i1 : 1; + uint64_t fabs : 1; + uint64_t foff : 8; + uint64_t rsvd_57_46 : 12; + uint64_t ld_type : 2; + uint64_t subdc : 4; + }; +}; + +PLT_STD_C11 +union nix_send_sg_s { + uint64_t u; + struct { + uint64_t seg1_size : 16; + uint64_t seg2_size : 16; + uint64_t seg3_size : 16; + uint64_t segs : 2; + uint64_t rsvd_54_50 : 5; + uint64_t i1 : 1; + uint64_t i2 : 1; + uint64_t i3 : 1; + uint64_t ld_type : 2; + uint64_t subdc : 4; + }; +}; + +/* NIX send work sub descriptor structure */ +struct nix_send_work_s { + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t rsvd_59_44 : 16; + uint64_t subdc : 4; + uint64_t addr : 64; /* W1 */ +}; + +/* [CN10K, .) NIX sq context hardware structure */ +struct nix_cn10k_sq_ctx_hw_s { + uint64_t ena : 1; + uint64_t substream : 20; + uint64_t max_sqe_size : 2; + uint64_t sqe_way_mask : 16; + uint64_t sqb_aura : 20; + uint64_t gbl_rsvd1 : 5; + uint64_t cq_id : 20; + uint64_t cq_ena : 1; + uint64_t qint_idx : 6; + uint64_t gbl_rsvd2 : 1; + uint64_t sq_int : 8; + uint64_t sq_int_ena : 8; + uint64_t xoff : 1; + uint64_t sqe_stype : 2; + uint64_t gbl_rsvd : 17; + uint64_t head_sqb : 64; /* W2 */ + uint64_t head_offset : 6; + uint64_t sqb_dequeue_count : 16; + uint64_t default_chan : 12; + uint64_t sdp_mcast : 1; + uint64_t sso_ena : 1; + uint64_t dse_rsvd1 : 28; + uint64_t sqb_enqueue_count : 16; + uint64_t tail_offset : 6; + uint64_t lmt_dis : 1; + uint64_t smq_rr_weight : 14; + uint64_t dnq_rsvd1 : 27; + uint64_t tail_sqb : 64; /* W5 */ + uint64_t next_sqb : 64; /* W6 */ + uint64_t smq : 10; + uint64_t smq_pend : 1; + uint64_t smq_next_sq : 20; + uint64_t smq_next_sq_vld : 1; + uint64_t mnq_dis : 1; + uint64_t scm1_rsvd2 : 31; + uint64_t smenq_sqb : 64; /* W8 */ + uint64_t smenq_offset : 6; + uint64_t cq_limit : 8; + uint64_t smq_rr_count : 32; + uint64_t scm_lso_rem : 18; + uint64_t smq_lso_segnum : 8; + uint64_t vfi_lso_total : 18; + uint64_t vfi_lso_sizem1 : 3; + uint64_t vfi_lso_sb : 8; + uint64_t vfi_lso_mps : 14; + uint64_t vfi_lso_vlan0_ins_ena : 1; + uint64_t vfi_lso_vlan1_ins_ena : 1; + uint64_t vfi_lso_vld : 1; + uint64_t smenq_next_sqb_vld : 1; + uint64_t scm_dq_rsvd1 : 9; + uint64_t smenq_next_sqb : 64; /* W11 */ + uint64_t age_drop_octs : 32; + uint64_t age_drop_pkts : 32; + uint64_t drop_pkts : 48; + uint64_t drop_octs_lsw : 16; + uint64_t drop_octs_msw : 32; + uint64_t pkts_lsw : 32; + uint64_t pkts_msw : 16; + uint64_t octs : 48; +}; + +/* NIX sq context hardware structure */ +struct nix_sq_ctx_hw_s { + uint64_t ena : 1; + uint64_t substream : 20; + uint64_t max_sqe_size : 2; + uint64_t sqe_way_mask : 16; + uint64_t sqb_aura : 20; + uint64_t gbl_rsvd1 : 5; + uint64_t cq_id : 20; + uint64_t cq_ena : 1; + uint64_t qint_idx : 6; + uint64_t gbl_rsvd2 : 1; + uint64_t sq_int : 8; + uint64_t sq_int_ena : 8; + uint64_t xoff : 1; + uint64_t sqe_stype : 2; + uint64_t gbl_rsvd : 17; + uint64_t head_sqb : 64; /* W2 */ + uint64_t head_offset : 6; + uint64_t sqb_dequeue_count : 16; + uint64_t default_chan : 12; + uint64_t sdp_mcast : 1; + uint64_t sso_ena : 1; + uint64_t dse_rsvd1 : 28; + uint64_t sqb_enqueue_count : 16; + uint64_t tail_offset : 6; + uint64_t lmt_dis : 1; + uint64_t smq_rr_quantum : 24; + uint64_t dnq_rsvd1 : 17; + uint64_t tail_sqb : 64; /* W5 */ + uint64_t next_sqb : 64; /* W6 */ + uint64_t mnq_dis : 1; + uint64_t smq : 9; + uint64_t smq_pend : 1; + uint64_t smq_next_sq : 20; + uint64_t smq_next_sq_vld : 1; + uint64_t scm1_rsvd2 : 32; + uint64_t smenq_sqb : 64; /* W8 */ + uint64_t smenq_offset : 6; + uint64_t cq_limit : 8; + uint64_t smq_rr_count : 25; + uint64_t scm_lso_rem : 18; + uint64_t scm_dq_rsvd0 : 7; + uint64_t smq_lso_segnum : 8; + uint64_t vfi_lso_total : 18; + uint64_t vfi_lso_sizem1 : 3; + uint64_t vfi_lso_sb : 8; + uint64_t vfi_lso_mps : 14; + uint64_t vfi_lso_vlan0_ins_ena : 1; + uint64_t vfi_lso_vlan1_ins_ena : 1; + uint64_t vfi_lso_vld : 1; + uint64_t smenq_next_sqb_vld : 1; + uint64_t scm_dq_rsvd1 : 9; + uint64_t smenq_next_sqb : 64; /* W11 */ + uint64_t seb_rsvd1 : 64; /* W12 */ + uint64_t drop_pkts : 48; + uint64_t drop_octs_lsw : 16; + uint64_t drop_octs_msw : 32; + uint64_t pkts_lsw : 32; + uint64_t pkts_msw : 16; + uint64_t octs : 48; +}; + +/* [CN10K, .) NIX Send queue context structure */ +struct nix_cn10k_sq_ctx_s { + uint64_t ena : 1; + uint64_t qint_idx : 6; + uint64_t substream : 20; + uint64_t sdp_mcast : 1; + uint64_t cq : 20; + uint64_t sqe_way_mask : 16; + uint64_t smq : 10; + uint64_t cq_ena : 1; + uint64_t xoff : 1; + uint64_t sso_ena : 1; + uint64_t smq_rr_weight : 14; + uint64_t default_chan : 12; + uint64_t sqb_count : 16; + uint64_t rsvd_120_119 : 2; + uint64_t smq_rr_count_lb : 7; + uint64_t smq_rr_count_ub : 25; + uint64_t sqb_aura : 20; + uint64_t sq_int : 8; + uint64_t sq_int_ena : 8; + uint64_t sqe_stype : 2; + uint64_t rsvd_191 : 1; + uint64_t max_sqe_size : 2; + uint64_t cq_limit : 8; + uint64_t lmt_dis : 1; + uint64_t mnq_dis : 1; + uint64_t smq_next_sq : 20; + uint64_t smq_lso_segnum : 8; + uint64_t tail_offset : 6; + uint64_t smenq_offset : 6; + uint64_t head_offset : 6; + uint64_t smenq_next_sqb_vld : 1; + uint64_t smq_pend : 1; + uint64_t smq_next_sq_vld : 1; + uint64_t rsvd_255_253 : 3; + uint64_t next_sqb : 64; /* W4 */ + uint64_t tail_sqb : 64; /* W5 */ + uint64_t smenq_sqb : 64; /* W6 */ + uint64_t smenq_next_sqb : 64; /* W7 */ + uint64_t head_sqb : 64; /* W8 */ + uint64_t rsvd_583_576 : 8; + uint64_t vfi_lso_total : 18; + uint64_t vfi_lso_sizem1 : 3; + uint64_t vfi_lso_sb : 8; + uint64_t vfi_lso_mps : 14; + uint64_t vfi_lso_vlan0_ins_ena : 1; + uint64_t vfi_lso_vlan1_ins_ena : 1; + uint64_t vfi_lso_vld : 1; + uint64_t rsvd_639_630 : 10; + uint64_t scm_lso_rem : 18; + uint64_t rsvd_703_658 : 46; + uint64_t octs : 48; + uint64_t rsvd_767_752 : 16; + uint64_t pkts : 48; + uint64_t rsvd_831_816 : 16; + uint64_t aged_drop_octs : 32; + uint64_t aged_drop_pkts : 32; + uint64_t drop_octs : 48; + uint64_t rsvd_959_944 : 16; + uint64_t drop_pkts : 48; + uint64_t rsvd_1023_1008 : 16; +}; + +/* NIX send queue context structure */ +struct nix_sq_ctx_s { + uint64_t ena : 1; + uint64_t qint_idx : 6; + uint64_t substream : 20; + uint64_t sdp_mcast : 1; + uint64_t cq : 20; + uint64_t sqe_way_mask : 16; + uint64_t smq : 9; + uint64_t cq_ena : 1; + uint64_t xoff : 1; + uint64_t sso_ena : 1; + uint64_t smq_rr_quantum : 24; + uint64_t default_chan : 12; + uint64_t sqb_count : 16; + uint64_t smq_rr_count : 25; + uint64_t sqb_aura : 20; + uint64_t sq_int : 8; + uint64_t sq_int_ena : 8; + uint64_t sqe_stype : 2; + uint64_t rsvd_191 : 1; + uint64_t max_sqe_size : 2; + uint64_t cq_limit : 8; + uint64_t lmt_dis : 1; + uint64_t mnq_dis : 1; + uint64_t smq_next_sq : 20; + uint64_t smq_lso_segnum : 8; + uint64_t tail_offset : 6; + uint64_t smenq_offset : 6; + uint64_t head_offset : 6; + uint64_t smenq_next_sqb_vld : 1; + uint64_t smq_pend : 1; + uint64_t smq_next_sq_vld : 1; + uint64_t rsvd_255_253 : 3; + uint64_t next_sqb : 64; /* W4 */ + uint64_t tail_sqb : 64; /* W5 */ + uint64_t smenq_sqb : 64; /* W6 */ + uint64_t smenq_next_sqb : 64; /* W7 */ + uint64_t head_sqb : 64; /* W8 */ + uint64_t rsvd_583_576 : 8; + uint64_t vfi_lso_total : 18; + uint64_t vfi_lso_sizem1 : 3; + uint64_t vfi_lso_sb : 8; + uint64_t vfi_lso_mps : 14; + uint64_t vfi_lso_vlan0_ins_ena : 1; + uint64_t vfi_lso_vlan1_ins_ena : 1; + uint64_t vfi_lso_vld : 1; + uint64_t rsvd_639_630 : 10; + uint64_t scm_lso_rem : 18; + uint64_t rsvd_703_658 : 46; + uint64_t octs : 48; + uint64_t rsvd_767_752 : 16; + uint64_t pkts : 48; + uint64_t rsvd_831_816 : 16; + uint64_t rsvd_895_832 : 64; /* W13 */ + uint64_t drop_octs : 48; + uint64_t rsvd_959_944 : 16; + uint64_t drop_pkts : 48; + uint64_t rsvd_1023_1008 : 16; +}; + +/* NIX transmit action structure */ +struct nix_tx_action_s { + uint64_t op : 4; + uint64_t rsvd_11_4 : 8; + uint64_t index : 20; + uint64_t match_id : 16; + uint64_t rsvd_63_48 : 16; +}; + +/* NIX transmit vtag action structure */ +struct nix_tx_vtag_action_s { + uint64_t vtag0_relptr : 8; + uint64_t vtag0_lid : 3; + uint64_t rsvd_11 : 1; + uint64_t vtag0_op : 2; + uint64_t rsvd_15_14 : 2; + uint64_t vtag0_def : 10; + uint64_t rsvd_31_26 : 6; + uint64_t vtag1_relptr : 8; + uint64_t vtag1_lid : 3; + uint64_t rsvd_43 : 1; + uint64_t vtag1_op : 2; + uint64_t rsvd_47_46 : 2; + uint64_t vtag1_def : 10; + uint64_t rsvd_63_58 : 6; +}; + +/* NIX work queue entry header structure */ +struct nix_wqe_hdr_s { + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t node : 2; + uint64_t q : 14; + uint64_t wqe_type : 4; +}; + +/* NIX Rx flow key algorithm field structure */ +struct nix_rx_flowkey_alg { + uint64_t key_offset : 6; + uint64_t ln_mask : 1; + uint64_t fn_mask : 1; + uint64_t hdr_offset : 8; + uint64_t bytesm1 : 5; + uint64_t lid : 3; + uint64_t reserved_24_24 : 1; + uint64_t ena : 1; + uint64_t sel_chan : 1; + uint64_t ltype_mask : 4; + uint64_t ltype_match : 4; + uint64_t reserved_35_63 : 29; +}; + +/* NIX LSO format field structure */ +struct nix_lso_format { + uint64_t offset : 8; + uint64_t layer : 2; + uint64_t rsvd_10_11 : 2; + uint64_t sizem1 : 2; + uint64_t rsvd_14_15 : 2; + uint64_t alg : 3; + uint64_t rsvd_19_63 : 45; +}; + +#define NIX_LSO_FIELD_MAX (8) +#define NIX_LSO_FIELD_ALG_MASK GENMASK(18, 16) +#define NIX_LSO_FIELD_SZ_MASK GENMASK(13, 12) +#define NIX_LSO_FIELD_LY_MASK GENMASK(9, 8) +#define NIX_LSO_FIELD_OFF_MASK GENMASK(7, 0) + +#define NIX_LSO_FIELD_MASK \ + (NIX_LSO_FIELD_OFF_MASK | NIX_LSO_FIELD_LY_MASK | \ + NIX_LSO_FIELD_SZ_MASK | NIX_LSO_FIELD_ALG_MASK) + +#define NIX_CN9K_MAX_HW_FRS 9212UL +#define NIX_LBK_MAX_HW_FRS 65535UL +#define NIX_RPM_MAX_HW_FRS 16380UL +#define NIX_MIN_HW_FRS 60UL + +/* NIX rate limits */ +#define NIX_TM_MAX_RATE_DIV_EXP 12 +#define NIX_TM_MAX_RATE_EXPONENT 0xf +#define NIX_TM_MAX_RATE_MANTISSA 0xff + +#define NIX_TM_SHAPER_RATE_CONST ((uint64_t)2E6) + +/* NIX rate calculation in Bits/Sec + * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA]) + * << NIX_*_PIR[RATE_EXPONENT]) / 256 + * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT])) + * + * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA]) + * << NIX_*_CIR[RATE_EXPONENT]) / 256 + * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT])) + */ +#define NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp) \ + ((NIX_TM_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent))) / \ + (((1ull << (div_exp)) * 256))) + +/* Rate limit in Bits/Sec */ +#define NIX_TM_MIN_SHAPER_RATE NIX_TM_SHAPER_RATE(0, 0, NIX_TM_MAX_RATE_DIV_EXP) + +#define NIX_TM_MAX_SHAPER_RATE \ + NIX_TM_SHAPER_RATE(NIX_TM_MAX_RATE_EXPONENT, NIX_TM_MAX_RATE_MANTISSA, \ + 0) + +/* NIX burst limits */ +#define NIX_TM_MAX_BURST_EXPONENT 0xf +#define NIX_TM_MAX_BURST_MANTISSA 0xff + +/* NIX burst calculation + * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA]) + * << (NIX_*_PIR[BURST_EXPONENT] + 1)) + * / 256 + * + * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA]) + * << (NIX_*_CIR[BURST_EXPONENT] + 1)) + * / 256 + */ +#define NIX_TM_SHAPER_BURST(exponent, mantissa) \ + (((256 + (mantissa)) << ((exponent) + 1)) / 256) + +/* Burst limit in Bytes */ +#define NIX_TM_MIN_SHAPER_BURST NIX_TM_SHAPER_BURST(0, 0) + +#define NIX_TM_MAX_SHAPER_BURST \ + NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ + NIX_TM_MAX_BURST_MANTISSA) + +/* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */ +#define NIX_TM_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1) +#define NIX_TM_LENGTH_ADJUST_MAX 255 + +#define NIX_TM_TLX_SP_PRIO_MAX 10 +#define NIX_CN9K_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1) +#define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(14) - 1) + +/* [CN9K, CN10K) */ +#define NIX_CN9K_TXSCH_LVL_SMQ_MAX 512 + +/* [CN10K, .) */ +#define NIX_TXSCH_LVL_SMQ_MAX 832 + +/* [CN9K, .) */ +#define NIX_TXSCH_LVL_TL4_MAX 512 +#define NIX_TXSCH_LVL_TL3_MAX 256 +#define NIX_TXSCH_LVL_TL2_MAX 256 +#define NIX_TXSCH_LVL_TL1_MAX 28 + +#define NIX_CQ_OP_STAT_OP_ERR 63 +#define NIX_CQ_OP_STAT_CQ_ERR 46 + +#define NIX_RQ_CN10K_SPB_MAX_SIZE 4096 + +/* [CN9K, .) */ +#define NIX_LSO_SEG_MAX 256 +#define NIX_LSO_MPS_MAX (BIT_ULL(14) - 1) + +/* Software defined LSO base format IDX */ +#define NIX_LSO_FORMAT_IDX_TSOV4 0 +#define NIX_LSO_FORMAT_IDX_TSOV6 1 + +#endif /* __NIX_HW_H__ */ diff --git a/drivers/common/cnxk/hw/npa.h b/drivers/common/cnxk/hw/npa.h new file mode 100644 index 0000000000..891a1b2b5f --- /dev/null +++ b/drivers/common/cnxk/hw/npa.h @@ -0,0 +1,376 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __NPA_HW_H__ +#define __NPA_HW_H__ + +/* Register offsets */ + +#define NPA_AF_BLK_RST (0x0ull) +#define NPA_AF_CONST (0x10ull) +#define NPA_AF_CONST1 (0x18ull) +#define NPA_AF_LF_RST (0x20ull) +#define NPA_AF_GEN_CFG (0x30ull) +#define NPA_AF_NDC_CFG (0x40ull) +#define NPA_AF_NDC_SYNC (0x50ull) +#define NPA_AF_INP_CTL (0xd0ull) +#define NPA_AF_ACTIVE_CYCLES_PC (0xf0ull) +#define NPA_AF_AVG_DELAY (0x100ull) +#define NPA_AF_GEN_INT (0x140ull) +#define NPA_AF_GEN_INT_W1S (0x148ull) +#define NPA_AF_GEN_INT_ENA_W1S (0x150ull) +#define NPA_AF_GEN_INT_ENA_W1C (0x158ull) +#define NPA_AF_RVU_INT (0x160ull) +#define NPA_AF_RVU_INT_W1S (0x168ull) +#define NPA_AF_RVU_INT_ENA_W1S (0x170ull) +#define NPA_AF_RVU_INT_ENA_W1C (0x178ull) +#define NPA_AF_ERR_INT (0x180ull) +#define NPA_AF_ERR_INT_W1S (0x188ull) +#define NPA_AF_ERR_INT_ENA_W1S (0x190ull) +#define NPA_AF_ERR_INT_ENA_W1C (0x198ull) +#define NPA_AF_RAS (0x1a0ull) +#define NPA_AF_RAS_W1S (0x1a8ull) +#define NPA_AF_RAS_ENA_W1S (0x1b0ull) +#define NPA_AF_RAS_ENA_W1C (0x1b8ull) +#define NPA_AF_AQ_CFG (0x600ull) +#define NPA_AF_AQ_BASE (0x610ull) +#define NPA_AF_AQ_STATUS (0x620ull) +#define NPA_AF_AQ_DOOR (0x630ull) +#define NPA_AF_AQ_DONE_WAIT (0x640ull) +#define NPA_AF_AQ_DONE (0x650ull) +#define NPA_AF_AQ_DONE_ACK (0x660ull) +#define NPA_AF_AQ_DONE_TIMER (0x670ull) +#define NPA_AF_AQ_DONE_INT (0x680ull) +#define NPA_AF_AQ_DONE_ENA_W1S (0x690ull) +#define NPA_AF_AQ_DONE_ENA_W1C (0x698ull) +#define NPA_AF_BATCH_CTL (0x6a0ull) /* [CN10K, .) */ +#define NPA_AF_BATCH_ACCEPT_CTL (0x6a8ull) /* [CN10K, .) */ +#define NPA_AF_BATCH_ERR_DATA0 (0x6c0ull) /* [CN10K, .) */ +#define NPA_AF_BATCH_ERR_DATA1 (0x6c8ull) /* [CN10K, .) */ +#define NPA_AF_LFX_AURAS_CFG(a) (0x4000ull | (uint64_t)(a) << 18) +#define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010ull | (uint64_t)(a) << 18) +#define NPA_AF_LFX_QINTS_CFG(a) (0x4100ull | (uint64_t)(a) << 18) +#define NPA_AF_LFX_QINTS_BASE(a) (0x4110ull | (uint64_t)(a) << 18) +#define NPA_PRIV_AF_INT_CFG (0x10000ull) +#define NPA_PRIV_LFX_CFG(a) (0x10010ull | (uint64_t)(a) << 8) +#define NPA_PRIV_LFX_INT_CFG(a) (0x10020ull | (uint64_t)(a) << 8) +#define NPA_AF_RVU_LF_CFG_DEBUG (0x10030ull) +#define NPA_AF_DTX_FILTER_CTL (0x10040ull) + +#define NPA_LF_AURA_OP_ALLOCX(a) (0x10ull | (uint64_t)(a) << 3) +#define NPA_LF_AURA_OP_FREE0 (0x20ull) +#define NPA_LF_AURA_OP_FREE1 (0x28ull) +#define NPA_LF_AURA_OP_CNT (0x30ull) +#define NPA_LF_AURA_OP_LIMIT (0x50ull) +#define NPA_LF_AURA_OP_INT (0x60ull) +#define NPA_LF_AURA_OP_THRESH (0x70ull) +#define NPA_LF_POOL_OP_PC (0x100ull) +#define NPA_LF_POOL_OP_AVAILABLE (0x110ull) +#define NPA_LF_POOL_OP_PTR_START0 (0x120ull) +#define NPA_LF_POOL_OP_PTR_START1 (0x128ull) +#define NPA_LF_POOL_OP_PTR_END0 (0x130ull) +#define NPA_LF_POOL_OP_PTR_END1 (0x138ull) +#define NPA_LF_POOL_OP_INT (0x160ull) +#define NPA_LF_POOL_OP_THRESH (0x170ull) +#define NPA_LF_ERR_INT (0x200ull) +#define NPA_LF_ERR_INT_W1S (0x208ull) +#define NPA_LF_ERR_INT_ENA_W1C (0x210ull) +#define NPA_LF_ERR_INT_ENA_W1S (0x218ull) +#define NPA_LF_RAS (0x220ull) +#define NPA_LF_RAS_W1S (0x228ull) +#define NPA_LF_RAS_ENA_W1C (0x230ull) +#define NPA_LF_RAS_ENA_W1S (0x238ull) +#define NPA_LF_QINTX_CNT(a) (0x300ull | (uint64_t)(a) << 12) +#define NPA_LF_QINTX_INT(a) (0x310ull | (uint64_t)(a) << 12) +#define NPA_LF_QINTX_ENA_W1S(a) (0x320ull | (uint64_t)(a) << 12) +#define NPA_LF_QINTX_ENA_W1C(a) (0x330ull | (uint64_t)(a) << 12) +#define NPA_LF_AURA_BATCH_ALLOC (0x340ull) /* [CN10K, .) */ +#define NPA_LF_AURA_BATCH_FREE0 (0x400ull) /* [CN10K, .) */ +#define NPA_LF_AURA_BATCH_FREEX(a) \ + (0x400ull | (uint64_t)(a) << 3) /* [CN10K, .) */ + +/* Enum offsets */ + +#define NPA_AF_BATCH_FAIL_BATCH_PASS (0x0ull) /* [CN10K, .) */ +#define NPA_AF_BATCH_FAIL_BATCH_CNT_OOR (0x1ull) /* [CN10K, .) */ +#define NPA_AF_BATCH_FAIL_BATCH_STORE_FAIL (0x2ull) /* [CN10K, .) */ + +#define NPA_AQ_COMP_NOTDONE (0x0ull) +#define NPA_AQ_COMP_GOOD (0x1ull) +#define NPA_AQ_COMP_SWERR (0x2ull) +#define NPA_AQ_COMP_CTX_POISON (0x3ull) +#define NPA_AQ_COMP_CTX_FAULT (0x4ull) +#define NPA_AQ_COMP_LOCKERR (0x5ull) + +#define NPA_AF_INT_VEC_RVU (0x0ull) +#define NPA_AF_INT_VEC_GEN (0x1ull) +#define NPA_AF_INT_VEC_AQ_DONE (0x2ull) +#define NPA_AF_INT_VEC_AF_ERR (0x3ull) +#define NPA_AF_INT_VEC_POISON (0x4ull) + +#define NPA_AQ_INSTOP_NOP (0x0ull) +#define NPA_AQ_INSTOP_INIT (0x1ull) +#define NPA_AQ_INSTOP_WRITE (0x2ull) +#define NPA_AQ_INSTOP_READ (0x3ull) +#define NPA_AQ_INSTOP_LOCK (0x4ull) +#define NPA_AQ_INSTOP_UNLOCK (0x5ull) + +#define NPA_AQ_CTYPE_AURA (0x0ull) +#define NPA_AQ_CTYPE_POOL (0x1ull) + +#define NPA_BPINTF_NIX0_RX (0x0ull) +#define NPA_BPINTF_NIX1_RX (0x1ull) + +#define NPA_AURA_ERR_INT_AURA_FREE_UNDER (0x0ull) +#define NPA_AURA_ERR_INT_AURA_ADD_OVER (0x1ull) +#define NPA_AURA_ERR_INT_AURA_ADD_UNDER (0x2ull) +#define NPA_AURA_ERR_INT_POOL_DIS (0x3ull) +#define NPA_AURA_ERR_INT_R4 (0x4ull) +#define NPA_AURA_ERR_INT_R5 (0x5ull) +#define NPA_AURA_ERR_INT_R6 (0x6ull) +#define NPA_AURA_ERR_INT_R7 (0x7ull) + +#define NPA_LF_INT_VEC_ERR_INT (0x40ull) +#define NPA_LF_INT_VEC_POISON (0x41ull) +#define NPA_LF_INT_VEC_QINT_END (0x3full) +#define NPA_LF_INT_VEC_QINT_START (0x0ull) + +#define NPA_INPQ_SSO (0x4ull) +#define NPA_INPQ_TIM (0x5ull) +#define NPA_INPQ_DPI (0x6ull) +#define NPA_INPQ_AURA_OP (0xeull) +#define NPA_INPQ_INTERNAL_RSV (0xfull) +#define NPA_INPQ_NIX0_RX (0x0ull) +#define NPA_INPQ_NIX1_RX (0x2ull) +#define NPA_INPQ_NIX0_TX (0x1ull) +#define NPA_INPQ_NIX1_TX (0x3ull) +#define NPA_INPQ_R_END (0xdull) +#define NPA_INPQ_R_START (0x7ull) + +#define NPA_POOL_ERR_INT_OVFLS (0x0ull) +#define NPA_POOL_ERR_INT_RANGE (0x1ull) +#define NPA_POOL_ERR_INT_PERR (0x2ull) +#define NPA_POOL_ERR_INT_R3 (0x3ull) +#define NPA_POOL_ERR_INT_R4 (0x4ull) +#define NPA_POOL_ERR_INT_R5 (0x5ull) +#define NPA_POOL_ERR_INT_R6 (0x6ull) +#define NPA_POOL_ERR_INT_R7 (0x7ull) + +#define NPA_NDC0_PORT_AURA0 (0x0ull) +#define NPA_NDC0_PORT_AURA1 (0x1ull) +#define NPA_NDC0_PORT_POOL0 (0x2ull) +#define NPA_NDC0_PORT_POOL1 (0x3ull) +#define NPA_NDC0_PORT_STACK0 (0x4ull) +#define NPA_NDC0_PORT_STACK1 (0x5ull) + +#define NPA_LF_ERR_INT_AURA_DIS (0x0ull) +#define NPA_LF_ERR_INT_AURA_OOR (0x1ull) +#define NPA_LF_ERR_INT_AURA_FAULT (0xcull) +#define NPA_LF_ERR_INT_POOL_FAULT (0xdull) +#define NPA_LF_ERR_INT_STACK_FAULT (0xeull) +#define NPA_LF_ERR_INT_QINT_FAULT (0xfull) + +#define NPA_BATCH_ALLOC_RESULT_ACCEPTED (0x0ull) /* [CN10K, .) */ +#define NPA_BATCH_ALLOC_RESULT_WAIT (0x1ull) /* [CN10K, .) */ +#define NPA_BATCH_ALLOC_RESULT_ERR (0x2ull) /* [CN10K, .) */ +#define NPA_BATCH_ALLOC_RESULT_NOCORE (0x3ull) /* [CN10K, .) */ +#define NPA_BATCH_ALLOC_RESULT_NOCORE_WAIT (0x4ull) /* [CN10K, .) */ + +#define NPA_BATCH_ALLOC_CCODE_INVAL (0x0ull) /* [CN10K, .) */ +#define NPA_BATCH_ALLOC_CCODE_VAL (0x1ull) /* [CN10K, .) */ +#define NPA_BATCH_ALLOC_CCODE_VAL_NULL (0x2ull) /* [CN10K, .) */ + +#define NPA_INPQ_ENAS_REMOTE_PORT (0x0ull) /* [CN10K, .) */ +#define NPA_INPQ_ENAS_RESP_DISABLE (0x702ull) /* [CN10K, .) */ +#define NPA_INPQ_ENAS_NOTIF_DISABLE (0x7cfull) /* [CN10K, .) */ + +/* Structures definitions */ + +/* NPA admin queue instruction structure */ +struct npa_aq_inst_s { + uint64_t op : 4; + uint64_t ctype : 4; + uint64_t lf : 9; + uint64_t rsvd_23_17 : 7; + uint64_t cindex : 20; + uint64_t rsvd_62_44 : 19; + uint64_t doneint : 1; + uint64_t res_addr : 64; /* W1 */ +}; + +/* NPA admin queue result structure */ +struct npa_aq_res_s { + uint64_t op : 4; + uint64_t ctype : 4; + uint64_t compcode : 8; + uint64_t doneint : 1; + uint64_t rsvd_63_17 : 47; + uint64_t rsvd_127_64 : 64; /* W1 */ +}; + +/* NPA aura operation write data structure */ +struct npa_aura_op_wdata_s { + uint64_t aura : 20; + uint64_t rsvd_62_20 : 43; + uint64_t drop : 1; +}; + +/* NPA aura context structure */ +struct npa_aura_s { + uint64_t pool_addr : 64; /* W0 */ + uint64_t ena : 1; + uint64_t rsvd_66_65 : 2; + uint64_t pool_caching : 1; + uint64_t pool_way_mask : 16; + uint64_t avg_con : 9; + uint64_t rsvd_93 : 1; + uint64_t pool_drop_ena : 1; + uint64_t aura_drop_ena : 1; + uint64_t bp_ena : 2; + uint64_t rsvd_103_98 : 6; + uint64_t aura_drop : 8; + uint64_t shift : 6; + uint64_t rsvd_119_118 : 2; + uint64_t avg_level : 8; + uint64_t count : 36; + uint64_t rsvd_167_164 : 4; + uint64_t nix0_bpid : 9; + uint64_t rsvd_179_177 : 3; + uint64_t nix1_bpid : 9; + uint64_t rsvd_191_189 : 3; + uint64_t limit : 36; + uint64_t rsvd_231_228 : 4; + uint64_t bp : 8; + uint64_t rsvd_242_240 : 3; + uint64_t fc_be : 1; /* [CN10K, .) */ + uint64_t fc_ena : 1; + uint64_t fc_up_crossing : 1; + uint64_t fc_stype : 2; + uint64_t fc_hyst_bits : 4; + uint64_t rsvd_255_252 : 4; + uint64_t fc_addr : 64; /* W4 */ + uint64_t pool_drop : 8; + uint64_t update_time : 16; + uint64_t err_int : 8; + uint64_t err_int_ena : 8; + uint64_t thresh_int : 1; + uint64_t thresh_int_ena : 1; + uint64_t thresh_up : 1; + uint64_t rsvd_363 : 1; + uint64_t thresh_qint_idx : 7; + uint64_t rsvd_371 : 1; + uint64_t err_qint_idx : 7; + uint64_t rsvd_383_379 : 5; + uint64_t thresh : 36; + uint64_t rsvd_423_420 : 4; + uint64_t fc_msh_dst : 11; /* [CN10K, .) */ + uint64_t rsvd_447_435 : 13; + uint64_t rsvd_511_448 : 64; /* W7 */ +}; + +/* NPA pool context structure */ +struct npa_pool_s { + uint64_t stack_base : 64; /* W0 */ + uint64_t ena : 1; + uint64_t nat_align : 1; + uint64_t rsvd_67_66 : 2; + uint64_t stack_caching : 1; + uint64_t rsvd_71_69 : 3; + uint64_t stack_way_mask : 16; + uint64_t buf_offset : 12; + uint64_t rsvd_103_100 : 4; + uint64_t buf_size : 11; + uint64_t rsvd_127_115 : 13; + uint64_t stack_max_pages : 32; + uint64_t stack_pages : 32; + uint64_t op_pc : 48; + uint64_t rsvd_255_240 : 16; + uint64_t stack_offset : 4; + uint64_t rsvd_263_260 : 4; + uint64_t shift : 6; + uint64_t rsvd_271_270 : 2; + uint64_t avg_level : 8; + uint64_t avg_con : 9; + uint64_t fc_ena : 1; + uint64_t fc_stype : 2; + uint64_t fc_hyst_bits : 4; + uint64_t fc_up_crossing : 1; + uint64_t fc_be : 1; /* [CN10K, .) */ + uint64_t rsvd_299_298 : 2; + uint64_t update_time : 16; + uint64_t rsvd_319_316 : 4; + uint64_t fc_addr : 64; /* W5 */ + uint64_t ptr_start : 64; /* W6 */ + uint64_t ptr_end : 64; /* W7 */ + uint64_t rsvd_535_512 : 24; + uint64_t err_int : 8; + uint64_t err_int_ena : 8; + uint64_t thresh_int : 1; + uint64_t thresh_int_ena : 1; + uint64_t thresh_up : 1; + uint64_t rsvd_555 : 1; + uint64_t thresh_qint_idx : 7; + uint64_t rsvd_563 : 1; + uint64_t err_qint_idx : 7; + uint64_t rsvd_575_571 : 5; + uint64_t thresh : 36; + uint64_t rsvd_615_612 : 4; + uint64_t fc_msh_dst : 11; /* [CN10K, .) */ + uint64_t rsvd_639_627 : 13; + uint64_t rsvd_703_640 : 64; /* W10 */ + uint64_t rsvd_767_704 : 64; /* W11 */ + uint64_t rsvd_831_768 : 64; /* W12 */ + uint64_t rsvd_895_832 : 64; /* W13 */ + uint64_t rsvd_959_896 : 64; /* W14 */ + uint64_t rsvd_1023_960 : 64; /* W15 */ +}; + +/* NPA queue interrupt context hardware structure */ +struct npa_qint_hw_s { + uint32_t count : 22; + uint32_t rsvd_30_22 : 9; + uint32_t ena : 1; +}; + +/* NPA batch allocate compare hardware structure */ +struct npa_batch_alloc_compare_s { + uint64_t aura : 20; + uint64_t rsvd_31_20 : 12; + uint64_t count : 10; + uint64_t rsvd_47_42 : 6; + uint64_t stype : 2; + uint64_t rsvd_61_50 : 12; + uint64_t dis_wait : 1; + uint64_t drop : 1; +}; + +/* NPA batch alloc dma write status structure */ +struct npa_batch_alloc_status_s { + uint8_t count : 5; + uint8_t ccode : 2; + uint8_t rsvd_7_7 : 1; +}; + +typedef enum { + ALLOC_RESULT_ACCEPTED = 0, + ALLOC_RESULT_WAIT = 1, + ALLOC_RESULT_ERR = 2, + ALLOC_RESULT_NOCORE = 3, + ALLOC_RESULT_NOCORE_WAIT = 4, +} npa_batch_alloc_result_e; + +typedef enum { + ALLOC_CCODE_INVAL = 0, + ALLOC_CCODE_VAL = 1, + ALLOC_CCODE_VAL_NULL = 2, +} npa_batch_alloc_ccode_e; + +typedef enum { + ALLOC_STYPE_STF = 0, + ALLOC_STYPE_STT = 1, + ALLOC_STYPE_STP = 2, + ALLOC_STYPE_STSTP = 3, +} npa_batch_alloc_stype_e; + +#endif /* __NPA_HW_H__ */ diff --git a/drivers/common/cnxk/hw/npc.h b/drivers/common/cnxk/hw/npc.h new file mode 100644 index 0000000000..e0f06bf0e7 --- /dev/null +++ b/drivers/common/cnxk/hw/npc.h @@ -0,0 +1,525 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __NPC_HW_H__ +#define __NPC_HW_H__ + +/* Register offsets */ + +#define NPC_AF_CFG (0x0ull) +#define NPC_AF_ACTIVE_PC (0x10ull) +#define NPC_AF_CONST (0x20ull) +#define NPC_AF_CONST1 (0x30ull) +#define NPC_AF_BLK_RST (0x40ull) +#define NPC_AF_MCAM_SCRUB_CTL (0xa0ull) +#define NPC_AF_KCAM_SCRUB_CTL (0xb0ull) +#define NPC_AF_KPUX_CFG(a) (0x500ull | (uint64_t)(a) << 3) +#define NPC_AF_PCK_CFG (0x600ull) +#define NPC_AF_PCK_DEF_OL2 (0x610ull) +#define NPC_AF_PCK_DEF_OIP4 (0x620ull) +#define NPC_AF_PCK_DEF_OIP6 (0x630ull) +#define NPC_AF_PCK_DEF_IIP4 (0x640ull) +#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x800ull | (uint64_t)(a) << 3) +#define NPC_AF_INTFX_KEX_CFG(a) (0x1010ull | (uint64_t)(a) << 8) +#define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (uint64_t)(a) << 6) +#define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (uint64_t)(a) << 6) +#define NPC_AF_PKINDX_CPI_DEFX(a, b) \ + (0x80020ull | (uint64_t)(a) << 6 | (uint64_t)(b) << 3) +#define NPC_AF_CHLEN90B_PKIND (0x3bull) +#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ + (0x100000ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6 | \ + (uint64_t)(c) << 3) +#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \ + (0x100020ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6) +#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \ + (0x100028ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6) +#define NPC_AF_KPUX_ENTRY_DISX(a, b) \ + (0x180000ull | (uint64_t)(a) << 6 | (uint64_t)(b) << 3) +#define NPC_AF_CPIX_CFG(a) (0x200000ull | (uint64_t)(a) << 3) +#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \ + (0x900000ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 12 | \ + (uint64_t)(c) << 5 | (uint64_t)(d) << 3) +#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \ + (0x980000ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 12 | \ + (uint64_t)(c) << 3) +#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) \ + (0x1000000ull | (uint64_t)(a) << 10 | (uint64_t)(b) << 6 | \ + (uint64_t)(c) << 3) +#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) \ + (0x1000010ull | (uint64_t)(a) << 10 | (uint64_t)(b) << 6 | \ + (uint64_t)(c) << 3) +#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) \ + (0x1000020ull | (uint64_t)(a) << 10 | (uint64_t)(b) << 6 | \ + (uint64_t)(c) << 3) +#define NPC_AF_MCAMEX_BANKX_CFG(a, b) \ + (0x1800000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) +#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) \ + (0x1880000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) +#define NPC_AF_MATCH_STATX(a) (0x1880008ull | (uint64_t)(a) << 8) +#define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040ull + 0x8 * (uint64_t)(a)) +#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) \ + (0x1900000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) +#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) \ + (0x1900008ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) +#define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000ull | (uint64_t)(a) << 4) +#define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008ull | (uint64_t)(a) << 4) +#define NPC_AF_MCAM_BANKX_HITX(a, b) \ + (0x1c80000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) +#define NPC_AF_LKUP_CTL (0x2000000ull) +#define NPC_AF_LKUP_DATAX(a) (0x2000200ull | (uint64_t)(a) << 4) +#define NPC_AF_LKUP_RESULTX(a) (0x2000400ull | (uint64_t)(a) << 4) +#define NPC_AF_INTFX_STAT(a) (0x2000800ull | (uint64_t)(a) << 4) +#define NPC_AF_DBG_CTL (0x3000000ull) +#define NPC_AF_DBG_STATUS (0x3000010ull) +#define NPC_AF_KPUX_DBG(a) (0x3000020ull | (uint64_t)(a) << 8) +#define NPC_AF_IKPU_ERR_CTL (0x3000080ull) +#define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0ull | (uint64_t)(a) << 8) +#define NPC_AF_MCAM_DBG (0x3001000ull) +#define NPC_AF_DBG_DATAX(a) (0x3001400ull | (uint64_t)(a) << 4) +#define NPC_AF_DBG_RESULTX(a) (0x3001800ull | (uint64_t)(a) << 4) + +/* Enum offsets */ + +#define NPC_INTF_NIX0_RX (0x0ull) +#define NPC_INTF_NIX0_TX (0x1ull) + +#define NPC_LKUPOP_PKT (0x0ull) +#define NPC_LKUPOP_KEY (0x1ull) + +#define NPC_MCAM_KEY_X1 (0x0ull) +#define NPC_MCAM_KEY_X2 (0x1ull) +#define NPC_MCAM_KEY_X4 (0x2ull) + +#ifndef __NPC_ERRLEVELS__ +#define __NPC_ERRLEVELS__ + +enum NPC_ERRLEV_E { + NPC_ERRLEV_RE = 0, + NPC_ERRLEV_LA = 1, + NPC_ERRLEV_LB = 2, + NPC_ERRLEV_LC = 3, + NPC_ERRLEV_LD = 4, + NPC_ERRLEV_LE = 5, + NPC_ERRLEV_LF = 6, + NPC_ERRLEV_LG = 7, + NPC_ERRLEV_LH = 8, + NPC_ERRLEV_R9 = 9, + NPC_ERRLEV_R10 = 10, + NPC_ERRLEV_R11 = 11, + NPC_ERRLEV_R12 = 12, + NPC_ERRLEV_R13 = 13, + NPC_ERRLEV_R14 = 14, + NPC_ERRLEV_NIX = 15, + NPC_ERRLEV_ENUM_LAST = 16, +}; + +#endif + +enum npc_kpu_err_code { + NPC_EC_NOERR = 0, /* has to be zero */ + NPC_EC_UNK, + NPC_EC_IH_LENGTH, + NPC_EC_EDSA_UNK, + NPC_EC_L2_K1, + NPC_EC_L2_K2, + NPC_EC_L2_K3, + NPC_EC_L2_K3_ETYPE_UNK, + NPC_EC_L2_K4, + NPC_EC_MPLS_2MANY, + NPC_EC_MPLS_UNK, + NPC_EC_NSH_UNK, + NPC_EC_IP_TTL_0, + NPC_EC_IP_FRAG_OFFSET_1, + NPC_EC_IP_VER, + NPC_EC_IP6_HOP_0, + NPC_EC_IP6_VER, + NPC_EC_TCP_FLAGS_FIN_ONLY, + NPC_EC_TCP_FLAGS_ZERO, + NPC_EC_TCP_FLAGS_RST_FIN, + NPC_EC_TCP_FLAGS_URG_SYN, + NPC_EC_TCP_FLAGS_RST_SYN, + NPC_EC_TCP_FLAGS_SYN_FIN, + NPC_EC_VXLAN, + NPC_EC_NVGRE, + NPC_EC_GRE, + NPC_EC_GRE_VER1, + NPC_EC_L4, + NPC_EC_OIP4_CSUM, + NPC_EC_IIP4_CSUM, + NPC_EC_LAST /* has to be the last item */ +}; + +enum NPC_LID_E { + NPC_LID_LA = 0, + NPC_LID_LB, + NPC_LID_LC, + NPC_LID_LD, + NPC_LID_LE, + NPC_LID_LF, + NPC_LID_LG, + NPC_LID_LH, +}; + +#ifndef __NPC_LT_TYPES__ +#define __NPC_LT_TYPES__ +#define NPC_LT_NA 0 + +enum npc_kpu_la_ltype { + NPC_LT_LA_8023 = 1, + NPC_LT_LA_ETHER, + NPC_LT_LA_IH_NIX_ETHER, + NPC_LT_LA_IH_8_ETHER, + NPC_LT_LA_IH_4_ETHER, + NPC_LT_LA_IH_2_ETHER, + NPC_LT_LA_HIGIG2_ETHER, + NPC_LT_LA_IH_NIX_HIGIG2_ETHER, + NPC_LT_LA_CH_LEN_90B_ETHER, + NPC_LT_LA_CPT_HDR, + NPC_LT_LA_CUSTOM0 = 0xE, + NPC_LT_LA_CUSTOM1 = 0xF, +}; + +enum npc_kpu_lb_ltype { + NPC_LT_LB_ETAG = 1, + NPC_LT_LB_CTAG, + NPC_LT_LB_STAG_QINQ, + NPC_LT_LB_BTAG, + NPC_LT_LB_ITAG, + NPC_LT_LB_DSA, + NPC_LT_LB_DSA_VLAN, + NPC_LT_LB_EDSA, + NPC_LT_LB_EDSA_VLAN, + NPC_LT_LB_EXDSA, + NPC_LT_LB_EXDSA_VLAN, + NPC_LT_LB_FDSA, + NPC_LT_LB_CUSTOM0 = 0xE, + NPC_LT_LB_CUSTOM1 = 0xF, +}; + +enum npc_kpu_lc_ltype { + NPC_LT_LC_PTP = 1, + NPC_LT_LC_IP, + NPC_LT_LC_IP_OPT, + NPC_LT_LC_IP6, + NPC_LT_LC_IP6_EXT, + NPC_LT_LC_ARP, + NPC_LT_LC_RARP, + NPC_LT_LC_MPLS, + NPC_LT_LC_NSH, + NPC_LT_LC_FCOE, + NPC_LT_LC_CUSTOM0 = 0xE, + NPC_LT_LC_CUSTOM1 = 0xF, +}; + +/* Don't modify Ltypes up to SCTP, otherwise it will + * effect flow tag calculation and thus RSS. + */ +enum npc_kpu_ld_ltype { + NPC_LT_LD_TCP = 1, + NPC_LT_LD_UDP, + NPC_LT_LD_ICMP, + NPC_LT_LD_SCTP, + NPC_LT_LD_ICMP6, + NPC_LT_LD_CUSTOM0, + NPC_LT_LD_CUSTOM1, + NPC_LT_LD_IGMP = 8, + NPC_LT_LD_AH, + NPC_LT_LD_GRE, + NPC_LT_LD_NVGRE, + NPC_LT_LD_NSH, + NPC_LT_LD_TU_MPLS_IN_NSH, + NPC_LT_LD_TU_MPLS_IN_IP, +}; + +enum npc_kpu_le_ltype { + NPC_LT_LE_VXLAN = 1, + NPC_LT_LE_GENEVE, + NPC_LT_LE_ESP, + NPC_LT_LE_GTPU = 4, + NPC_LT_LE_VXLANGPE, + NPC_LT_LE_GTPC, + NPC_LT_LE_NSH, + NPC_LT_LE_TU_MPLS_IN_GRE, + NPC_LT_LE_TU_NSH_IN_GRE, + NPC_LT_LE_TU_MPLS_IN_UDP, + NPC_LT_LE_CUSTOM0 = 0xE, + NPC_LT_LE_CUSTOM1 = 0xF, +}; + +#endif + +enum npc_kpu_lf_ltype { + NPC_LT_LF_TU_ETHER = 1, + NPC_LT_LF_TU_PPP, + NPC_LT_LF_TU_MPLS_IN_VXLANGPE, + NPC_LT_LF_TU_NSH_IN_VXLANGPE, + NPC_LT_LF_TU_MPLS_IN_NSH, + NPC_LT_LF_TU_3RD_NSH, + NPC_LT_LF_CUSTOM0 = 0xE, + NPC_LT_LF_CUSTOM1 = 0xF, +}; + +enum npc_kpu_lg_ltype { + NPC_LT_LG_TU_IP = 1, + NPC_LT_LG_TU_IP6, + NPC_LT_LG_TU_ARP, + NPC_LT_LG_TU_ETHER_IN_NSH, + NPC_LT_LG_CUSTOM0 = 0xE, + NPC_LT_LG_CUSTOM1 = 0xF, +}; + +/* Don't modify Ltypes up to SCTP, otherwise it will + * effect flow tag calculation and thus RSS. + */ +enum npc_kpu_lh_ltype { + NPC_LT_LH_TU_TCP = 1, + NPC_LT_LH_TU_UDP, + NPC_LT_LH_TU_ICMP, + NPC_LT_LH_TU_SCTP, + NPC_LT_LH_TU_ICMP6, + NPC_LT_LH_TU_IGMP = 8, + NPC_LT_LH_TU_ESP, + NPC_LT_LH_TU_AH, + NPC_LT_LH_CUSTOM0 = 0xE, + NPC_LT_LH_CUSTOM1 = 0xF, +}; + +enum npc_kpu_lb_uflag { + NPC_F_LB_U_UNK_ETYPE = 0x80, + NPC_F_LB_U_MORE_TAG = 0x40, +}; + +enum npc_kpu_lb_lflag { + NPC_F_LB_L_WITH_CTAG = 1, + NPC_F_LB_L_WITH_CTAG_UNK, + NPC_F_LB_L_WITH_STAG_CTAG, + NPC_F_LB_L_WITH_STAG_STAG, + NPC_F_LB_L_WITH_QINQ_CTAG, + NPC_F_LB_L_WITH_QINQ_QINQ, + NPC_F_LB_L_WITH_ITAG, + NPC_F_LB_L_WITH_ITAG_STAG, + NPC_F_LB_L_WITH_ITAG_CTAG, + NPC_F_LB_L_WITH_ITAG_UNK, + NPC_F_LB_L_WITH_BTAG_ITAG, + NPC_F_LB_L_WITH_STAG, + NPC_F_LB_L_WITH_QINQ, + NPC_F_LB_L_DSA, + NPC_F_LB_L_DSA_VLAN, + NPC_F_LB_L_EDSA, + NPC_F_LB_L_EDSA_VLAN, + NPC_F_LB_L_EXDSA, + NPC_F_LB_L_EXDSA_VLAN, + NPC_F_LB_L_FDSA, +}; + +enum npc_kpu_lc_uflag { + NPC_F_LC_U_UNK_PROTO = 0x10, + NPC_F_LC_U_IP_FRAG = 0x20, + NPC_F_LC_U_IP6_FRAG = 0x40, +}; + +/* Structures definitions */ +struct npc_kpu_profile_cam { + uint8_t state; + uint8_t state_mask; + uint16_t dp0; + uint16_t dp0_mask; + uint16_t dp1; + uint16_t dp1_mask; + uint16_t dp2; + uint16_t dp2_mask; +}; + +struct npc_kpu_profile_action { + uint8_t errlev; + uint8_t errcode; + uint8_t dp0_offset; + uint8_t dp1_offset; + uint8_t dp2_offset; + uint8_t bypass_count; + uint8_t parse_done; + uint8_t next_state; + uint8_t ptr_advance; + uint8_t cap_ena; + uint8_t lid; + uint8_t ltype; + uint8_t flags; + uint8_t offset; + uint8_t mask; + uint8_t right; + uint8_t shift; +}; + +struct npc_kpu_profile { + int cam_entries; + int action_entries; + struct npc_kpu_profile_cam *cam; + struct npc_kpu_profile_action *action; +}; + +/* NPC KPU register formats */ +struct npc_kpu_cam { + uint64_t dp0_data : 16; + uint64_t dp1_data : 16; + uint64_t dp2_data : 16; + uint64_t state : 8; + uint64_t rsvd_63_56 : 8; +}; + +struct npc_kpu_action0 { + uint64_t var_len_shift : 3; + uint64_t var_len_right : 1; + uint64_t var_len_mask : 8; + uint64_t var_len_offset : 8; + uint64_t ptr_advance : 8; + uint64_t capture_flags : 8; + uint64_t capture_ltype : 4; + uint64_t capture_lid : 3; + uint64_t rsvd_43 : 1; + uint64_t next_state : 8; + uint64_t parse_done : 1; + uint64_t capture_ena : 1; + uint64_t byp_count : 3; + uint64_t rsvd_63_57 : 7; +}; + +struct npc_kpu_action1 { + uint64_t dp0_offset : 8; + uint64_t dp1_offset : 8; + uint64_t dp2_offset : 8; + uint64_t errcode : 8; + uint64_t errlev : 4; + uint64_t rsvd_63_36 : 28; +}; + +struct npc_kpu_pkind_cpi_def { + uint64_t cpi_base : 10; + uint64_t rsvd_11_10 : 2; + uint64_t add_shift : 3; + uint64_t rsvd_15 : 1; + uint64_t add_mask : 8; + uint64_t add_offset : 8; + uint64_t flags_mask : 8; + uint64_t flags_match : 8; + uint64_t ltype_mask : 4; + uint64_t ltype_match : 4; + uint64_t lid : 3; + uint64_t rsvd_62_59 : 4; + uint64_t ena : 1; +}; + +struct nix_rx_action { + uint64_t op : 4; + uint64_t pf_func : 16; + uint64_t index : 20; + uint64_t match_id : 16; + uint64_t flow_key_alg : 5; + uint64_t rsvd_63_61 : 3; +}; + +struct nix_tx_action { + uint64_t op : 4; + uint64_t rsvd_11_4 : 8; + uint64_t index : 20; + uint64_t match_id : 16; + uint64_t rsvd_63_48 : 16; +}; + +/* NPC layer parse information structure */ +struct npc_layer_info_s { + uint32_t lptr : 8; + uint32_t flags : 8; + uint32_t ltype : 4; + uint32_t rsvd_31_20 : 12; +}; + +/* NPC layer mcam search key extract structure */ +struct npc_layer_kex_s { + uint16_t flags : 8; + uint16_t ltype : 4; + uint16_t rsvd_15_12 : 4; +}; + +/* NPC mcam search key x1 structure */ +struct npc_mcam_key_x1_s { + uint64_t intf : 2; + uint64_t rsvd_63_2 : 62; + uint64_t kw0 : 64; /* W1 */ + uint64_t kw1 : 48; + uint64_t rsvd_191_176 : 16; +}; + +/* NPC mcam search key x2 structure */ +struct npc_mcam_key_x2_s { + uint64_t intf : 2; + uint64_t rsvd_63_2 : 62; + uint64_t kw0 : 64; /* W1 */ + uint64_t kw1 : 64; /* W2 */ + uint64_t kw2 : 64; /* W3 */ + uint64_t kw3 : 32; + uint64_t rsvd_319_288 : 32; +}; + +/* NPC mcam search key x4 structure */ +struct npc_mcam_key_x4_s { + uint64_t intf : 2; + uint64_t rsvd_63_2 : 62; + uint64_t kw0 : 64; /* W1 */ + uint64_t kw1 : 64; /* W2 */ + uint64_t kw2 : 64; /* W3 */ + uint64_t kw3 : 64; /* W4 */ + uint64_t kw4 : 64; /* W5 */ + uint64_t kw5 : 64; /* W6 */ + uint64_t kw6 : 64; /* W7 */ +}; + +/* NPC parse key extract structure */ +struct npc_parse_kex_s { + uint64_t chan : 12; + uint64_t errlev : 4; + uint64_t errcode : 8; + uint64_t l2m : 1; + uint64_t l2b : 1; + uint64_t l3m : 1; + uint64_t l3b : 1; + uint64_t la : 12; + uint64_t lb : 12; + uint64_t lc : 12; + uint64_t ld : 12; + uint64_t le : 12; + uint64_t lf : 12; + uint64_t lg : 12; + uint64_t lh : 12; + uint64_t rsvd_127_124 : 4; +}; + +/* NPC result structure */ +struct npc_result_s { + uint64_t intf : 2; + uint64_t pkind : 6; + uint64_t chan : 12; + uint64_t errlev : 4; + uint64_t errcode : 8; + uint64_t l2m : 1; + uint64_t l2b : 1; + uint64_t l3m : 1; + uint64_t l3b : 1; + uint64_t eoh_ptr : 8; + uint64_t rsvd_63_44 : 20; + uint64_t action : 64; /* W1 */ + uint64_t vtag_action : 64; /* W2 */ + uint64_t la : 20; + uint64_t lb : 20; + uint64_t lc : 20; + uint64_t rsvd_255_252 : 4; + uint64_t ld : 20; + uint64_t le : 20; + uint64_t lf : 20; + uint64_t rsvd_319_316 : 4; + uint64_t lg : 20; + uint64_t lh : 20; + uint64_t rsvd_383_360 : 24; +}; + +#endif /* __NPC_HW_H__ */ diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h new file mode 100644 index 0000000000..632d9499ea --- /dev/null +++ b/drivers/common/cnxk/hw/rvu.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __RVU_HW_H__ +#define __RVU_HW_H__ + +/* Register offsets */ + +#define RVU_AF_MSIXTR_BASE (0x10ull) +#define RVU_AF_BLK_RST (0x30ull) +#define RVU_AF_PF_BAR4_ADDR (0x40ull) +#define RVU_AF_RAS (0x100ull) +#define RVU_AF_RAS_W1S (0x108ull) +#define RVU_AF_RAS_ENA_W1S (0x110ull) +#define RVU_AF_RAS_ENA_W1C (0x118ull) +#define RVU_AF_GEN_INT (0x120ull) +#define RVU_AF_GEN_INT_W1S (0x128ull) +#define RVU_AF_GEN_INT_ENA_W1S (0x130ull) +#define RVU_AF_GEN_INT_ENA_W1C (0x138ull) +#define RVU_AF_AFPFX_MBOXX(a, b) \ + (0x2000ull | (uint64_t)(a) << 4 | (uint64_t)(b) << 3) +#define RVU_AF_PFME_STATUS (0x2800ull) +#define RVU_AF_PFTRPEND (0x2810ull) +#define RVU_AF_PFTRPEND_W1S (0x2820ull) +#define RVU_AF_PF_RST (0x2840ull) +#define RVU_AF_HWVF_RST (0x2850ull) +#define RVU_AF_PFAF_MBOX_INT (0x2880ull) +#define RVU_AF_PFAF_MBOX_INT_W1S (0x2888ull) +#define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890ull) +#define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898ull) +#define RVU_AF_PFFLR_INT (0x28a0ull) +#define RVU_AF_PFFLR_INT_W1S (0x28a8ull) +#define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0ull) +#define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8ull) +#define RVU_AF_PFME_INT (0x28c0ull) +#define RVU_AF_PFME_INT_W1S (0x28c8ull) +#define RVU_AF_PFME_INT_ENA_W1S (0x28d0ull) +#define RVU_AF_PFME_INT_ENA_W1C (0x28d8ull) +#define RVU_PRIV_CONST (0x8000000ull) +#define RVU_PRIV_GEN_CFG (0x8000010ull) +#define RVU_PRIV_CLK_CFG (0x8000020ull) +#define RVU_PRIV_ACTIVE_PC (0x8000030ull) +#define RVU_PRIV_PFX_CFG(a) (0x8000100ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_ID_CFG(a) (0x8000120ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_INT_CFG(a) (0x8000200ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_NIXX_CFG(a, b) \ + (0x8000300ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) +#define RVU_PRIV_PFX_NPA_CFG(a) (0x8000310ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_SSO_CFG(a) (0x8000320ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_SSOW_CFG(a) (0x8000330ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_TIM_CFG(a) (0x8000340ull | (uint64_t)(a) << 16) +#define RVU_PRIV_PFX_CPTX_CFG(a, b) \ + (0x8000350ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) +#define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400ull | (uint64_t)(a) << 3) +#define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280ull | (uint64_t)(a) << 16) +#define RVU_PRIV_HWVFX_NIXX_CFG(a, b) \ + (0x8001300ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) +#define RVU_PRIV_HWVFX_NPA_CFG(a) (0x8001310ull | (uint64_t)(a) << 16) +#define RVU_PRIV_HWVFX_SSO_CFG(a) (0x8001320ull | (uint64_t)(a) << 16) +#define RVU_PRIV_HWVFX_SSOW_CFG(a) (0x8001330ull | (uint64_t)(a) << 16) +#define RVU_PRIV_HWVFX_TIM_CFG(a) (0x8001340ull | (uint64_t)(a) << 16) +#define RVU_PRIV_HWVFX_CPTX_CFG(a, b) \ + (0x8001350ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) + +#define RVU_PF_VFX_PFVF_MBOXX(a, b) \ + (0x0ull | (uint64_t)(a) << 12 | (uint64_t)(b) << 3) +#define RVU_PF_VF_BAR4_ADDR (0x10ull) +#define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200ull | (uint64_t)(a) << 3) +#define RVU_PF_VFME_STATUSX(a) (0x800ull | (uint64_t)(a) << 3) +#define RVU_PF_VFTRPENDX(a) (0x820ull | (uint64_t)(a) << 3) +#define RVU_PF_VFTRPEND_W1SX(a) (0x840ull | (uint64_t)(a) << 3) +#define RVU_PF_VFPF_MBOX_INTX(a) (0x880ull | (uint64_t)(a) << 3) +#define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8a0ull | (uint64_t)(a) << 3) +#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8c0ull | (uint64_t)(a) << 3) +#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8e0ull | (uint64_t)(a) << 3) +#define RVU_PF_VFFLR_INTX(a) (0x900ull | (uint64_t)(a) << 3) +#define RVU_PF_VFFLR_INT_W1SX(a) (0x920ull | (uint64_t)(a) << 3) +#define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940ull | (uint64_t)(a) << 3) +#define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960ull | (uint64_t)(a) << 3) +#define RVU_PF_VFME_INTX(a) (0x980ull | (uint64_t)(a) << 3) +#define RVU_PF_VFME_INT_W1SX(a) (0x9a0ull | (uint64_t)(a) << 3) +#define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9c0ull | (uint64_t)(a) << 3) +#define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9e0ull | (uint64_t)(a) << 3) +#define RVU_PF_PFAF_MBOXX(a) (0xc00ull | (uint64_t)(a) << 3) +#define RVU_PF_INT (0xc20ull) +#define RVU_PF_INT_W1S (0xc28ull) +#define RVU_PF_INT_ENA_W1S (0xc30ull) +#define RVU_PF_INT_ENA_W1C (0xc38ull) +#define RVU_PF_MSIX_VECX_ADDR(a) (0x80000ull | (uint64_t)(a) << 4) +#define RVU_PF_MSIX_VECX_CTL(a) (0x80008ull | (uint64_t)(a) << 4) +#define RVU_PF_MSIX_PBAX(a) (0xf0000ull | (uint64_t)(a) << 3) +#define RVU_VF_VFPF_MBOXX(a) (0x0ull | (uint64_t)(a) << 3) +#define RVU_VF_INT (0x20ull) +#define RVU_VF_INT_W1S (0x28ull) +#define RVU_VF_INT_ENA_W1S (0x30ull) +#define RVU_VF_INT_ENA_W1C (0x38ull) +#define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200ull | (uint64_t)(a) << 3) +#define RVU_VF_MSIX_VECX_ADDR(a) (0x80000ull | (uint64_t)(a) << 4) +#define RVU_VF_MSIX_VECX_CTL(a) (0x80008ull | (uint64_t)(a) << 4) +#define RVU_VF_MBOX_REGION (0xc0000ull) /* [CN10K, .) */ +#define RVU_VF_MSIX_PBAX(a) (0xf0000ull | (uint64_t)(a) << 3) + +/* Enum offsets */ + +#define RVU_BAR_RVU_PF_END_BAR0 (0x84f000000000ull) +#define RVU_BAR_RVU_PF_START_BAR0 (0x840000000000ull) +#define RVU_BAR_RVU_PFX_FUNCX_BAR2(a, b) \ + (0x840200000000ull | ((uint64_t)(a) << 36) | ((uint64_t)(b) << 25)) + +#define RVU_AF_INT_VEC_POISON (0x0ull) +#define RVU_AF_INT_VEC_PFFLR (0x1ull) +#define RVU_AF_INT_VEC_PFME (0x2ull) +#define RVU_AF_INT_VEC_GEN (0x3ull) +#define RVU_AF_INT_VEC_MBOX (0x4ull) + +#define RVU_BLOCK_TYPE_RVUM (0x0ull) +#define RVU_BLOCK_TYPE_LMT (0x2ull) +#define RVU_BLOCK_TYPE_NIX (0x3ull) +#define RVU_BLOCK_TYPE_NPA (0x4ull) +#define RVU_BLOCK_TYPE_NPC (0x5ull) +#define RVU_BLOCK_TYPE_SSO (0x6ull) +#define RVU_BLOCK_TYPE_SSOW (0x7ull) +#define RVU_BLOCK_TYPE_TIM (0x8ull) +#define RVU_BLOCK_TYPE_CPT (0x9ull) +#define RVU_BLOCK_TYPE_NDC (0xaull) +#define RVU_BLOCK_TYPE_DDF (0xbull) +#define RVU_BLOCK_TYPE_ZIP (0xcull) +#define RVU_BLOCK_TYPE_RAD (0xdull) +#define RVU_BLOCK_TYPE_DFA (0xeull) +#define RVU_BLOCK_TYPE_HNA (0xfull) + +#define RVU_BLOCK_ADDR_RVUM (0x0ull) +#define RVU_BLOCK_ADDR_LMT (0x1ull) +#define RVU_BLOCK_ADDR_NPA (0x3ull) +#define RVU_BLOCK_ADDR_NIX0 (0x4ull) +#define RVU_BLOCK_ADDR_NIX1 (0x5ull) +#define RVU_BLOCK_ADDR_NPC (0x6ull) +#define RVU_BLOCK_ADDR_SSO (0x7ull) +#define RVU_BLOCK_ADDR_SSOW (0x8ull) +#define RVU_BLOCK_ADDR_TIM (0x9ull) +#define RVU_BLOCK_ADDR_CPT0 (0xaull) +#define RVU_BLOCK_ADDR_CPT1 (0xbull) +#define RVU_BLOCK_ADDR_NDC0 (0xcull) +#define RVU_BLOCK_ADDR_NDC1 (0xdull) +#define RVU_BLOCK_ADDR_NDC2 (0xeull) +#define RVU_BLOCK_ADDR_R_END (0x1full) +#define RVU_BLOCK_ADDR_R_START (0x14ull) + +#define RVU_VF_INT_VEC_MBOX (0x0ull) + +#define RVU_PF_INT_VEC_AFPF_MBOX (0x6ull) +#define RVU_PF_INT_VEC_VFFLR0 (0x0ull) +#define RVU_PF_INT_VEC_VFFLR1 (0x1ull) +#define RVU_PF_INT_VEC_VFME0 (0x2ull) +#define RVU_PF_INT_VEC_VFME1 (0x3ull) +#define RVU_PF_INT_VEC_VFPF_MBOX0 (0x4ull) +#define RVU_PF_INT_VEC_VFPF_MBOX1 (0x5ull) + +#define AF_BAR2_ALIASX_SIZE (0x100000ull) + +#define TIM_AF_BAR2_SEL (0x9000000ull) +#define SSO_AF_BAR2_SEL (0x9000000ull) +#define NIX_AF_BAR2_SEL (0x9000000ull) +#define SSOW_AF_BAR2_SEL (0x9000000ull) +#define NPA_AF_BAR2_SEL (0x9000000ull) +#define CPT_AF_BAR2_SEL (0x9000000ull) +#define RVU_AF_BAR2_SEL (0x9000000ull) + +#define AF_BAR2_ALIASX(a, b) \ + (0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b)) +#define TIM_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) +#define SSO_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) +#define NIX_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(0, b) +#define SSOW_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) +#define NPA_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(0, b) +#define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) +#define RVU_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) + +/* Structures definitions */ + +/* RVU admin function register address structure */ +struct rvu_af_addr_s { + uint64_t addr : 28; + uint64_t block : 5; + uint64_t rsvd_63_33 : 31; +}; + +/* RVU function-unique address structure */ +struct rvu_func_addr_s { + uint32_t addr : 12; + uint32_t lf_slot : 8; + uint32_t block : 5; + uint32_t rsvd_31_25 : 7; +}; + +/* RVU msi-x vector structure */ +struct rvu_msix_vec_s { + uint64_t addr : 64; /* W0 */ + uint64_t data : 32; + uint64_t mask : 1; + uint64_t pend : 1; + uint64_t rsvd_127_98 : 30; +}; + +/* RVU pf function identification structure */ +struct rvu_pf_func_s { + uint16_t func : 10; + uint16_t pf : 6; +}; + +#define RVU_CN9K_LMT_SLOT_MAX 256ULL +#define RVU_CN9K_LMT_SLOT_MASK (RVU_CN9K_LMT_SLOT_MAX - 1) + +#define RVU_LMT_SZ 128ULL + +/* 2048 LMT lines in BAR4 [CN10k, .) */ +#define RVU_LMT_LINE_MAX 2048 +#define RVU_LMT_LINE_BURST_MAX (uint16_t)32 /* [CN10K, .) */ + +#endif /* __RVU_HW_H__ */ diff --git a/drivers/common/cnxk/hw/sdp.h b/drivers/common/cnxk/hw/sdp.h new file mode 100644 index 0000000000..686f516097 --- /dev/null +++ b/drivers/common/cnxk/hw/sdp.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __SDP_HW_H_ +#define __SDP_HW_H_ + +/* SDP VF IOQs */ +#define SDP_MIN_RINGS_PER_VF (1) +#define SDP_MAX_RINGS_PER_VF (8) + +/* SDP VF IQ configuration */ +#define SDP_VF_MAX_IQ_DESCRIPTORS (512) +#define SDP_VF_MIN_IQ_DESCRIPTORS (128) + +#define SDP_VF_DB_MIN (1) +#define SDP_VF_DB_TIMEOUT (1) +#define SDP_VF_INTR_THRESHOLD (0xFFFFFFFF) + +#define SDP_VF_64BYTE_INSTR (64) +#define SDP_VF_32BYTE_INSTR (32) + +/* SDP VF OQ configuration */ +#define SDP_VF_MAX_OQ_DESCRIPTORS (512) +#define SDP_VF_MIN_OQ_DESCRIPTORS (128) +#define SDP_VF_OQ_BUF_SIZE (2048) +#define SDP_VF_OQ_REFIL_THRESHOLD (16) + +#define SDP_VF_OQ_INFOPTR_MODE (1) +#define SDP_VF_OQ_BUFPTR_MODE (0) + +#define SDP_VF_OQ_INTR_PKT (1) +#define SDP_VF_OQ_INTR_TIME (10) +#define SDP_VF_CFG_IO_QUEUES SDP_MAX_RINGS_PER_VF + +/* Wait time in milliseconds for FLR */ +#define SDP_VF_PCI_FLR_WAIT (100) +#define SDP_VF_BUSY_LOOP_COUNT (10000) + +#define SDP_VF_MAX_IO_QUEUES SDP_MAX_RINGS_PER_VF +#define SDP_VF_MIN_IO_QUEUES SDP_MIN_RINGS_PER_VF + +/* SDP VF IOQs per rawdev */ +#define SDP_VF_MAX_IOQS_PER_RAWDEV SDP_VF_MAX_IO_QUEUES +#define SDP_VF_DEFAULT_IOQS_PER_RAWDEV SDP_VF_MIN_IO_QUEUES + +/* SDP VF Register definitions */ +#define SDP_VF_RING_OFFSET (0x1ull << 17) + +/* SDP VF IQ Registers */ +#define SDP_VF_R_IN_CONTROL_START (0x10000) +#define SDP_VF_R_IN_ENABLE_START (0x10010) +#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020) +#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030) +#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040) +#define SDP_VF_R_IN_CNTS_START (0x10050) +#define SDP_VF_R_IN_INT_LEVELS_START (0x10060) +#define SDP_VF_R_IN_PKT_CNT_START (0x10080) +#define SDP_VF_R_IN_BYTE_CNT_START (0x10090) + +#define SDP_VF_R_IN_CONTROL(ring) \ + (SDP_VF_R_IN_CONTROL_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_ENABLE(ring) \ + (SDP_VF_R_IN_ENABLE_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_INSTR_BADDR(ring) \ + (SDP_VF_R_IN_INSTR_BADDR_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_INSTR_RSIZE(ring) \ + (SDP_VF_R_IN_INSTR_RSIZE_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_INSTR_DBELL(ring) \ + (SDP_VF_R_IN_INSTR_DBELL_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_CNTS(ring) \ + (SDP_VF_R_IN_CNTS_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_INT_LEVELS(ring) \ + (SDP_VF_R_IN_INT_LEVELS_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_PKT_CNT(ring) \ + (SDP_VF_R_IN_PKT_CNT_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_IN_BYTE_CNT(ring) \ + (SDP_VF_R_IN_BYTE_CNT_START + (SDP_VF_RING_OFFSET * (ring))) + +/* SDP VF IQ Masks */ +#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF) +#define SDP_VF_R_IN_CTL_RPVF_POS (48) + +#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28) +#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */ +#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24) +#define SDP_VF_R_IN_CTL_D_NSR (0x1ull << 8) +#define SDP_VF_R_IN_CTL_D_ESR (0x1ull << 6) +#define SDP_VF_R_IN_CTL_D_ROR (0x1ull << 5) +#define SDP_VF_R_IN_CTL_NSR (0x1ull << 3) +#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1) +#define SDP_VF_R_IN_CTL_ROR (0x1ull << 0) + +#define SDP_VF_R_IN_CTL_MASK (SDP_VF_R_IN_CTL_RDSIZE | SDP_VF_R_IN_CTL_IS_64B) + +/* SDP VF OQ Registers */ +#define SDP_VF_R_OUT_CNTS_START (0x10100) +#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110) +#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120) +#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130) +#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140) +#define SDP_VF_R_OUT_CONTROL_START (0x10150) +#define SDP_VF_R_OUT_ENABLE_START (0x10160) +#define SDP_VF_R_OUT_PKT_CNT_START (0x10180) +#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190) + +#define SDP_VF_R_OUT_CONTROL(ring) \ + (SDP_VF_R_OUT_CONTROL_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_ENABLE(ring) \ + (SDP_VF_R_OUT_ENABLE_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_SLIST_BADDR(ring) \ + (SDP_VF_R_OUT_SLIST_BADDR_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \ + (SDP_VF_R_OUT_SLIST_RSIZE_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_SLIST_DBELL(ring) \ + (SDP_VF_R_OUT_SLIST_DBELL_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_CNTS(ring) \ + (SDP_VF_R_OUT_CNTS_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_INT_LEVELS(ring) \ + (SDP_VF_R_OUT_INT_LEVELS_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_PKT_CNT(ring) \ + (SDP_VF_R_OUT_PKT_CNT_START + (SDP_VF_RING_OFFSET * (ring))) + +#define SDP_VF_R_OUT_BYTE_CNT(ring) \ + (SDP_VF_R_OUT_BYTE_CNT_START + (SDP_VF_RING_OFFSET * (ring))) + +/* SDP VF OQ Masks */ +#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40) +#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34) +#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33) +#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32) +#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30) +#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29) +#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28) +#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26) +#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25) +#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24) +#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23) + +#define SDP_VF_R_OUT_INT_LEVELS_BMODE (1ull << 63) +#define SDP_VF_R_OUT_INT_LEVELS_TIMET (32) + +/* SDP Instruction Header */ +struct sdp_instr_ih { + /* Data Len */ + uint64_t tlen : 16; + + /* Reserved1 */ + uint64_t rsvd1 : 20; + + /* PKIND for SDP */ + uint64_t pkind : 6; + + /* Front Data size */ + uint64_t fsz : 6; + + /* No. of entries in gather list */ + uint64_t gsz : 14; + + /* Gather indicator */ + uint64_t gather : 1; + + /* Reserved2 */ + uint64_t rsvd2 : 1; +} __plt_packed; + +#endif /* __SDP_HW_H_ */ diff --git a/drivers/common/cnxk/hw/sso.h b/drivers/common/cnxk/hw/sso.h new file mode 100644 index 0000000000..25deaa4c14 --- /dev/null +++ b/drivers/common/cnxk/hw/sso.h @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __SSO_HW_H__ +#define __SSO_HW_H__ + +/* Register offsets */ + +#define SSO_AF_CONST (0x1000ull) +#define SSO_AF_CONST1 (0x1008ull) +#define SSO_AF_WQ_INT_PC (0x1020ull) +#define SSO_AF_NOS_CNT (0x1050ull) /* [CN9K, CN10K) */ +#define SSO_AF_GWS_INV (0x1060ull) /* [CN10K, .) */ +#define SSO_AF_AW_WE (0x1080ull) +#define SSO_AF_WS_CFG (0x1088ull) +#define SSO_AF_GWE_CFG (0x1098ull) +#define SSO_AF_GWE_RANDOM (0x10b0ull) +#define SSO_AF_LF_HWGRP_RST (0x10e0ull) +#define SSO_AF_AW_CFG (0x10f0ull) +#define SSO_AF_BLK_RST (0x10f8ull) +#define SSO_AF_ACTIVE_CYCLES0 (0x1100ull) +#define SSO_AF_ACTIVE_CYCLES1 (0x1108ull) +#define SSO_AF_ACTIVE_CYCLES2 (0x1110ull) +#define SSO_AF_ERR0 (0x1220ull) +#define SSO_AF_ERR0_W1S (0x1228ull) +#define SSO_AF_ERR0_ENA_W1C (0x1230ull) +#define SSO_AF_ERR0_ENA_W1S (0x1238ull) +#define SSO_AF_ERR2 (0x1260ull) +#define SSO_AF_ERR2_W1S (0x1268ull) +#define SSO_AF_ERR2_ENA_W1C (0x1270ull) +#define SSO_AF_ERR2_ENA_W1S (0x1278ull) +#define SSO_AF_UNMAP_INFO (0x12f0ull) +#define SSO_AF_UNMAP_INFO2 (0x1300ull) +#define SSO_AF_UNMAP_INFO3 (0x1310ull) +#define SSO_AF_RAS (0x1420ull) +#define SSO_AF_RAS_W1S (0x1430ull) +#define SSO_AF_RAS_ENA_W1C (0x1460ull) +#define SSO_AF_RAS_ENA_W1S (0x1470ull) +#define SSO_AF_AW_INP_CTL (0x2070ull) +#define SSO_AF_AW_ADD (0x2080ull) +#define SSO_AF_AW_READ_ARB (0x2090ull) +#define SSO_AF_XAQ_REQ_PC (0x20b0ull) +#define SSO_AF_XAQ_LATENCY_PC (0x20b8ull) +#define SSO_AF_TAQ_CNT (0x20c0ull) +#define SSO_AF_TAQ_ADD (0x20e0ull) +#define SSO_AF_POISONX(a) (0x2100ull | (uint64_t)(a) << 3) +#define SSO_AF_POISONX_W1S(a) (0x2200ull | (uint64_t)(a) << 3) +#define SSO_PRIV_AF_INT_CFG (0x3000ull) +#define SSO_AF_RVU_LF_CFG_DEBUG (0x3800ull) +#define SSO_PRIV_LFX_HWGRP_CFG(a) (0x10000ull | (uint64_t)(a) << 3) +#define SSO_PRIV_LFX_HWGRP_INT_CFG(a) (0x20000ull | (uint64_t)(a) << 3) +#define SSO_AF_IU_ACCNTX_CFG(a) (0x50000ull | (uint64_t)(a) << 3) +#define SSO_AF_IU_ACCNTX_RST(a) (0x60000ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQX_HEAD_PTR(a) (0x80000ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQX_TAIL_PTR(a) (0x90000ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQX_HEAD_NEXT(a) (0xa0000ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQX_TAIL_NEXT(a) (0xb0000ull | (uint64_t)(a) << 3) +#define SSO_AF_TIAQX_STATUS(a) (0xc0000ull | (uint64_t)(a) << 3) +#define SSO_AF_TOAQX_STATUS(a) (0xd0000ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQX_GMCTL(a) (0xe0000ull | (uint64_t)(a) << 3) +#define SSO_AF_HWGRPX_IAQ_THR(a) (0x200000ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_TAQ_THR(a) (0x200010ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_PRI(a) (0x200020ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_AW_FWD(a) \ + (0x200030ull | (uint64_t)(a) << 12) /* [CN10K, .) */ +#define SSO_AF_HWGRPX_WS_PC(a) (0x200050ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_EXT_PC(a) (0x200060ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_WA_PC(a) (0x200070ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_TS_PC(a) (0x200080ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_DS_PC(a) (0x200090ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_DQ_PC(a) (0x2000A0ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_LS_PC(a) \ + (0x2000c0ull | (uint64_t)(a) << 12) /* [CN10K, .) */ +#define SSO_AF_HWGRPX_PAGE_CNT(a) (0x200100ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_AW_STATUS(a) (0x200110ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_AW_CFG(a) (0x200120ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_AW_TAGSPACE(a) (0x200130ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_XAQ_AURA(a) (0x200140ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_XAQ_LIMIT(a) (0x200220ull | (uint64_t)(a) << 12) +#define SSO_AF_HWGRPX_IU_ACCNT(a) (0x200230ull | (uint64_t)(a) << 12) +#define SSO_AF_HWSX_ARB(a) (0x400100ull | (uint64_t)(a) << 12) +#define SSO_AF_HWSX_INV(a) (0x400180ull | (uint64_t)(a) << 12) +#define SSO_AF_HWSX_GMCTL(a) (0x400200ull | (uint64_t)(a) << 12) +#define SSO_AF_HWSX_LSW_CFG(a) \ + (0x400300ull | (uint64_t)(a) << 12) /* [CN10K, .) */ +#define SSO_AF_HWSX_SX_GRPMSKX(a, b, c) \ + (0x400400ull | (uint64_t)(a) << 12 | (uint64_t)(b) << 5 | \ + (uint64_t)(c) << 3) +#define SSO_AF_TILEMAPX(a) \ + (0x400600ull | (uint64_t)(a) << 12) /* [CN10K, .) \ + */ +#define SSO_AF_IPL_FREEX(a) (0x800000ull | (uint64_t)(a) << 3) +#define SSO_AF_IPL_IAQX(a) (0x840000ull | (uint64_t)(a) << 3) +#define SSO_AF_IPL_DESCHEDX(a) (0x860000ull | (uint64_t)(a) << 3) +#define SSO_AF_IPL_CONFX(a) (0x880000ull | (uint64_t)(a) << 3) +#define SSO_AF_NPA_DIGESTX(a) (0x900000ull | (uint64_t)(a) << 3) +#define SSO_AF_NPA_DIGESTX_W1S(a) (0x900100ull | (uint64_t)(a) << 3) +#define SSO_AF_BFP_DIGESTX(a) (0x900200ull | (uint64_t)(a) << 3) +#define SSO_AF_BFP_DIGESTX_W1S(a) (0x900300ull | (uint64_t)(a) << 3) +#define SSO_AF_BFPN_DIGESTX(a) (0x900400ull | (uint64_t)(a) << 3) +#define SSO_AF_BFPN_DIGESTX_W1S(a) (0x900500ull | (uint64_t)(a) << 3) +#define SSO_AF_GRPDIS_DIGESTX(a) (0x900600ull | (uint64_t)(a) << 3) +#define SSO_AF_GRPDIS_DIGESTX_W1S(a) (0x900700ull | (uint64_t)(a) << 3) +#define SSO_AF_AWEMPTY_DIGESTX(a) (0x900800ull | (uint64_t)(a) << 3) +#define SSO_AF_AWEMPTY_DIGESTX_W1S(a) (0x900900ull | (uint64_t)(a) << 3) +#define SSO_AF_WQP0_DIGESTX(a) (0x900a00ull | (uint64_t)(a) << 3) +#define SSO_AF_WQP0_DIGESTX_W1S(a) (0x900b00ull | (uint64_t)(a) << 3) +#define SSO_AF_AW_DROPPED_DIGESTX(a) (0x900c00ull | (uint64_t)(a) << 3) +#define SSO_AF_AW_DROPPED_DIGESTX_W1S(a) (0x900d00ull | (uint64_t)(a) << 3) +#define SSO_AF_QCTLDIS_DIGESTX(a) (0x900e00ull | (uint64_t)(a) << 3) +#define SSO_AF_QCTLDIS_DIGESTX_W1S(a) (0x900f00ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQDIS_DIGESTX(a) (0x901000ull | (uint64_t)(a) << 3) +#define SSO_AF_XAQDIS_DIGESTX_W1S(a) (0x901100ull | (uint64_t)(a) << 3) +#define SSO_AF_FLR_AQ_DIGESTX(a) (0x901200ull | (uint64_t)(a) << 3) +#define SSO_AF_FLR_AQ_DIGESTX_W1S(a) (0x901300ull | (uint64_t)(a) << 3) +#define SSO_AF_WS_GMULTI_DIGESTX(a) (0x902000ull | (uint64_t)(a) << 3) +#define SSO_AF_WS_GMULTI_DIGESTX_W1S(a) (0x902100ull | (uint64_t)(a) << 3) +#define SSO_AF_WS_GUNMAP_DIGESTX(a) (0x902200ull | (uint64_t)(a) << 3) +#define SSO_AF_WS_GUNMAP_DIGESTX_W1S(a) (0x902300ull | (uint64_t)(a) << 3) +#define SSO_AF_WS_AWE_DIGESTX(a) \ + (0x902400ull | (uint64_t)(a) << 3) /* [CN9K, CN10K) */ +#define SSO_AF_WS_AWE_DIGESTX_W1S(a) \ + (0x902500ull | (uint64_t)(a) << 3) /* [CN9K, CN10K) */ +#define SSO_AF_WS_GWI_DIGESTX(a) \ + (0x902600ull | (uint64_t)(a) << 3) /* [CN9K, CN10K) */ +#define SSO_AF_WS_GWI_DIGESTX_W1S(a) \ + (0x902700ull | (uint64_t)(a) << 3) /* [CN9K, CN10K) */ +#define SSO_AF_WS_NE_DIGESTX(a) (0x902800ull | (uint64_t)(a) << 3) +#define SSO_AF_WS_NE_DIGESTX_W1S(a) (0x902900ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_TAG(a) (0xa00000ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_GRP(a) (0xa20000ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_PENDTAG(a) (0xa40000ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_LINKS(a) (0xa60000ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_QLINKS(a) (0xa80000ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_WQP(a) (0xaa0000ull | (uint64_t)(a) << 3) +#define SSO_AF_IENTX_LSW(a) \ + (0xac0000ull | (uint64_t)(a) << 3) /* [CN10K, .) */ + +#define SSO_AF_TAQX_LINK(a) (0xc00000ull | (uint64_t)(a) << 3) +#define SSO_AF_TAQX_WAEX_TAG(a, b) \ + (0xe00000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) +#define SSO_AF_TAQX_WAEX_WQP(a, b) \ + (0xe00008ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4) + +#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull) +#define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull) +#define SSO_LF_GGRP_QCTL (0x20ull) +#define SSO_LF_GGRP_EXE_DIS (0x80ull) +#define SSO_LF_GGRP_INT (0x100ull) +#define SSO_LF_GGRP_INT_W1S (0x108ull) +#define SSO_LF_GGRP_INT_ENA_W1S (0x110ull) +#define SSO_LF_GGRP_INT_ENA_W1C (0x118ull) +#define SSO_LF_GGRP_INT_THR (0x140ull) +#define SSO_LF_GGRP_INT_CNT (0x180ull) +#define SSO_LF_GGRP_XAQ_CNT (0x1b0ull) +#define SSO_LF_GGRP_AQ_CNT (0x1c0ull) +#define SSO_LF_GGRP_AQ_THR (0x1e0ull) +#define SSO_LF_GGRP_MISC_CNT (0x200ull) + +#define SSO_AF_IAQ_FREE_CNT_MASK 0x3FFFull +#define SSO_AF_IAQ_RSVD_FREE_MASK 0x3FFFull +#define SSO_AF_IAQ_RSVD_FREE_SHIFT 16 +#define SSO_AF_IAQ_FREE_CNT_MAX SSO_AF_IAQ_FREE_CNT_MASK +#define SSO_AF_AW_ADD_RSVD_FREE_MASK 0x3FFFull +#define SSO_AF_AW_ADD_RSVD_FREE_SHIFT 16 +#define SSO_HWGRP_IAQ_MAX_THR_MASK 0x3FFFull +#define SSO_HWGRP_IAQ_RSVD_THR_MASK 0x3FFFull +#define SSO_HWGRP_IAQ_MAX_THR_SHIFT 32 +#define SSO_HWGRP_IAQ_RSVD_THR 0x2 + +#define SSO_AF_TAQ_FREE_CNT_MASK 0x7FFull +#define SSO_AF_TAQ_RSVD_FREE_MASK 0x7FFull +#define SSO_AF_TAQ_RSVD_FREE_SHIFT 16 +#define SSO_AF_TAQ_FREE_CNT_MAX SSO_AF_TAQ_FREE_CNT_MASK +#define SSO_AF_TAQ_ADD_RSVD_FREE_MASK 0x1FFFull +#define SSO_AF_TAQ_ADD_RSVD_FREE_SHIFT 16 +#define SSO_HWGRP_TAQ_MAX_THR_MASK 0x7FFull +#define SSO_HWGRP_TAQ_RSVD_THR_MASK 0x7FFull +#define SSO_HWGRP_TAQ_MAX_THR_SHIFT 32 +#define SSO_HWGRP_TAQ_RSVD_THR 0x3 + +#define SSO_HWGRP_PRI_AFF_MASK 0xFull +#define SSO_HWGRP_PRI_AFF_SHIFT 8 +#define SSO_HWGRP_PRI_WGT_MASK 0x3Full +#define SSO_HWGRP_PRI_WGT_SHIFT 16 +#define SSO_HWGRP_PRI_WGT_LEFT_MASK 0x3Full +#define SSO_HWGRP_PRI_WGT_LEFT_SHIFT 24 + +#define SSO_HWGRP_AW_CFG_RWEN BIT_ULL(0) +#define SSO_HWGRP_AW_CFG_LDWB BIT_ULL(1) +#define SSO_HWGRP_AW_CFG_LDT BIT_ULL(2) +#define SSO_HWGRP_AW_CFG_STT BIT_ULL(3) +#define SSO_HWGRP_AW_CFG_XAQ_BYP_DIS BIT_ULL(4) + +#define SSO_HWGRP_AW_STS_TPTR_VLD BIT_ULL(8) +#define SSO_HWGRP_AW_STS_NPA_FETCH BIT_ULL(9) +#define SSO_HWGRP_AW_STS_XAQ_BUFSC_MASK 0x7ull +#define SSO_HWGRP_AW_STS_INIT_STS 0x18ull + +/* Enum offsets */ + +#define SSO_LF_INT_VEC_GRP (0x0ull) + +#define SSO_AF_INT_VEC_ERR0 (0x0ull) +#define SSO_AF_INT_VEC_ERR2 (0x1ull) +#define SSO_AF_INT_VEC_RAS (0x2ull) + +#define SSO_LSW_MODE_NO_LSW (0x0ull) /* [CN10K, .) */ +#define SSO_LSW_MODE_WAITW (0x1ull) /* [CN10K, .) */ +#define SSO_LSW_MODE_IMMED (0x2ull) /* [CN10K, .) */ + +#define SSO_WA_IOBN (0x0ull) +#define SSO_WA_ADDWQ (0x3ull) +#define SSO_WA_DPI (0x4ull) +#define SSO_WA_TIM (0x6ull) +#define SSO_WA_ZIP (0x7ull) /* [CN9K, CN10K) */ +#define SSO_WA_PSM (0x7ull) /* [CN10K, .) */ +#define SSO_WA_NIXRX0 (0x1ull) +#define SSO_WA_NIXRX1 (0x8ull) /* [CN10K, .) */ +#define SSO_WA_CPT0 (0x2ull) +#define SSO_WA_CPT1 (0x9ull) /* [CN10K, .) */ +#define SSO_WA_NIXTX0 (0x5ull) +#define SSO_WA_NIXTX1 (0xbull) /* [CN10K, .) */ +#define SSO_WA_ML0 (0xaull) /* [CN10K, .) */ +#define SSO_WA_ML1 (0xcull) /* [CN10K, .) */ + +#define SSO_TT_ORDERED (0x0ull) +#define SSO_TT_ATOMIC (0x1ull) +#define SSO_TT_UNTAGGED (0x2ull) +#define SSO_TT_EMPTY (0x3ull) + +#endif /* __SSO_HW_H__ */ diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h new file mode 100644 index 0000000000..618ab7973b --- /dev/null +++ b/drivers/common/cnxk/hw/ssow.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __SSOW_HW_H__ +#define __SSOW_HW_H__ + +/* Register offsets */ + +#define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x10ull) +#define SSOW_AF_LF_HWS_RST (0x30ull) +#define SSOW_PRIV_LFX_HWS_CFG(a) (0x1000ull | (uint64_t)(a) << 3) +#define SSOW_PRIV_LFX_HWS_INT_CFG(a) (0x2000ull | (uint64_t)(a) << 3) +#define SSOW_AF_SCRATCH_WS (0x100000ull) +#define SSOW_AF_SCRATCH_GW (0x200000ull) +#define SSOW_AF_SCRATCH_AW (0x300000ull) + +#define SSOW_LF_GWS_LINKS (0x10ull) +#define SSOW_LF_GWS_PENDWQP (0x40ull) /* [CN9K, CN10K) */ +#define SSOW_LF_GWS_PENDSTATE (0x50ull) +#define SSOW_LF_GWS_NW_TIM (0x70ull) +#define SSOW_LF_GWS_GRPMSK_CHG (0x80ull) +#define SSOW_LF_GWS_INT (0x100ull) +#define SSOW_LF_GWS_INT_W1S (0x108ull) +#define SSOW_LF_GWS_INT_ENA_W1S (0x110ull) +#define SSOW_LF_GWS_INT_ENA_W1C (0x118ull) +#define SSOW_LF_GWS_TAG (0x200ull) +#define SSOW_LF_GWS_WQP (0x210ull) +#define SSOW_LF_GWS_SWTP (0x220ull) +#define SSOW_LF_GWS_PENDTAG (0x230ull) +#define SSOW_LF_GWS_WQE0 (0x240ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_WQE1 (0x248ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull) /* [CN9K, CN10K) */ +#define SSOW_LF_GWS_PRF_TAG (0x400ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_PRF_WQP (0x410ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_PRF_WQE0 (0x440ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_PRF_WQE1 (0x448ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_OP_GET_WORK0 (0x600ull) +#define SSOW_LF_GWS_OP_GET_WORK1 (0x608ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull) +#define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull) +#define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull) +#define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull) +#define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull) +#define SSOW_LF_GWS_OP_DESCHED (0x880ull) +#define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull) /* [CN9K, CN10K) */ +#define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull) +#define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull) /* [CN9K, CN10K) */ +#define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull) /* [CN9K, CN10K) */ +#define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull) /* [CN9K, CN10K) */ +#define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull) +#define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull) +#define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull) +#define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull) +#define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull) + +/* Enum offsets */ + +#define SSOW_LF_INT_VEC_IOP (0x0ull) + +#define SSOW_GW_RESULT_GW_WORK (0x0ull) /* [CN10K, .) */ +#define SSOW_GW_RESULT_GW_NO_WORK (0x1ull) /* [CN10K, .) */ +#define SSOW_GW_RESULT_GW_ERROR (0x2ull) /* [CN10K, .) */ + +#define SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT 63 +#define SSOW_LF_GWS_TAG_PEND_SWITCH_BIT 62 +#define SSOW_LF_GWS_TAG_PEND_DESCHED_BIT 58 +#define SSOW_LF_GWS_TAG_HEAD_BIT 35 + +#endif /* __SSOW_HW_H__ */ diff --git a/drivers/common/cnxk/hw/tim.h b/drivers/common/cnxk/hw/tim.h new file mode 100644 index 0000000000..a0fe29ddcf --- /dev/null +++ b/drivers/common/cnxk/hw/tim.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __TIM_HW_H__ +#define __TIM_HW_H__ + +/* TIM */ +#define TIM_AF_CONST (0x90) +#define TIM_PRIV_LFX_CFG(a) (0x20000 | (a) << 3) +#define TIM_PRIV_LFX_INT_CFG(a) (0x24000 | (a) << 3) +#define TIM_AF_RVU_LF_CFG_DEBUG (0x30000) +#define TIM_AF_BLK_RST (0x10) +#define TIM_AF_LF_RST (0x20) +#define TIM_AF_BLK_RST (0x10) +#define TIM_AF_RINGX_GMCTL(a) (0x2000 | (a) << 3) +#define TIM_AF_RINGX_CTL0(a) (0x4000 | (a) << 3) +#define TIM_AF_RINGX_CTL1(a) (0x6000 | (a) << 3) +#define TIM_AF_RINGX_CTL2(a) (0x8000 | (a) << 3) +#define TIM_AF_FLAGS_REG (0x80) +#define TIM_AF_FLAGS_REG_ENA_TIM BIT_ULL(0) +#define TIM_AF_RINGX_CTL1_ENA BIT_ULL(47) +#define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50) +#define TIM_AF_RINGX_CLT1_CLK_10NS (0) +#define TIM_AF_RINGX_CLT1_CLK_GPIO (1) +#define TIM_AF_RINGX_CLT1_CLK_GTI (2) +#define TIM_AF_RINGX_CLT1_CLK_PTP (3) + +/* ENUMS */ + +#define TIM_LF_INT_VEC_NRSPERR_INT (0x0ull) +#define TIM_LF_INT_VEC_RAS_INT (0x1ull) +#define TIM_LF_RING_AURA (0x0) +#define TIM_LF_RING_BASE (0x130) +#define TIM_LF_NRSPERR_INT (0x200) +#define TIM_LF_NRSPERR_INT_W1S (0x208) +#define TIM_LF_NRSPERR_INT_ENA_W1S (0x210) +#define TIM_LF_NRSPERR_INT_ENA_W1C (0x218) +#define TIM_LF_RAS_INT (0x300) +#define TIM_LF_RAS_INT_W1S (0x308) +#define TIM_LF_RAS_INT_ENA_W1S (0x310) +#define TIM_LF_RAS_INT_ENA_W1C (0x318) +#define TIM_LF_RING_REL (0x400) + +#define TIM_MAX_INTERVAL_TICKS ((1ULL << 32) - 1) +#define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 1) +#define TIM_MIN_BUCKET_SIZE 3 + +#endif /* __TIM_HW_H__ */ diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build new file mode 100644 index 0000000000..d1160e6229 --- /dev/null +++ b/drivers/common/cnxk/meson.build @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2021 Marvell, Inc +# + +if not is_linux or not dpdk_conf.get('RTE_ARCH_64') + build = false + reason = 'only supported on 64-bit Linux' + subdir_done() +endif + +config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' +deps = ['eal', 'pci', 'bus_pci', 'mbuf'] +sources = files('roc_platform.c') +includes += include_directories('../../bus/pci') diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h new file mode 100644 index 0000000000..ec4ea248f2 --- /dev/null +++ b/drivers/common/cnxk/roc_api.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_API_H_ +#define _ROC_API_H_ + +#include +#include +#include + +/* Alignment */ +#define ROC_ALIGN 128 + +/* Bits manipulation */ +#include "roc_bits.h" + +/* Bitfields manipulation */ +#include "roc_bitfield.h" + +/* Constants */ +#define PLT_ETHER_ADDR_LEN 6 + +/* Platform definition */ +#include "roc_platform.h" + +#define ROC_LMT_LINES_PER_CORE_LOG2 5 +#define ROC_LMT_LINE_SIZE_LOG2 7 +#define ROC_LMT_BASE_PER_CORE_LOG2 \ + (ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2) + +/* PCI IDs */ +#define PCI_VENDOR_ID_CAVIUM 0x177D +#define PCI_DEVID_CNXK_RVU_PF 0xA063 +#define PCI_DEVID_CNXK_RVU_VF 0xA064 +#define PCI_DEVID_CNXK_RVU_AF 0xA065 +#define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9 +#define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA +#define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB +#define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC +#define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8 +#define PCI_DEVID_CNXK_DPI_VF 0xA081 +#define PCI_DEVID_CNXK_EP_VF 0xB203 +#define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6 +#define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7 + +#define PCI_DEVID_CN9K_CGX 0xA059 +#define PCI_DEVID_CN10K_RPM 0xA060 + +#define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 +#define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 + +#define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000 +#define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400 +#define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200 +#define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200 +#define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100 + +/* HW structure definition */ +#include "hw/nix.h" +#include "hw/npa.h" +#include "hw/npc.h" +#include "hw/rvu.h" +#include "hw/sdp.h" +#include "hw/sso.h" +#include "hw/ssow.h" +#include "hw/tim.h" + +#endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_bitfield.h b/drivers/common/cnxk/roc_bitfield.h new file mode 100644 index 0000000000..d64cce2c7b --- /dev/null +++ b/drivers/common/cnxk/roc_bitfield.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BITFIELD_H_ +#define _ROC_BITFIELD_H_ + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define FIELD_PREP(mask, val) (((typeof(mask))(val) << __bf_shf(mask)) & (mask)) + +#define FIELD_GET(mask, reg) \ + ((typeof(mask))(((reg) & (mask)) >> __bf_shf(mask))) + +#endif /* _ROC_BITFIELD_H_ */ diff --git a/drivers/common/cnxk/roc_bits.h b/drivers/common/cnxk/roc_bits.h new file mode 100644 index 0000000000..11216d9d63 --- /dev/null +++ b/drivers/common/cnxk/roc_bits.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BITS_H_ +#define _ROC_BITS_H_ + +#ifndef BIT_ULL +#define BIT_ULL(nr) (1ULL << (nr)) +#endif + +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + +#ifndef BITS_PER_LONG +#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) +#endif +#ifndef BITS_PER_LONG_LONG +#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8) +#endif + +#ifndef GENMASK +#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#endif +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) +#endif + +#endif /* _ROC_BITS_H_ */ diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c new file mode 100644 index 0000000000..6ddbc3b5a8 --- /dev/null +++ b/drivers/common/cnxk/roc_platform.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h new file mode 100644 index 0000000000..6d498b2227 --- /dev/null +++ b/drivers/common/cnxk/roc_platform.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_PLATFORM_H_ +#define _ROC_PLATFORM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "roc_bits.h" + +#if defined(__ARM_FEATURE_SVE) +#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse+sve\n" +#else +#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse\n" +#endif + +#define PLT_ASSERT RTE_ASSERT +#define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE +#define PLT_STD_C11 RTE_STD_C11 +#define PLT_PTR_ADD RTE_PTR_ADD +#define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID +#define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET +#define PLT_MIN RTE_MIN +#define PLT_MAX RTE_MAX +#define PLT_DIM RTE_DIM +#define PLT_SET_USED RTE_SET_USED +#define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) +#define PLT_ALIGN RTE_ALIGN +#define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL +#define PLT_MODEL_MZ_NAME "roc_model_mz" +#define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE +#define BITMASK_ULL GENMASK_ULL + +/** Divide ceil */ +#define PLT_DIV_CEIL(x, y) \ + ({ \ + __typeof(x) __x = x; \ + __typeof(y) __y = y; \ + (__x + __y - 1) / __y; \ + }) + +#define __plt_cache_aligned __rte_cache_aligned +#define __plt_always_inline __rte_always_inline +#define __plt_packed __rte_packed +#define __roc_api __rte_internal +#define plt_iova_t rte_iova_t + +#define plt_pci_device rte_pci_device +#define plt_pci_read_config rte_pci_read_config +#define plt_pci_find_ext_capability rte_pci_find_ext_capability + +#define plt_log2_u32 rte_log2_u32 +#define plt_cpu_to_be_16 rte_cpu_to_be_16 +#define plt_be_to_cpu_16 rte_be_to_cpu_16 +#define plt_cpu_to_be_32 rte_cpu_to_be_32 +#define plt_be_to_cpu_32 rte_be_to_cpu_32 +#define plt_cpu_to_be_64 rte_cpu_to_be_64 +#define plt_be_to_cpu_64 rte_be_to_cpu_64 + +#define plt_align32prevpow2 rte_align32prevpow2 + +#define plt_bitmap rte_bitmap +#define plt_bitmap_init rte_bitmap_init +#define plt_bitmap_reset rte_bitmap_reset +#define plt_bitmap_free rte_bitmap_free +#define plt_bitmap_clear rte_bitmap_clear +#define plt_bitmap_set rte_bitmap_set +#define plt_bitmap_get rte_bitmap_get +#define plt_bitmap_scan_init __rte_bitmap_scan_init +#define plt_bitmap_scan rte_bitmap_scan +#define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint + +#define plt_spinlock_t rte_spinlock_t +#define plt_spinlock_init rte_spinlock_init +#define plt_spinlock_lock rte_spinlock_lock +#define plt_spinlock_unlock rte_spinlock_unlock + +#define plt_intr_callback_register rte_intr_callback_register +#define plt_intr_callback_unregister rte_intr_callback_unregister +#define plt_intr_disable rte_intr_disable +#define plt_thread_is_intr rte_thread_is_intr +#define plt_intr_callback_fn rte_intr_callback_fn + +#define plt_alarm_set rte_eal_alarm_set +#define plt_alarm_cancel rte_eal_alarm_cancel + +#define plt_intr_handle rte_intr_handle + +#define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) +#define plt_free rte_free + +#define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) +#define plt_write64(val, addr) \ + rte_write64_relaxed((val), (volatile void *)(addr)) + +#define plt_wmb() rte_wmb() +#define plt_rmb() rte_rmb() +#define plt_io_wmb() rte_io_wmb() +#define plt_io_rmb() rte_io_rmb() + +#define plt_mmap mmap +#define PLT_PROT_READ PROT_READ +#define PLT_PROT_WRITE PROT_WRITE +#define PLT_MAP_SHARED MAP_SHARED + +#define plt_memzone rte_memzone +#define plt_memzone_lookup rte_memzone_lookup +#define plt_memzone_reserve_cache_align(name, sz) \ + rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) +#define plt_memzone_free rte_memzone_free + +#define plt_tsc_hz rte_get_tsc_hz +#define plt_delay_ms rte_delay_ms +#define plt_delay_us rte_delay_us + +#define plt_lcore_id rte_lcore_id + +#define plt_strlcpy rte_strlcpy + +#ifdef __cplusplus +#define CNXK_PCI_ID(subsystem_dev, dev) \ + { \ + RTE_CLASS_ANY_ID, \ + PCI_VENDOR_ID_CAVIUM, \ + (dev), \ + PCI_ANY_ID, \ + (subsystem_dev), \ + } +#else +#define CNXK_PCI_ID(subsystem_dev, dev) \ + { \ + .class_id = RTE_CLASS_ANY_ID, \ + .vendor_id = PCI_VENDOR_ID_CAVIUM, \ + .device_id = (dev), \ + .subsystem_vendor_id = PCI_ANY_ID, \ + .subsystem_device_id = (subsystem_dev), \ + } +#endif + +#endif /* _ROC_PLATFORM_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map new file mode 100644 index 0000000000..dc012a161b --- /dev/null +++ b/drivers/common/cnxk/version.map @@ -0,0 +1,4 @@ +INTERNAL { + + local: *; +}; diff --git a/drivers/meson.build b/drivers/meson.build index 0532c069d6..45af8749da 100644 --- a/drivers/meson.build +++ b/drivers/meson.build @@ -5,6 +5,7 @@ subdirs = [ 'common', 'bus', + 'common/cnxk', # depends on bus. 'common/mlx5', # depends on bus. 'common/qat', # depends on bus. 'common/sfc_efx', # depends on bus. -- 2.20.1