From fde7a772701ab150d08aa17e6de6803df298d083 Mon Sep 17 00:00:00 2001 From: Cristian Dumitrescu Date: Thu, 1 Oct 2020 11:20:09 +0100 Subject: [PATCH] examples/pipeline: add VXLAN encapsulation example Add VXLAN encapsulation example to the SWX pipeline application. The VXLAN tunnels can be generated with the vxlan_table.py script. Example command line: ./build/pipeline -l0-1 -- -s ./examples/vxlan.cli Signed-off-by: Cristian Dumitrescu --- examples/pipeline/examples/vxlan.cli | 27 ++++ examples/pipeline/examples/vxlan.spec | 173 +++++++++++++++++++++ examples/pipeline/examples/vxlan_pcap.cli | 22 +++ examples/pipeline/examples/vxlan_table.py | 72 +++++++++ examples/pipeline/examples/vxlan_table.txt | 16 ++ 5 files changed, 310 insertions(+) create mode 100644 examples/pipeline/examples/vxlan.cli create mode 100644 examples/pipeline/examples/vxlan.spec create mode 100644 examples/pipeline/examples/vxlan_pcap.cli create mode 100644 examples/pipeline/examples/vxlan_table.py create mode 100644 examples/pipeline/examples/vxlan_table.txt diff --git a/examples/pipeline/examples/vxlan.cli b/examples/pipeline/examples/vxlan.cli new file mode 100644 index 0000000000..7bf4a57575 --- /dev/null +++ b/examples/pipeline/examples/vxlan.cli @@ -0,0 +1,27 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2020 Intel Corporation + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on + +pipeline PIPELINE0 create 0 + +pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32 +pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32 +pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32 +pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32 + +pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 +pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 +pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 +pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 +pipeline PIPELINE0 port out 4 sink none + +pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec +pipeline PIPELINE0 table vxlan_table update ./examples/pipeline/examples/vxlan_table.txt none none + +thread 1 pipeline PIPELINE0 enable diff --git a/examples/pipeline/examples/vxlan.spec b/examples/pipeline/examples/vxlan.spec new file mode 100644 index 0000000000..b3f28630d2 --- /dev/null +++ b/examples/pipeline/examples/vxlan.spec @@ -0,0 +1,173 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2020 Intel Corporation + +// +// Headers +// +struct ethernet_h { + bit<48> dst_addr + bit<48> src_addr + bit<16> ethertype +} + +struct ipv4_h { + bit<8> ver_ihl + bit<8> diffserv + bit<16> total_len + bit<16> identification + bit<16> flags_offset + bit<8> ttl + bit<8> protocol + bit<16> hdr_checksum + bit<32> src_addr + bit<32> dst_addr +} + +struct udp_h { + bit<16> src_port + bit<16> dst_port + bit<16> length + bit<16> checksum +} + +struct vxlan_h { + bit<8> flags + bit<24> reserved + bit<24> vni + bit<8> reserved2 +} + +header ethernet instanceof ethernet_h +header ipv4 instanceof ipv4_h +header outer_ethernet instanceof ethernet_h +header outer_ipv4 instanceof ipv4_h +header outer_udp instanceof udp_h +header outer_vxlan instanceof vxlan_h + +// +// Meta-data +// +struct metadata_t { + bit<32> port_in + bit<32> port_out +} + +metadata instanceof metadata_t + +// +// Actions +// +struct vxlan_encap_args_t { + bit<48> ethernet_dst_addr + bit<48> ethernet_src_addr + bit<16> ethernet_ether_type + bit<8> ipv4_ver_ihl + bit<8> ipv4_diffserv + bit<16> ipv4_total_len + bit<16> ipv4_identification + bit<16> ipv4_flags_offset + bit<8> ipv4_ttl + bit<8> ipv4_protocol + bit<16> ipv4_hdr_checksum + bit<32> ipv4_src_addr + bit<32> ipv4_dst_addr + bit<16> udp_src_port + bit<16> udp_dst_port + bit<16> udp_length + bit<16> udp_checksum + bit<8> vxlan_flags + bit<24> vxlan_reserved + bit<24> vxlan_vni + bit<8> vxlan_reserved2 + bit<32> port_out +} + +// Input frame: +// Ethernet (14) | IPv4 (total_len) +// +// Output frame: +// Ethernet (14) | IPv4 (20) | UDP (8) | VXLAN (8) | Input frame | Ethernet FCS (4) +// +// Note: The input frame has its FCS removed before encapsulation in the output +// frame. +// +// Assumption: When read from the table, the outer IPv4 and UDP headers contain +// the following fields: +// - t.ipv4_total_len: Set to 50, which covers the length of: +// - The outer IPv4 header (20 bytes); +// - The outer UDP header (8 bytes); +// - The outer VXLAN header (8 bytes); +// - The inner Ethernet header (14 bytes); +// - t.ipv4_hdr_checksum: Includes the above total length. +// - t.udp_length: Set to 30, which covers the length of: +// - The outer UDP header (8 bytes); +// - The outer VXLAN header (8 bytes); +// - The inner Ethernet header (14 bytes); +// - t.udp_checksum: Set to 0. +// +// Once the total length of the inner IPv4 packet (h.ipv4.total_len) is known, +// the outer IPv4 and UDP headers are updated as follows: +// - h.outer_ipv4.total_len = t.ipv4_total_len + h.ipv4.total_len +// - h.outer_ipv4.hdr_checksum = t.ipv4_hdr_checksum + h.ipv4.total_len +// - h.outer_udp.length = t.udp_length + h.ipv4.total_len +// - h.outer_udp.checksum: No change. +// + +action vxlan_encap args instanceof vxlan_encap_args_t { + //Copy from table entry to headers and metadata. + dma h.outer_ethernet t.ethernet_dst_addr + dma h.outer_ipv4 t.ipv4_ver_ihl + dma h.outer_udp t.udp_src_port + dma h.outer_vxlan t.vxlan_flags + mov m.port_out t.port_out + + //Update h.outer_ipv4.total_len field. + add h.outer_ipv4.total_len h.ipv4.total_len + + //Update h.outer_ipv4.hdr_checksum field. + ckadd h.outer_ipv4.hdr_checksum h.ipv4.total_len + + //Update h.outer_udp.length field. + add h.outer_udp.length h.ipv4.total_len + + return +} + +action drop args none { + mov m.port_out 4 + tx m.port_out +} + +// +// Tables. +// +table vxlan_table { + key { + h.ethernet.dst_addr exact + } + + actions { + vxlan_encap + drop + } + + default_action drop args none + size 1048576 +} + +// +// Pipeline. +// +apply { + rx m.port_in + extract h.ethernet + extract h.ipv4 + table vxlan_table + emit h.outer_ethernet + emit h.outer_ipv4 + emit h.outer_udp + emit h.outer_vxlan + emit h.ethernet + emit h.ipv4 + tx m.port_out +} diff --git a/examples/pipeline/examples/vxlan_pcap.cli b/examples/pipeline/examples/vxlan_pcap.cli new file mode 100644 index 0000000000..1636ba080e --- /dev/null +++ b/examples/pipeline/examples/vxlan_pcap.cli @@ -0,0 +1,22 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2020 Intel Corporation + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +pipeline PIPELINE0 create 0 + +pipeline PIPELINE0 port in 0 source MEMPOOL0 ./examples/packet.pcap +pipeline PIPELINE0 port in 1 source MEMPOOL0 ./examples/packet.pcap +pipeline PIPELINE0 port in 2 source MEMPOOL0 ./examples/packet.pcap +pipeline PIPELINE0 port in 3 source MEMPOOL0 ./examples/packet.pcap + +pipeline PIPELINE0 port out 0 sink none +pipeline PIPELINE0 port out 1 sink none +pipeline PIPELINE0 port out 2 sink none +pipeline PIPELINE0 port out 3 sink none +pipeline PIPELINE0 port out 4 sink none + +pipeline PIPELINE0 build ./examples/vxlan.spec +pipeline PIPELINE0 table vxlan_table update ./examples/vxlan_table.txt none none + +thread 1 pipeline PIPELINE0 enable diff --git a/examples/pipeline/examples/vxlan_table.py b/examples/pipeline/examples/vxlan_table.py new file mode 100644 index 0000000000..820c208c7d --- /dev/null +++ b/examples/pipeline/examples/vxlan_table.py @@ -0,0 +1,72 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2020 Intel Corporation +# + +""" +A Python program that generates the VXLAN tunnels for this example. +""" + +import argparse + +DESCRIPTION = 'Table Generator' + +KEY = '0xaabbccdd{0:04x}' +ACTION = 'vxlan_encap' +ETHERNET_HEADER = 'ethernet_dst_addr N(0xa0a1a2a3{0:04x}) ' \ + 'ethernet_src_addr N(0xb0b1b2b3{0:04x}) ' \ + 'ethernet_ether_type N(0x0800)' +IPV4_HEADER = 'ipv4_ver_ihl N(0x45) ' \ + 'ipv4_diffserv N(0) ' \ + 'ipv4_total_len N(50) ' \ + 'ipv4_identification N(0) ' \ + 'ipv4_flags_offset N(0) ' \ + 'ipv4_ttl N(64) ' \ + 'ipv4_protocol N(17) ' \ + 'ipv4_hdr_checksum N(0x{1:04x}) ' \ + 'ipv4_src_addr N(0xc0c1{0:04x}) ' \ + 'ipv4_dst_addr N(0xd0d1{0:04x})' +UDP_HEADER = 'udp_src_port N(0xe0{0:02x}) ' \ + 'udp_dst_port N(4789) ' \ + 'udp_length N(30) ' \ + 'udp_checksum N(0)' +VXLAN_HEADER = 'vxlan_flags N(0) ' \ + 'vxlan_reserved N(0) ' \ + 'vxlan_vni N({0:d}) ' \ + 'vxlan_reserved2 N(0)' +PORT_OUT = 'port_out H({0:d})' + +def ipv4_header_checksum(i): + cksum = (0x4500 + 0x0032) + (0x0000 + 0x0000) + (0x4011 + 0x0000) + (0xc0c1 + i) + (0xd0d1 + i) + cksum = (cksum & 0xFFFF) + (cksum >> 16) + cksum = (cksum & 0xFFFF) + (cksum >> 16) + cksum = ~cksum & 0xFFFF + return cksum + +def table_generate(n, p): + for i in range(0, n): + print("match %s action %s %s %s %s %s %s" % + (KEY.format(i), ACTION, + ETHERNET_HEADER.format(i), + IPV4_HEADER.format(i, ipv4_header_checksum(i)), + UDP_HEADER.format(i % 256), + VXLAN_HEADER.format(i), + PORT_OUT.format(i % p))) + +if __name__ == '__main__': + parser = argparse.ArgumentParser(description=DESCRIPTION) + + parser.add_argument( + '-n', + help='number of table entries (default: 65536)', + required=False, + default=65536) + + parser.add_argument( + '-p', + help='number of network ports (default: 4)', + required=False, + default=4) + + args = parser.parse_args() + table_generate(int(args.n), int(args.p)) diff --git a/examples/pipeline/examples/vxlan_table.txt b/examples/pipeline/examples/vxlan_table.txt new file mode 100644 index 0000000000..acac80a387 --- /dev/null +++ b/examples/pipeline/examples/vxlan_table.txt @@ -0,0 +1,16 @@ +match 0xaabbccdd0000 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30000) ethernet_src_addr N(0xb0b1b2b30000) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe928) ipv4_src_addr N(0xc0c10000) ipv4_dst_addr N(0xd0d10000) udp_src_port N(0xe000) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(0) vxlan_reserved2 N(0) port_out H(0) +match 0xaabbccdd0001 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30001) ethernet_src_addr N(0xb0b1b2b30001) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe926) ipv4_src_addr N(0xc0c10001) ipv4_dst_addr N(0xd0d10001) udp_src_port N(0xe001) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(1) vxlan_reserved2 N(0) port_out H(1) +match 0xaabbccdd0002 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30002) ethernet_src_addr N(0xb0b1b2b30002) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe924) ipv4_src_addr N(0xc0c10002) ipv4_dst_addr N(0xd0d10002) udp_src_port N(0xe002) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(2) vxlan_reserved2 N(0) port_out H(2) +match 0xaabbccdd0003 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30003) ethernet_src_addr N(0xb0b1b2b30003) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe922) ipv4_src_addr N(0xc0c10003) ipv4_dst_addr N(0xd0d10003) udp_src_port N(0xe003) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(3) vxlan_reserved2 N(0) port_out H(3) +match 0xaabbccdd0004 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30004) ethernet_src_addr N(0xb0b1b2b30004) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe920) ipv4_src_addr N(0xc0c10004) ipv4_dst_addr N(0xd0d10004) udp_src_port N(0xe004) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(4) vxlan_reserved2 N(0) port_out H(0) +match 0xaabbccdd0005 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30005) ethernet_src_addr N(0xb0b1b2b30005) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe91e) ipv4_src_addr N(0xc0c10005) ipv4_dst_addr N(0xd0d10005) udp_src_port N(0xe005) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(5) vxlan_reserved2 N(0) port_out H(1) +match 0xaabbccdd0006 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30006) ethernet_src_addr N(0xb0b1b2b30006) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe91c) ipv4_src_addr N(0xc0c10006) ipv4_dst_addr N(0xd0d10006) udp_src_port N(0xe006) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(6) vxlan_reserved2 N(0) port_out H(2) +match 0xaabbccdd0007 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30007) ethernet_src_addr N(0xb0b1b2b30007) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe91a) ipv4_src_addr N(0xc0c10007) ipv4_dst_addr N(0xd0d10007) udp_src_port N(0xe007) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(7) vxlan_reserved2 N(0) port_out H(3) +match 0xaabbccdd0008 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30008) ethernet_src_addr N(0xb0b1b2b30008) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe918) ipv4_src_addr N(0xc0c10008) ipv4_dst_addr N(0xd0d10008) udp_src_port N(0xe008) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(8) vxlan_reserved2 N(0) port_out H(0) +match 0xaabbccdd0009 action vxlan_encap ethernet_dst_addr N(0xa0a1a2a30009) ethernet_src_addr N(0xb0b1b2b30009) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe916) ipv4_src_addr N(0xc0c10009) ipv4_dst_addr N(0xd0d10009) udp_src_port N(0xe009) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(9) vxlan_reserved2 N(0) port_out H(1) +match 0xaabbccdd000a action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000a) ethernet_src_addr N(0xb0b1b2b3000a) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe914) ipv4_src_addr N(0xc0c1000a) ipv4_dst_addr N(0xd0d1000a) udp_src_port N(0xe00a) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(10) vxlan_reserved2 N(0) port_out H(2) +match 0xaabbccdd000b action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000b) ethernet_src_addr N(0xb0b1b2b3000b) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe912) ipv4_src_addr N(0xc0c1000b) ipv4_dst_addr N(0xd0d1000b) udp_src_port N(0xe00b) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(11) vxlan_reserved2 N(0) port_out H(3) +match 0xaabbccdd000c action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000c) ethernet_src_addr N(0xb0b1b2b3000c) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe910) ipv4_src_addr N(0xc0c1000c) ipv4_dst_addr N(0xd0d1000c) udp_src_port N(0xe00c) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(12) vxlan_reserved2 N(0) port_out H(0) +match 0xaabbccdd000d action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000d) ethernet_src_addr N(0xb0b1b2b3000d) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe90e) ipv4_src_addr N(0xc0c1000d) ipv4_dst_addr N(0xd0d1000d) udp_src_port N(0xe00d) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(13) vxlan_reserved2 N(0) port_out H(1) +match 0xaabbccdd000e action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000e) ethernet_src_addr N(0xb0b1b2b3000e) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe90c) ipv4_src_addr N(0xc0c1000e) ipv4_dst_addr N(0xd0d1000e) udp_src_port N(0xe00e) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(14) vxlan_reserved2 N(0) port_out H(2) +match 0xaabbccdd000f action vxlan_encap ethernet_dst_addr N(0xa0a1a2a3000f) ethernet_src_addr N(0xb0b1b2b3000f) ethernet_ether_type N(0x0800) ipv4_ver_ihl N(0x45) ipv4_diffserv N(0) ipv4_total_len N(50) ipv4_identification N(0) ipv4_flags_offset N(0) ipv4_ttl N(64) ipv4_protocol N(17) ipv4_hdr_checksum N(0xe90a) ipv4_src_addr N(0xc0c1000f) ipv4_dst_addr N(0xd0d1000f) udp_src_port N(0xe00f) udp_dst_port N(4789) udp_length N(30) udp_checksum N(0) vxlan_flags N(0) vxlan_reserved N(0) vxlan_vni N(15) vxlan_reserved2 N(0) port_out H(3) -- 2.20.1