4 * Copyright(c) 2010-2013 Tilera Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Tilera Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <sys/queue.h>
46 #include <rte_common.h>
47 #include <rte_byteorder.h>
49 #include <rte_debug.h>
50 #include <rte_cycles.h>
51 #include <rte_memory.h>
52 #include <rte_memcpy.h>
53 #include <rte_launch.h>
55 #include <rte_per_lcore.h>
56 #include <rte_lcore.h>
57 #include <rte_atomic.h>
58 #include <rte_branch_prediction.h>
59 #include <rte_mempool.h>
61 #include <rte_interrupts.h>
63 #include <rte_ether.h>
64 #include <rte_ethdev.h>
68 #include <rte_string_fns.h>
73 /* hardcoded configuration (for now) */
74 static unsigned cfg_n_flows = 1024;
75 static uint32_t cfg_ip_src = RTE_IPV4(10, 254, 0, 0);
76 static uint32_t cfg_ip_dst = RTE_IPV4(10, 253, 0, 0);
77 static uint16_t cfg_udp_src = 1000;
78 static uint16_t cfg_udp_dst = 1001;
79 static struct rte_ether_addr cfg_ether_src =
80 {{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x00 }};
81 static struct rte_ether_addr cfg_ether_dst =
82 {{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x01 }};
84 #define IP_DEFTTL 64 /* from RFC 1340. */
86 static inline uint16_t
87 ip_sum(const unaligned_uint16_t *hdr, int hdr_len)
95 sum = (sum & 0xFFFF) + (sum >> 16);
100 sum = (sum & 0xFFFF) + (sum >> 16);
106 * Multi-flow generation mode.
108 * We originate a bunch of flows (varying destination IP addresses), and
109 * terminate receive traffic. Received traffic is simply discarded, but we
110 * still do so in order to maintain traffic statistics.
113 pkt_burst_flow_gen(struct fwd_stream *fs)
115 unsigned pkt_size = tx_pkt_length - 4; /* Adjust FCS */
116 struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
117 struct rte_mempool *mbp;
118 struct rte_mbuf *pkt;
119 struct rte_ether_hdr *eth_hdr;
120 struct rte_ipv4_hdr *ip_hdr;
121 struct rte_udp_hdr *udp_hdr;
122 uint16_t vlan_tci, vlan_tci_outer;
123 uint64_t ol_flags = 0;
129 uint64_t tx_offloads;
130 #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
133 uint64_t core_cycles;
135 static int next_flow = 0;
137 #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
138 start_tsc = rte_rdtsc();
141 /* Receive a burst of packets and discard them. */
142 nb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,
144 fs->rx_packets += nb_rx;
146 for (i = 0; i < nb_rx; i++)
147 rte_pktmbuf_free(pkts_burst[i]);
149 mbp = current_fwd_lcore()->mbp;
150 vlan_tci = ports[fs->tx_port].tx_vlan_id;
151 vlan_tci_outer = ports[fs->tx_port].tx_vlan_id_outer;
153 tx_offloads = ports[fs->tx_port].dev_conf.txmode.offloads;
154 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
155 ol_flags |= PKT_TX_VLAN_PKT;
156 if (tx_offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
157 ol_flags |= PKT_TX_QINQ_PKT;
158 if (tx_offloads & DEV_TX_OFFLOAD_MACSEC_INSERT)
159 ol_flags |= PKT_TX_MACSEC;
161 for (nb_pkt = 0; nb_pkt < nb_pkt_per_burst; nb_pkt++) {
162 pkt = rte_mbuf_raw_alloc(mbp);
166 pkt->data_len = pkt_size;
169 /* Initialize Ethernet header. */
170 eth_hdr = rte_pktmbuf_mtod(pkt, struct rte_ether_hdr *);
171 rte_ether_addr_copy(&cfg_ether_dst, ð_hdr->d_addr);
172 rte_ether_addr_copy(&cfg_ether_src, ð_hdr->s_addr);
173 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
175 /* Initialize IP header. */
176 ip_hdr = (struct rte_ipv4_hdr *)(eth_hdr + 1);
177 memset(ip_hdr, 0, sizeof(*ip_hdr));
178 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
179 ip_hdr->type_of_service = 0;
180 ip_hdr->fragment_offset = 0;
181 ip_hdr->time_to_live = IP_DEFTTL;
182 ip_hdr->next_proto_id = IPPROTO_UDP;
183 ip_hdr->packet_id = 0;
184 ip_hdr->src_addr = rte_cpu_to_be_32(cfg_ip_src);
185 ip_hdr->dst_addr = rte_cpu_to_be_32(cfg_ip_dst +
187 ip_hdr->total_length = RTE_CPU_TO_BE_16(pkt_size -
189 ip_hdr->hdr_checksum = ip_sum((unaligned_uint16_t *)ip_hdr,
192 /* Initialize UDP header. */
193 udp_hdr = (struct rte_udp_hdr *)(ip_hdr + 1);
194 udp_hdr->src_port = rte_cpu_to_be_16(cfg_udp_src);
195 udp_hdr->dst_port = rte_cpu_to_be_16(cfg_udp_dst);
196 udp_hdr->dgram_cksum = 0; /* No UDP checksum. */
197 udp_hdr->dgram_len = RTE_CPU_TO_BE_16(pkt_size -
201 pkt->pkt_len = pkt_size;
202 pkt->ol_flags = ol_flags;
203 pkt->vlan_tci = vlan_tci;
204 pkt->vlan_tci_outer = vlan_tci_outer;
205 pkt->l2_len = sizeof(struct rte_ether_hdr);
206 pkt->l3_len = sizeof(struct rte_ipv4_hdr);
207 pkts_burst[nb_pkt] = pkt;
209 next_flow = (next_flow + 1) % cfg_n_flows;
212 nb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_pkt);
216 if (unlikely(nb_tx < nb_rx) && fs->retry_enabled) {
218 while (nb_tx < nb_rx && retry++ < burst_tx_retry_num) {
219 rte_delay_us(burst_tx_delay_time);
220 nb_tx += rte_eth_tx_burst(fs->tx_port, fs->tx_queue,
221 &pkts_burst[nb_tx], nb_rx - nb_tx);
224 fs->tx_packets += nb_tx;
226 #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
227 fs->tx_burst_stats.pkt_burst_spread[nb_tx]++;
229 if (unlikely(nb_tx < nb_pkt)) {
230 /* Back out the flow counter. */
231 next_flow -= (nb_pkt - nb_tx);
232 while (next_flow < 0)
233 next_flow += cfg_n_flows;
236 rte_pktmbuf_free(pkts_burst[nb_tx]);
237 } while (++nb_tx < nb_pkt);
239 #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
240 end_tsc = rte_rdtsc();
241 core_cycles = (end_tsc - start_tsc);
242 fs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);
246 struct fwd_engine flow_gen_engine = {
247 .fwd_mode_name = "flowgen",
248 .port_fwd_begin = NULL,
249 .port_fwd_end = NULL,
250 .packet_fwd = pkt_burst_flow_gen,