4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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14 * notice, this list of conditions and the following disclaimer in
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42 #include <sys/queue.h>
45 #include <rte_common.h>
46 #include <rte_byteorder.h>
48 #include <rte_debug.h>
49 #include <rte_cycles.h>
50 #include <rte_memory.h>
51 #include <rte_memzone.h>
52 #include <rte_launch.h>
53 #include <rte_tailq.h>
55 #include <rte_per_lcore.h>
56 #include <rte_lcore.h>
57 #include <rte_atomic.h>
58 #include <rte_branch_prediction.h>
60 #include <rte_memory.h>
61 #include <rte_mempool.h>
63 #include <rte_interrupts.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_string_fns.h>
72 * The structure of a PTP V2 packet.
74 * Only the minimum fields used by the ieee1588 test are represented.
78 uint8_t version; /**< must be 0x02 */
81 #define PTP_SYNC_MESSAGE 0x0
82 #define PTP_DELAY_REQ_MESSAGE 0x1
83 #define PTP_PATH_DELAY_REQ_MESSAGE 0x2
84 #define PTP_PATH_DELAY_RESP_MESSAGE 0x3
85 #define PTP_FOLLOWUP_MESSAGE 0x8
86 #define PTP_DELAY_RESP_MESSAGE 0x9
87 #define PTP_PATH_DELAY_FOLLOWUP_MESSAGE 0xA
88 #define PTP_ANNOUNCE_MESSAGE 0xB
89 #define PTP_SIGNALLING_MESSAGE 0xC
90 #define PTP_MANAGEMENT_MESSAGE 0xD
93 * Forwarding of IEEE1588 Precise Time Protocol (PTP) packets.
95 * In this mode, packets are received one by one and are expected to be
96 * PTP V2 L2 Ethernet frames (with the specific Ethernet type "0x88F7")
97 * containing PTP "sync" messages (version 2 at offset 1, and message ID
100 * Check that each received packet is a IEEE1588 PTP V2 packet of type
101 * PTP_SYNC_MESSAGE, and that it has been identified and timestamped
103 * Check that the value of the last RX timestamp recorded by the controller
104 * is greater than the previous one.
106 * If everything is OK, send the received packet back on the same port,
107 * requesting for it to be timestamped by the hardware.
108 * Check that the value of the last TX timestamp recorded by the controller
109 * is greater than the previous one.
113 * 1GbE 82576 Kawela registers used for IEEE1588 hardware support
115 #define IGBE_82576_ETQF(n) (0x05CB0 + (4 * (n)))
116 #define IGBE_82576_ETQF_FILTER_ENABLE (1 << 26)
117 #define IGBE_82576_ETQF_1588_TIMESTAMP (1 << 30)
119 #define IGBE_82576_TSYNCRXCTL 0x0B620
120 #define IGBE_82576_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
122 #define IGBE_82576_RXSTMPL 0x0B624
123 #define IGBE_82576_RXSTMPH 0x0B628
124 #define IGBE_82576_RXSATRL 0x0B62C
125 #define IGBE_82576_RXSATRH 0x0B630
126 #define IGBE_82576_TSYNCTXCTL 0x0B614
127 #define IGBE_82576_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
129 #define IGBE_82576_TXSTMPL 0x0B618
130 #define IGBE_82576_TXSTMPH 0x0B61C
131 #define IGBE_82576_SYSTIML 0x0B600
132 #define IGBE_82576_SYSTIMH 0x0B604
133 #define IGBE_82576_TIMINCA 0x0B608
134 #define IGBE_82576_TIMADJL 0x0B60C
135 #define IGBE_82576_TIMADJH 0x0B610
136 #define IGBE_82576_TSAUXC 0x0B640
137 #define IGBE_82576_TRGTTIML0 0x0B644
138 #define IGBE_82576_TRGTTIMH0 0x0B648
139 #define IGBE_82576_TRGTTIML1 0x0B64C
140 #define IGBE_82576_TRGTTIMH1 0x0B650
141 #define IGBE_82576_AUXSTMPL0 0x0B65C
142 #define IGBE_82576_AUXSTMPH0 0x0B660
143 #define IGBE_82576_AUXSTMPL1 0x0B664
144 #define IGBE_82576_AUXSTMPH1 0x0B668
145 #define IGBE_82576_TSYNCRXCFG 0x05F50
146 #define IGBE_82576_TSSDP 0x0003C
149 * 10GbE 82599 Niantic registers used for IEEE1588 hardware support
151 #define IXGBE_82599_ETQF(n) (0x05128 + (4 * (n)))
152 #define IXGBE_82599_ETQF_FILTER_ENABLE (1 << 31)
153 #define IXGBE_82599_ETQF_1588_TIMESTAMP (1 << 30)
155 #define IXGBE_82599_TSYNCRXCTL 0x05188
156 #define IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
158 #define IXGBE_82599_RXSTMPL 0x051E8
159 #define IXGBE_82599_RXSTMPH 0x051A4
160 #define IXGBE_82599_RXSATRL 0x051A0
161 #define IXGBE_82599_RXSATRH 0x051A8
162 #define IXGBE_82599_RXMTRL 0x05120
163 #define IXGBE_82599_TSYNCTXCTL 0x08C00
164 #define IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
166 #define IXGBE_82599_TXSTMPL 0x08C04
167 #define IXGBE_82599_TXSTMPH 0x08C08
168 #define IXGBE_82599_SYSTIML 0x08C0C
169 #define IXGBE_82599_SYSTIMH 0x08C10
170 #define IXGBE_82599_TIMINCA 0x08C14
171 #define IXGBE_82599_TIMADJL 0x08C18
172 #define IXGBE_82599_TIMADJH 0x08C1C
173 #define IXGBE_82599_TSAUXC 0x08C20
174 #define IXGBE_82599_TRGTTIML0 0x08C24
175 #define IXGBE_82599_TRGTTIMH0 0x08C28
176 #define IXGBE_82599_TRGTTIML1 0x08C2C
177 #define IXGBE_82599_TRGTTIMH1 0x08C30
178 #define IXGBE_82599_AUXSTMPL0 0x08C3C
179 #define IXGBE_82599_AUXSTMPH0 0x08C40
180 #define IXGBE_82599_AUXSTMPL1 0x08C44
181 #define IXGBE_82599_AUXSTMPH1 0x08C48
184 * Mandatory ETQF register for IEEE1588 packets filter.
186 #define ETQF_FILTER_1588_REG 3
189 * Recommended value for increment and period of
190 * the Increment Attribute Register.
192 #define IEEE1588_TIMINCA_INIT ((0x02 << 24) | 0x00F42400)
195 * Data structure with pointers to port-specific functions.
197 typedef void (*ieee1588_start_t)(portid_t pi); /**< Start IEEE1588 feature. */
198 typedef void (*ieee1588_stop_t)(portid_t pi); /**< Stop IEEE1588 feature. */
199 typedef int (*tmst_read_t)(portid_t pi, uint64_t *tmst); /**< Read TMST regs */
201 struct port_ieee1588_ops {
202 ieee1588_start_t ieee1588_start;
203 ieee1588_stop_t ieee1588_stop;
204 tmst_read_t rx_tmst_read;
205 tmst_read_t tx_tmst_read;
209 * 1GbE 82576 IEEE1588 operations.
212 igbe_82576_ieee1588_start(portid_t pi)
217 * Start incrementation of the System Time registers used to
218 * timestamp PTP packets.
220 port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, IEEE1588_TIMINCA_INIT);
221 port_id_pci_reg_write(pi, IGBE_82576_TSAUXC, 0);
224 * Enable L2 filtering of IEEE1588 Ethernet frame types.
226 port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG),
228 IGBE_82576_ETQF_FILTER_ENABLE |
229 IGBE_82576_ETQF_1588_TIMESTAMP));
232 * Enable timestamping of received PTP packets.
234 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
235 tsync_ctl |= IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
236 port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
239 * Enable Timestamping of transmitted PTP packets.
241 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
242 tsync_ctl |= IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
243 port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
247 igbe_82576_ieee1588_stop(portid_t pi)
252 * Disable Timestamping of transmitted PTP packets.
254 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
255 tsync_ctl &= ~IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
256 port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
259 * Disable timestamping of received PTP packets.
261 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
262 tsync_ctl &= ~IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
263 port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
266 * Disable L2 filtering of IEEE1588 Ethernet types.
268 port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG), 0);
271 * Stop incrementation of the System Time registers.
273 port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, 0);
277 * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
278 * of a 1GbE 82576 port.
281 * The port identifier.
284 * The address of a 64-bit variable to return the value of the RX timestamp.
287 * -1: the RXSTMPL and RXSTMPH registers of the port are not valid.
288 * 0: the variable pointed to by the "tmst" parameter contains the value
289 * of the RXSTMPL and RXSTMPH registers of the port.
292 igbe_82576_rx_timestamp_read(portid_t pi, uint64_t *tmst)
294 uint32_t tsync_rxctl;
298 tsync_rxctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
299 if ((tsync_rxctl & 0x01) == 0)
302 rx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPL);
303 rx_stmph = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPH);
304 *tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
309 * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
310 * of a 1GbE 82576 port.
313 * The port identifier.
316 * The address of a 64-bit variable to return the value of the TX timestamp.
319 * -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
320 * 0: the variable pointed to by the "tmst" parameter contains the value
321 * of the TXSTMPL and TXSTMPH registers of the port.
324 igbe_82576_tx_timestamp_read(portid_t pi, uint64_t *tmst)
326 uint32_t tsync_txctl;
330 tsync_txctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
331 if ((tsync_txctl & 0x01) == 0)
334 tx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPL);
335 tx_stmph = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPH);
336 *tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
340 static struct port_ieee1588_ops igbe_82576_ieee1588_ops = {
341 .ieee1588_start = igbe_82576_ieee1588_start,
342 .ieee1588_stop = igbe_82576_ieee1588_stop,
343 .rx_tmst_read = igbe_82576_rx_timestamp_read,
344 .tx_tmst_read = igbe_82576_tx_timestamp_read,
348 * 10GbE 82599 IEEE1588 operations.
351 ixgbe_82599_ieee1588_start(portid_t pi)
356 * Start incrementation of the System Time registers used to
357 * timestamp PTP packets.
359 port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, IEEE1588_TIMINCA_INIT);
362 * Enable L2 filtering of IEEE1588 Ethernet frame types.
364 port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG),
366 IXGBE_82599_ETQF_FILTER_ENABLE |
367 IXGBE_82599_ETQF_1588_TIMESTAMP));
370 * Enable timestamping of received PTP packets.
372 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
373 tsync_ctl |= IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
374 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
377 * Enable Timestamping of transmitted PTP packets.
379 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
380 tsync_ctl |= IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
381 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
385 ixgbe_82599_ieee1588_stop(portid_t pi)
390 * Disable Timestamping of transmitted PTP packets.
392 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
393 tsync_ctl &= ~IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
394 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
397 * Disable timestamping of received PTP packets.
399 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
400 tsync_ctl &= ~IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
401 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
404 * Disable L2 filtering of IEEE1588 Ethernet frame types.
406 port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG), 0);
409 * Stop incrementation of the System Time registers.
411 port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, 0);
415 * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
416 * of a 10GbE 82599 port.
419 * The port identifier.
422 * The address of a 64-bit variable to return the value of the TX timestamp.
425 * -1: the RX timestamp registers of the port are not valid.
426 * 0: the variable pointed to by the "tmst" parameter contains the value
427 * of the RXSTMPL and RXSTMPH registers of the port.
430 ixgbe_82599_rx_timestamp_read(portid_t pi, uint64_t *tmst)
432 uint32_t tsync_rxctl;
436 tsync_rxctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
437 if ((tsync_rxctl & 0x01) == 0)
440 rx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPL);
441 rx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPH);
442 *tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
447 * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
448 * of a 10GbE 82599 port.
451 * The port identifier.
454 * The address of a 64-bit variable to return the value of the TX timestamp.
457 * -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
458 * 0: the variable pointed to by the "tmst" parameter contains the value
459 * of the TXSTMPL and TXSTMPH registers of the port.
462 ixgbe_82599_tx_timestamp_read(portid_t pi, uint64_t *tmst)
464 uint32_t tsync_txctl;
468 tsync_txctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
469 if ((tsync_txctl & 0x01) == 0)
472 tx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPL);
473 tx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPH);
474 *tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
478 static struct port_ieee1588_ops ixgbe_82599_ieee1588_ops = {
479 .ieee1588_start = ixgbe_82599_ieee1588_start,
480 .ieee1588_stop = ixgbe_82599_ieee1588_stop,
481 .rx_tmst_read = ixgbe_82599_rx_timestamp_read,
482 .tx_tmst_read = ixgbe_82599_tx_timestamp_read,
486 port_ieee1588_rx_timestamp_check(portid_t pi)
488 struct port_ieee1588_ops *ieee_ops;
491 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
492 if (ieee_ops->rx_tmst_read(pi, &rx_tmst) < 0) {
493 printf("Port %u: RX timestamp registers not valid\n",
497 printf("Port %u RX timestamp value 0x%"PRIu64"\n",
498 (unsigned) pi, rx_tmst);
501 #define MAX_TX_TMST_WAIT_MICROSECS 1000 /**< 1 milli-second */
504 port_ieee1588_tx_timestamp_check(portid_t pi)
506 struct port_ieee1588_ops *ieee_ops;
510 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
512 while ((ieee_ops->tx_tmst_read(pi, &tx_tmst) < 0) &&
513 (wait_us < MAX_TX_TMST_WAIT_MICROSECS)) {
517 if (wait_us >= MAX_TX_TMST_WAIT_MICROSECS) {
518 printf("Port %u: TX timestamp registers not valid after"
519 "%u micro-seconds\n",
520 (unsigned) pi, (unsigned) MAX_TX_TMST_WAIT_MICROSECS);
523 printf("Port %u TX timestamp value 0x%"PRIu64" validated after "
524 "%u micro-second%s\n",
525 (unsigned) pi, tx_tmst, wait_us,
526 (wait_us == 1) ? "" : "s");
530 ieee1588_packet_fwd(struct fwd_stream *fs)
533 struct ether_hdr *eth_hdr;
534 struct ptpv2_msg *ptp_hdr;
538 * Receive 1 packet at a time.
540 if (rte_eth_rx_burst(fs->rx_port, fs->rx_queue, &mb, 1) == 0)
546 * Check that the received packet is a PTP packet that was detected
549 eth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);
550 eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
551 if (! (mb->ol_flags & PKT_RX_IEEE1588_PTP)) {
552 if (eth_type == ETHER_TYPE_1588) {
553 printf("Port %u Received PTP packet not filtered"
555 (unsigned) fs->rx_port);
557 printf("Port %u Received non PTP packet type=0x%4x "
559 (unsigned) fs->rx_port, eth_type,
560 (unsigned) mb->pkt_len);
562 rte_pktmbuf_free(mb);
565 if (eth_type != ETHER_TYPE_1588) {
566 printf("Port %u Received NON PTP packet wrongly"
567 " detected by hardware\n",
568 (unsigned) fs->rx_port);
569 rte_pktmbuf_free(mb);
574 * Check that the received PTP packet is a PTP V2 packet of type
577 ptp_hdr = (struct ptpv2_msg *) (rte_pktmbuf_mtod(mb, char *) +
578 sizeof(struct ether_hdr));
579 if (ptp_hdr->version != 0x02) {
580 printf("Port %u Received PTP V2 Ethernet frame with wrong PTP"
581 " protocol version 0x%x (should be 0x02)\n",
582 (unsigned) fs->rx_port, ptp_hdr->version);
583 rte_pktmbuf_free(mb);
586 if (ptp_hdr->msg_id != PTP_SYNC_MESSAGE) {
587 printf("Port %u Received PTP V2 Ethernet frame with unexpected"
588 " messageID 0x%x (expected 0x0 - PTP_SYNC_MESSAGE)\n",
589 (unsigned) fs->rx_port, ptp_hdr->msg_id);
590 rte_pktmbuf_free(mb);
593 printf("Port %u IEEE1588 PTP V2 SYNC Message filtered by hardware\n",
594 (unsigned) fs->rx_port);
597 * Check that the received PTP packet has been timestamped by the
600 if (! (mb->ol_flags & PKT_RX_IEEE1588_TMST)) {
601 printf("Port %u Received PTP packet not timestamped"
603 (unsigned) fs->rx_port);
604 rte_pktmbuf_free(mb);
608 /* Check the RX timestamp */
609 port_ieee1588_rx_timestamp_check(fs->rx_port);
611 /* Forward PTP packet with hardware TX timestamp */
612 mb->ol_flags |= PKT_TX_IEEE1588_TMST;
614 if (rte_eth_tx_burst(fs->rx_port, fs->tx_queue, &mb, 1) == 0) {
615 printf("Port %u sent PTP packet dropped\n",
616 (unsigned) fs->rx_port);
617 fs->fwd_dropped += 1;
618 rte_pktmbuf_free(mb);
623 * Check the TX timestamp.
625 port_ieee1588_tx_timestamp_check(fs->rx_port);
629 port_ieee1588_fwd_begin(portid_t pi)
631 struct port_ieee1588_ops *ieee_ops;
633 if (strcmp(ports[pi].dev_info.driver_name, "rte_igb_pmd") == 0)
634 ieee_ops = &igbe_82576_ieee1588_ops;
636 ieee_ops = &ixgbe_82599_ieee1588_ops;
637 ports[pi].fwd_ctx = ieee_ops;
638 (ieee_ops->ieee1588_start)(pi);
642 port_ieee1588_fwd_end(portid_t pi)
644 struct port_ieee1588_ops *ieee_ops;
646 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
647 (ieee_ops->ieee1588_stop)(pi);
650 struct fwd_engine ieee1588_fwd_engine = {
651 .fwd_mode_name = "ieee1588",
652 .port_fwd_begin = port_ieee1588_fwd_begin,
653 .port_fwd_end = port_ieee1588_fwd_end,
654 .packet_fwd = ieee1588_packet_fwd,