arch/stm32/include/ucg_reent_intr.h

   1 /*
   2  * Copyright 2016, Fabrice DESCLAUX <serpilliere@droids-corp.org>
   3  * Copyright 2016, Olivier MATZ <zer0@droids-corp.org>
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of the University of California, Berkeley nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY
  18  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  19  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  20  * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY
  21  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  22  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  23  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  24  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  26  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef UCG_REENT_INTR_H_
  30 #define UCG_REENT_INTR_H_
  31
  32 /* XXX doc */
  33 void ucg_reent_intr(uint32_t *context, void *fct);
  34 //void ucg_reent_intr(uint32_t *context);
  35
  36 /*
  37 .align 4
  38 .long my_var
  39 */
  40 #define UCG_REENT_INTR(f)                               \
  41         __asm__ volatile (                              \
  42                 "SUB    SP, SP, 0x38     \n"            \
  43                 "STR    LR, [SP]         \n"            \
  44                 "ADD    R0, SP, 0x10     \n"            \
  45                 "LDR    R1, =" #f "      \n"            \
  46                 "BL     ucg_reent_intr   \n"            \
  47                 "POP    {LR}             \n"            \
  48                 "ADD    SP, SP, 0xC      \n"            \
  49                 "BX     LR               \n"            \
  50                 :                                       \
  51                 :                                       \
  52                 : /* No clobbers */                     \
  53         )
  54
  55 #define old_UCG_REENT_INTR(f)                           \
  56         __asm__ volatile (                              \
  57                 "SUB    SP, SP, 0x38     \n"            \
  58                 "STR    LR, [SP]         \n"            \
  59                 "ADD    R0, SP, 0x10     \n"            \
  60                 "MOV    R1, %[value]     \n"            \
  61                 "BL     ucg_reent_intr   \n"            \
  62                 "POP    {LR}             \n"            \
  63                 "ADD    SP, SP, 0xC      \n"            \
  64                 "BX     LR               \n"            \
  65                 :                                       \
  66                 : [value]"r"   ((uint32_t)f)            \
  67                 : /* No clobbers */                     \
  68         )
  69
  70 #define XXX_UCG_REENT_INTR(f)                           \
  71         __asm__ volatile (                              \
  72                 "SUB    SP, SP, 0x38     \n"            \
  73                 "STR    LR, [SP]         \n"            \
  74                 "ADD    R0, SP, 0x10     \n"            \
  75                 "BL     ucg_reent_intr   \n"            \
  76                 "POP    {LR}             \n"            \
  77                 "ADD    SP, SP, 0xC      \n"            \
  78                 "BX     LR               \n"            \
  79         )
  80
  81 #endif