config/arm/meson.build

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright(c) 2017 Intel Corporation.
   3 # Copyright(c) 2017 Cavium, Inc
   4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
   5
   6 # common flags to all aarch64 builds, with lowest priority
   7 flags_common = [
   8         # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
   9         # to determine the best threshold in code. Refer to notes in source file
  10         # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
  11         ['RTE_ARCH_ARM64_MEMCPY', false],
  12         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
  13         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
  14         # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
  15         # unless there are strong reasons.
  16         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
  17         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
  18         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
  19
  20         ['RTE_SCHED_VECTOR', false],
  21         ['RTE_ARM_USE_WFE', false],
  22         ['RTE_ARCH_ARM64', true],
  23         ['RTE_CACHE_LINE_SIZE', 128]
  24 ]
  25
  26 ## Part numbers are specific to Arm implementers
  27 # implementer specific aarch64 flags have middle priority
  28 #     (will overwrite common flags)
  29 # part number specific aarch64 flags have higher priority
  30 #     (will overwrite both common and implementer specific flags)
  31 implementer_generic = {
  32         'description': 'Generic armv8',
  33         'flags': [
  34                 ['RTE_MACHINE', '"armv8a"'],
  35                 ['RTE_USE_C11_MEM_MODEL', true],
  36                 ['RTE_MAX_LCORE', 256],
  37                 ['RTE_MAX_NUMA_NODES', 4]
  38         ],
  39         'part_number_config': {
  40                 'generic': {'machine_args': ['-march=armv8-a+crc',
  41                                              '-moutline-atomics']}
  42         }
  43 }
  44
  45 part_number_config_arm = {
  46         '0xd03': {'machine_args':  ['-mcpu=cortex-a53']},
  47         '0xd04': {'machine_args':  ['-mcpu=cortex-a35']},
  48         '0xd07': {'machine_args':  ['-mcpu=cortex-a57']},
  49         '0xd08': {'machine_args':  ['-mcpu=cortex-a72']},
  50         '0xd09': {'machine_args':  ['-mcpu=cortex-a73']},
  51         '0xd0a': {'machine_args':  ['-mcpu=cortex-a75']},
  52         '0xd0b': {'machine_args':  ['-mcpu=cortex-a76']},
  53         '0xd0c': {
  54                 'machine_args':  ['-march=armv8.2-a+crypto',
  55                                   '-mcpu=neoverse-n1'],
  56                 'flags': [
  57                         ['RTE_MACHINE', '"neoverse-n1"'],
  58                         ['RTE_ARM_FEATURE_ATOMICS', true],
  59                         ['RTE_MAX_MEM_MB', 1048576],
  60                         ['RTE_MAX_LCORE', 160],
  61                         ['RTE_MAX_NUMA_NODES', 2]
  62                 ]
  63         },
  64         '0xd49': {
  65                 'machine_args':  ['-march=armv8.5-a+crypto+sve2'],
  66                 'flags': [
  67                         ['RTE_MACHINE', '"neoverse-n2"'],
  68                         ['RTE_ARM_FEATURE_ATOMICS', true],
  69                         ['RTE_MAX_LCORE', 64],
  70                         ['RTE_MAX_NUMA_NODES', 1]
  71                 ]
  72         }
  73 }
  74 implementer_arm = {
  75         'description': 'Arm',
  76         'flags': [
  77                 ['RTE_MACHINE', '"armv8a"'],
  78                 ['RTE_USE_C11_MEM_MODEL', true],
  79                 ['RTE_CACHE_LINE_SIZE', 64],
  80                 ['RTE_MAX_LCORE', 64],
  81                 ['RTE_MAX_NUMA_NODES', 4]
  82         ],
  83         'part_number_config': part_number_config_arm
  84 }
  85
  86 flags_part_number_thunderx = [
  87         ['RTE_MACHINE', '"thunderx"'],
  88         ['RTE_USE_C11_MEM_MODEL', false]
  89 ]
  90 implementer_cavium = {
  91         'description': 'Cavium',
  92         'flags': [
  93                 ['RTE_MAX_VFIO_GROUPS', 128],
  94                 ['RTE_MAX_LCORE', 96],
  95                 ['RTE_MAX_NUMA_NODES', 2]
  96         ],
  97         'part_number_config': {
  98                 '0xa1': {
  99                         'machine_args': ['-mcpu=thunderxt88'],
 100                         'flags': flags_part_number_thunderx
 101                 },
 102                 '0xa2': {
 103                         'machine_args': ['-mcpu=thunderxt81'],
 104                         'flags': flags_part_number_thunderx
 105                 },
 106                 '0xa3': {
 107                         'machine_args': ['-mcpu=thunderxt83'],
 108                         'flags': flags_part_number_thunderx
 109                 },
 110                 '0xaf': {
 111                         'machine_args': ['-march=armv8.1-a+crc+crypto',
 112                                          '-mcpu=thunderx2t99'],
 113                         'flags': [
 114                                 ['RTE_MACHINE', '"thunderx2"'],
 115                                 ['RTE_ARM_FEATURE_ATOMICS', true],
 116                                 ['RTE_USE_C11_MEM_MODEL', true],
 117                                 ['RTE_CACHE_LINE_SIZE', 64],
 118                                 ['RTE_MAX_LCORE', 256]
 119                         ]
 120                 },
 121                 '0xb2': {
 122                         'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
 123                                          '-mcpu=octeontx2'],
 124                         'flags': [
 125                                 ['RTE_MACHINE', '"octeontx2"'],
 126                                 ['RTE_ARM_FEATURE_ATOMICS', true],
 127                                 ['RTE_USE_C11_MEM_MODEL', true],
 128                                 ['RTE_MAX_LCORE', 36],
 129                                 ['RTE_MAX_NUMA_NODES', 1]
 130                         ]
 131                 }
 132         }
 133 }
 134
 135 implementer_ampere = {
 136         'description': 'Ampere Computing',
 137         'flags': [
 138                 ['RTE_MACHINE', '"emag"'],
 139                 ['RTE_CACHE_LINE_SIZE', 64],
 140                 ['RTE_MAX_LCORE', 32],
 141                 ['RTE_MAX_NUMA_NODES', 1]
 142         ],
 143         'part_number_config': {
 144                 '0x0': {'machine_args':  ['-march=armv8-a+crc+crypto',
 145                                           '-mtune=emag']}
 146         }
 147 }
 148
 149 implementer_qualcomm = {
 150         'description': 'Qualcomm',
 151         'flags': [
 152                 ['RTE_MACHINE', '"armv8a"'],
 153                 ['RTE_USE_C11_MEM_MODEL', true],
 154                 ['RTE_CACHE_LINE_SIZE', 64],
 155                 ['RTE_MAX_LCORE', 64],
 156                 ['RTE_MAX_NUMA_NODES', 1]
 157         ],
 158         'part_number_config': {
 159                 '0xc00': {'machine_args':  ['-march=armv8-a+crc']}
 160         }
 161 }
 162
 163 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
 164 implementers = {
 165         'generic': implementer_generic,
 166         '0x41': implementer_arm,
 167         '0x43': implementer_cavium,
 168         '0x50': implementer_ampere,
 169         '0x51': implementer_qualcomm
 170 }
 171
 172 # SoC specific aarch64 flags have the highest priority
 173 #     (will overwrite all other flags)
 174 soc_generic = {
 175         'description': 'Generic un-optimized build for all aarch64 machines',
 176         'implementer': 'generic',
 177         'part_number': 'generic'
 178 }
 179
 180 soc_armada = {
 181         'description': 'Marvell ARMADA',
 182         'implementer': '0x41',
 183         'part_number': '0xd08',
 184         'flags': [
 185                 ['RTE_MAX_LCORE', 16],
 186                 ['RTE_MAX_NUMA_NODES', 1]
 187         ],
 188         'numa': false
 189 }
 190
 191 soc_bluefield = {
 192         'description': 'NVIDIA BlueField',
 193         'implementer': '0x41',
 194         'part_number': '0xd08',
 195         'flags': [
 196                 ['RTE_MAX_LCORE', 16],
 197                 ['RTE_MAX_NUMA_NODES', 1]
 198         ],
 199         'numa': false
 200 }
 201
 202 soc_dpaa = {
 203         'description': 'NXP DPAA',
 204         'implementer': '0x41',
 205         'part_number': '0xd08',
 206         'flags': [
 207                 ['RTE_MACHINE', '"dpaa"'],
 208                 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
 209                 ['RTE_MAX_LCORE', 16],
 210                 ['RTE_MAX_NUMA_NODES', 1]
 211         ],
 212         'numa': false
 213 }
 214
 215 soc_emag = {
 216         'description': 'Ampere eMAG',
 217         'implementer': '0x50',
 218         'part_number': '0x0'
 219 }
 220
 221 soc_graviton2 = {
 222         'description': 'AWS Graviton2',
 223         'implementer': '0x41',
 224         'part_number': '0xd0c',
 225         'numa': false
 226 }
 227
 228 soc_n1sdp = {
 229         'description': 'Arm Neoverse N1SDP',
 230         'implementer': '0x41',
 231         'part_number': '0xd0c',
 232         'flags': [
 233                 ['RTE_MAX_LCORE', 4]
 234         ],
 235         'numa': false
 236 }
 237
 238 soc_n2 = {
 239         'description': 'Arm Neoverse N2',
 240         'implementer': '0x41',
 241         'part_number': '0xd49',
 242         'numa': false
 243 }
 244
 245 soc_octeontx2 = {
 246         'description': 'Marvell OCTEON TX2',
 247         'implementer': '0x43',
 248         'part_number': '0xb2',
 249         'numa': false
 250 }
 251
 252 soc_stingray = {
 253         'description': 'Broadcom Stingray',
 254         'implementer': '0x41',
 255         'flags': [
 256                 ['RTE_MAX_LCORE', 16],
 257                 ['RTE_MAX_NUMA_NODES', 1]
 258         ],
 259         'part_number': '0xd08',
 260         'numa': false
 261 }
 262
 263 soc_thunderx2 = {
 264         'description': 'Marvell ThunderX2 T99',
 265         'implementer': '0x43',
 266         'part_number': '0xaf'
 267 }
 268
 269 soc_thunderxt88 = {
 270         'description': 'Marvell ThunderX T88',
 271         'implementer': '0x43',
 272         'part_number': '0xa1'
 273 }
 274
 275 socs = {
 276         'generic': soc_generic,
 277         'armada': soc_armada,
 278         'bluefield': soc_bluefield,
 279         'dpaa': soc_dpaa,
 280         'emag': soc_emag,
 281         'graviton2': soc_graviton2,
 282         'n1sdp': soc_n1sdp,
 283         'n2': soc_n2,
 284         'octeontx2': soc_octeontx2,
 285         'stingray': soc_stingray,
 286         'thunderx2': soc_thunderx2,
 287         'thunderxt88': soc_thunderxt88
 288 }
 289
 290 dpdk_conf.set('RTE_ARCH_ARM', 1)
 291 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
 292
 293 if dpdk_conf.get('RTE_ARCH_32')
 294         # armv7 build
 295         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
 296         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
 297         # the minimum architecture supported, armv7-a, needs the following,
 298         machine_args += '-mfpu=neon'
 299 else
 300         # aarch64 build
 301         soc = get_option('platform')
 302         soc_config = {}
 303         if not meson.is_cross_build()
 304                 if machine == 'generic'
 305                         # generic build
 306                         if soc != ''
 307                                 error('Building for a particular platform is ' +
 308                                       'unsupported with generic build.')
 309                         endif
 310                         implementer_id = 'generic'
 311                         part_number = 'generic'
 312                 elif soc != ''
 313                         soc_config = socs.get(soc, {'not_supported': true})
 314                 else
 315                         # native build
 316                         # The script returns ['Implementer', 'Variant', 'Architecture',
 317                         # 'Primary Part number', 'Revision']
 318                         detect_vendor = find_program(join_paths(
 319                                         meson.current_source_dir(), 'armv8_machine.py'))
 320                         cmd = run_command(detect_vendor.path())
 321                         if cmd.returncode() == 0
 322                                 cmd_output = cmd.stdout().to_lower().strip().split(' ')
 323                                 implementer_id = cmd_output[0]
 324                                 part_number = cmd_output[3]
 325                         else
 326                                 error('Error when getting Arm Implementer ID and part number.')
 327                         endif
 328                 endif
 329         else
 330                 # cross build
 331                 soc = meson.get_cross_property('platform', '')
 332                 if soc == ''
 333                         error('Arm SoC must be specified in the cross file.')
 334                 endif
 335                 soc_config = socs.get(soc, {'not_supported': true})
 336         endif
 337
 338         soc_flags = []
 339         if soc_config.has_key('not_supported')
 340                 error('SoC @0@ not supported.'.format(soc))
 341         elif soc_config != {}
 342                 implementer_id = soc_config['implementer']
 343                 implementer_config = implementers[implementer_id]
 344                 part_number = soc_config['part_number']
 345                 soc_flags = soc_config.get('flags', [])
 346                 if not soc_config.get('numa', true)
 347                         has_libnuma = 0
 348                 endif
 349
 350                 disable_drivers += ',' + soc_config.get('disable_drivers', '')
 351                 enable_drivers += ',' + soc_config.get('enable_drivers', '')
 352         endif
 353
 354         if implementers.has_key(implementer_id)
 355                 implementer_config = implementers[implementer_id]
 356         else
 357                 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
 358                       'Please add support for it or use the generic ' +
 359                       '(-Dmachine=generic) build.')
 360         endif
 361
 362         message('Arm implementer: ' + implementer_config['description'])
 363         message('Arm part number: ' + part_number)
 364
 365         part_number_config = implementer_config['part_number_config']
 366         if part_number_config.has_key(part_number)
 367                 # use the specified part_number machine args if found
 368                 part_number_config = part_number_config[part_number]
 369         else
 370                 # unknown part number
 371                 error('Unsupported part number @0@ of implementer @1@. '
 372                       .format(part_number, implementer_id) +
 373                       'Please add support for it or use the generic ' +
 374                       '(-Dmachine=generic) build.')
 375         endif
 376
 377         # add/overwrite flags in the proper order
 378         dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
 379
 380         # apply supported machine args
 381         machine_args = [] # Clear previous machine args
 382         foreach flag: part_number_config['machine_args']
 383                 if cc.has_argument(flag)
 384                         machine_args += flag
 385                 endif
 386         endforeach
 387
 388         # apply flags
 389         foreach flag: dpdk_flags
 390                 if flag.length() > 0
 391                         dpdk_conf.set(flag[0], flag[1])
 392                 endif
 393         endforeach
 394 endif
 395 message('Using machine args: @0@'.format(machine_args))
 396
 397 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 398     cc.get_define('__aarch64__', args: machine_args) != '')
 399         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 400 endif
 401
 402 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
 403         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
 404 endif
 405
 406 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
 407         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
 408         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 409 endif