1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific armv8 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific armv8 flags have higher priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
42 'march_features': ['crc'],
43 'compiler_options': ['-moutline-atomics']
46 'machine_args': ['-march=armv8-a', '-mfpu=neon'],
48 ['RTE_ARCH_ARM_NEON_MEMCPY', false],
49 ['RTE_ARCH_STRICT_ALIGN', true],
50 ['RTE_ARCH_ARMv8_AARCH32', true],
51 ['RTE_CACHE_LINE_SIZE', 64]
57 part_number_config_arm = {
58 '0xd03': {'compiler_options': ['-mcpu=cortex-a53']},
59 '0xd04': {'compiler_options': ['-mcpu=cortex-a35']},
60 '0xd07': {'compiler_options': ['-mcpu=cortex-a57']},
61 '0xd08': {'compiler_options': ['-mcpu=cortex-a72']},
62 '0xd09': {'compiler_options': ['-mcpu=cortex-a73']},
63 '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']},
64 '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']},
67 'march_features': ['crypto'],
68 'compiler_options': ['-mcpu=neoverse-n1'],
70 ['RTE_MACHINE', '"neoverse-n1"'],
71 ['RTE_ARM_FEATURE_ATOMICS', true],
72 ['RTE_MAX_MEM_MB', 1048576],
73 ['RTE_MAX_LCORE', 160],
74 ['RTE_MAX_NUMA_NODES', 2]
79 'march_features': ['crypto', 'sve2'],
81 ['RTE_MACHINE', '"neoverse-n2"'],
82 ['RTE_ARM_FEATURE_ATOMICS', true],
83 ['RTE_MAX_LCORE', 64],
84 ['RTE_MAX_NUMA_NODES', 1]
91 ['RTE_MACHINE', '"armv8a"'],
92 ['RTE_USE_C11_MEM_MODEL', true],
93 ['RTE_CACHE_LINE_SIZE', 64],
94 ['RTE_MAX_LCORE', 64],
95 ['RTE_MAX_NUMA_NODES', 4]
97 'part_number_config': part_number_config_arm
100 flags_part_number_thunderx = [
101 ['RTE_MACHINE', '"thunderx"'],
102 ['RTE_USE_C11_MEM_MODEL', false]
104 implementer_cavium = {
105 'description': 'Cavium',
107 ['RTE_MAX_VFIO_GROUPS', 128],
108 ['RTE_MAX_LCORE', 96],
109 ['RTE_MAX_NUMA_NODES', 2]
111 'part_number_config': {
113 'compiler_options': ['-mcpu=thunderxt88'],
114 'flags': flags_part_number_thunderx
117 'compiler_options': ['-mcpu=thunderxt81'],
118 'flags': flags_part_number_thunderx
121 'compiler_options': ['-mcpu=thunderxt83'],
122 'flags': flags_part_number_thunderx
125 'march': 'armv8.1-a',
126 'march_features': ['crc', 'crypto'],
127 'compiler_options': ['-mcpu=thunderx2t99'],
129 ['RTE_MACHINE', '"thunderx2"'],
130 ['RTE_ARM_FEATURE_ATOMICS', true],
131 ['RTE_USE_C11_MEM_MODEL', true],
132 ['RTE_CACHE_LINE_SIZE', 64],
133 ['RTE_MAX_LCORE', 256]
137 'march': 'armv8.2-a',
138 'march_features': ['crc', 'crypto', 'lse'],
139 'compiler_options': ['-mcpu=octeontx2'],
141 ['RTE_MACHINE', '"octeontx2"'],
142 ['RTE_ARM_FEATURE_ATOMICS', true],
143 ['RTE_USE_C11_MEM_MODEL', true],
144 ['RTE_MAX_LCORE', 36],
145 ['RTE_MAX_NUMA_NODES', 1]
151 implementer_ampere = {
152 'description': 'Ampere Computing',
154 ['RTE_MACHINE', '"emag"'],
155 ['RTE_CACHE_LINE_SIZE', 64],
156 ['RTE_MAX_LCORE', 32],
157 ['RTE_MAX_NUMA_NODES', 1]
159 'part_number_config': {
162 'march_features': ['crc', 'crypto'],
163 'compiler_options': ['-mtune=emag']
168 implementer_hisilicon = {
169 'description': 'HiSilicon',
171 ['RTE_USE_C11_MEM_MODEL', true],
172 ['RTE_CACHE_LINE_SIZE', 128]
174 'part_number_config': {
176 'march': 'armv8.2-a',
177 'march_features': ['crypto'],
178 'compiler_options': ['-mtune=tsv110'],
180 ['RTE_MACHINE', '"Kunpeng 920"'],
181 ['RTE_ARM_FEATURE_ATOMICS', true],
182 ['RTE_MAX_LCORE', 256],
183 ['RTE_MAX_NUMA_NODES', 8]
187 'march': 'armv8.2-a',
188 'march_features': ['crypto', 'sve'],
190 ['RTE_MACHINE', '"Kunpeng 930"'],
191 ['RTE_ARM_FEATURE_ATOMICS', true],
192 ['RTE_MAX_LCORE', 1280],
193 ['RTE_MAX_NUMA_NODES', 16]
199 implementer_qualcomm = {
200 'description': 'Qualcomm',
202 ['RTE_MACHINE', '"armv8a"'],
203 ['RTE_USE_C11_MEM_MODEL', true],
204 ['RTE_CACHE_LINE_SIZE', 64],
205 ['RTE_MAX_LCORE', 64],
206 ['RTE_MAX_NUMA_NODES', 1]
208 'part_number_config': {
211 'march_features': ['crc']
215 'march_features': ['crc']
220 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
222 'generic': implementer_generic,
223 '0x41': implementer_arm,
224 '0x43': implementer_cavium,
225 '0x48': implementer_hisilicon,
226 '0x50': implementer_ampere,
227 '0x51': implementer_qualcomm
230 # SoC specific armv8 flags have the highest priority
231 # (will overwrite all other flags)
233 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
234 'implementer': 'generic',
235 'part_number': 'generic'
238 soc_generic_aarch32 = {
239 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
240 'implementer': 'generic',
241 'part_number': 'generic_aarch32'
245 'description': 'Marvell ARMADA',
246 'implementer': '0x41',
247 'part_number': '0xd08',
249 ['RTE_MAX_LCORE', 16],
250 ['RTE_MAX_NUMA_NODES', 1]
256 'description': 'NVIDIA BlueField',
257 'implementer': '0x41',
258 'part_number': '0xd08',
260 ['RTE_MAX_LCORE', 16],
261 ['RTE_MAX_NUMA_NODES', 1]
267 'description': 'Qualcomm Centriq 2400',
268 'implementer': '0x51',
269 'part_number': '0xc00',
274 'description' : 'Marvell OCTEON 10',
275 'implementer' : '0x41',
277 ['RTE_MAX_LCORE', 24],
278 ['RTE_MAX_NUMA_NODES', 1]
280 'part_number': '0xd49',
285 'description': 'NXP DPAA',
286 'implementer': '0x41',
287 'part_number': '0xd08',
289 ['RTE_MACHINE', '"dpaa"'],
290 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
291 ['RTE_MAX_LCORE', 16],
292 ['RTE_MAX_NUMA_NODES', 1]
298 'description': 'Ampere eMAG',
299 'implementer': '0x50',
304 'description': 'AWS Graviton2',
305 'implementer': '0x41',
306 'part_number': '0xd0c',
311 'description': 'HiSilicon Kunpeng 920',
312 'implementer': '0x48',
313 'part_number': '0xd01',
318 'description': 'HiSilicon Kunpeng 930',
319 'implementer': '0x48',
320 'part_number': '0xd02',
325 'description': 'Arm Neoverse N1SDP',
326 'implementer': '0x41',
327 'part_number': '0xd0c',
335 'description': 'Arm Neoverse N2',
336 'implementer': '0x41',
337 'part_number': '0xd49',
342 'description': 'Marvell OCTEON TX2',
343 'implementer': '0x43',
344 'part_number': '0xb2',
349 'description': 'Broadcom Stingray',
350 'implementer': '0x41',
352 ['RTE_MAX_LCORE', 16],
353 ['RTE_MAX_NUMA_NODES', 1]
355 'part_number': '0xd08',
360 'description': 'Marvell ThunderX2 T99',
361 'implementer': '0x43',
362 'part_number': '0xaf'
366 'description': 'Marvell ThunderX T88',
367 'implementer': '0x43',
368 'part_number': '0xa1'
373 generic: Generic un-optimized build for armv8 aarch64 execution mode.
374 generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.
375 armada: Marvell ARMADA
376 bluefield: NVIDIA BlueField
377 centriq2400: Qualcomm Centriq 2400
378 cn10k: Marvell OCTEON 10
381 graviton2: AWS Graviton2
382 kunpeng920: HiSilicon Kunpeng 920
383 kunpeng930: HiSilicon Kunpeng 930
384 n1sdp: Arm Neoverse N1SDP
386 octeontx2: Marvell OCTEON TX2
387 stingray: Broadcom Stingray
388 thunderx2: Marvell ThunderX2 T99
389 thunderxt88: Marvell ThunderX T88
392 # The string above is included in the documentation, keep it in sync with the
395 'generic': soc_generic,
396 'generic_aarch32': soc_generic_aarch32,
397 'armada': soc_armada,
398 'bluefield': soc_bluefield,
399 'centriq2400': soc_centriq2400,
403 'graviton2': soc_graviton2,
404 'kunpeng920': soc_kunpeng920,
405 'kunpeng930': soc_kunpeng930,
408 'octeontx2': soc_octeontx2,
409 'stingray': soc_stingray,
410 'thunderx2': soc_thunderx2,
411 'thunderxt88': soc_thunderxt88
414 dpdk_conf.set('RTE_ARCH_ARM', 1)
415 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
419 if dpdk_conf.get('RTE_ARCH_32')
421 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
422 if meson.is_cross_build()
424 soc = meson.get_cross_property('platform', '')
426 error('Arm SoC must be specified in the cross file.')
428 soc_config = socs.get(soc, {'not_supported': true})
432 dpdk_conf.set('RTE_ARCH_ARMv7', true)
433 # the minimum architecture supported, armv7-a, needs the following,
434 machine_args += '-mfpu=neon'
440 if not meson.is_cross_build()
441 # for backwards compatibility:
442 # machine=native is the same behavior as soc=native
443 # machine=generic/default is the same as soc=generic
444 # cpu_instruction_set holds the proper value - native, generic or cpu
445 # the old behavior only distinguished between generic and native build
447 if cpu_instruction_set == 'generic'
457 # The script returns ['Implementer', 'Variant', 'Architecture',
458 # 'Primary Part number', 'Revision']
459 detect_vendor = find_program(join_paths(meson.current_source_dir(),
461 cmd = run_command(detect_vendor.path())
462 if cmd.returncode() == 0
463 cmd_output = cmd.stdout().to_lower().strip().split(' ')
464 implementer_id = cmd_output[0]
465 part_number = cmd_output[3]
467 error('Error when getting Arm Implementer ID and part number.')
471 soc_config = socs.get(soc, {'not_supported': true})
475 soc = meson.get_cross_property('platform', '')
477 error('Arm SoC must be specified in the cross file.')
479 soc_config = socs.get(soc, {'not_supported': true})
484 if soc_config.has_key('not_supported')
485 error('SoC @0@ not supported.'.format(soc))
486 elif soc_config != {}
487 implementer_id = soc_config['implementer']
488 implementer_config = implementers[implementer_id]
489 part_number = soc_config['part_number']
490 soc_flags = soc_config.get('flags', [])
491 if not soc_config.get('numa', true)
495 disable_drivers += ',' + soc_config.get('disable_drivers', '')
496 enable_drivers += ',' + soc_config.get('enable_drivers', '')
499 if implementers.has_key(implementer_id)
500 implementer_config = implementers[implementer_id]
502 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
503 'Please add support for it or use the generic ' +
504 '(-Dplatform=generic) build.')
507 message('Arm implementer: ' + implementer_config['description'])
508 message('Arm part number: ' + part_number)
510 part_number_config = implementer_config['part_number_config']
511 if part_number_config.has_key(part_number)
512 # use the specified part_number machine args if found
513 part_number_config = part_number_config[part_number]
515 # unknown part number
516 error('Unsupported part number @0@ of implementer @1@. '
517 .format(part_number, implementer_id) +
518 'Please add support for it or use the generic ' +
519 '(-Dplatform=generic) build.')
522 # add/overwrite flags in the proper order
523 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
525 machine_args = [] # Clear previous machine args
527 # probe supported archs and their features
529 if part_number_config.has_key('march')
530 supported_marchs = ['armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a',
531 'armv8.2-a', 'armv8.1-a', 'armv8-a']
532 check_compiler_support = false
533 foreach supported_march: supported_marchs
534 if supported_march == part_number_config['march']
535 # start checking from this version downwards
536 check_compiler_support = true
538 if (check_compiler_support and
539 cc.has_argument('-march=' + supported_march))
540 candidate_march = supported_march
541 # highest supported march version found
545 if candidate_march == ''
546 error('No suitable armv8 march version found.')
548 if candidate_march != part_number_config['march']
549 warning('Configuration march version is ' +
550 '@0@, but the compiler supports only @1@.'
551 .format(part_number_config['march'], candidate_march))
553 candidate_march = '-march=' + candidate_march
556 if part_number_config.has_key('march_features')
557 march_features += part_number_config['march_features']
559 if soc_config.has_key('extra_march_features')
560 march_features += soc_config['extra_march_features']
562 foreach feature: march_features
563 if cc.has_argument('+'.join([candidate_march, feature]))
564 candidate_march = '+'.join([candidate_march, feature])
566 warning('The compiler does not support feature @0@'
570 machine_args += candidate_march
573 # apply supported compiler options
574 if part_number_config.has_key('compiler_options')
575 foreach flag: part_number_config['compiler_options']
576 if cc.has_argument(flag)
579 warning('Configuration compiler option ' +
580 '@0@ isn\'t supported.'.format(flag))
586 foreach flag: dpdk_flags
588 dpdk_conf.set(flag[0], flag[1])
592 message('Using machine args: @0@'.format(machine_args))
594 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
595 cc.get_define('__aarch64__', args: machine_args) != '')
596 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
599 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
600 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
601 if (cc.check_header('arm_sve.h'))
602 dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
606 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
607 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
610 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
611 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
612 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']