3 # Copyright (C) Cavium, Inc 2017. All rights reserved.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions
9 # * Redistributions of source code must retain the above copyright
10 # notice, this list of conditions and the following disclaimer.
11 # * Redistributions in binary form must reproduce the above copyright
12 # notice, this list of conditions and the following disclaimer in
13 # the documentation and/or other materials provided with the
15 # * Neither the name of Cavium, Inc nor the names of its
16 # contributors may be used to endorse or promote products derived
17 # from this software without specific prior written permission.
19 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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29 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "common_linuxapp"
34 CONFIG_RTE_MACHINE="armv8a"
36 CONFIG_RTE_ARCH="arm64"
37 CONFIG_RTE_ARCH_ARM64=y
40 CONFIG_RTE_FORCE_INTRINSICS=y
42 # Maximum available cache line size in arm64 implementations.
43 # Setting to maximum available cache line size in generic config
44 # to address minimum DMA alignment across all arm64 implementations.
45 CONFIG_RTE_CACHE_LINE_SIZE=128
47 CONFIG_RTE_LIBRTE_FM10K_PMD=n
48 CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
49 CONFIG_RTE_LIBRTE_AVP_PMD=n
51 CONFIG_RTE_SCHED_VECTOR=n